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Changhwan Youn30d8bea2011-03-11 10:39:57 +09001/* linux/arch/arm/mach-exynos4/mct.c
2 *
3 * Copyright (c) 2011 Samsung Electronics Co., Ltd.
4 * http://www.samsung.com
5 *
6 * EXYNOS4 MCT(Multi-Core Timer) support
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11*/
12
13#include <linux/sched.h>
14#include <linux/interrupt.h>
15#include <linux/irq.h>
16#include <linux/err.h>
17#include <linux/clk.h>
18#include <linux/clockchips.h>
Stephen Boydee98d272013-02-15 16:40:51 -080019#include <linux/cpu.h>
Changhwan Youn30d8bea2011-03-11 10:39:57 +090020#include <linux/platform_device.h>
21#include <linux/delay.h>
22#include <linux/percpu.h>
Kukjin Kim2edb36c2012-11-15 15:48:56 +090023#include <linux/of.h>
Thomas Abraham36ba5d52013-03-09 16:01:52 +090024#include <linux/of_irq.h>
25#include <linux/of_address.h>
Thomas Abraham9fbf0c82013-03-09 16:10:03 +090026#include <linux/clocksource.h>
Changhwan Youn30d8bea2011-03-11 10:39:57 +090027
Thomas Abrahama1ba7a72013-03-09 16:01:47 +090028#define EXYNOS4_MCTREG(x) (x)
29#define EXYNOS4_MCT_G_CNT_L EXYNOS4_MCTREG(0x100)
30#define EXYNOS4_MCT_G_CNT_U EXYNOS4_MCTREG(0x104)
31#define EXYNOS4_MCT_G_CNT_WSTAT EXYNOS4_MCTREG(0x110)
32#define EXYNOS4_MCT_G_COMP0_L EXYNOS4_MCTREG(0x200)
33#define EXYNOS4_MCT_G_COMP0_U EXYNOS4_MCTREG(0x204)
34#define EXYNOS4_MCT_G_COMP0_ADD_INCR EXYNOS4_MCTREG(0x208)
35#define EXYNOS4_MCT_G_TCON EXYNOS4_MCTREG(0x240)
36#define EXYNOS4_MCT_G_INT_CSTAT EXYNOS4_MCTREG(0x244)
37#define EXYNOS4_MCT_G_INT_ENB EXYNOS4_MCTREG(0x248)
38#define EXYNOS4_MCT_G_WSTAT EXYNOS4_MCTREG(0x24C)
39#define _EXYNOS4_MCT_L_BASE EXYNOS4_MCTREG(0x300)
40#define EXYNOS4_MCT_L_BASE(x) (_EXYNOS4_MCT_L_BASE + (0x100 * x))
41#define EXYNOS4_MCT_L_MASK (0xffffff00)
42
43#define MCT_L_TCNTB_OFFSET (0x00)
44#define MCT_L_ICNTB_OFFSET (0x08)
45#define MCT_L_TCON_OFFSET (0x20)
46#define MCT_L_INT_CSTAT_OFFSET (0x30)
47#define MCT_L_INT_ENB_OFFSET (0x34)
48#define MCT_L_WSTAT_OFFSET (0x40)
49#define MCT_G_TCON_START (1 << 8)
50#define MCT_G_TCON_COMP0_AUTO_INC (1 << 1)
51#define MCT_G_TCON_COMP0_ENABLE (1 << 0)
52#define MCT_L_TCON_INTERVAL_MODE (1 << 2)
53#define MCT_L_TCON_INT_START (1 << 1)
54#define MCT_L_TCON_TIMER_START (1 << 0)
55
Changhwan Youn4d2e4d72012-03-09 15:09:21 -080056#define TICK_BASE_CNT 1
57
Changhwan Youn3a062282011-10-04 17:02:58 +090058enum {
59 MCT_INT_SPI,
60 MCT_INT_PPI
61};
62
Thomas Abrahamc371dc62013-03-09 16:01:50 +090063enum {
64 MCT_G0_IRQ,
65 MCT_G1_IRQ,
66 MCT_G2_IRQ,
67 MCT_G3_IRQ,
68 MCT_L0_IRQ,
69 MCT_L1_IRQ,
70 MCT_L2_IRQ,
71 MCT_L3_IRQ,
Chander Kashyap6c16ded2013-12-02 07:48:23 +090072 MCT_L4_IRQ,
73 MCT_L5_IRQ,
74 MCT_L6_IRQ,
75 MCT_L7_IRQ,
Thomas Abrahamc371dc62013-03-09 16:01:50 +090076 MCT_NR_IRQS,
77};
78
Thomas Abrahama1ba7a72013-03-09 16:01:47 +090079static void __iomem *reg_base;
Changhwan Youn30d8bea2011-03-11 10:39:57 +090080static unsigned long clk_rate;
Changhwan Youn3a062282011-10-04 17:02:58 +090081static unsigned int mct_int_type;
Thomas Abrahamc371dc62013-03-09 16:01:50 +090082static int mct_irqs[MCT_NR_IRQS];
Changhwan Youn30d8bea2011-03-11 10:39:57 +090083
84struct mct_clock_event_device {
Stephen Boydee98d272013-02-15 16:40:51 -080085 struct clock_event_device evt;
Thomas Abrahama1ba7a72013-03-09 16:01:47 +090086 unsigned long base;
Changhwan Younc8987472011-10-04 17:09:26 +090087 char name[10];
Changhwan Youn30d8bea2011-03-11 10:39:57 +090088};
89
Thomas Abrahama1ba7a72013-03-09 16:01:47 +090090static void exynos4_mct_write(unsigned int value, unsigned long offset)
Changhwan Youn30d8bea2011-03-11 10:39:57 +090091{
Thomas Abrahama1ba7a72013-03-09 16:01:47 +090092 unsigned long stat_addr;
Changhwan Youn30d8bea2011-03-11 10:39:57 +090093 u32 mask;
94 u32 i;
95
Thomas Abrahama1ba7a72013-03-09 16:01:47 +090096 __raw_writel(value, reg_base + offset);
Changhwan Youn30d8bea2011-03-11 10:39:57 +090097
Thomas Abrahama1ba7a72013-03-09 16:01:47 +090098 if (likely(offset >= EXYNOS4_MCT_L_BASE(0))) {
99 stat_addr = (offset & ~EXYNOS4_MCT_L_MASK) + MCT_L_WSTAT_OFFSET;
100 switch (offset & EXYNOS4_MCT_L_MASK) {
101 case MCT_L_TCON_OFFSET:
Changhwan Younc8987472011-10-04 17:09:26 +0900102 mask = 1 << 3; /* L_TCON write status */
103 break;
Thomas Abrahama1ba7a72013-03-09 16:01:47 +0900104 case MCT_L_ICNTB_OFFSET:
Changhwan Younc8987472011-10-04 17:09:26 +0900105 mask = 1 << 1; /* L_ICNTB write status */
106 break;
Thomas Abrahama1ba7a72013-03-09 16:01:47 +0900107 case MCT_L_TCNTB_OFFSET:
Changhwan Younc8987472011-10-04 17:09:26 +0900108 mask = 1 << 0; /* L_TCNTB write status */
109 break;
110 default:
111 return;
112 }
113 } else {
Thomas Abrahama1ba7a72013-03-09 16:01:47 +0900114 switch (offset) {
115 case EXYNOS4_MCT_G_TCON:
Changhwan Younc8987472011-10-04 17:09:26 +0900116 stat_addr = EXYNOS4_MCT_G_WSTAT;
117 mask = 1 << 16; /* G_TCON write status */
118 break;
Thomas Abrahama1ba7a72013-03-09 16:01:47 +0900119 case EXYNOS4_MCT_G_COMP0_L:
Changhwan Younc8987472011-10-04 17:09:26 +0900120 stat_addr = EXYNOS4_MCT_G_WSTAT;
121 mask = 1 << 0; /* G_COMP0_L write status */
122 break;
Thomas Abrahama1ba7a72013-03-09 16:01:47 +0900123 case EXYNOS4_MCT_G_COMP0_U:
Changhwan Younc8987472011-10-04 17:09:26 +0900124 stat_addr = EXYNOS4_MCT_G_WSTAT;
125 mask = 1 << 1; /* G_COMP0_U write status */
126 break;
Thomas Abrahama1ba7a72013-03-09 16:01:47 +0900127 case EXYNOS4_MCT_G_COMP0_ADD_INCR:
Changhwan Younc8987472011-10-04 17:09:26 +0900128 stat_addr = EXYNOS4_MCT_G_WSTAT;
129 mask = 1 << 2; /* G_COMP0_ADD_INCR w status */
130 break;
Thomas Abrahama1ba7a72013-03-09 16:01:47 +0900131 case EXYNOS4_MCT_G_CNT_L:
Changhwan Younc8987472011-10-04 17:09:26 +0900132 stat_addr = EXYNOS4_MCT_G_CNT_WSTAT;
133 mask = 1 << 0; /* G_CNT_L write status */
134 break;
Thomas Abrahama1ba7a72013-03-09 16:01:47 +0900135 case EXYNOS4_MCT_G_CNT_U:
Changhwan Younc8987472011-10-04 17:09:26 +0900136 stat_addr = EXYNOS4_MCT_G_CNT_WSTAT;
137 mask = 1 << 1; /* G_CNT_U write status */
138 break;
139 default:
140 return;
141 }
Changhwan Youn30d8bea2011-03-11 10:39:57 +0900142 }
143
144 /* Wait maximum 1 ms until written values are applied */
145 for (i = 0; i < loops_per_jiffy / 1000 * HZ; i++)
Thomas Abrahama1ba7a72013-03-09 16:01:47 +0900146 if (__raw_readl(reg_base + stat_addr) & mask) {
147 __raw_writel(mask, reg_base + stat_addr);
Changhwan Youn30d8bea2011-03-11 10:39:57 +0900148 return;
149 }
150
Thomas Abrahama1ba7a72013-03-09 16:01:47 +0900151 panic("MCT hangs after writing %d (offset:0x%lx)\n", value, offset);
Changhwan Youn30d8bea2011-03-11 10:39:57 +0900152}
153
154/* Clocksource handling */
155static void exynos4_mct_frc_start(u32 hi, u32 lo)
156{
157 u32 reg;
158
159 exynos4_mct_write(lo, EXYNOS4_MCT_G_CNT_L);
160 exynos4_mct_write(hi, EXYNOS4_MCT_G_CNT_U);
161
Thomas Abrahama1ba7a72013-03-09 16:01:47 +0900162 reg = __raw_readl(reg_base + EXYNOS4_MCT_G_TCON);
Changhwan Youn30d8bea2011-03-11 10:39:57 +0900163 reg |= MCT_G_TCON_START;
164 exynos4_mct_write(reg, EXYNOS4_MCT_G_TCON);
165}
166
167static cycle_t exynos4_frc_read(struct clocksource *cs)
168{
169 unsigned int lo, hi;
Thomas Abrahama1ba7a72013-03-09 16:01:47 +0900170 u32 hi2 = __raw_readl(reg_base + EXYNOS4_MCT_G_CNT_U);
Changhwan Youn30d8bea2011-03-11 10:39:57 +0900171
172 do {
173 hi = hi2;
Thomas Abrahama1ba7a72013-03-09 16:01:47 +0900174 lo = __raw_readl(reg_base + EXYNOS4_MCT_G_CNT_L);
175 hi2 = __raw_readl(reg_base + EXYNOS4_MCT_G_CNT_U);
Changhwan Youn30d8bea2011-03-11 10:39:57 +0900176 } while (hi != hi2);
177
178 return ((cycle_t)hi << 32) | lo;
179}
180
Changhwan Younaa421c12011-09-02 14:10:52 +0900181static void exynos4_frc_resume(struct clocksource *cs)
182{
183 exynos4_mct_frc_start(0, 0);
184}
185
Changhwan Youn30d8bea2011-03-11 10:39:57 +0900186struct clocksource mct_frc = {
187 .name = "mct-frc",
188 .rating = 400,
189 .read = exynos4_frc_read,
190 .mask = CLOCKSOURCE_MASK(64),
191 .flags = CLOCK_SOURCE_IS_CONTINUOUS,
Changhwan Younaa421c12011-09-02 14:10:52 +0900192 .resume = exynos4_frc_resume,
Changhwan Youn30d8bea2011-03-11 10:39:57 +0900193};
194
195static void __init exynos4_clocksource_init(void)
196{
197 exynos4_mct_frc_start(0, 0);
198
199 if (clocksource_register_hz(&mct_frc, clk_rate))
200 panic("%s: can't register clocksource\n", mct_frc.name);
201}
202
203static void exynos4_mct_comp0_stop(void)
204{
205 unsigned int tcon;
206
Thomas Abrahama1ba7a72013-03-09 16:01:47 +0900207 tcon = __raw_readl(reg_base + EXYNOS4_MCT_G_TCON);
Changhwan Youn30d8bea2011-03-11 10:39:57 +0900208 tcon &= ~(MCT_G_TCON_COMP0_ENABLE | MCT_G_TCON_COMP0_AUTO_INC);
209
210 exynos4_mct_write(tcon, EXYNOS4_MCT_G_TCON);
211 exynos4_mct_write(0, EXYNOS4_MCT_G_INT_ENB);
212}
213
214static void exynos4_mct_comp0_start(enum clock_event_mode mode,
215 unsigned long cycles)
216{
217 unsigned int tcon;
218 cycle_t comp_cycle;
219
Thomas Abrahama1ba7a72013-03-09 16:01:47 +0900220 tcon = __raw_readl(reg_base + EXYNOS4_MCT_G_TCON);
Changhwan Youn30d8bea2011-03-11 10:39:57 +0900221
222 if (mode == CLOCK_EVT_MODE_PERIODIC) {
223 tcon |= MCT_G_TCON_COMP0_AUTO_INC;
224 exynos4_mct_write(cycles, EXYNOS4_MCT_G_COMP0_ADD_INCR);
225 }
226
227 comp_cycle = exynos4_frc_read(&mct_frc) + cycles;
228 exynos4_mct_write((u32)comp_cycle, EXYNOS4_MCT_G_COMP0_L);
229 exynos4_mct_write((u32)(comp_cycle >> 32), EXYNOS4_MCT_G_COMP0_U);
230
231 exynos4_mct_write(0x1, EXYNOS4_MCT_G_INT_ENB);
232
233 tcon |= MCT_G_TCON_COMP0_ENABLE;
234 exynos4_mct_write(tcon , EXYNOS4_MCT_G_TCON);
235}
236
237static int exynos4_comp_set_next_event(unsigned long cycles,
238 struct clock_event_device *evt)
239{
240 exynos4_mct_comp0_start(evt->mode, cycles);
241
242 return 0;
243}
244
245static void exynos4_comp_set_mode(enum clock_event_mode mode,
246 struct clock_event_device *evt)
247{
Changhwan Youn4d2e4d72012-03-09 15:09:21 -0800248 unsigned long cycles_per_jiffy;
Changhwan Youn30d8bea2011-03-11 10:39:57 +0900249 exynos4_mct_comp0_stop();
250
251 switch (mode) {
252 case CLOCK_EVT_MODE_PERIODIC:
Changhwan Youn4d2e4d72012-03-09 15:09:21 -0800253 cycles_per_jiffy =
254 (((unsigned long long) NSEC_PER_SEC / HZ * evt->mult) >> evt->shift);
255 exynos4_mct_comp0_start(mode, cycles_per_jiffy);
Changhwan Youn30d8bea2011-03-11 10:39:57 +0900256 break;
257
258 case CLOCK_EVT_MODE_ONESHOT:
259 case CLOCK_EVT_MODE_UNUSED:
260 case CLOCK_EVT_MODE_SHUTDOWN:
261 case CLOCK_EVT_MODE_RESUME:
262 break;
263 }
264}
265
266static struct clock_event_device mct_comp_device = {
267 .name = "mct-comp",
268 .features = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT,
269 .rating = 250,
270 .set_next_event = exynos4_comp_set_next_event,
271 .set_mode = exynos4_comp_set_mode,
272};
273
274static irqreturn_t exynos4_mct_comp_isr(int irq, void *dev_id)
275{
276 struct clock_event_device *evt = dev_id;
277
278 exynos4_mct_write(0x1, EXYNOS4_MCT_G_INT_CSTAT);
279
280 evt->event_handler(evt);
281
282 return IRQ_HANDLED;
283}
284
285static struct irqaction mct_comp_event_irq = {
286 .name = "mct_comp_irq",
287 .flags = IRQF_TIMER | IRQF_IRQPOLL,
288 .handler = exynos4_mct_comp_isr,
289 .dev_id = &mct_comp_device,
290};
291
292static void exynos4_clockevent_init(void)
293{
Changhwan Youn30d8bea2011-03-11 10:39:57 +0900294 mct_comp_device.cpumask = cpumask_of(0);
Shawn Guo838a2ae2013-01-12 11:50:05 +0000295 clockevents_config_and_register(&mct_comp_device, clk_rate,
296 0xf, 0xffffffff);
Thomas Abrahamc371dc62013-03-09 16:01:50 +0900297 setup_irq(mct_irqs[MCT_G0_IRQ], &mct_comp_event_irq);
Changhwan Youn30d8bea2011-03-11 10:39:57 +0900298}
299
Kukjin Kim991a6c72011-12-08 10:04:49 +0900300static DEFINE_PER_CPU(struct mct_clock_event_device, percpu_mct_tick);
301
Changhwan Youn30d8bea2011-03-11 10:39:57 +0900302/* Clock event handling */
303static void exynos4_mct_tick_stop(struct mct_clock_event_device *mevt)
304{
305 unsigned long tmp;
306 unsigned long mask = MCT_L_TCON_INT_START | MCT_L_TCON_TIMER_START;
Thomas Abrahama1ba7a72013-03-09 16:01:47 +0900307 unsigned long offset = mevt->base + MCT_L_TCON_OFFSET;
Changhwan Youn30d8bea2011-03-11 10:39:57 +0900308
Thomas Abrahama1ba7a72013-03-09 16:01:47 +0900309 tmp = __raw_readl(reg_base + offset);
Changhwan Youn30d8bea2011-03-11 10:39:57 +0900310 if (tmp & mask) {
311 tmp &= ~mask;
Thomas Abrahama1ba7a72013-03-09 16:01:47 +0900312 exynos4_mct_write(tmp, offset);
Changhwan Youn30d8bea2011-03-11 10:39:57 +0900313 }
314}
315
316static void exynos4_mct_tick_start(unsigned long cycles,
317 struct mct_clock_event_device *mevt)
318{
319 unsigned long tmp;
320
321 exynos4_mct_tick_stop(mevt);
322
323 tmp = (1 << 31) | cycles; /* MCT_L_UPDATE_ICNTB */
324
325 /* update interrupt count buffer */
326 exynos4_mct_write(tmp, mevt->base + MCT_L_ICNTB_OFFSET);
327
Lucas De Marchi25985ed2011-03-30 22:57:33 -0300328 /* enable MCT tick interrupt */
Changhwan Youn30d8bea2011-03-11 10:39:57 +0900329 exynos4_mct_write(0x1, mevt->base + MCT_L_INT_ENB_OFFSET);
330
Thomas Abrahama1ba7a72013-03-09 16:01:47 +0900331 tmp = __raw_readl(reg_base + mevt->base + MCT_L_TCON_OFFSET);
Changhwan Youn30d8bea2011-03-11 10:39:57 +0900332 tmp |= MCT_L_TCON_INT_START | MCT_L_TCON_TIMER_START |
333 MCT_L_TCON_INTERVAL_MODE;
334 exynos4_mct_write(tmp, mevt->base + MCT_L_TCON_OFFSET);
335}
336
337static int exynos4_tick_set_next_event(unsigned long cycles,
338 struct clock_event_device *evt)
339{
Marc Zyngiere700e412011-11-03 11:13:12 +0900340 struct mct_clock_event_device *mevt = this_cpu_ptr(&percpu_mct_tick);
Changhwan Youn30d8bea2011-03-11 10:39:57 +0900341
342 exynos4_mct_tick_start(cycles, mevt);
343
344 return 0;
345}
346
347static inline void exynos4_tick_set_mode(enum clock_event_mode mode,
348 struct clock_event_device *evt)
349{
Marc Zyngiere700e412011-11-03 11:13:12 +0900350 struct mct_clock_event_device *mevt = this_cpu_ptr(&percpu_mct_tick);
Changhwan Youn4d2e4d72012-03-09 15:09:21 -0800351 unsigned long cycles_per_jiffy;
Changhwan Youn30d8bea2011-03-11 10:39:57 +0900352
353 exynos4_mct_tick_stop(mevt);
354
355 switch (mode) {
356 case CLOCK_EVT_MODE_PERIODIC:
Changhwan Youn4d2e4d72012-03-09 15:09:21 -0800357 cycles_per_jiffy =
358 (((unsigned long long) NSEC_PER_SEC / HZ * evt->mult) >> evt->shift);
359 exynos4_mct_tick_start(cycles_per_jiffy, mevt);
Changhwan Youn30d8bea2011-03-11 10:39:57 +0900360 break;
361
362 case CLOCK_EVT_MODE_ONESHOT:
363 case CLOCK_EVT_MODE_UNUSED:
364 case CLOCK_EVT_MODE_SHUTDOWN:
365 case CLOCK_EVT_MODE_RESUME:
366 break;
367 }
368}
369
Changhwan Younc8987472011-10-04 17:09:26 +0900370static int exynos4_mct_tick_clear(struct mct_clock_event_device *mevt)
Changhwan Youn30d8bea2011-03-11 10:39:57 +0900371{
Stephen Boydee98d272013-02-15 16:40:51 -0800372 struct clock_event_device *evt = &mevt->evt;
Changhwan Youn30d8bea2011-03-11 10:39:57 +0900373
374 /*
375 * This is for supporting oneshot mode.
376 * Mct would generate interrupt periodically
377 * without explicit stopping.
378 */
379 if (evt->mode != CLOCK_EVT_MODE_PERIODIC)
380 exynos4_mct_tick_stop(mevt);
381
382 /* Clear the MCT tick interrupt */
Thomas Abrahama1ba7a72013-03-09 16:01:47 +0900383 if (__raw_readl(reg_base + mevt->base + MCT_L_INT_CSTAT_OFFSET) & 1) {
Changhwan Youn3a062282011-10-04 17:02:58 +0900384 exynos4_mct_write(0x1, mevt->base + MCT_L_INT_CSTAT_OFFSET);
385 return 1;
386 } else {
387 return 0;
388 }
389}
390
391static irqreturn_t exynos4_mct_tick_isr(int irq, void *dev_id)
392{
393 struct mct_clock_event_device *mevt = dev_id;
Stephen Boydee98d272013-02-15 16:40:51 -0800394 struct clock_event_device *evt = &mevt->evt;
Changhwan Youn3a062282011-10-04 17:02:58 +0900395
396 exynos4_mct_tick_clear(mevt);
Changhwan Youn30d8bea2011-03-11 10:39:57 +0900397
398 evt->event_handler(evt);
399
400 return IRQ_HANDLED;
401}
402
Paul Gortmaker8c37bb32013-06-19 11:32:08 -0400403static int exynos4_local_timer_setup(struct clock_event_device *evt)
Changhwan Youn30d8bea2011-03-11 10:39:57 +0900404{
Marc Zyngiere700e412011-11-03 11:13:12 +0900405 struct mct_clock_event_device *mevt;
Changhwan Youn30d8bea2011-03-11 10:39:57 +0900406 unsigned int cpu = smp_processor_id();
407
Stephen Boydee98d272013-02-15 16:40:51 -0800408 mevt = container_of(evt, struct mct_clock_event_device, evt);
Changhwan Youn30d8bea2011-03-11 10:39:57 +0900409
Marc Zyngiere700e412011-11-03 11:13:12 +0900410 mevt->base = EXYNOS4_MCT_L_BASE(cpu);
Dan Carpenter09e15172014-03-01 16:57:14 +0300411 snprintf(mevt->name, sizeof(mevt->name), "mct_tick%d", cpu);
Changhwan Youn30d8bea2011-03-11 10:39:57 +0900412
Marc Zyngiere700e412011-11-03 11:13:12 +0900413 evt->name = mevt->name;
Changhwan Youn30d8bea2011-03-11 10:39:57 +0900414 evt->cpumask = cpumask_of(cpu);
415 evt->set_next_event = exynos4_tick_set_next_event;
416 evt->set_mode = exynos4_tick_set_mode;
417 evt->features = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT;
418 evt->rating = 450;
Changhwan Youn30d8bea2011-03-11 10:39:57 +0900419
Changhwan Youn4d2e4d72012-03-09 15:09:21 -0800420 exynos4_mct_write(TICK_BASE_CNT, mevt->base + MCT_L_TCNTB_OFFSET);
Changhwan Youn30d8bea2011-03-11 10:39:57 +0900421
Changhwan Youn3a062282011-10-04 17:02:58 +0900422 if (mct_int_type == MCT_INT_SPI) {
Chander Kashyap7114cd72013-06-19 00:29:35 +0900423 evt->irq = mct_irqs[MCT_L0_IRQ + cpu];
424 if (request_irq(evt->irq, exynos4_mct_tick_isr,
425 IRQF_TIMER | IRQF_NOBALANCING,
426 evt->name, mevt)) {
427 pr_err("exynos-mct: cannot register IRQ %d\n",
428 evt->irq);
429 return -EIO;
Changhwan Youn3a062282011-10-04 17:02:58 +0900430 }
Thomas Gleixner30ccf032014-04-16 14:36:45 +0000431 irq_force_affinity(mct_irqs[MCT_L0_IRQ + cpu], cpumask_of(cpu));
Changhwan Youn30d8bea2011-03-11 10:39:57 +0900432 } else {
Thomas Abrahamc371dc62013-03-09 16:01:50 +0900433 enable_percpu_irq(mct_irqs[MCT_L0_IRQ], 0);
Changhwan Youn30d8bea2011-03-11 10:39:57 +0900434 }
Krzysztof Kozlowski8db6e512014-04-16 14:36:45 +0000435 clockevents_config_and_register(evt, clk_rate / (TICK_BASE_CNT + 1),
436 0xf, 0x7fffffff);
Kukjin Kim4d487d72011-08-24 16:07:39 +0900437
438 return 0;
Changhwan Youn30d8bea2011-03-11 10:39:57 +0900439}
440
Marc Zyngiera8cb6042012-01-10 19:44:19 +0000441static void exynos4_local_timer_stop(struct clock_event_device *evt)
Changhwan Youn30d8bea2011-03-11 10:39:57 +0900442{
Marc Zyngier28af6902011-07-22 12:52:37 +0100443 evt->set_mode(CLOCK_EVT_MODE_UNUSED, evt);
Marc Zyngiere700e412011-11-03 11:13:12 +0900444 if (mct_int_type == MCT_INT_SPI)
Chander Kashyap7114cd72013-06-19 00:29:35 +0900445 free_irq(evt->irq, this_cpu_ptr(&percpu_mct_tick));
Marc Zyngiere700e412011-11-03 11:13:12 +0900446 else
Thomas Abrahamc371dc62013-03-09 16:01:50 +0900447 disable_percpu_irq(mct_irqs[MCT_L0_IRQ]);
Changhwan Youn30d8bea2011-03-11 10:39:57 +0900448}
Marc Zyngiera8cb6042012-01-10 19:44:19 +0000449
Olof Johansson47dcd352013-07-23 14:51:34 -0700450static int exynos4_mct_cpu_notify(struct notifier_block *self,
Stephen Boydee98d272013-02-15 16:40:51 -0800451 unsigned long action, void *hcpu)
452{
453 struct mct_clock_event_device *mevt;
454
455 /*
456 * Grab cpu pointer in each case to avoid spurious
457 * preemptible warnings
458 */
459 switch (action & ~CPU_TASKS_FROZEN) {
460 case CPU_STARTING:
461 mevt = this_cpu_ptr(&percpu_mct_tick);
462 exynos4_local_timer_setup(&mevt->evt);
463 break;
464 case CPU_DYING:
465 mevt = this_cpu_ptr(&percpu_mct_tick);
466 exynos4_local_timer_stop(&mevt->evt);
467 break;
468 }
469
470 return NOTIFY_OK;
471}
472
Olof Johansson47dcd352013-07-23 14:51:34 -0700473static struct notifier_block exynos4_mct_cpu_nb = {
Stephen Boydee98d272013-02-15 16:40:51 -0800474 .notifier_call = exynos4_mct_cpu_notify,
Marc Zyngiera8cb6042012-01-10 19:44:19 +0000475};
Changhwan Youn30d8bea2011-03-11 10:39:57 +0900476
Arnd Bergmann19ce4f42013-04-09 22:24:06 +0200477static void __init exynos4_timer_resources(struct device_node *np, void __iomem *base)
Changhwan Youn30d8bea2011-03-11 10:39:57 +0900478{
Stephen Boydee98d272013-02-15 16:40:51 -0800479 int err;
480 struct mct_clock_event_device *mevt = this_cpu_ptr(&percpu_mct_tick);
Thomas Abrahamca9048e2013-03-09 17:10:37 +0900481 struct clk *mct_clk, *tick_clk;
Changhwan Youn30d8bea2011-03-11 10:39:57 +0900482
Thomas Abraham415ac2e2013-03-09 17:10:31 +0900483 tick_clk = np ? of_clk_get_by_name(np, "fin_pll") :
484 clk_get(NULL, "fin_pll");
485 if (IS_ERR(tick_clk))
486 panic("%s: unable to determine tick clock rate\n", __func__);
487 clk_rate = clk_get_rate(tick_clk);
Marc Zyngiere700e412011-11-03 11:13:12 +0900488
Thomas Abrahamca9048e2013-03-09 17:10:37 +0900489 mct_clk = np ? of_clk_get_by_name(np, "mct") : clk_get(NULL, "mct");
490 if (IS_ERR(mct_clk))
491 panic("%s: unable to retrieve mct clock instance\n", __func__);
492 clk_prepare_enable(mct_clk);
Marc Zyngiere700e412011-11-03 11:13:12 +0900493
Arnd Bergmann228e3022013-04-09 22:07:37 +0200494 reg_base = base;
Thomas Abraham36ba5d52013-03-09 16:01:52 +0900495 if (!reg_base)
496 panic("%s: unable to ioremap mct address space\n", __func__);
Thomas Abrahama1ba7a72013-03-09 16:01:47 +0900497
Marc Zyngiere700e412011-11-03 11:13:12 +0900498 if (mct_int_type == MCT_INT_PPI) {
Marc Zyngiere700e412011-11-03 11:13:12 +0900499
Thomas Abrahamc371dc62013-03-09 16:01:50 +0900500 err = request_percpu_irq(mct_irqs[MCT_L0_IRQ],
Marc Zyngiere700e412011-11-03 11:13:12 +0900501 exynos4_mct_tick_isr, "MCT",
502 &percpu_mct_tick);
503 WARN(err, "MCT: can't request IRQ %d (%d)\n",
Thomas Abrahamc371dc62013-03-09 16:01:50 +0900504 mct_irqs[MCT_L0_IRQ], err);
Tomasz Figa5df718d2013-09-25 12:00:59 +0200505 } else {
506 irq_set_affinity(mct_irqs[MCT_L0_IRQ], cpumask_of(0));
Marc Zyngiere700e412011-11-03 11:13:12 +0900507 }
Marc Zyngiera8cb6042012-01-10 19:44:19 +0000508
Stephen Boydee98d272013-02-15 16:40:51 -0800509 err = register_cpu_notifier(&exynos4_mct_cpu_nb);
510 if (err)
511 goto out_irq;
512
513 /* Immediately configure the timer on the boot CPU */
514 exynos4_local_timer_setup(&mevt->evt);
515 return;
516
517out_irq:
518 free_percpu_irq(mct_irqs[MCT_L0_IRQ], &percpu_mct_tick);
Changhwan Youn30d8bea2011-03-11 10:39:57 +0900519}
520
Arnd Bergmann034c0972013-04-10 11:35:29 +0200521void __init mct_init(void __iomem *base, int irq_g0, int irq_l0, int irq_l1)
Changhwan Youn30d8bea2011-03-11 10:39:57 +0900522{
Arnd Bergmann034c0972013-04-10 11:35:29 +0200523 mct_irqs[MCT_G0_IRQ] = irq_g0;
524 mct_irqs[MCT_L0_IRQ] = irq_l0;
525 mct_irqs[MCT_L1_IRQ] = irq_l1;
526 mct_int_type = MCT_INT_SPI;
Kukjin Kim2edb36c2012-11-15 15:48:56 +0900527
Arnd Bergmann034c0972013-04-10 11:35:29 +0200528 exynos4_timer_resources(NULL, base);
Changhwan Youn30d8bea2011-03-11 10:39:57 +0900529 exynos4_clocksource_init();
530 exynos4_clockevent_init();
531}
Arnd Bergmann228e3022013-04-09 22:07:37 +0200532
533static void __init mct_init_dt(struct device_node *np, unsigned int int_type)
534{
535 u32 nr_irqs, i;
536
537 mct_int_type = int_type;
538
539 /* This driver uses only one global timer interrupt */
540 mct_irqs[MCT_G0_IRQ] = irq_of_parse_and_map(np, MCT_G0_IRQ);
541
542 /*
543 * Find out the number of local irqs specified. The local
544 * timer irqs are specified after the four global timer
545 * irqs are specified.
546 */
Arnd Bergmannf4636d02013-04-19 22:00:04 +0200547#ifdef CONFIG_OF
Arnd Bergmann228e3022013-04-09 22:07:37 +0200548 nr_irqs = of_irq_count(np);
Arnd Bergmannf4636d02013-04-19 22:00:04 +0200549#else
550 nr_irqs = 0;
551#endif
Arnd Bergmann228e3022013-04-09 22:07:37 +0200552 for (i = MCT_L0_IRQ; i < nr_irqs; i++)
553 mct_irqs[i] = irq_of_parse_and_map(np, i);
554
Arnd Bergmann19ce4f42013-04-09 22:24:06 +0200555 exynos4_timer_resources(np, of_iomap(np, 0));
Arnd Bergmann228e3022013-04-09 22:07:37 +0200556 exynos4_clocksource_init();
557 exynos4_clockevent_init();
558}
559
560
561static void __init mct_init_spi(struct device_node *np)
562{
563 return mct_init_dt(np, MCT_INT_SPI);
564}
565
566static void __init mct_init_ppi(struct device_node *np)
567{
568 return mct_init_dt(np, MCT_INT_PPI);
569}
570CLOCKSOURCE_OF_DECLARE(exynos4210, "samsung,exynos4210-mct", mct_init_spi);
571CLOCKSOURCE_OF_DECLARE(exynos4412, "samsung,exynos4412-mct", mct_init_ppi);