Dan Williams | 9bc89cd | 2007-01-02 11:10:44 -0700 | [diff] [blame] | 1 | /* |
| 2 | * xor offload engine api |
| 3 | * |
| 4 | * Copyright © 2006, Intel Corporation. |
| 5 | * |
| 6 | * Dan Williams <dan.j.williams@intel.com> |
| 7 | * |
| 8 | * with architecture considerations by: |
| 9 | * Neil Brown <neilb@suse.de> |
| 10 | * Jeff Garzik <jeff@garzik.org> |
| 11 | * |
| 12 | * This program is free software; you can redistribute it and/or modify it |
| 13 | * under the terms and conditions of the GNU General Public License, |
| 14 | * version 2, as published by the Free Software Foundation. |
| 15 | * |
| 16 | * This program is distributed in the hope it will be useful, but WITHOUT |
| 17 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or |
| 18 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for |
| 19 | * more details. |
| 20 | * |
| 21 | * You should have received a copy of the GNU General Public License along with |
| 22 | * this program; if not, write to the Free Software Foundation, Inc., |
| 23 | * 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA. |
| 24 | * |
| 25 | */ |
| 26 | #include <linux/kernel.h> |
| 27 | #include <linux/interrupt.h> |
| 28 | #include <linux/mm.h> |
| 29 | #include <linux/dma-mapping.h> |
| 30 | #include <linux/raid/xor.h> |
| 31 | #include <linux/async_tx.h> |
| 32 | |
Dan Williams | 06164f3 | 2009-03-25 09:13:25 -0700 | [diff] [blame] | 33 | /* do_async_xor - dma map the pages and perform the xor with an engine */ |
| 34 | static __async_inline struct dma_async_tx_descriptor * |
Dan Williams | 1e55db2 | 2008-07-16 19:44:56 -0700 | [diff] [blame] | 35 | do_async_xor(struct dma_chan *chan, struct page *dest, struct page **src_list, |
Dan Williams | 04ce9ab | 2009-06-03 14:22:28 -0700 | [diff] [blame] | 36 | unsigned int offset, int src_cnt, size_t len, dma_addr_t *dma_src, |
Dan Williams | a08abd8 | 2009-06-03 11:43:59 -0700 | [diff] [blame] | 37 | struct async_submit_ctl *submit) |
Dan Williams | 9bc89cd | 2007-01-02 11:10:44 -0700 | [diff] [blame] | 38 | { |
Dan Williams | 1e55db2 | 2008-07-16 19:44:56 -0700 | [diff] [blame] | 39 | struct dma_device *dma = chan->device; |
Dan Williams | 1e55db2 | 2008-07-16 19:44:56 -0700 | [diff] [blame] | 40 | struct dma_async_tx_descriptor *tx = NULL; |
| 41 | int src_off = 0; |
Dan Williams | 9bc89cd | 2007-01-02 11:10:44 -0700 | [diff] [blame] | 42 | int i; |
Dan Williams | a08abd8 | 2009-06-03 11:43:59 -0700 | [diff] [blame] | 43 | dma_async_tx_callback cb_fn_orig = submit->cb_fn; |
| 44 | void *cb_param_orig = submit->cb_param; |
| 45 | enum async_tx_flags flags_orig = submit->flags; |
Dan Williams | 1e55db2 | 2008-07-16 19:44:56 -0700 | [diff] [blame] | 46 | enum dma_ctrl_flags dma_flags; |
| 47 | int xor_src_cnt; |
| 48 | dma_addr_t dma_dest; |
Dan Williams | 9bc89cd | 2007-01-02 11:10:44 -0700 | [diff] [blame] | 49 | |
Dan Williams | a06d568 | 2008-12-08 13:46:00 -0700 | [diff] [blame] | 50 | /* map the dest bidrectional in case it is re-used as a source */ |
| 51 | dma_dest = dma_map_page(dma->dev, dest, offset, len, DMA_BIDIRECTIONAL); |
| 52 | for (i = 0; i < src_cnt; i++) { |
| 53 | /* only map the dest once */ |
| 54 | if (unlikely(src_list[i] == dest)) { |
| 55 | dma_src[i] = dma_dest; |
| 56 | continue; |
| 57 | } |
Dan Williams | 1e55db2 | 2008-07-16 19:44:56 -0700 | [diff] [blame] | 58 | dma_src[i] = dma_map_page(dma->dev, src_list[i], offset, |
Dan Williams | 0036731 | 2008-02-02 19:49:57 -0700 | [diff] [blame] | 59 | len, DMA_TO_DEVICE); |
Dan Williams | a06d568 | 2008-12-08 13:46:00 -0700 | [diff] [blame] | 60 | } |
Dan Williams | 0036731 | 2008-02-02 19:49:57 -0700 | [diff] [blame] | 61 | |
Dan Williams | 1e55db2 | 2008-07-16 19:44:56 -0700 | [diff] [blame] | 62 | while (src_cnt) { |
Dan Williams | a08abd8 | 2009-06-03 11:43:59 -0700 | [diff] [blame] | 63 | submit->flags = flags_orig; |
Dan Williams | 1e55db2 | 2008-07-16 19:44:56 -0700 | [diff] [blame] | 64 | dma_flags = 0; |
Dan Williams | b2f46fd | 2009-07-14 12:20:36 -0700 | [diff] [blame] | 65 | xor_src_cnt = min(src_cnt, (int)dma->max_xor); |
Dan Williams | 1e55db2 | 2008-07-16 19:44:56 -0700 | [diff] [blame] | 66 | /* if we are submitting additional xors, leave the chain open, |
| 67 | * clear the callback parameters, and leave the destination |
| 68 | * buffer mapped |
| 69 | */ |
| 70 | if (src_cnt > xor_src_cnt) { |
Dan Williams | a08abd8 | 2009-06-03 11:43:59 -0700 | [diff] [blame] | 71 | submit->flags &= ~ASYNC_TX_ACK; |
Dan Williams | 0403e38 | 2009-09-08 17:42:50 -0700 | [diff] [blame] | 72 | submit->flags |= ASYNC_TX_FENCE; |
Dan Williams | 1e55db2 | 2008-07-16 19:44:56 -0700 | [diff] [blame] | 73 | dma_flags = DMA_COMPL_SKIP_DEST_UNMAP; |
Dan Williams | a08abd8 | 2009-06-03 11:43:59 -0700 | [diff] [blame] | 74 | submit->cb_fn = NULL; |
| 75 | submit->cb_param = NULL; |
Dan Williams | 1e55db2 | 2008-07-16 19:44:56 -0700 | [diff] [blame] | 76 | } else { |
Dan Williams | a08abd8 | 2009-06-03 11:43:59 -0700 | [diff] [blame] | 77 | submit->cb_fn = cb_fn_orig; |
| 78 | submit->cb_param = cb_param_orig; |
Dan Williams | 1e55db2 | 2008-07-16 19:44:56 -0700 | [diff] [blame] | 79 | } |
Dan Williams | a08abd8 | 2009-06-03 11:43:59 -0700 | [diff] [blame] | 80 | if (submit->cb_fn) |
Dan Williams | 1e55db2 | 2008-07-16 19:44:56 -0700 | [diff] [blame] | 81 | dma_flags |= DMA_PREP_INTERRUPT; |
Dan Williams | 0403e38 | 2009-09-08 17:42:50 -0700 | [diff] [blame] | 82 | if (submit->flags & ASYNC_TX_FENCE) |
| 83 | dma_flags |= DMA_PREP_FENCE; |
Dan Williams | 1e55db2 | 2008-07-16 19:44:56 -0700 | [diff] [blame] | 84 | /* Since we have clobbered the src_list we are committed |
| 85 | * to doing this asynchronously. Drivers force forward progress |
| 86 | * in case they can not provide a descriptor |
| 87 | */ |
| 88 | tx = dma->device_prep_dma_xor(chan, dma_dest, &dma_src[src_off], |
| 89 | xor_src_cnt, len, dma_flags); |
| 90 | |
Dan Williams | 669ab0b | 2008-07-17 17:59:55 -0700 | [diff] [blame] | 91 | if (unlikely(!tx)) |
Dan Williams | a08abd8 | 2009-06-03 11:43:59 -0700 | [diff] [blame] | 92 | async_tx_quiesce(&submit->depend_tx); |
Dan Williams | 0036731 | 2008-02-02 19:49:57 -0700 | [diff] [blame] | 93 | |
Dan Williams | 1e55db2 | 2008-07-16 19:44:56 -0700 | [diff] [blame] | 94 | /* spin wait for the preceeding transactions to complete */ |
Dan Williams | 669ab0b | 2008-07-17 17:59:55 -0700 | [diff] [blame] | 95 | while (unlikely(!tx)) { |
| 96 | dma_async_issue_pending(chan); |
Dan Williams | 1e55db2 | 2008-07-16 19:44:56 -0700 | [diff] [blame] | 97 | tx = dma->device_prep_dma_xor(chan, dma_dest, |
| 98 | &dma_src[src_off], |
| 99 | xor_src_cnt, len, |
| 100 | dma_flags); |
Dan Williams | 669ab0b | 2008-07-17 17:59:55 -0700 | [diff] [blame] | 101 | } |
Dan Williams | 9bc89cd | 2007-01-02 11:10:44 -0700 | [diff] [blame] | 102 | |
Dan Williams | a08abd8 | 2009-06-03 11:43:59 -0700 | [diff] [blame] | 103 | async_tx_submit(chan, tx, submit); |
| 104 | submit->depend_tx = tx; |
Dan Williams | 1e55db2 | 2008-07-16 19:44:56 -0700 | [diff] [blame] | 105 | |
| 106 | if (src_cnt > xor_src_cnt) { |
| 107 | /* drop completed sources */ |
| 108 | src_cnt -= xor_src_cnt; |
| 109 | src_off += xor_src_cnt; |
| 110 | |
| 111 | /* use the intermediate result a source */ |
| 112 | dma_src[--src_off] = dma_dest; |
| 113 | src_cnt++; |
| 114 | } else |
| 115 | break; |
| 116 | } |
Dan Williams | 0036731 | 2008-02-02 19:49:57 -0700 | [diff] [blame] | 117 | |
| 118 | return tx; |
Dan Williams | 9bc89cd | 2007-01-02 11:10:44 -0700 | [diff] [blame] | 119 | } |
| 120 | |
| 121 | static void |
| 122 | do_sync_xor(struct page *dest, struct page **src_list, unsigned int offset, |
Dan Williams | a08abd8 | 2009-06-03 11:43:59 -0700 | [diff] [blame] | 123 | int src_cnt, size_t len, struct async_submit_ctl *submit) |
Dan Williams | 9bc89cd | 2007-01-02 11:10:44 -0700 | [diff] [blame] | 124 | { |
Dan Williams | 9bc89cd | 2007-01-02 11:10:44 -0700 | [diff] [blame] | 125 | int i; |
Dan Williams | 1e55db2 | 2008-07-16 19:44:56 -0700 | [diff] [blame] | 126 | int xor_src_cnt; |
| 127 | int src_off = 0; |
| 128 | void *dest_buf; |
Dan Williams | 04ce9ab | 2009-06-03 14:22:28 -0700 | [diff] [blame] | 129 | void **srcs; |
Dan Williams | 9bc89cd | 2007-01-02 11:10:44 -0700 | [diff] [blame] | 130 | |
Dan Williams | 04ce9ab | 2009-06-03 14:22:28 -0700 | [diff] [blame] | 131 | if (submit->scribble) |
| 132 | srcs = submit->scribble; |
| 133 | else |
| 134 | srcs = (void **) src_list; |
| 135 | |
| 136 | /* convert to buffer pointers */ |
Dan Williams | 9bc89cd | 2007-01-02 11:10:44 -0700 | [diff] [blame] | 137 | for (i = 0; i < src_cnt; i++) |
Dan Williams | 1e55db2 | 2008-07-16 19:44:56 -0700 | [diff] [blame] | 138 | srcs[i] = page_address(src_list[i]) + offset; |
Dan Williams | 9bc89cd | 2007-01-02 11:10:44 -0700 | [diff] [blame] | 139 | |
| 140 | /* set destination address */ |
Dan Williams | 1e55db2 | 2008-07-16 19:44:56 -0700 | [diff] [blame] | 141 | dest_buf = page_address(dest) + offset; |
Dan Williams | 9bc89cd | 2007-01-02 11:10:44 -0700 | [diff] [blame] | 142 | |
Dan Williams | a08abd8 | 2009-06-03 11:43:59 -0700 | [diff] [blame] | 143 | if (submit->flags & ASYNC_TX_XOR_ZERO_DST) |
Dan Williams | 1e55db2 | 2008-07-16 19:44:56 -0700 | [diff] [blame] | 144 | memset(dest_buf, 0, len); |
Dan Williams | 9bc89cd | 2007-01-02 11:10:44 -0700 | [diff] [blame] | 145 | |
Dan Williams | 1e55db2 | 2008-07-16 19:44:56 -0700 | [diff] [blame] | 146 | while (src_cnt > 0) { |
| 147 | /* process up to 'MAX_XOR_BLOCKS' sources */ |
| 148 | xor_src_cnt = min(src_cnt, MAX_XOR_BLOCKS); |
| 149 | xor_blocks(xor_src_cnt, len, dest_buf, &srcs[src_off]); |
| 150 | |
| 151 | /* drop completed sources */ |
| 152 | src_cnt -= xor_src_cnt; |
| 153 | src_off += xor_src_cnt; |
| 154 | } |
Dan Williams | 9bc89cd | 2007-01-02 11:10:44 -0700 | [diff] [blame] | 155 | |
Dan Williams | a08abd8 | 2009-06-03 11:43:59 -0700 | [diff] [blame] | 156 | async_tx_sync_epilog(submit); |
Dan Williams | 9bc89cd | 2007-01-02 11:10:44 -0700 | [diff] [blame] | 157 | } |
| 158 | |
| 159 | /** |
| 160 | * async_xor - attempt to xor a set of blocks with a dma engine. |
Dan Williams | 9bc89cd | 2007-01-02 11:10:44 -0700 | [diff] [blame] | 161 | * @dest: destination page |
Dan Williams | a08abd8 | 2009-06-03 11:43:59 -0700 | [diff] [blame] | 162 | * @src_list: array of source pages |
| 163 | * @offset: common src/dst offset to start transaction |
Dan Williams | 9bc89cd | 2007-01-02 11:10:44 -0700 | [diff] [blame] | 164 | * @src_cnt: number of source pages |
| 165 | * @len: length in bytes |
Dan Williams | a08abd8 | 2009-06-03 11:43:59 -0700 | [diff] [blame] | 166 | * @submit: submission / completion modifiers |
| 167 | * |
| 168 | * honored flags: ASYNC_TX_ACK, ASYNC_TX_XOR_ZERO_DST, ASYNC_TX_XOR_DROP_DST |
| 169 | * |
| 170 | * xor_blocks always uses the dest as a source so the |
| 171 | * ASYNC_TX_XOR_ZERO_DST flag must be set to not include dest data in |
| 172 | * the calculation. The assumption with dma eninges is that they only |
| 173 | * use the destination buffer as a source when it is explicity specified |
| 174 | * in the source list. |
| 175 | * |
| 176 | * src_list note: if the dest is also a source it must be at index zero. |
| 177 | * The contents of this array will be overwritten if a scribble region |
| 178 | * is not specified. |
Dan Williams | 9bc89cd | 2007-01-02 11:10:44 -0700 | [diff] [blame] | 179 | */ |
| 180 | struct dma_async_tx_descriptor * |
| 181 | async_xor(struct page *dest, struct page **src_list, unsigned int offset, |
Dan Williams | a08abd8 | 2009-06-03 11:43:59 -0700 | [diff] [blame] | 182 | int src_cnt, size_t len, struct async_submit_ctl *submit) |
Dan Williams | 9bc89cd | 2007-01-02 11:10:44 -0700 | [diff] [blame] | 183 | { |
Dan Williams | a08abd8 | 2009-06-03 11:43:59 -0700 | [diff] [blame] | 184 | struct dma_chan *chan = async_tx_find_channel(submit, DMA_XOR, |
Dan Williams | 47437b2 | 2008-02-02 19:49:59 -0700 | [diff] [blame] | 185 | &dest, 1, src_list, |
| 186 | src_cnt, len); |
Dan Williams | 04ce9ab | 2009-06-03 14:22:28 -0700 | [diff] [blame] | 187 | dma_addr_t *dma_src = NULL; |
| 188 | |
Dan Williams | 9bc89cd | 2007-01-02 11:10:44 -0700 | [diff] [blame] | 189 | BUG_ON(src_cnt <= 1); |
| 190 | |
Dan Williams | 04ce9ab | 2009-06-03 14:22:28 -0700 | [diff] [blame] | 191 | if (submit->scribble) |
| 192 | dma_src = submit->scribble; |
| 193 | else if (sizeof(dma_addr_t) <= sizeof(struct page *)) |
| 194 | dma_src = (dma_addr_t *) src_list; |
| 195 | |
Dan Williams | 83544ae | 2009-09-08 17:42:53 -0700 | [diff] [blame] | 196 | if (dma_src && chan && is_dma_xor_aligned(chan->device, offset, 0, len)) { |
Dan Williams | 1e55db2 | 2008-07-16 19:44:56 -0700 | [diff] [blame] | 197 | /* run the xor asynchronously */ |
| 198 | pr_debug("%s (async): len: %zu\n", __func__, len); |
Dan Williams | 9bc89cd | 2007-01-02 11:10:44 -0700 | [diff] [blame] | 199 | |
Dan Williams | 1e55db2 | 2008-07-16 19:44:56 -0700 | [diff] [blame] | 200 | return do_async_xor(chan, dest, src_list, offset, src_cnt, len, |
Dan Williams | 04ce9ab | 2009-06-03 14:22:28 -0700 | [diff] [blame] | 201 | dma_src, submit); |
Dan Williams | 1e55db2 | 2008-07-16 19:44:56 -0700 | [diff] [blame] | 202 | } else { |
| 203 | /* run the xor synchronously */ |
| 204 | pr_debug("%s (sync): len: %zu\n", __func__, len); |
Dan Williams | 04ce9ab | 2009-06-03 14:22:28 -0700 | [diff] [blame] | 205 | WARN_ONCE(chan, "%s: no space for dma address conversion\n", |
| 206 | __func__); |
Dan Williams | 9bc89cd | 2007-01-02 11:10:44 -0700 | [diff] [blame] | 207 | |
Dan Williams | 1e55db2 | 2008-07-16 19:44:56 -0700 | [diff] [blame] | 208 | /* in the sync case the dest is an implied source |
| 209 | * (assumes the dest is the first source) |
| 210 | */ |
Dan Williams | a08abd8 | 2009-06-03 11:43:59 -0700 | [diff] [blame] | 211 | if (submit->flags & ASYNC_TX_XOR_DROP_DST) { |
Dan Williams | 1e55db2 | 2008-07-16 19:44:56 -0700 | [diff] [blame] | 212 | src_cnt--; |
| 213 | src_list++; |
Dan Williams | 9bc89cd | 2007-01-02 11:10:44 -0700 | [diff] [blame] | 214 | } |
| 215 | |
Dan Williams | 1e55db2 | 2008-07-16 19:44:56 -0700 | [diff] [blame] | 216 | /* wait for any prerequisite operations */ |
Dan Williams | a08abd8 | 2009-06-03 11:43:59 -0700 | [diff] [blame] | 217 | async_tx_quiesce(&submit->depend_tx); |
Dan Williams | 9bc89cd | 2007-01-02 11:10:44 -0700 | [diff] [blame] | 218 | |
Dan Williams | a08abd8 | 2009-06-03 11:43:59 -0700 | [diff] [blame] | 219 | do_sync_xor(dest, src_list, offset, src_cnt, len, submit); |
Dan Williams | 1e55db2 | 2008-07-16 19:44:56 -0700 | [diff] [blame] | 220 | |
| 221 | return NULL; |
| 222 | } |
Dan Williams | 9bc89cd | 2007-01-02 11:10:44 -0700 | [diff] [blame] | 223 | } |
| 224 | EXPORT_SYMBOL_GPL(async_xor); |
| 225 | |
| 226 | static int page_is_zero(struct page *p, unsigned int offset, size_t len) |
| 227 | { |
| 228 | char *a = page_address(p) + offset; |
| 229 | return ((*(u32 *) a) == 0 && |
| 230 | memcmp(a, a + 4, len - 4) == 0); |
| 231 | } |
| 232 | |
| 233 | /** |
Dan Williams | 099f53c | 2009-04-08 14:28:37 -0700 | [diff] [blame] | 234 | * async_xor_val - attempt a xor parity check with a dma engine. |
Dan Williams | 9bc89cd | 2007-01-02 11:10:44 -0700 | [diff] [blame] | 235 | * @dest: destination page used if the xor is performed synchronously |
Dan Williams | a08abd8 | 2009-06-03 11:43:59 -0700 | [diff] [blame] | 236 | * @src_list: array of source pages |
Dan Williams | 9bc89cd | 2007-01-02 11:10:44 -0700 | [diff] [blame] | 237 | * @offset: offset in pages to start transaction |
| 238 | * @src_cnt: number of source pages |
| 239 | * @len: length in bytes |
| 240 | * @result: 0 if sum == 0 else non-zero |
Dan Williams | a08abd8 | 2009-06-03 11:43:59 -0700 | [diff] [blame] | 241 | * @submit: submission / completion modifiers |
| 242 | * |
| 243 | * honored flags: ASYNC_TX_ACK |
| 244 | * |
| 245 | * src_list note: if the dest is also a source it must be at index zero. |
| 246 | * The contents of this array will be overwritten if a scribble region |
| 247 | * is not specified. |
Dan Williams | 9bc89cd | 2007-01-02 11:10:44 -0700 | [diff] [blame] | 248 | */ |
| 249 | struct dma_async_tx_descriptor * |
Dan Williams | a08abd8 | 2009-06-03 11:43:59 -0700 | [diff] [blame] | 250 | async_xor_val(struct page *dest, struct page **src_list, unsigned int offset, |
Dan Williams | ad283ea | 2009-08-29 19:09:26 -0700 | [diff] [blame] | 251 | int src_cnt, size_t len, enum sum_check_flags *result, |
Dan Williams | a08abd8 | 2009-06-03 11:43:59 -0700 | [diff] [blame] | 252 | struct async_submit_ctl *submit) |
Dan Williams | 9bc89cd | 2007-01-02 11:10:44 -0700 | [diff] [blame] | 253 | { |
Dan Williams | a08abd8 | 2009-06-03 11:43:59 -0700 | [diff] [blame] | 254 | struct dma_chan *chan = async_tx_find_channel(submit, DMA_XOR_VAL, |
Dan Williams | 47437b2 | 2008-02-02 19:49:59 -0700 | [diff] [blame] | 255 | &dest, 1, src_list, |
| 256 | src_cnt, len); |
Dan Williams | 9bc89cd | 2007-01-02 11:10:44 -0700 | [diff] [blame] | 257 | struct dma_device *device = chan ? chan->device : NULL; |
Dan Williams | 0036731 | 2008-02-02 19:49:57 -0700 | [diff] [blame] | 258 | struct dma_async_tx_descriptor *tx = NULL; |
Dan Williams | 04ce9ab | 2009-06-03 14:22:28 -0700 | [diff] [blame] | 259 | dma_addr_t *dma_src = NULL; |
Dan Williams | 9bc89cd | 2007-01-02 11:10:44 -0700 | [diff] [blame] | 260 | |
| 261 | BUG_ON(src_cnt <= 1); |
| 262 | |
Dan Williams | 04ce9ab | 2009-06-03 14:22:28 -0700 | [diff] [blame] | 263 | if (submit->scribble) |
| 264 | dma_src = submit->scribble; |
| 265 | else if (sizeof(dma_addr_t) <= sizeof(struct page *)) |
| 266 | dma_src = (dma_addr_t *) src_list; |
| 267 | |
Dan Williams | 83544ae | 2009-09-08 17:42:53 -0700 | [diff] [blame] | 268 | if (dma_src && device && src_cnt <= device->max_xor && |
| 269 | is_dma_xor_aligned(device, offset, 0, len)) { |
Dan Williams | 0403e38 | 2009-09-08 17:42:50 -0700 | [diff] [blame] | 270 | unsigned long dma_prep_flags = 0; |
Dan Williams | 0036731 | 2008-02-02 19:49:57 -0700 | [diff] [blame] | 271 | int i; |
Dan Williams | 9bc89cd | 2007-01-02 11:10:44 -0700 | [diff] [blame] | 272 | |
Dan Williams | 3280ab3e | 2008-03-13 17:45:28 -0700 | [diff] [blame] | 273 | pr_debug("%s: (async) len: %zu\n", __func__, len); |
Dan Williams | 9bc89cd | 2007-01-02 11:10:44 -0700 | [diff] [blame] | 274 | |
Dan Williams | 0403e38 | 2009-09-08 17:42:50 -0700 | [diff] [blame] | 275 | if (submit->cb_fn) |
| 276 | dma_prep_flags |= DMA_PREP_INTERRUPT; |
| 277 | if (submit->flags & ASYNC_TX_FENCE) |
| 278 | dma_prep_flags |= DMA_PREP_FENCE; |
Dan Williams | 0036731 | 2008-02-02 19:49:57 -0700 | [diff] [blame] | 279 | for (i = 0; i < src_cnt; i++) |
| 280 | dma_src[i] = dma_map_page(device->dev, src_list[i], |
| 281 | offset, len, DMA_TO_DEVICE); |
| 282 | |
Dan Williams | 099f53c | 2009-04-08 14:28:37 -0700 | [diff] [blame] | 283 | tx = device->device_prep_dma_xor_val(chan, dma_src, src_cnt, |
| 284 | len, result, |
| 285 | dma_prep_flags); |
Dan Williams | 669ab0b | 2008-07-17 17:59:55 -0700 | [diff] [blame] | 286 | if (unlikely(!tx)) { |
Dan Williams | a08abd8 | 2009-06-03 11:43:59 -0700 | [diff] [blame] | 287 | async_tx_quiesce(&submit->depend_tx); |
Dan Williams | 0036731 | 2008-02-02 19:49:57 -0700 | [diff] [blame] | 288 | |
Dan Williams | e34a8ae | 2008-08-05 10:22:05 -0700 | [diff] [blame] | 289 | while (!tx) { |
Dan Williams | 669ab0b | 2008-07-17 17:59:55 -0700 | [diff] [blame] | 290 | dma_async_issue_pending(chan); |
Dan Williams | 099f53c | 2009-04-08 14:28:37 -0700 | [diff] [blame] | 291 | tx = device->device_prep_dma_xor_val(chan, |
Dan Williams | 0036731 | 2008-02-02 19:49:57 -0700 | [diff] [blame] | 292 | dma_src, src_cnt, len, result, |
Dan Williams | d4c56f9 | 2008-02-02 19:49:58 -0700 | [diff] [blame] | 293 | dma_prep_flags); |
Dan Williams | e34a8ae | 2008-08-05 10:22:05 -0700 | [diff] [blame] | 294 | } |
Dan Williams | 9bc89cd | 2007-01-02 11:10:44 -0700 | [diff] [blame] | 295 | } |
| 296 | |
Dan Williams | a08abd8 | 2009-06-03 11:43:59 -0700 | [diff] [blame] | 297 | async_tx_submit(chan, tx, submit); |
Dan Williams | 9bc89cd | 2007-01-02 11:10:44 -0700 | [diff] [blame] | 298 | } else { |
Dan Williams | a08abd8 | 2009-06-03 11:43:59 -0700 | [diff] [blame] | 299 | enum async_tx_flags flags_orig = submit->flags; |
Dan Williams | 9bc89cd | 2007-01-02 11:10:44 -0700 | [diff] [blame] | 300 | |
Dan Williams | 3280ab3e | 2008-03-13 17:45:28 -0700 | [diff] [blame] | 301 | pr_debug("%s: (sync) len: %zu\n", __func__, len); |
Dan Williams | 04ce9ab | 2009-06-03 14:22:28 -0700 | [diff] [blame] | 302 | WARN_ONCE(device && src_cnt <= device->max_xor, |
| 303 | "%s: no space for dma address conversion\n", |
| 304 | __func__); |
Dan Williams | 9bc89cd | 2007-01-02 11:10:44 -0700 | [diff] [blame] | 305 | |
Dan Williams | a08abd8 | 2009-06-03 11:43:59 -0700 | [diff] [blame] | 306 | submit->flags |= ASYNC_TX_XOR_DROP_DST; |
| 307 | submit->flags &= ~ASYNC_TX_ACK; |
Dan Williams | 9bc89cd | 2007-01-02 11:10:44 -0700 | [diff] [blame] | 308 | |
Dan Williams | a08abd8 | 2009-06-03 11:43:59 -0700 | [diff] [blame] | 309 | tx = async_xor(dest, src_list, offset, src_cnt, len, submit); |
Dan Williams | 9bc89cd | 2007-01-02 11:10:44 -0700 | [diff] [blame] | 310 | |
Dan Williams | d2c52b7 | 2008-07-17 17:59:55 -0700 | [diff] [blame] | 311 | async_tx_quiesce(&tx); |
Dan Williams | 9bc89cd | 2007-01-02 11:10:44 -0700 | [diff] [blame] | 312 | |
Dan Williams | ad283ea | 2009-08-29 19:09:26 -0700 | [diff] [blame] | 313 | *result = !page_is_zero(dest, offset, len) << SUM_CHECK_P; |
Dan Williams | 9bc89cd | 2007-01-02 11:10:44 -0700 | [diff] [blame] | 314 | |
Dan Williams | a08abd8 | 2009-06-03 11:43:59 -0700 | [diff] [blame] | 315 | async_tx_sync_epilog(submit); |
| 316 | submit->flags = flags_orig; |
Dan Williams | 9bc89cd | 2007-01-02 11:10:44 -0700 | [diff] [blame] | 317 | } |
| 318 | |
| 319 | return tx; |
| 320 | } |
Dan Williams | 099f53c | 2009-04-08 14:28:37 -0700 | [diff] [blame] | 321 | EXPORT_SYMBOL_GPL(async_xor_val); |
Dan Williams | 9bc89cd | 2007-01-02 11:10:44 -0700 | [diff] [blame] | 322 | |
Dan Williams | 9bc89cd | 2007-01-02 11:10:44 -0700 | [diff] [blame] | 323 | MODULE_AUTHOR("Intel Corporation"); |
| 324 | MODULE_DESCRIPTION("asynchronous xor/xor-zero-sum api"); |
| 325 | MODULE_LICENSE("GPL"); |