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Jean-Christophe PLAGNIOL-VILLARD4abb3672012-02-26 19:12:43 +08001/*
2 * at91sam9263.dtsi - Device Tree Include file for AT91SAM9263 family SoC
3 *
4 * Copyright (C) 2012 Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
5 *
6 * Licensed under GPLv2 only.
7 */
8
Jean-Christophe PLAGNIOL-VILLARD6db64d22013-05-15 01:21:50 +08009#include "skeleton.dtsi"
Jean-Christophe PLAGNIOL-VILLARD92f86292013-04-24 08:34:25 +080010#include <dt-bindings/gpio/gpio.h>
Jean-Christophe PLAGNIOL-VILLARD4abb3672012-02-26 19:12:43 +080011
12/ {
13 model = "Atmel AT91SAM9263 family SoC";
14 compatible = "atmel,at91sam9263";
15 interrupt-parent = <&aic>;
16
17 aliases {
18 serial0 = &dbgu;
19 serial1 = &usart0;
20 serial2 = &usart1;
21 serial3 = &usart2;
22 gpio0 = &pioA;
23 gpio1 = &pioB;
24 gpio2 = &pioC;
25 gpio3 = &pioD;
26 gpio4 = &pioE;
27 tcb0 = &tcb0;
Ludovic Desroches05dcd362012-09-12 08:42:16 +020028 i2c0 = &i2c0;
Bo Shen099343c2012-11-07 11:41:41 +080029 ssc0 = &ssc0;
30 ssc1 = &ssc1;
Jean-Christophe PLAGNIOL-VILLARD4abb3672012-02-26 19:12:43 +080031 };
32 cpus {
33 cpu@0 {
34 compatible = "arm,arm926ejs";
35 };
36 };
37
38 memory {
39 reg = <0x20000000 0x08000000>;
40 };
41
42 ahb {
43 compatible = "simple-bus";
44 #address-cells = <1>;
45 #size-cells = <1>;
46 ranges;
47
48 apb {
49 compatible = "simple-bus";
50 #address-cells = <1>;
51 #size-cells = <1>;
52 ranges;
53
54 aic: interrupt-controller@fffff000 {
Ludovic Desrochesf8a073e2012-06-20 16:13:30 +020055 #interrupt-cells = <3>;
Jean-Christophe PLAGNIOL-VILLARD4abb3672012-02-26 19:12:43 +080056 compatible = "atmel,at91rm9200-aic";
57 interrupt-controller;
58 reg = <0xfffff000 0x200>;
Jean-Christophe PLAGNIOL-VILLARDc6573942012-04-09 19:36:36 +080059 atmel,external-irqs = <30 31>;
Jean-Christophe PLAGNIOL-VILLARD4abb3672012-02-26 19:12:43 +080060 };
61
62 pmc: pmc@fffffc00 {
63 compatible = "atmel,at91rm9200-pmc";
64 reg = <0xfffffc00 0x100>;
65 };
66
67 ramc: ramc@ffffe200 {
68 compatible = "atmel,at91sam9260-sdramc";
69 reg = <0xffffe200 0x200
70 0xffffe800 0x200>;
71 };
72
73 pit: timer@fffffd30 {
74 compatible = "atmel,at91sam9260-pit";
75 reg = <0xfffffd30 0xf>;
Ludovic Desrochesf8a073e2012-06-20 16:13:30 +020076 interrupts = <1 4 7>;
Jean-Christophe PLAGNIOL-VILLARD4abb3672012-02-26 19:12:43 +080077 };
78
79 tcb0: timer@fff7c000 {
80 compatible = "atmel,at91rm9200-tcb";
81 reg = <0xfff7c000 0x100>;
Ludovic Desrochesf8a073e2012-06-20 16:13:30 +020082 interrupts = <19 4 0>;
Jean-Christophe PLAGNIOL-VILLARD4abb3672012-02-26 19:12:43 +080083 };
84
85 rstc@fffffd00 {
86 compatible = "atmel,at91sam9260-rstc";
87 reg = <0xfffffd00 0x10>;
88 };
89
90 shdwc@fffffd10 {
91 compatible = "atmel,at91sam9260-shdwc";
92 reg = <0xfffffd10 0x10>;
93 };
94
Jean-Christophe PLAGNIOL-VILLARDe4541ff2012-07-04 17:20:46 +080095 pinctrl@fffff200 {
96 #address-cells = <1>;
97 #size-cells = <1>;
98 compatible = "atmel,at91rm9200-pinctrl", "simple-bus";
99 ranges = <0xfffff200 0xfffff200 0xa00>;
Jean-Christophe PLAGNIOL-VILLARD4abb3672012-02-26 19:12:43 +0800100
Jean-Christophe PLAGNIOL-VILLARD5314ec82012-07-05 16:56:09 +0800101 atmel,mux-mask = <
102 /* A B */
103 0xfffffffb 0xffffe07f /* pioA */
104 0x0007ffff 0x39072fff /* pioB */
105 0xffffffff 0x3ffffff8 /* pioC */
106 0xfffffbff 0xffffffff /* pioD */
107 0xffe00fff 0xfbfcff00 /* pioE */
108 >;
109
110 /* shared pinctrl settings */
Jean-Christophe PLAGNIOL-VILLARDec6754a2012-07-05 16:56:09 +0800111 dbgu {
112 pinctrl_dbgu: dbgu-0 {
113 atmel,pins =
114 <2 30 0x1 0x0 /* PC30 periph A */
115 2 31 0x1 0x1>; /* PC31 periph with pullup */
116 };
117 };
118
Jean-Christophe PLAGNIOL-VILLARD9e3129e2012-11-19 06:40:01 +0800119 usart0 {
120 pinctrl_usart0: usart0-0 {
Jean-Christophe PLAGNIOL-VILLARDec6754a2012-07-05 16:56:09 +0800121 atmel,pins =
122 <0 26 0x1 0x1 /* PA26 periph A with pullup */
123 0 27 0x1 0x0>; /* PA27 periph A */
124 };
125
Jean-Christophe PLAGNIOL-VILLARDc58c0c52012-11-19 07:30:01 +0800126 pinctrl_usart0_rts: usart0_rts-0 {
Jean-Christophe PLAGNIOL-VILLARDec6754a2012-07-05 16:56:09 +0800127 atmel,pins =
Jean-Christophe PLAGNIOL-VILLARDc58c0c52012-11-19 07:30:01 +0800128 <0 28 0x1 0x0>; /* PA28 periph A */
129 };
130
131 pinctrl_usart0_cts: usart0_cts-0 {
132 atmel,pins =
133 <0 29 0x1 0x0>; /* PA29 periph A */
Jean-Christophe PLAGNIOL-VILLARDec6754a2012-07-05 16:56:09 +0800134 };
135 };
136
Jean-Christophe PLAGNIOL-VILLARD9e3129e2012-11-19 06:40:01 +0800137 usart1 {
138 pinctrl_usart1: usart1-0 {
Jean-Christophe PLAGNIOL-VILLARDec6754a2012-07-05 16:56:09 +0800139 atmel,pins =
140 <3 0 0x1 0x1 /* PD0 periph A with pullup */
141 3 1 0x1 0x0>; /* PD1 periph A */
142 };
143
Jean-Christophe PLAGNIOL-VILLARDc58c0c52012-11-19 07:30:01 +0800144 pinctrl_usart1_rts: usart1_rts-0 {
Jean-Christophe PLAGNIOL-VILLARDec6754a2012-07-05 16:56:09 +0800145 atmel,pins =
Jean-Christophe PLAGNIOL-VILLARDc58c0c52012-11-19 07:30:01 +0800146 <3 7 0x2 0x0>; /* PD7 periph B */
147 };
148
149 pinctrl_usart1_cts: usart1_cts-0 {
150 atmel,pins =
151 <3 8 0x2 0x0>; /* PD8 periph B */
Jean-Christophe PLAGNIOL-VILLARDec6754a2012-07-05 16:56:09 +0800152 };
153 };
154
Jean-Christophe PLAGNIOL-VILLARD9e3129e2012-11-19 06:40:01 +0800155 usart2 {
156 pinctrl_usart2: usart2-0 {
Jean-Christophe PLAGNIOL-VILLARDec6754a2012-07-05 16:56:09 +0800157 atmel,pins =
158 <3 2 0x1 0x1 /* PD2 periph A with pullup */
159 3 3 0x1 0x0>; /* PD3 periph A */
160 };
161
Jean-Christophe PLAGNIOL-VILLARDc58c0c52012-11-19 07:30:01 +0800162 pinctrl_usart2_rts: usart2_rts-0 {
Jean-Christophe PLAGNIOL-VILLARDec6754a2012-07-05 16:56:09 +0800163 atmel,pins =
Jean-Christophe PLAGNIOL-VILLARDc58c0c52012-11-19 07:30:01 +0800164 <3 5 0x2 0x0>; /* PD5 periph B */
165 };
166
167 pinctrl_usart2_cts: usart2_cts-0 {
168 atmel,pins =
169 <4 6 0x2 0x0>; /* PD6 periph B */
Jean-Christophe PLAGNIOL-VILLARDec6754a2012-07-05 16:56:09 +0800170 };
171 };
Jean-Christophe PLAGNIOL-VILLARD5314ec82012-07-05 16:56:09 +0800172
Jean-Christophe PLAGNIOL-VILLARD7a38d452012-07-12 23:36:52 +0800173 nand {
174 pinctrl_nand: nand-0 {
175 atmel,pins =
176 <0 22 0x0 0x1 /* PA22 gpio RDY pin pull_up*/
177 3 15 0x0 0x1>; /* PD15 gpio enable pin pull_up */
178 };
179 };
180
Jean-Christophe PLAGNIOL-VILLARDd9b4fe82012-10-23 10:19:11 +0800181 macb {
182 pinctrl_macb_rmii: macb_rmii-0 {
183 atmel,pins =
184 <2 25 0x2 0x0 /* PC25 periph B */
185 4 21 0x1 0x0 /* PE21 periph A */
186 4 23 0x1 0x0 /* PE23 periph A */
187 4 24 0x1 0x0 /* PE24 periph A */
188 4 25 0x1 0x0 /* PE25 periph A */
189 4 26 0x1 0x0 /* PE26 periph A */
190 4 27 0x1 0x0 /* PE27 periph A */
191 4 28 0x1 0x0 /* PE28 periph A */
192 4 29 0x1 0x0 /* PE29 periph A */
193 4 30 0x1 0x0>; /* PE30 periph A */
194 };
195
196 pinctrl_macb_rmii_mii: macb_rmii_mii-0 {
197 atmel,pins =
198 <2 20 0x2 0x0 /* PC20 periph B */
199 2 21 0x2 0x0 /* PC21 periph B */
200 2 22 0x2 0x0 /* PC22 periph B */
201 2 23 0x2 0x0 /* PC23 periph B */
202 2 24 0x2 0x0 /* PC24 periph B */
203 2 25 0x2 0x0 /* PC25 periph B */
204 2 27 0x2 0x0 /* PC27 periph B */
205 4 22 0x2 0x0>; /* PE22 periph B */
206 };
207 };
208
Jean-Christophe PLAGNIOL-VILLARDd4fe9ac2012-11-16 08:24:17 +0800209 mmc0 {
210 pinctrl_mmc0_clk: mmc0_clk-0 {
211 atmel,pins =
212 <0 12 0x1 0x0>; /* PA12 periph A */
213 };
214
215 pinctrl_mmc0_slot0_cmd_dat0: mmc0_slot0_cmd_dat0-0 {
216 atmel,pins =
217 <0 1 0x1 0x1 /* PA1 periph A with pullup */
218 0 0 0x1 0x1>; /* PA0 periph A with pullup */
219 };
220
221 pinctrl_mmc0_slot0_dat1_3: mmc0_slot0_dat1_3-0 {
222 atmel,pins =
223 <0 3 0x1 0x1 /* PA3 periph A with pullup */
224 0 4 0x1 0x1 /* PA4 periph A with pullup */
225 0 5 0x1 0x1>; /* PA5 periph A with pullup */
226 };
227
228 pinctrl_mmc0_slot1_cmd_dat0: mmc0_slot1_cmd_dat0-0 {
229 atmel,pins =
230 <0 16 0x1 0x1 /* PA16 periph A with pullup */
231 0 17 0x1 0x1>; /* PA17 periph A with pullup */
232 };
233
234 pinctrl_mmc0_slot1_dat1_3: mmc0_slot1_dat1_3-0 {
235 atmel,pins =
236 <0 18 0x1 0x1 /* PA18 periph A with pullup */
237 0 19 0x1 0x1 /* PA19 periph A with pullup */
238 0 20 0x1 0x1>; /* PA20 periph A with pullup */
239 };
240 };
241
242 mmc1 {
243 pinctrl_mmc1_clk: mmc1_clk-0 {
244 atmel,pins =
245 <0 6 0x1 0x0>; /* PA6 periph A */
246 };
247
248 pinctrl_mmc1_slot0_cmd_dat0: mmc1_slot0_cmd_dat0-0 {
249 atmel,pins =
250 <0 7 0x1 0x1 /* PA7 periph A with pullup */
251 0 8 0x1 0x1>; /* PA8 periph A with pullup */
252 };
253
254 pinctrl_mmc1_slot0_dat1_3: mmc1_slot0_dat1_3-0 {
255 atmel,pins =
256 <0 9 0x1 0x1 /* PA9 periph A with pullup */
257 0 10 0x1 0x1 /* PA10 periph A with pullup */
258 0 11 0x1 0x1>; /* PA11 periph A with pullup */
259 };
260
261 pinctrl_mmc1_slot1_cmd_dat0: mmc1_slot1_cmd_dat0-0 {
262 atmel,pins =
263 <0 21 0x1 0x1 /* PA21 periph A with pullup */
264 0 22 0x1 0x1>; /* PA22 periph A with pullup */
265 };
266
267 pinctrl_mmc1_slot1_dat1_3: mmc1_slot1_dat1_3-0 {
268 atmel,pins =
269 <0 23 0x1 0x1 /* PA23 periph A with pullup */
270 0 24 0x1 0x1 /* PA24 periph A with pullup */
271 0 25 0x1 0x1>; /* PA25 periph A with pullup */
272 };
273 };
274
Bo Shen544ae6b2013-01-11 15:08:30 +0100275 ssc0 {
276 pinctrl_ssc0_tx: ssc0_tx-0 {
277 atmel,pins =
278 <1 0 0x2 0x0 /* PB0 periph B */
279 1 1 0x2 0x0 /* PB1 periph B */
280 1 2 0x2 0x0>; /* PB2 periph B */
281 };
282
283 pinctrl_ssc0_rx: ssc0_rx-0 {
284 atmel,pins =
285 <1 3 0x2 0x0 /* PB3 periph B */
286 1 4 0x2 0x0 /* PB4 periph B */
287 1 5 0x2 0x0>; /* PB5 periph B */
288 };
289 };
290
291 ssc1 {
292 pinctrl_ssc1_tx: ssc1_tx-0 {
293 atmel,pins =
294 <1 6 0x1 0x0 /* PB6 periph A */
295 1 7 0x1 0x0 /* PB7 periph A */
296 1 8 0x1 0x0>; /* PB8 periph A */
297 };
298
299 pinctrl_ssc1_rx: ssc1_rx-0 {
300 atmel,pins =
301 <1 9 0x1 0x0 /* PB9 periph A */
302 1 10 0x1 0x0 /* PB10 periph A */
303 1 11 0x1 0x0>; /* PB11 periph A */
304 };
305 };
306
Wenyou Yanga68b7282013-04-03 14:03:52 +0800307 spi0 {
308 pinctrl_spi0: spi0-0 {
309 atmel,pins =
310 <0 0 0x2 0x0 /* PA0 periph B SPI0_MISO pin */
311 0 1 0x2 0x0 /* PA1 periph B SPI0_MOSI pin */
312 0 2 0x2 0x0>; /* PA2 periph B SPI0_SPCK pin */
313 };
314 };
315
316 spi1 {
317 pinctrl_spi1: spi1-0 {
318 atmel,pins =
319 <1 12 0x1 0x0 /* PB12 periph A SPI1_MISO pin */
320 1 13 0x1 0x0 /* PB13 periph A SPI1_MOSI pin */
321 1 14 0x1 0x0>; /* PB14 periph A SPI1_SPCK pin */
322 };
323 };
324
Jean-Christophe PLAGNIOL-VILLARDe4541ff2012-07-04 17:20:46 +0800325 pioA: gpio@fffff200 {
326 compatible = "atmel,at91rm9200-gpio";
327 reg = <0xfffff200 0x200>;
328 interrupts = <2 4 1>;
329 #gpio-cells = <2>;
330 gpio-controller;
331 interrupt-controller;
332 #interrupt-cells = <2>;
333 };
Jean-Christophe PLAGNIOL-VILLARD4abb3672012-02-26 19:12:43 +0800334
Jean-Christophe PLAGNIOL-VILLARDe4541ff2012-07-04 17:20:46 +0800335 pioB: gpio@fffff400 {
336 compatible = "atmel,at91rm9200-gpio";
337 reg = <0xfffff400 0x200>;
338 interrupts = <3 4 1>;
339 #gpio-cells = <2>;
340 gpio-controller;
341 interrupt-controller;
342 #interrupt-cells = <2>;
343 };
Jean-Christophe PLAGNIOL-VILLARD4abb3672012-02-26 19:12:43 +0800344
Jean-Christophe PLAGNIOL-VILLARDe4541ff2012-07-04 17:20:46 +0800345 pioC: gpio@fffff600 {
346 compatible = "atmel,at91rm9200-gpio";
347 reg = <0xfffff600 0x200>;
348 interrupts = <4 4 1>;
349 #gpio-cells = <2>;
350 gpio-controller;
351 interrupt-controller;
352 #interrupt-cells = <2>;
353 };
Jean-Christophe PLAGNIOL-VILLARD4abb3672012-02-26 19:12:43 +0800354
Jean-Christophe PLAGNIOL-VILLARDe4541ff2012-07-04 17:20:46 +0800355 pioD: gpio@fffff800 {
356 compatible = "atmel,at91rm9200-gpio";
357 reg = <0xfffff800 0x200>;
358 interrupts = <4 4 1>;
359 #gpio-cells = <2>;
360 gpio-controller;
361 interrupt-controller;
362 #interrupt-cells = <2>;
363 };
364
365 pioE: gpio@fffffa00 {
366 compatible = "atmel,at91rm9200-gpio";
367 reg = <0xfffffa00 0x200>;
368 interrupts = <4 4 1>;
369 #gpio-cells = <2>;
370 gpio-controller;
371 interrupt-controller;
372 #interrupt-cells = <2>;
Jean-Christophe PLAGNIOL-VILLARD5314ec82012-07-05 16:56:09 +0800373 };
Jean-Christophe PLAGNIOL-VILLARD4abb3672012-02-26 19:12:43 +0800374 };
375
376 dbgu: serial@ffffee00 {
377 compatible = "atmel,at91sam9260-usart";
378 reg = <0xffffee00 0x200>;
Ludovic Desrochesf8a073e2012-06-20 16:13:30 +0200379 interrupts = <1 4 7>;
Jean-Christophe PLAGNIOL-VILLARDec6754a2012-07-05 16:56:09 +0800380 pinctrl-names = "default";
381 pinctrl-0 = <&pinctrl_dbgu>;
Jean-Christophe PLAGNIOL-VILLARD4abb3672012-02-26 19:12:43 +0800382 status = "disabled";
383 };
384
385 usart0: serial@fff8c000 {
386 compatible = "atmel,at91sam9260-usart";
387 reg = <0xfff8c000 0x200>;
Ludovic Desrochesf8a073e2012-06-20 16:13:30 +0200388 interrupts = <7 4 5>;
Jean-Christophe PLAGNIOL-VILLARD4abb3672012-02-26 19:12:43 +0800389 atmel,use-dma-rx;
390 atmel,use-dma-tx;
Jean-Christophe PLAGNIOL-VILLARDec6754a2012-07-05 16:56:09 +0800391 pinctrl-names = "default";
Jean-Christophe PLAGNIOL-VILLARD9e3129e2012-11-19 06:40:01 +0800392 pinctrl-0 = <&pinctrl_usart0>;
Jean-Christophe PLAGNIOL-VILLARD4abb3672012-02-26 19:12:43 +0800393 status = "disabled";
394 };
395
396 usart1: serial@fff90000 {
397 compatible = "atmel,at91sam9260-usart";
398 reg = <0xfff90000 0x200>;
Ludovic Desrochesf8a073e2012-06-20 16:13:30 +0200399 interrupts = <8 4 5>;
Jean-Christophe PLAGNIOL-VILLARD4abb3672012-02-26 19:12:43 +0800400 atmel,use-dma-rx;
401 atmel,use-dma-tx;
Jean-Christophe PLAGNIOL-VILLARDec6754a2012-07-05 16:56:09 +0800402 pinctrl-names = "default";
Jean-Christophe PLAGNIOL-VILLARD9e3129e2012-11-19 06:40:01 +0800403 pinctrl-0 = <&pinctrl_usart1>;
Jean-Christophe PLAGNIOL-VILLARD4abb3672012-02-26 19:12:43 +0800404 status = "disabled";
405 };
406
407 usart2: serial@fff94000 {
408 compatible = "atmel,at91sam9260-usart";
409 reg = <0xfff94000 0x200>;
Ludovic Desrochesf8a073e2012-06-20 16:13:30 +0200410 interrupts = <9 4 5>;
Jean-Christophe PLAGNIOL-VILLARD4abb3672012-02-26 19:12:43 +0800411 atmel,use-dma-rx;
412 atmel,use-dma-tx;
Jean-Christophe PLAGNIOL-VILLARDec6754a2012-07-05 16:56:09 +0800413 pinctrl-names = "default";
Jean-Christophe PLAGNIOL-VILLARD9e3129e2012-11-19 06:40:01 +0800414 pinctrl-0 = <&pinctrl_usart2>;
Jean-Christophe PLAGNIOL-VILLARD4abb3672012-02-26 19:12:43 +0800415 status = "disabled";
416 };
417
Bo Shen099343c2012-11-07 11:41:41 +0800418 ssc0: ssc@fff98000 {
419 compatible = "atmel,at91rm9200-ssc";
420 reg = <0xfff98000 0x4000>;
421 interrupts = <16 4 5>;
Bo Shen544ae6b2013-01-11 15:08:30 +0100422 pinctrl-names = "default";
423 pinctrl-0 = <&pinctrl_ssc0_tx &pinctrl_ssc0_rx>;
Bo Shen315656b2012-12-13 10:05:07 +0800424 status = "disabled";
Bo Shen099343c2012-11-07 11:41:41 +0800425 };
426
427 ssc1: ssc@fff9c000 {
428 compatible = "atmel,at91rm9200-ssc";
429 reg = <0xfff9c000 0x4000>;
430 interrupts = <17 4 5>;
Bo Shen544ae6b2013-01-11 15:08:30 +0100431 pinctrl-names = "default";
432 pinctrl-0 = <&pinctrl_ssc1_tx &pinctrl_ssc1_rx>;
Bo Shen315656b2012-12-13 10:05:07 +0800433 status = "disabled";
Bo Shen099343c2012-11-07 11:41:41 +0800434 };
435
Jean-Christophe PLAGNIOL-VILLARD4abb3672012-02-26 19:12:43 +0800436 macb0: ethernet@fffbc000 {
437 compatible = "cdns,at32ap7000-macb", "cdns,macb";
438 reg = <0xfffbc000 0x100>;
Ludovic Desrochesf8a073e2012-06-20 16:13:30 +0200439 interrupts = <21 4 3>;
Jean-Christophe PLAGNIOL-VILLARDd9b4fe82012-10-23 10:19:11 +0800440 pinctrl-names = "default";
441 pinctrl-0 = <&pinctrl_macb_rmii>;
Jean-Christophe PLAGNIOL-VILLARD4abb3672012-02-26 19:12:43 +0800442 status = "disabled";
443 };
444
445 usb1: gadget@fff78000 {
446 compatible = "atmel,at91rm9200-udc";
447 reg = <0xfff78000 0x4000>;
Ludovic Desrochesf8a073e2012-06-20 16:13:30 +0200448 interrupts = <24 4 2>;
Jean-Christophe PLAGNIOL-VILLARD4abb3672012-02-26 19:12:43 +0800449 status = "disabled";
450 };
Ludovic Desroches05dcd362012-09-12 08:42:16 +0200451
452 i2c0: i2c@fff88000 {
453 compatible = "atmel,at91sam9263-i2c";
454 reg = <0xfff88000 0x100>;
455 interrupts = <13 4 6>;
456 #address-cells = <1>;
457 #size-cells = <0>;
458 status = "disabled";
459 };
Ludovic Desroches98731372012-11-19 12:23:36 +0100460
461 mmc0: mmc@fff80000 {
462 compatible = "atmel,hsmci";
463 reg = <0xfff80000 0x600>;
464 interrupts = <10 4 0>;
465 #address-cells = <1>;
466 #size-cells = <0>;
467 status = "disabled";
468 };
469
470 mmc1: mmc@fff84000 {
471 compatible = "atmel,hsmci";
472 reg = <0xfff84000 0x600>;
473 interrupts = <11 4 0>;
474 #address-cells = <1>;
475 #size-cells = <0>;
476 status = "disabled";
477 };
Linus Torvaldsdb5b0ae2012-12-13 10:39:26 -0800478
Fabio Porcedda7492e7c2012-11-12 09:37:26 +0100479 watchdog@fffffd40 {
480 compatible = "atmel,at91sam9260-wdt";
481 reg = <0xfffffd40 0x10>;
482 status = "disabled";
483 };
Richard Genoudd50f88a2013-04-03 14:02:18 +0800484
485 spi0: spi@fffa4000 {
486 #address-cells = <1>;
487 #size-cells = <0>;
488 compatible = "atmel,at91rm9200-spi";
489 reg = <0xfffa4000 0x200>;
490 interrupts = <14 4 3>;
Wenyou Yanga68b7282013-04-03 14:03:52 +0800491 pinctrl-names = "default";
492 pinctrl-0 = <&pinctrl_spi0>;
Richard Genoudd50f88a2013-04-03 14:02:18 +0800493 status = "disabled";
494 };
495
496 spi1: spi@fffa8000 {
497 #address-cells = <1>;
498 #size-cells = <0>;
499 compatible = "atmel,at91rm9200-spi";
500 reg = <0xfffa8000 0x200>;
501 interrupts = <15 4 3>;
Wenyou Yanga68b7282013-04-03 14:03:52 +0800502 pinctrl-names = "default";
503 pinctrl-0 = <&pinctrl_spi1>;
Richard Genoudd50f88a2013-04-03 14:02:18 +0800504 status = "disabled";
505 };
Jean-Christophe PLAGNIOL-VILLARD4abb3672012-02-26 19:12:43 +0800506 };
507
508 nand0: nand@40000000 {
509 compatible = "atmel,at91rm9200-nand";
510 #address-cells = <1>;
511 #size-cells = <1>;
512 reg = <0x40000000 0x10000000
513 0xffffe000 0x200
514 >;
515 atmel,nand-addr-offset = <21>;
516 atmel,nand-cmd-offset = <22>;
Jean-Christophe PLAGNIOL-VILLARD7a38d452012-07-12 23:36:52 +0800517 pinctrl-names = "default";
518 pinctrl-0 = <&pinctrl_nand>;
Jean-Christophe PLAGNIOL-VILLARD92f86292013-04-24 08:34:25 +0800519 gpios = <&pioA 22 GPIO_ACTIVE_HIGH
520 &pioD 15 GPIO_ACTIVE_HIGH
Jean-Christophe PLAGNIOL-VILLARD4abb3672012-02-26 19:12:43 +0800521 0
522 >;
523 status = "disabled";
524 };
525
526 usb0: ohci@00a00000 {
527 compatible = "atmel,at91rm9200-ohci", "usb-ohci";
528 reg = <0x00a00000 0x100000>;
Ludovic Desrochesf8a073e2012-06-20 16:13:30 +0200529 interrupts = <29 4 2>;
Jean-Christophe PLAGNIOL-VILLARD4abb3672012-02-26 19:12:43 +0800530 status = "disabled";
531 };
532 };
533
534 i2c@0 {
535 compatible = "i2c-gpio";
Jean-Christophe PLAGNIOL-VILLARD92f86292013-04-24 08:34:25 +0800536 gpios = <&pioB 4 GPIO_ACTIVE_HIGH /* sda */
537 &pioB 5 GPIO_ACTIVE_HIGH /* scl */
Jean-Christophe PLAGNIOL-VILLARD4abb3672012-02-26 19:12:43 +0800538 >;
539 i2c-gpio,sda-open-drain;
540 i2c-gpio,scl-open-drain;
541 i2c-gpio,delay-us = <2>; /* ~100 kHz */
542 #address-cells = <1>;
543 #size-cells = <0>;
544 status = "disabled";
545 };
546};