blob: ea4dfc09779090ec35776b30f006a053f3d36650 [file] [log] [blame]
Changhwan Youn30d8bea2011-03-11 10:39:57 +09001/* linux/arch/arm/mach-exynos4/mct.c
2 *
3 * Copyright (c) 2011 Samsung Electronics Co., Ltd.
4 * http://www.samsung.com
5 *
6 * EXYNOS4 MCT(Multi-Core Timer) support
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11*/
12
13#include <linux/sched.h>
14#include <linux/interrupt.h>
15#include <linux/irq.h>
16#include <linux/err.h>
17#include <linux/clk.h>
18#include <linux/clockchips.h>
Stephen Boydee98d272013-02-15 16:40:51 -080019#include <linux/cpu.h>
Changhwan Youn30d8bea2011-03-11 10:39:57 +090020#include <linux/platform_device.h>
21#include <linux/delay.h>
22#include <linux/percpu.h>
Kukjin Kim2edb36c2012-11-15 15:48:56 +090023#include <linux/of.h>
Thomas Abraham36ba5d52013-03-09 16:01:52 +090024#include <linux/of_irq.h>
25#include <linux/of_address.h>
Thomas Abraham9fbf0c82013-03-09 16:10:03 +090026#include <linux/clocksource.h>
Vincent Guittot93bfb762014-05-02 22:27:01 +090027#include <linux/sched_clock.h>
Changhwan Youn30d8bea2011-03-11 10:39:57 +090028
Thomas Abrahama1ba7a72013-03-09 16:01:47 +090029#define EXYNOS4_MCTREG(x) (x)
30#define EXYNOS4_MCT_G_CNT_L EXYNOS4_MCTREG(0x100)
31#define EXYNOS4_MCT_G_CNT_U EXYNOS4_MCTREG(0x104)
32#define EXYNOS4_MCT_G_CNT_WSTAT EXYNOS4_MCTREG(0x110)
33#define EXYNOS4_MCT_G_COMP0_L EXYNOS4_MCTREG(0x200)
34#define EXYNOS4_MCT_G_COMP0_U EXYNOS4_MCTREG(0x204)
35#define EXYNOS4_MCT_G_COMP0_ADD_INCR EXYNOS4_MCTREG(0x208)
36#define EXYNOS4_MCT_G_TCON EXYNOS4_MCTREG(0x240)
37#define EXYNOS4_MCT_G_INT_CSTAT EXYNOS4_MCTREG(0x244)
38#define EXYNOS4_MCT_G_INT_ENB EXYNOS4_MCTREG(0x248)
39#define EXYNOS4_MCT_G_WSTAT EXYNOS4_MCTREG(0x24C)
40#define _EXYNOS4_MCT_L_BASE EXYNOS4_MCTREG(0x300)
41#define EXYNOS4_MCT_L_BASE(x) (_EXYNOS4_MCT_L_BASE + (0x100 * x))
42#define EXYNOS4_MCT_L_MASK (0xffffff00)
43
44#define MCT_L_TCNTB_OFFSET (0x00)
45#define MCT_L_ICNTB_OFFSET (0x08)
46#define MCT_L_TCON_OFFSET (0x20)
47#define MCT_L_INT_CSTAT_OFFSET (0x30)
48#define MCT_L_INT_ENB_OFFSET (0x34)
49#define MCT_L_WSTAT_OFFSET (0x40)
50#define MCT_G_TCON_START (1 << 8)
51#define MCT_G_TCON_COMP0_AUTO_INC (1 << 1)
52#define MCT_G_TCON_COMP0_ENABLE (1 << 0)
53#define MCT_L_TCON_INTERVAL_MODE (1 << 2)
54#define MCT_L_TCON_INT_START (1 << 1)
55#define MCT_L_TCON_TIMER_START (1 << 0)
56
Changhwan Youn4d2e4d72012-03-09 15:09:21 -080057#define TICK_BASE_CNT 1
58
Changhwan Youn3a062282011-10-04 17:02:58 +090059enum {
60 MCT_INT_SPI,
61 MCT_INT_PPI
62};
63
Thomas Abrahamc371dc62013-03-09 16:01:50 +090064enum {
65 MCT_G0_IRQ,
66 MCT_G1_IRQ,
67 MCT_G2_IRQ,
68 MCT_G3_IRQ,
69 MCT_L0_IRQ,
70 MCT_L1_IRQ,
71 MCT_L2_IRQ,
72 MCT_L3_IRQ,
Chander Kashyap6c16ded2013-12-02 07:48:23 +090073 MCT_L4_IRQ,
74 MCT_L5_IRQ,
75 MCT_L6_IRQ,
76 MCT_L7_IRQ,
Thomas Abrahamc371dc62013-03-09 16:01:50 +090077 MCT_NR_IRQS,
78};
79
Thomas Abrahama1ba7a72013-03-09 16:01:47 +090080static void __iomem *reg_base;
Changhwan Youn30d8bea2011-03-11 10:39:57 +090081static unsigned long clk_rate;
Changhwan Youn3a062282011-10-04 17:02:58 +090082static unsigned int mct_int_type;
Thomas Abrahamc371dc62013-03-09 16:01:50 +090083static int mct_irqs[MCT_NR_IRQS];
Changhwan Youn30d8bea2011-03-11 10:39:57 +090084
85struct mct_clock_event_device {
Stephen Boydee98d272013-02-15 16:40:51 -080086 struct clock_event_device evt;
Thomas Abrahama1ba7a72013-03-09 16:01:47 +090087 unsigned long base;
Changhwan Younc8987472011-10-04 17:09:26 +090088 char name[10];
Changhwan Youn30d8bea2011-03-11 10:39:57 +090089};
90
Thomas Abrahama1ba7a72013-03-09 16:01:47 +090091static void exynos4_mct_write(unsigned int value, unsigned long offset)
Changhwan Youn30d8bea2011-03-11 10:39:57 +090092{
Thomas Abrahama1ba7a72013-03-09 16:01:47 +090093 unsigned long stat_addr;
Changhwan Youn30d8bea2011-03-11 10:39:57 +090094 u32 mask;
95 u32 i;
96
Thomas Abrahama1ba7a72013-03-09 16:01:47 +090097 __raw_writel(value, reg_base + offset);
Changhwan Youn30d8bea2011-03-11 10:39:57 +090098
Thomas Abrahama1ba7a72013-03-09 16:01:47 +090099 if (likely(offset >= EXYNOS4_MCT_L_BASE(0))) {
100 stat_addr = (offset & ~EXYNOS4_MCT_L_MASK) + MCT_L_WSTAT_OFFSET;
101 switch (offset & EXYNOS4_MCT_L_MASK) {
102 case MCT_L_TCON_OFFSET:
Changhwan Younc8987472011-10-04 17:09:26 +0900103 mask = 1 << 3; /* L_TCON write status */
104 break;
Thomas Abrahama1ba7a72013-03-09 16:01:47 +0900105 case MCT_L_ICNTB_OFFSET:
Changhwan Younc8987472011-10-04 17:09:26 +0900106 mask = 1 << 1; /* L_ICNTB write status */
107 break;
Thomas Abrahama1ba7a72013-03-09 16:01:47 +0900108 case MCT_L_TCNTB_OFFSET:
Changhwan Younc8987472011-10-04 17:09:26 +0900109 mask = 1 << 0; /* L_TCNTB write status */
110 break;
111 default:
112 return;
113 }
114 } else {
Thomas Abrahama1ba7a72013-03-09 16:01:47 +0900115 switch (offset) {
116 case EXYNOS4_MCT_G_TCON:
Changhwan Younc8987472011-10-04 17:09:26 +0900117 stat_addr = EXYNOS4_MCT_G_WSTAT;
118 mask = 1 << 16; /* G_TCON write status */
119 break;
Thomas Abrahama1ba7a72013-03-09 16:01:47 +0900120 case EXYNOS4_MCT_G_COMP0_L:
Changhwan Younc8987472011-10-04 17:09:26 +0900121 stat_addr = EXYNOS4_MCT_G_WSTAT;
122 mask = 1 << 0; /* G_COMP0_L write status */
123 break;
Thomas Abrahama1ba7a72013-03-09 16:01:47 +0900124 case EXYNOS4_MCT_G_COMP0_U:
Changhwan Younc8987472011-10-04 17:09:26 +0900125 stat_addr = EXYNOS4_MCT_G_WSTAT;
126 mask = 1 << 1; /* G_COMP0_U write status */
127 break;
Thomas Abrahama1ba7a72013-03-09 16:01:47 +0900128 case EXYNOS4_MCT_G_COMP0_ADD_INCR:
Changhwan Younc8987472011-10-04 17:09:26 +0900129 stat_addr = EXYNOS4_MCT_G_WSTAT;
130 mask = 1 << 2; /* G_COMP0_ADD_INCR w status */
131 break;
Thomas Abrahama1ba7a72013-03-09 16:01:47 +0900132 case EXYNOS4_MCT_G_CNT_L:
Changhwan Younc8987472011-10-04 17:09:26 +0900133 stat_addr = EXYNOS4_MCT_G_CNT_WSTAT;
134 mask = 1 << 0; /* G_CNT_L write status */
135 break;
Thomas Abrahama1ba7a72013-03-09 16:01:47 +0900136 case EXYNOS4_MCT_G_CNT_U:
Changhwan Younc8987472011-10-04 17:09:26 +0900137 stat_addr = EXYNOS4_MCT_G_CNT_WSTAT;
138 mask = 1 << 1; /* G_CNT_U write status */
139 break;
140 default:
141 return;
142 }
Changhwan Youn30d8bea2011-03-11 10:39:57 +0900143 }
144
145 /* Wait maximum 1 ms until written values are applied */
146 for (i = 0; i < loops_per_jiffy / 1000 * HZ; i++)
Thomas Abrahama1ba7a72013-03-09 16:01:47 +0900147 if (__raw_readl(reg_base + stat_addr) & mask) {
148 __raw_writel(mask, reg_base + stat_addr);
Changhwan Youn30d8bea2011-03-11 10:39:57 +0900149 return;
150 }
151
Thomas Abrahama1ba7a72013-03-09 16:01:47 +0900152 panic("MCT hangs after writing %d (offset:0x%lx)\n", value, offset);
Changhwan Youn30d8bea2011-03-11 10:39:57 +0900153}
154
155/* Clocksource handling */
156static void exynos4_mct_frc_start(u32 hi, u32 lo)
157{
158 u32 reg;
159
160 exynos4_mct_write(lo, EXYNOS4_MCT_G_CNT_L);
161 exynos4_mct_write(hi, EXYNOS4_MCT_G_CNT_U);
162
Thomas Abrahama1ba7a72013-03-09 16:01:47 +0900163 reg = __raw_readl(reg_base + EXYNOS4_MCT_G_TCON);
Changhwan Youn30d8bea2011-03-11 10:39:57 +0900164 reg |= MCT_G_TCON_START;
165 exynos4_mct_write(reg, EXYNOS4_MCT_G_TCON);
166}
167
168static cycle_t exynos4_frc_read(struct clocksource *cs)
169{
170 unsigned int lo, hi;
Thomas Abrahama1ba7a72013-03-09 16:01:47 +0900171 u32 hi2 = __raw_readl(reg_base + EXYNOS4_MCT_G_CNT_U);
Changhwan Youn30d8bea2011-03-11 10:39:57 +0900172
173 do {
174 hi = hi2;
Thomas Abrahama1ba7a72013-03-09 16:01:47 +0900175 lo = __raw_readl(reg_base + EXYNOS4_MCT_G_CNT_L);
176 hi2 = __raw_readl(reg_base + EXYNOS4_MCT_G_CNT_U);
Changhwan Youn30d8bea2011-03-11 10:39:57 +0900177 } while (hi != hi2);
178
179 return ((cycle_t)hi << 32) | lo;
180}
181
Changhwan Younaa421c12011-09-02 14:10:52 +0900182static void exynos4_frc_resume(struct clocksource *cs)
183{
184 exynos4_mct_frc_start(0, 0);
185}
186
Changhwan Youn30d8bea2011-03-11 10:39:57 +0900187struct clocksource mct_frc = {
188 .name = "mct-frc",
189 .rating = 400,
190 .read = exynos4_frc_read,
191 .mask = CLOCKSOURCE_MASK(64),
192 .flags = CLOCK_SOURCE_IS_CONTINUOUS,
Changhwan Younaa421c12011-09-02 14:10:52 +0900193 .resume = exynos4_frc_resume,
Changhwan Youn30d8bea2011-03-11 10:39:57 +0900194};
195
Vincent Guittot93bfb762014-05-02 22:27:01 +0900196static u64 notrace exynos4_read_sched_clock(void)
197{
198 return exynos4_frc_read(&mct_frc);
199}
200
Changhwan Youn30d8bea2011-03-11 10:39:57 +0900201static void __init exynos4_clocksource_init(void)
202{
203 exynos4_mct_frc_start(0, 0);
204
205 if (clocksource_register_hz(&mct_frc, clk_rate))
206 panic("%s: can't register clocksource\n", mct_frc.name);
Vincent Guittot93bfb762014-05-02 22:27:01 +0900207
208 sched_clock_register(exynos4_read_sched_clock, 64, clk_rate);
Changhwan Youn30d8bea2011-03-11 10:39:57 +0900209}
210
211static void exynos4_mct_comp0_stop(void)
212{
213 unsigned int tcon;
214
Thomas Abrahama1ba7a72013-03-09 16:01:47 +0900215 tcon = __raw_readl(reg_base + EXYNOS4_MCT_G_TCON);
Changhwan Youn30d8bea2011-03-11 10:39:57 +0900216 tcon &= ~(MCT_G_TCON_COMP0_ENABLE | MCT_G_TCON_COMP0_AUTO_INC);
217
218 exynos4_mct_write(tcon, EXYNOS4_MCT_G_TCON);
219 exynos4_mct_write(0, EXYNOS4_MCT_G_INT_ENB);
220}
221
222static void exynos4_mct_comp0_start(enum clock_event_mode mode,
223 unsigned long cycles)
224{
225 unsigned int tcon;
226 cycle_t comp_cycle;
227
Thomas Abrahama1ba7a72013-03-09 16:01:47 +0900228 tcon = __raw_readl(reg_base + EXYNOS4_MCT_G_TCON);
Changhwan Youn30d8bea2011-03-11 10:39:57 +0900229
230 if (mode == CLOCK_EVT_MODE_PERIODIC) {
231 tcon |= MCT_G_TCON_COMP0_AUTO_INC;
232 exynos4_mct_write(cycles, EXYNOS4_MCT_G_COMP0_ADD_INCR);
233 }
234
235 comp_cycle = exynos4_frc_read(&mct_frc) + cycles;
236 exynos4_mct_write((u32)comp_cycle, EXYNOS4_MCT_G_COMP0_L);
237 exynos4_mct_write((u32)(comp_cycle >> 32), EXYNOS4_MCT_G_COMP0_U);
238
239 exynos4_mct_write(0x1, EXYNOS4_MCT_G_INT_ENB);
240
241 tcon |= MCT_G_TCON_COMP0_ENABLE;
242 exynos4_mct_write(tcon , EXYNOS4_MCT_G_TCON);
243}
244
245static int exynos4_comp_set_next_event(unsigned long cycles,
246 struct clock_event_device *evt)
247{
248 exynos4_mct_comp0_start(evt->mode, cycles);
249
250 return 0;
251}
252
253static void exynos4_comp_set_mode(enum clock_event_mode mode,
254 struct clock_event_device *evt)
255{
Changhwan Youn4d2e4d72012-03-09 15:09:21 -0800256 unsigned long cycles_per_jiffy;
Changhwan Youn30d8bea2011-03-11 10:39:57 +0900257 exynos4_mct_comp0_stop();
258
259 switch (mode) {
260 case CLOCK_EVT_MODE_PERIODIC:
Changhwan Youn4d2e4d72012-03-09 15:09:21 -0800261 cycles_per_jiffy =
262 (((unsigned long long) NSEC_PER_SEC / HZ * evt->mult) >> evt->shift);
263 exynos4_mct_comp0_start(mode, cycles_per_jiffy);
Changhwan Youn30d8bea2011-03-11 10:39:57 +0900264 break;
265
266 case CLOCK_EVT_MODE_ONESHOT:
267 case CLOCK_EVT_MODE_UNUSED:
268 case CLOCK_EVT_MODE_SHUTDOWN:
269 case CLOCK_EVT_MODE_RESUME:
270 break;
271 }
272}
273
274static struct clock_event_device mct_comp_device = {
275 .name = "mct-comp",
276 .features = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT,
277 .rating = 250,
278 .set_next_event = exynos4_comp_set_next_event,
279 .set_mode = exynos4_comp_set_mode,
280};
281
282static irqreturn_t exynos4_mct_comp_isr(int irq, void *dev_id)
283{
284 struct clock_event_device *evt = dev_id;
285
286 exynos4_mct_write(0x1, EXYNOS4_MCT_G_INT_CSTAT);
287
288 evt->event_handler(evt);
289
290 return IRQ_HANDLED;
291}
292
293static struct irqaction mct_comp_event_irq = {
294 .name = "mct_comp_irq",
295 .flags = IRQF_TIMER | IRQF_IRQPOLL,
296 .handler = exynos4_mct_comp_isr,
297 .dev_id = &mct_comp_device,
298};
299
300static void exynos4_clockevent_init(void)
301{
Changhwan Youn30d8bea2011-03-11 10:39:57 +0900302 mct_comp_device.cpumask = cpumask_of(0);
Shawn Guo838a2ae2013-01-12 11:50:05 +0000303 clockevents_config_and_register(&mct_comp_device, clk_rate,
304 0xf, 0xffffffff);
Thomas Abrahamc371dc62013-03-09 16:01:50 +0900305 setup_irq(mct_irqs[MCT_G0_IRQ], &mct_comp_event_irq);
Changhwan Youn30d8bea2011-03-11 10:39:57 +0900306}
307
Kukjin Kim991a6c72011-12-08 10:04:49 +0900308static DEFINE_PER_CPU(struct mct_clock_event_device, percpu_mct_tick);
309
Changhwan Youn30d8bea2011-03-11 10:39:57 +0900310/* Clock event handling */
311static void exynos4_mct_tick_stop(struct mct_clock_event_device *mevt)
312{
313 unsigned long tmp;
314 unsigned long mask = MCT_L_TCON_INT_START | MCT_L_TCON_TIMER_START;
Thomas Abrahama1ba7a72013-03-09 16:01:47 +0900315 unsigned long offset = mevt->base + MCT_L_TCON_OFFSET;
Changhwan Youn30d8bea2011-03-11 10:39:57 +0900316
Thomas Abrahama1ba7a72013-03-09 16:01:47 +0900317 tmp = __raw_readl(reg_base + offset);
Changhwan Youn30d8bea2011-03-11 10:39:57 +0900318 if (tmp & mask) {
319 tmp &= ~mask;
Thomas Abrahama1ba7a72013-03-09 16:01:47 +0900320 exynos4_mct_write(tmp, offset);
Changhwan Youn30d8bea2011-03-11 10:39:57 +0900321 }
322}
323
324static void exynos4_mct_tick_start(unsigned long cycles,
325 struct mct_clock_event_device *mevt)
326{
327 unsigned long tmp;
328
329 exynos4_mct_tick_stop(mevt);
330
331 tmp = (1 << 31) | cycles; /* MCT_L_UPDATE_ICNTB */
332
333 /* update interrupt count buffer */
334 exynos4_mct_write(tmp, mevt->base + MCT_L_ICNTB_OFFSET);
335
Lucas De Marchi25985ed2011-03-30 22:57:33 -0300336 /* enable MCT tick interrupt */
Changhwan Youn30d8bea2011-03-11 10:39:57 +0900337 exynos4_mct_write(0x1, mevt->base + MCT_L_INT_ENB_OFFSET);
338
Thomas Abrahama1ba7a72013-03-09 16:01:47 +0900339 tmp = __raw_readl(reg_base + mevt->base + MCT_L_TCON_OFFSET);
Changhwan Youn30d8bea2011-03-11 10:39:57 +0900340 tmp |= MCT_L_TCON_INT_START | MCT_L_TCON_TIMER_START |
341 MCT_L_TCON_INTERVAL_MODE;
342 exynos4_mct_write(tmp, mevt->base + MCT_L_TCON_OFFSET);
343}
344
345static int exynos4_tick_set_next_event(unsigned long cycles,
346 struct clock_event_device *evt)
347{
Marc Zyngiere700e412011-11-03 11:13:12 +0900348 struct mct_clock_event_device *mevt = this_cpu_ptr(&percpu_mct_tick);
Changhwan Youn30d8bea2011-03-11 10:39:57 +0900349
350 exynos4_mct_tick_start(cycles, mevt);
351
352 return 0;
353}
354
355static inline void exynos4_tick_set_mode(enum clock_event_mode mode,
356 struct clock_event_device *evt)
357{
Marc Zyngiere700e412011-11-03 11:13:12 +0900358 struct mct_clock_event_device *mevt = this_cpu_ptr(&percpu_mct_tick);
Changhwan Youn4d2e4d72012-03-09 15:09:21 -0800359 unsigned long cycles_per_jiffy;
Changhwan Youn30d8bea2011-03-11 10:39:57 +0900360
361 exynos4_mct_tick_stop(mevt);
362
363 switch (mode) {
364 case CLOCK_EVT_MODE_PERIODIC:
Changhwan Youn4d2e4d72012-03-09 15:09:21 -0800365 cycles_per_jiffy =
366 (((unsigned long long) NSEC_PER_SEC / HZ * evt->mult) >> evt->shift);
367 exynos4_mct_tick_start(cycles_per_jiffy, mevt);
Changhwan Youn30d8bea2011-03-11 10:39:57 +0900368 break;
369
370 case CLOCK_EVT_MODE_ONESHOT:
371 case CLOCK_EVT_MODE_UNUSED:
372 case CLOCK_EVT_MODE_SHUTDOWN:
373 case CLOCK_EVT_MODE_RESUME:
374 break;
375 }
376}
377
Changhwan Younc8987472011-10-04 17:09:26 +0900378static int exynos4_mct_tick_clear(struct mct_clock_event_device *mevt)
Changhwan Youn30d8bea2011-03-11 10:39:57 +0900379{
Stephen Boydee98d272013-02-15 16:40:51 -0800380 struct clock_event_device *evt = &mevt->evt;
Changhwan Youn30d8bea2011-03-11 10:39:57 +0900381
382 /*
383 * This is for supporting oneshot mode.
384 * Mct would generate interrupt periodically
385 * without explicit stopping.
386 */
387 if (evt->mode != CLOCK_EVT_MODE_PERIODIC)
388 exynos4_mct_tick_stop(mevt);
389
390 /* Clear the MCT tick interrupt */
Thomas Abrahama1ba7a72013-03-09 16:01:47 +0900391 if (__raw_readl(reg_base + mevt->base + MCT_L_INT_CSTAT_OFFSET) & 1) {
Changhwan Youn3a062282011-10-04 17:02:58 +0900392 exynos4_mct_write(0x1, mevt->base + MCT_L_INT_CSTAT_OFFSET);
393 return 1;
394 } else {
395 return 0;
396 }
397}
398
399static irqreturn_t exynos4_mct_tick_isr(int irq, void *dev_id)
400{
401 struct mct_clock_event_device *mevt = dev_id;
Stephen Boydee98d272013-02-15 16:40:51 -0800402 struct clock_event_device *evt = &mevt->evt;
Changhwan Youn3a062282011-10-04 17:02:58 +0900403
404 exynos4_mct_tick_clear(mevt);
Changhwan Youn30d8bea2011-03-11 10:39:57 +0900405
406 evt->event_handler(evt);
407
408 return IRQ_HANDLED;
409}
410
Paul Gortmaker8c37bb32013-06-19 11:32:08 -0400411static int exynos4_local_timer_setup(struct clock_event_device *evt)
Changhwan Youn30d8bea2011-03-11 10:39:57 +0900412{
Marc Zyngiere700e412011-11-03 11:13:12 +0900413 struct mct_clock_event_device *mevt;
Changhwan Youn30d8bea2011-03-11 10:39:57 +0900414 unsigned int cpu = smp_processor_id();
415
Stephen Boydee98d272013-02-15 16:40:51 -0800416 mevt = container_of(evt, struct mct_clock_event_device, evt);
Changhwan Youn30d8bea2011-03-11 10:39:57 +0900417
Marc Zyngiere700e412011-11-03 11:13:12 +0900418 mevt->base = EXYNOS4_MCT_L_BASE(cpu);
Dan Carpenter09e15172014-03-01 16:57:14 +0300419 snprintf(mevt->name, sizeof(mevt->name), "mct_tick%d", cpu);
Changhwan Youn30d8bea2011-03-11 10:39:57 +0900420
Marc Zyngiere700e412011-11-03 11:13:12 +0900421 evt->name = mevt->name;
Changhwan Youn30d8bea2011-03-11 10:39:57 +0900422 evt->cpumask = cpumask_of(cpu);
423 evt->set_next_event = exynos4_tick_set_next_event;
424 evt->set_mode = exynos4_tick_set_mode;
425 evt->features = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT;
426 evt->rating = 450;
Shawn Guo838a2ae2013-01-12 11:50:05 +0000427 clockevents_config_and_register(evt, clk_rate / (TICK_BASE_CNT + 1),
428 0xf, 0x7fffffff);
Changhwan Youn30d8bea2011-03-11 10:39:57 +0900429
Changhwan Youn4d2e4d72012-03-09 15:09:21 -0800430 exynos4_mct_write(TICK_BASE_CNT, mevt->base + MCT_L_TCNTB_OFFSET);
Changhwan Youn30d8bea2011-03-11 10:39:57 +0900431
Changhwan Youn3a062282011-10-04 17:02:58 +0900432 if (mct_int_type == MCT_INT_SPI) {
Chander Kashyap7114cd72013-06-19 00:29:35 +0900433 evt->irq = mct_irqs[MCT_L0_IRQ + cpu];
434 if (request_irq(evt->irq, exynos4_mct_tick_isr,
435 IRQF_TIMER | IRQF_NOBALANCING,
436 evt->name, mevt)) {
437 pr_err("exynos-mct: cannot register IRQ %d\n",
438 evt->irq);
439 return -EIO;
Changhwan Youn3a062282011-10-04 17:02:58 +0900440 }
Changhwan Youn30d8bea2011-03-11 10:39:57 +0900441 } else {
Thomas Abrahamc371dc62013-03-09 16:01:50 +0900442 enable_percpu_irq(mct_irqs[MCT_L0_IRQ], 0);
Changhwan Youn30d8bea2011-03-11 10:39:57 +0900443 }
Kukjin Kim4d487d72011-08-24 16:07:39 +0900444
445 return 0;
Changhwan Youn30d8bea2011-03-11 10:39:57 +0900446}
447
Marc Zyngiera8cb6042012-01-10 19:44:19 +0000448static void exynos4_local_timer_stop(struct clock_event_device *evt)
Changhwan Youn30d8bea2011-03-11 10:39:57 +0900449{
Marc Zyngier28af6902011-07-22 12:52:37 +0100450 evt->set_mode(CLOCK_EVT_MODE_UNUSED, evt);
Marc Zyngiere700e412011-11-03 11:13:12 +0900451 if (mct_int_type == MCT_INT_SPI)
Chander Kashyap7114cd72013-06-19 00:29:35 +0900452 free_irq(evt->irq, this_cpu_ptr(&percpu_mct_tick));
Marc Zyngiere700e412011-11-03 11:13:12 +0900453 else
Thomas Abrahamc371dc62013-03-09 16:01:50 +0900454 disable_percpu_irq(mct_irqs[MCT_L0_IRQ]);
Changhwan Youn30d8bea2011-03-11 10:39:57 +0900455}
Marc Zyngiera8cb6042012-01-10 19:44:19 +0000456
Olof Johansson47dcd352013-07-23 14:51:34 -0700457static int exynos4_mct_cpu_notify(struct notifier_block *self,
Stephen Boydee98d272013-02-15 16:40:51 -0800458 unsigned long action, void *hcpu)
459{
460 struct mct_clock_event_device *mevt;
Tomasz Figa5df718d2013-09-25 12:00:59 +0200461 unsigned int cpu;
Stephen Boydee98d272013-02-15 16:40:51 -0800462
463 /*
464 * Grab cpu pointer in each case to avoid spurious
465 * preemptible warnings
466 */
467 switch (action & ~CPU_TASKS_FROZEN) {
468 case CPU_STARTING:
469 mevt = this_cpu_ptr(&percpu_mct_tick);
470 exynos4_local_timer_setup(&mevt->evt);
471 break;
Tomasz Figa5df718d2013-09-25 12:00:59 +0200472 case CPU_ONLINE:
473 cpu = (unsigned long)hcpu;
474 if (mct_int_type == MCT_INT_SPI)
475 irq_set_affinity(mct_irqs[MCT_L0_IRQ + cpu],
476 cpumask_of(cpu));
477 break;
Stephen Boydee98d272013-02-15 16:40:51 -0800478 case CPU_DYING:
479 mevt = this_cpu_ptr(&percpu_mct_tick);
480 exynos4_local_timer_stop(&mevt->evt);
481 break;
482 }
483
484 return NOTIFY_OK;
485}
486
Olof Johansson47dcd352013-07-23 14:51:34 -0700487static struct notifier_block exynos4_mct_cpu_nb = {
Stephen Boydee98d272013-02-15 16:40:51 -0800488 .notifier_call = exynos4_mct_cpu_notify,
Marc Zyngiera8cb6042012-01-10 19:44:19 +0000489};
Changhwan Youn30d8bea2011-03-11 10:39:57 +0900490
Arnd Bergmann19ce4f42013-04-09 22:24:06 +0200491static void __init exynos4_timer_resources(struct device_node *np, void __iomem *base)
Changhwan Youn30d8bea2011-03-11 10:39:57 +0900492{
Stephen Boydee98d272013-02-15 16:40:51 -0800493 int err;
494 struct mct_clock_event_device *mevt = this_cpu_ptr(&percpu_mct_tick);
Thomas Abrahamca9048e2013-03-09 17:10:37 +0900495 struct clk *mct_clk, *tick_clk;
Changhwan Youn30d8bea2011-03-11 10:39:57 +0900496
Thomas Abraham415ac2e2013-03-09 17:10:31 +0900497 tick_clk = np ? of_clk_get_by_name(np, "fin_pll") :
498 clk_get(NULL, "fin_pll");
499 if (IS_ERR(tick_clk))
500 panic("%s: unable to determine tick clock rate\n", __func__);
501 clk_rate = clk_get_rate(tick_clk);
Marc Zyngiere700e412011-11-03 11:13:12 +0900502
Thomas Abrahamca9048e2013-03-09 17:10:37 +0900503 mct_clk = np ? of_clk_get_by_name(np, "mct") : clk_get(NULL, "mct");
504 if (IS_ERR(mct_clk))
505 panic("%s: unable to retrieve mct clock instance\n", __func__);
506 clk_prepare_enable(mct_clk);
Marc Zyngiere700e412011-11-03 11:13:12 +0900507
Arnd Bergmann228e3022013-04-09 22:07:37 +0200508 reg_base = base;
Thomas Abraham36ba5d52013-03-09 16:01:52 +0900509 if (!reg_base)
510 panic("%s: unable to ioremap mct address space\n", __func__);
Thomas Abrahama1ba7a72013-03-09 16:01:47 +0900511
Marc Zyngiere700e412011-11-03 11:13:12 +0900512 if (mct_int_type == MCT_INT_PPI) {
Marc Zyngiere700e412011-11-03 11:13:12 +0900513
Thomas Abrahamc371dc62013-03-09 16:01:50 +0900514 err = request_percpu_irq(mct_irqs[MCT_L0_IRQ],
Marc Zyngiere700e412011-11-03 11:13:12 +0900515 exynos4_mct_tick_isr, "MCT",
516 &percpu_mct_tick);
517 WARN(err, "MCT: can't request IRQ %d (%d)\n",
Thomas Abrahamc371dc62013-03-09 16:01:50 +0900518 mct_irqs[MCT_L0_IRQ], err);
Tomasz Figa5df718d2013-09-25 12:00:59 +0200519 } else {
520 irq_set_affinity(mct_irqs[MCT_L0_IRQ], cpumask_of(0));
Marc Zyngiere700e412011-11-03 11:13:12 +0900521 }
Marc Zyngiera8cb6042012-01-10 19:44:19 +0000522
Stephen Boydee98d272013-02-15 16:40:51 -0800523 err = register_cpu_notifier(&exynos4_mct_cpu_nb);
524 if (err)
525 goto out_irq;
526
527 /* Immediately configure the timer on the boot CPU */
528 exynos4_local_timer_setup(&mevt->evt);
529 return;
530
531out_irq:
532 free_percpu_irq(mct_irqs[MCT_L0_IRQ], &percpu_mct_tick);
Changhwan Youn30d8bea2011-03-11 10:39:57 +0900533}
534
Arnd Bergmann034c0972013-04-10 11:35:29 +0200535void __init mct_init(void __iomem *base, int irq_g0, int irq_l0, int irq_l1)
Changhwan Youn30d8bea2011-03-11 10:39:57 +0900536{
Arnd Bergmann034c0972013-04-10 11:35:29 +0200537 mct_irqs[MCT_G0_IRQ] = irq_g0;
538 mct_irqs[MCT_L0_IRQ] = irq_l0;
539 mct_irqs[MCT_L1_IRQ] = irq_l1;
540 mct_int_type = MCT_INT_SPI;
Kukjin Kim2edb36c2012-11-15 15:48:56 +0900541
Arnd Bergmann034c0972013-04-10 11:35:29 +0200542 exynos4_timer_resources(NULL, base);
Changhwan Youn30d8bea2011-03-11 10:39:57 +0900543 exynos4_clocksource_init();
544 exynos4_clockevent_init();
545}
Arnd Bergmann228e3022013-04-09 22:07:37 +0200546
547static void __init mct_init_dt(struct device_node *np, unsigned int int_type)
548{
549 u32 nr_irqs, i;
550
551 mct_int_type = int_type;
552
553 /* This driver uses only one global timer interrupt */
554 mct_irqs[MCT_G0_IRQ] = irq_of_parse_and_map(np, MCT_G0_IRQ);
555
556 /*
557 * Find out the number of local irqs specified. The local
558 * timer irqs are specified after the four global timer
559 * irqs are specified.
560 */
Arnd Bergmannf4636d02013-04-19 22:00:04 +0200561#ifdef CONFIG_OF
Arnd Bergmann228e3022013-04-09 22:07:37 +0200562 nr_irqs = of_irq_count(np);
Arnd Bergmannf4636d02013-04-19 22:00:04 +0200563#else
564 nr_irqs = 0;
565#endif
Arnd Bergmann228e3022013-04-09 22:07:37 +0200566 for (i = MCT_L0_IRQ; i < nr_irqs; i++)
567 mct_irqs[i] = irq_of_parse_and_map(np, i);
568
Arnd Bergmann19ce4f42013-04-09 22:24:06 +0200569 exynos4_timer_resources(np, of_iomap(np, 0));
Arnd Bergmann228e3022013-04-09 22:07:37 +0200570 exynos4_clocksource_init();
571 exynos4_clockevent_init();
572}
573
574
575static void __init mct_init_spi(struct device_node *np)
576{
577 return mct_init_dt(np, MCT_INT_SPI);
578}
579
580static void __init mct_init_ppi(struct device_node *np)
581{
582 return mct_init_dt(np, MCT_INT_PPI);
583}
584CLOCKSOURCE_OF_DECLARE(exynos4210, "samsung,exynos4210-mct", mct_init_spi);
585CLOCKSOURCE_OF_DECLARE(exynos4412, "samsung,exynos4412-mct", mct_init_ppi);