blob: f0a6de748faeee8acbb7d577d68b007b404b4598 [file] [log] [blame]
Thor Thayer71bcada2014-09-03 10:27:54 -05001/*
Thor Thayerc3eea192016-02-10 13:26:21 -06002 * Copyright Altera Corporation (C) 2014-2016. All rights reserved.
Thor Thayer71bcada2014-09-03 10:27:54 -05003 * Copyright 2011-2012 Calxeda, Inc.
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms and conditions of the GNU General Public License,
7 * version 2, as published by the Free Software Foundation.
8 *
9 * This program is distributed in the hope it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
12 * more details.
13 *
14 * You should have received a copy of the GNU General Public License along with
15 * this program. If not, see <http://www.gnu.org/licenses/>.
16 *
17 * Adapted from the highbank_mc_edac driver.
18 */
19
Thor Thayerc3eea192016-02-10 13:26:21 -060020#include <asm/cacheflush.h>
Thor Thayer71bcada2014-09-03 10:27:54 -050021#include <linux/ctype.h>
22#include <linux/edac.h>
Thor Thayerc3eea192016-02-10 13:26:21 -060023#include <linux/genalloc.h>
Thor Thayer71bcada2014-09-03 10:27:54 -050024#include <linux/interrupt.h>
25#include <linux/kernel.h>
26#include <linux/mfd/syscon.h>
Thor Thayer588cb032016-03-21 11:01:44 -050027#include <linux/of_address.h>
Thor Thayer71bcada2014-09-03 10:27:54 -050028#include <linux/of_platform.h>
29#include <linux/platform_device.h>
30#include <linux/regmap.h>
31#include <linux/types.h>
32#include <linux/uaccess.h>
33
Thor Thayer143f4a52015-06-04 09:28:46 -050034#include "altera_edac.h"
Thor Thayer71bcada2014-09-03 10:27:54 -050035#include "edac_core.h"
36#include "edac_module.h"
37
38#define EDAC_MOD_STR "altera_edac"
39#define EDAC_VERSION "1"
Thor Thayerc3eea192016-02-10 13:26:21 -060040#define EDAC_DEVICE "Altera"
Thor Thayer71bcada2014-09-03 10:27:54 -050041
Thor Thayer143f4a52015-06-04 09:28:46 -050042static const struct altr_sdram_prv_data c5_data = {
43 .ecc_ctrl_offset = CV_CTLCFG_OFST,
44 .ecc_ctl_en_mask = CV_CTLCFG_ECC_AUTO_EN,
45 .ecc_stat_offset = CV_DRAMSTS_OFST,
46 .ecc_stat_ce_mask = CV_DRAMSTS_SBEERR,
47 .ecc_stat_ue_mask = CV_DRAMSTS_DBEERR,
48 .ecc_saddr_offset = CV_ERRADDR_OFST,
Thor Thayer73bcc942015-06-04 09:28:47 -050049 .ecc_daddr_offset = CV_ERRADDR_OFST,
Thor Thayer143f4a52015-06-04 09:28:46 -050050 .ecc_cecnt_offset = CV_SBECOUNT_OFST,
51 .ecc_uecnt_offset = CV_DBECOUNT_OFST,
52 .ecc_irq_en_offset = CV_DRAMINTR_OFST,
53 .ecc_irq_en_mask = CV_DRAMINTR_INTREN,
54 .ecc_irq_clr_offset = CV_DRAMINTR_OFST,
55 .ecc_irq_clr_mask = (CV_DRAMINTR_INTRCLR | CV_DRAMINTR_INTREN),
56 .ecc_cnt_rst_offset = CV_DRAMINTR_OFST,
57 .ecc_cnt_rst_mask = CV_DRAMINTR_INTRCLR,
Thor Thayer143f4a52015-06-04 09:28:46 -050058 .ce_ue_trgr_offset = CV_CTLCFG_OFST,
59 .ce_set_mask = CV_CTLCFG_GEN_SB_ERR,
60 .ue_set_mask = CV_CTLCFG_GEN_DB_ERR,
Thor Thayer71bcada2014-09-03 10:27:54 -050061};
62
Thor Thayer73bcc942015-06-04 09:28:47 -050063static const struct altr_sdram_prv_data a10_data = {
64 .ecc_ctrl_offset = A10_ECCCTRL1_OFST,
65 .ecc_ctl_en_mask = A10_ECCCTRL1_ECC_EN,
66 .ecc_stat_offset = A10_INTSTAT_OFST,
67 .ecc_stat_ce_mask = A10_INTSTAT_SBEERR,
68 .ecc_stat_ue_mask = A10_INTSTAT_DBEERR,
69 .ecc_saddr_offset = A10_SERRADDR_OFST,
70 .ecc_daddr_offset = A10_DERRADDR_OFST,
71 .ecc_irq_en_offset = A10_ERRINTEN_OFST,
72 .ecc_irq_en_mask = A10_ECC_IRQ_EN_MASK,
73 .ecc_irq_clr_offset = A10_INTSTAT_OFST,
74 .ecc_irq_clr_mask = (A10_INTSTAT_SBEERR | A10_INTSTAT_DBEERR),
75 .ecc_cnt_rst_offset = A10_ECCCTRL1_OFST,
76 .ecc_cnt_rst_mask = A10_ECC_CNT_RESET_MASK,
Thor Thayer73bcc942015-06-04 09:28:47 -050077 .ce_ue_trgr_offset = A10_DIAGINTTEST_OFST,
78 .ce_set_mask = A10_DIAGINT_TSERRA_MASK,
79 .ue_set_mask = A10_DIAGINT_TDERRA_MASK,
Thor Thayer73bcc942015-06-04 09:28:47 -050080};
81
Thor Thayerc3eea192016-02-10 13:26:21 -060082/*********************** EDAC Memory Controller Functions ****************/
83
84/* The SDRAM controller uses the EDAC Memory Controller framework. */
85
Thor Thayer71bcada2014-09-03 10:27:54 -050086static irqreturn_t altr_sdram_mc_err_handler(int irq, void *dev_id)
87{
88 struct mem_ctl_info *mci = dev_id;
89 struct altr_sdram_mc_data *drvdata = mci->pvt_info;
Thor Thayer143f4a52015-06-04 09:28:46 -050090 const struct altr_sdram_prv_data *priv = drvdata->data;
Thor Thayer73bcc942015-06-04 09:28:47 -050091 u32 status, err_count = 1, err_addr;
Thor Thayer71bcada2014-09-03 10:27:54 -050092
Thor Thayer143f4a52015-06-04 09:28:46 -050093 regmap_read(drvdata->mc_vbase, priv->ecc_stat_offset, &status);
Thor Thayer71bcada2014-09-03 10:27:54 -050094
Thor Thayer143f4a52015-06-04 09:28:46 -050095 if (status & priv->ecc_stat_ue_mask) {
Thor Thayer73bcc942015-06-04 09:28:47 -050096 regmap_read(drvdata->mc_vbase, priv->ecc_daddr_offset,
97 &err_addr);
98 if (priv->ecc_uecnt_offset)
99 regmap_read(drvdata->mc_vbase, priv->ecc_uecnt_offset,
100 &err_count);
Thor Thayer71bcada2014-09-03 10:27:54 -0500101 panic("\nEDAC: [%d Uncorrectable errors @ 0x%08X]\n",
102 err_count, err_addr);
103 }
Thor Thayer143f4a52015-06-04 09:28:46 -0500104 if (status & priv->ecc_stat_ce_mask) {
Thor Thayer73bcc942015-06-04 09:28:47 -0500105 regmap_read(drvdata->mc_vbase, priv->ecc_saddr_offset,
106 &err_addr);
107 if (priv->ecc_uecnt_offset)
108 regmap_read(drvdata->mc_vbase, priv->ecc_cecnt_offset,
109 &err_count);
Thor Thayer71bcada2014-09-03 10:27:54 -0500110 edac_mc_handle_error(HW_EVENT_ERR_CORRECTED, mci, err_count,
111 err_addr >> PAGE_SHIFT,
112 err_addr & ~PAGE_MASK, 0,
113 0, 0, -1, mci->ctl_name, "");
Thor Thayer73bcc942015-06-04 09:28:47 -0500114 /* Clear IRQ to resume */
115 regmap_write(drvdata->mc_vbase, priv->ecc_irq_clr_offset,
116 priv->ecc_irq_clr_mask);
117
118 return IRQ_HANDLED;
Thor Thayer71bcada2014-09-03 10:27:54 -0500119 }
Thor Thayer73bcc942015-06-04 09:28:47 -0500120 return IRQ_NONE;
Thor Thayer71bcada2014-09-03 10:27:54 -0500121}
122
Thor Thayer71bcada2014-09-03 10:27:54 -0500123static ssize_t altr_sdr_mc_err_inject_write(struct file *file,
124 const char __user *data,
125 size_t count, loff_t *ppos)
126{
127 struct mem_ctl_info *mci = file->private_data;
128 struct altr_sdram_mc_data *drvdata = mci->pvt_info;
Thor Thayer143f4a52015-06-04 09:28:46 -0500129 const struct altr_sdram_prv_data *priv = drvdata->data;
Thor Thayer71bcada2014-09-03 10:27:54 -0500130 u32 *ptemp;
131 dma_addr_t dma_handle;
132 u32 reg, read_reg;
133
134 ptemp = dma_alloc_coherent(mci->pdev, 16, &dma_handle, GFP_KERNEL);
135 if (!ptemp) {
136 dma_free_coherent(mci->pdev, 16, ptemp, dma_handle);
137 edac_printk(KERN_ERR, EDAC_MC,
138 "Inject: Buffer Allocation error\n");
139 return -ENOMEM;
140 }
141
Thor Thayer143f4a52015-06-04 09:28:46 -0500142 regmap_read(drvdata->mc_vbase, priv->ce_ue_trgr_offset,
143 &read_reg);
144 read_reg &= ~(priv->ce_set_mask | priv->ue_set_mask);
Thor Thayer71bcada2014-09-03 10:27:54 -0500145
146 /* Error are injected by writing a word while the SBE or DBE
147 * bit in the CTLCFG register is set. Reading the word will
148 * trigger the SBE or DBE error and the corresponding IRQ.
149 */
150 if (count == 3) {
151 edac_printk(KERN_ALERT, EDAC_MC,
152 "Inject Double bit error\n");
Thor Thayer143f4a52015-06-04 09:28:46 -0500153 regmap_write(drvdata->mc_vbase, priv->ce_ue_trgr_offset,
154 (read_reg | priv->ue_set_mask));
Thor Thayer71bcada2014-09-03 10:27:54 -0500155 } else {
156 edac_printk(KERN_ALERT, EDAC_MC,
157 "Inject Single bit error\n");
Thor Thayer143f4a52015-06-04 09:28:46 -0500158 regmap_write(drvdata->mc_vbase, priv->ce_ue_trgr_offset,
159 (read_reg | priv->ce_set_mask));
Thor Thayer71bcada2014-09-03 10:27:54 -0500160 }
161
162 ptemp[0] = 0x5A5A5A5A;
163 ptemp[1] = 0xA5A5A5A5;
164
165 /* Clear the error injection bits */
Thor Thayer143f4a52015-06-04 09:28:46 -0500166 regmap_write(drvdata->mc_vbase, priv->ce_ue_trgr_offset, read_reg);
Thor Thayer71bcada2014-09-03 10:27:54 -0500167 /* Ensure it has been written out */
168 wmb();
169
170 /*
171 * To trigger the error, we need to read the data back
172 * (the data was written with errors above).
173 * The ACCESS_ONCE macros and printk are used to prevent the
174 * the compiler optimizing these reads out.
175 */
176 reg = ACCESS_ONCE(ptemp[0]);
177 read_reg = ACCESS_ONCE(ptemp[1]);
178 /* Force Read */
179 rmb();
180
181 edac_printk(KERN_ALERT, EDAC_MC, "Read Data [0x%X, 0x%X]\n",
182 reg, read_reg);
183
184 dma_free_coherent(mci->pdev, 16, ptemp, dma_handle);
185
186 return count;
187}
188
189static const struct file_operations altr_sdr_mc_debug_inject_fops = {
190 .open = simple_open,
191 .write = altr_sdr_mc_err_inject_write,
192 .llseek = generic_file_llseek,
193};
194
195static void altr_sdr_mc_create_debugfs_nodes(struct mem_ctl_info *mci)
196{
Borislav Petkovbba3b312015-09-22 12:27:29 +0200197 if (!IS_ENABLED(CONFIG_EDAC_DEBUG))
198 return;
199
200 if (!mci->debugfs)
201 return;
202
203 edac_debugfs_create_file("inject_ctrl", S_IWUSR, mci->debugfs, mci,
204 &altr_sdr_mc_debug_inject_fops);
Thor Thayer71bcada2014-09-03 10:27:54 -0500205}
Thor Thayer71bcada2014-09-03 10:27:54 -0500206
Thor Thayerf9ae4872015-06-04 09:28:45 -0500207/* Get total memory size from Open Firmware DTB */
208static unsigned long get_total_mem(void)
Thor Thayer71bcada2014-09-03 10:27:54 -0500209{
Thor Thayerf9ae4872015-06-04 09:28:45 -0500210 struct device_node *np = NULL;
211 const unsigned int *reg, *reg_end;
212 int len, sw, aw;
213 unsigned long start, size, total_mem = 0;
Thor Thayer71bcada2014-09-03 10:27:54 -0500214
Thor Thayerf9ae4872015-06-04 09:28:45 -0500215 for_each_node_by_type(np, "memory") {
216 aw = of_n_addr_cells(np);
217 sw = of_n_size_cells(np);
218 reg = (const unsigned int *)of_get_property(np, "reg", &len);
219 reg_end = reg + (len / sizeof(u32));
Thor Thayer71bcada2014-09-03 10:27:54 -0500220
Thor Thayerf9ae4872015-06-04 09:28:45 -0500221 total_mem = 0;
222 do {
223 start = of_read_number(reg, aw);
224 reg += aw;
225 size = of_read_number(reg, sw);
226 reg += sw;
227 total_mem += size;
228 } while (reg < reg_end);
229 }
230 edac_dbg(0, "total_mem 0x%lx\n", total_mem);
231 return total_mem;
Thor Thayer71bcada2014-09-03 10:27:54 -0500232}
233
Thor Thayer143f4a52015-06-04 09:28:46 -0500234static const struct of_device_id altr_sdram_ctrl_of_match[] = {
235 { .compatible = "altr,sdram-edac", .data = (void *)&c5_data},
Thor Thayer73bcc942015-06-04 09:28:47 -0500236 { .compatible = "altr,sdram-edac-a10", .data = (void *)&a10_data},
Thor Thayer143f4a52015-06-04 09:28:46 -0500237 {},
238};
239MODULE_DEVICE_TABLE(of, altr_sdram_ctrl_of_match);
240
Thor Thayer73bcc942015-06-04 09:28:47 -0500241static int a10_init(struct regmap *mc_vbase)
242{
243 if (regmap_update_bits(mc_vbase, A10_INTMODE_OFST,
244 A10_INTMODE_SB_INT, A10_INTMODE_SB_INT)) {
245 edac_printk(KERN_ERR, EDAC_MC,
246 "Error setting SB IRQ mode\n");
247 return -ENODEV;
248 }
249
250 if (regmap_write(mc_vbase, A10_SERRCNTREG_OFST, 1)) {
251 edac_printk(KERN_ERR, EDAC_MC,
252 "Error setting trigger count\n");
253 return -ENODEV;
254 }
255
256 return 0;
257}
258
259static int a10_unmask_irq(struct platform_device *pdev, u32 mask)
260{
261 void __iomem *sm_base;
262 int ret = 0;
263
264 if (!request_mem_region(A10_SYMAN_INTMASK_CLR, sizeof(u32),
265 dev_name(&pdev->dev))) {
266 edac_printk(KERN_ERR, EDAC_MC,
267 "Unable to request mem region\n");
268 return -EBUSY;
269 }
270
271 sm_base = ioremap(A10_SYMAN_INTMASK_CLR, sizeof(u32));
272 if (!sm_base) {
273 edac_printk(KERN_ERR, EDAC_MC,
274 "Unable to ioremap device\n");
275
276 ret = -ENOMEM;
277 goto release;
278 }
279
280 iowrite32(mask, sm_base);
281
282 iounmap(sm_base);
283
284release:
285 release_mem_region(A10_SYMAN_INTMASK_CLR, sizeof(u32));
286
287 return ret;
288}
289
Thor Thayer71bcada2014-09-03 10:27:54 -0500290static int altr_sdram_probe(struct platform_device *pdev)
291{
Thor Thayer143f4a52015-06-04 09:28:46 -0500292 const struct of_device_id *id;
Thor Thayer71bcada2014-09-03 10:27:54 -0500293 struct edac_mc_layer layers[2];
294 struct mem_ctl_info *mci;
295 struct altr_sdram_mc_data *drvdata;
Thor Thayer143f4a52015-06-04 09:28:46 -0500296 const struct altr_sdram_prv_data *priv;
Thor Thayer71bcada2014-09-03 10:27:54 -0500297 struct regmap *mc_vbase;
298 struct dimm_info *dimm;
Thor Thayer143f4a52015-06-04 09:28:46 -0500299 u32 read_reg;
Thor Thayer73bcc942015-06-04 09:28:47 -0500300 int irq, irq2, res = 0;
301 unsigned long mem_size, irqflags = 0;
Thor Thayer71bcada2014-09-03 10:27:54 -0500302
Thor Thayer143f4a52015-06-04 09:28:46 -0500303 id = of_match_device(altr_sdram_ctrl_of_match, &pdev->dev);
304 if (!id)
305 return -ENODEV;
306
Thor Thayer71bcada2014-09-03 10:27:54 -0500307 /* Grab the register range from the sdr controller in device tree */
308 mc_vbase = syscon_regmap_lookup_by_phandle(pdev->dev.of_node,
309 "altr,sdr-syscon");
310 if (IS_ERR(mc_vbase)) {
311 edac_printk(KERN_ERR, EDAC_MC,
312 "regmap for altr,sdr-syscon lookup failed.\n");
313 return -ENODEV;
314 }
315
Thor Thayer143f4a52015-06-04 09:28:46 -0500316 /* Check specific dependencies for the module */
317 priv = of_match_node(altr_sdram_ctrl_of_match,
318 pdev->dev.of_node)->data;
319
320 /* Validate the SDRAM controller has ECC enabled */
321 if (regmap_read(mc_vbase, priv->ecc_ctrl_offset, &read_reg) ||
322 ((read_reg & priv->ecc_ctl_en_mask) != priv->ecc_ctl_en_mask)) {
Thor Thayer71bcada2014-09-03 10:27:54 -0500323 edac_printk(KERN_ERR, EDAC_MC,
324 "No ECC/ECC disabled [0x%08X]\n", read_reg);
325 return -ENODEV;
326 }
327
328 /* Grab memory size from device tree. */
Thor Thayerf9ae4872015-06-04 09:28:45 -0500329 mem_size = get_total_mem();
Thor Thayer71bcada2014-09-03 10:27:54 -0500330 if (!mem_size) {
Thor Thayerf9ae4872015-06-04 09:28:45 -0500331 edac_printk(KERN_ERR, EDAC_MC, "Unable to calculate memory size\n");
Thor Thayer71bcada2014-09-03 10:27:54 -0500332 return -ENODEV;
333 }
334
Thor Thayer143f4a52015-06-04 09:28:46 -0500335 /* Ensure the SDRAM Interrupt is disabled */
336 if (regmap_update_bits(mc_vbase, priv->ecc_irq_en_offset,
337 priv->ecc_irq_en_mask, 0)) {
Thor Thayer71bcada2014-09-03 10:27:54 -0500338 edac_printk(KERN_ERR, EDAC_MC,
Thor Thayer143f4a52015-06-04 09:28:46 -0500339 "Error disabling SDRAM ECC IRQ\n");
340 return -ENODEV;
341 }
342
343 /* Toggle to clear the SDRAM Error count */
344 if (regmap_update_bits(mc_vbase, priv->ecc_cnt_rst_offset,
345 priv->ecc_cnt_rst_mask,
346 priv->ecc_cnt_rst_mask)) {
347 edac_printk(KERN_ERR, EDAC_MC,
348 "Error clearing SDRAM ECC count\n");
349 return -ENODEV;
350 }
351
352 if (regmap_update_bits(mc_vbase, priv->ecc_cnt_rst_offset,
353 priv->ecc_cnt_rst_mask, 0)) {
354 edac_printk(KERN_ERR, EDAC_MC,
355 "Error clearing SDRAM ECC count\n");
Thor Thayer71bcada2014-09-03 10:27:54 -0500356 return -ENODEV;
357 }
358
359 irq = platform_get_irq(pdev, 0);
360 if (irq < 0) {
361 edac_printk(KERN_ERR, EDAC_MC,
362 "No irq %d in DT\n", irq);
363 return -ENODEV;
364 }
365
Thor Thayer73bcc942015-06-04 09:28:47 -0500366 /* Arria10 has a 2nd IRQ */
367 irq2 = platform_get_irq(pdev, 1);
368
Thor Thayer71bcada2014-09-03 10:27:54 -0500369 layers[0].type = EDAC_MC_LAYER_CHIP_SELECT;
370 layers[0].size = 1;
371 layers[0].is_virt_csrow = true;
372 layers[1].type = EDAC_MC_LAYER_CHANNEL;
373 layers[1].size = 1;
374 layers[1].is_virt_csrow = false;
375 mci = edac_mc_alloc(0, ARRAY_SIZE(layers), layers,
376 sizeof(struct altr_sdram_mc_data));
377 if (!mci)
378 return -ENOMEM;
379
380 mci->pdev = &pdev->dev;
381 drvdata = mci->pvt_info;
382 drvdata->mc_vbase = mc_vbase;
Thor Thayer143f4a52015-06-04 09:28:46 -0500383 drvdata->data = priv;
Thor Thayer71bcada2014-09-03 10:27:54 -0500384 platform_set_drvdata(pdev, mci);
385
386 if (!devres_open_group(&pdev->dev, NULL, GFP_KERNEL)) {
Thor Thayer143f4a52015-06-04 09:28:46 -0500387 edac_printk(KERN_ERR, EDAC_MC,
388 "Unable to get managed device resource\n");
Thor Thayer71bcada2014-09-03 10:27:54 -0500389 res = -ENOMEM;
390 goto free;
391 }
392
393 mci->mtype_cap = MEM_FLAG_DDR3;
394 mci->edac_ctl_cap = EDAC_FLAG_NONE | EDAC_FLAG_SECDED;
395 mci->edac_cap = EDAC_FLAG_SECDED;
396 mci->mod_name = EDAC_MOD_STR;
397 mci->mod_ver = EDAC_VERSION;
398 mci->ctl_name = dev_name(&pdev->dev);
399 mci->scrub_mode = SCRUB_SW_SRC;
400 mci->dev_name = dev_name(&pdev->dev);
401
402 dimm = *mci->dimms;
403 dimm->nr_pages = ((mem_size - 1) >> PAGE_SHIFT) + 1;
404 dimm->grain = 8;
405 dimm->dtype = DEV_X8;
406 dimm->mtype = MEM_DDR3;
407 dimm->edac_mode = EDAC_SECDED;
408
409 res = edac_mc_add_mc(mci);
410 if (res < 0)
411 goto err;
412
Thor Thayer73bcc942015-06-04 09:28:47 -0500413 /* Only the Arria10 has separate IRQs */
414 if (irq2 > 0) {
415 /* Arria10 specific initialization */
416 res = a10_init(mc_vbase);
417 if (res < 0)
418 goto err2;
419
420 res = devm_request_irq(&pdev->dev, irq2,
421 altr_sdram_mc_err_handler,
422 IRQF_SHARED, dev_name(&pdev->dev), mci);
423 if (res < 0) {
424 edac_mc_printk(mci, KERN_ERR,
425 "Unable to request irq %d\n", irq2);
426 res = -ENODEV;
427 goto err2;
428 }
429
430 res = a10_unmask_irq(pdev, A10_DDR0_IRQ_MASK);
431 if (res < 0)
432 goto err2;
433
434 irqflags = IRQF_SHARED;
435 }
436
Thor Thayer71bcada2014-09-03 10:27:54 -0500437 res = devm_request_irq(&pdev->dev, irq, altr_sdram_mc_err_handler,
Thor Thayer73bcc942015-06-04 09:28:47 -0500438 irqflags, dev_name(&pdev->dev), mci);
Thor Thayer71bcada2014-09-03 10:27:54 -0500439 if (res < 0) {
440 edac_mc_printk(mci, KERN_ERR,
441 "Unable to request irq %d\n", irq);
442 res = -ENODEV;
443 goto err2;
444 }
445
Thor Thayer143f4a52015-06-04 09:28:46 -0500446 /* Infrastructure ready - enable the IRQ */
447 if (regmap_update_bits(drvdata->mc_vbase, priv->ecc_irq_en_offset,
448 priv->ecc_irq_en_mask, priv->ecc_irq_en_mask)) {
Thor Thayer71bcada2014-09-03 10:27:54 -0500449 edac_mc_printk(mci, KERN_ERR,
450 "Error enabling SDRAM ECC IRQ\n");
451 res = -ENODEV;
452 goto err2;
453 }
454
455 altr_sdr_mc_create_debugfs_nodes(mci);
456
457 devres_close_group(&pdev->dev, NULL);
458
459 return 0;
460
461err2:
462 edac_mc_del_mc(&pdev->dev);
463err:
464 devres_release_group(&pdev->dev, NULL);
465free:
466 edac_mc_free(mci);
467 edac_printk(KERN_ERR, EDAC_MC,
468 "EDAC Probe Failed; Error %d\n", res);
469
470 return res;
471}
472
473static int altr_sdram_remove(struct platform_device *pdev)
474{
475 struct mem_ctl_info *mci = platform_get_drvdata(pdev);
476
477 edac_mc_del_mc(&pdev->dev);
478 edac_mc_free(mci);
479 platform_set_drvdata(pdev, NULL);
480
481 return 0;
482}
483
Alan Tull6f2b6422015-06-05 08:49:15 -0500484/*
485 * If you want to suspend, need to disable EDAC by removing it
486 * from the device tree or defconfig.
487 */
488#ifdef CONFIG_PM
489static int altr_sdram_prepare(struct device *dev)
490{
491 pr_err("Suspend not allowed when EDAC is enabled.\n");
492
493 return -EPERM;
494}
495
496static const struct dev_pm_ops altr_sdram_pm_ops = {
497 .prepare = altr_sdram_prepare,
498};
499#endif
500
Thor Thayer71bcada2014-09-03 10:27:54 -0500501static struct platform_driver altr_sdram_edac_driver = {
502 .probe = altr_sdram_probe,
503 .remove = altr_sdram_remove,
504 .driver = {
505 .name = "altr_sdram_edac",
Alan Tull6f2b6422015-06-05 08:49:15 -0500506#ifdef CONFIG_PM
507 .pm = &altr_sdram_pm_ops,
508#endif
Thor Thayer71bcada2014-09-03 10:27:54 -0500509 .of_match_table = altr_sdram_ctrl_of_match,
510 },
511};
512
513module_platform_driver(altr_sdram_edac_driver);
514
Thor Thayerc3eea192016-02-10 13:26:21 -0600515/************************* EDAC Parent Probe *************************/
516
517static const struct of_device_id altr_edac_device_of_match[];
518
519static const struct of_device_id altr_edac_of_match[] = {
520 { .compatible = "altr,socfpga-ecc-manager" },
521 {},
522};
523MODULE_DEVICE_TABLE(of, altr_edac_of_match);
524
525static int altr_edac_probe(struct platform_device *pdev)
526{
527 of_platform_populate(pdev->dev.of_node, altr_edac_device_of_match,
528 NULL, &pdev->dev);
529 return 0;
530}
531
532static struct platform_driver altr_edac_driver = {
533 .probe = altr_edac_probe,
534 .driver = {
535 .name = "socfpga_ecc_manager",
536 .of_match_table = altr_edac_of_match,
537 },
538};
539module_platform_driver(altr_edac_driver);
540
541/************************* EDAC Device Functions *************************/
542
543/*
544 * EDAC Device Functions (shared between various IPs).
545 * The discrete memories use the EDAC Device framework. The probe
546 * and error handling functions are very similar between memories
547 * so they are shared. The memory allocation and freeing for EDAC
548 * trigger testing are different for each memory.
549 */
550
551const struct edac_device_prv_data ocramecc_data;
552const struct edac_device_prv_data l2ecc_data;
Thor Thayer588cb032016-03-21 11:01:44 -0500553const struct edac_device_prv_data a10_l2ecc_data;
Thor Thayerc3eea192016-02-10 13:26:21 -0600554
Thor Thayerc3eea192016-02-10 13:26:21 -0600555static irqreturn_t altr_edac_device_handler(int irq, void *dev_id)
556{
557 irqreturn_t ret_value = IRQ_NONE;
558 struct edac_device_ctl_info *dci = dev_id;
559 struct altr_edac_device_dev *drvdata = dci->pvt_info;
560 const struct edac_device_prv_data *priv = drvdata->data;
561
562 if (irq == drvdata->sb_irq) {
563 if (priv->ce_clear_mask)
564 writel(priv->ce_clear_mask, drvdata->base);
565 edac_device_handle_ce(dci, 0, 0, drvdata->edac_dev_name);
566 ret_value = IRQ_HANDLED;
567 } else if (irq == drvdata->db_irq) {
568 if (priv->ue_clear_mask)
569 writel(priv->ue_clear_mask, drvdata->base);
570 edac_device_handle_ue(dci, 0, 0, drvdata->edac_dev_name);
571 panic("\nEDAC:ECC_DEVICE[Uncorrectable errors]\n");
572 ret_value = IRQ_HANDLED;
573 } else {
574 WARN_ON(1);
575 }
576
577 return ret_value;
578}
579
580static ssize_t altr_edac_device_trig(struct file *file,
581 const char __user *user_buf,
582 size_t count, loff_t *ppos)
583
584{
585 u32 *ptemp, i, error_mask;
586 int result = 0;
587 u8 trig_type;
588 unsigned long flags;
589 struct edac_device_ctl_info *edac_dci = file->private_data;
590 struct altr_edac_device_dev *drvdata = edac_dci->pvt_info;
591 const struct edac_device_prv_data *priv = drvdata->data;
592 void *generic_ptr = edac_dci->dev;
593
594 if (!user_buf || get_user(trig_type, user_buf))
595 return -EFAULT;
596
597 if (!priv->alloc_mem)
598 return -ENOMEM;
599
600 /*
601 * Note that generic_ptr is initialized to the device * but in
602 * some alloc_functions, this is overridden and returns data.
603 */
604 ptemp = priv->alloc_mem(priv->trig_alloc_sz, &generic_ptr);
605 if (!ptemp) {
606 edac_printk(KERN_ERR, EDAC_DEVICE,
607 "Inject: Buffer Allocation error\n");
608 return -ENOMEM;
609 }
610
611 if (trig_type == ALTR_UE_TRIGGER_CHAR)
612 error_mask = priv->ue_set_mask;
613 else
614 error_mask = priv->ce_set_mask;
615
616 edac_printk(KERN_ALERT, EDAC_DEVICE,
617 "Trigger Error Mask (0x%X)\n", error_mask);
618
619 local_irq_save(flags);
620 /* write ECC corrupted data out. */
621 for (i = 0; i < (priv->trig_alloc_sz / sizeof(*ptemp)); i++) {
622 /* Read data so we're in the correct state */
623 rmb();
624 if (ACCESS_ONCE(ptemp[i]))
625 result = -1;
626 /* Toggle Error bit (it is latched), leave ECC enabled */
Thor Thayer811fce42016-03-21 11:01:42 -0500627 writel(error_mask, (drvdata->base + priv->set_err_ofst));
628 writel(priv->ecc_enable_mask, (drvdata->base +
629 priv->set_err_ofst));
Thor Thayerc3eea192016-02-10 13:26:21 -0600630 ptemp[i] = i;
631 }
632 /* Ensure it has been written out */
633 wmb();
634 local_irq_restore(flags);
635
636 if (result)
637 edac_printk(KERN_ERR, EDAC_DEVICE, "Mem Not Cleared\n");
638
639 /* Read out written data. ECC error caused here */
640 for (i = 0; i < ALTR_TRIGGER_READ_WRD_CNT; i++)
641 if (ACCESS_ONCE(ptemp[i]) != i)
642 edac_printk(KERN_ERR, EDAC_DEVICE,
643 "Read doesn't match written data\n");
644
645 if (priv->free_mem)
646 priv->free_mem(ptemp, priv->trig_alloc_sz, generic_ptr);
647
648 return count;
649}
650
651static const struct file_operations altr_edac_device_inject_fops = {
652 .open = simple_open,
653 .write = altr_edac_device_trig,
654 .llseek = generic_file_llseek,
655};
656
657static void altr_create_edacdev_dbgfs(struct edac_device_ctl_info *edac_dci,
658 const struct edac_device_prv_data *priv)
659{
660 struct altr_edac_device_dev *drvdata = edac_dci->pvt_info;
661
662 if (!IS_ENABLED(CONFIG_EDAC_DEBUG))
663 return;
664
665 drvdata->debugfs_dir = edac_debugfs_create_dir(drvdata->edac_dev_name);
666 if (!drvdata->debugfs_dir)
667 return;
668
669 if (!edac_debugfs_create_file(priv->dbgfs_name, S_IWUSR,
670 drvdata->debugfs_dir, edac_dci,
Thor Thayere17ced22016-03-31 13:48:01 -0500671 priv->inject_fops))
Thor Thayerc3eea192016-02-10 13:26:21 -0600672 debugfs_remove_recursive(drvdata->debugfs_dir);
673}
674
675static const struct of_device_id altr_edac_device_of_match[] = {
676#ifdef CONFIG_EDAC_ALTERA_L2C
677 { .compatible = "altr,socfpga-l2-ecc", .data = (void *)&l2ecc_data },
Thor Thayer588cb032016-03-21 11:01:44 -0500678 { .compatible = "altr,socfpga-a10-l2-ecc",
679 .data = (void *)&a10_l2ecc_data },
Thor Thayerc3eea192016-02-10 13:26:21 -0600680#endif
681#ifdef CONFIG_EDAC_ALTERA_OCRAM
682 { .compatible = "altr,socfpga-ocram-ecc",
683 .data = (void *)&ocramecc_data },
684#endif
685 {},
686};
687MODULE_DEVICE_TABLE(of, altr_edac_device_of_match);
688
689/*
690 * altr_edac_device_probe()
691 * This is a generic EDAC device driver that will support
692 * various Altera memory devices such as the L2 cache ECC and
693 * OCRAM ECC as well as the memories for other peripherals.
694 * Module specific initialization is done by passing the
695 * function index in the device tree.
696 */
697static int altr_edac_device_probe(struct platform_device *pdev)
698{
699 struct edac_device_ctl_info *dci;
700 struct altr_edac_device_dev *drvdata;
701 struct resource *r;
702 int res = 0;
703 struct device_node *np = pdev->dev.of_node;
704 char *ecc_name = (char *)np->name;
705 static int dev_instance;
706
707 if (!devres_open_group(&pdev->dev, NULL, GFP_KERNEL)) {
708 edac_printk(KERN_ERR, EDAC_DEVICE,
709 "Unable to open devm\n");
710 return -ENOMEM;
711 }
712
713 r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
714 if (!r) {
715 edac_printk(KERN_ERR, EDAC_DEVICE,
716 "Unable to get mem resource\n");
717 res = -ENODEV;
718 goto fail;
719 }
720
721 if (!devm_request_mem_region(&pdev->dev, r->start, resource_size(r),
722 dev_name(&pdev->dev))) {
723 edac_printk(KERN_ERR, EDAC_DEVICE,
724 "%s:Error requesting mem region\n", ecc_name);
725 res = -EBUSY;
726 goto fail;
727 }
728
729 dci = edac_device_alloc_ctl_info(sizeof(*drvdata), ecc_name,
730 1, ecc_name, 1, 0, NULL, 0,
731 dev_instance++);
732
733 if (!dci) {
734 edac_printk(KERN_ERR, EDAC_DEVICE,
735 "%s: Unable to allocate EDAC device\n", ecc_name);
736 res = -ENOMEM;
737 goto fail;
738 }
739
740 drvdata = dci->pvt_info;
741 dci->dev = &pdev->dev;
742 platform_set_drvdata(pdev, dci);
743 drvdata->edac_dev_name = ecc_name;
744
745 drvdata->base = devm_ioremap(&pdev->dev, r->start, resource_size(r));
746 if (!drvdata->base)
747 goto fail1;
748
749 /* Get driver specific data for this EDAC device */
750 drvdata->data = of_match_node(altr_edac_device_of_match, np)->data;
751
752 /* Check specific dependencies for the module */
753 if (drvdata->data->setup) {
Thor Thayer328ca7a2016-03-21 11:01:40 -0500754 res = drvdata->data->setup(drvdata);
Thor Thayerc3eea192016-02-10 13:26:21 -0600755 if (res)
756 goto fail1;
757 }
758
759 drvdata->sb_irq = platform_get_irq(pdev, 0);
760 res = devm_request_irq(&pdev->dev, drvdata->sb_irq,
761 altr_edac_device_handler,
762 0, dev_name(&pdev->dev), dci);
763 if (res)
764 goto fail1;
765
766 drvdata->db_irq = platform_get_irq(pdev, 1);
767 res = devm_request_irq(&pdev->dev, drvdata->db_irq,
768 altr_edac_device_handler,
769 0, dev_name(&pdev->dev), dci);
770 if (res)
771 goto fail1;
772
773 dci->mod_name = "Altera ECC Manager";
774 dci->dev_name = drvdata->edac_dev_name;
775
776 res = edac_device_add_device(dci);
777 if (res)
778 goto fail1;
779
780 altr_create_edacdev_dbgfs(dci, drvdata->data);
781
782 devres_close_group(&pdev->dev, NULL);
783
784 return 0;
785
786fail1:
787 edac_device_free_ctl_info(dci);
788fail:
789 devres_release_group(&pdev->dev, NULL);
790 edac_printk(KERN_ERR, EDAC_DEVICE,
791 "%s:Error setting up EDAC device: %d\n", ecc_name, res);
792
793 return res;
794}
795
796static int altr_edac_device_remove(struct platform_device *pdev)
797{
798 struct edac_device_ctl_info *dci = platform_get_drvdata(pdev);
799 struct altr_edac_device_dev *drvdata = dci->pvt_info;
800
801 debugfs_remove_recursive(drvdata->debugfs_dir);
802 edac_device_del_device(&pdev->dev);
803 edac_device_free_ctl_info(dci);
804
805 return 0;
806}
807
808static struct platform_driver altr_edac_device_driver = {
809 .probe = altr_edac_device_probe,
810 .remove = altr_edac_device_remove,
811 .driver = {
812 .name = "altr_edac_device",
813 .of_match_table = altr_edac_device_of_match,
814 },
815};
816module_platform_driver(altr_edac_device_driver);
817
818/*********************** OCRAM EDAC Device Functions *********************/
819
820#ifdef CONFIG_EDAC_ALTERA_OCRAM
821
822static void *ocram_alloc_mem(size_t size, void **other)
823{
824 struct device_node *np;
825 struct gen_pool *gp;
826 void *sram_addr;
827
828 np = of_find_compatible_node(NULL, NULL, "altr,socfpga-ocram-ecc");
829 if (!np)
830 return NULL;
831
832 gp = of_gen_pool_get(np, "iram", 0);
833 of_node_put(np);
834 if (!gp)
835 return NULL;
836
837 sram_addr = (void *)gen_pool_alloc(gp, size);
838 if (!sram_addr)
839 return NULL;
840
841 memset(sram_addr, 0, size);
842 /* Ensure data is written out */
843 wmb();
844
845 /* Remember this handle for freeing later */
846 *other = gp;
847
848 return sram_addr;
849}
850
851static void ocram_free_mem(void *p, size_t size, void *other)
852{
853 gen_pool_free((struct gen_pool *)other, (u32)p, size);
854}
855
856/*
857 * altr_ocram_check_deps()
858 * Test for OCRAM cache ECC dependencies upon entry because
859 * platform specific startup should have initialized the
860 * On-Chip RAM memory and enabled the ECC.
861 * Can't turn on ECC here because accessing un-initialized
862 * memory will cause CE/UE errors possibly causing an ABORT.
863 */
Thor Thayer328ca7a2016-03-21 11:01:40 -0500864static int altr_ocram_check_deps(struct altr_edac_device_dev *device)
Thor Thayerc3eea192016-02-10 13:26:21 -0600865{
Thor Thayer328ca7a2016-03-21 11:01:40 -0500866 void __iomem *base = device->base;
Thor Thayer27439a12016-03-21 11:01:41 -0500867 const struct edac_device_prv_data *prv = device->data;
868
Thor Thayer943ad912016-03-31 13:48:02 -0500869 if (readl(base + prv->ecc_en_ofst) & prv->ecc_enable_mask)
Thor Thayerc3eea192016-02-10 13:26:21 -0600870 return 0;
871
872 edac_printk(KERN_ERR, EDAC_DEVICE,
873 "OCRAM: No ECC present or ECC disabled.\n");
874 return -ENODEV;
875}
876
877const struct edac_device_prv_data ocramecc_data = {
878 .setup = altr_ocram_check_deps,
879 .ce_clear_mask = (ALTR_OCR_ECC_EN | ALTR_OCR_ECC_SERR),
880 .ue_clear_mask = (ALTR_OCR_ECC_EN | ALTR_OCR_ECC_DERR),
881 .dbgfs_name = "altr_ocram_trigger",
882 .alloc_mem = ocram_alloc_mem,
883 .free_mem = ocram_free_mem,
884 .ecc_enable_mask = ALTR_OCR_ECC_EN,
Thor Thayer943ad912016-03-31 13:48:02 -0500885 .ecc_en_ofst = ALTR_OCR_ECC_REG_OFFSET,
Thor Thayerc3eea192016-02-10 13:26:21 -0600886 .ce_set_mask = (ALTR_OCR_ECC_EN | ALTR_OCR_ECC_INJS),
887 .ue_set_mask = (ALTR_OCR_ECC_EN | ALTR_OCR_ECC_INJD),
Thor Thayer811fce42016-03-21 11:01:42 -0500888 .set_err_ofst = ALTR_OCR_ECC_REG_OFFSET,
Thor Thayerc3eea192016-02-10 13:26:21 -0600889 .trig_alloc_sz = ALTR_TRIG_OCRAM_BYTE_SIZE,
Thor Thayere17ced22016-03-31 13:48:01 -0500890 .inject_fops = &altr_edac_device_inject_fops,
Thor Thayerc3eea192016-02-10 13:26:21 -0600891};
892
893#endif /* CONFIG_EDAC_ALTERA_OCRAM */
894
895/********************* L2 Cache EDAC Device Functions ********************/
896
897#ifdef CONFIG_EDAC_ALTERA_L2C
898
899static void *l2_alloc_mem(size_t size, void **other)
900{
901 struct device *dev = *other;
902 void *ptemp = devm_kzalloc(dev, size, GFP_KERNEL);
903
904 if (!ptemp)
905 return NULL;
906
907 /* Make sure everything is written out */
908 wmb();
909
910 /*
911 * Clean all cache levels up to LoC (includes L2)
912 * This ensures the corrupted data is written into
913 * L2 cache for readback test (which causes ECC error).
914 */
915 flush_cache_all();
916
917 return ptemp;
918}
919
920static void l2_free_mem(void *p, size_t size, void *other)
921{
922 struct device *dev = other;
923
924 if (dev && p)
925 devm_kfree(dev, p);
926}
927
928/*
929 * altr_l2_check_deps()
930 * Test for L2 cache ECC dependencies upon entry because
931 * platform specific startup should have initialized the L2
932 * memory and enabled the ECC.
933 * Bail if ECC is not enabled.
934 * Note that L2 Cache Enable is forced at build time.
935 */
Thor Thayer328ca7a2016-03-21 11:01:40 -0500936static int altr_l2_check_deps(struct altr_edac_device_dev *device)
Thor Thayerc3eea192016-02-10 13:26:21 -0600937{
Thor Thayer328ca7a2016-03-21 11:01:40 -0500938 void __iomem *base = device->base;
Thor Thayer27439a12016-03-21 11:01:41 -0500939 const struct edac_device_prv_data *prv = device->data;
940
941 if ((readl(base) & prv->ecc_enable_mask) ==
942 prv->ecc_enable_mask)
Thor Thayerc3eea192016-02-10 13:26:21 -0600943 return 0;
944
945 edac_printk(KERN_ERR, EDAC_DEVICE,
946 "L2: No ECC present, or ECC disabled\n");
947 return -ENODEV;
948}
949
Thor Thayer588cb032016-03-21 11:01:44 -0500950static irqreturn_t altr_edac_a10_l2_irq(struct altr_edac_device_dev *dci,
951 bool sberr)
952{
953 if (sberr) {
954 regmap_write(dci->edac->ecc_mgr_map,
955 A10_SYSGMR_MPU_CLEAR_L2_ECC_OFST,
956 A10_SYSGMR_MPU_CLEAR_L2_ECC_SB);
957 edac_device_handle_ce(dci->edac_dev, 0, 0, dci->edac_dev_name);
958 } else {
959 regmap_write(dci->edac->ecc_mgr_map,
960 A10_SYSGMR_MPU_CLEAR_L2_ECC_OFST,
961 A10_SYSGMR_MPU_CLEAR_L2_ECC_MB);
962 edac_device_handle_ue(dci->edac_dev, 0, 0, dci->edac_dev_name);
963 panic("\nEDAC:ECC_DEVICE[Uncorrectable errors]\n");
964 }
965 return IRQ_HANDLED;
966}
967
Thor Thayerc3eea192016-02-10 13:26:21 -0600968const struct edac_device_prv_data l2ecc_data = {
969 .setup = altr_l2_check_deps,
970 .ce_clear_mask = 0,
971 .ue_clear_mask = 0,
972 .dbgfs_name = "altr_l2_trigger",
973 .alloc_mem = l2_alloc_mem,
974 .free_mem = l2_free_mem,
975 .ecc_enable_mask = ALTR_L2_ECC_EN,
976 .ce_set_mask = (ALTR_L2_ECC_EN | ALTR_L2_ECC_INJS),
977 .ue_set_mask = (ALTR_L2_ECC_EN | ALTR_L2_ECC_INJD),
Thor Thayer811fce42016-03-21 11:01:42 -0500978 .set_err_ofst = ALTR_L2_ECC_REG_OFFSET,
Thor Thayerc3eea192016-02-10 13:26:21 -0600979 .trig_alloc_sz = ALTR_TRIG_L2C_BYTE_SIZE,
Thor Thayere17ced22016-03-31 13:48:01 -0500980 .inject_fops = &altr_edac_device_inject_fops,
Thor Thayerc3eea192016-02-10 13:26:21 -0600981};
982
Thor Thayer588cb032016-03-21 11:01:44 -0500983const struct edac_device_prv_data a10_l2ecc_data = {
984 .setup = altr_l2_check_deps,
985 .ce_clear_mask = ALTR_A10_L2_ECC_SERR_CLR,
986 .ue_clear_mask = ALTR_A10_L2_ECC_MERR_CLR,
987 .irq_status_mask = A10_SYSMGR_ECC_INTSTAT_L2,
988 .dbgfs_name = "altr_l2_trigger",
989 .alloc_mem = l2_alloc_mem,
990 .free_mem = l2_free_mem,
991 .ecc_enable_mask = ALTR_A10_L2_ECC_EN_CTL,
992 .ce_set_mask = ALTR_A10_L2_ECC_CE_INJ_MASK,
993 .ue_set_mask = ALTR_A10_L2_ECC_UE_INJ_MASK,
994 .set_err_ofst = ALTR_A10_L2_ECC_INJ_OFST,
995 .ecc_irq_handler = altr_edac_a10_l2_irq,
996 .trig_alloc_sz = ALTR_TRIG_L2C_BYTE_SIZE,
Thor Thayere17ced22016-03-31 13:48:01 -0500997 .inject_fops = &altr_edac_device_inject_fops,
Thor Thayer588cb032016-03-21 11:01:44 -0500998};
999
Thor Thayerc3eea192016-02-10 13:26:21 -06001000#endif /* CONFIG_EDAC_ALTERA_L2C */
1001
Thor Thayer588cb032016-03-21 11:01:44 -05001002/********************* Arria10 EDAC Device Functions *************************/
1003
1004/*
1005 * The Arria10 EDAC Device Functions differ from the Cyclone5/Arria5
1006 * because 2 IRQs are shared among the all ECC peripherals. The ECC
1007 * manager manages the IRQs and the children.
1008 * Based on xgene_edac.c peripheral code.
1009 */
1010
1011static irqreturn_t altr_edac_a10_irq_handler(int irq, void *dev_id)
1012{
1013 irqreturn_t rc = IRQ_NONE;
1014 struct altr_arria10_edac *edac = dev_id;
1015 struct altr_edac_device_dev *dci;
1016 int irq_status;
1017 bool sberr = (irq == edac->sb_irq) ? 1 : 0;
1018 int sm_offset = sberr ? A10_SYSMGR_ECC_INTSTAT_SERR_OFST :
1019 A10_SYSMGR_ECC_INTSTAT_DERR_OFST;
1020
1021 regmap_read(edac->ecc_mgr_map, sm_offset, &irq_status);
1022
1023 if ((irq != edac->sb_irq) && (irq != edac->db_irq)) {
1024 WARN_ON(1);
1025 } else {
1026 list_for_each_entry(dci, &edac->a10_ecc_devices, next) {
1027 if (irq_status & dci->data->irq_status_mask)
1028 rc = dci->data->ecc_irq_handler(dci, sberr);
1029 }
1030 }
1031
1032 return rc;
1033}
1034
1035static int altr_edac_a10_device_add(struct altr_arria10_edac *edac,
1036 struct device_node *np)
1037{
1038 struct edac_device_ctl_info *dci;
1039 struct altr_edac_device_dev *altdev;
1040 char *ecc_name = (char *)np->name;
1041 struct resource res;
1042 int edac_idx;
1043 int rc = 0;
1044 const struct edac_device_prv_data *prv;
1045 /* Get matching node and check for valid result */
1046 const struct of_device_id *pdev_id =
1047 of_match_node(altr_edac_device_of_match, np);
1048 if (IS_ERR_OR_NULL(pdev_id))
1049 return -ENODEV;
1050
1051 /* Get driver specific data for this EDAC device */
1052 prv = pdev_id->data;
1053 if (IS_ERR_OR_NULL(prv))
1054 return -ENODEV;
1055
1056 if (!devres_open_group(edac->dev, altr_edac_a10_device_add, GFP_KERNEL))
1057 return -ENOMEM;
1058
1059 rc = of_address_to_resource(np, 0, &res);
1060 if (rc < 0) {
1061 edac_printk(KERN_ERR, EDAC_DEVICE,
1062 "%s: no resource address\n", ecc_name);
1063 goto err_release_group;
1064 }
1065
1066 edac_idx = edac_device_alloc_index();
1067 dci = edac_device_alloc_ctl_info(sizeof(*altdev), ecc_name,
1068 1, ecc_name, 1, 0, NULL, 0,
1069 edac_idx);
1070
1071 if (!dci) {
1072 edac_printk(KERN_ERR, EDAC_DEVICE,
1073 "%s: Unable to allocate EDAC device\n", ecc_name);
1074 rc = -ENOMEM;
1075 goto err_release_group;
1076 }
1077
1078 altdev = dci->pvt_info;
1079 dci->dev = edac->dev;
1080 altdev->edac_dev_name = ecc_name;
1081 altdev->edac_idx = edac_idx;
1082 altdev->edac = edac;
1083 altdev->edac_dev = dci;
1084 altdev->data = prv;
1085 altdev->ddev = *edac->dev;
1086 dci->dev = &altdev->ddev;
1087 dci->ctl_name = "Altera ECC Manager";
1088 dci->mod_name = ecc_name;
1089 dci->dev_name = ecc_name;
1090
1091 altdev->base = devm_ioremap_resource(edac->dev, &res);
1092 if (IS_ERR(altdev->base)) {
1093 rc = PTR_ERR(altdev->base);
1094 goto err_release_group1;
1095 }
1096
1097 /* Check specific dependencies for the module */
1098 if (altdev->data->setup) {
1099 rc = altdev->data->setup(altdev);
1100 if (rc)
1101 goto err_release_group1;
1102 }
1103
1104 rc = edac_device_add_device(dci);
1105 if (rc) {
1106 dev_err(edac->dev, "edac_device_add_device failed\n");
1107 rc = -ENOMEM;
1108 goto err_release_group1;
1109 }
1110
1111 altr_create_edacdev_dbgfs(dci, prv);
1112
1113 list_add(&altdev->next, &edac->a10_ecc_devices);
1114
1115 devres_remove_group(edac->dev, altr_edac_a10_device_add);
1116
1117 return 0;
1118
1119err_release_group1:
1120 edac_device_free_ctl_info(dci);
1121err_release_group:
1122 edac_printk(KERN_ALERT, EDAC_DEVICE, "%s: %d\n", __func__, __LINE__);
1123 devres_release_group(edac->dev, NULL);
1124 edac_printk(KERN_ERR, EDAC_DEVICE,
1125 "%s:Error setting up EDAC device: %d\n", ecc_name, rc);
1126
1127 return rc;
1128}
1129
1130static int altr_edac_a10_probe(struct platform_device *pdev)
1131{
1132 struct altr_arria10_edac *edac;
1133 struct device_node *child;
1134 int rc;
1135
1136 edac = devm_kzalloc(&pdev->dev, sizeof(*edac), GFP_KERNEL);
1137 if (!edac)
1138 return -ENOMEM;
1139
1140 edac->dev = &pdev->dev;
1141 platform_set_drvdata(pdev, edac);
1142 INIT_LIST_HEAD(&edac->a10_ecc_devices);
1143
1144 edac->ecc_mgr_map = syscon_regmap_lookup_by_phandle(pdev->dev.of_node,
1145 "altr,sysmgr-syscon");
1146 if (IS_ERR(edac->ecc_mgr_map)) {
1147 edac_printk(KERN_ERR, EDAC_DEVICE,
1148 "Unable to get syscon altr,sysmgr-syscon\n");
1149 return PTR_ERR(edac->ecc_mgr_map);
1150 }
1151
1152 edac->sb_irq = platform_get_irq(pdev, 0);
1153 rc = devm_request_irq(&pdev->dev, edac->sb_irq,
1154 altr_edac_a10_irq_handler,
1155 IRQF_SHARED, dev_name(&pdev->dev), edac);
1156 if (rc) {
1157 edac_printk(KERN_ERR, EDAC_DEVICE, "No SBERR IRQ resource\n");
1158 return rc;
1159 }
1160
1161 edac->db_irq = platform_get_irq(pdev, 1);
1162 rc = devm_request_irq(&pdev->dev, edac->db_irq,
1163 altr_edac_a10_irq_handler,
1164 IRQF_SHARED, dev_name(&pdev->dev), edac);
1165 if (rc) {
1166 edac_printk(KERN_ERR, EDAC_DEVICE, "No DBERR IRQ resource\n");
1167 return rc;
1168 }
1169
1170 for_each_child_of_node(pdev->dev.of_node, child) {
1171 if (!of_device_is_available(child))
1172 continue;
1173 if (of_device_is_compatible(child, "altr,socfpga-a10-l2-ecc"))
1174 altr_edac_a10_device_add(edac, child);
1175 }
1176
1177 return 0;
1178}
1179
1180static const struct of_device_id altr_edac_a10_of_match[] = {
1181 { .compatible = "altr,socfpga-a10-ecc-manager" },
1182 {},
1183};
1184MODULE_DEVICE_TABLE(of, altr_edac_a10_of_match);
1185
1186static struct platform_driver altr_edac_a10_driver = {
1187 .probe = altr_edac_a10_probe,
1188 .driver = {
1189 .name = "socfpga_a10_ecc_manager",
1190 .of_match_table = altr_edac_a10_of_match,
1191 },
1192};
1193module_platform_driver(altr_edac_a10_driver);
1194
Thor Thayer71bcada2014-09-03 10:27:54 -05001195MODULE_LICENSE("GPL v2");
1196MODULE_AUTHOR("Thor Thayer");
Thor Thayerc3eea192016-02-10 13:26:21 -06001197MODULE_DESCRIPTION("EDAC Driver for Altera Memories");