blob: 34a5b93704d3ecb1d98190f6a12437a9acab7204 [file] [log] [blame]
H. Peter Anvin1965aae2008-10-22 22:26:29 -07001#ifndef _ASM_X86_IO_H
2#define _ASM_X86_IO_H
venkatesh.pallipadi@intel.come045fb22008-03-18 17:00:15 -07003
Brian Gerst1c5b9062010-02-05 09:37:09 -05004/*
5 * This file contains the definitions for the x86 IO instructions
6 * inb/inw/inl/outb/outw/outl and the "string versions" of the same
7 * (insb/insw/insl/outsb/outsw/outsl). You can also use "pausing"
8 * versions of the single-IO instructions (inb_p/inw_p/..).
9 *
10 * This file is not meant to be obfuscating: it's just complicated
11 * to (a) handle it all in a way that makes gcc able to optimize it
12 * as well as possible and (b) trying to avoid writing the same thing
13 * over and over again with slight variations and possibly making a
14 * mistake somewhere.
15 */
16
17/*
18 * Thanks to James van Artsdalen for a better timing-fix than
19 * the two short jumps: using outb's to a nonexistent port seems
20 * to guarantee better timings even on fast machines.
21 *
22 * On the other hand, I'd like to be sure of a non-existent port:
23 * I feel a bit unsafe about using 0x80 (should be safe, though)
24 *
25 * Linus
26 */
27
28 /*
29 * Bit simplified and optimized by Jan Hubicka
30 * Support of BIGMEM added by Gerhard Wichert, Siemens AG, July 1999.
31 *
32 * isa_memset_io, isa_memcpy_fromio, isa_memcpy_toio added,
33 * isa_read[wl] and isa_write[wl] fixed
34 * - Arnaldo Carvalho de Melo <acme@conectiva.com.br>
35 */
36
venkatesh.pallipadi@intel.comb310f381d2008-03-18 17:00:24 -070037#define ARCH_HAS_IOREMAP_WC
38
Brian Gerst1c5b9062010-02-05 09:37:09 -050039#include <linux/string.h>
Linus Torvaldsc1f64a52008-05-27 09:47:13 -070040#include <linux/compiler.h>
Jeremy Fitzhardinge976e8f62009-02-06 13:29:44 -080041#include <asm/page.h>
Mark Salter5b7c73e2014-04-07 15:39:49 -070042#include <asm/early_ioremap.h>
Linus Torvaldsc1f64a52008-05-27 09:47:13 -070043
44#define build_mmio_read(name, size, type, reg, barrier) \
45static inline type name(const volatile void __iomem *addr) \
Mikael Pettersson1c5b0eb2008-08-13 21:07:07 +020046{ type ret; asm volatile("mov" size " %1,%0":reg (ret) \
Linus Torvaldsc1f64a52008-05-27 09:47:13 -070047:"m" (*(volatile type __force *)addr) barrier); return ret; }
48
49#define build_mmio_write(name, size, type, reg, barrier) \
50static inline void name(type val, volatile void __iomem *addr) \
51{ asm volatile("mov" size " %0,%1": :reg (val), \
52"m" (*(volatile type __force *)addr) barrier); }
53
Mikael Pettersson1c5b0eb2008-08-13 21:07:07 +020054build_mmio_read(readb, "b", unsigned char, "=q", :"memory")
55build_mmio_read(readw, "w", unsigned short, "=r", :"memory")
56build_mmio_read(readl, "l", unsigned int, "=r", :"memory")
Linus Torvaldsc1f64a52008-05-27 09:47:13 -070057
Mikael Pettersson1c5b0eb2008-08-13 21:07:07 +020058build_mmio_read(__readb, "b", unsigned char, "=q", )
59build_mmio_read(__readw, "w", unsigned short, "=r", )
60build_mmio_read(__readl, "l", unsigned int, "=r", )
Linus Torvaldsc1f64a52008-05-27 09:47:13 -070061
62build_mmio_write(writeb, "b", unsigned char, "q", :"memory")
63build_mmio_write(writew, "w", unsigned short, "r", :"memory")
64build_mmio_write(writel, "l", unsigned int, "r", :"memory")
65
66build_mmio_write(__writeb, "b", unsigned char, "q", )
67build_mmio_write(__writew, "w", unsigned short, "r", )
68build_mmio_write(__writel, "l", unsigned int, "r", )
69
70#define readb_relaxed(a) __readb(a)
71#define readw_relaxed(a) __readw(a)
72#define readl_relaxed(a) __readl(a)
73#define __raw_readb __readb
74#define __raw_readw __readw
75#define __raw_readl __readl
76
Will Deaconcbc908e2013-09-04 11:34:08 +010077#define writeb_relaxed(v, a) __writeb(v, a)
78#define writew_relaxed(v, a) __writew(v, a)
79#define writel_relaxed(v, a) __writel(v, a)
Linus Torvaldsc1f64a52008-05-27 09:47:13 -070080#define __raw_writeb __writeb
81#define __raw_writew __writew
82#define __raw_writel __writel
83
84#define mmiowb() barrier()
85
86#ifdef CONFIG_X86_64
Ingo Molnar93093d02008-11-30 10:20:20 +010087
Mikael Pettersson1c5b0eb2008-08-13 21:07:07 +020088build_mmio_read(readq, "q", unsigned long, "=r", :"memory")
Linus Torvaldsc1f64a52008-05-27 09:47:13 -070089build_mmio_write(writeq, "q", unsigned long, "r", :"memory")
Linus Torvaldsc1f64a52008-05-27 09:47:13 -070090
Ingo Molnar93093d02008-11-30 10:20:20 +010091#define readq_relaxed(a) readq(a)
Will Deaconcbc908e2013-09-04 11:34:08 +010092#define writeq_relaxed(v, a) writeq(v, a)
Ingo Molnar93093d02008-11-30 10:20:20 +010093
94#define __raw_readq(a) readq(a)
95#define __raw_writeq(val, addr) writeq(val, addr)
96
Ingo Molnara0b11312008-11-30 09:33:55 +010097/* Let people know that we have them */
Ingo Molnar93093d02008-11-30 10:20:20 +010098#define readq readq
99#define writeq writeq
Hitoshi Mitake2c5643b2008-11-30 17:16:04 +0900100
Roland Dreierdbee8a02011-05-24 17:13:09 -0700101#endif
102
Jeremy Fitzhardinge976e8f62009-02-06 13:29:44 -0800103/**
104 * virt_to_phys - map virtual addresses to physical
105 * @address: address to remap
106 *
107 * The returned physical address is the physical (CPU) mapping for
108 * the memory address given. It is only valid to use this function on
109 * addresses directly mapped or allocated via kmalloc.
110 *
111 * This function does not give bus mappings for DMA transfers. In
112 * almost all conceivable cases a device driver should not be using
113 * this function
114 */
115
116static inline phys_addr_t virt_to_phys(volatile void *address)
117{
118 return __pa(address);
119}
120
121/**
122 * phys_to_virt - map physical address to virtual
123 * @address: address to remap
124 *
125 * The returned virtual address is a current CPU mapping for
126 * the memory address given. It is only valid to use this function on
127 * addresses that have a kernel mapping
128 *
129 * This function does not handle bus mappings for DMA transfers. In
130 * almost all conceivable cases a device driver should not be using
131 * this function
132 */
133
134static inline void *phys_to_virt(phys_addr_t address)
135{
136 return __va(address);
137}
138
139/*
140 * Change "struct page" to physical address.
141 */
142#define page_to_phys(page) ((dma_addr_t)page_to_pfn(page) << PAGE_SHIFT)
143
144/*
145 * ISA I/O bus memory addresses are 1:1 with the physical address.
H. Peter Anvina7eb5182009-02-17 13:01:51 -0800146 * However, we truncate the address to unsigned int to avoid undesirable
147 * promitions in legacy drivers.
Jeremy Fitzhardinge976e8f62009-02-06 13:29:44 -0800148 */
H. Peter Anvina7eb5182009-02-17 13:01:51 -0800149static inline unsigned int isa_virt_to_bus(volatile void *address)
150{
151 return (unsigned int)virt_to_phys(address);
152}
153#define isa_page_to_bus(page) ((unsigned int)page_to_phys(page))
154#define isa_bus_to_virt phys_to_virt
Jeremy Fitzhardinge976e8f62009-02-06 13:29:44 -0800155
156/*
157 * However PCI ones are not necessarily 1:1 and therefore these interfaces
158 * are forbidden in portable PCI drivers.
159 *
160 * Allow them on x86 for legacy drivers, though.
161 */
162#define virt_to_bus virt_to_phys
163#define bus_to_virt phys_to_virt
164
Jeremy Fitzhardinge133822c2009-02-06 13:29:52 -0800165/**
166 * ioremap - map bus memory into CPU space
167 * @offset: bus address of the memory
168 * @size: size of the resource to map
169 *
170 * ioremap performs a platform specific sequence of operations to
171 * make bus memory CPU accessible via the readb/readw/readl/writeb/
172 * writew/writel functions and the other mmio helpers. The returned
173 * address is not guaranteed to be usable directly as a virtual
174 * address.
175 *
176 * If the area you are trying to map is a PCI BAR you should have a
177 * look at pci_iomap().
178 */
179extern void __iomem *ioremap_nocache(resource_size_t offset, unsigned long size);
180extern void __iomem *ioremap_cache(resource_size_t offset, unsigned long size);
181extern void __iomem *ioremap_prot(resource_size_t offset, unsigned long size,
182 unsigned long prot_val);
183
184/*
185 * The default ioremap() behavior is non-cached:
186 */
187static inline void __iomem *ioremap(resource_size_t offset, unsigned long size)
188{
189 return ioremap_nocache(offset, size);
190}
191
192extern void iounmap(volatile void __iomem *addr);
193
Cliff Wickman3ee48b62010-09-16 11:44:02 -0500194extern void set_iounmap_nonlazy(void);
Jaswinder Singh9321b8c2008-07-21 22:24:29 +0530195
Brian Gerst1c5b9062010-02-05 09:37:09 -0500196#ifdef __KERNEL__
197
198#include <asm-generic/iomap.h>
199
200#include <linux/vmalloc.h>
201
202/*
203 * Convert a virtual cached pointer to an uncached pointer
204 */
205#define xlate_dev_kmem_ptr(p) p
206
207static inline void
208memset_io(volatile void __iomem *addr, unsigned char val, size_t count)
209{
210 memset((void __force *)addr, val, count);
211}
212
213static inline void
214memcpy_fromio(void *dst, const volatile void __iomem *src, size_t count)
215{
216 memcpy(dst, (const void __force *)src, count);
217}
218
219static inline void
220memcpy_toio(volatile void __iomem *dst, const void *src, size_t count)
221{
222 memcpy((void __force *)dst, src, count);
223}
224
225/*
226 * ISA space is 'always mapped' on a typical x86 system, no need to
227 * explicitly ioremap() it. The fact that the ISA IO space is mapped
228 * to PAGE_OFFSET is pure coincidence - it does not mean ISA values
229 * are physical addresses. The following constant pointer can be
230 * used as the IO-area pointer (it can be iounmapped as well, so the
231 * analogy with PCI is quite large):
232 */
233#define __ISA_IO_base ((char __iomem *)(PAGE_OFFSET))
234
235/*
236 * Cache management
237 *
238 * This needed for two cases
239 * 1. Out of order aware processors
240 * 2. Accidentally out of order processors (PPro errata #51)
241 */
242
243static inline void flush_write_buffers(void)
244{
Dave Jones09df7c42014-03-10 19:32:22 -0400245#if defined(CONFIG_X86_PPRO_FENCE)
Brian Gerst1c5b9062010-02-05 09:37:09 -0500246 asm volatile("lock; addl $0,0(%%esp)": : :"memory");
Thomas Gleixner96a388d2007-10-11 11:20:03 +0200247#endif
Brian Gerst1c5b9062010-02-05 09:37:09 -0500248}
249
250#endif /* __KERNEL__ */
251
252extern void native_io_delay(void);
253
254extern int io_delay_type;
255extern void io_delay_init(void);
256
257#if defined(CONFIG_PARAVIRT)
258#include <asm/paravirt.h>
259#else
260
261static inline void slow_down_io(void)
262{
263 native_io_delay();
264#ifdef REALLY_SLOW_IO
265 native_io_delay();
266 native_io_delay();
267 native_io_delay();
268#endif
269}
270
271#endif
272
273#define BUILDIO(bwl, bw, type) \
274static inline void out##bwl(unsigned type value, int port) \
275{ \
276 asm volatile("out" #bwl " %" #bw "0, %w1" \
277 : : "a"(value), "Nd"(port)); \
278} \
279 \
280static inline unsigned type in##bwl(int port) \
281{ \
282 unsigned type value; \
283 asm volatile("in" #bwl " %w1, %" #bw "0" \
284 : "=a"(value) : "Nd"(port)); \
285 return value; \
286} \
287 \
288static inline void out##bwl##_p(unsigned type value, int port) \
289{ \
290 out##bwl(value, port); \
291 slow_down_io(); \
292} \
293 \
294static inline unsigned type in##bwl##_p(int port) \
295{ \
296 unsigned type value = in##bwl(port); \
297 slow_down_io(); \
298 return value; \
299} \
300 \
301static inline void outs##bwl(int port, const void *addr, unsigned long count) \
302{ \
303 asm volatile("rep; outs" #bwl \
304 : "+S"(addr), "+c"(count) : "d"(port)); \
305} \
306 \
307static inline void ins##bwl(int port, void *addr, unsigned long count) \
308{ \
309 asm volatile("rep; ins" #bwl \
310 : "+D"(addr), "+c"(count) : "d"(port)); \
311}
312
313BUILDIO(b, b, char)
314BUILDIO(w, w, short)
315BUILDIO(l, , int)
venkatesh.pallipadi@intel.come045fb22008-03-18 17:00:15 -0700316
Thierry Reding4707a342014-07-28 17:20:33 +0200317extern void *xlate_dev_mem_ptr(phys_addr_t phys);
318extern void unxlate_dev_mem_ptr(phys_addr_t phys, void *addr);
venkatesh.pallipadi@intel.come045fb22008-03-18 17:00:15 -0700319
venkatesh.pallipadi@intel.com3a96ce82008-03-18 17:00:16 -0700320extern int ioremap_change_attr(unsigned long vaddr, unsigned long size,
Juergen Grossb14097b2014-11-03 14:01:58 +0100321 enum page_cache_mode pcm);
venkatesh.pallipadi@intel.comd639bab2009-01-09 16:13:13 -0800322extern void __iomem *ioremap_wc(resource_size_t offset, unsigned long size);
venkatesh.pallipadi@intel.com3a96ce82008-03-18 17:00:16 -0700323
Jeremy Fitzhardingefef5ba72010-10-13 16:02:24 -0700324extern bool is_early_ioremap_ptep(pte_t *ptep);
Jeremy Fitzhardinge4583ed52008-06-25 00:19:03 -0400325
Jeremy Fitzhardinged8e04202009-02-09 12:05:46 -0800326#ifdef CONFIG_XEN
Linus Torvalds33f35f22011-08-03 22:00:38 -1000327#include <xen/xen.h>
Jeremy Fitzhardinged8e04202009-02-09 12:05:46 -0800328struct bio_vec;
329
330extern bool xen_biovec_phys_mergeable(const struct bio_vec *vec1,
331 const struct bio_vec *vec2);
332
333#define BIOVEC_PHYS_MERGEABLE(vec1, vec2) \
334 (__BIOVEC_PHYS_MERGEABLE(vec1, vec2) && \
335 (!xen_domain() || xen_biovec_phys_mergeable(vec1, vec2)))
336#endif /* CONFIG_XEN */
337
Jeremy Fitzhardingea4487202009-01-28 15:42:23 -0800338#define IO_SPACE_LIMIT 0xffff
Jeremy Fitzhardinge4583ed52008-06-25 00:19:03 -0400339
Andy Lutomirskid0d98ee2013-05-13 23:58:40 +0000340#ifdef CONFIG_MTRR
341extern int __must_check arch_phys_wc_add(unsigned long base,
342 unsigned long size);
343extern void arch_phys_wc_del(int handle);
344#define arch_phys_wc_add arch_phys_wc_add
345#endif
346
H. Peter Anvin1965aae2008-10-22 22:26:29 -0700347#endif /* _ASM_X86_IO_H */