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gerrit-public.fairphone.software / kernel / msm-4.9 / 95decf84742d712a5875bb655cd7440f6d7c1184 / . / arch / arm / boot / dts / tegra-cardhu.dts
blob: 378b65e186e8801d244c28517b280be7a13234a6 [file] [log] [blame]
Peter De Schrijver64c4e9f2011-12-14 17:03:26 +0200[diff] [blame]1/dts-v1/;
2
3/include/ "tegra30.dtsi"
4
5/ {
6 model = "NVIDIA Tegra30 Cardhu evaluation board";
7 compatible = "nvidia,cardhu", "nvidia,tegra30";
8
9 memory {
Stephen Warren95decf82012-05-11 16:11:38 -0600[diff] [blame^]10 reg = <0x80000000 0x40000000>;
Peter De Schrijver64c4e9f2011-12-14 17:03:26 +0200[diff] [blame]11 };
12
Stephen Warrene5cbeef2012-03-13 13:28:02 -0600[diff] [blame]13 pinmux@70000000 {
14 pinctrl-names = "default";
15 pinctrl-0 = <&state_default>;
16
17 state_default: pinmux {
18 sdmmc1_clk_pz0 {
19 nvidia,pins = "sdmmc1_clk_pz0";
20 nvidia,function = "sdmmc1";
21 nvidia,pull = <0>;
22 nvidia,tristate = <0>;
23 };
24 sdmmc1_cmd_pz1 {
25 nvidia,pins = "sdmmc1_cmd_pz1",
26 "sdmmc1_dat0_py7",
27 "sdmmc1_dat1_py6",
28 "sdmmc1_dat2_py5",
29 "sdmmc1_dat3_py4";
30 nvidia,function = "sdmmc1";
31 nvidia,pull = <2>;
32 nvidia,tristate = <0>;
33 };
34 sdmmc4_clk_pcc4 {
35 nvidia,pins = "sdmmc4_clk_pcc4",
36 "sdmmc4_rst_n_pcc3";
37 nvidia,function = "sdmmc4";
38 nvidia,pull = <0>;
39 nvidia,tristate = <0>;
40 };
41 sdmmc4_dat0_paa0 {
42 nvidia,pins = "sdmmc4_dat0_paa0",
43 "sdmmc4_dat1_paa1",
44 "sdmmc4_dat2_paa2",
45 "sdmmc4_dat3_paa3",
46 "sdmmc4_dat4_paa4",
47 "sdmmc4_dat5_paa5",
48 "sdmmc4_dat6_paa6",
49 "sdmmc4_dat7_paa7";
50 nvidia,function = "sdmmc4";
51 nvidia,pull = <2>;
52 nvidia,tristate = <0>;
53 };
Stephen Warren8c6a3852012-03-27 12:41:37 -0600[diff] [blame]54 dap2_fs_pa2 {
55 nvidia,pins = "dap2_fs_pa2",
56 "dap2_sclk_pa3",
57 "dap2_din_pa4",
58 "dap2_dout_pa5";
59 nvidia,function = "i2s1";
60 nvidia,pull = <0>;
61 nvidia,tristate = <0>;
62 };
Stephen Warrene5cbeef2012-03-13 13:28:02 -0600[diff] [blame]63 };
64 };
65
Peter De Schrijver64c4e9f2011-12-14 17:03:26 +0200[diff] [blame]66 serial@70006000 {
Stephen Warren95decf82012-05-11 16:11:38 -0600[diff] [blame^]67 clock-frequency = <408000000>;
Peter De Schrijver64c4e9f2011-12-14 17:03:26 +0200[diff] [blame]68 };
69
Stephen Warren8c690fd2012-02-02 12:24:19 -0700[diff] [blame]70 serial@70006040 {
71 status = "disable";
72 };
73
74 serial@70006200 {
75 status = "disable";
76 };
77
78 serial@70006300 {
79 status = "disable";
80 };
81
82 serial@70006400 {
83 status = "disable";
84 };
85
Peter De Schrijver64c4e9f2011-12-14 17:03:26 +0200[diff] [blame]86 i2c@7000c000 {
87 clock-frequency = <100000>;
88 };
89
90 i2c@7000c400 {
91 clock-frequency = <100000>;
92 };
93
94 i2c@7000c500 {
95 clock-frequency = <100000>;
Laxman Dewanganb46b0b52012-04-23 17:41:36 +0530[diff] [blame]96
97 /* ALS and Proximity sensor */
98 isl29028@44 {
99 compatible = "isil,isl29028";
100 reg = <0x44>;
101 interrupt-parent = <&gpio>;
102 interrupts = <88 0x04>; /*gpio PL0 */
103 };
Peter De Schrijver64c4e9f2011-12-14 17:03:26 +0200[diff] [blame]104 };
105
106 i2c@7000c700 {
107 clock-frequency = <100000>;
108 };
109
110 i2c@7000d000 {
111 clock-frequency = <100000>;
Stephen Warren8c6a3852012-03-27 12:41:37 -0600[diff] [blame]112
113 wm8903: wm8903@1a {
114 compatible = "wlf,wm8903";
115 reg = <0x1a>;
116 interrupt-parent = <&gpio>;
117 interrupts = <179 0x04>; /* gpio PW3 */
118
119 gpio-controller;
120 #gpio-cells = <2>;
121
122 micdet-cfg = <0>;
123 micdet-delay = <100>;
124 gpio-cfg = <0xffffffff 0xffffffff 0 0xffffffff 0xffffffff>;
125 };
Laxman Dewangan331da582012-05-10 20:38:45 +0000[diff] [blame]126
127 tps62361 {
128 compatible = "ti,tps62361";
129 reg = <0x60>;
130
131 regulator-name = "tps62361-vout";
132 regulator-min-microvolt = <500000>;
133 regulator-max-microvolt = <1500000>;
134 regulator-boot-on;
135 regulator-always-on;
136 ti,vsel0-state-high;
137 ti,vsel1-state-high;
138 };
Peter De Schrijver64c4e9f2011-12-14 17:03:26 +0200[diff] [blame]139 };
Stephen Warren850c4c82012-02-01 16:29:57 -0700[diff] [blame]140
141 sdhci@78000000 {
142 cd-gpios = <&gpio 69 0>; /* gpio PI5 */
143 wp-gpios = <&gpio 155 0>; /* gpio PT3 */
144 power-gpios = <&gpio 31 0>; /* gpio PD7 */
145 };
146
147 sdhci@78000200 {
148 status = "disable";
149 };
150
151 sdhci@78000400 {
152 status = "disable";
153 };
154
Stephen Warren1dfebb42012-05-11 18:01:38 -0600[diff] [blame]155 sdhci@78000600 {
Stephen Warren850c4c82012-02-01 16:29:57 -0700[diff] [blame]156 support-8bit;
157 };
Stephen Warren8c6a3852012-03-27 12:41:37 -0600[diff] [blame]158
159 ahub@70080000 {
160 i2s@70080300 {
161 status = "disable";
162 };
163
164 i2s@70080500 {
165 status = "disable";
166 };
167
168 i2s@70080600 {
169 status = "disable";
170 };
171
172 i2s@70080700 {
173 status = "disable";
174 };
175 };
176
177 sound {
178 compatible = "nvidia,tegra-audio-wm8903-cardhu",
179 "nvidia,tegra-audio-wm8903";
180 nvidia,model = "NVIDIA Tegra Cardhu";
181
182 nvidia,audio-routing =
183 "Headphone Jack", "HPOUTR",
184 "Headphone Jack", "HPOUTL",
185 "Int Spk", "ROP",
186 "Int Spk", "RON",
187 "Int Spk", "LOP",
188 "Int Spk", "LON",
189 "Mic Jack", "MICBIAS",
190 "IN1L", "Mic Jack";
191
192 nvidia,i2s-controller = <&tegra_i2s1>;
193 nvidia,audio-codec = <&wm8903>;
194
195 nvidia,spkr-en-gpios = <&wm8903 2 0>;
196 nvidia,hp-det-gpios = <&gpio 178 0>; /* gpio PW2 */
197 };
Peter De Schrijver64c4e9f2011-12-14 17:03:26 +0200[diff] [blame]198};