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Linus Walleij8d318a52010-03-30 15:33:42 +02001/*
Per Forlind49278e2010-12-20 18:31:38 +01002 * Copyright (C) Ericsson AB 2007-2008
3 * Copyright (C) ST-Ericsson SA 2008-2010
Per Forlin661385f2010-10-06 09:05:28 +00004 * Author: Per Forlin <per.forlin@stericsson.com> for ST-Ericsson
Jonas Aaberg767a9672010-08-09 12:08:34 +00005 * Author: Jonas Aaberg <jonas.aberg@stericsson.com> for ST-Ericsson
Linus Walleij8d318a52010-03-30 15:33:42 +02006 * License terms: GNU General Public License (GPL) version 2
Linus Walleij8d318a52010-03-30 15:33:42 +02007 */
8
Alexey Dobriyanb7f080c2011-06-16 11:01:34 +00009#include <linux/dma-mapping.h>
Linus Walleij8d318a52010-03-30 15:33:42 +020010#include <linux/kernel.h>
11#include <linux/slab.h>
Paul Gortmakerf492b212011-07-31 16:17:36 -040012#include <linux/export.h>
Linus Walleij8d318a52010-03-30 15:33:42 +020013#include <linux/dmaengine.h>
14#include <linux/platform_device.h>
15#include <linux/clk.h>
16#include <linux/delay.h>
Narayanan G7fb3e752011-11-17 17:26:41 +053017#include <linux/pm.h>
18#include <linux/pm_runtime.h>
Jonas Aaberg698e4732010-08-09 12:08:56 +000019#include <linux/err.h>
Linus Walleijf4b89762011-06-27 11:33:46 +020020#include <linux/amba/bus.h>
Linus Walleij8d318a52010-03-30 15:33:42 +020021
22#include <plat/ste_dma40.h>
23
Russell King - ARM Linuxd2ebfb32012-03-06 22:34:26 +000024#include "dmaengine.h"
Linus Walleij8d318a52010-03-30 15:33:42 +020025#include "ste_dma40_ll.h"
26
27#define D40_NAME "dma40"
28
29#define D40_PHY_CHAN -1
30
31/* For masking out/in 2 bit channel positions */
32#define D40_CHAN_POS(chan) (2 * (chan / 2))
33#define D40_CHAN_POS_MASK(chan) (0x3 << D40_CHAN_POS(chan))
34
35/* Maximum iterations taken before giving up suspending a channel */
36#define D40_SUSPEND_MAX_IT 500
37
Narayanan G7fb3e752011-11-17 17:26:41 +053038/* Milliseconds */
39#define DMA40_AUTOSUSPEND_DELAY 100
40
Linus Walleij508849a2010-06-20 21:26:07 +000041/* Hardware requirement on LCLA alignment */
42#define LCLA_ALIGNMENT 0x40000
Jonas Aaberg698e4732010-08-09 12:08:56 +000043
44/* Max number of links per event group */
45#define D40_LCLA_LINK_PER_EVENT_GRP 128
46#define D40_LCLA_END D40_LCLA_LINK_PER_EVENT_GRP
47
Linus Walleij508849a2010-06-20 21:26:07 +000048/* Attempts before giving up to trying to get pages that are aligned */
49#define MAX_LCLA_ALLOC_ATTEMPTS 256
50
51/* Bit markings for allocation map */
Linus Walleij8d318a52010-03-30 15:33:42 +020052#define D40_ALLOC_FREE (1 << 31)
53#define D40_ALLOC_PHY (1 << 30)
54#define D40_ALLOC_LOG_FREE 0
55
Linus Walleij8d318a52010-03-30 15:33:42 +020056/**
57 * enum 40_command - The different commands and/or statuses.
58 *
59 * @D40_DMA_STOP: DMA channel command STOP or status STOPPED,
60 * @D40_DMA_RUN: The DMA channel is RUNNING of the command RUN.
61 * @D40_DMA_SUSPEND_REQ: Request the DMA to SUSPEND as soon as possible.
62 * @D40_DMA_SUSPENDED: The DMA channel is SUSPENDED.
63 */
64enum d40_command {
65 D40_DMA_STOP = 0,
66 D40_DMA_RUN = 1,
67 D40_DMA_SUSPEND_REQ = 2,
68 D40_DMA_SUSPENDED = 3
69};
70
Narayanan G7fb3e752011-11-17 17:26:41 +053071/*
72 * These are the registers that has to be saved and later restored
73 * when the DMA hw is powered off.
74 * TODO: Add save/restore of D40_DREG_GCC on dma40 v3 or later, if that works.
75 */
76static u32 d40_backup_regs[] = {
77 D40_DREG_LCPA,
78 D40_DREG_LCLA,
79 D40_DREG_PRMSE,
80 D40_DREG_PRMSO,
81 D40_DREG_PRMOE,
82 D40_DREG_PRMOO,
83};
84
85#define BACKUP_REGS_SZ ARRAY_SIZE(d40_backup_regs)
86
87/* TODO: Check if all these registers have to be saved/restored on dma40 v3 */
88static u32 d40_backup_regs_v3[] = {
89 D40_DREG_PSEG1,
90 D40_DREG_PSEG2,
91 D40_DREG_PSEG3,
92 D40_DREG_PSEG4,
93 D40_DREG_PCEG1,
94 D40_DREG_PCEG2,
95 D40_DREG_PCEG3,
96 D40_DREG_PCEG4,
97 D40_DREG_RSEG1,
98 D40_DREG_RSEG2,
99 D40_DREG_RSEG3,
100 D40_DREG_RSEG4,
101 D40_DREG_RCEG1,
102 D40_DREG_RCEG2,
103 D40_DREG_RCEG3,
104 D40_DREG_RCEG4,
105};
106
107#define BACKUP_REGS_SZ_V3 ARRAY_SIZE(d40_backup_regs_v3)
108
109static u32 d40_backup_regs_chan[] = {
110 D40_CHAN_REG_SSCFG,
111 D40_CHAN_REG_SSELT,
112 D40_CHAN_REG_SSPTR,
113 D40_CHAN_REG_SSLNK,
114 D40_CHAN_REG_SDCFG,
115 D40_CHAN_REG_SDELT,
116 D40_CHAN_REG_SDPTR,
117 D40_CHAN_REG_SDLNK,
118};
119
Linus Walleij8d318a52010-03-30 15:33:42 +0200120/**
121 * struct d40_lli_pool - Structure for keeping LLIs in memory
122 *
123 * @base: Pointer to memory area when the pre_alloc_lli's are not large
124 * enough, IE bigger than the most common case, 1 dst and 1 src. NULL if
125 * pre_alloc_lli is used.
Rabin Vincentb00f9382011-01-25 11:18:15 +0100126 * @dma_addr: DMA address, if mapped
Linus Walleij8d318a52010-03-30 15:33:42 +0200127 * @size: The size in bytes of the memory at base or the size of pre_alloc_lli.
128 * @pre_alloc_lli: Pre allocated area for the most common case of transfers,
129 * one buffer to one buffer.
130 */
131struct d40_lli_pool {
132 void *base;
Linus Walleij508849a2010-06-20 21:26:07 +0000133 int size;
Rabin Vincentb00f9382011-01-25 11:18:15 +0100134 dma_addr_t dma_addr;
Linus Walleij8d318a52010-03-30 15:33:42 +0200135 /* Space for dst and src, plus an extra for padding */
Linus Walleij508849a2010-06-20 21:26:07 +0000136 u8 pre_alloc_lli[3 * sizeof(struct d40_phy_lli)];
Linus Walleij8d318a52010-03-30 15:33:42 +0200137};
138
139/**
140 * struct d40_desc - A descriptor is one DMA job.
141 *
142 * @lli_phy: LLI settings for physical channel. Both src and dst=
143 * points into the lli_pool, to base if lli_len > 1 or to pre_alloc_lli if
144 * lli_len equals one.
145 * @lli_log: Same as above but for logical channels.
146 * @lli_pool: The pool with two entries pre-allocated.
Per Friden941b77a2010-06-20 21:24:45 +0000147 * @lli_len: Number of llis of current descriptor.
Lucas De Marchi25985ed2011-03-30 22:57:33 -0300148 * @lli_current: Number of transferred llis.
Jonas Aaberg698e4732010-08-09 12:08:56 +0000149 * @lcla_alloc: Number of LCLA entries allocated.
Linus Walleij8d318a52010-03-30 15:33:42 +0200150 * @txd: DMA engine struct. Used for among other things for communication
151 * during a transfer.
152 * @node: List entry.
Linus Walleij8d318a52010-03-30 15:33:42 +0200153 * @is_in_client_list: true if the client owns this descriptor.
Narayanan G7fb3e752011-11-17 17:26:41 +0530154 * @cyclic: true if this is a cyclic job
Linus Walleij8d318a52010-03-30 15:33:42 +0200155 *
156 * This descriptor is used for both logical and physical transfers.
157 */
Linus Walleij8d318a52010-03-30 15:33:42 +0200158struct d40_desc {
159 /* LLI physical */
160 struct d40_phy_lli_bidir lli_phy;
161 /* LLI logical */
162 struct d40_log_lli_bidir lli_log;
163
164 struct d40_lli_pool lli_pool;
Per Friden941b77a2010-06-20 21:24:45 +0000165 int lli_len;
Jonas Aaberg698e4732010-08-09 12:08:56 +0000166 int lli_current;
167 int lcla_alloc;
Linus Walleij8d318a52010-03-30 15:33:42 +0200168
169 struct dma_async_tx_descriptor txd;
170 struct list_head node;
171
Linus Walleij8d318a52010-03-30 15:33:42 +0200172 bool is_in_client_list;
Rabin Vincent0c842b52011-01-25 11:18:35 +0100173 bool cyclic;
Linus Walleij8d318a52010-03-30 15:33:42 +0200174};
175
176/**
177 * struct d40_lcla_pool - LCLA pool settings and data.
178 *
Linus Walleij508849a2010-06-20 21:26:07 +0000179 * @base: The virtual address of LCLA. 18 bit aligned.
180 * @base_unaligned: The orignal kmalloc pointer, if kmalloc is used.
181 * This pointer is only there for clean-up on error.
182 * @pages: The number of pages needed for all physical channels.
183 * Only used later for clean-up on error
Linus Walleij8d318a52010-03-30 15:33:42 +0200184 * @lock: Lock to protect the content in this struct.
Jonas Aaberg698e4732010-08-09 12:08:56 +0000185 * @alloc_map: big map over which LCLA entry is own by which job.
Linus Walleij8d318a52010-03-30 15:33:42 +0200186 */
187struct d40_lcla_pool {
188 void *base;
Rabin Vincent026cbc42011-01-25 11:18:14 +0100189 dma_addr_t dma_addr;
Linus Walleij508849a2010-06-20 21:26:07 +0000190 void *base_unaligned;
191 int pages;
Linus Walleij8d318a52010-03-30 15:33:42 +0200192 spinlock_t lock;
Jonas Aaberg698e4732010-08-09 12:08:56 +0000193 struct d40_desc **alloc_map;
Linus Walleij8d318a52010-03-30 15:33:42 +0200194};
195
196/**
197 * struct d40_phy_res - struct for handling eventlines mapped to physical
198 * channels.
199 *
200 * @lock: A lock protection this entity.
Narayanan G7fb3e752011-11-17 17:26:41 +0530201 * @reserved: True if used by secure world or otherwise.
Linus Walleij8d318a52010-03-30 15:33:42 +0200202 * @num: The physical channel number of this entity.
203 * @allocated_src: Bit mapped to show which src event line's are mapped to
204 * this physical channel. Can also be free or physically allocated.
205 * @allocated_dst: Same as for src but is dst.
206 * allocated_dst and allocated_src uses the D40_ALLOC* defines as well as
Jonas Aaberg767a9672010-08-09 12:08:34 +0000207 * event line number.
Linus Walleij8d318a52010-03-30 15:33:42 +0200208 */
209struct d40_phy_res {
210 spinlock_t lock;
Narayanan G7fb3e752011-11-17 17:26:41 +0530211 bool reserved;
Linus Walleij8d318a52010-03-30 15:33:42 +0200212 int num;
213 u32 allocated_src;
214 u32 allocated_dst;
215};
216
217struct d40_base;
218
219/**
220 * struct d40_chan - Struct that describes a channel.
221 *
222 * @lock: A spinlock to protect this struct.
223 * @log_num: The logical number, if any of this channel.
Linus Walleij8d318a52010-03-30 15:33:42 +0200224 * @pending_tx: The number of pending transfers. Used between interrupt handler
225 * and tasklet.
226 * @busy: Set to true when transfer is ongoing on this channel.
Jonas Aaberg2a614342010-06-20 21:25:24 +0000227 * @phy_chan: Pointer to physical channel which this instance runs on. If this
228 * point is NULL, then the channel is not allocated.
Linus Walleij8d318a52010-03-30 15:33:42 +0200229 * @chan: DMA engine handle.
230 * @tasklet: Tasklet that gets scheduled from interrupt context to complete a
231 * transfer and call client callback.
232 * @client: Cliented owned descriptor list.
Per Forlinda063d22011-08-29 13:33:32 +0200233 * @pending_queue: Submitted jobs, to be issued by issue_pending()
Linus Walleij8d318a52010-03-30 15:33:42 +0200234 * @active: Active descriptor.
235 * @queue: Queued jobs.
Per Forlin82babbb362011-08-29 13:33:35 +0200236 * @prepare_queue: Prepared jobs.
Linus Walleij8d318a52010-03-30 15:33:42 +0200237 * @dma_cfg: The client configuration of this dma channel.
Rabin Vincentce2ca122010-10-12 13:00:49 +0000238 * @configured: whether the dma_cfg configuration is valid
Linus Walleij8d318a52010-03-30 15:33:42 +0200239 * @base: Pointer to the device instance struct.
240 * @src_def_cfg: Default cfg register setting for src.
241 * @dst_def_cfg: Default cfg register setting for dst.
242 * @log_def: Default logical channel settings.
Linus Walleij8d318a52010-03-30 15:33:42 +0200243 * @lcpa: Pointer to dst and src lcpa settings.
om prakashae752bf2011-06-27 11:33:31 +0200244 * @runtime_addr: runtime configured address.
245 * @runtime_direction: runtime configured direction.
Linus Walleij8d318a52010-03-30 15:33:42 +0200246 *
247 * This struct can either "be" a logical or a physical channel.
248 */
249struct d40_chan {
250 spinlock_t lock;
251 int log_num;
Linus Walleij8d318a52010-03-30 15:33:42 +0200252 int pending_tx;
253 bool busy;
254 struct d40_phy_res *phy_chan;
255 struct dma_chan chan;
256 struct tasklet_struct tasklet;
257 struct list_head client;
Per Forlina8f30672011-06-26 23:29:52 +0200258 struct list_head pending_queue;
Linus Walleij8d318a52010-03-30 15:33:42 +0200259 struct list_head active;
260 struct list_head queue;
Per Forlin82babbb362011-08-29 13:33:35 +0200261 struct list_head prepare_queue;
Linus Walleij8d318a52010-03-30 15:33:42 +0200262 struct stedma40_chan_cfg dma_cfg;
Rabin Vincentce2ca122010-10-12 13:00:49 +0000263 bool configured;
Linus Walleij8d318a52010-03-30 15:33:42 +0200264 struct d40_base *base;
265 /* Default register configurations */
266 u32 src_def_cfg;
267 u32 dst_def_cfg;
268 struct d40_def_lcsp log_def;
Linus Walleij8d318a52010-03-30 15:33:42 +0200269 struct d40_log_lli_full *lcpa;
Linus Walleij95e14002010-08-04 13:37:45 +0200270 /* Runtime reconfiguration */
271 dma_addr_t runtime_addr;
Vinod Kouldb8196d2011-10-13 22:34:23 +0530272 enum dma_transfer_direction runtime_direction;
Linus Walleij8d318a52010-03-30 15:33:42 +0200273};
274
275/**
276 * struct d40_base - The big global struct, one for each probe'd instance.
277 *
278 * @interrupt_lock: Lock used to make sure one interrupt is handle a time.
279 * @execmd_lock: Lock for execute command usage since several channels share
280 * the same physical register.
281 * @dev: The device structure.
282 * @virtbase: The virtual base address of the DMA's register.
Linus Walleijf4185592010-06-22 18:06:42 -0700283 * @rev: silicon revision detected.
Linus Walleij8d318a52010-03-30 15:33:42 +0200284 * @clk: Pointer to the DMA clock structure.
285 * @phy_start: Physical memory start of the DMA registers.
286 * @phy_size: Size of the DMA register map.
287 * @irq: The IRQ number.
288 * @num_phy_chans: The number of physical channels. Read from HW. This
289 * is the number of available channels for this driver, not counting "Secure
290 * mode" allocated physical channels.
291 * @num_log_chans: The number of logical channels. Calculated from
292 * num_phy_chans.
293 * @dma_both: dma_device channels that can do both memcpy and slave transfers.
294 * @dma_slave: dma_device channels that can do only do slave transfers.
295 * @dma_memcpy: dma_device channels that can do only do memcpy transfers.
Narayanan G7fb3e752011-11-17 17:26:41 +0530296 * @phy_chans: Room for all possible physical channels in system.
Linus Walleij8d318a52010-03-30 15:33:42 +0200297 * @log_chans: Room for all possible logical channels in system.
298 * @lookup_log_chans: Used to map interrupt number to logical channel. Points
299 * to log_chans entries.
300 * @lookup_phy_chans: Used to map interrupt number to physical channel. Points
301 * to phy_chans entries.
302 * @plat_data: Pointer to provided platform_data which is the driver
303 * configuration.
Narayanan G28c7a192011-11-22 13:56:55 +0530304 * @lcpa_regulator: Pointer to hold the regulator for the esram bank for lcla.
Linus Walleij8d318a52010-03-30 15:33:42 +0200305 * @phy_res: Vector containing all physical channels.
306 * @lcla_pool: lcla pool settings and data.
307 * @lcpa_base: The virtual mapped address of LCPA.
308 * @phy_lcpa: The physical address of the LCPA.
309 * @lcpa_size: The size of the LCPA area.
Jonas Aabergc675b1b2010-06-20 21:25:08 +0000310 * @desc_slab: cache for descriptors.
Narayanan G7fb3e752011-11-17 17:26:41 +0530311 * @reg_val_backup: Here the values of some hardware registers are stored
312 * before the DMA is powered off. They are restored when the power is back on.
313 * @reg_val_backup_v3: Backup of registers that only exits on dma40 v3 and
314 * later.
315 * @reg_val_backup_chan: Backup data for standard channel parameter registers.
316 * @gcc_pwr_off_mask: Mask to maintain the channels that can be turned off.
317 * @initialized: true if the dma has been initialized
Linus Walleij8d318a52010-03-30 15:33:42 +0200318 */
319struct d40_base {
320 spinlock_t interrupt_lock;
321 spinlock_t execmd_lock;
322 struct device *dev;
323 void __iomem *virtbase;
Linus Walleijf4185592010-06-22 18:06:42 -0700324 u8 rev:4;
Linus Walleij8d318a52010-03-30 15:33:42 +0200325 struct clk *clk;
326 phys_addr_t phy_start;
327 resource_size_t phy_size;
328 int irq;
329 int num_phy_chans;
330 int num_log_chans;
331 struct dma_device dma_both;
332 struct dma_device dma_slave;
333 struct dma_device dma_memcpy;
334 struct d40_chan *phy_chans;
335 struct d40_chan *log_chans;
336 struct d40_chan **lookup_log_chans;
337 struct d40_chan **lookup_phy_chans;
338 struct stedma40_platform_data *plat_data;
Narayanan G28c7a192011-11-22 13:56:55 +0530339 struct regulator *lcpa_regulator;
Linus Walleij8d318a52010-03-30 15:33:42 +0200340 /* Physical half channels */
341 struct d40_phy_res *phy_res;
342 struct d40_lcla_pool lcla_pool;
343 void *lcpa_base;
344 dma_addr_t phy_lcpa;
345 resource_size_t lcpa_size;
Jonas Aabergc675b1b2010-06-20 21:25:08 +0000346 struct kmem_cache *desc_slab;
Narayanan G7fb3e752011-11-17 17:26:41 +0530347 u32 reg_val_backup[BACKUP_REGS_SZ];
348 u32 reg_val_backup_v3[BACKUP_REGS_SZ_V3];
349 u32 *reg_val_backup_chan;
350 u16 gcc_pwr_off_mask;
351 bool initialized;
Linus Walleij8d318a52010-03-30 15:33:42 +0200352};
353
354/**
355 * struct d40_interrupt_lookup - lookup table for interrupt handler
356 *
357 * @src: Interrupt mask register.
358 * @clr: Interrupt clear register.
359 * @is_error: true if this is an error interrupt.
360 * @offset: start delta in the lookup_log_chans in d40_base. If equals to
361 * D40_PHY_CHAN, the lookup_phy_chans shall be used instead.
362 */
363struct d40_interrupt_lookup {
364 u32 src;
365 u32 clr;
366 bool is_error;
367 int offset;
368};
369
370/**
371 * struct d40_reg_val - simple lookup struct
372 *
373 * @reg: The register.
374 * @val: The value that belongs to the register in reg.
375 */
376struct d40_reg_val {
377 unsigned int reg;
378 unsigned int val;
379};
380
Rabin Vincent262d2912011-01-25 11:18:05 +0100381static struct device *chan2dev(struct d40_chan *d40c)
382{
383 return &d40c->chan.dev->device;
384}
385
Rabin Vincent724a8572011-01-25 11:18:08 +0100386static bool chan_is_physical(struct d40_chan *chan)
387{
388 return chan->log_num == D40_PHY_CHAN;
389}
390
391static bool chan_is_logical(struct d40_chan *chan)
392{
393 return !chan_is_physical(chan);
394}
395
Rabin Vincent8ca84682011-01-25 11:18:07 +0100396static void __iomem *chan_base(struct d40_chan *chan)
397{
398 return chan->base->virtbase + D40_DREG_PCBASE +
399 chan->phy_chan->num * D40_DREG_PCDELTA;
400}
401
Rabin Vincent6db5a8b2011-01-25 11:18:09 +0100402#define d40_err(dev, format, arg...) \
403 dev_err(dev, "[%s] " format, __func__, ## arg)
404
405#define chan_err(d40c, format, arg...) \
406 d40_err(chan2dev(d40c), format, ## arg)
407
Rabin Vincentb00f9382011-01-25 11:18:15 +0100408static int d40_pool_lli_alloc(struct d40_chan *d40c, struct d40_desc *d40d,
Rabin Vincentdbd88782011-01-25 11:18:19 +0100409 int lli_len)
Linus Walleij8d318a52010-03-30 15:33:42 +0200410{
Rabin Vincentdbd88782011-01-25 11:18:19 +0100411 bool is_log = chan_is_logical(d40c);
Linus Walleij8d318a52010-03-30 15:33:42 +0200412 u32 align;
413 void *base;
414
415 if (is_log)
416 align = sizeof(struct d40_log_lli);
417 else
418 align = sizeof(struct d40_phy_lli);
419
420 if (lli_len == 1) {
421 base = d40d->lli_pool.pre_alloc_lli;
422 d40d->lli_pool.size = sizeof(d40d->lli_pool.pre_alloc_lli);
423 d40d->lli_pool.base = NULL;
424 } else {
Rabin Vincent594ece42011-01-25 11:18:12 +0100425 d40d->lli_pool.size = lli_len * 2 * align;
Linus Walleij8d318a52010-03-30 15:33:42 +0200426
427 base = kmalloc(d40d->lli_pool.size + align, GFP_NOWAIT);
428 d40d->lli_pool.base = base;
429
430 if (d40d->lli_pool.base == NULL)
431 return -ENOMEM;
432 }
433
434 if (is_log) {
Rabin Vincentd924aba2011-01-25 11:18:16 +0100435 d40d->lli_log.src = PTR_ALIGN(base, align);
Rabin Vincent594ece42011-01-25 11:18:12 +0100436 d40d->lli_log.dst = d40d->lli_log.src + lli_len;
Rabin Vincentb00f9382011-01-25 11:18:15 +0100437
438 d40d->lli_pool.dma_addr = 0;
Linus Walleij8d318a52010-03-30 15:33:42 +0200439 } else {
Rabin Vincentd924aba2011-01-25 11:18:16 +0100440 d40d->lli_phy.src = PTR_ALIGN(base, align);
Rabin Vincent594ece42011-01-25 11:18:12 +0100441 d40d->lli_phy.dst = d40d->lli_phy.src + lli_len;
Rabin Vincentb00f9382011-01-25 11:18:15 +0100442
443 d40d->lli_pool.dma_addr = dma_map_single(d40c->base->dev,
444 d40d->lli_phy.src,
445 d40d->lli_pool.size,
446 DMA_TO_DEVICE);
447
448 if (dma_mapping_error(d40c->base->dev,
449 d40d->lli_pool.dma_addr)) {
450 kfree(d40d->lli_pool.base);
451 d40d->lli_pool.base = NULL;
452 d40d->lli_pool.dma_addr = 0;
453 return -ENOMEM;
454 }
Linus Walleij8d318a52010-03-30 15:33:42 +0200455 }
456
457 return 0;
458}
459
Rabin Vincentb00f9382011-01-25 11:18:15 +0100460static void d40_pool_lli_free(struct d40_chan *d40c, struct d40_desc *d40d)
Linus Walleij8d318a52010-03-30 15:33:42 +0200461{
Rabin Vincentb00f9382011-01-25 11:18:15 +0100462 if (d40d->lli_pool.dma_addr)
463 dma_unmap_single(d40c->base->dev, d40d->lli_pool.dma_addr,
464 d40d->lli_pool.size, DMA_TO_DEVICE);
465
Linus Walleij8d318a52010-03-30 15:33:42 +0200466 kfree(d40d->lli_pool.base);
467 d40d->lli_pool.base = NULL;
468 d40d->lli_pool.size = 0;
469 d40d->lli_log.src = NULL;
470 d40d->lli_log.dst = NULL;
471 d40d->lli_phy.src = NULL;
472 d40d->lli_phy.dst = NULL;
Linus Walleij8d318a52010-03-30 15:33:42 +0200473}
474
Jonas Aaberg698e4732010-08-09 12:08:56 +0000475static int d40_lcla_alloc_one(struct d40_chan *d40c,
476 struct d40_desc *d40d)
477{
478 unsigned long flags;
479 int i;
480 int ret = -EINVAL;
481 int p;
482
483 spin_lock_irqsave(&d40c->base->lcla_pool.lock, flags);
484
485 p = d40c->phy_chan->num * D40_LCLA_LINK_PER_EVENT_GRP;
486
487 /*
488 * Allocate both src and dst at the same time, therefore the half
489 * start on 1 since 0 can't be used since zero is used as end marker.
490 */
491 for (i = 1 ; i < D40_LCLA_LINK_PER_EVENT_GRP / 2; i++) {
492 if (!d40c->base->lcla_pool.alloc_map[p + i]) {
493 d40c->base->lcla_pool.alloc_map[p + i] = d40d;
494 d40d->lcla_alloc++;
495 ret = i;
496 break;
497 }
498 }
499
500 spin_unlock_irqrestore(&d40c->base->lcla_pool.lock, flags);
501
502 return ret;
503}
504
505static int d40_lcla_free_all(struct d40_chan *d40c,
506 struct d40_desc *d40d)
507{
508 unsigned long flags;
509 int i;
510 int ret = -EINVAL;
511
Rabin Vincent724a8572011-01-25 11:18:08 +0100512 if (chan_is_physical(d40c))
Jonas Aaberg698e4732010-08-09 12:08:56 +0000513 return 0;
514
515 spin_lock_irqsave(&d40c->base->lcla_pool.lock, flags);
516
517 for (i = 1 ; i < D40_LCLA_LINK_PER_EVENT_GRP / 2; i++) {
518 if (d40c->base->lcla_pool.alloc_map[d40c->phy_chan->num *
519 D40_LCLA_LINK_PER_EVENT_GRP + i] == d40d) {
520 d40c->base->lcla_pool.alloc_map[d40c->phy_chan->num *
521 D40_LCLA_LINK_PER_EVENT_GRP + i] = NULL;
522 d40d->lcla_alloc--;
523 if (d40d->lcla_alloc == 0) {
524 ret = 0;
525 break;
526 }
527 }
528 }
529
530 spin_unlock_irqrestore(&d40c->base->lcla_pool.lock, flags);
531
532 return ret;
533
534}
535
Linus Walleij8d318a52010-03-30 15:33:42 +0200536static void d40_desc_remove(struct d40_desc *d40d)
537{
538 list_del(&d40d->node);
539}
540
541static struct d40_desc *d40_desc_get(struct d40_chan *d40c)
542{
Rabin Vincenta2c15fa2010-10-06 08:20:37 +0000543 struct d40_desc *desc = NULL;
Linus Walleij8d318a52010-03-30 15:33:42 +0200544
545 if (!list_empty(&d40c->client)) {
Rabin Vincenta2c15fa2010-10-06 08:20:37 +0000546 struct d40_desc *d;
547 struct d40_desc *_d;
548
Narayanan G7fb3e752011-11-17 17:26:41 +0530549 list_for_each_entry_safe(d, _d, &d40c->client, node) {
Linus Walleij8d318a52010-03-30 15:33:42 +0200550 if (async_tx_test_ack(&d->txd)) {
Linus Walleij8d318a52010-03-30 15:33:42 +0200551 d40_desc_remove(d);
Rabin Vincenta2c15fa2010-10-06 08:20:37 +0000552 desc = d;
553 memset(desc, 0, sizeof(*desc));
Jonas Aabergc675b1b2010-06-20 21:25:08 +0000554 break;
Linus Walleij8d318a52010-03-30 15:33:42 +0200555 }
Narayanan G7fb3e752011-11-17 17:26:41 +0530556 }
Linus Walleij8d318a52010-03-30 15:33:42 +0200557 }
Rabin Vincenta2c15fa2010-10-06 08:20:37 +0000558
559 if (!desc)
560 desc = kmem_cache_zalloc(d40c->base->desc_slab, GFP_NOWAIT);
561
562 if (desc)
563 INIT_LIST_HEAD(&desc->node);
564
565 return desc;
Linus Walleij8d318a52010-03-30 15:33:42 +0200566}
567
568static void d40_desc_free(struct d40_chan *d40c, struct d40_desc *d40d)
569{
Jonas Aaberg698e4732010-08-09 12:08:56 +0000570
Rabin Vincentb00f9382011-01-25 11:18:15 +0100571 d40_pool_lli_free(d40c, d40d);
Jonas Aaberg698e4732010-08-09 12:08:56 +0000572 d40_lcla_free_all(d40c, d40d);
Jonas Aabergc675b1b2010-06-20 21:25:08 +0000573 kmem_cache_free(d40c->base->desc_slab, d40d);
Linus Walleij8d318a52010-03-30 15:33:42 +0200574}
575
576static void d40_desc_submit(struct d40_chan *d40c, struct d40_desc *desc)
577{
578 list_add_tail(&desc->node, &d40c->active);
579}
580
Rabin Vincent1c4b0922011-01-25 11:18:24 +0100581static void d40_phy_lli_load(struct d40_chan *chan, struct d40_desc *desc)
582{
583 struct d40_phy_lli *lli_dst = desc->lli_phy.dst;
584 struct d40_phy_lli *lli_src = desc->lli_phy.src;
585 void __iomem *base = chan_base(chan);
586
587 writel(lli_src->reg_cfg, base + D40_CHAN_REG_SSCFG);
588 writel(lli_src->reg_elt, base + D40_CHAN_REG_SSELT);
589 writel(lli_src->reg_ptr, base + D40_CHAN_REG_SSPTR);
590 writel(lli_src->reg_lnk, base + D40_CHAN_REG_SSLNK);
591
592 writel(lli_dst->reg_cfg, base + D40_CHAN_REG_SDCFG);
593 writel(lli_dst->reg_elt, base + D40_CHAN_REG_SDELT);
594 writel(lli_dst->reg_ptr, base + D40_CHAN_REG_SDPTR);
595 writel(lli_dst->reg_lnk, base + D40_CHAN_REG_SDLNK);
596}
597
Rabin Vincente65889c2011-01-25 11:18:31 +0100598static void d40_log_lli_to_lcxa(struct d40_chan *chan, struct d40_desc *desc)
599{
600 struct d40_lcla_pool *pool = &chan->base->lcla_pool;
601 struct d40_log_lli_bidir *lli = &desc->lli_log;
602 int lli_current = desc->lli_current;
603 int lli_len = desc->lli_len;
Rabin Vincent0c842b52011-01-25 11:18:35 +0100604 bool cyclic = desc->cyclic;
Rabin Vincente65889c2011-01-25 11:18:31 +0100605 int curr_lcla = -EINVAL;
Rabin Vincent0c842b52011-01-25 11:18:35 +0100606 int first_lcla = 0;
Narayanan G28c7a192011-11-22 13:56:55 +0530607 bool use_esram_lcla = chan->base->plat_data->use_esram_lcla;
Rabin Vincent0c842b52011-01-25 11:18:35 +0100608 bool linkback;
Rabin Vincente65889c2011-01-25 11:18:31 +0100609
Rabin Vincent0c842b52011-01-25 11:18:35 +0100610 /*
611 * We may have partially running cyclic transfers, in case we did't get
612 * enough LCLA entries.
613 */
614 linkback = cyclic && lli_current == 0;
615
616 /*
617 * For linkback, we need one LCLA even with only one link, because we
618 * can't link back to the one in LCPA space
619 */
620 if (linkback || (lli_len - lli_current > 1)) {
Rabin Vincente65889c2011-01-25 11:18:31 +0100621 curr_lcla = d40_lcla_alloc_one(chan, desc);
Rabin Vincent0c842b52011-01-25 11:18:35 +0100622 first_lcla = curr_lcla;
623 }
Rabin Vincente65889c2011-01-25 11:18:31 +0100624
Rabin Vincent0c842b52011-01-25 11:18:35 +0100625 /*
626 * For linkback, we normally load the LCPA in the loop since we need to
627 * link it to the second LCLA and not the first. However, if we
628 * couldn't even get a first LCLA, then we have to run in LCPA and
629 * reload manually.
630 */
631 if (!linkback || curr_lcla == -EINVAL) {
632 unsigned int flags = 0;
Rabin Vincente65889c2011-01-25 11:18:31 +0100633
Rabin Vincent0c842b52011-01-25 11:18:35 +0100634 if (curr_lcla == -EINVAL)
635 flags |= LLI_TERM_INT;
636
637 d40_log_lli_lcpa_write(chan->lcpa,
638 &lli->dst[lli_current],
639 &lli->src[lli_current],
640 curr_lcla,
641 flags);
642 lli_current++;
643 }
Rabin Vincent6045f0b2011-01-25 11:18:32 +0100644
645 if (curr_lcla < 0)
646 goto out;
647
Rabin Vincente65889c2011-01-25 11:18:31 +0100648 for (; lli_current < lli_len; lli_current++) {
649 unsigned int lcla_offset = chan->phy_chan->num * 1024 +
650 8 * curr_lcla * 2;
651 struct d40_log_lli *lcla = pool->base + lcla_offset;
Rabin Vincent0c842b52011-01-25 11:18:35 +0100652 unsigned int flags = 0;
Rabin Vincente65889c2011-01-25 11:18:31 +0100653 int next_lcla;
654
655 if (lli_current + 1 < lli_len)
656 next_lcla = d40_lcla_alloc_one(chan, desc);
657 else
Rabin Vincent0c842b52011-01-25 11:18:35 +0100658 next_lcla = linkback ? first_lcla : -EINVAL;
Rabin Vincente65889c2011-01-25 11:18:31 +0100659
Rabin Vincent0c842b52011-01-25 11:18:35 +0100660 if (cyclic || next_lcla == -EINVAL)
661 flags |= LLI_TERM_INT;
662
663 if (linkback && curr_lcla == first_lcla) {
664 /* First link goes in both LCPA and LCLA */
665 d40_log_lli_lcpa_write(chan->lcpa,
666 &lli->dst[lli_current],
667 &lli->src[lli_current],
668 next_lcla, flags);
669 }
670
671 /*
672 * One unused LCLA in the cyclic case if the very first
673 * next_lcla fails...
674 */
Rabin Vincente65889c2011-01-25 11:18:31 +0100675 d40_log_lli_lcla_write(lcla,
676 &lli->dst[lli_current],
677 &lli->src[lli_current],
Rabin Vincent0c842b52011-01-25 11:18:35 +0100678 next_lcla, flags);
Rabin Vincente65889c2011-01-25 11:18:31 +0100679
Narayanan G28c7a192011-11-22 13:56:55 +0530680 /*
681 * Cache maintenance is not needed if lcla is
682 * mapped in esram
683 */
684 if (!use_esram_lcla) {
685 dma_sync_single_range_for_device(chan->base->dev,
686 pool->dma_addr, lcla_offset,
687 2 * sizeof(struct d40_log_lli),
688 DMA_TO_DEVICE);
689 }
Rabin Vincente65889c2011-01-25 11:18:31 +0100690 curr_lcla = next_lcla;
691
Rabin Vincent0c842b52011-01-25 11:18:35 +0100692 if (curr_lcla == -EINVAL || curr_lcla == first_lcla) {
Rabin Vincente65889c2011-01-25 11:18:31 +0100693 lli_current++;
694 break;
695 }
696 }
697
Rabin Vincent6045f0b2011-01-25 11:18:32 +0100698out:
Rabin Vincente65889c2011-01-25 11:18:31 +0100699 desc->lli_current = lli_current;
700}
701
Jonas Aaberg698e4732010-08-09 12:08:56 +0000702static void d40_desc_load(struct d40_chan *d40c, struct d40_desc *d40d)
703{
Rabin Vincent724a8572011-01-25 11:18:08 +0100704 if (chan_is_physical(d40c)) {
Rabin Vincent1c4b0922011-01-25 11:18:24 +0100705 d40_phy_lli_load(d40c, d40d);
Jonas Aaberg698e4732010-08-09 12:08:56 +0000706 d40d->lli_current = d40d->lli_len;
Rabin Vincente65889c2011-01-25 11:18:31 +0100707 } else
708 d40_log_lli_to_lcxa(d40c, d40d);
Jonas Aaberg698e4732010-08-09 12:08:56 +0000709}
710
Linus Walleij8d318a52010-03-30 15:33:42 +0200711static struct d40_desc *d40_first_active_get(struct d40_chan *d40c)
712{
713 struct d40_desc *d;
714
715 if (list_empty(&d40c->active))
716 return NULL;
717
718 d = list_first_entry(&d40c->active,
719 struct d40_desc,
720 node);
721 return d;
722}
723
Per Forlin74043682011-08-29 13:33:34 +0200724/* remove desc from current queue and add it to the pending_queue */
Linus Walleij8d318a52010-03-30 15:33:42 +0200725static void d40_desc_queue(struct d40_chan *d40c, struct d40_desc *desc)
726{
Per Forlin74043682011-08-29 13:33:34 +0200727 d40_desc_remove(desc);
728 desc->is_in_client_list = false;
Per Forlina8f30672011-06-26 23:29:52 +0200729 list_add_tail(&desc->node, &d40c->pending_queue);
730}
731
732static struct d40_desc *d40_first_pending(struct d40_chan *d40c)
733{
734 struct d40_desc *d;
735
736 if (list_empty(&d40c->pending_queue))
737 return NULL;
738
739 d = list_first_entry(&d40c->pending_queue,
740 struct d40_desc,
741 node);
742 return d;
Linus Walleij8d318a52010-03-30 15:33:42 +0200743}
744
745static struct d40_desc *d40_first_queued(struct d40_chan *d40c)
746{
747 struct d40_desc *d;
748
749 if (list_empty(&d40c->queue))
750 return NULL;
751
752 d = list_first_entry(&d40c->queue,
753 struct d40_desc,
754 node);
755 return d;
756}
757
Per Forlind49278e2010-12-20 18:31:38 +0100758static int d40_psize_2_burst_size(bool is_log, int psize)
759{
760 if (is_log) {
761 if (psize == STEDMA40_PSIZE_LOG_1)
762 return 1;
763 } else {
764 if (psize == STEDMA40_PSIZE_PHY_1)
765 return 1;
766 }
Linus Walleij8d318a52010-03-30 15:33:42 +0200767
Per Forlind49278e2010-12-20 18:31:38 +0100768 return 2 << psize;
769}
770
771/*
772 * The dma only supports transmitting packages up to
773 * STEDMA40_MAX_SEG_SIZE << data_width. Calculate the total number of
774 * dma elements required to send the entire sg list
775 */
776static int d40_size_2_dmalen(int size, u32 data_width1, u32 data_width2)
777{
778 int dmalen;
779 u32 max_w = max(data_width1, data_width2);
780 u32 min_w = min(data_width1, data_width2);
781 u32 seg_max = ALIGN(STEDMA40_MAX_SEG_SIZE << min_w, 1 << max_w);
782
783 if (seg_max > STEDMA40_MAX_SEG_SIZE)
784 seg_max -= (1 << max_w);
785
786 if (!IS_ALIGNED(size, 1 << max_w))
787 return -EINVAL;
788
789 if (size <= seg_max)
790 dmalen = 1;
791 else {
792 dmalen = size / seg_max;
793 if (dmalen * seg_max < size)
794 dmalen++;
795 }
796 return dmalen;
797}
798
799static int d40_sg_2_dmalen(struct scatterlist *sgl, int sg_len,
800 u32 data_width1, u32 data_width2)
801{
802 struct scatterlist *sg;
803 int i;
804 int len = 0;
805 int ret;
806
807 for_each_sg(sgl, sg, sg_len, i) {
808 ret = d40_size_2_dmalen(sg_dma_len(sg),
809 data_width1, data_width2);
810 if (ret < 0)
811 return ret;
812 len += ret;
813 }
814 return len;
815}
816
Narayanan G7fb3e752011-11-17 17:26:41 +0530817
818#ifdef CONFIG_PM
819static void dma40_backup(void __iomem *baseaddr, u32 *backup,
820 u32 *regaddr, int num, bool save)
821{
822 int i;
823
824 for (i = 0; i < num; i++) {
825 void __iomem *addr = baseaddr + regaddr[i];
826
827 if (save)
828 backup[i] = readl_relaxed(addr);
829 else
830 writel_relaxed(backup[i], addr);
831 }
832}
833
834static void d40_save_restore_registers(struct d40_base *base, bool save)
835{
836 int i;
837
838 /* Save/Restore channel specific registers */
839 for (i = 0; i < base->num_phy_chans; i++) {
840 void __iomem *addr;
841 int idx;
842
843 if (base->phy_res[i].reserved)
844 continue;
845
846 addr = base->virtbase + D40_DREG_PCBASE + i * D40_DREG_PCDELTA;
847 idx = i * ARRAY_SIZE(d40_backup_regs_chan);
848
849 dma40_backup(addr, &base->reg_val_backup_chan[idx],
850 d40_backup_regs_chan,
851 ARRAY_SIZE(d40_backup_regs_chan),
852 save);
853 }
854
855 /* Save/Restore global registers */
856 dma40_backup(base->virtbase, base->reg_val_backup,
857 d40_backup_regs, ARRAY_SIZE(d40_backup_regs),
858 save);
859
860 /* Save/Restore registers only existing on dma40 v3 and later */
861 if (base->rev >= 3)
862 dma40_backup(base->virtbase, base->reg_val_backup_v3,
863 d40_backup_regs_v3,
864 ARRAY_SIZE(d40_backup_regs_v3),
865 save);
866}
867#else
868static void d40_save_restore_registers(struct d40_base *base, bool save)
869{
870}
871#endif
Linus Walleij8d318a52010-03-30 15:33:42 +0200872
873static int d40_channel_execute_command(struct d40_chan *d40c,
874 enum d40_command command)
875{
Jonas Aaberg767a9672010-08-09 12:08:34 +0000876 u32 status;
877 int i;
Linus Walleij8d318a52010-03-30 15:33:42 +0200878 void __iomem *active_reg;
879 int ret = 0;
880 unsigned long flags;
Jonas Aaberg1d392a72010-06-20 21:26:01 +0000881 u32 wmask;
Linus Walleij8d318a52010-03-30 15:33:42 +0200882
883 spin_lock_irqsave(&d40c->base->execmd_lock, flags);
884
885 if (d40c->phy_chan->num % 2 == 0)
886 active_reg = d40c->base->virtbase + D40_DREG_ACTIVE;
887 else
888 active_reg = d40c->base->virtbase + D40_DREG_ACTIVO;
889
890 if (command == D40_DMA_SUSPEND_REQ) {
891 status = (readl(active_reg) &
892 D40_CHAN_POS_MASK(d40c->phy_chan->num)) >>
893 D40_CHAN_POS(d40c->phy_chan->num);
894
895 if (status == D40_DMA_SUSPENDED || status == D40_DMA_STOP)
896 goto done;
897 }
898
Jonas Aaberg1d392a72010-06-20 21:26:01 +0000899 wmask = 0xffffffff & ~(D40_CHAN_POS_MASK(d40c->phy_chan->num));
900 writel(wmask | (command << D40_CHAN_POS(d40c->phy_chan->num)),
901 active_reg);
Linus Walleij8d318a52010-03-30 15:33:42 +0200902
903 if (command == D40_DMA_SUSPEND_REQ) {
904
905 for (i = 0 ; i < D40_SUSPEND_MAX_IT; i++) {
906 status = (readl(active_reg) &
907 D40_CHAN_POS_MASK(d40c->phy_chan->num)) >>
908 D40_CHAN_POS(d40c->phy_chan->num);
909
910 cpu_relax();
911 /*
912 * Reduce the number of bus accesses while
913 * waiting for the DMA to suspend.
914 */
915 udelay(3);
916
917 if (status == D40_DMA_STOP ||
918 status == D40_DMA_SUSPENDED)
919 break;
920 }
921
922 if (i == D40_SUSPEND_MAX_IT) {
Rabin Vincent6db5a8b2011-01-25 11:18:09 +0100923 chan_err(d40c,
924 "unable to suspend the chl %d (log: %d) status %x\n",
925 d40c->phy_chan->num, d40c->log_num,
Linus Walleij8d318a52010-03-30 15:33:42 +0200926 status);
927 dump_stack();
928 ret = -EBUSY;
929 }
930
931 }
932done:
933 spin_unlock_irqrestore(&d40c->base->execmd_lock, flags);
934 return ret;
935}
936
937static void d40_term_all(struct d40_chan *d40c)
938{
939 struct d40_desc *d40d;
Per Forlin74043682011-08-29 13:33:34 +0200940 struct d40_desc *_d;
Linus Walleij8d318a52010-03-30 15:33:42 +0200941
942 /* Release active descriptors */
943 while ((d40d = d40_first_active_get(d40c))) {
944 d40_desc_remove(d40d);
Linus Walleij8d318a52010-03-30 15:33:42 +0200945 d40_desc_free(d40c, d40d);
946 }
947
948 /* Release queued descriptors waiting for transfer */
949 while ((d40d = d40_first_queued(d40c))) {
950 d40_desc_remove(d40d);
Linus Walleij8d318a52010-03-30 15:33:42 +0200951 d40_desc_free(d40c, d40d);
952 }
953
Per Forlina8f30672011-06-26 23:29:52 +0200954 /* Release pending descriptors */
955 while ((d40d = d40_first_pending(d40c))) {
956 d40_desc_remove(d40d);
957 d40_desc_free(d40c, d40d);
958 }
Linus Walleij8d318a52010-03-30 15:33:42 +0200959
Per Forlin74043682011-08-29 13:33:34 +0200960 /* Release client owned descriptors */
961 if (!list_empty(&d40c->client))
962 list_for_each_entry_safe(d40d, _d, &d40c->client, node) {
963 d40_desc_remove(d40d);
964 d40_desc_free(d40c, d40d);
965 }
966
Per Forlin82babbb362011-08-29 13:33:35 +0200967 /* Release descriptors in prepare queue */
968 if (!list_empty(&d40c->prepare_queue))
969 list_for_each_entry_safe(d40d, _d,
970 &d40c->prepare_queue, node) {
971 d40_desc_remove(d40d);
972 d40_desc_free(d40c, d40d);
973 }
Per Forlin74043682011-08-29 13:33:34 +0200974
Linus Walleij8d318a52010-03-30 15:33:42 +0200975 d40c->pending_tx = 0;
976 d40c->busy = false;
977}
978
Rabin Vincent262d2912011-01-25 11:18:05 +0100979static void __d40_config_set_event(struct d40_chan *d40c, bool enable,
980 u32 event, int reg)
981{
Rabin Vincent8ca84682011-01-25 11:18:07 +0100982 void __iomem *addr = chan_base(d40c) + reg;
Rabin Vincent262d2912011-01-25 11:18:05 +0100983 int tries;
984
985 if (!enable) {
986 writel((D40_DEACTIVATE_EVENTLINE << D40_EVENTLINE_POS(event))
987 | ~D40_EVENTLINE_MASK(event), addr);
988 return;
989 }
990
991 /*
992 * The hardware sometimes doesn't register the enable when src and dst
993 * event lines are active on the same logical channel. Retry to ensure
994 * it does. Usually only one retry is sufficient.
995 */
996 tries = 100;
997 while (--tries) {
998 writel((D40_ACTIVATE_EVENTLINE << D40_EVENTLINE_POS(event))
999 | ~D40_EVENTLINE_MASK(event), addr);
1000
1001 if (readl(addr) & D40_EVENTLINE_MASK(event))
1002 break;
1003 }
1004
1005 if (tries != 99)
1006 dev_dbg(chan2dev(d40c),
1007 "[%s] workaround enable S%cLNK (%d tries)\n",
1008 __func__, reg == D40_CHAN_REG_SSLNK ? 'S' : 'D',
1009 100 - tries);
1010
1011 WARN_ON(!tries);
1012}
1013
Linus Walleij8d318a52010-03-30 15:33:42 +02001014static void d40_config_set_event(struct d40_chan *d40c, bool do_enable)
1015{
Linus Walleij8d318a52010-03-30 15:33:42 +02001016 unsigned long flags;
1017
Linus Walleij8d318a52010-03-30 15:33:42 +02001018 spin_lock_irqsave(&d40c->phy_chan->lock, flags);
1019
1020 /* Enable event line connected to device (or memcpy) */
1021 if ((d40c->dma_cfg.dir == STEDMA40_PERIPH_TO_MEM) ||
1022 (d40c->dma_cfg.dir == STEDMA40_PERIPH_TO_PERIPH)) {
1023 u32 event = D40_TYPE_TO_EVENT(d40c->dma_cfg.src_dev_type);
1024
Rabin Vincent262d2912011-01-25 11:18:05 +01001025 __d40_config_set_event(d40c, do_enable, event,
1026 D40_CHAN_REG_SSLNK);
Linus Walleij8d318a52010-03-30 15:33:42 +02001027 }
Rabin Vincent262d2912011-01-25 11:18:05 +01001028
Linus Walleij8d318a52010-03-30 15:33:42 +02001029 if (d40c->dma_cfg.dir != STEDMA40_PERIPH_TO_MEM) {
1030 u32 event = D40_TYPE_TO_EVENT(d40c->dma_cfg.dst_dev_type);
1031
Rabin Vincent262d2912011-01-25 11:18:05 +01001032 __d40_config_set_event(d40c, do_enable, event,
1033 D40_CHAN_REG_SDLNK);
Linus Walleij8d318a52010-03-30 15:33:42 +02001034 }
1035
1036 spin_unlock_irqrestore(&d40c->phy_chan->lock, flags);
1037}
1038
Jonas Aaberga5ebca42010-05-18 00:41:09 +02001039static u32 d40_chan_has_events(struct d40_chan *d40c)
Linus Walleij8d318a52010-03-30 15:33:42 +02001040{
Rabin Vincent8ca84682011-01-25 11:18:07 +01001041 void __iomem *chanbase = chan_base(d40c);
Jonas Aabergbe8cb7d2010-08-09 12:07:44 +00001042 u32 val;
Linus Walleij8d318a52010-03-30 15:33:42 +02001043
Rabin Vincent8ca84682011-01-25 11:18:07 +01001044 val = readl(chanbase + D40_CHAN_REG_SSLNK);
1045 val |= readl(chanbase + D40_CHAN_REG_SDLNK);
Linus Walleij8d318a52010-03-30 15:33:42 +02001046
Jonas Aaberga5ebca42010-05-18 00:41:09 +02001047 return val;
Linus Walleij8d318a52010-03-30 15:33:42 +02001048}
1049
Rabin Vincent20a5b6d2010-10-12 13:00:52 +00001050static u32 d40_get_prmo(struct d40_chan *d40c)
1051{
1052 static const unsigned int phy_map[] = {
1053 [STEDMA40_PCHAN_BASIC_MODE]
1054 = D40_DREG_PRMO_PCHAN_BASIC,
1055 [STEDMA40_PCHAN_MODULO_MODE]
1056 = D40_DREG_PRMO_PCHAN_MODULO,
1057 [STEDMA40_PCHAN_DOUBLE_DST_MODE]
1058 = D40_DREG_PRMO_PCHAN_DOUBLE_DST,
1059 };
1060 static const unsigned int log_map[] = {
1061 [STEDMA40_LCHAN_SRC_PHY_DST_LOG]
1062 = D40_DREG_PRMO_LCHAN_SRC_PHY_DST_LOG,
1063 [STEDMA40_LCHAN_SRC_LOG_DST_PHY]
1064 = D40_DREG_PRMO_LCHAN_SRC_LOG_DST_PHY,
1065 [STEDMA40_LCHAN_SRC_LOG_DST_LOG]
1066 = D40_DREG_PRMO_LCHAN_SRC_LOG_DST_LOG,
1067 };
1068
Rabin Vincent724a8572011-01-25 11:18:08 +01001069 if (chan_is_physical(d40c))
Rabin Vincent20a5b6d2010-10-12 13:00:52 +00001070 return phy_map[d40c->dma_cfg.mode_opt];
1071 else
1072 return log_map[d40c->dma_cfg.mode_opt];
1073}
1074
Jonas Aabergb55912c2010-08-09 12:08:02 +00001075static void d40_config_write(struct d40_chan *d40c)
Linus Walleij8d318a52010-03-30 15:33:42 +02001076{
1077 u32 addr_base;
1078 u32 var;
Linus Walleij8d318a52010-03-30 15:33:42 +02001079
1080 /* Odd addresses are even addresses + 4 */
1081 addr_base = (d40c->phy_chan->num % 2) * 4;
1082 /* Setup channel mode to logical or physical */
Rabin Vincent724a8572011-01-25 11:18:08 +01001083 var = ((u32)(chan_is_logical(d40c)) + 1) <<
Linus Walleij8d318a52010-03-30 15:33:42 +02001084 D40_CHAN_POS(d40c->phy_chan->num);
1085 writel(var, d40c->base->virtbase + D40_DREG_PRMSE + addr_base);
1086
1087 /* Setup operational mode option register */
Rabin Vincent20a5b6d2010-10-12 13:00:52 +00001088 var = d40_get_prmo(d40c) << D40_CHAN_POS(d40c->phy_chan->num);
Linus Walleij8d318a52010-03-30 15:33:42 +02001089
1090 writel(var, d40c->base->virtbase + D40_DREG_PRMOE + addr_base);
1091
Rabin Vincent724a8572011-01-25 11:18:08 +01001092 if (chan_is_logical(d40c)) {
Rabin Vincent8ca84682011-01-25 11:18:07 +01001093 int lidx = (d40c->phy_chan->num << D40_SREG_ELEM_LOG_LIDX_POS)
1094 & D40_SREG_ELEM_LOG_LIDX_MASK;
1095 void __iomem *chanbase = chan_base(d40c);
1096
Linus Walleij8d318a52010-03-30 15:33:42 +02001097 /* Set default config for CFG reg */
Rabin Vincent8ca84682011-01-25 11:18:07 +01001098 writel(d40c->src_def_cfg, chanbase + D40_CHAN_REG_SSCFG);
1099 writel(d40c->dst_def_cfg, chanbase + D40_CHAN_REG_SDCFG);
Linus Walleij8d318a52010-03-30 15:33:42 +02001100
Jonas Aabergb55912c2010-08-09 12:08:02 +00001101 /* Set LIDX for lcla */
Rabin Vincent8ca84682011-01-25 11:18:07 +01001102 writel(lidx, chanbase + D40_CHAN_REG_SSELT);
1103 writel(lidx, chanbase + D40_CHAN_REG_SDELT);
Rabin Vincente9f3a492011-12-28 11:27:40 +05301104
1105 /* Clear LNK which will be used by d40_chan_has_events() */
1106 writel(0, chanbase + D40_CHAN_REG_SSLNK);
1107 writel(0, chanbase + D40_CHAN_REG_SDLNK);
Linus Walleij8d318a52010-03-30 15:33:42 +02001108 }
Linus Walleij8d318a52010-03-30 15:33:42 +02001109}
1110
Jonas Aabergaa182ae2010-08-09 12:08:26 +00001111static u32 d40_residue(struct d40_chan *d40c)
1112{
1113 u32 num_elt;
1114
Rabin Vincent724a8572011-01-25 11:18:08 +01001115 if (chan_is_logical(d40c))
Jonas Aabergaa182ae2010-08-09 12:08:26 +00001116 num_elt = (readl(&d40c->lcpa->lcsp2) & D40_MEM_LCSP2_ECNT_MASK)
1117 >> D40_MEM_LCSP2_ECNT_POS;
Rabin Vincent8ca84682011-01-25 11:18:07 +01001118 else {
1119 u32 val = readl(chan_base(d40c) + D40_CHAN_REG_SDELT);
1120 num_elt = (val & D40_SREG_ELEM_PHY_ECNT_MASK)
1121 >> D40_SREG_ELEM_PHY_ECNT_POS;
1122 }
1123
Jonas Aabergaa182ae2010-08-09 12:08:26 +00001124 return num_elt * (1 << d40c->dma_cfg.dst_info.data_width);
1125}
1126
1127static bool d40_tx_is_linked(struct d40_chan *d40c)
1128{
1129 bool is_link;
1130
Rabin Vincent724a8572011-01-25 11:18:08 +01001131 if (chan_is_logical(d40c))
Jonas Aabergaa182ae2010-08-09 12:08:26 +00001132 is_link = readl(&d40c->lcpa->lcsp3) & D40_MEM_LCSP3_DLOS_MASK;
1133 else
Rabin Vincent8ca84682011-01-25 11:18:07 +01001134 is_link = readl(chan_base(d40c) + D40_CHAN_REG_SDLNK)
1135 & D40_SREG_LNK_PHYS_LNK_MASK;
1136
Jonas Aabergaa182ae2010-08-09 12:08:26 +00001137 return is_link;
1138}
1139
Rabin Vincent86eb5fb2011-01-25 11:18:34 +01001140static int d40_pause(struct d40_chan *d40c)
Jonas Aabergaa182ae2010-08-09 12:08:26 +00001141{
Jonas Aabergaa182ae2010-08-09 12:08:26 +00001142 int res = 0;
1143 unsigned long flags;
1144
Jonas Aaberg3ac012a2010-08-09 12:09:12 +00001145 if (!d40c->busy)
1146 return 0;
1147
Narayanan G7fb3e752011-11-17 17:26:41 +05301148 pm_runtime_get_sync(d40c->base->dev);
Jonas Aabergaa182ae2010-08-09 12:08:26 +00001149 spin_lock_irqsave(&d40c->lock, flags);
1150
1151 res = d40_channel_execute_command(d40c, D40_DMA_SUSPEND_REQ);
1152 if (res == 0) {
Rabin Vincent724a8572011-01-25 11:18:08 +01001153 if (chan_is_logical(d40c)) {
Jonas Aabergaa182ae2010-08-09 12:08:26 +00001154 d40_config_set_event(d40c, false);
1155 /* Resume the other logical channels if any */
1156 if (d40_chan_has_events(d40c))
1157 res = d40_channel_execute_command(d40c,
1158 D40_DMA_RUN);
1159 }
1160 }
Narayanan G7fb3e752011-11-17 17:26:41 +05301161 pm_runtime_mark_last_busy(d40c->base->dev);
1162 pm_runtime_put_autosuspend(d40c->base->dev);
Jonas Aabergaa182ae2010-08-09 12:08:26 +00001163 spin_unlock_irqrestore(&d40c->lock, flags);
1164 return res;
1165}
1166
Rabin Vincent86eb5fb2011-01-25 11:18:34 +01001167static int d40_resume(struct d40_chan *d40c)
Jonas Aabergaa182ae2010-08-09 12:08:26 +00001168{
Jonas Aabergaa182ae2010-08-09 12:08:26 +00001169 int res = 0;
1170 unsigned long flags;
1171
Jonas Aaberg3ac012a2010-08-09 12:09:12 +00001172 if (!d40c->busy)
1173 return 0;
1174
Jonas Aabergaa182ae2010-08-09 12:08:26 +00001175 spin_lock_irqsave(&d40c->lock, flags);
Narayanan G7fb3e752011-11-17 17:26:41 +05301176 pm_runtime_get_sync(d40c->base->dev);
Jonas Aabergaa182ae2010-08-09 12:08:26 +00001177 if (d40c->base->rev == 0)
Rabin Vincent724a8572011-01-25 11:18:08 +01001178 if (chan_is_logical(d40c)) {
Jonas Aabergaa182ae2010-08-09 12:08:26 +00001179 res = d40_channel_execute_command(d40c,
1180 D40_DMA_SUSPEND_REQ);
1181 goto no_suspend;
1182 }
1183
1184 /* If bytes left to transfer or linked tx resume job */
1185 if (d40_residue(d40c) || d40_tx_is_linked(d40c)) {
1186
Rabin Vincent724a8572011-01-25 11:18:08 +01001187 if (chan_is_logical(d40c))
Jonas Aabergaa182ae2010-08-09 12:08:26 +00001188 d40_config_set_event(d40c, true);
1189
1190 res = d40_channel_execute_command(d40c, D40_DMA_RUN);
1191 }
1192
1193no_suspend:
Narayanan G7fb3e752011-11-17 17:26:41 +05301194 pm_runtime_mark_last_busy(d40c->base->dev);
1195 pm_runtime_put_autosuspend(d40c->base->dev);
Jonas Aabergaa182ae2010-08-09 12:08:26 +00001196 spin_unlock_irqrestore(&d40c->lock, flags);
1197 return res;
1198}
1199
Rabin Vincent86eb5fb2011-01-25 11:18:34 +01001200static int d40_terminate_all(struct d40_chan *chan)
1201{
1202 unsigned long flags;
1203 int ret = 0;
1204
1205 ret = d40_pause(chan);
1206 if (!ret && chan_is_physical(chan))
1207 ret = d40_channel_execute_command(chan, D40_DMA_STOP);
1208
1209 spin_lock_irqsave(&chan->lock, flags);
1210 d40_term_all(chan);
1211 spin_unlock_irqrestore(&chan->lock, flags);
1212
1213 return ret;
1214}
1215
Linus Walleij8d318a52010-03-30 15:33:42 +02001216static dma_cookie_t d40_tx_submit(struct dma_async_tx_descriptor *tx)
1217{
1218 struct d40_chan *d40c = container_of(tx->chan,
1219 struct d40_chan,
1220 chan);
1221 struct d40_desc *d40d = container_of(tx, struct d40_desc, txd);
1222 unsigned long flags;
Russell King - ARM Linux884485e2012-03-06 22:34:46 +00001223 dma_cookie_t cookie;
Linus Walleij8d318a52010-03-30 15:33:42 +02001224
1225 spin_lock_irqsave(&d40c->lock, flags);
Russell King - ARM Linux884485e2012-03-06 22:34:46 +00001226 cookie = dma_cookie_assign(tx);
Linus Walleij8d318a52010-03-30 15:33:42 +02001227 d40_desc_queue(d40c, d40d);
Linus Walleij8d318a52010-03-30 15:33:42 +02001228 spin_unlock_irqrestore(&d40c->lock, flags);
1229
Russell King - ARM Linux884485e2012-03-06 22:34:46 +00001230 return cookie;
Linus Walleij8d318a52010-03-30 15:33:42 +02001231}
1232
1233static int d40_start(struct d40_chan *d40c)
1234{
Linus Walleijf4185592010-06-22 18:06:42 -07001235 if (d40c->base->rev == 0) {
1236 int err;
1237
Rabin Vincent724a8572011-01-25 11:18:08 +01001238 if (chan_is_logical(d40c)) {
Linus Walleijf4185592010-06-22 18:06:42 -07001239 err = d40_channel_execute_command(d40c,
1240 D40_DMA_SUSPEND_REQ);
1241 if (err)
1242 return err;
1243 }
1244 }
1245
Rabin Vincent724a8572011-01-25 11:18:08 +01001246 if (chan_is_logical(d40c))
Linus Walleij8d318a52010-03-30 15:33:42 +02001247 d40_config_set_event(d40c, true);
Linus Walleij8d318a52010-03-30 15:33:42 +02001248
Jonas Aaberg0c322692010-06-20 21:25:46 +00001249 return d40_channel_execute_command(d40c, D40_DMA_RUN);
Linus Walleij8d318a52010-03-30 15:33:42 +02001250}
1251
1252static struct d40_desc *d40_queue_start(struct d40_chan *d40c)
1253{
1254 struct d40_desc *d40d;
1255 int err;
1256
1257 /* Start queued jobs, if any */
1258 d40d = d40_first_queued(d40c);
1259
1260 if (d40d != NULL) {
Narayanan G7fb3e752011-11-17 17:26:41 +05301261 if (!d40c->busy)
1262 d40c->busy = true;
1263
1264 pm_runtime_get_sync(d40c->base->dev);
Linus Walleij8d318a52010-03-30 15:33:42 +02001265
1266 /* Remove from queue */
1267 d40_desc_remove(d40d);
1268
1269 /* Add to active queue */
1270 d40_desc_submit(d40c, d40d);
1271
Rabin Vincent7d83a852011-01-25 11:18:06 +01001272 /* Initiate DMA job */
1273 d40_desc_load(d40c, d40d);
Jonas Aaberg698e4732010-08-09 12:08:56 +00001274
Rabin Vincent7d83a852011-01-25 11:18:06 +01001275 /* Start dma job */
1276 err = d40_start(d40c);
Linus Walleij8d318a52010-03-30 15:33:42 +02001277
Rabin Vincent7d83a852011-01-25 11:18:06 +01001278 if (err)
1279 return NULL;
Linus Walleij8d318a52010-03-30 15:33:42 +02001280 }
1281
1282 return d40d;
1283}
1284
1285/* called from interrupt context */
1286static void dma_tc_handle(struct d40_chan *d40c)
1287{
1288 struct d40_desc *d40d;
1289
Linus Walleij8d318a52010-03-30 15:33:42 +02001290 /* Get first active entry from list */
1291 d40d = d40_first_active_get(d40c);
1292
1293 if (d40d == NULL)
1294 return;
1295
Rabin Vincent0c842b52011-01-25 11:18:35 +01001296 if (d40d->cyclic) {
1297 /*
1298 * If this was a paritially loaded list, we need to reloaded
1299 * it, and only when the list is completed. We need to check
1300 * for done because the interrupt will hit for every link, and
1301 * not just the last one.
1302 */
1303 if (d40d->lli_current < d40d->lli_len
1304 && !d40_tx_is_linked(d40c)
1305 && !d40_residue(d40c)) {
1306 d40_lcla_free_all(d40c, d40d);
1307 d40_desc_load(d40c, d40d);
1308 (void) d40_start(d40c);
Linus Walleij8d318a52010-03-30 15:33:42 +02001309
Rabin Vincent0c842b52011-01-25 11:18:35 +01001310 if (d40d->lli_current == d40d->lli_len)
1311 d40d->lli_current = 0;
1312 }
1313 } else {
1314 d40_lcla_free_all(d40c, d40d);
1315
1316 if (d40d->lli_current < d40d->lli_len) {
1317 d40_desc_load(d40c, d40d);
1318 /* Start dma job */
1319 (void) d40_start(d40c);
1320 return;
1321 }
1322
1323 if (d40_queue_start(d40c) == NULL)
1324 d40c->busy = false;
Narayanan G7fb3e752011-11-17 17:26:41 +05301325 pm_runtime_mark_last_busy(d40c->base->dev);
1326 pm_runtime_put_autosuspend(d40c->base->dev);
Linus Walleij8d318a52010-03-30 15:33:42 +02001327 }
1328
Linus Walleij8d318a52010-03-30 15:33:42 +02001329 d40c->pending_tx++;
1330 tasklet_schedule(&d40c->tasklet);
1331
1332}
1333
1334static void dma_tasklet(unsigned long data)
1335{
1336 struct d40_chan *d40c = (struct d40_chan *) data;
Jonas Aaberg767a9672010-08-09 12:08:34 +00001337 struct d40_desc *d40d;
Linus Walleij8d318a52010-03-30 15:33:42 +02001338 unsigned long flags;
1339 dma_async_tx_callback callback;
1340 void *callback_param;
1341
1342 spin_lock_irqsave(&d40c->lock, flags);
1343
1344 /* Get first active entry from list */
Jonas Aaberg767a9672010-08-09 12:08:34 +00001345 d40d = d40_first_active_get(d40c);
Jonas Aaberg767a9672010-08-09 12:08:34 +00001346 if (d40d == NULL)
Linus Walleij8d318a52010-03-30 15:33:42 +02001347 goto err;
1348
Rabin Vincent0c842b52011-01-25 11:18:35 +01001349 if (!d40d->cyclic)
Russell King - ARM Linuxf7fbce02012-03-06 22:35:07 +00001350 dma_cookie_complete(&d40d->txd);
Linus Walleij8d318a52010-03-30 15:33:42 +02001351
1352 /*
1353 * If terminating a channel pending_tx is set to zero.
1354 * This prevents any finished active jobs to return to the client.
1355 */
1356 if (d40c->pending_tx == 0) {
1357 spin_unlock_irqrestore(&d40c->lock, flags);
1358 return;
1359 }
1360
1361 /* Callback to client */
Jonas Aaberg767a9672010-08-09 12:08:34 +00001362 callback = d40d->txd.callback;
1363 callback_param = d40d->txd.callback_param;
Linus Walleij8d318a52010-03-30 15:33:42 +02001364
Rabin Vincent0c842b52011-01-25 11:18:35 +01001365 if (!d40d->cyclic) {
1366 if (async_tx_test_ack(&d40d->txd)) {
Jonas Aaberg767a9672010-08-09 12:08:34 +00001367 d40_desc_remove(d40d);
Rabin Vincent0c842b52011-01-25 11:18:35 +01001368 d40_desc_free(d40c, d40d);
1369 } else {
1370 if (!d40d->is_in_client_list) {
1371 d40_desc_remove(d40d);
1372 d40_lcla_free_all(d40c, d40d);
1373 list_add_tail(&d40d->node, &d40c->client);
1374 d40d->is_in_client_list = true;
1375 }
Linus Walleij8d318a52010-03-30 15:33:42 +02001376 }
1377 }
1378
1379 d40c->pending_tx--;
1380
1381 if (d40c->pending_tx)
1382 tasklet_schedule(&d40c->tasklet);
1383
1384 spin_unlock_irqrestore(&d40c->lock, flags);
1385
Jonas Aaberg767a9672010-08-09 12:08:34 +00001386 if (callback && (d40d->txd.flags & DMA_PREP_INTERRUPT))
Linus Walleij8d318a52010-03-30 15:33:42 +02001387 callback(callback_param);
1388
1389 return;
1390
1391 err:
Lucas De Marchi25985ed2011-03-30 22:57:33 -03001392 /* Rescue manoeuvre if receiving double interrupts */
Linus Walleij8d318a52010-03-30 15:33:42 +02001393 if (d40c->pending_tx > 0)
1394 d40c->pending_tx--;
1395 spin_unlock_irqrestore(&d40c->lock, flags);
1396}
1397
1398static irqreturn_t d40_handle_interrupt(int irq, void *data)
1399{
1400 static const struct d40_interrupt_lookup il[] = {
1401 {D40_DREG_LCTIS0, D40_DREG_LCICR0, false, 0},
1402 {D40_DREG_LCTIS1, D40_DREG_LCICR1, false, 32},
1403 {D40_DREG_LCTIS2, D40_DREG_LCICR2, false, 64},
1404 {D40_DREG_LCTIS3, D40_DREG_LCICR3, false, 96},
1405 {D40_DREG_LCEIS0, D40_DREG_LCICR0, true, 0},
1406 {D40_DREG_LCEIS1, D40_DREG_LCICR1, true, 32},
1407 {D40_DREG_LCEIS2, D40_DREG_LCICR2, true, 64},
1408 {D40_DREG_LCEIS3, D40_DREG_LCICR3, true, 96},
1409 {D40_DREG_PCTIS, D40_DREG_PCICR, false, D40_PHY_CHAN},
1410 {D40_DREG_PCEIS, D40_DREG_PCICR, true, D40_PHY_CHAN},
1411 };
1412
1413 int i;
1414 u32 regs[ARRAY_SIZE(il)];
Linus Walleij8d318a52010-03-30 15:33:42 +02001415 u32 idx;
1416 u32 row;
1417 long chan = -1;
1418 struct d40_chan *d40c;
1419 unsigned long flags;
1420 struct d40_base *base = data;
1421
1422 spin_lock_irqsave(&base->interrupt_lock, flags);
1423
1424 /* Read interrupt status of both logical and physical channels */
1425 for (i = 0; i < ARRAY_SIZE(il); i++)
1426 regs[i] = readl(base->virtbase + il[i].src);
1427
1428 for (;;) {
1429
1430 chan = find_next_bit((unsigned long *)regs,
1431 BITS_PER_LONG * ARRAY_SIZE(il), chan + 1);
1432
1433 /* No more set bits found? */
1434 if (chan == BITS_PER_LONG * ARRAY_SIZE(il))
1435 break;
1436
1437 row = chan / BITS_PER_LONG;
1438 idx = chan & (BITS_PER_LONG - 1);
1439
1440 /* ACK interrupt */
Jonas Aaberg1b003482010-08-09 12:07:54 +00001441 writel(1 << idx, base->virtbase + il[row].clr);
Linus Walleij8d318a52010-03-30 15:33:42 +02001442
1443 if (il[row].offset == D40_PHY_CHAN)
1444 d40c = base->lookup_phy_chans[idx];
1445 else
1446 d40c = base->lookup_log_chans[il[row].offset + idx];
1447 spin_lock(&d40c->lock);
1448
1449 if (!il[row].is_error)
1450 dma_tc_handle(d40c);
1451 else
Rabin Vincent6db5a8b2011-01-25 11:18:09 +01001452 d40_err(base->dev, "IRQ chan: %ld offset %d idx %d\n",
1453 chan, il[row].offset, idx);
Linus Walleij8d318a52010-03-30 15:33:42 +02001454
1455 spin_unlock(&d40c->lock);
1456 }
1457
1458 spin_unlock_irqrestore(&base->interrupt_lock, flags);
1459
1460 return IRQ_HANDLED;
1461}
1462
Linus Walleij8d318a52010-03-30 15:33:42 +02001463static int d40_validate_conf(struct d40_chan *d40c,
1464 struct stedma40_chan_cfg *conf)
1465{
1466 int res = 0;
1467 u32 dst_event_group = D40_TYPE_TO_GROUP(conf->dst_dev_type);
1468 u32 src_event_group = D40_TYPE_TO_GROUP(conf->src_dev_type);
Rabin Vincent38bdbf02010-10-12 13:00:51 +00001469 bool is_log = conf->mode == STEDMA40_MODE_LOGICAL;
Linus Walleij8d318a52010-03-30 15:33:42 +02001470
Linus Walleij0747c7ba2010-08-09 12:07:36 +00001471 if (!conf->dir) {
Rabin Vincent6db5a8b2011-01-25 11:18:09 +01001472 chan_err(d40c, "Invalid direction.\n");
Linus Walleij0747c7ba2010-08-09 12:07:36 +00001473 res = -EINVAL;
1474 }
1475
1476 if (conf->dst_dev_type != STEDMA40_DEV_DST_MEMORY &&
1477 d40c->base->plat_data->dev_tx[conf->dst_dev_type] == 0 &&
1478 d40c->runtime_addr == 0) {
1479
Rabin Vincent6db5a8b2011-01-25 11:18:09 +01001480 chan_err(d40c, "Invalid TX channel address (%d)\n",
1481 conf->dst_dev_type);
Linus Walleij0747c7ba2010-08-09 12:07:36 +00001482 res = -EINVAL;
1483 }
1484
1485 if (conf->src_dev_type != STEDMA40_DEV_SRC_MEMORY &&
1486 d40c->base->plat_data->dev_rx[conf->src_dev_type] == 0 &&
1487 d40c->runtime_addr == 0) {
Rabin Vincent6db5a8b2011-01-25 11:18:09 +01001488 chan_err(d40c, "Invalid RX channel address (%d)\n",
1489 conf->src_dev_type);
Linus Walleij0747c7ba2010-08-09 12:07:36 +00001490 res = -EINVAL;
1491 }
1492
1493 if (conf->dir == STEDMA40_MEM_TO_PERIPH &&
Linus Walleij8d318a52010-03-30 15:33:42 +02001494 dst_event_group == STEDMA40_DEV_DST_MEMORY) {
Rabin Vincent6db5a8b2011-01-25 11:18:09 +01001495 chan_err(d40c, "Invalid dst\n");
Linus Walleij8d318a52010-03-30 15:33:42 +02001496 res = -EINVAL;
1497 }
1498
Linus Walleij0747c7ba2010-08-09 12:07:36 +00001499 if (conf->dir == STEDMA40_PERIPH_TO_MEM &&
Linus Walleij8d318a52010-03-30 15:33:42 +02001500 src_event_group == STEDMA40_DEV_SRC_MEMORY) {
Rabin Vincent6db5a8b2011-01-25 11:18:09 +01001501 chan_err(d40c, "Invalid src\n");
Linus Walleij8d318a52010-03-30 15:33:42 +02001502 res = -EINVAL;
1503 }
1504
1505 if (src_event_group == STEDMA40_DEV_SRC_MEMORY &&
1506 dst_event_group == STEDMA40_DEV_DST_MEMORY && is_log) {
Rabin Vincent6db5a8b2011-01-25 11:18:09 +01001507 chan_err(d40c, "No event line\n");
Linus Walleij8d318a52010-03-30 15:33:42 +02001508 res = -EINVAL;
1509 }
1510
1511 if (conf->dir == STEDMA40_PERIPH_TO_PERIPH &&
1512 (src_event_group != dst_event_group)) {
Rabin Vincent6db5a8b2011-01-25 11:18:09 +01001513 chan_err(d40c, "Invalid event group\n");
Linus Walleij8d318a52010-03-30 15:33:42 +02001514 res = -EINVAL;
1515 }
1516
1517 if (conf->dir == STEDMA40_PERIPH_TO_PERIPH) {
1518 /*
1519 * DMAC HW supports it. Will be added to this driver,
1520 * in case any dma client requires it.
1521 */
Rabin Vincent6db5a8b2011-01-25 11:18:09 +01001522 chan_err(d40c, "periph to periph not supported\n");
Linus Walleij8d318a52010-03-30 15:33:42 +02001523 res = -EINVAL;
1524 }
1525
Per Forlind49278e2010-12-20 18:31:38 +01001526 if (d40_psize_2_burst_size(is_log, conf->src_info.psize) *
1527 (1 << conf->src_info.data_width) !=
1528 d40_psize_2_burst_size(is_log, conf->dst_info.psize) *
1529 (1 << conf->dst_info.data_width)) {
1530 /*
1531 * The DMAC hardware only supports
1532 * src (burst x width) == dst (burst x width)
1533 */
1534
Rabin Vincent6db5a8b2011-01-25 11:18:09 +01001535 chan_err(d40c, "src (burst x width) != dst (burst x width)\n");
Per Forlind49278e2010-12-20 18:31:38 +01001536 res = -EINVAL;
1537 }
1538
Linus Walleij8d318a52010-03-30 15:33:42 +02001539 return res;
1540}
1541
Narayanan G5cd326f2011-11-30 19:20:42 +05301542static bool d40_alloc_mask_set(struct d40_phy_res *phy,
1543 bool is_src, int log_event_line, bool is_log,
1544 bool *first_user)
Linus Walleij8d318a52010-03-30 15:33:42 +02001545{
1546 unsigned long flags;
1547 spin_lock_irqsave(&phy->lock, flags);
Narayanan G5cd326f2011-11-30 19:20:42 +05301548
1549 *first_user = ((phy->allocated_src | phy->allocated_dst)
1550 == D40_ALLOC_FREE);
1551
Marcin Mielczarczyk4aed79b2010-05-18 00:41:21 +02001552 if (!is_log) {
Linus Walleij8d318a52010-03-30 15:33:42 +02001553 /* Physical interrupts are masked per physical full channel */
1554 if (phy->allocated_src == D40_ALLOC_FREE &&
1555 phy->allocated_dst == D40_ALLOC_FREE) {
1556 phy->allocated_dst = D40_ALLOC_PHY;
1557 phy->allocated_src = D40_ALLOC_PHY;
1558 goto found;
1559 } else
1560 goto not_found;
1561 }
1562
1563 /* Logical channel */
1564 if (is_src) {
1565 if (phy->allocated_src == D40_ALLOC_PHY)
1566 goto not_found;
1567
1568 if (phy->allocated_src == D40_ALLOC_FREE)
1569 phy->allocated_src = D40_ALLOC_LOG_FREE;
1570
1571 if (!(phy->allocated_src & (1 << log_event_line))) {
1572 phy->allocated_src |= 1 << log_event_line;
1573 goto found;
1574 } else
1575 goto not_found;
1576 } else {
1577 if (phy->allocated_dst == D40_ALLOC_PHY)
1578 goto not_found;
1579
1580 if (phy->allocated_dst == D40_ALLOC_FREE)
1581 phy->allocated_dst = D40_ALLOC_LOG_FREE;
1582
1583 if (!(phy->allocated_dst & (1 << log_event_line))) {
1584 phy->allocated_dst |= 1 << log_event_line;
1585 goto found;
1586 } else
1587 goto not_found;
1588 }
1589
1590not_found:
1591 spin_unlock_irqrestore(&phy->lock, flags);
1592 return false;
1593found:
1594 spin_unlock_irqrestore(&phy->lock, flags);
1595 return true;
1596}
1597
1598static bool d40_alloc_mask_free(struct d40_phy_res *phy, bool is_src,
1599 int log_event_line)
1600{
1601 unsigned long flags;
1602 bool is_free = false;
1603
1604 spin_lock_irqsave(&phy->lock, flags);
1605 if (!log_event_line) {
Linus Walleij8d318a52010-03-30 15:33:42 +02001606 phy->allocated_dst = D40_ALLOC_FREE;
1607 phy->allocated_src = D40_ALLOC_FREE;
1608 is_free = true;
1609 goto out;
1610 }
1611
1612 /* Logical channel */
1613 if (is_src) {
1614 phy->allocated_src &= ~(1 << log_event_line);
1615 if (phy->allocated_src == D40_ALLOC_LOG_FREE)
1616 phy->allocated_src = D40_ALLOC_FREE;
1617 } else {
1618 phy->allocated_dst &= ~(1 << log_event_line);
1619 if (phy->allocated_dst == D40_ALLOC_LOG_FREE)
1620 phy->allocated_dst = D40_ALLOC_FREE;
1621 }
1622
1623 is_free = ((phy->allocated_src | phy->allocated_dst) ==
1624 D40_ALLOC_FREE);
1625
1626out:
1627 spin_unlock_irqrestore(&phy->lock, flags);
1628
1629 return is_free;
1630}
1631
Narayanan G5cd326f2011-11-30 19:20:42 +05301632static int d40_allocate_channel(struct d40_chan *d40c, bool *first_phy_user)
Linus Walleij8d318a52010-03-30 15:33:42 +02001633{
1634 int dev_type;
1635 int event_group;
1636 int event_line;
1637 struct d40_phy_res *phys;
1638 int i;
1639 int j;
1640 int log_num;
1641 bool is_src;
Rabin Vincent38bdbf02010-10-12 13:00:51 +00001642 bool is_log = d40c->dma_cfg.mode == STEDMA40_MODE_LOGICAL;
Linus Walleij8d318a52010-03-30 15:33:42 +02001643
1644 phys = d40c->base->phy_res;
1645
1646 if (d40c->dma_cfg.dir == STEDMA40_PERIPH_TO_MEM) {
1647 dev_type = d40c->dma_cfg.src_dev_type;
1648 log_num = 2 * dev_type;
1649 is_src = true;
1650 } else if (d40c->dma_cfg.dir == STEDMA40_MEM_TO_PERIPH ||
1651 d40c->dma_cfg.dir == STEDMA40_MEM_TO_MEM) {
1652 /* dst event lines are used for logical memcpy */
1653 dev_type = d40c->dma_cfg.dst_dev_type;
1654 log_num = 2 * dev_type + 1;
1655 is_src = false;
1656 } else
1657 return -EINVAL;
1658
1659 event_group = D40_TYPE_TO_GROUP(dev_type);
1660 event_line = D40_TYPE_TO_EVENT(dev_type);
1661
1662 if (!is_log) {
1663 if (d40c->dma_cfg.dir == STEDMA40_MEM_TO_MEM) {
1664 /* Find physical half channel */
1665 for (i = 0; i < d40c->base->num_phy_chans; i++) {
1666
Marcin Mielczarczyk4aed79b2010-05-18 00:41:21 +02001667 if (d40_alloc_mask_set(&phys[i], is_src,
Narayanan G5cd326f2011-11-30 19:20:42 +05301668 0, is_log,
1669 first_phy_user))
Linus Walleij8d318a52010-03-30 15:33:42 +02001670 goto found_phy;
1671 }
1672 } else
1673 for (j = 0; j < d40c->base->num_phy_chans; j += 8) {
1674 int phy_num = j + event_group * 2;
1675 for (i = phy_num; i < phy_num + 2; i++) {
Linus Walleij508849a2010-06-20 21:26:07 +00001676 if (d40_alloc_mask_set(&phys[i],
1677 is_src,
1678 0,
Narayanan G5cd326f2011-11-30 19:20:42 +05301679 is_log,
1680 first_phy_user))
Linus Walleij8d318a52010-03-30 15:33:42 +02001681 goto found_phy;
1682 }
1683 }
1684 return -EINVAL;
1685found_phy:
1686 d40c->phy_chan = &phys[i];
1687 d40c->log_num = D40_PHY_CHAN;
1688 goto out;
1689 }
1690 if (dev_type == -1)
1691 return -EINVAL;
1692
1693 /* Find logical channel */
1694 for (j = 0; j < d40c->base->num_phy_chans; j += 8) {
1695 int phy_num = j + event_group * 2;
Narayanan G5cd326f2011-11-30 19:20:42 +05301696
1697 if (d40c->dma_cfg.use_fixed_channel) {
1698 i = d40c->dma_cfg.phy_channel;
1699
1700 if ((i != phy_num) && (i != phy_num + 1)) {
1701 dev_err(chan2dev(d40c),
1702 "invalid fixed phy channel %d\n", i);
1703 return -EINVAL;
1704 }
1705
1706 if (d40_alloc_mask_set(&phys[i], is_src, event_line,
1707 is_log, first_phy_user))
1708 goto found_log;
1709
1710 dev_err(chan2dev(d40c),
1711 "could not allocate fixed phy channel %d\n", i);
1712 return -EINVAL;
1713 }
1714
Linus Walleij8d318a52010-03-30 15:33:42 +02001715 /*
1716 * Spread logical channels across all available physical rather
1717 * than pack every logical channel at the first available phy
1718 * channels.
1719 */
1720 if (is_src) {
1721 for (i = phy_num; i < phy_num + 2; i++) {
1722 if (d40_alloc_mask_set(&phys[i], is_src,
Narayanan G5cd326f2011-11-30 19:20:42 +05301723 event_line, is_log,
1724 first_phy_user))
Linus Walleij8d318a52010-03-30 15:33:42 +02001725 goto found_log;
1726 }
1727 } else {
1728 for (i = phy_num + 1; i >= phy_num; i--) {
1729 if (d40_alloc_mask_set(&phys[i], is_src,
Narayanan G5cd326f2011-11-30 19:20:42 +05301730 event_line, is_log,
1731 first_phy_user))
Linus Walleij8d318a52010-03-30 15:33:42 +02001732 goto found_log;
1733 }
1734 }
1735 }
1736 return -EINVAL;
1737
1738found_log:
1739 d40c->phy_chan = &phys[i];
1740 d40c->log_num = log_num;
1741out:
1742
1743 if (is_log)
1744 d40c->base->lookup_log_chans[d40c->log_num] = d40c;
1745 else
1746 d40c->base->lookup_phy_chans[d40c->phy_chan->num] = d40c;
1747
1748 return 0;
1749
1750}
1751
Linus Walleij8d318a52010-03-30 15:33:42 +02001752static int d40_config_memcpy(struct d40_chan *d40c)
1753{
1754 dma_cap_mask_t cap = d40c->chan.device->cap_mask;
1755
1756 if (dma_has_cap(DMA_MEMCPY, cap) && !dma_has_cap(DMA_SLAVE, cap)) {
1757 d40c->dma_cfg = *d40c->base->plat_data->memcpy_conf_log;
1758 d40c->dma_cfg.src_dev_type = STEDMA40_DEV_SRC_MEMORY;
1759 d40c->dma_cfg.dst_dev_type = d40c->base->plat_data->
1760 memcpy[d40c->chan.chan_id];
1761
1762 } else if (dma_has_cap(DMA_MEMCPY, cap) &&
1763 dma_has_cap(DMA_SLAVE, cap)) {
1764 d40c->dma_cfg = *d40c->base->plat_data->memcpy_conf_phy;
1765 } else {
Rabin Vincent6db5a8b2011-01-25 11:18:09 +01001766 chan_err(d40c, "No memcpy\n");
Linus Walleij8d318a52010-03-30 15:33:42 +02001767 return -EINVAL;
1768 }
1769
1770 return 0;
1771}
1772
1773
1774static int d40_free_dma(struct d40_chan *d40c)
1775{
1776
1777 int res = 0;
Jonas Aabergd181b3a2010-06-20 21:26:38 +00001778 u32 event;
Linus Walleij8d318a52010-03-30 15:33:42 +02001779 struct d40_phy_res *phy = d40c->phy_chan;
1780 bool is_src;
1781
1782 /* Terminate all queued and active transfers */
1783 d40_term_all(d40c);
1784
1785 if (phy == NULL) {
Rabin Vincent6db5a8b2011-01-25 11:18:09 +01001786 chan_err(d40c, "phy == null\n");
Linus Walleij8d318a52010-03-30 15:33:42 +02001787 return -EINVAL;
1788 }
1789
1790 if (phy->allocated_src == D40_ALLOC_FREE &&
1791 phy->allocated_dst == D40_ALLOC_FREE) {
Rabin Vincent6db5a8b2011-01-25 11:18:09 +01001792 chan_err(d40c, "channel already free\n");
Linus Walleij8d318a52010-03-30 15:33:42 +02001793 return -EINVAL;
1794 }
1795
Linus Walleij8d318a52010-03-30 15:33:42 +02001796 if (d40c->dma_cfg.dir == STEDMA40_MEM_TO_PERIPH ||
1797 d40c->dma_cfg.dir == STEDMA40_MEM_TO_MEM) {
1798 event = D40_TYPE_TO_EVENT(d40c->dma_cfg.dst_dev_type);
Linus Walleij8d318a52010-03-30 15:33:42 +02001799 is_src = false;
1800 } else if (d40c->dma_cfg.dir == STEDMA40_PERIPH_TO_MEM) {
1801 event = D40_TYPE_TO_EVENT(d40c->dma_cfg.src_dev_type);
Linus Walleij8d318a52010-03-30 15:33:42 +02001802 is_src = true;
1803 } else {
Rabin Vincent6db5a8b2011-01-25 11:18:09 +01001804 chan_err(d40c, "Unknown direction\n");
Linus Walleij8d318a52010-03-30 15:33:42 +02001805 return -EINVAL;
1806 }
1807
Narayanan G7fb3e752011-11-17 17:26:41 +05301808 pm_runtime_get_sync(d40c->base->dev);
Jonas Aabergd181b3a2010-06-20 21:26:38 +00001809 res = d40_channel_execute_command(d40c, D40_DMA_SUSPEND_REQ);
1810 if (res) {
Rabin Vincent6db5a8b2011-01-25 11:18:09 +01001811 chan_err(d40c, "suspend failed\n");
Narayanan G7fb3e752011-11-17 17:26:41 +05301812 goto out;
Jonas Aabergd181b3a2010-06-20 21:26:38 +00001813 }
Linus Walleij8d318a52010-03-30 15:33:42 +02001814
Rabin Vincent724a8572011-01-25 11:18:08 +01001815 if (chan_is_logical(d40c)) {
Jonas Aabergd181b3a2010-06-20 21:26:38 +00001816 /* Release logical channel, deactivate the event line */
1817
1818 d40_config_set_event(d40c, false);
Linus Walleij8d318a52010-03-30 15:33:42 +02001819 d40c->base->lookup_log_chans[d40c->log_num] = NULL;
1820
1821 /*
1822 * Check if there are more logical allocation
1823 * on this phy channel.
1824 */
1825 if (!d40_alloc_mask_free(phy, is_src, event)) {
1826 /* Resume the other logical channels if any */
1827 if (d40_chan_has_events(d40c)) {
1828 res = d40_channel_execute_command(d40c,
1829 D40_DMA_RUN);
Narayanan G7fb3e752011-11-17 17:26:41 +05301830 if (res)
Rabin Vincent6db5a8b2011-01-25 11:18:09 +01001831 chan_err(d40c,
1832 "Executing RUN command\n");
Linus Walleij8d318a52010-03-30 15:33:42 +02001833 }
Narayanan G7fb3e752011-11-17 17:26:41 +05301834 goto out;
Linus Walleij8d318a52010-03-30 15:33:42 +02001835 }
Jonas Aabergd181b3a2010-06-20 21:26:38 +00001836 } else {
1837 (void) d40_alloc_mask_free(phy, is_src, 0);
1838 }
Linus Walleij8d318a52010-03-30 15:33:42 +02001839
1840 /* Release physical channel */
1841 res = d40_channel_execute_command(d40c, D40_DMA_STOP);
1842 if (res) {
Rabin Vincent6db5a8b2011-01-25 11:18:09 +01001843 chan_err(d40c, "Failed to stop channel\n");
Narayanan G7fb3e752011-11-17 17:26:41 +05301844 goto out;
Linus Walleij8d318a52010-03-30 15:33:42 +02001845 }
Narayanan G7fb3e752011-11-17 17:26:41 +05301846
1847 if (d40c->busy) {
1848 pm_runtime_mark_last_busy(d40c->base->dev);
1849 pm_runtime_put_autosuspend(d40c->base->dev);
1850 }
1851
1852 d40c->busy = false;
Linus Walleij8d318a52010-03-30 15:33:42 +02001853 d40c->phy_chan = NULL;
Rabin Vincentce2ca122010-10-12 13:00:49 +00001854 d40c->configured = false;
Linus Walleij8d318a52010-03-30 15:33:42 +02001855 d40c->base->lookup_phy_chans[phy->num] = NULL;
Narayanan G7fb3e752011-11-17 17:26:41 +05301856out:
Linus Walleij8d318a52010-03-30 15:33:42 +02001857
Narayanan G7fb3e752011-11-17 17:26:41 +05301858 pm_runtime_mark_last_busy(d40c->base->dev);
1859 pm_runtime_put_autosuspend(d40c->base->dev);
1860 return res;
Linus Walleij8d318a52010-03-30 15:33:42 +02001861}
1862
Jonas Aaberga5ebca42010-05-18 00:41:09 +02001863static bool d40_is_paused(struct d40_chan *d40c)
1864{
Rabin Vincent8ca84682011-01-25 11:18:07 +01001865 void __iomem *chanbase = chan_base(d40c);
Jonas Aaberga5ebca42010-05-18 00:41:09 +02001866 bool is_paused = false;
1867 unsigned long flags;
1868 void __iomem *active_reg;
1869 u32 status;
1870 u32 event;
Jonas Aaberga5ebca42010-05-18 00:41:09 +02001871
1872 spin_lock_irqsave(&d40c->lock, flags);
1873
Rabin Vincent724a8572011-01-25 11:18:08 +01001874 if (chan_is_physical(d40c)) {
Jonas Aaberga5ebca42010-05-18 00:41:09 +02001875 if (d40c->phy_chan->num % 2 == 0)
1876 active_reg = d40c->base->virtbase + D40_DREG_ACTIVE;
1877 else
1878 active_reg = d40c->base->virtbase + D40_DREG_ACTIVO;
1879
1880 status = (readl(active_reg) &
1881 D40_CHAN_POS_MASK(d40c->phy_chan->num)) >>
1882 D40_CHAN_POS(d40c->phy_chan->num);
1883 if (status == D40_DMA_SUSPENDED || status == D40_DMA_STOP)
1884 is_paused = true;
1885
1886 goto _exit;
1887 }
1888
Jonas Aaberga5ebca42010-05-18 00:41:09 +02001889 if (d40c->dma_cfg.dir == STEDMA40_MEM_TO_PERIPH ||
Jonas Aaberg9dbfbd35c2010-08-09 12:08:41 +00001890 d40c->dma_cfg.dir == STEDMA40_MEM_TO_MEM) {
Jonas Aaberga5ebca42010-05-18 00:41:09 +02001891 event = D40_TYPE_TO_EVENT(d40c->dma_cfg.dst_dev_type);
Rabin Vincent8ca84682011-01-25 11:18:07 +01001892 status = readl(chanbase + D40_CHAN_REG_SDLNK);
Jonas Aaberg9dbfbd35c2010-08-09 12:08:41 +00001893 } else if (d40c->dma_cfg.dir == STEDMA40_PERIPH_TO_MEM) {
Jonas Aaberga5ebca42010-05-18 00:41:09 +02001894 event = D40_TYPE_TO_EVENT(d40c->dma_cfg.src_dev_type);
Rabin Vincent8ca84682011-01-25 11:18:07 +01001895 status = readl(chanbase + D40_CHAN_REG_SSLNK);
Jonas Aaberg9dbfbd35c2010-08-09 12:08:41 +00001896 } else {
Rabin Vincent6db5a8b2011-01-25 11:18:09 +01001897 chan_err(d40c, "Unknown direction\n");
Jonas Aaberga5ebca42010-05-18 00:41:09 +02001898 goto _exit;
1899 }
Jonas Aaberg9dbfbd35c2010-08-09 12:08:41 +00001900
Jonas Aaberga5ebca42010-05-18 00:41:09 +02001901 status = (status & D40_EVENTLINE_MASK(event)) >>
1902 D40_EVENTLINE_POS(event);
1903
1904 if (status != D40_DMA_RUN)
1905 is_paused = true;
Jonas Aaberga5ebca42010-05-18 00:41:09 +02001906_exit:
1907 spin_unlock_irqrestore(&d40c->lock, flags);
1908 return is_paused;
1909
1910}
1911
1912
Linus Walleij8d318a52010-03-30 15:33:42 +02001913static u32 stedma40_residue(struct dma_chan *chan)
1914{
1915 struct d40_chan *d40c =
1916 container_of(chan, struct d40_chan, chan);
1917 u32 bytes_left;
1918 unsigned long flags;
1919
1920 spin_lock_irqsave(&d40c->lock, flags);
1921 bytes_left = d40_residue(d40c);
1922 spin_unlock_irqrestore(&d40c->lock, flags);
1923
1924 return bytes_left;
1925}
1926
Rabin Vincent3e3a0762011-01-25 11:18:21 +01001927static int
1928d40_prep_sg_log(struct d40_chan *chan, struct d40_desc *desc,
1929 struct scatterlist *sg_src, struct scatterlist *sg_dst,
Rabin Vincent822c5672011-01-25 11:18:28 +01001930 unsigned int sg_len, dma_addr_t src_dev_addr,
1931 dma_addr_t dst_dev_addr)
Rabin Vincent3e3a0762011-01-25 11:18:21 +01001932{
1933 struct stedma40_chan_cfg *cfg = &chan->dma_cfg;
1934 struct stedma40_half_channel_info *src_info = &cfg->src_info;
1935 struct stedma40_half_channel_info *dst_info = &cfg->dst_info;
Rabin Vincent5ed04b82011-01-25 11:18:26 +01001936 int ret;
Rabin Vincent3e3a0762011-01-25 11:18:21 +01001937
Rabin Vincent5ed04b82011-01-25 11:18:26 +01001938 ret = d40_log_sg_to_lli(sg_src, sg_len,
1939 src_dev_addr,
1940 desc->lli_log.src,
1941 chan->log_def.lcsp1,
1942 src_info->data_width,
1943 dst_info->data_width);
Rabin Vincent3e3a0762011-01-25 11:18:21 +01001944
Rabin Vincent5ed04b82011-01-25 11:18:26 +01001945 ret = d40_log_sg_to_lli(sg_dst, sg_len,
1946 dst_dev_addr,
1947 desc->lli_log.dst,
1948 chan->log_def.lcsp3,
1949 dst_info->data_width,
1950 src_info->data_width);
Rabin Vincent3e3a0762011-01-25 11:18:21 +01001951
Rabin Vincent5ed04b82011-01-25 11:18:26 +01001952 return ret < 0 ? ret : 0;
Rabin Vincent3e3a0762011-01-25 11:18:21 +01001953}
1954
1955static int
1956d40_prep_sg_phy(struct d40_chan *chan, struct d40_desc *desc,
1957 struct scatterlist *sg_src, struct scatterlist *sg_dst,
Rabin Vincent822c5672011-01-25 11:18:28 +01001958 unsigned int sg_len, dma_addr_t src_dev_addr,
1959 dma_addr_t dst_dev_addr)
Rabin Vincent3e3a0762011-01-25 11:18:21 +01001960{
Rabin Vincent3e3a0762011-01-25 11:18:21 +01001961 struct stedma40_chan_cfg *cfg = &chan->dma_cfg;
1962 struct stedma40_half_channel_info *src_info = &cfg->src_info;
1963 struct stedma40_half_channel_info *dst_info = &cfg->dst_info;
Rabin Vincent0c842b52011-01-25 11:18:35 +01001964 unsigned long flags = 0;
Rabin Vincent3e3a0762011-01-25 11:18:21 +01001965 int ret;
1966
Rabin Vincent0c842b52011-01-25 11:18:35 +01001967 if (desc->cyclic)
1968 flags |= LLI_CYCLIC | LLI_TERM_INT;
1969
Rabin Vincent3e3a0762011-01-25 11:18:21 +01001970 ret = d40_phy_sg_to_lli(sg_src, sg_len, src_dev_addr,
1971 desc->lli_phy.src,
1972 virt_to_phys(desc->lli_phy.src),
1973 chan->src_def_cfg,
Rabin Vincent0c842b52011-01-25 11:18:35 +01001974 src_info, dst_info, flags);
Rabin Vincent3e3a0762011-01-25 11:18:21 +01001975
1976 ret = d40_phy_sg_to_lli(sg_dst, sg_len, dst_dev_addr,
1977 desc->lli_phy.dst,
1978 virt_to_phys(desc->lli_phy.dst),
1979 chan->dst_def_cfg,
Rabin Vincent0c842b52011-01-25 11:18:35 +01001980 dst_info, src_info, flags);
Rabin Vincent3e3a0762011-01-25 11:18:21 +01001981
1982 dma_sync_single_for_device(chan->base->dev, desc->lli_pool.dma_addr,
1983 desc->lli_pool.size, DMA_TO_DEVICE);
1984
1985 return ret < 0 ? ret : 0;
1986}
1987
1988
Rabin Vincent5f811582011-01-25 11:18:18 +01001989static struct d40_desc *
1990d40_prep_desc(struct d40_chan *chan, struct scatterlist *sg,
1991 unsigned int sg_len, unsigned long dma_flags)
1992{
1993 struct stedma40_chan_cfg *cfg = &chan->dma_cfg;
1994 struct d40_desc *desc;
Rabin Vincentdbd88782011-01-25 11:18:19 +01001995 int ret;
Rabin Vincent5f811582011-01-25 11:18:18 +01001996
1997 desc = d40_desc_get(chan);
1998 if (!desc)
1999 return NULL;
2000
2001 desc->lli_len = d40_sg_2_dmalen(sg, sg_len, cfg->src_info.data_width,
2002 cfg->dst_info.data_width);
2003 if (desc->lli_len < 0) {
2004 chan_err(chan, "Unaligned size\n");
Rabin Vincentdbd88782011-01-25 11:18:19 +01002005 goto err;
Rabin Vincent5f811582011-01-25 11:18:18 +01002006 }
2007
Rabin Vincentdbd88782011-01-25 11:18:19 +01002008 ret = d40_pool_lli_alloc(chan, desc, desc->lli_len);
2009 if (ret < 0) {
2010 chan_err(chan, "Could not allocate lli\n");
2011 goto err;
2012 }
2013
2014
Rabin Vincent5f811582011-01-25 11:18:18 +01002015 desc->lli_current = 0;
2016 desc->txd.flags = dma_flags;
2017 desc->txd.tx_submit = d40_tx_submit;
2018
2019 dma_async_tx_descriptor_init(&desc->txd, &chan->chan);
2020
2021 return desc;
Rabin Vincentdbd88782011-01-25 11:18:19 +01002022
2023err:
2024 d40_desc_free(chan, desc);
2025 return NULL;
Rabin Vincent5f811582011-01-25 11:18:18 +01002026}
2027
Rabin Vincentcade1d32011-01-25 11:18:23 +01002028static dma_addr_t
Vinod Kouldb8196d2011-10-13 22:34:23 +05302029d40_get_dev_addr(struct d40_chan *chan, enum dma_transfer_direction direction)
Linus Walleij8d318a52010-03-30 15:33:42 +02002030{
Rabin Vincentcade1d32011-01-25 11:18:23 +01002031 struct stedma40_platform_data *plat = chan->base->plat_data;
2032 struct stedma40_chan_cfg *cfg = &chan->dma_cfg;
Philippe Langlais711b9ce2011-05-07 17:09:43 +02002033 dma_addr_t addr = 0;
Linus Walleij8d318a52010-03-30 15:33:42 +02002034
Rabin Vincentcade1d32011-01-25 11:18:23 +01002035 if (chan->runtime_addr)
2036 return chan->runtime_addr;
2037
Vinod Kouldb8196d2011-10-13 22:34:23 +05302038 if (direction == DMA_DEV_TO_MEM)
Rabin Vincentcade1d32011-01-25 11:18:23 +01002039 addr = plat->dev_rx[cfg->src_dev_type];
Vinod Kouldb8196d2011-10-13 22:34:23 +05302040 else if (direction == DMA_MEM_TO_DEV)
Rabin Vincentcade1d32011-01-25 11:18:23 +01002041 addr = plat->dev_tx[cfg->dst_dev_type];
2042
2043 return addr;
2044}
2045
2046static struct dma_async_tx_descriptor *
2047d40_prep_sg(struct dma_chan *dchan, struct scatterlist *sg_src,
2048 struct scatterlist *sg_dst, unsigned int sg_len,
Vinod Kouldb8196d2011-10-13 22:34:23 +05302049 enum dma_transfer_direction direction, unsigned long dma_flags)
Rabin Vincentcade1d32011-01-25 11:18:23 +01002050{
2051 struct d40_chan *chan = container_of(dchan, struct d40_chan, chan);
Rabin Vincent822c5672011-01-25 11:18:28 +01002052 dma_addr_t src_dev_addr = 0;
2053 dma_addr_t dst_dev_addr = 0;
Rabin Vincentcade1d32011-01-25 11:18:23 +01002054 struct d40_desc *desc;
2055 unsigned long flags;
2056 int ret;
2057
2058 if (!chan->phy_chan) {
2059 chan_err(chan, "Cannot prepare unallocated channel\n");
2060 return NULL;
Jonas Aaberg0d0f6b82010-06-20 21:25:31 +00002061 }
2062
Rabin Vincent0c842b52011-01-25 11:18:35 +01002063
Rabin Vincentcade1d32011-01-25 11:18:23 +01002064 spin_lock_irqsave(&chan->lock, flags);
Linus Walleij8d318a52010-03-30 15:33:42 +02002065
Rabin Vincentcade1d32011-01-25 11:18:23 +01002066 desc = d40_prep_desc(chan, sg_src, sg_len, dma_flags);
2067 if (desc == NULL)
Linus Walleij8d318a52010-03-30 15:33:42 +02002068 goto err;
2069
Rabin Vincent0c842b52011-01-25 11:18:35 +01002070 if (sg_next(&sg_src[sg_len - 1]) == sg_src)
2071 desc->cyclic = true;
2072
Rabin Vincent822c5672011-01-25 11:18:28 +01002073 if (direction != DMA_NONE) {
2074 dma_addr_t dev_addr = d40_get_dev_addr(chan, direction);
2075
Vinod Kouldb8196d2011-10-13 22:34:23 +05302076 if (direction == DMA_DEV_TO_MEM)
Rabin Vincent822c5672011-01-25 11:18:28 +01002077 src_dev_addr = dev_addr;
Vinod Kouldb8196d2011-10-13 22:34:23 +05302078 else if (direction == DMA_MEM_TO_DEV)
Rabin Vincent822c5672011-01-25 11:18:28 +01002079 dst_dev_addr = dev_addr;
2080 }
Rabin Vincentcade1d32011-01-25 11:18:23 +01002081
2082 if (chan_is_logical(chan))
2083 ret = d40_prep_sg_log(chan, desc, sg_src, sg_dst,
Rabin Vincent822c5672011-01-25 11:18:28 +01002084 sg_len, src_dev_addr, dst_dev_addr);
Rabin Vincentcade1d32011-01-25 11:18:23 +01002085 else
2086 ret = d40_prep_sg_phy(chan, desc, sg_src, sg_dst,
Rabin Vincent822c5672011-01-25 11:18:28 +01002087 sg_len, src_dev_addr, dst_dev_addr);
Rabin Vincentcade1d32011-01-25 11:18:23 +01002088
2089 if (ret) {
2090 chan_err(chan, "Failed to prepare %s sg job: %d\n",
2091 chan_is_logical(chan) ? "log" : "phy", ret);
2092 goto err;
Linus Walleij8d318a52010-03-30 15:33:42 +02002093 }
2094
Per Forlin82babbb362011-08-29 13:33:35 +02002095 /*
2096 * add descriptor to the prepare queue in order to be able
2097 * to free them later in terminate_all
2098 */
2099 list_add_tail(&desc->node, &chan->prepare_queue);
2100
Rabin Vincentcade1d32011-01-25 11:18:23 +01002101 spin_unlock_irqrestore(&chan->lock, flags);
Linus Walleij8d318a52010-03-30 15:33:42 +02002102
Rabin Vincentcade1d32011-01-25 11:18:23 +01002103 return &desc->txd;
2104
Linus Walleij8d318a52010-03-30 15:33:42 +02002105err:
Rabin Vincentcade1d32011-01-25 11:18:23 +01002106 if (desc)
2107 d40_desc_free(chan, desc);
2108 spin_unlock_irqrestore(&chan->lock, flags);
Linus Walleij8d318a52010-03-30 15:33:42 +02002109 return NULL;
2110}
Linus Walleij8d318a52010-03-30 15:33:42 +02002111
2112bool stedma40_filter(struct dma_chan *chan, void *data)
2113{
2114 struct stedma40_chan_cfg *info = data;
2115 struct d40_chan *d40c =
2116 container_of(chan, struct d40_chan, chan);
2117 int err;
2118
2119 if (data) {
2120 err = d40_validate_conf(d40c, info);
2121 if (!err)
2122 d40c->dma_cfg = *info;
2123 } else
2124 err = d40_config_memcpy(d40c);
2125
Rabin Vincentce2ca122010-10-12 13:00:49 +00002126 if (!err)
2127 d40c->configured = true;
2128
Linus Walleij8d318a52010-03-30 15:33:42 +02002129 return err == 0;
2130}
2131EXPORT_SYMBOL(stedma40_filter);
2132
Rabin Vincentac2c0a32011-01-25 11:18:11 +01002133static void __d40_set_prio_rt(struct d40_chan *d40c, int dev_type, bool src)
2134{
2135 bool realtime = d40c->dma_cfg.realtime;
2136 bool highprio = d40c->dma_cfg.high_priority;
2137 u32 prioreg = highprio ? D40_DREG_PSEG1 : D40_DREG_PCEG1;
2138 u32 rtreg = realtime ? D40_DREG_RSEG1 : D40_DREG_RCEG1;
2139 u32 event = D40_TYPE_TO_EVENT(dev_type);
2140 u32 group = D40_TYPE_TO_GROUP(dev_type);
2141 u32 bit = 1 << event;
2142
2143 /* Destination event lines are stored in the upper halfword */
2144 if (!src)
2145 bit <<= 16;
2146
2147 writel(bit, d40c->base->virtbase + prioreg + group * 4);
2148 writel(bit, d40c->base->virtbase + rtreg + group * 4);
2149}
2150
2151static void d40_set_prio_realtime(struct d40_chan *d40c)
2152{
2153 if (d40c->base->rev < 3)
2154 return;
2155
2156 if ((d40c->dma_cfg.dir == STEDMA40_PERIPH_TO_MEM) ||
2157 (d40c->dma_cfg.dir == STEDMA40_PERIPH_TO_PERIPH))
2158 __d40_set_prio_rt(d40c, d40c->dma_cfg.src_dev_type, true);
2159
2160 if ((d40c->dma_cfg.dir == STEDMA40_MEM_TO_PERIPH) ||
2161 (d40c->dma_cfg.dir == STEDMA40_PERIPH_TO_PERIPH))
2162 __d40_set_prio_rt(d40c, d40c->dma_cfg.dst_dev_type, false);
2163}
2164
Linus Walleij8d318a52010-03-30 15:33:42 +02002165/* DMA ENGINE functions */
2166static int d40_alloc_chan_resources(struct dma_chan *chan)
2167{
2168 int err;
2169 unsigned long flags;
2170 struct d40_chan *d40c =
2171 container_of(chan, struct d40_chan, chan);
Linus Walleijef1872e2010-06-20 21:24:52 +00002172 bool is_free_phy;
Linus Walleij8d318a52010-03-30 15:33:42 +02002173 spin_lock_irqsave(&d40c->lock, flags);
2174
Russell King - ARM Linux4d4e58d2012-03-06 22:34:06 +00002175 chan->completed_cookie = chan->cookie = 1;
Linus Walleij8d318a52010-03-30 15:33:42 +02002176
Rabin Vincentce2ca122010-10-12 13:00:49 +00002177 /* If no dma configuration is set use default configuration (memcpy) */
2178 if (!d40c->configured) {
Linus Walleij8d318a52010-03-30 15:33:42 +02002179 err = d40_config_memcpy(d40c);
Jonas Aabergff0b12b2010-06-20 21:25:15 +00002180 if (err) {
Rabin Vincent6db5a8b2011-01-25 11:18:09 +01002181 chan_err(d40c, "Failed to configure memcpy channel\n");
Jonas Aabergff0b12b2010-06-20 21:25:15 +00002182 goto fail;
2183 }
Linus Walleij8d318a52010-03-30 15:33:42 +02002184 }
2185
Narayanan G5cd326f2011-11-30 19:20:42 +05302186 err = d40_allocate_channel(d40c, &is_free_phy);
Linus Walleij8d318a52010-03-30 15:33:42 +02002187 if (err) {
Rabin Vincent6db5a8b2011-01-25 11:18:09 +01002188 chan_err(d40c, "Failed to allocate channel\n");
Narayanan G7fb3e752011-11-17 17:26:41 +05302189 d40c->configured = false;
Jonas Aabergff0b12b2010-06-20 21:25:15 +00002190 goto fail;
Linus Walleij8d318a52010-03-30 15:33:42 +02002191 }
2192
Narayanan G7fb3e752011-11-17 17:26:41 +05302193 pm_runtime_get_sync(d40c->base->dev);
Linus Walleijef1872e2010-06-20 21:24:52 +00002194 /* Fill in basic CFG register values */
2195 d40_phy_cfg(&d40c->dma_cfg, &d40c->src_def_cfg,
Rabin Vincent724a8572011-01-25 11:18:08 +01002196 &d40c->dst_def_cfg, chan_is_logical(d40c));
Linus Walleijef1872e2010-06-20 21:24:52 +00002197
Rabin Vincentac2c0a32011-01-25 11:18:11 +01002198 d40_set_prio_realtime(d40c);
2199
Rabin Vincent724a8572011-01-25 11:18:08 +01002200 if (chan_is_logical(d40c)) {
Linus Walleijef1872e2010-06-20 21:24:52 +00002201 d40_log_cfg(&d40c->dma_cfg,
2202 &d40c->log_def.lcsp1, &d40c->log_def.lcsp3);
2203
2204 if (d40c->dma_cfg.dir == STEDMA40_PERIPH_TO_MEM)
2205 d40c->lcpa = d40c->base->lcpa_base +
2206 d40c->dma_cfg.src_dev_type * D40_LCPA_CHAN_SIZE;
2207 else
2208 d40c->lcpa = d40c->base->lcpa_base +
2209 d40c->dma_cfg.dst_dev_type *
2210 D40_LCPA_CHAN_SIZE + D40_LCPA_CHAN_DST_DELTA;
2211 }
2212
Narayanan G5cd326f2011-11-30 19:20:42 +05302213 dev_dbg(chan2dev(d40c), "allocated %s channel (phy %d%s)\n",
2214 chan_is_logical(d40c) ? "logical" : "physical",
2215 d40c->phy_chan->num,
2216 d40c->dma_cfg.use_fixed_channel ? ", fixed" : "");
2217
2218
Linus Walleijef1872e2010-06-20 21:24:52 +00002219 /*
2220 * Only write channel configuration to the DMA if the physical
2221 * resource is free. In case of multiple logical channels
2222 * on the same physical resource, only the first write is necessary.
2223 */
Jonas Aabergb55912c2010-08-09 12:08:02 +00002224 if (is_free_phy)
2225 d40_config_write(d40c);
Jonas Aabergff0b12b2010-06-20 21:25:15 +00002226fail:
Narayanan G7fb3e752011-11-17 17:26:41 +05302227 pm_runtime_mark_last_busy(d40c->base->dev);
2228 pm_runtime_put_autosuspend(d40c->base->dev);
Linus Walleij8d318a52010-03-30 15:33:42 +02002229 spin_unlock_irqrestore(&d40c->lock, flags);
Jonas Aabergff0b12b2010-06-20 21:25:15 +00002230 return err;
Linus Walleij8d318a52010-03-30 15:33:42 +02002231}
2232
2233static void d40_free_chan_resources(struct dma_chan *chan)
2234{
2235 struct d40_chan *d40c =
2236 container_of(chan, struct d40_chan, chan);
2237 int err;
2238 unsigned long flags;
2239
Jonas Aaberg0d0f6b82010-06-20 21:25:31 +00002240 if (d40c->phy_chan == NULL) {
Rabin Vincent6db5a8b2011-01-25 11:18:09 +01002241 chan_err(d40c, "Cannot free unallocated channel\n");
Jonas Aaberg0d0f6b82010-06-20 21:25:31 +00002242 return;
2243 }
2244
2245
Linus Walleij8d318a52010-03-30 15:33:42 +02002246 spin_lock_irqsave(&d40c->lock, flags);
2247
2248 err = d40_free_dma(d40c);
2249
2250 if (err)
Rabin Vincent6db5a8b2011-01-25 11:18:09 +01002251 chan_err(d40c, "Failed to free channel\n");
Linus Walleij8d318a52010-03-30 15:33:42 +02002252 spin_unlock_irqrestore(&d40c->lock, flags);
2253}
2254
2255static struct dma_async_tx_descriptor *d40_prep_memcpy(struct dma_chan *chan,
2256 dma_addr_t dst,
2257 dma_addr_t src,
2258 size_t size,
Jonas Aaberg2a614342010-06-20 21:25:24 +00002259 unsigned long dma_flags)
Linus Walleij8d318a52010-03-30 15:33:42 +02002260{
Rabin Vincent95944c62011-01-25 11:18:17 +01002261 struct scatterlist dst_sg;
2262 struct scatterlist src_sg;
Linus Walleij8d318a52010-03-30 15:33:42 +02002263
Rabin Vincent95944c62011-01-25 11:18:17 +01002264 sg_init_table(&dst_sg, 1);
2265 sg_init_table(&src_sg, 1);
Jonas Aaberg0d0f6b82010-06-20 21:25:31 +00002266
Rabin Vincent95944c62011-01-25 11:18:17 +01002267 sg_dma_address(&dst_sg) = dst;
2268 sg_dma_address(&src_sg) = src;
Linus Walleij8d318a52010-03-30 15:33:42 +02002269
Rabin Vincent95944c62011-01-25 11:18:17 +01002270 sg_dma_len(&dst_sg) = size;
2271 sg_dma_len(&src_sg) = size;
Linus Walleij8d318a52010-03-30 15:33:42 +02002272
Rabin Vincentcade1d32011-01-25 11:18:23 +01002273 return d40_prep_sg(chan, &src_sg, &dst_sg, 1, DMA_NONE, dma_flags);
Linus Walleij8d318a52010-03-30 15:33:42 +02002274}
2275
Ira Snyder0d688662010-09-30 11:46:47 +00002276static struct dma_async_tx_descriptor *
Rabin Vincentcade1d32011-01-25 11:18:23 +01002277d40_prep_memcpy_sg(struct dma_chan *chan,
2278 struct scatterlist *dst_sg, unsigned int dst_nents,
2279 struct scatterlist *src_sg, unsigned int src_nents,
2280 unsigned long dma_flags)
Ira Snyder0d688662010-09-30 11:46:47 +00002281{
2282 if (dst_nents != src_nents)
2283 return NULL;
2284
Rabin Vincentcade1d32011-01-25 11:18:23 +01002285 return d40_prep_sg(chan, src_sg, dst_sg, src_nents, DMA_NONE, dma_flags);
Rabin Vincent00ac0342011-01-25 11:18:20 +01002286}
2287
Linus Walleij8d318a52010-03-30 15:33:42 +02002288static struct dma_async_tx_descriptor *d40_prep_slave_sg(struct dma_chan *chan,
2289 struct scatterlist *sgl,
2290 unsigned int sg_len,
Vinod Kouldb8196d2011-10-13 22:34:23 +05302291 enum dma_transfer_direction direction,
Jonas Aaberg2a614342010-06-20 21:25:24 +00002292 unsigned long dma_flags)
Linus Walleij8d318a52010-03-30 15:33:42 +02002293{
Vinod Kouldb8196d2011-10-13 22:34:23 +05302294 if (direction != DMA_DEV_TO_MEM && direction != DMA_MEM_TO_DEV)
Rabin Vincent00ac0342011-01-25 11:18:20 +01002295 return NULL;
2296
Rabin Vincentcade1d32011-01-25 11:18:23 +01002297 return d40_prep_sg(chan, sgl, sgl, sg_len, direction, dma_flags);
Linus Walleij8d318a52010-03-30 15:33:42 +02002298}
2299
Rabin Vincent0c842b52011-01-25 11:18:35 +01002300static struct dma_async_tx_descriptor *
2301dma40_prep_dma_cyclic(struct dma_chan *chan, dma_addr_t dma_addr,
2302 size_t buf_len, size_t period_len,
Vinod Kouldb8196d2011-10-13 22:34:23 +05302303 enum dma_transfer_direction direction)
Rabin Vincent0c842b52011-01-25 11:18:35 +01002304{
2305 unsigned int periods = buf_len / period_len;
2306 struct dma_async_tx_descriptor *txd;
2307 struct scatterlist *sg;
2308 int i;
2309
Robert Marklund79ca7ec2011-06-27 11:33:24 +02002310 sg = kcalloc(periods + 1, sizeof(struct scatterlist), GFP_NOWAIT);
Rabin Vincent0c842b52011-01-25 11:18:35 +01002311 for (i = 0; i < periods; i++) {
2312 sg_dma_address(&sg[i]) = dma_addr;
2313 sg_dma_len(&sg[i]) = period_len;
2314 dma_addr += period_len;
2315 }
2316
2317 sg[periods].offset = 0;
2318 sg[periods].length = 0;
2319 sg[periods].page_link =
2320 ((unsigned long)sg | 0x01) & ~0x02;
2321
2322 txd = d40_prep_sg(chan, sg, sg, periods, direction,
2323 DMA_PREP_INTERRUPT);
2324
2325 kfree(sg);
2326
2327 return txd;
2328}
2329
Linus Walleij8d318a52010-03-30 15:33:42 +02002330static enum dma_status d40_tx_status(struct dma_chan *chan,
2331 dma_cookie_t cookie,
2332 struct dma_tx_state *txstate)
2333{
2334 struct d40_chan *d40c = container_of(chan, struct d40_chan, chan);
Russell King - ARM Linux96a2af42012-03-06 22:35:27 +00002335 enum dma_status ret;
Linus Walleij8d318a52010-03-30 15:33:42 +02002336
Jonas Aaberg0d0f6b82010-06-20 21:25:31 +00002337 if (d40c->phy_chan == NULL) {
Rabin Vincent6db5a8b2011-01-25 11:18:09 +01002338 chan_err(d40c, "Cannot read status of unallocated channel\n");
Jonas Aaberg0d0f6b82010-06-20 21:25:31 +00002339 return -EINVAL;
2340 }
2341
Russell King - ARM Linux96a2af42012-03-06 22:35:27 +00002342 ret = dma_cookie_status(chan, cookie, txstate);
2343 if (ret != DMA_SUCCESS)
2344 dma_set_residue(txstate, stedma40_residue(chan));
Linus Walleij8d318a52010-03-30 15:33:42 +02002345
Jonas Aaberga5ebca42010-05-18 00:41:09 +02002346 if (d40_is_paused(d40c))
2347 ret = DMA_PAUSED;
Linus Walleij8d318a52010-03-30 15:33:42 +02002348
2349 return ret;
2350}
2351
2352static void d40_issue_pending(struct dma_chan *chan)
2353{
2354 struct d40_chan *d40c = container_of(chan, struct d40_chan, chan);
2355 unsigned long flags;
2356
Jonas Aaberg0d0f6b82010-06-20 21:25:31 +00002357 if (d40c->phy_chan == NULL) {
Rabin Vincent6db5a8b2011-01-25 11:18:09 +01002358 chan_err(d40c, "Channel is not allocated!\n");
Jonas Aaberg0d0f6b82010-06-20 21:25:31 +00002359 return;
2360 }
2361
Linus Walleij8d318a52010-03-30 15:33:42 +02002362 spin_lock_irqsave(&d40c->lock, flags);
2363
Per Forlina8f30672011-06-26 23:29:52 +02002364 list_splice_tail_init(&d40c->pending_queue, &d40c->queue);
2365
2366 /* Busy means that queued jobs are already being processed */
Linus Walleij8d318a52010-03-30 15:33:42 +02002367 if (!d40c->busy)
2368 (void) d40_queue_start(d40c);
2369
2370 spin_unlock_irqrestore(&d40c->lock, flags);
2371}
2372
Rabin Vincent98ca5282011-06-27 11:33:38 +02002373static int
2374dma40_config_to_halfchannel(struct d40_chan *d40c,
2375 struct stedma40_half_channel_info *info,
2376 enum dma_slave_buswidth width,
2377 u32 maxburst)
2378{
2379 enum stedma40_periph_data_width addr_width;
2380 int psize;
2381
2382 switch (width) {
2383 case DMA_SLAVE_BUSWIDTH_1_BYTE:
2384 addr_width = STEDMA40_BYTE_WIDTH;
2385 break;
2386 case DMA_SLAVE_BUSWIDTH_2_BYTES:
2387 addr_width = STEDMA40_HALFWORD_WIDTH;
2388 break;
2389 case DMA_SLAVE_BUSWIDTH_4_BYTES:
2390 addr_width = STEDMA40_WORD_WIDTH;
2391 break;
2392 case DMA_SLAVE_BUSWIDTH_8_BYTES:
2393 addr_width = STEDMA40_DOUBLEWORD_WIDTH;
2394 break;
2395 default:
2396 dev_err(d40c->base->dev,
2397 "illegal peripheral address width "
2398 "requested (%d)\n",
2399 width);
2400 return -EINVAL;
2401 }
2402
2403 if (chan_is_logical(d40c)) {
2404 if (maxburst >= 16)
2405 psize = STEDMA40_PSIZE_LOG_16;
2406 else if (maxburst >= 8)
2407 psize = STEDMA40_PSIZE_LOG_8;
2408 else if (maxburst >= 4)
2409 psize = STEDMA40_PSIZE_LOG_4;
2410 else
2411 psize = STEDMA40_PSIZE_LOG_1;
2412 } else {
2413 if (maxburst >= 16)
2414 psize = STEDMA40_PSIZE_PHY_16;
2415 else if (maxburst >= 8)
2416 psize = STEDMA40_PSIZE_PHY_8;
2417 else if (maxburst >= 4)
2418 psize = STEDMA40_PSIZE_PHY_4;
2419 else
2420 psize = STEDMA40_PSIZE_PHY_1;
2421 }
2422
2423 info->data_width = addr_width;
2424 info->psize = psize;
2425 info->flow_ctrl = STEDMA40_NO_FLOW_CTRL;
2426
2427 return 0;
2428}
2429
Linus Walleij95e14002010-08-04 13:37:45 +02002430/* Runtime reconfiguration extension */
Rabin Vincent98ca5282011-06-27 11:33:38 +02002431static int d40_set_runtime_config(struct dma_chan *chan,
2432 struct dma_slave_config *config)
Linus Walleij95e14002010-08-04 13:37:45 +02002433{
2434 struct d40_chan *d40c = container_of(chan, struct d40_chan, chan);
2435 struct stedma40_chan_cfg *cfg = &d40c->dma_cfg;
Rabin Vincent98ca5282011-06-27 11:33:38 +02002436 enum dma_slave_buswidth src_addr_width, dst_addr_width;
Linus Walleij95e14002010-08-04 13:37:45 +02002437 dma_addr_t config_addr;
Rabin Vincent98ca5282011-06-27 11:33:38 +02002438 u32 src_maxburst, dst_maxburst;
2439 int ret;
2440
2441 src_addr_width = config->src_addr_width;
2442 src_maxburst = config->src_maxburst;
2443 dst_addr_width = config->dst_addr_width;
2444 dst_maxburst = config->dst_maxburst;
Linus Walleij95e14002010-08-04 13:37:45 +02002445
Vinod Kouldb8196d2011-10-13 22:34:23 +05302446 if (config->direction == DMA_DEV_TO_MEM) {
Linus Walleij95e14002010-08-04 13:37:45 +02002447 dma_addr_t dev_addr_rx =
2448 d40c->base->plat_data->dev_rx[cfg->src_dev_type];
2449
2450 config_addr = config->src_addr;
2451 if (dev_addr_rx)
2452 dev_dbg(d40c->base->dev,
2453 "channel has a pre-wired RX address %08x "
2454 "overriding with %08x\n",
2455 dev_addr_rx, config_addr);
2456 if (cfg->dir != STEDMA40_PERIPH_TO_MEM)
2457 dev_dbg(d40c->base->dev,
2458 "channel was not configured for peripheral "
2459 "to memory transfer (%d) overriding\n",
2460 cfg->dir);
2461 cfg->dir = STEDMA40_PERIPH_TO_MEM;
2462
Rabin Vincent98ca5282011-06-27 11:33:38 +02002463 /* Configure the memory side */
2464 if (dst_addr_width == DMA_SLAVE_BUSWIDTH_UNDEFINED)
2465 dst_addr_width = src_addr_width;
2466 if (dst_maxburst == 0)
2467 dst_maxburst = src_maxburst;
Linus Walleij95e14002010-08-04 13:37:45 +02002468
Vinod Kouldb8196d2011-10-13 22:34:23 +05302469 } else if (config->direction == DMA_MEM_TO_DEV) {
Linus Walleij95e14002010-08-04 13:37:45 +02002470 dma_addr_t dev_addr_tx =
2471 d40c->base->plat_data->dev_tx[cfg->dst_dev_type];
2472
2473 config_addr = config->dst_addr;
2474 if (dev_addr_tx)
2475 dev_dbg(d40c->base->dev,
2476 "channel has a pre-wired TX address %08x "
2477 "overriding with %08x\n",
2478 dev_addr_tx, config_addr);
2479 if (cfg->dir != STEDMA40_MEM_TO_PERIPH)
2480 dev_dbg(d40c->base->dev,
2481 "channel was not configured for memory "
2482 "to peripheral transfer (%d) overriding\n",
2483 cfg->dir);
2484 cfg->dir = STEDMA40_MEM_TO_PERIPH;
2485
Rabin Vincent98ca5282011-06-27 11:33:38 +02002486 /* Configure the memory side */
2487 if (src_addr_width == DMA_SLAVE_BUSWIDTH_UNDEFINED)
2488 src_addr_width = dst_addr_width;
2489 if (src_maxburst == 0)
2490 src_maxburst = dst_maxburst;
Linus Walleij95e14002010-08-04 13:37:45 +02002491 } else {
2492 dev_err(d40c->base->dev,
2493 "unrecognized channel direction %d\n",
2494 config->direction);
Rabin Vincent98ca5282011-06-27 11:33:38 +02002495 return -EINVAL;
Linus Walleij95e14002010-08-04 13:37:45 +02002496 }
2497
Rabin Vincent98ca5282011-06-27 11:33:38 +02002498 if (src_maxburst * src_addr_width != dst_maxburst * dst_addr_width) {
Linus Walleij95e14002010-08-04 13:37:45 +02002499 dev_err(d40c->base->dev,
Rabin Vincent98ca5282011-06-27 11:33:38 +02002500 "src/dst width/maxburst mismatch: %d*%d != %d*%d\n",
2501 src_maxburst,
2502 src_addr_width,
2503 dst_maxburst,
2504 dst_addr_width);
2505 return -EINVAL;
Linus Walleij95e14002010-08-04 13:37:45 +02002506 }
2507
Rabin Vincent98ca5282011-06-27 11:33:38 +02002508 ret = dma40_config_to_halfchannel(d40c, &cfg->src_info,
2509 src_addr_width,
2510 src_maxburst);
2511 if (ret)
2512 return ret;
Linus Walleij95e14002010-08-04 13:37:45 +02002513
Rabin Vincent98ca5282011-06-27 11:33:38 +02002514 ret = dma40_config_to_halfchannel(d40c, &cfg->dst_info,
2515 dst_addr_width,
2516 dst_maxburst);
2517 if (ret)
2518 return ret;
Linus Walleij95e14002010-08-04 13:37:45 +02002519
Per Forlina59670a2010-10-06 09:05:27 +00002520 /* Fill in register values */
Rabin Vincent724a8572011-01-25 11:18:08 +01002521 if (chan_is_logical(d40c))
Per Forlina59670a2010-10-06 09:05:27 +00002522 d40_log_cfg(cfg, &d40c->log_def.lcsp1, &d40c->log_def.lcsp3);
2523 else
2524 d40_phy_cfg(cfg, &d40c->src_def_cfg,
2525 &d40c->dst_def_cfg, false);
2526
Linus Walleij95e14002010-08-04 13:37:45 +02002527 /* These settings will take precedence later */
2528 d40c->runtime_addr = config_addr;
2529 d40c->runtime_direction = config->direction;
2530 dev_dbg(d40c->base->dev,
Rabin Vincent98ca5282011-06-27 11:33:38 +02002531 "configured channel %s for %s, data width %d/%d, "
2532 "maxburst %d/%d elements, LE, no flow control\n",
Linus Walleij95e14002010-08-04 13:37:45 +02002533 dma_chan_name(chan),
Vinod Kouldb8196d2011-10-13 22:34:23 +05302534 (config->direction == DMA_DEV_TO_MEM) ? "RX" : "TX",
Rabin Vincent98ca5282011-06-27 11:33:38 +02002535 src_addr_width, dst_addr_width,
2536 src_maxburst, dst_maxburst);
2537
2538 return 0;
Linus Walleij95e14002010-08-04 13:37:45 +02002539}
2540
Linus Walleij05827632010-05-17 16:30:42 -07002541static int d40_control(struct dma_chan *chan, enum dma_ctrl_cmd cmd,
2542 unsigned long arg)
Linus Walleij8d318a52010-03-30 15:33:42 +02002543{
Linus Walleij8d318a52010-03-30 15:33:42 +02002544 struct d40_chan *d40c = container_of(chan, struct d40_chan, chan);
2545
Jonas Aaberg0d0f6b82010-06-20 21:25:31 +00002546 if (d40c->phy_chan == NULL) {
Rabin Vincent6db5a8b2011-01-25 11:18:09 +01002547 chan_err(d40c, "Channel is not allocated!\n");
Jonas Aaberg0d0f6b82010-06-20 21:25:31 +00002548 return -EINVAL;
2549 }
2550
Linus Walleij8d318a52010-03-30 15:33:42 +02002551 switch (cmd) {
2552 case DMA_TERMINATE_ALL:
Rabin Vincent86eb5fb2011-01-25 11:18:34 +01002553 return d40_terminate_all(d40c);
Linus Walleij8d318a52010-03-30 15:33:42 +02002554 case DMA_PAUSE:
Rabin Vincent86eb5fb2011-01-25 11:18:34 +01002555 return d40_pause(d40c);
Linus Walleij8d318a52010-03-30 15:33:42 +02002556 case DMA_RESUME:
Rabin Vincent86eb5fb2011-01-25 11:18:34 +01002557 return d40_resume(d40c);
Linus Walleij95e14002010-08-04 13:37:45 +02002558 case DMA_SLAVE_CONFIG:
Rabin Vincent98ca5282011-06-27 11:33:38 +02002559 return d40_set_runtime_config(chan,
Linus Walleij95e14002010-08-04 13:37:45 +02002560 (struct dma_slave_config *) arg);
Linus Walleij95e14002010-08-04 13:37:45 +02002561 default:
2562 break;
Linus Walleij8d318a52010-03-30 15:33:42 +02002563 }
2564
2565 /* Other commands are unimplemented */
2566 return -ENXIO;
2567}
2568
2569/* Initialization functions */
2570
2571static void __init d40_chan_init(struct d40_base *base, struct dma_device *dma,
2572 struct d40_chan *chans, int offset,
2573 int num_chans)
2574{
2575 int i = 0;
2576 struct d40_chan *d40c;
2577
2578 INIT_LIST_HEAD(&dma->channels);
2579
2580 for (i = offset; i < offset + num_chans; i++) {
2581 d40c = &chans[i];
2582 d40c->base = base;
2583 d40c->chan.device = dma;
2584
Linus Walleij8d318a52010-03-30 15:33:42 +02002585 spin_lock_init(&d40c->lock);
2586
2587 d40c->log_num = D40_PHY_CHAN;
2588
Linus Walleij8d318a52010-03-30 15:33:42 +02002589 INIT_LIST_HEAD(&d40c->active);
2590 INIT_LIST_HEAD(&d40c->queue);
Per Forlina8f30672011-06-26 23:29:52 +02002591 INIT_LIST_HEAD(&d40c->pending_queue);
Linus Walleij8d318a52010-03-30 15:33:42 +02002592 INIT_LIST_HEAD(&d40c->client);
Per Forlin82babbb362011-08-29 13:33:35 +02002593 INIT_LIST_HEAD(&d40c->prepare_queue);
Linus Walleij8d318a52010-03-30 15:33:42 +02002594
Linus Walleij8d318a52010-03-30 15:33:42 +02002595 tasklet_init(&d40c->tasklet, dma_tasklet,
2596 (unsigned long) d40c);
2597
2598 list_add_tail(&d40c->chan.device_node,
2599 &dma->channels);
2600 }
2601}
2602
Rabin Vincent7ad74a72011-01-25 11:18:33 +01002603static void d40_ops_init(struct d40_base *base, struct dma_device *dev)
2604{
2605 if (dma_has_cap(DMA_SLAVE, dev->cap_mask))
2606 dev->device_prep_slave_sg = d40_prep_slave_sg;
2607
2608 if (dma_has_cap(DMA_MEMCPY, dev->cap_mask)) {
2609 dev->device_prep_dma_memcpy = d40_prep_memcpy;
2610
2611 /*
2612 * This controller can only access address at even
2613 * 32bit boundaries, i.e. 2^2
2614 */
2615 dev->copy_align = 2;
2616 }
2617
2618 if (dma_has_cap(DMA_SG, dev->cap_mask))
2619 dev->device_prep_dma_sg = d40_prep_memcpy_sg;
2620
Rabin Vincent0c842b52011-01-25 11:18:35 +01002621 if (dma_has_cap(DMA_CYCLIC, dev->cap_mask))
2622 dev->device_prep_dma_cyclic = dma40_prep_dma_cyclic;
2623
Rabin Vincent7ad74a72011-01-25 11:18:33 +01002624 dev->device_alloc_chan_resources = d40_alloc_chan_resources;
2625 dev->device_free_chan_resources = d40_free_chan_resources;
2626 dev->device_issue_pending = d40_issue_pending;
2627 dev->device_tx_status = d40_tx_status;
2628 dev->device_control = d40_control;
2629 dev->dev = base->dev;
2630}
2631
Linus Walleij8d318a52010-03-30 15:33:42 +02002632static int __init d40_dmaengine_init(struct d40_base *base,
2633 int num_reserved_chans)
2634{
2635 int err ;
2636
2637 d40_chan_init(base, &base->dma_slave, base->log_chans,
2638 0, base->num_log_chans);
2639
2640 dma_cap_zero(base->dma_slave.cap_mask);
2641 dma_cap_set(DMA_SLAVE, base->dma_slave.cap_mask);
Rabin Vincent0c842b52011-01-25 11:18:35 +01002642 dma_cap_set(DMA_CYCLIC, base->dma_slave.cap_mask);
Linus Walleij8d318a52010-03-30 15:33:42 +02002643
Rabin Vincent7ad74a72011-01-25 11:18:33 +01002644 d40_ops_init(base, &base->dma_slave);
Linus Walleij8d318a52010-03-30 15:33:42 +02002645
2646 err = dma_async_device_register(&base->dma_slave);
2647
2648 if (err) {
Rabin Vincent6db5a8b2011-01-25 11:18:09 +01002649 d40_err(base->dev, "Failed to register slave channels\n");
Linus Walleij8d318a52010-03-30 15:33:42 +02002650 goto failure1;
2651 }
2652
2653 d40_chan_init(base, &base->dma_memcpy, base->log_chans,
2654 base->num_log_chans, base->plat_data->memcpy_len);
2655
2656 dma_cap_zero(base->dma_memcpy.cap_mask);
2657 dma_cap_set(DMA_MEMCPY, base->dma_memcpy.cap_mask);
Rabin Vincent7ad74a72011-01-25 11:18:33 +01002658 dma_cap_set(DMA_SG, base->dma_memcpy.cap_mask);
Linus Walleij8d318a52010-03-30 15:33:42 +02002659
Rabin Vincent7ad74a72011-01-25 11:18:33 +01002660 d40_ops_init(base, &base->dma_memcpy);
Linus Walleij8d318a52010-03-30 15:33:42 +02002661
2662 err = dma_async_device_register(&base->dma_memcpy);
2663
2664 if (err) {
Rabin Vincent6db5a8b2011-01-25 11:18:09 +01002665 d40_err(base->dev,
2666 "Failed to regsiter memcpy only channels\n");
Linus Walleij8d318a52010-03-30 15:33:42 +02002667 goto failure2;
2668 }
2669
2670 d40_chan_init(base, &base->dma_both, base->phy_chans,
2671 0, num_reserved_chans);
2672
2673 dma_cap_zero(base->dma_both.cap_mask);
2674 dma_cap_set(DMA_SLAVE, base->dma_both.cap_mask);
2675 dma_cap_set(DMA_MEMCPY, base->dma_both.cap_mask);
Rabin Vincent7ad74a72011-01-25 11:18:33 +01002676 dma_cap_set(DMA_SG, base->dma_both.cap_mask);
Rabin Vincent0c842b52011-01-25 11:18:35 +01002677 dma_cap_set(DMA_CYCLIC, base->dma_slave.cap_mask);
Linus Walleij8d318a52010-03-30 15:33:42 +02002678
Rabin Vincent7ad74a72011-01-25 11:18:33 +01002679 d40_ops_init(base, &base->dma_both);
Linus Walleij8d318a52010-03-30 15:33:42 +02002680 err = dma_async_device_register(&base->dma_both);
2681
2682 if (err) {
Rabin Vincent6db5a8b2011-01-25 11:18:09 +01002683 d40_err(base->dev,
2684 "Failed to register logical and physical capable channels\n");
Linus Walleij8d318a52010-03-30 15:33:42 +02002685 goto failure3;
2686 }
2687 return 0;
2688failure3:
2689 dma_async_device_unregister(&base->dma_memcpy);
2690failure2:
2691 dma_async_device_unregister(&base->dma_slave);
2692failure1:
2693 return err;
2694}
2695
Narayanan G7fb3e752011-11-17 17:26:41 +05302696/* Suspend resume functionality */
2697#ifdef CONFIG_PM
2698static int dma40_pm_suspend(struct device *dev)
2699{
Narayanan G28c7a192011-11-22 13:56:55 +05302700 struct platform_device *pdev = to_platform_device(dev);
2701 struct d40_base *base = platform_get_drvdata(pdev);
2702 int ret = 0;
Narayanan G7fb3e752011-11-17 17:26:41 +05302703 if (!pm_runtime_suspended(dev))
2704 return -EBUSY;
2705
Narayanan G28c7a192011-11-22 13:56:55 +05302706 if (base->lcpa_regulator)
2707 ret = regulator_disable(base->lcpa_regulator);
2708 return ret;
Narayanan G7fb3e752011-11-17 17:26:41 +05302709}
2710
2711static int dma40_runtime_suspend(struct device *dev)
2712{
2713 struct platform_device *pdev = to_platform_device(dev);
2714 struct d40_base *base = platform_get_drvdata(pdev);
2715
2716 d40_save_restore_registers(base, true);
2717
2718 /* Don't disable/enable clocks for v1 due to HW bugs */
2719 if (base->rev != 1)
2720 writel_relaxed(base->gcc_pwr_off_mask,
2721 base->virtbase + D40_DREG_GCC);
2722
2723 return 0;
2724}
2725
2726static int dma40_runtime_resume(struct device *dev)
2727{
2728 struct platform_device *pdev = to_platform_device(dev);
2729 struct d40_base *base = platform_get_drvdata(pdev);
2730
2731 if (base->initialized)
2732 d40_save_restore_registers(base, false);
2733
2734 writel_relaxed(D40_DREG_GCC_ENABLE_ALL,
2735 base->virtbase + D40_DREG_GCC);
2736 return 0;
2737}
2738
Narayanan G28c7a192011-11-22 13:56:55 +05302739static int dma40_resume(struct device *dev)
2740{
2741 struct platform_device *pdev = to_platform_device(dev);
2742 struct d40_base *base = platform_get_drvdata(pdev);
2743 int ret = 0;
2744
2745 if (base->lcpa_regulator)
2746 ret = regulator_enable(base->lcpa_regulator);
2747
2748 return ret;
2749}
Narayanan G7fb3e752011-11-17 17:26:41 +05302750
2751static const struct dev_pm_ops dma40_pm_ops = {
2752 .suspend = dma40_pm_suspend,
2753 .runtime_suspend = dma40_runtime_suspend,
2754 .runtime_resume = dma40_runtime_resume,
Narayanan G28c7a192011-11-22 13:56:55 +05302755 .resume = dma40_resume,
Narayanan G7fb3e752011-11-17 17:26:41 +05302756};
2757#define DMA40_PM_OPS (&dma40_pm_ops)
2758#else
2759#define DMA40_PM_OPS NULL
2760#endif
2761
Linus Walleij8d318a52010-03-30 15:33:42 +02002762/* Initialization functions. */
2763
2764static int __init d40_phy_res_init(struct d40_base *base)
2765{
2766 int i;
2767 int num_phy_chans_avail = 0;
2768 u32 val[2];
2769 int odd_even_bit = -2;
Narayanan G7fb3e752011-11-17 17:26:41 +05302770 int gcc = D40_DREG_GCC_ENA;
Linus Walleij8d318a52010-03-30 15:33:42 +02002771
2772 val[0] = readl(base->virtbase + D40_DREG_PRSME);
2773 val[1] = readl(base->virtbase + D40_DREG_PRSMO);
2774
2775 for (i = 0; i < base->num_phy_chans; i++) {
2776 base->phy_res[i].num = i;
2777 odd_even_bit += 2 * ((i % 2) == 0);
2778 if (((val[i % 2] >> odd_even_bit) & 3) == 1) {
2779 /* Mark security only channels as occupied */
2780 base->phy_res[i].allocated_src = D40_ALLOC_PHY;
2781 base->phy_res[i].allocated_dst = D40_ALLOC_PHY;
Narayanan G7fb3e752011-11-17 17:26:41 +05302782 base->phy_res[i].reserved = true;
2783 gcc |= D40_DREG_GCC_EVTGRP_ENA(D40_PHYS_TO_GROUP(i),
2784 D40_DREG_GCC_SRC);
2785 gcc |= D40_DREG_GCC_EVTGRP_ENA(D40_PHYS_TO_GROUP(i),
2786 D40_DREG_GCC_DST);
2787
2788
Linus Walleij8d318a52010-03-30 15:33:42 +02002789 } else {
2790 base->phy_res[i].allocated_src = D40_ALLOC_FREE;
2791 base->phy_res[i].allocated_dst = D40_ALLOC_FREE;
Narayanan G7fb3e752011-11-17 17:26:41 +05302792 base->phy_res[i].reserved = false;
Linus Walleij8d318a52010-03-30 15:33:42 +02002793 num_phy_chans_avail++;
2794 }
2795 spin_lock_init(&base->phy_res[i].lock);
2796 }
Jonas Aaberg6b7acd82010-06-20 21:26:59 +00002797
2798 /* Mark disabled channels as occupied */
2799 for (i = 0; base->plat_data->disabled_channels[i] != -1; i++) {
Rabin Vincentf57b4072010-10-06 08:20:35 +00002800 int chan = base->plat_data->disabled_channels[i];
2801
2802 base->phy_res[chan].allocated_src = D40_ALLOC_PHY;
2803 base->phy_res[chan].allocated_dst = D40_ALLOC_PHY;
Narayanan G7fb3e752011-11-17 17:26:41 +05302804 base->phy_res[chan].reserved = true;
2805 gcc |= D40_DREG_GCC_EVTGRP_ENA(D40_PHYS_TO_GROUP(chan),
2806 D40_DREG_GCC_SRC);
2807 gcc |= D40_DREG_GCC_EVTGRP_ENA(D40_PHYS_TO_GROUP(chan),
2808 D40_DREG_GCC_DST);
Rabin Vincentf57b4072010-10-06 08:20:35 +00002809 num_phy_chans_avail--;
Jonas Aaberg6b7acd82010-06-20 21:26:59 +00002810 }
2811
Linus Walleij8d318a52010-03-30 15:33:42 +02002812 dev_info(base->dev, "%d of %d physical DMA channels available\n",
2813 num_phy_chans_avail, base->num_phy_chans);
2814
2815 /* Verify settings extended vs standard */
2816 val[0] = readl(base->virtbase + D40_DREG_PRTYP);
2817
2818 for (i = 0; i < base->num_phy_chans; i++) {
2819
2820 if (base->phy_res[i].allocated_src == D40_ALLOC_FREE &&
2821 (val[0] & 0x3) != 1)
2822 dev_info(base->dev,
2823 "[%s] INFO: channel %d is misconfigured (%d)\n",
2824 __func__, i, val[0] & 0x3);
2825
2826 val[0] = val[0] >> 2;
2827 }
2828
Narayanan G7fb3e752011-11-17 17:26:41 +05302829 /*
2830 * To keep things simple, Enable all clocks initially.
2831 * The clocks will get managed later post channel allocation.
2832 * The clocks for the event lines on which reserved channels exists
2833 * are not managed here.
2834 */
2835 writel(D40_DREG_GCC_ENABLE_ALL, base->virtbase + D40_DREG_GCC);
2836 base->gcc_pwr_off_mask = gcc;
2837
Linus Walleij8d318a52010-03-30 15:33:42 +02002838 return num_phy_chans_avail;
2839}
2840
2841static struct d40_base * __init d40_hw_detect_init(struct platform_device *pdev)
2842{
Linus Walleij8d318a52010-03-30 15:33:42 +02002843 struct stedma40_platform_data *plat_data;
2844 struct clk *clk = NULL;
2845 void __iomem *virtbase = NULL;
2846 struct resource *res = NULL;
2847 struct d40_base *base = NULL;
2848 int num_log_chans = 0;
2849 int num_phy_chans;
2850 int i;
Linus Walleijf4b89762011-06-27 11:33:46 +02002851 u32 pid;
2852 u32 cid;
2853 u8 rev;
Linus Walleij8d318a52010-03-30 15:33:42 +02002854
2855 clk = clk_get(&pdev->dev, NULL);
2856
2857 if (IS_ERR(clk)) {
Rabin Vincent6db5a8b2011-01-25 11:18:09 +01002858 d40_err(&pdev->dev, "No matching clock found\n");
Linus Walleij8d318a52010-03-30 15:33:42 +02002859 goto failure;
2860 }
2861
2862 clk_enable(clk);
2863
2864 /* Get IO for DMAC base address */
2865 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "base");
2866 if (!res)
2867 goto failure;
2868
2869 if (request_mem_region(res->start, resource_size(res),
2870 D40_NAME " I/O base") == NULL)
2871 goto failure;
2872
2873 virtbase = ioremap(res->start, resource_size(res));
2874 if (!virtbase)
2875 goto failure;
2876
Linus Walleijf4b89762011-06-27 11:33:46 +02002877 /* This is just a regular AMBA PrimeCell ID actually */
2878 for (pid = 0, i = 0; i < 4; i++)
2879 pid |= (readl(virtbase + resource_size(res) - 0x20 + 4 * i)
2880 & 255) << (i * 8);
2881 for (cid = 0, i = 0; i < 4; i++)
2882 cid |= (readl(virtbase + resource_size(res) - 0x10 + 4 * i)
2883 & 255) << (i * 8);
Linus Walleij8d318a52010-03-30 15:33:42 +02002884
Linus Walleijf4b89762011-06-27 11:33:46 +02002885 if (cid != AMBA_CID) {
2886 d40_err(&pdev->dev, "Unknown hardware! No PrimeCell ID\n");
Linus Walleij8d318a52010-03-30 15:33:42 +02002887 goto failure;
2888 }
Linus Walleijf4b89762011-06-27 11:33:46 +02002889 if (AMBA_MANF_BITS(pid) != AMBA_VENDOR_ST) {
2890 d40_err(&pdev->dev, "Unknown designer! Got %x wanted %x\n",
2891 AMBA_MANF_BITS(pid),
2892 AMBA_VENDOR_ST);
2893 goto failure;
2894 }
2895 /*
2896 * HW revision:
2897 * DB8500ed has revision 0
2898 * ? has revision 1
2899 * DB8500v1 has revision 2
2900 * DB8500v2 has revision 3
2901 */
2902 rev = AMBA_REV_BITS(pid);
Jonas Aaberg3ae02672010-08-09 12:08:18 +00002903
Linus Walleij8d318a52010-03-30 15:33:42 +02002904 /* The number of physical channels on this HW */
2905 num_phy_chans = 4 * (readl(virtbase + D40_DREG_ICFG) & 0x7) + 4;
2906
2907 dev_info(&pdev->dev, "hardware revision: %d @ 0x%x\n",
Jonas Aaberg3ae02672010-08-09 12:08:18 +00002908 rev, res->start);
Linus Walleij8d318a52010-03-30 15:33:42 +02002909
2910 plat_data = pdev->dev.platform_data;
2911
2912 /* Count the number of logical channels in use */
2913 for (i = 0; i < plat_data->dev_len; i++)
2914 if (plat_data->dev_rx[i] != 0)
2915 num_log_chans++;
2916
2917 for (i = 0; i < plat_data->dev_len; i++)
2918 if (plat_data->dev_tx[i] != 0)
2919 num_log_chans++;
2920
2921 base = kzalloc(ALIGN(sizeof(struct d40_base), 4) +
2922 (num_phy_chans + num_log_chans + plat_data->memcpy_len) *
2923 sizeof(struct d40_chan), GFP_KERNEL);
2924
2925 if (base == NULL) {
Rabin Vincent6db5a8b2011-01-25 11:18:09 +01002926 d40_err(&pdev->dev, "Out of memory\n");
Linus Walleij8d318a52010-03-30 15:33:42 +02002927 goto failure;
2928 }
2929
Jonas Aaberg3ae02672010-08-09 12:08:18 +00002930 base->rev = rev;
Linus Walleij8d318a52010-03-30 15:33:42 +02002931 base->clk = clk;
2932 base->num_phy_chans = num_phy_chans;
2933 base->num_log_chans = num_log_chans;
2934 base->phy_start = res->start;
2935 base->phy_size = resource_size(res);
2936 base->virtbase = virtbase;
2937 base->plat_data = plat_data;
2938 base->dev = &pdev->dev;
2939 base->phy_chans = ((void *)base) + ALIGN(sizeof(struct d40_base), 4);
2940 base->log_chans = &base->phy_chans[num_phy_chans];
2941
2942 base->phy_res = kzalloc(num_phy_chans * sizeof(struct d40_phy_res),
2943 GFP_KERNEL);
2944 if (!base->phy_res)
2945 goto failure;
2946
2947 base->lookup_phy_chans = kzalloc(num_phy_chans *
2948 sizeof(struct d40_chan *),
2949 GFP_KERNEL);
2950 if (!base->lookup_phy_chans)
2951 goto failure;
2952
2953 if (num_log_chans + plat_data->memcpy_len) {
2954 /*
2955 * The max number of logical channels are event lines for all
2956 * src devices and dst devices
2957 */
2958 base->lookup_log_chans = kzalloc(plat_data->dev_len * 2 *
2959 sizeof(struct d40_chan *),
2960 GFP_KERNEL);
2961 if (!base->lookup_log_chans)
2962 goto failure;
2963 }
Jonas Aaberg698e4732010-08-09 12:08:56 +00002964
Narayanan G7fb3e752011-11-17 17:26:41 +05302965 base->reg_val_backup_chan = kmalloc(base->num_phy_chans *
2966 sizeof(d40_backup_regs_chan),
Linus Walleij8d318a52010-03-30 15:33:42 +02002967 GFP_KERNEL);
Narayanan G7fb3e752011-11-17 17:26:41 +05302968 if (!base->reg_val_backup_chan)
2969 goto failure;
2970
2971 base->lcla_pool.alloc_map =
2972 kzalloc(num_phy_chans * sizeof(struct d40_desc *)
2973 * D40_LCLA_LINK_PER_EVENT_GRP, GFP_KERNEL);
Linus Walleij8d318a52010-03-30 15:33:42 +02002974 if (!base->lcla_pool.alloc_map)
2975 goto failure;
2976
Jonas Aabergc675b1b2010-06-20 21:25:08 +00002977 base->desc_slab = kmem_cache_create(D40_NAME, sizeof(struct d40_desc),
2978 0, SLAB_HWCACHE_ALIGN,
2979 NULL);
2980 if (base->desc_slab == NULL)
2981 goto failure;
2982
Linus Walleij8d318a52010-03-30 15:33:42 +02002983 return base;
2984
2985failure:
Rabin Vincentc6134c92010-10-06 08:20:36 +00002986 if (!IS_ERR(clk)) {
Linus Walleij8d318a52010-03-30 15:33:42 +02002987 clk_disable(clk);
2988 clk_put(clk);
2989 }
2990 if (virtbase)
2991 iounmap(virtbase);
2992 if (res)
2993 release_mem_region(res->start,
2994 resource_size(res));
2995 if (virtbase)
2996 iounmap(virtbase);
2997
2998 if (base) {
2999 kfree(base->lcla_pool.alloc_map);
3000 kfree(base->lookup_log_chans);
3001 kfree(base->lookup_phy_chans);
3002 kfree(base->phy_res);
3003 kfree(base);
3004 }
3005
3006 return NULL;
3007}
3008
3009static void __init d40_hw_init(struct d40_base *base)
3010{
3011
Narayanan G7fb3e752011-11-17 17:26:41 +05303012 static struct d40_reg_val dma_init_reg[] = {
Linus Walleij8d318a52010-03-30 15:33:42 +02003013 /* Clock every part of the DMA block from start */
Narayanan G7fb3e752011-11-17 17:26:41 +05303014 { .reg = D40_DREG_GCC, .val = D40_DREG_GCC_ENABLE_ALL},
Linus Walleij8d318a52010-03-30 15:33:42 +02003015
3016 /* Interrupts on all logical channels */
3017 { .reg = D40_DREG_LCMIS0, .val = 0xFFFFFFFF},
3018 { .reg = D40_DREG_LCMIS1, .val = 0xFFFFFFFF},
3019 { .reg = D40_DREG_LCMIS2, .val = 0xFFFFFFFF},
3020 { .reg = D40_DREG_LCMIS3, .val = 0xFFFFFFFF},
3021 { .reg = D40_DREG_LCICR0, .val = 0xFFFFFFFF},
3022 { .reg = D40_DREG_LCICR1, .val = 0xFFFFFFFF},
3023 { .reg = D40_DREG_LCICR2, .val = 0xFFFFFFFF},
3024 { .reg = D40_DREG_LCICR3, .val = 0xFFFFFFFF},
3025 { .reg = D40_DREG_LCTIS0, .val = 0xFFFFFFFF},
3026 { .reg = D40_DREG_LCTIS1, .val = 0xFFFFFFFF},
3027 { .reg = D40_DREG_LCTIS2, .val = 0xFFFFFFFF},
3028 { .reg = D40_DREG_LCTIS3, .val = 0xFFFFFFFF}
3029 };
3030 int i;
3031 u32 prmseo[2] = {0, 0};
3032 u32 activeo[2] = {0xFFFFFFFF, 0xFFFFFFFF};
3033 u32 pcmis = 0;
3034 u32 pcicr = 0;
3035
3036 for (i = 0; i < ARRAY_SIZE(dma_init_reg); i++)
3037 writel(dma_init_reg[i].val,
3038 base->virtbase + dma_init_reg[i].reg);
3039
3040 /* Configure all our dma channels to default settings */
3041 for (i = 0; i < base->num_phy_chans; i++) {
3042
3043 activeo[i % 2] = activeo[i % 2] << 2;
3044
3045 if (base->phy_res[base->num_phy_chans - i - 1].allocated_src
3046 == D40_ALLOC_PHY) {
3047 activeo[i % 2] |= 3;
3048 continue;
3049 }
3050
3051 /* Enable interrupt # */
3052 pcmis = (pcmis << 1) | 1;
3053
3054 /* Clear interrupt # */
3055 pcicr = (pcicr << 1) | 1;
3056
3057 /* Set channel to physical mode */
3058 prmseo[i % 2] = prmseo[i % 2] << 2;
3059 prmseo[i % 2] |= 1;
3060
3061 }
3062
3063 writel(prmseo[1], base->virtbase + D40_DREG_PRMSE);
3064 writel(prmseo[0], base->virtbase + D40_DREG_PRMSO);
3065 writel(activeo[1], base->virtbase + D40_DREG_ACTIVE);
3066 writel(activeo[0], base->virtbase + D40_DREG_ACTIVO);
3067
3068 /* Write which interrupt to enable */
3069 writel(pcmis, base->virtbase + D40_DREG_PCMIS);
3070
3071 /* Write which interrupt to clear */
3072 writel(pcicr, base->virtbase + D40_DREG_PCICR);
3073
3074}
3075
Linus Walleij508849a2010-06-20 21:26:07 +00003076static int __init d40_lcla_allocate(struct d40_base *base)
3077{
Rabin Vincent026cbc42011-01-25 11:18:14 +01003078 struct d40_lcla_pool *pool = &base->lcla_pool;
Linus Walleij508849a2010-06-20 21:26:07 +00003079 unsigned long *page_list;
3080 int i, j;
3081 int ret = 0;
3082
3083 /*
3084 * This is somewhat ugly. We need 8192 bytes that are 18 bit aligned,
3085 * To full fill this hardware requirement without wasting 256 kb
3086 * we allocate pages until we get an aligned one.
3087 */
3088 page_list = kmalloc(sizeof(unsigned long) * MAX_LCLA_ALLOC_ATTEMPTS,
3089 GFP_KERNEL);
3090
3091 if (!page_list) {
3092 ret = -ENOMEM;
3093 goto failure;
3094 }
3095
3096 /* Calculating how many pages that are required */
3097 base->lcla_pool.pages = SZ_1K * base->num_phy_chans / PAGE_SIZE;
3098
3099 for (i = 0; i < MAX_LCLA_ALLOC_ATTEMPTS; i++) {
3100 page_list[i] = __get_free_pages(GFP_KERNEL,
3101 base->lcla_pool.pages);
3102 if (!page_list[i]) {
3103
Rabin Vincent6db5a8b2011-01-25 11:18:09 +01003104 d40_err(base->dev, "Failed to allocate %d pages.\n",
3105 base->lcla_pool.pages);
Linus Walleij508849a2010-06-20 21:26:07 +00003106
3107 for (j = 0; j < i; j++)
3108 free_pages(page_list[j], base->lcla_pool.pages);
3109 goto failure;
3110 }
3111
3112 if ((virt_to_phys((void *)page_list[i]) &
3113 (LCLA_ALIGNMENT - 1)) == 0)
3114 break;
3115 }
3116
3117 for (j = 0; j < i; j++)
3118 free_pages(page_list[j], base->lcla_pool.pages);
3119
3120 if (i < MAX_LCLA_ALLOC_ATTEMPTS) {
3121 base->lcla_pool.base = (void *)page_list[i];
3122 } else {
Jonas Aaberg767a9672010-08-09 12:08:34 +00003123 /*
3124 * After many attempts and no succees with finding the correct
3125 * alignment, try with allocating a big buffer.
3126 */
Linus Walleij508849a2010-06-20 21:26:07 +00003127 dev_warn(base->dev,
3128 "[%s] Failed to get %d pages @ 18 bit align.\n",
3129 __func__, base->lcla_pool.pages);
3130 base->lcla_pool.base_unaligned = kmalloc(SZ_1K *
3131 base->num_phy_chans +
3132 LCLA_ALIGNMENT,
3133 GFP_KERNEL);
3134 if (!base->lcla_pool.base_unaligned) {
3135 ret = -ENOMEM;
3136 goto failure;
3137 }
3138
3139 base->lcla_pool.base = PTR_ALIGN(base->lcla_pool.base_unaligned,
3140 LCLA_ALIGNMENT);
3141 }
3142
Rabin Vincent026cbc42011-01-25 11:18:14 +01003143 pool->dma_addr = dma_map_single(base->dev, pool->base,
3144 SZ_1K * base->num_phy_chans,
3145 DMA_TO_DEVICE);
3146 if (dma_mapping_error(base->dev, pool->dma_addr)) {
3147 pool->dma_addr = 0;
3148 ret = -ENOMEM;
3149 goto failure;
3150 }
3151
Linus Walleij508849a2010-06-20 21:26:07 +00003152 writel(virt_to_phys(base->lcla_pool.base),
3153 base->virtbase + D40_DREG_LCLA);
3154failure:
3155 kfree(page_list);
3156 return ret;
3157}
3158
Linus Walleij8d318a52010-03-30 15:33:42 +02003159static int __init d40_probe(struct platform_device *pdev)
3160{
3161 int err;
3162 int ret = -ENOENT;
3163 struct d40_base *base;
3164 struct resource *res = NULL;
3165 int num_reserved_chans;
3166 u32 val;
3167
3168 base = d40_hw_detect_init(pdev);
3169
3170 if (!base)
3171 goto failure;
3172
3173 num_reserved_chans = d40_phy_res_init(base);
3174
3175 platform_set_drvdata(pdev, base);
3176
3177 spin_lock_init(&base->interrupt_lock);
3178 spin_lock_init(&base->execmd_lock);
3179
3180 /* Get IO for logical channel parameter address */
3181 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "lcpa");
3182 if (!res) {
3183 ret = -ENOENT;
Rabin Vincent6db5a8b2011-01-25 11:18:09 +01003184 d40_err(&pdev->dev, "No \"lcpa\" memory resource\n");
Linus Walleij8d318a52010-03-30 15:33:42 +02003185 goto failure;
3186 }
3187 base->lcpa_size = resource_size(res);
3188 base->phy_lcpa = res->start;
3189
3190 if (request_mem_region(res->start, resource_size(res),
3191 D40_NAME " I/O lcpa") == NULL) {
3192 ret = -EBUSY;
Rabin Vincent6db5a8b2011-01-25 11:18:09 +01003193 d40_err(&pdev->dev,
3194 "Failed to request LCPA region 0x%x-0x%x\n",
3195 res->start, res->end);
Linus Walleij8d318a52010-03-30 15:33:42 +02003196 goto failure;
3197 }
3198
3199 /* We make use of ESRAM memory for this. */
3200 val = readl(base->virtbase + D40_DREG_LCPA);
3201 if (res->start != val && val != 0) {
3202 dev_warn(&pdev->dev,
3203 "[%s] Mismatch LCPA dma 0x%x, def 0x%x\n",
3204 __func__, val, res->start);
3205 } else
3206 writel(res->start, base->virtbase + D40_DREG_LCPA);
3207
3208 base->lcpa_base = ioremap(res->start, resource_size(res));
3209 if (!base->lcpa_base) {
3210 ret = -ENOMEM;
Rabin Vincent6db5a8b2011-01-25 11:18:09 +01003211 d40_err(&pdev->dev, "Failed to ioremap LCPA region\n");
Linus Walleij8d318a52010-03-30 15:33:42 +02003212 goto failure;
3213 }
Narayanan G28c7a192011-11-22 13:56:55 +05303214 /* If lcla has to be located in ESRAM we don't need to allocate */
3215 if (base->plat_data->use_esram_lcla) {
3216 res = platform_get_resource_byname(pdev, IORESOURCE_MEM,
3217 "lcla_esram");
3218 if (!res) {
3219 ret = -ENOENT;
3220 d40_err(&pdev->dev,
3221 "No \"lcla_esram\" memory resource\n");
3222 goto failure;
3223 }
3224 base->lcla_pool.base = ioremap(res->start,
3225 resource_size(res));
3226 if (!base->lcla_pool.base) {
3227 ret = -ENOMEM;
3228 d40_err(&pdev->dev, "Failed to ioremap LCLA region\n");
3229 goto failure;
3230 }
3231 writel(res->start, base->virtbase + D40_DREG_LCLA);
Linus Walleij508849a2010-06-20 21:26:07 +00003232
Narayanan G28c7a192011-11-22 13:56:55 +05303233 } else {
3234 ret = d40_lcla_allocate(base);
3235 if (ret) {
3236 d40_err(&pdev->dev, "Failed to allocate LCLA area\n");
3237 goto failure;
3238 }
Linus Walleij8d318a52010-03-30 15:33:42 +02003239 }
3240
Linus Walleij8d318a52010-03-30 15:33:42 +02003241 spin_lock_init(&base->lcla_pool.lock);
3242
Linus Walleij8d318a52010-03-30 15:33:42 +02003243 base->irq = platform_get_irq(pdev, 0);
3244
3245 ret = request_irq(base->irq, d40_handle_interrupt, 0, D40_NAME, base);
Linus Walleij8d318a52010-03-30 15:33:42 +02003246 if (ret) {
Rabin Vincent6db5a8b2011-01-25 11:18:09 +01003247 d40_err(&pdev->dev, "No IRQ defined\n");
Linus Walleij8d318a52010-03-30 15:33:42 +02003248 goto failure;
3249 }
3250
Narayanan G7fb3e752011-11-17 17:26:41 +05303251 pm_runtime_irq_safe(base->dev);
3252 pm_runtime_set_autosuspend_delay(base->dev, DMA40_AUTOSUSPEND_DELAY);
3253 pm_runtime_use_autosuspend(base->dev);
3254 pm_runtime_enable(base->dev);
3255 pm_runtime_resume(base->dev);
Narayanan G28c7a192011-11-22 13:56:55 +05303256
3257 if (base->plat_data->use_esram_lcla) {
3258
3259 base->lcpa_regulator = regulator_get(base->dev, "lcla_esram");
3260 if (IS_ERR(base->lcpa_regulator)) {
3261 d40_err(&pdev->dev, "Failed to get lcpa_regulator\n");
3262 base->lcpa_regulator = NULL;
3263 goto failure;
3264 }
3265
3266 ret = regulator_enable(base->lcpa_regulator);
3267 if (ret) {
3268 d40_err(&pdev->dev,
3269 "Failed to enable lcpa_regulator\n");
3270 regulator_put(base->lcpa_regulator);
3271 base->lcpa_regulator = NULL;
3272 goto failure;
3273 }
3274 }
3275
Narayanan G7fb3e752011-11-17 17:26:41 +05303276 base->initialized = true;
Linus Walleij8d318a52010-03-30 15:33:42 +02003277 err = d40_dmaengine_init(base, num_reserved_chans);
3278 if (err)
3279 goto failure;
3280
3281 d40_hw_init(base);
3282
3283 dev_info(base->dev, "initialized\n");
3284 return 0;
3285
3286failure:
3287 if (base) {
Jonas Aabergc675b1b2010-06-20 21:25:08 +00003288 if (base->desc_slab)
3289 kmem_cache_destroy(base->desc_slab);
Linus Walleij8d318a52010-03-30 15:33:42 +02003290 if (base->virtbase)
3291 iounmap(base->virtbase);
Rabin Vincent026cbc42011-01-25 11:18:14 +01003292
Narayanan G28c7a192011-11-22 13:56:55 +05303293 if (base->lcla_pool.base && base->plat_data->use_esram_lcla) {
3294 iounmap(base->lcla_pool.base);
3295 base->lcla_pool.base = NULL;
3296 }
3297
Rabin Vincent026cbc42011-01-25 11:18:14 +01003298 if (base->lcla_pool.dma_addr)
3299 dma_unmap_single(base->dev, base->lcla_pool.dma_addr,
3300 SZ_1K * base->num_phy_chans,
3301 DMA_TO_DEVICE);
3302
Linus Walleij508849a2010-06-20 21:26:07 +00003303 if (!base->lcla_pool.base_unaligned && base->lcla_pool.base)
3304 free_pages((unsigned long)base->lcla_pool.base,
3305 base->lcla_pool.pages);
Jonas Aaberg767a9672010-08-09 12:08:34 +00003306
3307 kfree(base->lcla_pool.base_unaligned);
3308
Linus Walleij8d318a52010-03-30 15:33:42 +02003309 if (base->phy_lcpa)
3310 release_mem_region(base->phy_lcpa,
3311 base->lcpa_size);
3312 if (base->phy_start)
3313 release_mem_region(base->phy_start,
3314 base->phy_size);
3315 if (base->clk) {
3316 clk_disable(base->clk);
3317 clk_put(base->clk);
3318 }
3319
Narayanan G28c7a192011-11-22 13:56:55 +05303320 if (base->lcpa_regulator) {
3321 regulator_disable(base->lcpa_regulator);
3322 regulator_put(base->lcpa_regulator);
3323 }
3324
Linus Walleij8d318a52010-03-30 15:33:42 +02003325 kfree(base->lcla_pool.alloc_map);
3326 kfree(base->lookup_log_chans);
3327 kfree(base->lookup_phy_chans);
3328 kfree(base->phy_res);
3329 kfree(base);
3330 }
3331
Rabin Vincent6db5a8b2011-01-25 11:18:09 +01003332 d40_err(&pdev->dev, "probe failed\n");
Linus Walleij8d318a52010-03-30 15:33:42 +02003333 return ret;
3334}
3335
3336static struct platform_driver d40_driver = {
3337 .driver = {
3338 .owner = THIS_MODULE,
3339 .name = D40_NAME,
Narayanan G7fb3e752011-11-17 17:26:41 +05303340 .pm = DMA40_PM_OPS,
Linus Walleij8d318a52010-03-30 15:33:42 +02003341 },
3342};
3343
Rabin Vincentcb9ab2d2011-01-25 11:18:04 +01003344static int __init stedma40_init(void)
Linus Walleij8d318a52010-03-30 15:33:42 +02003345{
3346 return platform_driver_probe(&d40_driver, d40_probe);
3347}
Linus Walleija0eb2212011-05-18 14:18:57 +02003348subsys_initcall(stedma40_init);