Mathieu Poirier | 799656d | 2014-11-12 16:36:59 -0700 | [diff] [blame] | 1 | * CoreSight Components: |
| 2 | |
| 3 | CoreSight components are compliant with the ARM CoreSight architecture |
Sundara Vinayagam | 2b9efc4 | 2018-04-07 21:51:28 +0530 | [diff] [blame] | 4 | specification and can be connected in various topologies to suit a particular |
| 5 | SoCs tracing needs. These trace components can generally be classified as |
| 6 | sinks, links and sources. Trace data produced by one or more sources flows |
| 7 | through the intermediate links connecting the source to the currently selected |
| 8 | sink. Each CoreSight component device should use these properties to describe |
| 9 | its hardware characteristcs. |
Mathieu Poirier | 799656d | 2014-11-12 16:36:59 -0700 | [diff] [blame] | 10 | |
| 11 | * Required properties for all components *except* non-configurable replicators: |
| 12 | |
| 13 | * compatible: These have to be supplemented with "arm,primecell" as |
| 14 | drivers are using the AMBA bus interface. Possible values include: |
mathieu.poirier@linaro.org | 4b681ef | 2016-06-22 09:01:03 -0600 | [diff] [blame] | 15 | - Embedded Trace Buffer (version 1.0): |
| 16 | "arm,coresight-etb10", "arm,primecell"; |
| 17 | |
| 18 | - Trace Port Interface Unit: |
| 19 | "arm,coresight-tpiu", "arm,primecell"; |
| 20 | |
| 21 | - Trace Memory Controller, used for Embedded Trace Buffer(ETB), |
| 22 | Embedded Trace FIFO(ETF) and Embedded Trace Router(ETR) |
| 23 | configuration. The configuration mode (ETB, ETF, ETR) is |
| 24 | discovered at boot time when the device is probed. |
| 25 | "arm,coresight-tmc", "arm,primecell"; |
| 26 | |
| 27 | - Trace Funnel: |
| 28 | "arm,coresight-funnel", "arm,primecell"; |
| 29 | |
| 30 | - Embedded Trace Macrocell (version 3.x) and |
| 31 | Program Flow Trace Macrocell: |
| 32 | "arm,coresight-etm3x", "arm,primecell"; |
| 33 | |
| 34 | - Embedded Trace Macrocell (version 4.x): |
| 35 | "arm,coresight-etm4x", "arm,primecell"; |
| 36 | |
| 37 | - Qualcomm Configurable Replicator (version 1.x): |
| 38 | "qcom,coresight-replicator1x", "arm,primecell"; |
| 39 | |
| 40 | - System Trace Macrocell: |
| 41 | "arm,coresight-stm", "arm,primecell"; [1] |
Rama Aparna Mallavarapu | a2a8e3e | 2017-08-16 20:56:00 -0700 | [diff] [blame] | 42 | - Trigger Generation Unit: |
| 43 | "arm,primecell"; |
Mathieu Poirier | 799656d | 2014-11-12 16:36:59 -0700 | [diff] [blame] | 44 | |
| 45 | * reg: physical base address and length of the register |
| 46 | set(s) of the component. |
| 47 | |
Linus Walleij | 70dd9d2 | 2015-05-19 10:55:19 -0600 | [diff] [blame] | 48 | * clocks: the clocks associated to this component. |
Mathieu Poirier | 799656d | 2014-11-12 16:36:59 -0700 | [diff] [blame] | 49 | |
Linus Walleij | 70dd9d2 | 2015-05-19 10:55:19 -0600 | [diff] [blame] | 50 | * clock-names: the name of the clocks referenced by the code. |
| 51 | Since we are using the AMBA framework, the name of the clock |
| 52 | providing the interconnect should be "apb_pclk", and some |
| 53 | coresight blocks also have an additional clock "atclk", which |
| 54 | clocks the core of that coresight component. The latter clock |
| 55 | is optional. |
Mathieu Poirier | 799656d | 2014-11-12 16:36:59 -0700 | [diff] [blame] | 56 | |
| 57 | * port or ports: The representation of the component's port |
| 58 | layout using the generic DT graph presentation found in |
| 59 | "bindings/graph.txt". |
| 60 | |
Satyajit Desai | 7bd8804 | 2016-09-15 12:01:50 -0700 | [diff] [blame] | 61 | * coresight-name: unique descriptive name of the component. |
| 62 | |
Mathieu Poirier | 9eb9331 | 2016-05-03 11:33:39 -0600 | [diff] [blame] | 63 | * Additional required properties for System Trace Macrocells (STM): |
| 64 | * reg: along with the physical base address and length of the register |
| 65 | set as described above, another entry is required to describe the |
| 66 | mapping of the extended stimulus port area. |
| 67 | |
| 68 | * reg-names: the only acceptable values are "stm-base" and |
| 69 | "stm-stimulus-base", each corresponding to the areas defined in "reg". |
| 70 | |
Mathieu Poirier | 799656d | 2014-11-12 16:36:59 -0700 | [diff] [blame] | 71 | * Required properties for devices that don't show up on the AMBA bus, such as |
| 72 | non-configurable replicators: |
| 73 | |
| 74 | * compatible: Currently supported value is (note the absence of the |
| 75 | AMBA markee): |
| 76 | - "arm,coresight-replicator" |
Satyajit Desai | 7bd8804 | 2016-09-15 12:01:50 -0700 | [diff] [blame] | 77 | - "qcom,coresight-csr" |
Satyajit Desai | 7bd8804 | 2016-09-15 12:01:50 -0700 | [diff] [blame] | 78 | - "qcom,coresight-remote-etm" |
| 79 | - "qcom,coresight-hwevent" |
| 80 | - "qcom,coresight-dummy" |
Mukesh Ojha | 4350ecb | 2017-11-30 19:24:55 +0530 | [diff] [blame] | 81 | - "qcom,coresight-dbgui" |
Mathieu Poirier | 799656d | 2014-11-12 16:36:59 -0700 | [diff] [blame] | 82 | |
Mathieu Poirier | 799656d | 2014-11-12 16:36:59 -0700 | [diff] [blame] | 83 | * port or ports: same as above. |
| 84 | |
Satyajit Desai | 7bd8804 | 2016-09-15 12:01:50 -0700 | [diff] [blame] | 85 | * coresight-name: unique descriptive name of the component. |
| 86 | |
Satyajit Desai | 80e47d4 | 2017-03-06 18:23:52 -0800 | [diff] [blame] | 87 | * Additional required property for coresight-dummy devices: |
| 88 | * qcom,dummy-source: Configure the device as source. |
| 89 | |
Satyajit Desai | f4c5ee9 | 2017-01-04 15:31:06 -0800 | [diff] [blame] | 90 | * qcom,dummy-sink: Configure the device as sink. |
| 91 | |
Rama Aparna Mallavarapu | a2a8e3e | 2017-08-16 20:56:00 -0700 | [diff] [blame] | 92 | * Additional required property for coresight-tgu devices: |
| 93 | * tgu-steps: must be present. Indicates number of steps supported |
| 94 | by the TGU. |
| 95 | * tgu-conditions: must be present. Indicates the number of conditions |
| 96 | supported by the TGU. |
| 97 | * tgu-regs: must be present. Indicates the number of regs supported |
| 98 | by the TGU. |
| 99 | * tgu-timer-counters: must be present. Indicates the number of timers and |
| 100 | counters available in the TGU to do a comparision. |
| 101 | |
Satyajit Desai | 7bd8804 | 2016-09-15 12:01:50 -0700 | [diff] [blame] | 102 | * Optional properties for all components: |
| 103 | * reg-names: names corresponding to each reg property value. |
| 104 | |
Mathieu Poirier | 799656d | 2014-11-12 16:36:59 -0700 | [diff] [blame] | 105 | * Optional properties for ETM/PTMs: |
| 106 | |
| 107 | * arm,cp14: must be present if the system accesses ETM/PTM management |
| 108 | registers via co-processor 14. |
| 109 | |
| 110 | * cpu: the cpu phandle this ETM/PTM is affined to. When omitted the |
| 111 | source is considered to belong to CPU0. |
| 112 | |
Mao Jinlong | 4c6d848 | 2018-06-05 20:58:13 +0800 | [diff] [blame] | 113 | * qcom,tupwr-disable: For ETM, don't keep trace unit powered across power |
| 114 | collapse. |
| 115 | |
Mathieu Poirier | 799656d | 2014-11-12 16:36:59 -0700 | [diff] [blame] | 116 | * Optional property for TMC: |
| 117 | |
| 118 | * arm,buffer-size: size of contiguous buffer space for TMC ETR |
| 119 | (embedded trace router) |
| 120 | |
Satyajit Desai | 7bd8804 | 2016-09-15 12:01:50 -0700 | [diff] [blame] | 121 | * arm,default-sink: represents the default compile time CoreSight sink |
| 122 | |
| 123 | * coresight-ctis: represents flush and reset CTIs for TMC buffer |
| 124 | |
| 125 | * qcom,force-reg-dump: enables TMC reg dump support |
| 126 | |
| 127 | * arm,sg-enable : indicates whether scatter gather feature is enabled |
| 128 | by default for TMC ETR configuration. |
| 129 | |
| 130 | * Required property for TPDAs: |
| 131 | |
| 132 | * qcom,tpda-atid: must be present. Specifies the ATID for TPDA. |
| 133 | |
| 134 | * Optional properties for TPDAs: |
| 135 | |
| 136 | * qcom,bc-elem-size: specifies the BC element size supported by each |
| 137 | monitor connected to the aggregator on each port. Should be specified |
| 138 | in pairs (port, bc element size). |
| 139 | |
| 140 | * qcom,tc-elem-size: specifies the TC element size supported by each |
| 141 | monitor connected to the aggregator on each port. Should be specified |
| 142 | in pairs (port, tc element size). |
| 143 | |
| 144 | * qcom,dsb-elem-size: specifies the DSB element size supported by each |
| 145 | monitor connected to the aggregator on each port. Should be specified |
| 146 | in pairs (port, dsb element size). |
| 147 | |
| 148 | * qcom,cmb-elem-size: specifies the CMB element size supported by each |
| 149 | monitor connected to the aggregator on each port. Should be specified |
| 150 | in pairs (port, cmb element size). |
| 151 | |
| 152 | * Optional properties for TPDM: |
| 153 | |
| 154 | * qcom,clk-enable: specifies whether additional clock bit needs to be |
| 155 | set for M4M TPDM. |
| 156 | |
| 157 | * qcom,msr-fix-req: boolean, indicating if MSRs need to be programmed |
| 158 | after enabling the subunit. |
| 159 | |
Satyajit Desai | 267d857 | 2017-10-26 15:21:07 -0700 | [diff] [blame] | 160 | * qcom,dump-enable: boolean, specifies to dump MCMB data. |
Satyajit Desai | e450813 | 2017-04-05 17:15:22 -0700 | [diff] [blame] | 161 | * Optional properties for CTI: |
| 162 | |
| 163 | * qcom,cti-gpio-trigin: cti trigger input driven by gpio. |
| 164 | |
| 165 | * qcom,cti-gpio-trigout: cti trigger output sent to gpio. |
| 166 | |
| 167 | * pinctrl-names: names corresponding to the numbered pinctrl. The |
| 168 | allowed names are subset of the following: cti-trigin-pinctrl, |
| 169 | cti-trigout-pctrl. |
| 170 | |
| 171 | * pinctrl-<n>: list of pinctrl phandles for the different pinctrl |
| 172 | states. Refer to |
| 173 | "Documentation/devicetree/bindings/pinctrl/pinctrl-bindings.txt" |
| 174 | |
Satyajit Desai | 7bd8804 | 2016-09-15 12:01:50 -0700 | [diff] [blame] | 175 | * Required property for Remote ETMs: |
| 176 | |
| 177 | * qcom,inst-id: must be present. QMI instance id for remote ETMs. |
Mathieu Poirier | 799656d | 2014-11-12 16:36:59 -0700 | [diff] [blame] | 178 | |
Satyajit Desai | caa081f | 2017-06-15 14:54:27 -0700 | [diff] [blame] | 179 | * Optional properties for funnels: |
| 180 | |
| 181 | * qcom,duplicate-funnel: boolean, indicates its a duplicate of an |
| 182 | existing funnel. Funnel devices are now capable of supporting |
| 183 | multiple-input and multiple-output configuration with in built |
| 184 | hardware filtering for TPDM devices. Each set of input-output |
| 185 | combination is treated as independent funnel device. |
| 186 | funnel-base-dummy and funnel-base-real reg-names must be specified |
| 187 | when this property is enabled. |
| 188 | |
| 189 | * reg-names: funnel-base-dummy: dummy register space used by a |
| 190 | duplicate funnel. Should be a valid register address space that |
| 191 | no other device is using. |
| 192 | |
| 193 | * reg-names: funnel-base-real: actual register space for the |
| 194 | duplicate funnel. |
| 195 | |
Mulu He | 1a59c48 | 2017-12-26 19:32:58 +0800 | [diff] [blame] | 196 | * Optional properties for CSRs: |
| 197 | |
| 198 | * qcom,usb-bam-support: boolean, indicates CSR has the ability to operate on |
| 199 | usb bam, include enable,disable and flush. |
| 200 | |
| 201 | * qcom,hwctrl-set-support: boolean, indicates CSR has the ability to operate on |
| 202 | to "HWCTRL" register. |
| 203 | |
| 204 | * qcom,set-byte-cntr-support:boolean, indicates CSR has the ability to operate on |
| 205 | to "BYTECNT" register. |
| 206 | |
| 207 | * qcom,timestamp-support:boolean, indicates CSR support sys interface to read |
| 208 | timestamp value. |
| 209 | |
Mathieu Poirier | 799656d | 2014-11-12 16:36:59 -0700 | [diff] [blame] | 210 | Example: |
| 211 | |
| 212 | 1. Sinks |
| 213 | etb@20010000 { |
| 214 | compatible = "arm,coresight-etb10", "arm,primecell"; |
| 215 | reg = <0 0x20010000 0 0x1000>; |
| 216 | |
Mathieu Poirier | 799656d | 2014-11-12 16:36:59 -0700 | [diff] [blame] | 217 | clocks = <&oscclk6a>; |
| 218 | clock-names = "apb_pclk"; |
| 219 | port { |
| 220 | etb_in_port: endpoint@0 { |
| 221 | slave-mode; |
| 222 | remote-endpoint = <&replicator_out_port0>; |
| 223 | }; |
| 224 | }; |
| 225 | }; |
| 226 | |
| 227 | tpiu@20030000 { |
| 228 | compatible = "arm,coresight-tpiu", "arm,primecell"; |
| 229 | reg = <0 0x20030000 0 0x1000>; |
| 230 | |
| 231 | clocks = <&oscclk6a>; |
| 232 | clock-names = "apb_pclk"; |
| 233 | port { |
| 234 | tpiu_in_port: endpoint@0 { |
| 235 | slave-mode; |
| 236 | remote-endpoint = <&replicator_out_port1>; |
| 237 | }; |
| 238 | }; |
| 239 | }; |
| 240 | |
| 241 | 2. Links |
| 242 | replicator { |
| 243 | /* non-configurable replicators don't show up on the |
| 244 | * AMBA bus. As such no need to add "arm,primecell". |
| 245 | */ |
| 246 | compatible = "arm,coresight-replicator"; |
Mathieu Poirier | 799656d | 2014-11-12 16:36:59 -0700 | [diff] [blame] | 247 | |
| 248 | ports { |
| 249 | #address-cells = <1>; |
| 250 | #size-cells = <0>; |
| 251 | |
| 252 | /* replicator output ports */ |
| 253 | port@0 { |
| 254 | reg = <0>; |
| 255 | replicator_out_port0: endpoint { |
| 256 | remote-endpoint = <&etb_in_port>; |
| 257 | }; |
| 258 | }; |
| 259 | |
| 260 | port@1 { |
| 261 | reg = <1>; |
| 262 | replicator_out_port1: endpoint { |
| 263 | remote-endpoint = <&tpiu_in_port>; |
| 264 | }; |
| 265 | }; |
| 266 | |
| 267 | /* replicator input port */ |
| 268 | port@2 { |
| 269 | reg = <0>; |
| 270 | replicator_in_port0: endpoint { |
| 271 | slave-mode; |
| 272 | remote-endpoint = <&funnel_out_port0>; |
| 273 | }; |
| 274 | }; |
| 275 | }; |
| 276 | }; |
| 277 | |
| 278 | funnel@20040000 { |
| 279 | compatible = "arm,coresight-funnel", "arm,primecell"; |
| 280 | reg = <0 0x20040000 0 0x1000>; |
| 281 | |
| 282 | clocks = <&oscclk6a>; |
| 283 | clock-names = "apb_pclk"; |
| 284 | ports { |
| 285 | #address-cells = <1>; |
| 286 | #size-cells = <0>; |
| 287 | |
| 288 | /* funnel output port */ |
| 289 | port@0 { |
| 290 | reg = <0>; |
| 291 | funnel_out_port0: endpoint { |
| 292 | remote-endpoint = |
| 293 | <&replicator_in_port0>; |
| 294 | }; |
| 295 | }; |
| 296 | |
| 297 | /* funnel input ports */ |
| 298 | port@1 { |
| 299 | reg = <0>; |
| 300 | funnel_in_port0: endpoint { |
| 301 | slave-mode; |
| 302 | remote-endpoint = <&ptm0_out_port>; |
| 303 | }; |
| 304 | }; |
| 305 | |
| 306 | port@2 { |
| 307 | reg = <1>; |
| 308 | funnel_in_port1: endpoint { |
| 309 | slave-mode; |
| 310 | remote-endpoint = <&ptm1_out_port>; |
| 311 | }; |
| 312 | }; |
| 313 | |
| 314 | port@3 { |
| 315 | reg = <2>; |
| 316 | funnel_in_port2: endpoint { |
| 317 | slave-mode; |
| 318 | remote-endpoint = <&etm0_out_port>; |
| 319 | }; |
| 320 | }; |
| 321 | |
| 322 | }; |
| 323 | }; |
| 324 | |
Satyajit Desai | 7bd8804 | 2016-09-15 12:01:50 -0700 | [diff] [blame] | 325 | tpda_mss: tpda@7043000 { |
Satyajit Desai | 045b56b | 2017-04-18 17:47:51 -0700 | [diff] [blame] | 326 | compatible = "qcom,coresight-tpda", "arm,primecell"; |
Satyajit Desai | 7bd8804 | 2016-09-15 12:01:50 -0700 | [diff] [blame] | 327 | reg = <0x7043000 0x1000>; |
| 328 | reg-names = "tpda-base"; |
| 329 | |
| 330 | coresight-name = "coresight-tpda-mss"; |
| 331 | |
| 332 | qcom,tpda-atid = <67>; |
| 333 | qcom,dsb-elem-size = <0 32>; |
| 334 | qcom,cmb-elem-size = <0 32>; |
| 335 | |
Satyajit Desai | 045b56b | 2017-04-18 17:47:51 -0700 | [diff] [blame] | 336 | clocks = <&clock_aop clk_qdss_clk>; |
| 337 | clock-names = "apb_pclk"; |
Satyajit Desai | 7bd8804 | 2016-09-15 12:01:50 -0700 | [diff] [blame] | 338 | |
| 339 | ports { |
| 340 | #address-cells = <1>; |
| 341 | #size-cells = <0>; |
| 342 | port@0 { |
| 343 | reg = <0>; |
| 344 | tpda_mss_out_funnel_in1: endpoint { |
| 345 | remote-endpoint = |
| 346 | <&funnel_in1_in_tpda_mss>; |
| 347 | }; |
| 348 | }; |
| 349 | port@1 { |
| 350 | reg = <0>; |
| 351 | tpda_mss_in_tpdm_mss: endpoint { |
| 352 | slave-mode; |
| 353 | remote-endpoint = |
| 354 | <&tpdm_mss_out_tpda_mss>; |
| 355 | }; |
| 356 | }; |
| 357 | }; |
| 358 | }; |
| 359 | |
Mathieu Poirier | 799656d | 2014-11-12 16:36:59 -0700 | [diff] [blame] | 360 | 3. Sources |
| 361 | ptm@2201c000 { |
| 362 | compatible = "arm,coresight-etm3x", "arm,primecell"; |
| 363 | reg = <0 0x2201c000 0 0x1000>; |
| 364 | |
| 365 | cpu = <&cpu0>; |
| 366 | clocks = <&oscclk6a>; |
| 367 | clock-names = "apb_pclk"; |
| 368 | port { |
| 369 | ptm0_out_port: endpoint { |
| 370 | remote-endpoint = <&funnel_in_port0>; |
| 371 | }; |
| 372 | }; |
| 373 | }; |
| 374 | |
| 375 | ptm@2201d000 { |
| 376 | compatible = "arm,coresight-etm3x", "arm,primecell"; |
| 377 | reg = <0 0x2201d000 0 0x1000>; |
| 378 | |
| 379 | cpu = <&cpu1>; |
| 380 | clocks = <&oscclk6a>; |
| 381 | clock-names = "apb_pclk"; |
| 382 | port { |
| 383 | ptm1_out_port: endpoint { |
| 384 | remote-endpoint = <&funnel_in_port1>; |
| 385 | }; |
| 386 | }; |
| 387 | }; |
Mathieu Poirier | 9eb9331 | 2016-05-03 11:33:39 -0600 | [diff] [blame] | 388 | |
| 389 | 4. STM |
| 390 | stm@20100000 { |
| 391 | compatible = "arm,coresight-stm", "arm,primecell"; |
| 392 | reg = <0 0x20100000 0 0x1000>, |
| 393 | <0 0x28000000 0 0x180000>; |
| 394 | reg-names = "stm-base", "stm-stimulus-base"; |
| 395 | |
| 396 | clocks = <&soc_smc50mhz>; |
| 397 | clock-names = "apb_pclk"; |
| 398 | port { |
| 399 | stm_out_port: endpoint { |
| 400 | remote-endpoint = <&main_funnel_in_port2>; |
| 401 | }; |
| 402 | }; |
| 403 | }; |
| 404 | |
Satyajit Desai | 7bd8804 | 2016-09-15 12:01:50 -0700 | [diff] [blame] | 405 | tpdm_mss: tpdm@7042000 { |
Satyajit Desai | 045b56b | 2017-04-18 17:47:51 -0700 | [diff] [blame] | 406 | compatible = "qcom,coresight-tpdm", "arm,primecell"; |
Satyajit Desai | 7bd8804 | 2016-09-15 12:01:50 -0700 | [diff] [blame] | 407 | reg = <0x7042000 0x1000>; |
| 408 | reg-names = "tpdm-base"; |
| 409 | |
| 410 | coresight-name = "coresight-tpdm-mss"; |
| 411 | |
Satyajit Desai | 045b56b | 2017-04-18 17:47:51 -0700 | [diff] [blame] | 412 | clocks = <&clock_aop qdss_clk>; |
| 413 | clock-names = "apb_pclk"; |
Satyajit Desai | 7bd8804 | 2016-09-15 12:01:50 -0700 | [diff] [blame] | 414 | |
| 415 | port{ |
| 416 | tpdm_mss_out_tpda_mss: endpoint { |
| 417 | remote-endpoint = <&tpda_mss_in_tpdm_mss>; |
| 418 | }; |
| 419 | }; |
| 420 | }; |
| 421 | |
Rama Aparna Mallavarapu | a2a8e3e | 2017-08-16 20:56:00 -0700 | [diff] [blame] | 422 | 5. CTIs |
Satyajit Desai | 7bd8804 | 2016-09-15 12:01:50 -0700 | [diff] [blame] | 423 | cti0: cti@6010000 { |
Satyajit Desai | 045b56b | 2017-04-18 17:47:51 -0700 | [diff] [blame] | 424 | compatible = "arm,coresight-cti", "arm,primecell"; |
Satyajit Desai | 7bd8804 | 2016-09-15 12:01:50 -0700 | [diff] [blame] | 425 | reg = <0x6010000 0x1000>; |
| 426 | reg-names = "cti-base"; |
| 427 | |
| 428 | coresight-name = "coresight-cti0"; |
| 429 | |
Satyajit Desai | 045b56b | 2017-04-18 17:47:51 -0700 | [diff] [blame] | 430 | clocks = <&clock_aop qdss_clk>; |
| 431 | clock-names = "apb_pclk"; |
Satyajit Desai | 7bd8804 | 2016-09-15 12:01:50 -0700 | [diff] [blame] | 432 | }; |
| 433 | |
Rama Aparna Mallavarapu | a2a8e3e | 2017-08-16 20:56:00 -0700 | [diff] [blame] | 434 | 6. TGUs |
| 435 | ipcb_tgu: tgu@6b0c000 { |
| 436 | compatible = "arm,primecell"; |
| 437 | arm,primecell-periphid = <0x0003b999>; |
| 438 | reg = <0x06B0C000 0x1000>; |
| 439 | reg-names = "tgu-base"; |
| 440 | tgu-steps = <3>; |
| 441 | tgu-conditions = <4>; |
| 442 | tgu-regs = <4>; |
| 443 | tgu-timer-counters = <8>; |
| 444 | |
| 445 | coresight-name = "coresight-tgu-ipcb"; |
| 446 | |
| 447 | clocks = <&clock_aop QDSS_CLK>; |
| 448 | clock-names = "apb_pclk"; |
| 449 | }; |
Mathieu Poirier | 9eb9331 | 2016-05-03 11:33:39 -0600 | [diff] [blame] | 450 | [1]. There is currently two version of STM: STM32 and STM500. Both |
| 451 | have the same HW interface and as such don't need an explicit binding name. |