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Magnus Damm119f5e42013-03-13 20:32:13 +09001/*
2 * Renesas R-Car GPIO Support
3 *
Hisashi Nakamura1fd2b492014-11-07 20:54:08 +09004 * Copyright (C) 2014 Renesas Electronics Corporation
Magnus Damm119f5e42013-03-13 20:32:13 +09005 * Copyright (C) 2013 Magnus Damm
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; either version 2 of the License
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 */
16
Geert Uytterhoevenab82fa72015-03-18 19:41:09 +010017#include <linux/clk.h>
Magnus Damm119f5e42013-03-13 20:32:13 +090018#include <linux/err.h>
19#include <linux/gpio.h>
20#include <linux/init.h>
21#include <linux/interrupt.h>
22#include <linux/io.h>
23#include <linux/ioport.h>
24#include <linux/irq.h>
Magnus Damm119f5e42013-03-13 20:32:13 +090025#include <linux/module.h>
Sachin Kamatbd0bf462013-10-16 15:35:02 +053026#include <linux/of.h>
Laurent Pinchartdc3465a2013-03-10 03:27:00 +010027#include <linux/pinctrl/consumer.h>
Magnus Damm119f5e42013-03-13 20:32:13 +090028#include <linux/platform_data/gpio-rcar.h>
29#include <linux/platform_device.h>
Geert Uytterhoevendf0c6c82014-04-14 20:33:13 +020030#include <linux/pm_runtime.h>
Magnus Damm119f5e42013-03-13 20:32:13 +090031#include <linux/spinlock.h>
32#include <linux/slab.h>
33
34struct gpio_rcar_priv {
35 void __iomem *base;
36 spinlock_t lock;
37 struct gpio_rcar_config config;
38 struct platform_device *pdev;
39 struct gpio_chip gpio_chip;
40 struct irq_chip irq_chip;
Geert Uytterhoevenab82fa72015-03-18 19:41:09 +010041 unsigned int irq_parent;
42 struct clk *clk;
Magnus Damm119f5e42013-03-13 20:32:13 +090043};
44
Geert Uytterhoeven3dc1e682015-03-18 19:41:08 +010045#define IOINTSEL 0x00 /* General IO/Interrupt Switching Register */
46#define INOUTSEL 0x04 /* General Input/Output Switching Register */
47#define OUTDT 0x08 /* General Output Register */
48#define INDT 0x0c /* General Input Register */
49#define INTDT 0x10 /* Interrupt Display Register */
50#define INTCLR 0x14 /* Interrupt Clear Register */
51#define INTMSK 0x18 /* Interrupt Mask Register */
52#define MSKCLR 0x1c /* Interrupt Mask Clear Register */
53#define POSNEG 0x20 /* Positive/Negative Logic Select Register */
54#define EDGLEVEL 0x24 /* Edge/level Select Register */
55#define FILONOFF 0x28 /* Chattering Prevention On/Off Register */
56#define BOTHEDGE 0x4c /* One Edge/Both Edge Select Register */
Magnus Damm119f5e42013-03-13 20:32:13 +090057
Laurent Pinchart159f8a02013-05-21 13:40:06 +020058#define RCAR_MAX_GPIO_PER_BANK 32
59
Magnus Damm119f5e42013-03-13 20:32:13 +090060static inline u32 gpio_rcar_read(struct gpio_rcar_priv *p, int offs)
61{
62 return ioread32(p->base + offs);
63}
64
65static inline void gpio_rcar_write(struct gpio_rcar_priv *p, int offs,
66 u32 value)
67{
68 iowrite32(value, p->base + offs);
69}
70
71static void gpio_rcar_modify_bit(struct gpio_rcar_priv *p, int offs,
72 int bit, bool value)
73{
74 u32 tmp = gpio_rcar_read(p, offs);
75
76 if (value)
77 tmp |= BIT(bit);
78 else
79 tmp &= ~BIT(bit);
80
81 gpio_rcar_write(p, offs, tmp);
82}
83
84static void gpio_rcar_irq_disable(struct irq_data *d)
85{
Geert Uytterhoevenc7f3c5d2015-01-12 11:07:59 +010086 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
87 struct gpio_rcar_priv *p = container_of(gc, struct gpio_rcar_priv,
88 gpio_chip);
Magnus Damm119f5e42013-03-13 20:32:13 +090089
90 gpio_rcar_write(p, INTMSK, ~BIT(irqd_to_hwirq(d)));
91}
92
93static void gpio_rcar_irq_enable(struct irq_data *d)
94{
Geert Uytterhoevenc7f3c5d2015-01-12 11:07:59 +010095 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
96 struct gpio_rcar_priv *p = container_of(gc, struct gpio_rcar_priv,
97 gpio_chip);
Magnus Damm119f5e42013-03-13 20:32:13 +090098
99 gpio_rcar_write(p, MSKCLR, BIT(irqd_to_hwirq(d)));
100}
101
102static void gpio_rcar_config_interrupt_input_mode(struct gpio_rcar_priv *p,
103 unsigned int hwirq,
104 bool active_high_rising_edge,
Simon Horman7e1092b2013-05-24 18:47:24 +0900105 bool level_trigger,
106 bool both)
Magnus Damm119f5e42013-03-13 20:32:13 +0900107{
108 unsigned long flags;
109
110 /* follow steps in the GPIO documentation for
111 * "Setting Edge-Sensitive Interrupt Input Mode" and
112 * "Setting Level-Sensitive Interrupt Input Mode"
113 */
114
115 spin_lock_irqsave(&p->lock, flags);
116
117 /* Configure postive or negative logic in POSNEG */
118 gpio_rcar_modify_bit(p, POSNEG, hwirq, !active_high_rising_edge);
119
120 /* Configure edge or level trigger in EDGLEVEL */
121 gpio_rcar_modify_bit(p, EDGLEVEL, hwirq, !level_trigger);
122
Simon Horman7e1092b2013-05-24 18:47:24 +0900123 /* Select one edge or both edges in BOTHEDGE */
124 if (p->config.has_both_edge_trigger)
125 gpio_rcar_modify_bit(p, BOTHEDGE, hwirq, both);
126
Magnus Damm119f5e42013-03-13 20:32:13 +0900127 /* Select "Interrupt Input Mode" in IOINTSEL */
128 gpio_rcar_modify_bit(p, IOINTSEL, hwirq, true);
129
130 /* Write INTCLR in case of edge trigger */
131 if (!level_trigger)
132 gpio_rcar_write(p, INTCLR, BIT(hwirq));
133
134 spin_unlock_irqrestore(&p->lock, flags);
135}
136
137static int gpio_rcar_irq_set_type(struct irq_data *d, unsigned int type)
138{
Geert Uytterhoevenc7f3c5d2015-01-12 11:07:59 +0100139 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
140 struct gpio_rcar_priv *p = container_of(gc, struct gpio_rcar_priv,
141 gpio_chip);
Magnus Damm119f5e42013-03-13 20:32:13 +0900142 unsigned int hwirq = irqd_to_hwirq(d);
143
144 dev_dbg(&p->pdev->dev, "sense irq = %d, type = %d\n", hwirq, type);
145
146 switch (type & IRQ_TYPE_SENSE_MASK) {
147 case IRQ_TYPE_LEVEL_HIGH:
Simon Horman7e1092b2013-05-24 18:47:24 +0900148 gpio_rcar_config_interrupt_input_mode(p, hwirq, true, true,
149 false);
Magnus Damm119f5e42013-03-13 20:32:13 +0900150 break;
151 case IRQ_TYPE_LEVEL_LOW:
Simon Horman7e1092b2013-05-24 18:47:24 +0900152 gpio_rcar_config_interrupt_input_mode(p, hwirq, false, true,
153 false);
Magnus Damm119f5e42013-03-13 20:32:13 +0900154 break;
155 case IRQ_TYPE_EDGE_RISING:
Simon Horman7e1092b2013-05-24 18:47:24 +0900156 gpio_rcar_config_interrupt_input_mode(p, hwirq, true, false,
157 false);
Magnus Damm119f5e42013-03-13 20:32:13 +0900158 break;
159 case IRQ_TYPE_EDGE_FALLING:
Simon Horman7e1092b2013-05-24 18:47:24 +0900160 gpio_rcar_config_interrupt_input_mode(p, hwirq, false, false,
161 false);
162 break;
163 case IRQ_TYPE_EDGE_BOTH:
164 if (!p->config.has_both_edge_trigger)
165 return -EINVAL;
166 gpio_rcar_config_interrupt_input_mode(p, hwirq, true, false,
167 true);
Magnus Damm119f5e42013-03-13 20:32:13 +0900168 break;
169 default:
170 return -EINVAL;
171 }
172 return 0;
173}
174
Geert Uytterhoevenab82fa72015-03-18 19:41:09 +0100175static int gpio_rcar_irq_set_wake(struct irq_data *d, unsigned int on)
176{
177 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
178 struct gpio_rcar_priv *p = container_of(gc, struct gpio_rcar_priv,
179 gpio_chip);
Geert Uytterhoeven501ef0f2015-05-21 13:21:37 +0200180 int error;
Geert Uytterhoevenab82fa72015-03-18 19:41:09 +0100181
Geert Uytterhoeven501ef0f2015-05-21 13:21:37 +0200182 if (p->irq_parent) {
183 error = irq_set_irq_wake(p->irq_parent, on);
184 if (error) {
185 dev_dbg(&p->pdev->dev,
186 "irq %u doesn't support irq_set_wake\n",
187 p->irq_parent);
188 p->irq_parent = 0;
189 }
190 }
Geert Uytterhoevenab82fa72015-03-18 19:41:09 +0100191
192 if (!p->clk)
193 return 0;
194
195 if (on)
196 clk_enable(p->clk);
197 else
198 clk_disable(p->clk);
199
200 return 0;
201}
202
Magnus Damm119f5e42013-03-13 20:32:13 +0900203static irqreturn_t gpio_rcar_irq_handler(int irq, void *dev_id)
204{
205 struct gpio_rcar_priv *p = dev_id;
206 u32 pending;
207 unsigned int offset, irqs_handled = 0;
208
Valentine Barshak8808b642013-11-29 22:04:09 +0400209 while ((pending = gpio_rcar_read(p, INTDT) &
210 gpio_rcar_read(p, INTMSK))) {
Magnus Damm119f5e42013-03-13 20:32:13 +0900211 offset = __ffs(pending);
212 gpio_rcar_write(p, INTCLR, BIT(offset));
Geert Uytterhoevenc7f3c5d2015-01-12 11:07:59 +0100213 generic_handle_irq(irq_find_mapping(p->gpio_chip.irqdomain,
214 offset));
Magnus Damm119f5e42013-03-13 20:32:13 +0900215 irqs_handled++;
216 }
217
218 return irqs_handled ? IRQ_HANDLED : IRQ_NONE;
219}
220
221static inline struct gpio_rcar_priv *gpio_to_priv(struct gpio_chip *chip)
222{
223 return container_of(chip, struct gpio_rcar_priv, gpio_chip);
224}
225
226static void gpio_rcar_config_general_input_output_mode(struct gpio_chip *chip,
227 unsigned int gpio,
228 bool output)
229{
230 struct gpio_rcar_priv *p = gpio_to_priv(chip);
231 unsigned long flags;
232
233 /* follow steps in the GPIO documentation for
234 * "Setting General Output Mode" and
235 * "Setting General Input Mode"
236 */
237
238 spin_lock_irqsave(&p->lock, flags);
239
240 /* Configure postive logic in POSNEG */
241 gpio_rcar_modify_bit(p, POSNEG, gpio, false);
242
243 /* Select "General Input/Output Mode" in IOINTSEL */
244 gpio_rcar_modify_bit(p, IOINTSEL, gpio, false);
245
246 /* Select Input Mode or Output Mode in INOUTSEL */
247 gpio_rcar_modify_bit(p, INOUTSEL, gpio, output);
248
249 spin_unlock_irqrestore(&p->lock, flags);
250}
251
Laurent Pinchartdc3465a2013-03-10 03:27:00 +0100252static int gpio_rcar_request(struct gpio_chip *chip, unsigned offset)
253{
254 return pinctrl_request_gpio(chip->base + offset);
255}
256
257static void gpio_rcar_free(struct gpio_chip *chip, unsigned offset)
258{
259 pinctrl_free_gpio(chip->base + offset);
260
261 /* Set the GPIO as an input to ensure that the next GPIO request won't
262 * drive the GPIO pin as an output.
263 */
264 gpio_rcar_config_general_input_output_mode(chip, offset, false);
265}
266
Magnus Damm119f5e42013-03-13 20:32:13 +0900267static int gpio_rcar_direction_input(struct gpio_chip *chip, unsigned offset)
268{
269 gpio_rcar_config_general_input_output_mode(chip, offset, false);
270 return 0;
271}
272
273static int gpio_rcar_get(struct gpio_chip *chip, unsigned offset)
274{
Magnus Dammae9550f2013-06-17 08:41:52 +0900275 u32 bit = BIT(offset);
276
277 /* testing on r8a7790 shows that INDT does not show correct pin state
278 * when configured as output, so use OUTDT in case of output pins */
279 if (gpio_rcar_read(gpio_to_priv(chip), INOUTSEL) & bit)
Jürg Billeter7cb54092014-06-24 04:19:50 +0200280 return !!(gpio_rcar_read(gpio_to_priv(chip), OUTDT) & bit);
Magnus Dammae9550f2013-06-17 08:41:52 +0900281 else
Jürg Billeter7cb54092014-06-24 04:19:50 +0200282 return !!(gpio_rcar_read(gpio_to_priv(chip), INDT) & bit);
Magnus Damm119f5e42013-03-13 20:32:13 +0900283}
284
285static void gpio_rcar_set(struct gpio_chip *chip, unsigned offset, int value)
286{
287 struct gpio_rcar_priv *p = gpio_to_priv(chip);
288 unsigned long flags;
289
290 spin_lock_irqsave(&p->lock, flags);
291 gpio_rcar_modify_bit(p, OUTDT, offset, value);
292 spin_unlock_irqrestore(&p->lock, flags);
293}
294
295static int gpio_rcar_direction_output(struct gpio_chip *chip, unsigned offset,
296 int value)
297{
298 /* write GPIO value to output before selecting output mode of pin */
299 gpio_rcar_set(chip, offset, value);
300 gpio_rcar_config_general_input_output_mode(chip, offset, true);
301 return 0;
302}
303
Laurent Pinchart850dfe12013-11-29 14:48:00 +0100304struct gpio_rcar_info {
305 bool has_both_edge_trigger;
306};
307
Hisashi Nakamura1fd2b492014-11-07 20:54:08 +0900308static const struct gpio_rcar_info gpio_rcar_info_gen1 = {
309 .has_both_edge_trigger = false,
310};
311
312static const struct gpio_rcar_info gpio_rcar_info_gen2 = {
313 .has_both_edge_trigger = true,
314};
315
Laurent Pinchart850dfe12013-11-29 14:48:00 +0100316static const struct of_device_id gpio_rcar_of_table[] = {
317 {
318 .compatible = "renesas,gpio-r8a7790",
Hisashi Nakamura1fd2b492014-11-07 20:54:08 +0900319 .data = &gpio_rcar_info_gen2,
Laurent Pinchart850dfe12013-11-29 14:48:00 +0100320 }, {
321 .compatible = "renesas,gpio-r8a7791",
Hisashi Nakamura1fd2b492014-11-07 20:54:08 +0900322 .data = &gpio_rcar_info_gen2,
323 }, {
324 .compatible = "renesas,gpio-r8a7793",
325 .data = &gpio_rcar_info_gen2,
326 }, {
327 .compatible = "renesas,gpio-r8a7794",
328 .data = &gpio_rcar_info_gen2,
Laurent Pinchart850dfe12013-11-29 14:48:00 +0100329 }, {
330 .compatible = "renesas,gpio-rcar",
Hisashi Nakamura1fd2b492014-11-07 20:54:08 +0900331 .data = &gpio_rcar_info_gen1,
Laurent Pinchart850dfe12013-11-29 14:48:00 +0100332 }, {
333 /* Terminator */
334 },
335};
336
337MODULE_DEVICE_TABLE(of, gpio_rcar_of_table);
338
339static int gpio_rcar_parse_pdata(struct gpio_rcar_priv *p)
Laurent Pinchart159f8a02013-05-21 13:40:06 +0200340{
Jingoo Hane56aee12013-07-30 17:08:05 +0900341 struct gpio_rcar_config *pdata = dev_get_platdata(&p->pdev->dev);
Laurent Pinchart159f8a02013-05-21 13:40:06 +0200342 struct device_node *np = p->pdev->dev.of_node;
343 struct of_phandle_args args;
344 int ret;
Laurent Pinchart159f8a02013-05-21 13:40:06 +0200345
Laurent Pincharte3050622013-06-18 12:29:49 +0200346 if (pdata) {
Laurent Pinchart159f8a02013-05-21 13:40:06 +0200347 p->config = *pdata;
Laurent Pincharte3050622013-06-18 12:29:49 +0200348 } else if (IS_ENABLED(CONFIG_OF) && np) {
Laurent Pinchart850dfe12013-11-29 14:48:00 +0100349 const struct of_device_id *match;
350 const struct gpio_rcar_info *info;
351
352 match = of_match_node(gpio_rcar_of_table, np);
353 if (!match)
354 return -EINVAL;
355
356 info = match->data;
357
Laurent Pinchart01eb2d12013-09-11 15:51:01 +0200358 ret = of_parse_phandle_with_fixed_args(np, "gpio-ranges", 3, 0,
359 &args);
360 p->config.number_of_pins = ret == 0 ? args.args[2]
Laurent Pinchart159f8a02013-05-21 13:40:06 +0200361 : RCAR_MAX_GPIO_PER_BANK;
362 p->config.gpio_base = -1;
Laurent Pinchart850dfe12013-11-29 14:48:00 +0100363 p->config.has_both_edge_trigger = info->has_both_edge_trigger;
Laurent Pinchart159f8a02013-05-21 13:40:06 +0200364 }
Laurent Pinchart159f8a02013-05-21 13:40:06 +0200365
366 if (p->config.number_of_pins == 0 ||
367 p->config.number_of_pins > RCAR_MAX_GPIO_PER_BANK) {
368 dev_warn(&p->pdev->dev,
369 "Invalid number of gpio lines %u, using %u\n",
370 p->config.number_of_pins, RCAR_MAX_GPIO_PER_BANK);
371 p->config.number_of_pins = RCAR_MAX_GPIO_PER_BANK;
372 }
Laurent Pinchart850dfe12013-11-29 14:48:00 +0100373
374 return 0;
Laurent Pinchart159f8a02013-05-21 13:40:06 +0200375}
376
Magnus Damm119f5e42013-03-13 20:32:13 +0900377static int gpio_rcar_probe(struct platform_device *pdev)
378{
Magnus Damm119f5e42013-03-13 20:32:13 +0900379 struct gpio_rcar_priv *p;
380 struct resource *io, *irq;
381 struct gpio_chip *gpio_chip;
382 struct irq_chip *irq_chip;
Geert Uytterhoevenb22978f2014-03-27 21:47:36 +0100383 struct device *dev = &pdev->dev;
384 const char *name = dev_name(dev);
Magnus Damm119f5e42013-03-13 20:32:13 +0900385 int ret;
386
Geert Uytterhoevenb22978f2014-03-27 21:47:36 +0100387 p = devm_kzalloc(dev, sizeof(*p), GFP_KERNEL);
Geert Uytterhoeven7d82bf32015-01-12 11:07:58 +0100388 if (!p)
389 return -ENOMEM;
Magnus Damm119f5e42013-03-13 20:32:13 +0900390
Magnus Damm119f5e42013-03-13 20:32:13 +0900391 p->pdev = pdev;
Magnus Damm119f5e42013-03-13 20:32:13 +0900392 spin_lock_init(&p->lock);
393
Laurent Pinchart159f8a02013-05-21 13:40:06 +0200394 /* Get device configuration from DT node or platform data. */
Laurent Pinchart850dfe12013-11-29 14:48:00 +0100395 ret = gpio_rcar_parse_pdata(p);
396 if (ret < 0)
397 return ret;
Laurent Pinchart159f8a02013-05-21 13:40:06 +0200398
399 platform_set_drvdata(pdev, p);
400
Geert Uytterhoevenab82fa72015-03-18 19:41:09 +0100401 p->clk = devm_clk_get(dev, NULL);
402 if (IS_ERR(p->clk)) {
403 dev_warn(dev, "unable to get clock\n");
404 p->clk = NULL;
405 }
406
Geert Uytterhoevendf0c6c82014-04-14 20:33:13 +0200407 pm_runtime_enable(dev);
408 pm_runtime_get_sync(dev);
409
Magnus Damm119f5e42013-03-13 20:32:13 +0900410 io = platform_get_resource(pdev, IORESOURCE_MEM, 0);
411 irq = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
412
413 if (!io || !irq) {
Geert Uytterhoevenb22978f2014-03-27 21:47:36 +0100414 dev_err(dev, "missing IRQ or IOMEM\n");
Magnus Damm119f5e42013-03-13 20:32:13 +0900415 ret = -EINVAL;
416 goto err0;
417 }
418
Geert Uytterhoevenb22978f2014-03-27 21:47:36 +0100419 p->base = devm_ioremap_nocache(dev, io->start, resource_size(io));
Magnus Damm119f5e42013-03-13 20:32:13 +0900420 if (!p->base) {
Geert Uytterhoevenb22978f2014-03-27 21:47:36 +0100421 dev_err(dev, "failed to remap I/O memory\n");
Magnus Damm119f5e42013-03-13 20:32:13 +0900422 ret = -ENXIO;
423 goto err0;
424 }
425
426 gpio_chip = &p->gpio_chip;
Laurent Pinchartdc3465a2013-03-10 03:27:00 +0100427 gpio_chip->request = gpio_rcar_request;
428 gpio_chip->free = gpio_rcar_free;
Magnus Damm119f5e42013-03-13 20:32:13 +0900429 gpio_chip->direction_input = gpio_rcar_direction_input;
430 gpio_chip->get = gpio_rcar_get;
431 gpio_chip->direction_output = gpio_rcar_direction_output;
432 gpio_chip->set = gpio_rcar_set;
Magnus Damm119f5e42013-03-13 20:32:13 +0900433 gpio_chip->label = name;
Geert Uytterhoevenb22978f2014-03-27 21:47:36 +0100434 gpio_chip->dev = dev;
Magnus Damm119f5e42013-03-13 20:32:13 +0900435 gpio_chip->owner = THIS_MODULE;
436 gpio_chip->base = p->config.gpio_base;
437 gpio_chip->ngpio = p->config.number_of_pins;
438
439 irq_chip = &p->irq_chip;
440 irq_chip->name = name;
441 irq_chip->irq_mask = gpio_rcar_irq_disable;
442 irq_chip->irq_unmask = gpio_rcar_irq_enable;
Magnus Damm119f5e42013-03-13 20:32:13 +0900443 irq_chip->irq_set_type = gpio_rcar_irq_set_type;
Geert Uytterhoevenab82fa72015-03-18 19:41:09 +0100444 irq_chip->irq_set_wake = gpio_rcar_irq_set_wake;
445 irq_chip->flags = IRQCHIP_SET_TYPE_MASKED | IRQCHIP_MASK_ON_SUSPEND;
Magnus Damm119f5e42013-03-13 20:32:13 +0900446
Geert Uytterhoevenc7f3c5d2015-01-12 11:07:59 +0100447 ret = gpiochip_add(gpio_chip);
448 if (ret) {
449 dev_err(dev, "failed to add GPIO controller\n");
Dan Carpenter0c8aab82013-11-07 10:56:51 +0300450 goto err0;
Magnus Damm119f5e42013-03-13 20:32:13 +0900451 }
452
Geert Uytterhoeven4d84b9e2015-03-18 19:41:07 +0100453 ret = gpiochip_irqchip_add(gpio_chip, irq_chip, p->config.irq_base,
Geert Uytterhoevenc7f3c5d2015-01-12 11:07:59 +0100454 handle_level_irq, IRQ_TYPE_NONE);
455 if (ret) {
456 dev_err(dev, "cannot add irqchip\n");
457 goto err1;
458 }
459
Geert Uytterhoevenab82fa72015-03-18 19:41:09 +0100460 p->irq_parent = irq->start;
Geert Uytterhoevenb22978f2014-03-27 21:47:36 +0100461 if (devm_request_irq(dev, irq->start, gpio_rcar_irq_handler,
462 IRQF_SHARED, name, p)) {
463 dev_err(dev, "failed to request IRQ\n");
Magnus Damm119f5e42013-03-13 20:32:13 +0900464 ret = -ENOENT;
465 goto err1;
466 }
467
Geert Uytterhoevenb22978f2014-03-27 21:47:36 +0100468 dev_info(dev, "driving %d GPIOs\n", p->config.number_of_pins);
Magnus Damm119f5e42013-03-13 20:32:13 +0900469
470 /* warn in case of mismatch if irq base is specified */
471 if (p->config.irq_base) {
Geert Uytterhoeven4d84b9e2015-03-18 19:41:07 +0100472 ret = irq_find_mapping(gpio_chip->irqdomain, 0);
Magnus Damm119f5e42013-03-13 20:32:13 +0900473 if (p->config.irq_base != ret)
Geert Uytterhoevenb22978f2014-03-27 21:47:36 +0100474 dev_warn(dev, "irq base mismatch (%u/%u)\n",
Magnus Damm119f5e42013-03-13 20:32:13 +0900475 p->config.irq_base, ret);
476 }
477
Laurent Pinchart159f8a02013-05-21 13:40:06 +0200478 if (p->config.pctl_name) {
479 ret = gpiochip_add_pin_range(gpio_chip, p->config.pctl_name, 0,
480 gpio_chip->base, gpio_chip->ngpio);
481 if (ret < 0)
Geert Uytterhoevenb22978f2014-03-27 21:47:36 +0100482 dev_warn(dev, "failed to add pin range\n");
Laurent Pinchart159f8a02013-05-21 13:40:06 +0200483 }
Laurent Pinchartdc3465a2013-03-10 03:27:00 +0100484
Magnus Damm119f5e42013-03-13 20:32:13 +0900485 return 0;
486
487err1:
Geert Uytterhoeven4d84b9e2015-03-18 19:41:07 +0100488 gpiochip_remove(gpio_chip);
Magnus Damm119f5e42013-03-13 20:32:13 +0900489err0:
Geert Uytterhoevendf0c6c82014-04-14 20:33:13 +0200490 pm_runtime_put(dev);
491 pm_runtime_disable(dev);
Magnus Damm119f5e42013-03-13 20:32:13 +0900492 return ret;
493}
494
495static int gpio_rcar_remove(struct platform_device *pdev)
496{
497 struct gpio_rcar_priv *p = platform_get_drvdata(pdev);
Magnus Damm119f5e42013-03-13 20:32:13 +0900498
abdoulaye berthe9f5132a2014-07-12 22:30:12 +0200499 gpiochip_remove(&p->gpio_chip);
Magnus Damm119f5e42013-03-13 20:32:13 +0900500
Geert Uytterhoevendf0c6c82014-04-14 20:33:13 +0200501 pm_runtime_put(&pdev->dev);
502 pm_runtime_disable(&pdev->dev);
Magnus Damm119f5e42013-03-13 20:32:13 +0900503 return 0;
504}
505
506static struct platform_driver gpio_rcar_device_driver = {
507 .probe = gpio_rcar_probe,
508 .remove = gpio_rcar_remove,
509 .driver = {
510 .name = "gpio_rcar",
Laurent Pinchart159f8a02013-05-21 13:40:06 +0200511 .of_match_table = of_match_ptr(gpio_rcar_of_table),
Magnus Damm119f5e42013-03-13 20:32:13 +0900512 }
513};
514
515module_platform_driver(gpio_rcar_device_driver);
516
517MODULE_AUTHOR("Magnus Damm");
518MODULE_DESCRIPTION("Renesas R-Car GPIO Driver");
519MODULE_LICENSE("GPL v2");