Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 1 | /* |
| 2 | * Copyright © 2008 Intel Corporation |
| 3 | * |
| 4 | * Permission is hereby granted, free of charge, to any person obtaining a |
| 5 | * copy of this software and associated documentation files (the "Software"), |
| 6 | * to deal in the Software without restriction, including without limitation |
| 7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, |
| 8 | * and/or sell copies of the Software, and to permit persons to whom the |
| 9 | * Software is furnished to do so, subject to the following conditions: |
| 10 | * |
| 11 | * The above copyright notice and this permission notice (including the next |
| 12 | * paragraph) shall be included in all copies or substantial portions of the |
| 13 | * Software. |
| 14 | * |
| 15 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
| 16 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
| 17 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
| 18 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER |
| 19 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING |
| 20 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS |
| 21 | * IN THE SOFTWARE. |
| 22 | * |
| 23 | * Authors: |
| 24 | * Keith Packard <keithp@keithp.com> |
| 25 | * |
| 26 | */ |
| 27 | |
| 28 | #include <linux/i2c.h> |
Tejun Heo | 5a0e3ad | 2010-03-24 17:04:11 +0900 | [diff] [blame] | 29 | #include <linux/slab.h> |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 30 | #include "drmP.h" |
| 31 | #include "drm.h" |
| 32 | #include "drm_crtc.h" |
| 33 | #include "drm_crtc_helper.h" |
| 34 | #include "intel_drv.h" |
| 35 | #include "i915_drm.h" |
| 36 | #include "i915_drv.h" |
Dave Airlie | ab2c067 | 2009-12-04 10:55:24 +1000 | [diff] [blame] | 37 | #include "drm_dp_helper.h" |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 38 | |
Zhao Yakui | ae266c9 | 2009-11-24 09:48:46 +0800 | [diff] [blame] | 39 | |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 40 | #define DP_LINK_STATUS_SIZE 6 |
| 41 | #define DP_LINK_CHECK_TIMEOUT (10 * 1000) |
| 42 | |
| 43 | #define DP_LINK_CONFIGURATION_SIZE 9 |
| 44 | |
Chris Wilson | ea5b213 | 2010-08-04 13:50:23 +0100 | [diff] [blame] | 45 | struct intel_dp { |
| 46 | struct intel_encoder base; |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 47 | uint32_t output_reg; |
| 48 | uint32_t DP; |
| 49 | uint8_t link_configuration[DP_LINK_CONFIGURATION_SIZE]; |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 50 | bool has_audio; |
Chris Wilson | f684960 | 2010-09-19 09:29:33 +0100 | [diff] [blame] | 51 | int force_audio; |
Chris Wilson | e953fd7 | 2011-02-21 22:23:52 +0000 | [diff] [blame] | 52 | uint32_t color_range; |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 53 | uint8_t link_bw; |
| 54 | uint8_t lane_count; |
| 55 | uint8_t dpcd[4]; |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 56 | struct i2c_adapter adapter; |
| 57 | struct i2c_algo_dp_aux_data algo; |
Adam Jackson | f091737 | 2010-07-16 14:46:27 -0400 | [diff] [blame] | 58 | bool is_pch_edp; |
Jesse Barnes | 33a34e4 | 2010-09-08 12:42:02 -0700 | [diff] [blame] | 59 | uint8_t train_set[4]; |
| 60 | uint8_t link_status[DP_LINK_STATUS_SIZE]; |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 61 | }; |
| 62 | |
Jesse Barnes | cfcb0fc | 2010-10-07 16:01:06 -0700 | [diff] [blame] | 63 | /** |
| 64 | * is_edp - is the given port attached to an eDP panel (either CPU or PCH) |
| 65 | * @intel_dp: DP struct |
| 66 | * |
| 67 | * If a CPU or PCH DP output is attached to an eDP panel, this function |
| 68 | * will return true, and false otherwise. |
| 69 | */ |
| 70 | static bool is_edp(struct intel_dp *intel_dp) |
| 71 | { |
| 72 | return intel_dp->base.type == INTEL_OUTPUT_EDP; |
| 73 | } |
| 74 | |
| 75 | /** |
| 76 | * is_pch_edp - is the port on the PCH and attached to an eDP panel? |
| 77 | * @intel_dp: DP struct |
| 78 | * |
| 79 | * Returns true if the given DP struct corresponds to a PCH DP port attached |
| 80 | * to an eDP panel, false otherwise. Helpful for determining whether we |
| 81 | * may need FDI resources for a given DP output or not. |
| 82 | */ |
| 83 | static bool is_pch_edp(struct intel_dp *intel_dp) |
| 84 | { |
| 85 | return intel_dp->is_pch_edp; |
| 86 | } |
| 87 | |
Chris Wilson | ea5b213 | 2010-08-04 13:50:23 +0100 | [diff] [blame] | 88 | static struct intel_dp *enc_to_intel_dp(struct drm_encoder *encoder) |
| 89 | { |
Chris Wilson | 4ef69c7 | 2010-09-09 15:14:28 +0100 | [diff] [blame] | 90 | return container_of(encoder, struct intel_dp, base.base); |
Chris Wilson | ea5b213 | 2010-08-04 13:50:23 +0100 | [diff] [blame] | 91 | } |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 92 | |
Chris Wilson | df0e924 | 2010-09-09 16:20:55 +0100 | [diff] [blame] | 93 | static struct intel_dp *intel_attached_dp(struct drm_connector *connector) |
| 94 | { |
| 95 | return container_of(intel_attached_encoder(connector), |
| 96 | struct intel_dp, base); |
| 97 | } |
| 98 | |
Jesse Barnes | 814948a | 2010-10-07 16:01:09 -0700 | [diff] [blame] | 99 | /** |
| 100 | * intel_encoder_is_pch_edp - is the given encoder a PCH attached eDP? |
| 101 | * @encoder: DRM encoder |
| 102 | * |
| 103 | * Return true if @encoder corresponds to a PCH attached eDP panel. Needed |
| 104 | * by intel_display.c. |
| 105 | */ |
| 106 | bool intel_encoder_is_pch_edp(struct drm_encoder *encoder) |
| 107 | { |
| 108 | struct intel_dp *intel_dp; |
| 109 | |
| 110 | if (!encoder) |
| 111 | return false; |
| 112 | |
| 113 | intel_dp = enc_to_intel_dp(encoder); |
| 114 | |
| 115 | return is_pch_edp(intel_dp); |
| 116 | } |
| 117 | |
Jesse Barnes | 33a34e4 | 2010-09-08 12:42:02 -0700 | [diff] [blame] | 118 | static void intel_dp_start_link_train(struct intel_dp *intel_dp); |
| 119 | static void intel_dp_complete_link_train(struct intel_dp *intel_dp); |
Chris Wilson | ea5b213 | 2010-08-04 13:50:23 +0100 | [diff] [blame] | 120 | static void intel_dp_link_down(struct intel_dp *intel_dp); |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 121 | |
Zhenyu Wang | 32f9d65 | 2009-07-24 01:00:32 +0800 | [diff] [blame] | 122 | void |
Eric Anholt | 21d40d3 | 2010-03-25 11:11:14 -0700 | [diff] [blame] | 123 | intel_edp_link_config (struct intel_encoder *intel_encoder, |
Chris Wilson | ea5b213 | 2010-08-04 13:50:23 +0100 | [diff] [blame] | 124 | int *lane_num, int *link_bw) |
Zhenyu Wang | 32f9d65 | 2009-07-24 01:00:32 +0800 | [diff] [blame] | 125 | { |
Chris Wilson | ea5b213 | 2010-08-04 13:50:23 +0100 | [diff] [blame] | 126 | struct intel_dp *intel_dp = container_of(intel_encoder, struct intel_dp, base); |
Zhenyu Wang | 32f9d65 | 2009-07-24 01:00:32 +0800 | [diff] [blame] | 127 | |
Chris Wilson | ea5b213 | 2010-08-04 13:50:23 +0100 | [diff] [blame] | 128 | *lane_num = intel_dp->lane_count; |
| 129 | if (intel_dp->link_bw == DP_LINK_BW_1_62) |
Zhenyu Wang | 32f9d65 | 2009-07-24 01:00:32 +0800 | [diff] [blame] | 130 | *link_bw = 162000; |
Chris Wilson | ea5b213 | 2010-08-04 13:50:23 +0100 | [diff] [blame] | 131 | else if (intel_dp->link_bw == DP_LINK_BW_2_7) |
Zhenyu Wang | 32f9d65 | 2009-07-24 01:00:32 +0800 | [diff] [blame] | 132 | *link_bw = 270000; |
| 133 | } |
| 134 | |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 135 | static int |
Chris Wilson | ea5b213 | 2010-08-04 13:50:23 +0100 | [diff] [blame] | 136 | intel_dp_max_lane_count(struct intel_dp *intel_dp) |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 137 | { |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 138 | int max_lane_count = 4; |
| 139 | |
Jesse Barnes | 7183dc2 | 2011-07-07 11:10:58 -0700 | [diff] [blame] | 140 | if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11) { |
| 141 | max_lane_count = intel_dp->dpcd[DP_MAX_LANE_COUNT] & 0x1f; |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 142 | switch (max_lane_count) { |
| 143 | case 1: case 2: case 4: |
| 144 | break; |
| 145 | default: |
| 146 | max_lane_count = 4; |
| 147 | } |
| 148 | } |
| 149 | return max_lane_count; |
| 150 | } |
| 151 | |
| 152 | static int |
Chris Wilson | ea5b213 | 2010-08-04 13:50:23 +0100 | [diff] [blame] | 153 | intel_dp_max_link_bw(struct intel_dp *intel_dp) |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 154 | { |
Jesse Barnes | 7183dc2 | 2011-07-07 11:10:58 -0700 | [diff] [blame] | 155 | int max_link_bw = intel_dp->dpcd[DP_MAX_LINK_RATE]; |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 156 | |
| 157 | switch (max_link_bw) { |
| 158 | case DP_LINK_BW_1_62: |
| 159 | case DP_LINK_BW_2_7: |
| 160 | break; |
| 161 | default: |
| 162 | max_link_bw = DP_LINK_BW_1_62; |
| 163 | break; |
| 164 | } |
| 165 | return max_link_bw; |
| 166 | } |
| 167 | |
| 168 | static int |
| 169 | intel_dp_link_clock(uint8_t link_bw) |
| 170 | { |
| 171 | if (link_bw == DP_LINK_BW_2_7) |
| 172 | return 270000; |
| 173 | else |
| 174 | return 162000; |
| 175 | } |
| 176 | |
| 177 | /* I think this is a fiction */ |
| 178 | static int |
Chris Wilson | ea5b213 | 2010-08-04 13:50:23 +0100 | [diff] [blame] | 179 | intel_dp_link_required(struct drm_device *dev, struct intel_dp *intel_dp, int pixel_clock) |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 180 | { |
Zhenyu Wang | 885a5fb | 2010-01-12 05:38:31 +0800 | [diff] [blame] | 181 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 182 | |
Jesse Barnes | 4d92646 | 2010-10-07 16:01:07 -0700 | [diff] [blame] | 183 | if (is_edp(intel_dp)) |
Chris Wilson | 5ceb0f9 | 2010-09-24 10:24:28 +0100 | [diff] [blame] | 184 | return (pixel_clock * dev_priv->edp.bpp + 7) / 8; |
Zhenyu Wang | 885a5fb | 2010-01-12 05:38:31 +0800 | [diff] [blame] | 185 | else |
| 186 | return pixel_clock * 3; |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 187 | } |
| 188 | |
| 189 | static int |
Dave Airlie | fe27d53 | 2010-06-30 11:46:17 +1000 | [diff] [blame] | 190 | intel_dp_max_data_rate(int max_link_clock, int max_lanes) |
| 191 | { |
| 192 | return (max_link_clock * max_lanes * 8) / 10; |
| 193 | } |
| 194 | |
| 195 | static int |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 196 | intel_dp_mode_valid(struct drm_connector *connector, |
| 197 | struct drm_display_mode *mode) |
| 198 | { |
Chris Wilson | df0e924 | 2010-09-09 16:20:55 +0100 | [diff] [blame] | 199 | struct intel_dp *intel_dp = intel_attached_dp(connector); |
Zhao Yakui | 7de56f4 | 2010-07-19 09:43:14 +0100 | [diff] [blame] | 200 | struct drm_device *dev = connector->dev; |
| 201 | struct drm_i915_private *dev_priv = dev->dev_private; |
Chris Wilson | ea5b213 | 2010-08-04 13:50:23 +0100 | [diff] [blame] | 202 | int max_link_clock = intel_dp_link_clock(intel_dp_max_link_bw(intel_dp)); |
| 203 | int max_lanes = intel_dp_max_lane_count(intel_dp); |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 204 | |
Jesse Barnes | 4d92646 | 2010-10-07 16:01:07 -0700 | [diff] [blame] | 205 | if (is_edp(intel_dp) && dev_priv->panel_fixed_mode) { |
Zhao Yakui | 7de56f4 | 2010-07-19 09:43:14 +0100 | [diff] [blame] | 206 | if (mode->hdisplay > dev_priv->panel_fixed_mode->hdisplay) |
| 207 | return MODE_PANEL; |
| 208 | |
| 209 | if (mode->vdisplay > dev_priv->panel_fixed_mode->vdisplay) |
| 210 | return MODE_PANEL; |
| 211 | } |
| 212 | |
Lucas De Marchi | 25985ed | 2011-03-30 22:57:33 -0300 | [diff] [blame] | 213 | /* only refuse the mode on non eDP since we have seen some weird eDP panels |
Dave Airlie | fe27d53 | 2010-06-30 11:46:17 +1000 | [diff] [blame] | 214 | which are outside spec tolerances but somehow work by magic */ |
Jesse Barnes | cfcb0fc | 2010-10-07 16:01:06 -0700 | [diff] [blame] | 215 | if (!is_edp(intel_dp) && |
Chris Wilson | ea5b213 | 2010-08-04 13:50:23 +0100 | [diff] [blame] | 216 | (intel_dp_link_required(connector->dev, intel_dp, mode->clock) |
Dave Airlie | fe27d53 | 2010-06-30 11:46:17 +1000 | [diff] [blame] | 217 | > intel_dp_max_data_rate(max_link_clock, max_lanes))) |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 218 | return MODE_CLOCK_HIGH; |
| 219 | |
| 220 | if (mode->clock < 10000) |
| 221 | return MODE_CLOCK_LOW; |
| 222 | |
| 223 | return MODE_OK; |
| 224 | } |
| 225 | |
| 226 | static uint32_t |
| 227 | pack_aux(uint8_t *src, int src_bytes) |
| 228 | { |
| 229 | int i; |
| 230 | uint32_t v = 0; |
| 231 | |
| 232 | if (src_bytes > 4) |
| 233 | src_bytes = 4; |
| 234 | for (i = 0; i < src_bytes; i++) |
| 235 | v |= ((uint32_t) src[i]) << ((3-i) * 8); |
| 236 | return v; |
| 237 | } |
| 238 | |
| 239 | static void |
| 240 | unpack_aux(uint32_t src, uint8_t *dst, int dst_bytes) |
| 241 | { |
| 242 | int i; |
| 243 | if (dst_bytes > 4) |
| 244 | dst_bytes = 4; |
| 245 | for (i = 0; i < dst_bytes; i++) |
| 246 | dst[i] = src >> ((3-i) * 8); |
| 247 | } |
| 248 | |
Keith Packard | fb0f8fb | 2009-06-11 22:31:31 -0700 | [diff] [blame] | 249 | /* hrawclock is 1/4 the FSB frequency */ |
| 250 | static int |
| 251 | intel_hrawclk(struct drm_device *dev) |
| 252 | { |
| 253 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 254 | uint32_t clkcfg; |
| 255 | |
| 256 | clkcfg = I915_READ(CLKCFG); |
| 257 | switch (clkcfg & CLKCFG_FSB_MASK) { |
| 258 | case CLKCFG_FSB_400: |
| 259 | return 100; |
| 260 | case CLKCFG_FSB_533: |
| 261 | return 133; |
| 262 | case CLKCFG_FSB_667: |
| 263 | return 166; |
| 264 | case CLKCFG_FSB_800: |
| 265 | return 200; |
| 266 | case CLKCFG_FSB_1067: |
| 267 | return 266; |
| 268 | case CLKCFG_FSB_1333: |
| 269 | return 333; |
| 270 | /* these two are just a guess; one of them might be right */ |
| 271 | case CLKCFG_FSB_1600: |
| 272 | case CLKCFG_FSB_1600_ALT: |
| 273 | return 400; |
| 274 | default: |
| 275 | return 133; |
| 276 | } |
| 277 | } |
| 278 | |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 279 | static int |
Chris Wilson | ea5b213 | 2010-08-04 13:50:23 +0100 | [diff] [blame] | 280 | intel_dp_aux_ch(struct intel_dp *intel_dp, |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 281 | uint8_t *send, int send_bytes, |
| 282 | uint8_t *recv, int recv_size) |
| 283 | { |
Chris Wilson | ea5b213 | 2010-08-04 13:50:23 +0100 | [diff] [blame] | 284 | uint32_t output_reg = intel_dp->output_reg; |
Chris Wilson | 4ef69c7 | 2010-09-09 15:14:28 +0100 | [diff] [blame] | 285 | struct drm_device *dev = intel_dp->base.base.dev; |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 286 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 287 | uint32_t ch_ctl = output_reg + 0x10; |
| 288 | uint32_t ch_data = ch_ctl + 4; |
| 289 | int i; |
| 290 | int recv_bytes; |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 291 | uint32_t status; |
Keith Packard | fb0f8fb | 2009-06-11 22:31:31 -0700 | [diff] [blame] | 292 | uint32_t aux_clock_divider; |
Zhenyu Wang | e3421a1 | 2010-04-08 09:43:27 +0800 | [diff] [blame] | 293 | int try, precharge; |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 294 | |
| 295 | /* The clock divider is based off the hrawclk, |
Keith Packard | fb0f8fb | 2009-06-11 22:31:31 -0700 | [diff] [blame] | 296 | * and would like to run at 2MHz. So, take the |
| 297 | * hrawclk value and divide by 2 and use that |
Jesse Barnes | 6176b8f | 2010-09-08 12:42:00 -0700 | [diff] [blame] | 298 | * |
| 299 | * Note that PCH attached eDP panels should use a 125MHz input |
| 300 | * clock divider. |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 301 | */ |
Jesse Barnes | cfcb0fc | 2010-10-07 16:01:06 -0700 | [diff] [blame] | 302 | if (is_edp(intel_dp) && !is_pch_edp(intel_dp)) { |
Zhenyu Wang | e3421a1 | 2010-04-08 09:43:27 +0800 | [diff] [blame] | 303 | if (IS_GEN6(dev)) |
| 304 | aux_clock_divider = 200; /* SNB eDP input clock at 400Mhz */ |
| 305 | else |
| 306 | aux_clock_divider = 225; /* eDP input clock at 450Mhz */ |
| 307 | } else if (HAS_PCH_SPLIT(dev)) |
Adam Jackson | f2b115e | 2009-12-03 17:14:42 -0500 | [diff] [blame] | 308 | aux_clock_divider = 62; /* IRL input clock fixed at 125Mhz */ |
Zhenyu Wang | 5eb08b6 | 2009-07-24 01:00:31 +0800 | [diff] [blame] | 309 | else |
| 310 | aux_clock_divider = intel_hrawclk(dev) / 2; |
| 311 | |
Zhenyu Wang | e3421a1 | 2010-04-08 09:43:27 +0800 | [diff] [blame] | 312 | if (IS_GEN6(dev)) |
| 313 | precharge = 3; |
| 314 | else |
| 315 | precharge = 5; |
| 316 | |
Chris Wilson | 4f7f7b7 | 2010-08-18 18:12:56 +0100 | [diff] [blame] | 317 | if (I915_READ(ch_ctl) & DP_AUX_CH_CTL_SEND_BUSY) { |
| 318 | DRM_ERROR("dp_aux_ch not started status 0x%08x\n", |
| 319 | I915_READ(ch_ctl)); |
| 320 | return -EBUSY; |
| 321 | } |
| 322 | |
Keith Packard | fb0f8fb | 2009-06-11 22:31:31 -0700 | [diff] [blame] | 323 | /* Must try at least 3 times according to DP spec */ |
| 324 | for (try = 0; try < 5; try++) { |
| 325 | /* Load the send data into the aux channel data registers */ |
Chris Wilson | 4f7f7b7 | 2010-08-18 18:12:56 +0100 | [diff] [blame] | 326 | for (i = 0; i < send_bytes; i += 4) |
| 327 | I915_WRITE(ch_data + i, |
| 328 | pack_aux(send + i, send_bytes - i)); |
Keith Packard | fb0f8fb | 2009-06-11 22:31:31 -0700 | [diff] [blame] | 329 | |
| 330 | /* Send the command and wait for it to complete */ |
Chris Wilson | 4f7f7b7 | 2010-08-18 18:12:56 +0100 | [diff] [blame] | 331 | I915_WRITE(ch_ctl, |
| 332 | DP_AUX_CH_CTL_SEND_BUSY | |
| 333 | DP_AUX_CH_CTL_TIME_OUT_400us | |
| 334 | (send_bytes << DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT) | |
| 335 | (precharge << DP_AUX_CH_CTL_PRECHARGE_2US_SHIFT) | |
| 336 | (aux_clock_divider << DP_AUX_CH_CTL_BIT_CLOCK_2X_SHIFT) | |
| 337 | DP_AUX_CH_CTL_DONE | |
| 338 | DP_AUX_CH_CTL_TIME_OUT_ERROR | |
| 339 | DP_AUX_CH_CTL_RECEIVE_ERROR); |
Keith Packard | fb0f8fb | 2009-06-11 22:31:31 -0700 | [diff] [blame] | 340 | for (;;) { |
Keith Packard | fb0f8fb | 2009-06-11 22:31:31 -0700 | [diff] [blame] | 341 | status = I915_READ(ch_ctl); |
| 342 | if ((status & DP_AUX_CH_CTL_SEND_BUSY) == 0) |
| 343 | break; |
Chris Wilson | 4f7f7b7 | 2010-08-18 18:12:56 +0100 | [diff] [blame] | 344 | udelay(100); |
Keith Packard | fb0f8fb | 2009-06-11 22:31:31 -0700 | [diff] [blame] | 345 | } |
| 346 | |
| 347 | /* Clear done status and any errors */ |
Chris Wilson | 4f7f7b7 | 2010-08-18 18:12:56 +0100 | [diff] [blame] | 348 | I915_WRITE(ch_ctl, |
| 349 | status | |
| 350 | DP_AUX_CH_CTL_DONE | |
| 351 | DP_AUX_CH_CTL_TIME_OUT_ERROR | |
| 352 | DP_AUX_CH_CTL_RECEIVE_ERROR); |
| 353 | if (status & DP_AUX_CH_CTL_DONE) |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 354 | break; |
| 355 | } |
| 356 | |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 357 | if ((status & DP_AUX_CH_CTL_DONE) == 0) { |
Keith Packard | 1ae8c0a | 2009-06-28 15:42:17 -0700 | [diff] [blame] | 358 | DRM_ERROR("dp_aux_ch not done status 0x%08x\n", status); |
Keith Packard | a5b3da5 | 2009-06-11 22:30:32 -0700 | [diff] [blame] | 359 | return -EBUSY; |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 360 | } |
| 361 | |
| 362 | /* Check for timeout or receive error. |
| 363 | * Timeouts occur when the sink is not connected |
| 364 | */ |
Keith Packard | a5b3da5 | 2009-06-11 22:30:32 -0700 | [diff] [blame] | 365 | if (status & DP_AUX_CH_CTL_RECEIVE_ERROR) { |
Keith Packard | 1ae8c0a | 2009-06-28 15:42:17 -0700 | [diff] [blame] | 366 | DRM_ERROR("dp_aux_ch receive error status 0x%08x\n", status); |
Keith Packard | a5b3da5 | 2009-06-11 22:30:32 -0700 | [diff] [blame] | 367 | return -EIO; |
| 368 | } |
Keith Packard | 1ae8c0a | 2009-06-28 15:42:17 -0700 | [diff] [blame] | 369 | |
| 370 | /* Timeouts occur when the device isn't connected, so they're |
| 371 | * "normal" -- don't fill the kernel log with these */ |
Keith Packard | a5b3da5 | 2009-06-11 22:30:32 -0700 | [diff] [blame] | 372 | if (status & DP_AUX_CH_CTL_TIME_OUT_ERROR) { |
Zhao Yakui | 28c9773 | 2009-10-09 11:39:41 +0800 | [diff] [blame] | 373 | DRM_DEBUG_KMS("dp_aux_ch timeout status 0x%08x\n", status); |
Keith Packard | a5b3da5 | 2009-06-11 22:30:32 -0700 | [diff] [blame] | 374 | return -ETIMEDOUT; |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 375 | } |
| 376 | |
| 377 | /* Unload any bytes sent back from the other side */ |
| 378 | recv_bytes = ((status & DP_AUX_CH_CTL_MESSAGE_SIZE_MASK) >> |
| 379 | DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT); |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 380 | if (recv_bytes > recv_size) |
| 381 | recv_bytes = recv_size; |
| 382 | |
Chris Wilson | 4f7f7b7 | 2010-08-18 18:12:56 +0100 | [diff] [blame] | 383 | for (i = 0; i < recv_bytes; i += 4) |
| 384 | unpack_aux(I915_READ(ch_data + i), |
| 385 | recv + i, recv_bytes - i); |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 386 | |
| 387 | return recv_bytes; |
| 388 | } |
| 389 | |
| 390 | /* Write data to the aux channel in native mode */ |
| 391 | static int |
Chris Wilson | ea5b213 | 2010-08-04 13:50:23 +0100 | [diff] [blame] | 392 | intel_dp_aux_native_write(struct intel_dp *intel_dp, |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 393 | uint16_t address, uint8_t *send, int send_bytes) |
| 394 | { |
| 395 | int ret; |
| 396 | uint8_t msg[20]; |
| 397 | int msg_bytes; |
| 398 | uint8_t ack; |
| 399 | |
| 400 | if (send_bytes > 16) |
| 401 | return -1; |
| 402 | msg[0] = AUX_NATIVE_WRITE << 4; |
| 403 | msg[1] = address >> 8; |
Zhenyu Wang | eebc863 | 2009-07-24 01:00:30 +0800 | [diff] [blame] | 404 | msg[2] = address & 0xff; |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 405 | msg[3] = send_bytes - 1; |
| 406 | memcpy(&msg[4], send, send_bytes); |
| 407 | msg_bytes = send_bytes + 4; |
| 408 | for (;;) { |
Chris Wilson | ea5b213 | 2010-08-04 13:50:23 +0100 | [diff] [blame] | 409 | ret = intel_dp_aux_ch(intel_dp, msg, msg_bytes, &ack, 1); |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 410 | if (ret < 0) |
| 411 | return ret; |
| 412 | if ((ack & AUX_NATIVE_REPLY_MASK) == AUX_NATIVE_REPLY_ACK) |
| 413 | break; |
| 414 | else if ((ack & AUX_NATIVE_REPLY_MASK) == AUX_NATIVE_REPLY_DEFER) |
| 415 | udelay(100); |
| 416 | else |
Keith Packard | a5b3da5 | 2009-06-11 22:30:32 -0700 | [diff] [blame] | 417 | return -EIO; |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 418 | } |
| 419 | return send_bytes; |
| 420 | } |
| 421 | |
| 422 | /* Write a single byte to the aux channel in native mode */ |
| 423 | static int |
Chris Wilson | ea5b213 | 2010-08-04 13:50:23 +0100 | [diff] [blame] | 424 | intel_dp_aux_native_write_1(struct intel_dp *intel_dp, |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 425 | uint16_t address, uint8_t byte) |
| 426 | { |
Chris Wilson | ea5b213 | 2010-08-04 13:50:23 +0100 | [diff] [blame] | 427 | return intel_dp_aux_native_write(intel_dp, address, &byte, 1); |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 428 | } |
| 429 | |
| 430 | /* read bytes from a native aux channel */ |
| 431 | static int |
Chris Wilson | ea5b213 | 2010-08-04 13:50:23 +0100 | [diff] [blame] | 432 | intel_dp_aux_native_read(struct intel_dp *intel_dp, |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 433 | uint16_t address, uint8_t *recv, int recv_bytes) |
| 434 | { |
| 435 | uint8_t msg[4]; |
| 436 | int msg_bytes; |
| 437 | uint8_t reply[20]; |
| 438 | int reply_bytes; |
| 439 | uint8_t ack; |
| 440 | int ret; |
| 441 | |
| 442 | msg[0] = AUX_NATIVE_READ << 4; |
| 443 | msg[1] = address >> 8; |
| 444 | msg[2] = address & 0xff; |
| 445 | msg[3] = recv_bytes - 1; |
| 446 | |
| 447 | msg_bytes = 4; |
| 448 | reply_bytes = recv_bytes + 1; |
| 449 | |
| 450 | for (;;) { |
Chris Wilson | ea5b213 | 2010-08-04 13:50:23 +0100 | [diff] [blame] | 451 | ret = intel_dp_aux_ch(intel_dp, msg, msg_bytes, |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 452 | reply, reply_bytes); |
Keith Packard | a5b3da5 | 2009-06-11 22:30:32 -0700 | [diff] [blame] | 453 | if (ret == 0) |
| 454 | return -EPROTO; |
| 455 | if (ret < 0) |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 456 | return ret; |
| 457 | ack = reply[0]; |
| 458 | if ((ack & AUX_NATIVE_REPLY_MASK) == AUX_NATIVE_REPLY_ACK) { |
| 459 | memcpy(recv, reply + 1, ret - 1); |
| 460 | return ret - 1; |
| 461 | } |
| 462 | else if ((ack & AUX_NATIVE_REPLY_MASK) == AUX_NATIVE_REPLY_DEFER) |
| 463 | udelay(100); |
| 464 | else |
Keith Packard | a5b3da5 | 2009-06-11 22:30:32 -0700 | [diff] [blame] | 465 | return -EIO; |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 466 | } |
| 467 | } |
| 468 | |
| 469 | static int |
Dave Airlie | ab2c067 | 2009-12-04 10:55:24 +1000 | [diff] [blame] | 470 | intel_dp_i2c_aux_ch(struct i2c_adapter *adapter, int mode, |
| 471 | uint8_t write_byte, uint8_t *read_byte) |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 472 | { |
Dave Airlie | ab2c067 | 2009-12-04 10:55:24 +1000 | [diff] [blame] | 473 | struct i2c_algo_dp_aux_data *algo_data = adapter->algo_data; |
Chris Wilson | ea5b213 | 2010-08-04 13:50:23 +0100 | [diff] [blame] | 474 | struct intel_dp *intel_dp = container_of(adapter, |
| 475 | struct intel_dp, |
| 476 | adapter); |
Dave Airlie | ab2c067 | 2009-12-04 10:55:24 +1000 | [diff] [blame] | 477 | uint16_t address = algo_data->address; |
| 478 | uint8_t msg[5]; |
| 479 | uint8_t reply[2]; |
David Flynn | 8316f33 | 2010-12-08 16:10:21 +0000 | [diff] [blame] | 480 | unsigned retry; |
Dave Airlie | ab2c067 | 2009-12-04 10:55:24 +1000 | [diff] [blame] | 481 | int msg_bytes; |
| 482 | int reply_bytes; |
| 483 | int ret; |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 484 | |
Dave Airlie | ab2c067 | 2009-12-04 10:55:24 +1000 | [diff] [blame] | 485 | /* Set up the command byte */ |
| 486 | if (mode & MODE_I2C_READ) |
| 487 | msg[0] = AUX_I2C_READ << 4; |
| 488 | else |
| 489 | msg[0] = AUX_I2C_WRITE << 4; |
| 490 | |
| 491 | if (!(mode & MODE_I2C_STOP)) |
| 492 | msg[0] |= AUX_I2C_MOT << 4; |
| 493 | |
| 494 | msg[1] = address >> 8; |
| 495 | msg[2] = address; |
| 496 | |
| 497 | switch (mode) { |
| 498 | case MODE_I2C_WRITE: |
| 499 | msg[3] = 0; |
| 500 | msg[4] = write_byte; |
| 501 | msg_bytes = 5; |
| 502 | reply_bytes = 1; |
| 503 | break; |
| 504 | case MODE_I2C_READ: |
| 505 | msg[3] = 0; |
| 506 | msg_bytes = 4; |
| 507 | reply_bytes = 2; |
| 508 | break; |
| 509 | default: |
| 510 | msg_bytes = 3; |
| 511 | reply_bytes = 1; |
| 512 | break; |
| 513 | } |
| 514 | |
David Flynn | 8316f33 | 2010-12-08 16:10:21 +0000 | [diff] [blame] | 515 | for (retry = 0; retry < 5; retry++) { |
| 516 | ret = intel_dp_aux_ch(intel_dp, |
| 517 | msg, msg_bytes, |
| 518 | reply, reply_bytes); |
Dave Airlie | ab2c067 | 2009-12-04 10:55:24 +1000 | [diff] [blame] | 519 | if (ret < 0) { |
Dave Airlie | 3ff9916 | 2009-12-08 14:03:47 +1000 | [diff] [blame] | 520 | DRM_DEBUG_KMS("aux_ch failed %d\n", ret); |
Dave Airlie | ab2c067 | 2009-12-04 10:55:24 +1000 | [diff] [blame] | 521 | return ret; |
| 522 | } |
David Flynn | 8316f33 | 2010-12-08 16:10:21 +0000 | [diff] [blame] | 523 | |
| 524 | switch (reply[0] & AUX_NATIVE_REPLY_MASK) { |
| 525 | case AUX_NATIVE_REPLY_ACK: |
| 526 | /* I2C-over-AUX Reply field is only valid |
| 527 | * when paired with AUX ACK. |
| 528 | */ |
| 529 | break; |
| 530 | case AUX_NATIVE_REPLY_NACK: |
| 531 | DRM_DEBUG_KMS("aux_ch native nack\n"); |
| 532 | return -EREMOTEIO; |
| 533 | case AUX_NATIVE_REPLY_DEFER: |
| 534 | udelay(100); |
| 535 | continue; |
| 536 | default: |
| 537 | DRM_ERROR("aux_ch invalid native reply 0x%02x\n", |
| 538 | reply[0]); |
| 539 | return -EREMOTEIO; |
| 540 | } |
| 541 | |
Dave Airlie | ab2c067 | 2009-12-04 10:55:24 +1000 | [diff] [blame] | 542 | switch (reply[0] & AUX_I2C_REPLY_MASK) { |
| 543 | case AUX_I2C_REPLY_ACK: |
| 544 | if (mode == MODE_I2C_READ) { |
| 545 | *read_byte = reply[1]; |
| 546 | } |
| 547 | return reply_bytes - 1; |
| 548 | case AUX_I2C_REPLY_NACK: |
David Flynn | 8316f33 | 2010-12-08 16:10:21 +0000 | [diff] [blame] | 549 | DRM_DEBUG_KMS("aux_i2c nack\n"); |
Dave Airlie | ab2c067 | 2009-12-04 10:55:24 +1000 | [diff] [blame] | 550 | return -EREMOTEIO; |
| 551 | case AUX_I2C_REPLY_DEFER: |
David Flynn | 8316f33 | 2010-12-08 16:10:21 +0000 | [diff] [blame] | 552 | DRM_DEBUG_KMS("aux_i2c defer\n"); |
Dave Airlie | ab2c067 | 2009-12-04 10:55:24 +1000 | [diff] [blame] | 553 | udelay(100); |
| 554 | break; |
| 555 | default: |
David Flynn | 8316f33 | 2010-12-08 16:10:21 +0000 | [diff] [blame] | 556 | DRM_ERROR("aux_i2c invalid reply 0x%02x\n", reply[0]); |
Dave Airlie | ab2c067 | 2009-12-04 10:55:24 +1000 | [diff] [blame] | 557 | return -EREMOTEIO; |
| 558 | } |
| 559 | } |
David Flynn | 8316f33 | 2010-12-08 16:10:21 +0000 | [diff] [blame] | 560 | |
| 561 | DRM_ERROR("too many retries, giving up\n"); |
| 562 | return -EREMOTEIO; |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 563 | } |
| 564 | |
| 565 | static int |
Chris Wilson | ea5b213 | 2010-08-04 13:50:23 +0100 | [diff] [blame] | 566 | intel_dp_i2c_init(struct intel_dp *intel_dp, |
Zhenyu Wang | 55f78c4 | 2010-03-29 16:13:57 +0800 | [diff] [blame] | 567 | struct intel_connector *intel_connector, const char *name) |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 568 | { |
Zhenyu Wang | d54e9d2 | 2009-10-19 15:43:51 +0800 | [diff] [blame] | 569 | DRM_DEBUG_KMS("i2c_init %s\n", name); |
Chris Wilson | ea5b213 | 2010-08-04 13:50:23 +0100 | [diff] [blame] | 570 | intel_dp->algo.running = false; |
| 571 | intel_dp->algo.address = 0; |
| 572 | intel_dp->algo.aux_ch = intel_dp_i2c_aux_ch; |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 573 | |
Chris Wilson | ea5b213 | 2010-08-04 13:50:23 +0100 | [diff] [blame] | 574 | memset(&intel_dp->adapter, '\0', sizeof (intel_dp->adapter)); |
| 575 | intel_dp->adapter.owner = THIS_MODULE; |
| 576 | intel_dp->adapter.class = I2C_CLASS_DDC; |
| 577 | strncpy (intel_dp->adapter.name, name, sizeof(intel_dp->adapter.name) - 1); |
| 578 | intel_dp->adapter.name[sizeof(intel_dp->adapter.name) - 1] = '\0'; |
| 579 | intel_dp->adapter.algo_data = &intel_dp->algo; |
| 580 | intel_dp->adapter.dev.parent = &intel_connector->base.kdev; |
| 581 | |
| 582 | return i2c_dp_aux_add_bus(&intel_dp->adapter); |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 583 | } |
| 584 | |
| 585 | static bool |
| 586 | intel_dp_mode_fixup(struct drm_encoder *encoder, struct drm_display_mode *mode, |
| 587 | struct drm_display_mode *adjusted_mode) |
| 588 | { |
Zhao Yakui | 0d3a1be | 2010-07-19 09:43:13 +0100 | [diff] [blame] | 589 | struct drm_device *dev = encoder->dev; |
| 590 | struct drm_i915_private *dev_priv = dev->dev_private; |
Chris Wilson | ea5b213 | 2010-08-04 13:50:23 +0100 | [diff] [blame] | 591 | struct intel_dp *intel_dp = enc_to_intel_dp(encoder); |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 592 | int lane_count, clock; |
Chris Wilson | ea5b213 | 2010-08-04 13:50:23 +0100 | [diff] [blame] | 593 | int max_lane_count = intel_dp_max_lane_count(intel_dp); |
| 594 | int max_clock = intel_dp_max_link_bw(intel_dp) == DP_LINK_BW_2_7 ? 1 : 0; |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 595 | static int bws[2] = { DP_LINK_BW_1_62, DP_LINK_BW_2_7 }; |
| 596 | |
Jesse Barnes | 4d92646 | 2010-10-07 16:01:07 -0700 | [diff] [blame] | 597 | if (is_edp(intel_dp) && dev_priv->panel_fixed_mode) { |
Chris Wilson | 1d8e1c7 | 2010-08-07 11:01:28 +0100 | [diff] [blame] | 598 | intel_fixed_panel_mode(dev_priv->panel_fixed_mode, adjusted_mode); |
| 599 | intel_pch_panel_fitting(dev, DRM_MODE_SCALE_FULLSCREEN, |
| 600 | mode, adjusted_mode); |
Zhao Yakui | 0d3a1be | 2010-07-19 09:43:13 +0100 | [diff] [blame] | 601 | /* |
| 602 | * the mode->clock is used to calculate the Data&Link M/N |
| 603 | * of the pipe. For the eDP the fixed clock should be used. |
| 604 | */ |
| 605 | mode->clock = dev_priv->panel_fixed_mode->clock; |
| 606 | } |
| 607 | |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 608 | for (lane_count = 1; lane_count <= max_lane_count; lane_count <<= 1) { |
| 609 | for (clock = 0; clock <= max_clock; clock++) { |
Dave Airlie | fe27d53 | 2010-06-30 11:46:17 +1000 | [diff] [blame] | 610 | int link_avail = intel_dp_max_data_rate(intel_dp_link_clock(bws[clock]), lane_count); |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 611 | |
Chris Wilson | ea5b213 | 2010-08-04 13:50:23 +0100 | [diff] [blame] | 612 | if (intel_dp_link_required(encoder->dev, intel_dp, mode->clock) |
Zhenyu Wang | 885a5fb | 2010-01-12 05:38:31 +0800 | [diff] [blame] | 613 | <= link_avail) { |
Chris Wilson | ea5b213 | 2010-08-04 13:50:23 +0100 | [diff] [blame] | 614 | intel_dp->link_bw = bws[clock]; |
| 615 | intel_dp->lane_count = lane_count; |
| 616 | adjusted_mode->clock = intel_dp_link_clock(intel_dp->link_bw); |
Zhao Yakui | 28c9773 | 2009-10-09 11:39:41 +0800 | [diff] [blame] | 617 | DRM_DEBUG_KMS("Display port link bw %02x lane " |
| 618 | "count %d clock %d\n", |
Chris Wilson | ea5b213 | 2010-08-04 13:50:23 +0100 | [diff] [blame] | 619 | intel_dp->link_bw, intel_dp->lane_count, |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 620 | adjusted_mode->clock); |
| 621 | return true; |
| 622 | } |
| 623 | } |
| 624 | } |
Dave Airlie | fe27d53 | 2010-06-30 11:46:17 +1000 | [diff] [blame] | 625 | |
Chris Wilson | 3cf2efb | 2010-11-29 10:09:55 +0000 | [diff] [blame] | 626 | if (is_edp(intel_dp)) { |
| 627 | /* okay we failed just pick the highest */ |
| 628 | intel_dp->lane_count = max_lane_count; |
| 629 | intel_dp->link_bw = bws[max_clock]; |
| 630 | adjusted_mode->clock = intel_dp_link_clock(intel_dp->link_bw); |
| 631 | DRM_DEBUG_KMS("Force picking display port link bw %02x lane " |
| 632 | "count %d clock %d\n", |
| 633 | intel_dp->link_bw, intel_dp->lane_count, |
| 634 | adjusted_mode->clock); |
| 635 | |
| 636 | return true; |
| 637 | } |
| 638 | |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 639 | return false; |
| 640 | } |
| 641 | |
| 642 | struct intel_dp_m_n { |
| 643 | uint32_t tu; |
| 644 | uint32_t gmch_m; |
| 645 | uint32_t gmch_n; |
| 646 | uint32_t link_m; |
| 647 | uint32_t link_n; |
| 648 | }; |
| 649 | |
| 650 | static void |
| 651 | intel_reduce_ratio(uint32_t *num, uint32_t *den) |
| 652 | { |
| 653 | while (*num > 0xffffff || *den > 0xffffff) { |
| 654 | *num >>= 1; |
| 655 | *den >>= 1; |
| 656 | } |
| 657 | } |
| 658 | |
| 659 | static void |
Zhao Yakui | 36e83a1 | 2010-06-12 14:32:21 +0800 | [diff] [blame] | 660 | intel_dp_compute_m_n(int bpp, |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 661 | int nlanes, |
| 662 | int pixel_clock, |
| 663 | int link_clock, |
| 664 | struct intel_dp_m_n *m_n) |
| 665 | { |
| 666 | m_n->tu = 64; |
Zhao Yakui | 36e83a1 | 2010-06-12 14:32:21 +0800 | [diff] [blame] | 667 | m_n->gmch_m = (pixel_clock * bpp) >> 3; |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 668 | m_n->gmch_n = link_clock * nlanes; |
| 669 | intel_reduce_ratio(&m_n->gmch_m, &m_n->gmch_n); |
| 670 | m_n->link_m = pixel_clock; |
| 671 | m_n->link_n = link_clock; |
| 672 | intel_reduce_ratio(&m_n->link_m, &m_n->link_n); |
| 673 | } |
| 674 | |
| 675 | void |
| 676 | intel_dp_set_m_n(struct drm_crtc *crtc, struct drm_display_mode *mode, |
| 677 | struct drm_display_mode *adjusted_mode) |
| 678 | { |
| 679 | struct drm_device *dev = crtc->dev; |
| 680 | struct drm_mode_config *mode_config = &dev->mode_config; |
Zhenyu Wang | 55f78c4 | 2010-03-29 16:13:57 +0800 | [diff] [blame] | 681 | struct drm_encoder *encoder; |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 682 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 683 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
Zhao Yakui | 36e83a1 | 2010-06-12 14:32:21 +0800 | [diff] [blame] | 684 | int lane_count = 4, bpp = 24; |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 685 | struct intel_dp_m_n m_n; |
Jesse Barnes | 9db4a9c | 2011-02-07 12:26:52 -0800 | [diff] [blame] | 686 | int pipe = intel_crtc->pipe; |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 687 | |
| 688 | /* |
Eric Anholt | 21d40d3 | 2010-03-25 11:11:14 -0700 | [diff] [blame] | 689 | * Find the lane count in the intel_encoder private |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 690 | */ |
Zhenyu Wang | 55f78c4 | 2010-03-29 16:13:57 +0800 | [diff] [blame] | 691 | list_for_each_entry(encoder, &mode_config->encoder_list, head) { |
Chris Wilson | ea5b213 | 2010-08-04 13:50:23 +0100 | [diff] [blame] | 692 | struct intel_dp *intel_dp; |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 693 | |
Dan Carpenter | d8201ab | 2010-05-07 10:39:00 +0200 | [diff] [blame] | 694 | if (encoder->crtc != crtc) |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 695 | continue; |
| 696 | |
Chris Wilson | ea5b213 | 2010-08-04 13:50:23 +0100 | [diff] [blame] | 697 | intel_dp = enc_to_intel_dp(encoder); |
| 698 | if (intel_dp->base.type == INTEL_OUTPUT_DISPLAYPORT) { |
| 699 | lane_count = intel_dp->lane_count; |
Jesse Barnes | 5119066 | 2010-10-07 16:01:08 -0700 | [diff] [blame] | 700 | break; |
| 701 | } else if (is_edp(intel_dp)) { |
| 702 | lane_count = dev_priv->edp.lanes; |
| 703 | bpp = dev_priv->edp.bpp; |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 704 | break; |
| 705 | } |
| 706 | } |
| 707 | |
| 708 | /* |
| 709 | * Compute the GMCH and Link ratios. The '3' here is |
| 710 | * the number of bytes_per_pixel post-LUT, which we always |
| 711 | * set up for 8-bits of R/G/B, or 3 bytes total. |
| 712 | */ |
Zhao Yakui | 36e83a1 | 2010-06-12 14:32:21 +0800 | [diff] [blame] | 713 | intel_dp_compute_m_n(bpp, lane_count, |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 714 | mode->clock, adjusted_mode->clock, &m_n); |
| 715 | |
Eric Anholt | c619eed | 2010-01-28 16:45:52 -0800 | [diff] [blame] | 716 | if (HAS_PCH_SPLIT(dev)) { |
Jesse Barnes | 9db4a9c | 2011-02-07 12:26:52 -0800 | [diff] [blame] | 717 | I915_WRITE(TRANSDATA_M1(pipe), |
| 718 | ((m_n.tu - 1) << PIPE_GMCH_DATA_M_TU_SIZE_SHIFT) | |
| 719 | m_n.gmch_m); |
| 720 | I915_WRITE(TRANSDATA_N1(pipe), m_n.gmch_n); |
| 721 | I915_WRITE(TRANSDPLINK_M1(pipe), m_n.link_m); |
| 722 | I915_WRITE(TRANSDPLINK_N1(pipe), m_n.link_n); |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 723 | } else { |
Jesse Barnes | 9db4a9c | 2011-02-07 12:26:52 -0800 | [diff] [blame] | 724 | I915_WRITE(PIPE_GMCH_DATA_M(pipe), |
| 725 | ((m_n.tu - 1) << PIPE_GMCH_DATA_M_TU_SIZE_SHIFT) | |
| 726 | m_n.gmch_m); |
| 727 | I915_WRITE(PIPE_GMCH_DATA_N(pipe), m_n.gmch_n); |
| 728 | I915_WRITE(PIPE_DP_LINK_M(pipe), m_n.link_m); |
| 729 | I915_WRITE(PIPE_DP_LINK_N(pipe), m_n.link_n); |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 730 | } |
| 731 | } |
| 732 | |
| 733 | static void |
| 734 | intel_dp_mode_set(struct drm_encoder *encoder, struct drm_display_mode *mode, |
| 735 | struct drm_display_mode *adjusted_mode) |
| 736 | { |
Zhenyu Wang | e3421a1 | 2010-04-08 09:43:27 +0800 | [diff] [blame] | 737 | struct drm_device *dev = encoder->dev; |
Chris Wilson | ea5b213 | 2010-08-04 13:50:23 +0100 | [diff] [blame] | 738 | struct intel_dp *intel_dp = enc_to_intel_dp(encoder); |
Chris Wilson | 4ef69c7 | 2010-09-09 15:14:28 +0100 | [diff] [blame] | 739 | struct drm_crtc *crtc = intel_dp->base.base.crtc; |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 740 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
| 741 | |
Chris Wilson | e953fd7 | 2011-02-21 22:23:52 +0000 | [diff] [blame] | 742 | intel_dp->DP = DP_VOLTAGE_0_4 | DP_PRE_EMPHASIS_0; |
| 743 | intel_dp->DP |= intel_dp->color_range; |
Adam Jackson | 9c9e792 | 2010-04-05 17:57:59 -0400 | [diff] [blame] | 744 | |
| 745 | if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC) |
Chris Wilson | ea5b213 | 2010-08-04 13:50:23 +0100 | [diff] [blame] | 746 | intel_dp->DP |= DP_SYNC_HS_HIGH; |
Adam Jackson | 9c9e792 | 2010-04-05 17:57:59 -0400 | [diff] [blame] | 747 | if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC) |
Chris Wilson | ea5b213 | 2010-08-04 13:50:23 +0100 | [diff] [blame] | 748 | intel_dp->DP |= DP_SYNC_VS_HIGH; |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 749 | |
Jesse Barnes | cfcb0fc | 2010-10-07 16:01:06 -0700 | [diff] [blame] | 750 | if (HAS_PCH_CPT(dev) && !is_edp(intel_dp)) |
Chris Wilson | ea5b213 | 2010-08-04 13:50:23 +0100 | [diff] [blame] | 751 | intel_dp->DP |= DP_LINK_TRAIN_OFF_CPT; |
Zhenyu Wang | e3421a1 | 2010-04-08 09:43:27 +0800 | [diff] [blame] | 752 | else |
Chris Wilson | ea5b213 | 2010-08-04 13:50:23 +0100 | [diff] [blame] | 753 | intel_dp->DP |= DP_LINK_TRAIN_OFF; |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 754 | |
Chris Wilson | ea5b213 | 2010-08-04 13:50:23 +0100 | [diff] [blame] | 755 | switch (intel_dp->lane_count) { |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 756 | case 1: |
Chris Wilson | ea5b213 | 2010-08-04 13:50:23 +0100 | [diff] [blame] | 757 | intel_dp->DP |= DP_PORT_WIDTH_1; |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 758 | break; |
| 759 | case 2: |
Chris Wilson | ea5b213 | 2010-08-04 13:50:23 +0100 | [diff] [blame] | 760 | intel_dp->DP |= DP_PORT_WIDTH_2; |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 761 | break; |
| 762 | case 4: |
Chris Wilson | ea5b213 | 2010-08-04 13:50:23 +0100 | [diff] [blame] | 763 | intel_dp->DP |= DP_PORT_WIDTH_4; |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 764 | break; |
| 765 | } |
Chris Wilson | ea5b213 | 2010-08-04 13:50:23 +0100 | [diff] [blame] | 766 | if (intel_dp->has_audio) |
| 767 | intel_dp->DP |= DP_AUDIO_OUTPUT_ENABLE; |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 768 | |
Chris Wilson | ea5b213 | 2010-08-04 13:50:23 +0100 | [diff] [blame] | 769 | memset(intel_dp->link_configuration, 0, DP_LINK_CONFIGURATION_SIZE); |
| 770 | intel_dp->link_configuration[0] = intel_dp->link_bw; |
| 771 | intel_dp->link_configuration[1] = intel_dp->lane_count; |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 772 | |
| 773 | /* |
Adam Jackson | 9962c92 | 2010-05-13 14:45:42 -0400 | [diff] [blame] | 774 | * Check for DPCD version > 1.1 and enhanced framing support |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 775 | */ |
Jesse Barnes | 7183dc2 | 2011-07-07 11:10:58 -0700 | [diff] [blame] | 776 | if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11 && |
| 777 | (intel_dp->dpcd[DP_MAX_LANE_COUNT] & DP_ENHANCED_FRAME_CAP)) { |
Chris Wilson | ea5b213 | 2010-08-04 13:50:23 +0100 | [diff] [blame] | 778 | intel_dp->link_configuration[1] |= DP_LANE_COUNT_ENHANCED_FRAME_EN; |
| 779 | intel_dp->DP |= DP_ENHANCED_FRAMING; |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 780 | } |
| 781 | |
Zhenyu Wang | e3421a1 | 2010-04-08 09:43:27 +0800 | [diff] [blame] | 782 | /* CPT DP's pipe select is decided in TRANS_DP_CTL */ |
| 783 | if (intel_crtc->pipe == 1 && !HAS_PCH_CPT(dev)) |
Chris Wilson | ea5b213 | 2010-08-04 13:50:23 +0100 | [diff] [blame] | 784 | intel_dp->DP |= DP_PIPEB_SELECT; |
Zhenyu Wang | 32f9d65 | 2009-07-24 01:00:32 +0800 | [diff] [blame] | 785 | |
Jesse Barnes | 895692b | 2010-10-07 16:01:23 -0700 | [diff] [blame] | 786 | if (is_edp(intel_dp) && !is_pch_edp(intel_dp)) { |
Zhenyu Wang | 32f9d65 | 2009-07-24 01:00:32 +0800 | [diff] [blame] | 787 | /* don't miss out required setting for eDP */ |
Chris Wilson | ea5b213 | 2010-08-04 13:50:23 +0100 | [diff] [blame] | 788 | intel_dp->DP |= DP_PLL_ENABLE; |
Zhenyu Wang | 32f9d65 | 2009-07-24 01:00:32 +0800 | [diff] [blame] | 789 | if (adjusted_mode->clock < 200000) |
Chris Wilson | ea5b213 | 2010-08-04 13:50:23 +0100 | [diff] [blame] | 790 | intel_dp->DP |= DP_PLL_FREQ_160MHZ; |
Zhenyu Wang | 32f9d65 | 2009-07-24 01:00:32 +0800 | [diff] [blame] | 791 | else |
Chris Wilson | ea5b213 | 2010-08-04 13:50:23 +0100 | [diff] [blame] | 792 | intel_dp->DP |= DP_PLL_FREQ_270MHZ; |
Zhenyu Wang | 32f9d65 | 2009-07-24 01:00:32 +0800 | [diff] [blame] | 793 | } |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 794 | } |
| 795 | |
Jesse Barnes | 5d61350 | 2011-01-24 17:10:54 -0800 | [diff] [blame] | 796 | static void ironlake_edp_panel_vdd_on(struct intel_dp *intel_dp) |
| 797 | { |
| 798 | struct drm_device *dev = intel_dp->base.base.dev; |
| 799 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 800 | u32 pp; |
| 801 | |
| 802 | /* |
| 803 | * If the panel wasn't on, make sure there's not a currently |
| 804 | * active PP sequence before enabling AUX VDD. |
| 805 | */ |
| 806 | if (!(I915_READ(PCH_PP_STATUS) & PP_ON)) |
| 807 | msleep(dev_priv->panel_t3); |
| 808 | |
| 809 | pp = I915_READ(PCH_PP_CONTROL); |
| 810 | pp |= EDP_FORCE_VDD; |
| 811 | I915_WRITE(PCH_PP_CONTROL, pp); |
| 812 | POSTING_READ(PCH_PP_CONTROL); |
| 813 | } |
| 814 | |
| 815 | static void ironlake_edp_panel_vdd_off(struct intel_dp *intel_dp) |
| 816 | { |
| 817 | struct drm_device *dev = intel_dp->base.base.dev; |
| 818 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 819 | u32 pp; |
| 820 | |
| 821 | pp = I915_READ(PCH_PP_CONTROL); |
| 822 | pp &= ~EDP_FORCE_VDD; |
| 823 | I915_WRITE(PCH_PP_CONTROL, pp); |
| 824 | POSTING_READ(PCH_PP_CONTROL); |
| 825 | |
| 826 | /* Make sure sequencer is idle before allowing subsequent activity */ |
| 827 | msleep(dev_priv->panel_t12); |
| 828 | } |
| 829 | |
Jesse Barnes | 7eaf554 | 2010-09-08 12:41:59 -0700 | [diff] [blame] | 830 | /* Returns true if the panel was already on when called */ |
Jesse Barnes | 01cb9ea | 2010-10-07 16:01:12 -0700 | [diff] [blame] | 831 | static bool ironlake_edp_panel_on (struct intel_dp *intel_dp) |
Jesse Barnes | 9934c13 | 2010-07-22 13:18:19 -0700 | [diff] [blame] | 832 | { |
Jesse Barnes | 01cb9ea | 2010-10-07 16:01:12 -0700 | [diff] [blame] | 833 | struct drm_device *dev = intel_dp->base.base.dev; |
Jesse Barnes | 9934c13 | 2010-07-22 13:18:19 -0700 | [diff] [blame] | 834 | struct drm_i915_private *dev_priv = dev->dev_private; |
Jesse Barnes | 01cb9ea | 2010-10-07 16:01:12 -0700 | [diff] [blame] | 835 | u32 pp, idle_on_mask = PP_ON | PP_SEQUENCE_STATE_ON_IDLE; |
Jesse Barnes | 9934c13 | 2010-07-22 13:18:19 -0700 | [diff] [blame] | 836 | |
Chris Wilson | 913d8d1 | 2010-08-07 11:01:35 +0100 | [diff] [blame] | 837 | if (I915_READ(PCH_PP_STATUS) & PP_ON) |
Jesse Barnes | 7eaf554 | 2010-09-08 12:41:59 -0700 | [diff] [blame] | 838 | return true; |
Jesse Barnes | 9934c13 | 2010-07-22 13:18:19 -0700 | [diff] [blame] | 839 | |
| 840 | pp = I915_READ(PCH_PP_CONTROL); |
Jesse Barnes | 37c6c9b | 2010-08-11 10:04:43 -0700 | [diff] [blame] | 841 | |
| 842 | /* ILK workaround: disable reset around power sequence */ |
| 843 | pp &= ~PANEL_POWER_RESET; |
| 844 | I915_WRITE(PCH_PP_CONTROL, pp); |
| 845 | POSTING_READ(PCH_PP_CONTROL); |
| 846 | |
Jesse Barnes | 01cb9ea | 2010-10-07 16:01:12 -0700 | [diff] [blame] | 847 | pp |= PANEL_UNLOCK_REGS | POWER_TARGET_ON; |
Jesse Barnes | 9934c13 | 2010-07-22 13:18:19 -0700 | [diff] [blame] | 848 | I915_WRITE(PCH_PP_CONTROL, pp); |
Jesse Barnes | 01cb9ea | 2010-10-07 16:01:12 -0700 | [diff] [blame] | 849 | POSTING_READ(PCH_PP_CONTROL); |
Jesse Barnes | 9934c13 | 2010-07-22 13:18:19 -0700 | [diff] [blame] | 850 | |
Jesse Barnes | 01cb9ea | 2010-10-07 16:01:12 -0700 | [diff] [blame] | 851 | if (wait_for((I915_READ(PCH_PP_STATUS) & idle_on_mask) == idle_on_mask, |
| 852 | 5000)) |
Chris Wilson | 913d8d1 | 2010-08-07 11:01:35 +0100 | [diff] [blame] | 853 | DRM_ERROR("panel on wait timed out: 0x%08x\n", |
| 854 | I915_READ(PCH_PP_STATUS)); |
Jesse Barnes | 9934c13 | 2010-07-22 13:18:19 -0700 | [diff] [blame] | 855 | |
Jesse Barnes | 37c6c9b | 2010-08-11 10:04:43 -0700 | [diff] [blame] | 856 | pp |= PANEL_POWER_RESET; /* restore panel reset bit */ |
Jesse Barnes | 9934c13 | 2010-07-22 13:18:19 -0700 | [diff] [blame] | 857 | I915_WRITE(PCH_PP_CONTROL, pp); |
Jesse Barnes | 37c6c9b | 2010-08-11 10:04:43 -0700 | [diff] [blame] | 858 | POSTING_READ(PCH_PP_CONTROL); |
Jesse Barnes | 7eaf554 | 2010-09-08 12:41:59 -0700 | [diff] [blame] | 859 | |
| 860 | return false; |
Jesse Barnes | 9934c13 | 2010-07-22 13:18:19 -0700 | [diff] [blame] | 861 | } |
| 862 | |
| 863 | static void ironlake_edp_panel_off (struct drm_device *dev) |
| 864 | { |
| 865 | struct drm_i915_private *dev_priv = dev->dev_private; |
Jesse Barnes | 01cb9ea | 2010-10-07 16:01:12 -0700 | [diff] [blame] | 866 | u32 pp, idle_off_mask = PP_ON | PP_SEQUENCE_MASK | |
| 867 | PP_CYCLE_DELAY_ACTIVE | PP_SEQUENCE_STATE_MASK; |
Jesse Barnes | 9934c13 | 2010-07-22 13:18:19 -0700 | [diff] [blame] | 868 | |
| 869 | pp = I915_READ(PCH_PP_CONTROL); |
Jesse Barnes | 37c6c9b | 2010-08-11 10:04:43 -0700 | [diff] [blame] | 870 | |
| 871 | /* ILK workaround: disable reset around power sequence */ |
| 872 | pp &= ~PANEL_POWER_RESET; |
| 873 | I915_WRITE(PCH_PP_CONTROL, pp); |
| 874 | POSTING_READ(PCH_PP_CONTROL); |
| 875 | |
Jesse Barnes | 9934c13 | 2010-07-22 13:18:19 -0700 | [diff] [blame] | 876 | pp &= ~POWER_TARGET_ON; |
| 877 | I915_WRITE(PCH_PP_CONTROL, pp); |
Jesse Barnes | 01cb9ea | 2010-10-07 16:01:12 -0700 | [diff] [blame] | 878 | POSTING_READ(PCH_PP_CONTROL); |
Jesse Barnes | 9934c13 | 2010-07-22 13:18:19 -0700 | [diff] [blame] | 879 | |
Jesse Barnes | 01cb9ea | 2010-10-07 16:01:12 -0700 | [diff] [blame] | 880 | if (wait_for((I915_READ(PCH_PP_STATUS) & idle_off_mask) == 0, 5000)) |
Chris Wilson | 913d8d1 | 2010-08-07 11:01:35 +0100 | [diff] [blame] | 881 | DRM_ERROR("panel off wait timed out: 0x%08x\n", |
| 882 | I915_READ(PCH_PP_STATUS)); |
Jesse Barnes | 9934c13 | 2010-07-22 13:18:19 -0700 | [diff] [blame] | 883 | |
Jesse Barnes | 3969c9c9 | 2010-09-08 12:42:03 -0700 | [diff] [blame] | 884 | pp |= PANEL_POWER_RESET; /* restore panel reset bit */ |
Jesse Barnes | 9934c13 | 2010-07-22 13:18:19 -0700 | [diff] [blame] | 885 | I915_WRITE(PCH_PP_CONTROL, pp); |
Jesse Barnes | 37c6c9b | 2010-08-11 10:04:43 -0700 | [diff] [blame] | 886 | POSTING_READ(PCH_PP_CONTROL); |
Jesse Barnes | 9934c13 | 2010-07-22 13:18:19 -0700 | [diff] [blame] | 887 | } |
| 888 | |
Adam Jackson | f2b115e | 2009-12-03 17:14:42 -0500 | [diff] [blame] | 889 | static void ironlake_edp_backlight_on (struct drm_device *dev) |
Zhenyu Wang | 32f9d65 | 2009-07-24 01:00:32 +0800 | [diff] [blame] | 890 | { |
| 891 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 892 | u32 pp; |
| 893 | |
Zhao Yakui | 28c9773 | 2009-10-09 11:39:41 +0800 | [diff] [blame] | 894 | DRM_DEBUG_KMS("\n"); |
Jesse Barnes | 01cb9ea | 2010-10-07 16:01:12 -0700 | [diff] [blame] | 895 | /* |
| 896 | * If we enable the backlight right away following a panel power |
| 897 | * on, we may see slight flicker as the panel syncs with the eDP |
| 898 | * link. So delay a bit to make sure the image is solid before |
| 899 | * allowing it to appear. |
| 900 | */ |
| 901 | msleep(300); |
Zhenyu Wang | 32f9d65 | 2009-07-24 01:00:32 +0800 | [diff] [blame] | 902 | pp = I915_READ(PCH_PP_CONTROL); |
| 903 | pp |= EDP_BLC_ENABLE; |
| 904 | I915_WRITE(PCH_PP_CONTROL, pp); |
| 905 | } |
| 906 | |
Adam Jackson | f2b115e | 2009-12-03 17:14:42 -0500 | [diff] [blame] | 907 | static void ironlake_edp_backlight_off (struct drm_device *dev) |
Zhenyu Wang | 32f9d65 | 2009-07-24 01:00:32 +0800 | [diff] [blame] | 908 | { |
| 909 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 910 | u32 pp; |
| 911 | |
Zhao Yakui | 28c9773 | 2009-10-09 11:39:41 +0800 | [diff] [blame] | 912 | DRM_DEBUG_KMS("\n"); |
Zhenyu Wang | 32f9d65 | 2009-07-24 01:00:32 +0800 | [diff] [blame] | 913 | pp = I915_READ(PCH_PP_CONTROL); |
| 914 | pp &= ~EDP_BLC_ENABLE; |
| 915 | I915_WRITE(PCH_PP_CONTROL, pp); |
| 916 | } |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 917 | |
Jesse Barnes | d240f20 | 2010-08-13 15:43:26 -0700 | [diff] [blame] | 918 | static void ironlake_edp_pll_on(struct drm_encoder *encoder) |
| 919 | { |
| 920 | struct drm_device *dev = encoder->dev; |
| 921 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 922 | u32 dpa_ctl; |
| 923 | |
| 924 | DRM_DEBUG_KMS("\n"); |
| 925 | dpa_ctl = I915_READ(DP_A); |
Jesse Barnes | 298b0b3 | 2010-10-07 16:01:24 -0700 | [diff] [blame] | 926 | dpa_ctl |= DP_PLL_ENABLE; |
Jesse Barnes | d240f20 | 2010-08-13 15:43:26 -0700 | [diff] [blame] | 927 | I915_WRITE(DP_A, dpa_ctl); |
Jesse Barnes | 298b0b3 | 2010-10-07 16:01:24 -0700 | [diff] [blame] | 928 | POSTING_READ(DP_A); |
| 929 | udelay(200); |
Jesse Barnes | d240f20 | 2010-08-13 15:43:26 -0700 | [diff] [blame] | 930 | } |
| 931 | |
| 932 | static void ironlake_edp_pll_off(struct drm_encoder *encoder) |
| 933 | { |
| 934 | struct drm_device *dev = encoder->dev; |
| 935 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 936 | u32 dpa_ctl; |
| 937 | |
| 938 | dpa_ctl = I915_READ(DP_A); |
Jesse Barnes | 298b0b3 | 2010-10-07 16:01:24 -0700 | [diff] [blame] | 939 | dpa_ctl &= ~DP_PLL_ENABLE; |
Jesse Barnes | d240f20 | 2010-08-13 15:43:26 -0700 | [diff] [blame] | 940 | I915_WRITE(DP_A, dpa_ctl); |
Chris Wilson | 1af5fa1 | 2010-09-08 21:07:28 +0100 | [diff] [blame] | 941 | POSTING_READ(DP_A); |
Jesse Barnes | d240f20 | 2010-08-13 15:43:26 -0700 | [diff] [blame] | 942 | udelay(200); |
| 943 | } |
| 944 | |
Jesse Barnes | c7ad381 | 2011-07-07 11:11:03 -0700 | [diff] [blame] | 945 | /* If the sink supports it, try to set the power state appropriately */ |
| 946 | static void intel_dp_sink_dpms(struct intel_dp *intel_dp, int mode) |
| 947 | { |
| 948 | int ret, i; |
| 949 | |
| 950 | /* Should have a valid DPCD by this point */ |
| 951 | if (intel_dp->dpcd[DP_DPCD_REV] < 0x11) |
| 952 | return; |
| 953 | |
| 954 | if (mode != DRM_MODE_DPMS_ON) { |
| 955 | ret = intel_dp_aux_native_write_1(intel_dp, DP_SET_POWER, |
| 956 | DP_SET_POWER_D3); |
| 957 | if (ret != 1) |
| 958 | DRM_DEBUG_DRIVER("failed to write sink power state\n"); |
| 959 | } else { |
| 960 | /* |
| 961 | * When turning on, we need to retry for 1ms to give the sink |
| 962 | * time to wake up. |
| 963 | */ |
| 964 | for (i = 0; i < 3; i++) { |
| 965 | ret = intel_dp_aux_native_write_1(intel_dp, |
| 966 | DP_SET_POWER, |
| 967 | DP_SET_POWER_D0); |
| 968 | if (ret == 1) |
| 969 | break; |
| 970 | msleep(1); |
| 971 | } |
| 972 | } |
| 973 | } |
| 974 | |
Jesse Barnes | d240f20 | 2010-08-13 15:43:26 -0700 | [diff] [blame] | 975 | static void intel_dp_prepare(struct drm_encoder *encoder) |
| 976 | { |
| 977 | struct intel_dp *intel_dp = enc_to_intel_dp(encoder); |
| 978 | struct drm_device *dev = encoder->dev; |
Jesse Barnes | d240f20 | 2010-08-13 15:43:26 -0700 | [diff] [blame] | 979 | |
Jesse Barnes | c7ad381 | 2011-07-07 11:11:03 -0700 | [diff] [blame] | 980 | /* Wake up the sink first */ |
| 981 | intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_ON); |
| 982 | |
Jesse Barnes | 4d92646 | 2010-10-07 16:01:07 -0700 | [diff] [blame] | 983 | if (is_edp(intel_dp)) { |
Jesse Barnes | d240f20 | 2010-08-13 15:43:26 -0700 | [diff] [blame] | 984 | ironlake_edp_backlight_off(dev); |
Jesse Barnes | 5d61350 | 2011-01-24 17:10:54 -0800 | [diff] [blame] | 985 | ironlake_edp_panel_off(dev); |
Jesse Barnes | 01cb9ea | 2010-10-07 16:01:12 -0700 | [diff] [blame] | 986 | if (!is_pch_edp(intel_dp)) |
| 987 | ironlake_edp_pll_on(encoder); |
| 988 | else |
| 989 | ironlake_edp_pll_off(encoder); |
Jesse Barnes | d240f20 | 2010-08-13 15:43:26 -0700 | [diff] [blame] | 990 | } |
Jesse Barnes | 736085b | 2010-10-08 10:35:55 -0700 | [diff] [blame] | 991 | intel_dp_link_down(intel_dp); |
Jesse Barnes | d240f20 | 2010-08-13 15:43:26 -0700 | [diff] [blame] | 992 | } |
| 993 | |
| 994 | static void intel_dp_commit(struct drm_encoder *encoder) |
| 995 | { |
| 996 | struct intel_dp *intel_dp = enc_to_intel_dp(encoder); |
| 997 | struct drm_device *dev = encoder->dev; |
Jesse Barnes | d240f20 | 2010-08-13 15:43:26 -0700 | [diff] [blame] | 998 | |
Jesse Barnes | 5d61350 | 2011-01-24 17:10:54 -0800 | [diff] [blame] | 999 | if (is_edp(intel_dp)) |
| 1000 | ironlake_edp_panel_vdd_on(intel_dp); |
| 1001 | |
Jesse Barnes | 33a34e4 | 2010-09-08 12:42:02 -0700 | [diff] [blame] | 1002 | intel_dp_start_link_train(intel_dp); |
| 1003 | |
Jesse Barnes | 5d61350 | 2011-01-24 17:10:54 -0800 | [diff] [blame] | 1004 | if (is_edp(intel_dp)) { |
Jesse Barnes | 01cb9ea | 2010-10-07 16:01:12 -0700 | [diff] [blame] | 1005 | ironlake_edp_panel_on(intel_dp); |
Jesse Barnes | 5d61350 | 2011-01-24 17:10:54 -0800 | [diff] [blame] | 1006 | ironlake_edp_panel_vdd_off(intel_dp); |
| 1007 | } |
Jesse Barnes | 33a34e4 | 2010-09-08 12:42:02 -0700 | [diff] [blame] | 1008 | |
| 1009 | intel_dp_complete_link_train(intel_dp); |
| 1010 | |
Jesse Barnes | 4d92646 | 2010-10-07 16:01:07 -0700 | [diff] [blame] | 1011 | if (is_edp(intel_dp)) |
Jesse Barnes | d240f20 | 2010-08-13 15:43:26 -0700 | [diff] [blame] | 1012 | ironlake_edp_backlight_on(dev); |
| 1013 | } |
| 1014 | |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 1015 | static void |
| 1016 | intel_dp_dpms(struct drm_encoder *encoder, int mode) |
| 1017 | { |
Chris Wilson | ea5b213 | 2010-08-04 13:50:23 +0100 | [diff] [blame] | 1018 | struct intel_dp *intel_dp = enc_to_intel_dp(encoder); |
Zhenyu Wang | 55f78c4 | 2010-03-29 16:13:57 +0800 | [diff] [blame] | 1019 | struct drm_device *dev = encoder->dev; |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 1020 | struct drm_i915_private *dev_priv = dev->dev_private; |
Chris Wilson | ea5b213 | 2010-08-04 13:50:23 +0100 | [diff] [blame] | 1021 | uint32_t dp_reg = I915_READ(intel_dp->output_reg); |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 1022 | |
| 1023 | if (mode != DRM_MODE_DPMS_ON) { |
Jesse Barnes | 01cb9ea | 2010-10-07 16:01:12 -0700 | [diff] [blame] | 1024 | if (is_edp(intel_dp)) |
Jesse Barnes | 7643a7f | 2010-08-11 10:06:44 -0700 | [diff] [blame] | 1025 | ironlake_edp_backlight_off(dev); |
Jesse Barnes | c7ad381 | 2011-07-07 11:11:03 -0700 | [diff] [blame] | 1026 | intel_dp_sink_dpms(intel_dp, mode); |
Jesse Barnes | 736085b | 2010-10-08 10:35:55 -0700 | [diff] [blame] | 1027 | intel_dp_link_down(intel_dp); |
Jesse Barnes | 4d92646 | 2010-10-07 16:01:07 -0700 | [diff] [blame] | 1028 | if (is_edp(intel_dp)) |
Jesse Barnes | 01cb9ea | 2010-10-07 16:01:12 -0700 | [diff] [blame] | 1029 | ironlake_edp_panel_off(dev); |
| 1030 | if (is_edp(intel_dp) && !is_pch_edp(intel_dp)) |
Jesse Barnes | d240f20 | 2010-08-13 15:43:26 -0700 | [diff] [blame] | 1031 | ironlake_edp_pll_off(encoder); |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 1032 | } else { |
Jesse Barnes | 736085b | 2010-10-08 10:35:55 -0700 | [diff] [blame] | 1033 | if (is_edp(intel_dp)) |
Jesse Barnes | 5d61350 | 2011-01-24 17:10:54 -0800 | [diff] [blame] | 1034 | ironlake_edp_panel_vdd_on(intel_dp); |
Jesse Barnes | c7ad381 | 2011-07-07 11:11:03 -0700 | [diff] [blame] | 1035 | intel_dp_sink_dpms(intel_dp, mode); |
Zhenyu Wang | 32f9d65 | 2009-07-24 01:00:32 +0800 | [diff] [blame] | 1036 | if (!(dp_reg & DP_PORT_EN)) { |
Jesse Barnes | 01cb9ea | 2010-10-07 16:01:12 -0700 | [diff] [blame] | 1037 | intel_dp_start_link_train(intel_dp); |
Jesse Barnes | 5d61350 | 2011-01-24 17:10:54 -0800 | [diff] [blame] | 1038 | if (is_edp(intel_dp)) { |
| 1039 | ironlake_edp_panel_on(intel_dp); |
| 1040 | ironlake_edp_panel_vdd_off(intel_dp); |
| 1041 | } |
Jesse Barnes | 33a34e4 | 2010-09-08 12:42:02 -0700 | [diff] [blame] | 1042 | intel_dp_complete_link_train(intel_dp); |
Zhenyu Wang | 32f9d65 | 2009-07-24 01:00:32 +0800 | [diff] [blame] | 1043 | } |
Jesse Barnes | 736085b | 2010-10-08 10:35:55 -0700 | [diff] [blame] | 1044 | if (is_edp(intel_dp)) |
| 1045 | ironlake_edp_backlight_on(dev); |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 1046 | } |
| 1047 | } |
| 1048 | |
| 1049 | /* |
Jesse Barnes | df0c237 | 2011-07-07 11:11:02 -0700 | [diff] [blame] | 1050 | * Native read with retry for link status and receiver capability reads for |
| 1051 | * cases where the sink may still be asleep. |
| 1052 | */ |
| 1053 | static bool |
| 1054 | intel_dp_aux_native_read_retry(struct intel_dp *intel_dp, uint16_t address, |
| 1055 | uint8_t *recv, int recv_bytes) |
| 1056 | { |
| 1057 | int ret, i; |
| 1058 | |
| 1059 | /* |
| 1060 | * Sinks are *supposed* to come up within 1ms from an off state, |
| 1061 | * but we're also supposed to retry 3 times per the spec. |
| 1062 | */ |
| 1063 | for (i = 0; i < 3; i++) { |
| 1064 | ret = intel_dp_aux_native_read(intel_dp, address, recv, |
| 1065 | recv_bytes); |
| 1066 | if (ret == recv_bytes) |
| 1067 | return true; |
| 1068 | msleep(1); |
| 1069 | } |
| 1070 | |
| 1071 | return false; |
| 1072 | } |
| 1073 | |
| 1074 | /* |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 1075 | * Fetch AUX CH registers 0x202 - 0x207 which contain |
| 1076 | * link status information |
| 1077 | */ |
| 1078 | static bool |
Jesse Barnes | 33a34e4 | 2010-09-08 12:42:02 -0700 | [diff] [blame] | 1079 | intel_dp_get_link_status(struct intel_dp *intel_dp) |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 1080 | { |
Jesse Barnes | df0c237 | 2011-07-07 11:11:02 -0700 | [diff] [blame] | 1081 | return intel_dp_aux_native_read_retry(intel_dp, |
| 1082 | DP_LANE0_1_STATUS, |
| 1083 | intel_dp->link_status, |
| 1084 | DP_LINK_STATUS_SIZE); |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 1085 | } |
| 1086 | |
| 1087 | static uint8_t |
| 1088 | intel_dp_link_status(uint8_t link_status[DP_LINK_STATUS_SIZE], |
| 1089 | int r) |
| 1090 | { |
| 1091 | return link_status[r - DP_LANE0_1_STATUS]; |
| 1092 | } |
| 1093 | |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 1094 | static uint8_t |
| 1095 | intel_get_adjust_request_voltage(uint8_t link_status[DP_LINK_STATUS_SIZE], |
| 1096 | int lane) |
| 1097 | { |
| 1098 | int i = DP_ADJUST_REQUEST_LANE0_1 + (lane >> 1); |
| 1099 | int s = ((lane & 1) ? |
| 1100 | DP_ADJUST_VOLTAGE_SWING_LANE1_SHIFT : |
| 1101 | DP_ADJUST_VOLTAGE_SWING_LANE0_SHIFT); |
| 1102 | uint8_t l = intel_dp_link_status(link_status, i); |
| 1103 | |
| 1104 | return ((l >> s) & 3) << DP_TRAIN_VOLTAGE_SWING_SHIFT; |
| 1105 | } |
| 1106 | |
| 1107 | static uint8_t |
| 1108 | intel_get_adjust_request_pre_emphasis(uint8_t link_status[DP_LINK_STATUS_SIZE], |
| 1109 | int lane) |
| 1110 | { |
| 1111 | int i = DP_ADJUST_REQUEST_LANE0_1 + (lane >> 1); |
| 1112 | int s = ((lane & 1) ? |
| 1113 | DP_ADJUST_PRE_EMPHASIS_LANE1_SHIFT : |
| 1114 | DP_ADJUST_PRE_EMPHASIS_LANE0_SHIFT); |
| 1115 | uint8_t l = intel_dp_link_status(link_status, i); |
| 1116 | |
| 1117 | return ((l >> s) & 3) << DP_TRAIN_PRE_EMPHASIS_SHIFT; |
| 1118 | } |
| 1119 | |
| 1120 | |
| 1121 | #if 0 |
| 1122 | static char *voltage_names[] = { |
| 1123 | "0.4V", "0.6V", "0.8V", "1.2V" |
| 1124 | }; |
| 1125 | static char *pre_emph_names[] = { |
| 1126 | "0dB", "3.5dB", "6dB", "9.5dB" |
| 1127 | }; |
| 1128 | static char *link_train_names[] = { |
| 1129 | "pattern 1", "pattern 2", "idle", "off" |
| 1130 | }; |
| 1131 | #endif |
| 1132 | |
| 1133 | /* |
| 1134 | * These are source-specific values; current Intel hardware supports |
| 1135 | * a maximum voltage of 800mV and a maximum pre-emphasis of 6dB |
| 1136 | */ |
| 1137 | #define I830_DP_VOLTAGE_MAX DP_TRAIN_VOLTAGE_SWING_800 |
| 1138 | |
| 1139 | static uint8_t |
| 1140 | intel_dp_pre_emphasis_max(uint8_t voltage_swing) |
| 1141 | { |
| 1142 | switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) { |
| 1143 | case DP_TRAIN_VOLTAGE_SWING_400: |
| 1144 | return DP_TRAIN_PRE_EMPHASIS_6; |
| 1145 | case DP_TRAIN_VOLTAGE_SWING_600: |
| 1146 | return DP_TRAIN_PRE_EMPHASIS_6; |
| 1147 | case DP_TRAIN_VOLTAGE_SWING_800: |
| 1148 | return DP_TRAIN_PRE_EMPHASIS_3_5; |
| 1149 | case DP_TRAIN_VOLTAGE_SWING_1200: |
| 1150 | default: |
| 1151 | return DP_TRAIN_PRE_EMPHASIS_0; |
| 1152 | } |
| 1153 | } |
| 1154 | |
| 1155 | static void |
Jesse Barnes | 33a34e4 | 2010-09-08 12:42:02 -0700 | [diff] [blame] | 1156 | intel_get_adjust_train(struct intel_dp *intel_dp) |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 1157 | { |
| 1158 | uint8_t v = 0; |
| 1159 | uint8_t p = 0; |
| 1160 | int lane; |
| 1161 | |
Jesse Barnes | 33a34e4 | 2010-09-08 12:42:02 -0700 | [diff] [blame] | 1162 | for (lane = 0; lane < intel_dp->lane_count; lane++) { |
| 1163 | uint8_t this_v = intel_get_adjust_request_voltage(intel_dp->link_status, lane); |
| 1164 | uint8_t this_p = intel_get_adjust_request_pre_emphasis(intel_dp->link_status, lane); |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 1165 | |
| 1166 | if (this_v > v) |
| 1167 | v = this_v; |
| 1168 | if (this_p > p) |
| 1169 | p = this_p; |
| 1170 | } |
| 1171 | |
| 1172 | if (v >= I830_DP_VOLTAGE_MAX) |
| 1173 | v = I830_DP_VOLTAGE_MAX | DP_TRAIN_MAX_SWING_REACHED; |
| 1174 | |
| 1175 | if (p >= intel_dp_pre_emphasis_max(v)) |
| 1176 | p = intel_dp_pre_emphasis_max(v) | DP_TRAIN_MAX_PRE_EMPHASIS_REACHED; |
| 1177 | |
| 1178 | for (lane = 0; lane < 4; lane++) |
Jesse Barnes | 33a34e4 | 2010-09-08 12:42:02 -0700 | [diff] [blame] | 1179 | intel_dp->train_set[lane] = v | p; |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 1180 | } |
| 1181 | |
| 1182 | static uint32_t |
Chris Wilson | 3cf2efb | 2010-11-29 10:09:55 +0000 | [diff] [blame] | 1183 | intel_dp_signal_levels(uint8_t train_set, int lane_count) |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 1184 | { |
Chris Wilson | 3cf2efb | 2010-11-29 10:09:55 +0000 | [diff] [blame] | 1185 | uint32_t signal_levels = 0; |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 1186 | |
Chris Wilson | 3cf2efb | 2010-11-29 10:09:55 +0000 | [diff] [blame] | 1187 | switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) { |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 1188 | case DP_TRAIN_VOLTAGE_SWING_400: |
| 1189 | default: |
| 1190 | signal_levels |= DP_VOLTAGE_0_4; |
| 1191 | break; |
| 1192 | case DP_TRAIN_VOLTAGE_SWING_600: |
| 1193 | signal_levels |= DP_VOLTAGE_0_6; |
| 1194 | break; |
| 1195 | case DP_TRAIN_VOLTAGE_SWING_800: |
| 1196 | signal_levels |= DP_VOLTAGE_0_8; |
| 1197 | break; |
| 1198 | case DP_TRAIN_VOLTAGE_SWING_1200: |
| 1199 | signal_levels |= DP_VOLTAGE_1_2; |
| 1200 | break; |
| 1201 | } |
Chris Wilson | 3cf2efb | 2010-11-29 10:09:55 +0000 | [diff] [blame] | 1202 | switch (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) { |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 1203 | case DP_TRAIN_PRE_EMPHASIS_0: |
| 1204 | default: |
| 1205 | signal_levels |= DP_PRE_EMPHASIS_0; |
| 1206 | break; |
| 1207 | case DP_TRAIN_PRE_EMPHASIS_3_5: |
| 1208 | signal_levels |= DP_PRE_EMPHASIS_3_5; |
| 1209 | break; |
| 1210 | case DP_TRAIN_PRE_EMPHASIS_6: |
| 1211 | signal_levels |= DP_PRE_EMPHASIS_6; |
| 1212 | break; |
| 1213 | case DP_TRAIN_PRE_EMPHASIS_9_5: |
| 1214 | signal_levels |= DP_PRE_EMPHASIS_9_5; |
| 1215 | break; |
| 1216 | } |
| 1217 | return signal_levels; |
| 1218 | } |
| 1219 | |
Zhenyu Wang | e3421a1 | 2010-04-08 09:43:27 +0800 | [diff] [blame] | 1220 | /* Gen6's DP voltage swing and pre-emphasis control */ |
| 1221 | static uint32_t |
| 1222 | intel_gen6_edp_signal_levels(uint8_t train_set) |
| 1223 | { |
Yuanhan Liu | 3c5a62b | 2011-01-06 18:26:08 +0800 | [diff] [blame] | 1224 | int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK | |
| 1225 | DP_TRAIN_PRE_EMPHASIS_MASK); |
| 1226 | switch (signal_levels) { |
Zhenyu Wang | e3421a1 | 2010-04-08 09:43:27 +0800 | [diff] [blame] | 1227 | case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_0: |
Yuanhan Liu | 3c5a62b | 2011-01-06 18:26:08 +0800 | [diff] [blame] | 1228 | case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_0: |
| 1229 | return EDP_LINK_TRAIN_400_600MV_0DB_SNB_B; |
| 1230 | case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_3_5: |
| 1231 | return EDP_LINK_TRAIN_400MV_3_5DB_SNB_B; |
Zhenyu Wang | e3421a1 | 2010-04-08 09:43:27 +0800 | [diff] [blame] | 1232 | case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_6: |
Yuanhan Liu | 3c5a62b | 2011-01-06 18:26:08 +0800 | [diff] [blame] | 1233 | case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_6: |
| 1234 | return EDP_LINK_TRAIN_400_600MV_6DB_SNB_B; |
Zhenyu Wang | e3421a1 | 2010-04-08 09:43:27 +0800 | [diff] [blame] | 1235 | case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_3_5: |
Yuanhan Liu | 3c5a62b | 2011-01-06 18:26:08 +0800 | [diff] [blame] | 1236 | case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_3_5: |
| 1237 | return EDP_LINK_TRAIN_600_800MV_3_5DB_SNB_B; |
Zhenyu Wang | e3421a1 | 2010-04-08 09:43:27 +0800 | [diff] [blame] | 1238 | case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_0: |
Yuanhan Liu | 3c5a62b | 2011-01-06 18:26:08 +0800 | [diff] [blame] | 1239 | case DP_TRAIN_VOLTAGE_SWING_1200 | DP_TRAIN_PRE_EMPHASIS_0: |
| 1240 | return EDP_LINK_TRAIN_800_1200MV_0DB_SNB_B; |
Zhenyu Wang | e3421a1 | 2010-04-08 09:43:27 +0800 | [diff] [blame] | 1241 | default: |
Yuanhan Liu | 3c5a62b | 2011-01-06 18:26:08 +0800 | [diff] [blame] | 1242 | DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:" |
| 1243 | "0x%x\n", signal_levels); |
| 1244 | return EDP_LINK_TRAIN_400_600MV_0DB_SNB_B; |
Zhenyu Wang | e3421a1 | 2010-04-08 09:43:27 +0800 | [diff] [blame] | 1245 | } |
| 1246 | } |
| 1247 | |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 1248 | static uint8_t |
| 1249 | intel_get_lane_status(uint8_t link_status[DP_LINK_STATUS_SIZE], |
| 1250 | int lane) |
| 1251 | { |
| 1252 | int i = DP_LANE0_1_STATUS + (lane >> 1); |
| 1253 | int s = (lane & 1) * 4; |
| 1254 | uint8_t l = intel_dp_link_status(link_status, i); |
| 1255 | |
| 1256 | return (l >> s) & 0xf; |
| 1257 | } |
| 1258 | |
| 1259 | /* Check for clock recovery is done on all channels */ |
| 1260 | static bool |
| 1261 | intel_clock_recovery_ok(uint8_t link_status[DP_LINK_STATUS_SIZE], int lane_count) |
| 1262 | { |
| 1263 | int lane; |
| 1264 | uint8_t lane_status; |
| 1265 | |
| 1266 | for (lane = 0; lane < lane_count; lane++) { |
| 1267 | lane_status = intel_get_lane_status(link_status, lane); |
| 1268 | if ((lane_status & DP_LANE_CR_DONE) == 0) |
| 1269 | return false; |
| 1270 | } |
| 1271 | return true; |
| 1272 | } |
| 1273 | |
| 1274 | /* Check to see if channel eq is done on all channels */ |
| 1275 | #define CHANNEL_EQ_BITS (DP_LANE_CR_DONE|\ |
| 1276 | DP_LANE_CHANNEL_EQ_DONE|\ |
| 1277 | DP_LANE_SYMBOL_LOCKED) |
| 1278 | static bool |
Jesse Barnes | 33a34e4 | 2010-09-08 12:42:02 -0700 | [diff] [blame] | 1279 | intel_channel_eq_ok(struct intel_dp *intel_dp) |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 1280 | { |
| 1281 | uint8_t lane_align; |
| 1282 | uint8_t lane_status; |
| 1283 | int lane; |
| 1284 | |
Jesse Barnes | 33a34e4 | 2010-09-08 12:42:02 -0700 | [diff] [blame] | 1285 | lane_align = intel_dp_link_status(intel_dp->link_status, |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 1286 | DP_LANE_ALIGN_STATUS_UPDATED); |
| 1287 | if ((lane_align & DP_INTERLANE_ALIGN_DONE) == 0) |
| 1288 | return false; |
Jesse Barnes | 33a34e4 | 2010-09-08 12:42:02 -0700 | [diff] [blame] | 1289 | for (lane = 0; lane < intel_dp->lane_count; lane++) { |
| 1290 | lane_status = intel_get_lane_status(intel_dp->link_status, lane); |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 1291 | if ((lane_status & CHANNEL_EQ_BITS) != CHANNEL_EQ_BITS) |
| 1292 | return false; |
| 1293 | } |
| 1294 | return true; |
| 1295 | } |
| 1296 | |
| 1297 | static bool |
Chris Wilson | ea5b213 | 2010-08-04 13:50:23 +0100 | [diff] [blame] | 1298 | intel_dp_set_link_train(struct intel_dp *intel_dp, |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 1299 | uint32_t dp_reg_value, |
Chris Wilson | 58e10eb | 2010-10-03 10:56:11 +0100 | [diff] [blame] | 1300 | uint8_t dp_train_pat) |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 1301 | { |
Chris Wilson | 4ef69c7 | 2010-09-09 15:14:28 +0100 | [diff] [blame] | 1302 | struct drm_device *dev = intel_dp->base.base.dev; |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 1303 | struct drm_i915_private *dev_priv = dev->dev_private; |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 1304 | int ret; |
| 1305 | |
Chris Wilson | ea5b213 | 2010-08-04 13:50:23 +0100 | [diff] [blame] | 1306 | I915_WRITE(intel_dp->output_reg, dp_reg_value); |
| 1307 | POSTING_READ(intel_dp->output_reg); |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 1308 | |
Chris Wilson | ea5b213 | 2010-08-04 13:50:23 +0100 | [diff] [blame] | 1309 | intel_dp_aux_native_write_1(intel_dp, |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 1310 | DP_TRAINING_PATTERN_SET, |
| 1311 | dp_train_pat); |
| 1312 | |
Chris Wilson | ea5b213 | 2010-08-04 13:50:23 +0100 | [diff] [blame] | 1313 | ret = intel_dp_aux_native_write(intel_dp, |
Chris Wilson | 58e10eb | 2010-10-03 10:56:11 +0100 | [diff] [blame] | 1314 | DP_TRAINING_LANE0_SET, |
| 1315 | intel_dp->train_set, 4); |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 1316 | if (ret != 4) |
| 1317 | return false; |
| 1318 | |
| 1319 | return true; |
| 1320 | } |
| 1321 | |
Jesse Barnes | 33a34e4 | 2010-09-08 12:42:02 -0700 | [diff] [blame] | 1322 | /* Enable corresponding port and start training pattern 1 */ |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 1323 | static void |
Jesse Barnes | 33a34e4 | 2010-09-08 12:42:02 -0700 | [diff] [blame] | 1324 | intel_dp_start_link_train(struct intel_dp *intel_dp) |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 1325 | { |
Chris Wilson | 4ef69c7 | 2010-09-09 15:14:28 +0100 | [diff] [blame] | 1326 | struct drm_device *dev = intel_dp->base.base.dev; |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 1327 | struct drm_i915_private *dev_priv = dev->dev_private; |
Chris Wilson | 58e10eb | 2010-10-03 10:56:11 +0100 | [diff] [blame] | 1328 | struct intel_crtc *intel_crtc = to_intel_crtc(intel_dp->base.base.crtc); |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 1329 | int i; |
| 1330 | uint8_t voltage; |
| 1331 | bool clock_recovery = false; |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 1332 | int tries; |
Zhenyu Wang | e3421a1 | 2010-04-08 09:43:27 +0800 | [diff] [blame] | 1333 | u32 reg; |
Chris Wilson | ea5b213 | 2010-08-04 13:50:23 +0100 | [diff] [blame] | 1334 | uint32_t DP = intel_dp->DP; |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 1335 | |
Keith Packard | b99a9d9 | 2010-10-03 00:33:05 -0700 | [diff] [blame] | 1336 | /* Enable output, wait for it to become active */ |
| 1337 | I915_WRITE(intel_dp->output_reg, intel_dp->DP); |
| 1338 | POSTING_READ(intel_dp->output_reg); |
| 1339 | intel_wait_for_vblank(dev, intel_crtc->pipe); |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 1340 | |
Chris Wilson | 3cf2efb | 2010-11-29 10:09:55 +0000 | [diff] [blame] | 1341 | /* Write the link configuration data */ |
| 1342 | intel_dp_aux_native_write(intel_dp, DP_LINK_BW_SET, |
| 1343 | intel_dp->link_configuration, |
| 1344 | DP_LINK_CONFIGURATION_SIZE); |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 1345 | |
| 1346 | DP |= DP_PORT_EN; |
Jesse Barnes | cfcb0fc | 2010-10-07 16:01:06 -0700 | [diff] [blame] | 1347 | if (HAS_PCH_CPT(dev) && !is_edp(intel_dp)) |
Zhenyu Wang | e3421a1 | 2010-04-08 09:43:27 +0800 | [diff] [blame] | 1348 | DP &= ~DP_LINK_TRAIN_MASK_CPT; |
| 1349 | else |
| 1350 | DP &= ~DP_LINK_TRAIN_MASK; |
Jesse Barnes | 33a34e4 | 2010-09-08 12:42:02 -0700 | [diff] [blame] | 1351 | memset(intel_dp->train_set, 0, 4); |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 1352 | voltage = 0xff; |
| 1353 | tries = 0; |
| 1354 | clock_recovery = false; |
| 1355 | for (;;) { |
Jesse Barnes | 33a34e4 | 2010-09-08 12:42:02 -0700 | [diff] [blame] | 1356 | /* Use intel_dp->train_set[0] to set the voltage and pre emphasis values */ |
Zhenyu Wang | e3421a1 | 2010-04-08 09:43:27 +0800 | [diff] [blame] | 1357 | uint32_t signal_levels; |
Jesse Barnes | cfcb0fc | 2010-10-07 16:01:06 -0700 | [diff] [blame] | 1358 | if (IS_GEN6(dev) && is_edp(intel_dp)) { |
Jesse Barnes | 33a34e4 | 2010-09-08 12:42:02 -0700 | [diff] [blame] | 1359 | signal_levels = intel_gen6_edp_signal_levels(intel_dp->train_set[0]); |
Zhenyu Wang | e3421a1 | 2010-04-08 09:43:27 +0800 | [diff] [blame] | 1360 | DP = (DP & ~EDP_LINK_TRAIN_VOL_EMP_MASK_SNB) | signal_levels; |
| 1361 | } else { |
Chris Wilson | 3cf2efb | 2010-11-29 10:09:55 +0000 | [diff] [blame] | 1362 | signal_levels = intel_dp_signal_levels(intel_dp->train_set[0], intel_dp->lane_count); |
Zhenyu Wang | e3421a1 | 2010-04-08 09:43:27 +0800 | [diff] [blame] | 1363 | DP = (DP & ~(DP_VOLTAGE_MASK|DP_PRE_EMPHASIS_MASK)) | signal_levels; |
| 1364 | } |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 1365 | |
Jesse Barnes | cfcb0fc | 2010-10-07 16:01:06 -0700 | [diff] [blame] | 1366 | if (HAS_PCH_CPT(dev) && !is_edp(intel_dp)) |
Zhenyu Wang | e3421a1 | 2010-04-08 09:43:27 +0800 | [diff] [blame] | 1367 | reg = DP | DP_LINK_TRAIN_PAT_1_CPT; |
| 1368 | else |
| 1369 | reg = DP | DP_LINK_TRAIN_PAT_1; |
| 1370 | |
Chris Wilson | ea5b213 | 2010-08-04 13:50:23 +0100 | [diff] [blame] | 1371 | if (!intel_dp_set_link_train(intel_dp, reg, |
Chris Wilson | 58e10eb | 2010-10-03 10:56:11 +0100 | [diff] [blame] | 1372 | DP_TRAINING_PATTERN_1)) |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 1373 | break; |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 1374 | /* Set training pattern 1 */ |
| 1375 | |
Chris Wilson | 3cf2efb | 2010-11-29 10:09:55 +0000 | [diff] [blame] | 1376 | udelay(100); |
| 1377 | if (!intel_dp_get_link_status(intel_dp)) |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 1378 | break; |
| 1379 | |
Chris Wilson | 3cf2efb | 2010-11-29 10:09:55 +0000 | [diff] [blame] | 1380 | if (intel_clock_recovery_ok(intel_dp->link_status, intel_dp->lane_count)) { |
| 1381 | clock_recovery = true; |
| 1382 | break; |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 1383 | } |
Chris Wilson | 3cf2efb | 2010-11-29 10:09:55 +0000 | [diff] [blame] | 1384 | |
| 1385 | /* Check to see if we've tried the max voltage */ |
| 1386 | for (i = 0; i < intel_dp->lane_count; i++) |
| 1387 | if ((intel_dp->train_set[i] & DP_TRAIN_MAX_SWING_REACHED) == 0) |
| 1388 | break; |
| 1389 | if (i == intel_dp->lane_count) |
| 1390 | break; |
| 1391 | |
| 1392 | /* Check to see if we've tried the same voltage 5 times */ |
| 1393 | if ((intel_dp->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK) == voltage) { |
| 1394 | ++tries; |
| 1395 | if (tries == 5) |
| 1396 | break; |
| 1397 | } else |
| 1398 | tries = 0; |
| 1399 | voltage = intel_dp->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK; |
| 1400 | |
| 1401 | /* Compute new intel_dp->train_set as requested by target */ |
| 1402 | intel_get_adjust_train(intel_dp); |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 1403 | } |
| 1404 | |
Jesse Barnes | 33a34e4 | 2010-09-08 12:42:02 -0700 | [diff] [blame] | 1405 | intel_dp->DP = DP; |
| 1406 | } |
| 1407 | |
| 1408 | static void |
| 1409 | intel_dp_complete_link_train(struct intel_dp *intel_dp) |
| 1410 | { |
Chris Wilson | 4ef69c7 | 2010-09-09 15:14:28 +0100 | [diff] [blame] | 1411 | struct drm_device *dev = intel_dp->base.base.dev; |
Jesse Barnes | 33a34e4 | 2010-09-08 12:42:02 -0700 | [diff] [blame] | 1412 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 1413 | bool channel_eq = false; |
Jesse Barnes | 37f8097 | 2011-01-05 14:45:24 -0800 | [diff] [blame] | 1414 | int tries, cr_tries; |
Jesse Barnes | 33a34e4 | 2010-09-08 12:42:02 -0700 | [diff] [blame] | 1415 | u32 reg; |
| 1416 | uint32_t DP = intel_dp->DP; |
| 1417 | |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 1418 | /* channel equalization */ |
| 1419 | tries = 0; |
Jesse Barnes | 37f8097 | 2011-01-05 14:45:24 -0800 | [diff] [blame] | 1420 | cr_tries = 0; |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 1421 | channel_eq = false; |
| 1422 | for (;;) { |
Jesse Barnes | 33a34e4 | 2010-09-08 12:42:02 -0700 | [diff] [blame] | 1423 | /* Use intel_dp->train_set[0] to set the voltage and pre emphasis values */ |
Zhenyu Wang | e3421a1 | 2010-04-08 09:43:27 +0800 | [diff] [blame] | 1424 | uint32_t signal_levels; |
| 1425 | |
Jesse Barnes | 37f8097 | 2011-01-05 14:45:24 -0800 | [diff] [blame] | 1426 | if (cr_tries > 5) { |
| 1427 | DRM_ERROR("failed to train DP, aborting\n"); |
| 1428 | intel_dp_link_down(intel_dp); |
| 1429 | break; |
| 1430 | } |
| 1431 | |
Jesse Barnes | cfcb0fc | 2010-10-07 16:01:06 -0700 | [diff] [blame] | 1432 | if (IS_GEN6(dev) && is_edp(intel_dp)) { |
Jesse Barnes | 33a34e4 | 2010-09-08 12:42:02 -0700 | [diff] [blame] | 1433 | signal_levels = intel_gen6_edp_signal_levels(intel_dp->train_set[0]); |
Zhenyu Wang | e3421a1 | 2010-04-08 09:43:27 +0800 | [diff] [blame] | 1434 | DP = (DP & ~EDP_LINK_TRAIN_VOL_EMP_MASK_SNB) | signal_levels; |
| 1435 | } else { |
Chris Wilson | 3cf2efb | 2010-11-29 10:09:55 +0000 | [diff] [blame] | 1436 | signal_levels = intel_dp_signal_levels(intel_dp->train_set[0], intel_dp->lane_count); |
Zhenyu Wang | e3421a1 | 2010-04-08 09:43:27 +0800 | [diff] [blame] | 1437 | DP = (DP & ~(DP_VOLTAGE_MASK|DP_PRE_EMPHASIS_MASK)) | signal_levels; |
| 1438 | } |
| 1439 | |
Jesse Barnes | cfcb0fc | 2010-10-07 16:01:06 -0700 | [diff] [blame] | 1440 | if (HAS_PCH_CPT(dev) && !is_edp(intel_dp)) |
Zhenyu Wang | e3421a1 | 2010-04-08 09:43:27 +0800 | [diff] [blame] | 1441 | reg = DP | DP_LINK_TRAIN_PAT_2_CPT; |
| 1442 | else |
| 1443 | reg = DP | DP_LINK_TRAIN_PAT_2; |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 1444 | |
| 1445 | /* channel eq pattern */ |
Chris Wilson | ea5b213 | 2010-08-04 13:50:23 +0100 | [diff] [blame] | 1446 | if (!intel_dp_set_link_train(intel_dp, reg, |
Chris Wilson | 58e10eb | 2010-10-03 10:56:11 +0100 | [diff] [blame] | 1447 | DP_TRAINING_PATTERN_2)) |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 1448 | break; |
| 1449 | |
Chris Wilson | 3cf2efb | 2010-11-29 10:09:55 +0000 | [diff] [blame] | 1450 | udelay(400); |
| 1451 | if (!intel_dp_get_link_status(intel_dp)) |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 1452 | break; |
Jesse Barnes | 869184a | 2010-10-07 16:01:22 -0700 | [diff] [blame] | 1453 | |
Jesse Barnes | 37f8097 | 2011-01-05 14:45:24 -0800 | [diff] [blame] | 1454 | /* Make sure clock is still ok */ |
| 1455 | if (!intel_clock_recovery_ok(intel_dp->link_status, intel_dp->lane_count)) { |
| 1456 | intel_dp_start_link_train(intel_dp); |
| 1457 | cr_tries++; |
| 1458 | continue; |
| 1459 | } |
| 1460 | |
Chris Wilson | 3cf2efb | 2010-11-29 10:09:55 +0000 | [diff] [blame] | 1461 | if (intel_channel_eq_ok(intel_dp)) { |
| 1462 | channel_eq = true; |
| 1463 | break; |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 1464 | } |
Chris Wilson | 3cf2efb | 2010-11-29 10:09:55 +0000 | [diff] [blame] | 1465 | |
Jesse Barnes | 37f8097 | 2011-01-05 14:45:24 -0800 | [diff] [blame] | 1466 | /* Try 5 times, then try clock recovery if that fails */ |
| 1467 | if (tries > 5) { |
| 1468 | intel_dp_link_down(intel_dp); |
| 1469 | intel_dp_start_link_train(intel_dp); |
| 1470 | tries = 0; |
| 1471 | cr_tries++; |
| 1472 | continue; |
| 1473 | } |
Chris Wilson | 3cf2efb | 2010-11-29 10:09:55 +0000 | [diff] [blame] | 1474 | |
| 1475 | /* Compute new intel_dp->train_set as requested by target */ |
| 1476 | intel_get_adjust_train(intel_dp); |
| 1477 | ++tries; |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 1478 | } |
Chris Wilson | 3cf2efb | 2010-11-29 10:09:55 +0000 | [diff] [blame] | 1479 | |
Jesse Barnes | cfcb0fc | 2010-10-07 16:01:06 -0700 | [diff] [blame] | 1480 | if (HAS_PCH_CPT(dev) && !is_edp(intel_dp)) |
Zhenyu Wang | e3421a1 | 2010-04-08 09:43:27 +0800 | [diff] [blame] | 1481 | reg = DP | DP_LINK_TRAIN_OFF_CPT; |
| 1482 | else |
| 1483 | reg = DP | DP_LINK_TRAIN_OFF; |
| 1484 | |
Chris Wilson | ea5b213 | 2010-08-04 13:50:23 +0100 | [diff] [blame] | 1485 | I915_WRITE(intel_dp->output_reg, reg); |
| 1486 | POSTING_READ(intel_dp->output_reg); |
| 1487 | intel_dp_aux_native_write_1(intel_dp, |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 1488 | DP_TRAINING_PATTERN_SET, DP_TRAINING_PATTERN_DISABLE); |
| 1489 | } |
| 1490 | |
| 1491 | static void |
Chris Wilson | ea5b213 | 2010-08-04 13:50:23 +0100 | [diff] [blame] | 1492 | intel_dp_link_down(struct intel_dp *intel_dp) |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 1493 | { |
Chris Wilson | 4ef69c7 | 2010-09-09 15:14:28 +0100 | [diff] [blame] | 1494 | struct drm_device *dev = intel_dp->base.base.dev; |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 1495 | struct drm_i915_private *dev_priv = dev->dev_private; |
Chris Wilson | ea5b213 | 2010-08-04 13:50:23 +0100 | [diff] [blame] | 1496 | uint32_t DP = intel_dp->DP; |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 1497 | |
Chris Wilson | 1b39d6f | 2010-12-06 11:20:45 +0000 | [diff] [blame] | 1498 | if ((I915_READ(intel_dp->output_reg) & DP_PORT_EN) == 0) |
| 1499 | return; |
| 1500 | |
Zhao Yakui | 28c9773 | 2009-10-09 11:39:41 +0800 | [diff] [blame] | 1501 | DRM_DEBUG_KMS("\n"); |
Zhenyu Wang | 32f9d65 | 2009-07-24 01:00:32 +0800 | [diff] [blame] | 1502 | |
Jesse Barnes | cfcb0fc | 2010-10-07 16:01:06 -0700 | [diff] [blame] | 1503 | if (is_edp(intel_dp)) { |
Zhenyu Wang | 32f9d65 | 2009-07-24 01:00:32 +0800 | [diff] [blame] | 1504 | DP &= ~DP_PLL_ENABLE; |
Chris Wilson | ea5b213 | 2010-08-04 13:50:23 +0100 | [diff] [blame] | 1505 | I915_WRITE(intel_dp->output_reg, DP); |
| 1506 | POSTING_READ(intel_dp->output_reg); |
Zhenyu Wang | 32f9d65 | 2009-07-24 01:00:32 +0800 | [diff] [blame] | 1507 | udelay(100); |
| 1508 | } |
| 1509 | |
Jesse Barnes | cfcb0fc | 2010-10-07 16:01:06 -0700 | [diff] [blame] | 1510 | if (HAS_PCH_CPT(dev) && !is_edp(intel_dp)) { |
Zhenyu Wang | e3421a1 | 2010-04-08 09:43:27 +0800 | [diff] [blame] | 1511 | DP &= ~DP_LINK_TRAIN_MASK_CPT; |
Chris Wilson | ea5b213 | 2010-08-04 13:50:23 +0100 | [diff] [blame] | 1512 | I915_WRITE(intel_dp->output_reg, DP | DP_LINK_TRAIN_PAT_IDLE_CPT); |
Zhenyu Wang | e3421a1 | 2010-04-08 09:43:27 +0800 | [diff] [blame] | 1513 | } else { |
| 1514 | DP &= ~DP_LINK_TRAIN_MASK; |
Chris Wilson | ea5b213 | 2010-08-04 13:50:23 +0100 | [diff] [blame] | 1515 | I915_WRITE(intel_dp->output_reg, DP | DP_LINK_TRAIN_PAT_IDLE); |
Zhenyu Wang | e3421a1 | 2010-04-08 09:43:27 +0800 | [diff] [blame] | 1516 | } |
Chris Wilson | fe255d0 | 2010-09-11 21:37:48 +0100 | [diff] [blame] | 1517 | POSTING_READ(intel_dp->output_reg); |
Zhenyu Wang | 5eb08b6 | 2009-07-24 01:00:31 +0800 | [diff] [blame] | 1518 | |
Chris Wilson | fe255d0 | 2010-09-11 21:37:48 +0100 | [diff] [blame] | 1519 | msleep(17); |
Zhenyu Wang | 5eb08b6 | 2009-07-24 01:00:31 +0800 | [diff] [blame] | 1520 | |
Jesse Barnes | cfcb0fc | 2010-10-07 16:01:06 -0700 | [diff] [blame] | 1521 | if (is_edp(intel_dp)) |
Zhenyu Wang | 32f9d65 | 2009-07-24 01:00:32 +0800 | [diff] [blame] | 1522 | DP |= DP_LINK_TRAIN_OFF; |
Eric Anholt | 5bddd17 | 2010-11-18 09:32:59 +0800 | [diff] [blame] | 1523 | |
Chris Wilson | 1b39d6f | 2010-12-06 11:20:45 +0000 | [diff] [blame] | 1524 | if (!HAS_PCH_CPT(dev) && |
| 1525 | I915_READ(intel_dp->output_reg) & DP_PIPEB_SELECT) { |
Chris Wilson | 31acbcc | 2011-04-17 06:38:35 +0100 | [diff] [blame] | 1526 | struct drm_crtc *crtc = intel_dp->base.base.crtc; |
| 1527 | |
Eric Anholt | 5bddd17 | 2010-11-18 09:32:59 +0800 | [diff] [blame] | 1528 | /* Hardware workaround: leaving our transcoder select |
| 1529 | * set to transcoder B while it's off will prevent the |
| 1530 | * corresponding HDMI output on transcoder A. |
| 1531 | * |
| 1532 | * Combine this with another hardware workaround: |
| 1533 | * transcoder select bit can only be cleared while the |
| 1534 | * port is enabled. |
| 1535 | */ |
| 1536 | DP &= ~DP_PIPEB_SELECT; |
| 1537 | I915_WRITE(intel_dp->output_reg, DP); |
| 1538 | |
| 1539 | /* Changes to enable or select take place the vblank |
| 1540 | * after being written. |
| 1541 | */ |
Chris Wilson | 31acbcc | 2011-04-17 06:38:35 +0100 | [diff] [blame] | 1542 | if (crtc == NULL) { |
| 1543 | /* We can arrive here never having been attached |
| 1544 | * to a CRTC, for instance, due to inheriting |
| 1545 | * random state from the BIOS. |
| 1546 | * |
| 1547 | * If the pipe is not running, play safe and |
| 1548 | * wait for the clocks to stabilise before |
| 1549 | * continuing. |
| 1550 | */ |
| 1551 | POSTING_READ(intel_dp->output_reg); |
| 1552 | msleep(50); |
| 1553 | } else |
| 1554 | intel_wait_for_vblank(dev, to_intel_crtc(crtc)->pipe); |
Eric Anholt | 5bddd17 | 2010-11-18 09:32:59 +0800 | [diff] [blame] | 1555 | } |
| 1556 | |
Chris Wilson | ea5b213 | 2010-08-04 13:50:23 +0100 | [diff] [blame] | 1557 | I915_WRITE(intel_dp->output_reg, DP & ~DP_PORT_EN); |
| 1558 | POSTING_READ(intel_dp->output_reg); |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 1559 | } |
| 1560 | |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 1561 | /* |
| 1562 | * According to DP spec |
| 1563 | * 5.1.2: |
| 1564 | * 1. Read DPCD |
| 1565 | * 2. Configure link according to Receiver Capabilities |
| 1566 | * 3. Use Link Training from 2.5.3.3 and 3.5.1.3 |
| 1567 | * 4. Check link status on receipt of hot-plug interrupt |
| 1568 | */ |
| 1569 | |
| 1570 | static void |
Chris Wilson | ea5b213 | 2010-08-04 13:50:23 +0100 | [diff] [blame] | 1571 | intel_dp_check_link_status(struct intel_dp *intel_dp) |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 1572 | { |
Jesse Barnes | 59cd09e | 2011-07-07 11:10:59 -0700 | [diff] [blame] | 1573 | int ret; |
| 1574 | |
Chris Wilson | 4ef69c7 | 2010-09-09 15:14:28 +0100 | [diff] [blame] | 1575 | if (!intel_dp->base.base.crtc) |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 1576 | return; |
| 1577 | |
Jesse Barnes | 33a34e4 | 2010-09-08 12:42:02 -0700 | [diff] [blame] | 1578 | if (!intel_dp_get_link_status(intel_dp)) { |
Chris Wilson | ea5b213 | 2010-08-04 13:50:23 +0100 | [diff] [blame] | 1579 | intel_dp_link_down(intel_dp); |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 1580 | return; |
| 1581 | } |
| 1582 | |
Jesse Barnes | 59cd09e | 2011-07-07 11:10:59 -0700 | [diff] [blame] | 1583 | /* Try to read receiver status if the link appears to be up */ |
| 1584 | ret = intel_dp_aux_native_read(intel_dp, |
| 1585 | 0x000, intel_dp->dpcd, |
| 1586 | sizeof (intel_dp->dpcd)); |
| 1587 | if (ret != sizeof(intel_dp->dpcd)) { |
| 1588 | intel_dp_link_down(intel_dp); |
| 1589 | return; |
| 1590 | } |
| 1591 | |
Jesse Barnes | 33a34e4 | 2010-09-08 12:42:02 -0700 | [diff] [blame] | 1592 | if (!intel_channel_eq_ok(intel_dp)) { |
| 1593 | intel_dp_start_link_train(intel_dp); |
| 1594 | intel_dp_complete_link_train(intel_dp); |
| 1595 | } |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 1596 | } |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 1597 | |
Zhenyu Wang | 5eb08b6 | 2009-07-24 01:00:31 +0800 | [diff] [blame] | 1598 | static enum drm_connector_status |
Zhenyu Wang | a9756bb | 2010-09-19 13:09:06 +0800 | [diff] [blame] | 1599 | ironlake_dp_detect(struct intel_dp *intel_dp) |
Zhenyu Wang | 5eb08b6 | 2009-07-24 01:00:31 +0800 | [diff] [blame] | 1600 | { |
Zhenyu Wang | 5eb08b6 | 2009-07-24 01:00:31 +0800 | [diff] [blame] | 1601 | enum drm_connector_status status; |
Jesse Barnes | df0c237 | 2011-07-07 11:11:02 -0700 | [diff] [blame] | 1602 | bool ret; |
Zhenyu Wang | 5eb08b6 | 2009-07-24 01:00:31 +0800 | [diff] [blame] | 1603 | |
Chris Wilson | fe16d94 | 2011-02-12 10:29:38 +0000 | [diff] [blame] | 1604 | /* Can't disconnect eDP, but you can close the lid... */ |
| 1605 | if (is_edp(intel_dp)) { |
| 1606 | status = intel_panel_detect(intel_dp->base.base.dev); |
| 1607 | if (status == connector_status_unknown) |
| 1608 | status = connector_status_connected; |
| 1609 | return status; |
| 1610 | } |
Jesse Barnes | 01cb9ea | 2010-10-07 16:01:12 -0700 | [diff] [blame] | 1611 | |
Zhenyu Wang | 5eb08b6 | 2009-07-24 01:00:31 +0800 | [diff] [blame] | 1612 | status = connector_status_disconnected; |
Jesse Barnes | df0c237 | 2011-07-07 11:11:02 -0700 | [diff] [blame] | 1613 | ret = intel_dp_aux_native_read_retry(intel_dp, |
| 1614 | 0x000, intel_dp->dpcd, |
| 1615 | sizeof (intel_dp->dpcd)); |
| 1616 | if (ret && intel_dp->dpcd[DP_DPCD_REV] != 0) |
| 1617 | status = connector_status_connected; |
Chris Wilson | ea5b213 | 2010-08-04 13:50:23 +0100 | [diff] [blame] | 1618 | DRM_DEBUG_KMS("DPCD: %hx%hx%hx%hx\n", intel_dp->dpcd[0], |
| 1619 | intel_dp->dpcd[1], intel_dp->dpcd[2], intel_dp->dpcd[3]); |
Zhenyu Wang | 5eb08b6 | 2009-07-24 01:00:31 +0800 | [diff] [blame] | 1620 | return status; |
| 1621 | } |
| 1622 | |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 1623 | static enum drm_connector_status |
Zhenyu Wang | a9756bb | 2010-09-19 13:09:06 +0800 | [diff] [blame] | 1624 | g4x_dp_detect(struct intel_dp *intel_dp) |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 1625 | { |
Chris Wilson | 4ef69c7 | 2010-09-09 15:14:28 +0100 | [diff] [blame] | 1626 | struct drm_device *dev = intel_dp->base.base.dev; |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 1627 | struct drm_i915_private *dev_priv = dev->dev_private; |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 1628 | enum drm_connector_status status; |
Zhenyu Wang | a9756bb | 2010-09-19 13:09:06 +0800 | [diff] [blame] | 1629 | uint32_t temp, bit; |
Zhenyu Wang | 5eb08b6 | 2009-07-24 01:00:31 +0800 | [diff] [blame] | 1630 | |
Chris Wilson | ea5b213 | 2010-08-04 13:50:23 +0100 | [diff] [blame] | 1631 | switch (intel_dp->output_reg) { |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 1632 | case DP_B: |
| 1633 | bit = DPB_HOTPLUG_INT_STATUS; |
| 1634 | break; |
| 1635 | case DP_C: |
| 1636 | bit = DPC_HOTPLUG_INT_STATUS; |
| 1637 | break; |
| 1638 | case DP_D: |
| 1639 | bit = DPD_HOTPLUG_INT_STATUS; |
| 1640 | break; |
| 1641 | default: |
| 1642 | return connector_status_unknown; |
| 1643 | } |
| 1644 | |
| 1645 | temp = I915_READ(PORT_HOTPLUG_STAT); |
| 1646 | |
| 1647 | if ((temp & bit) == 0) |
| 1648 | return connector_status_disconnected; |
| 1649 | |
| 1650 | status = connector_status_disconnected; |
Zhenyu Wang | a9756bb | 2010-09-19 13:09:06 +0800 | [diff] [blame] | 1651 | if (intel_dp_aux_native_read(intel_dp, 0x000, intel_dp->dpcd, |
Chris Wilson | ea5b213 | 2010-08-04 13:50:23 +0100 | [diff] [blame] | 1652 | sizeof (intel_dp->dpcd)) == sizeof (intel_dp->dpcd)) |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 1653 | { |
Jesse Barnes | 7183dc2 | 2011-07-07 11:10:58 -0700 | [diff] [blame] | 1654 | if (intel_dp->dpcd[DP_DPCD_REV] != 0) |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 1655 | status = connector_status_connected; |
| 1656 | } |
Zhenyu Wang | a9756bb | 2010-09-19 13:09:06 +0800 | [diff] [blame] | 1657 | |
Takashi Iwai | dd2b379 | 2010-10-26 17:14:36 +0100 | [diff] [blame] | 1658 | return status; |
Zhenyu Wang | a9756bb | 2010-09-19 13:09:06 +0800 | [diff] [blame] | 1659 | } |
| 1660 | |
| 1661 | /** |
| 1662 | * Uses CRT_HOTPLUG_EN and CRT_HOTPLUG_STAT to detect DP connection. |
| 1663 | * |
| 1664 | * \return true if DP port is connected. |
| 1665 | * \return false if DP port is disconnected. |
| 1666 | */ |
| 1667 | static enum drm_connector_status |
| 1668 | intel_dp_detect(struct drm_connector *connector, bool force) |
| 1669 | { |
| 1670 | struct intel_dp *intel_dp = intel_attached_dp(connector); |
| 1671 | struct drm_device *dev = intel_dp->base.base.dev; |
| 1672 | enum drm_connector_status status; |
| 1673 | struct edid *edid = NULL; |
| 1674 | |
| 1675 | intel_dp->has_audio = false; |
| 1676 | |
| 1677 | if (HAS_PCH_SPLIT(dev)) |
| 1678 | status = ironlake_dp_detect(intel_dp); |
| 1679 | else |
| 1680 | status = g4x_dp_detect(intel_dp); |
| 1681 | if (status != connector_status_connected) |
| 1682 | return status; |
| 1683 | |
Chris Wilson | f684960 | 2010-09-19 09:29:33 +0100 | [diff] [blame] | 1684 | if (intel_dp->force_audio) { |
| 1685 | intel_dp->has_audio = intel_dp->force_audio > 0; |
| 1686 | } else { |
| 1687 | edid = drm_get_edid(connector, &intel_dp->adapter); |
| 1688 | if (edid) { |
| 1689 | intel_dp->has_audio = drm_detect_monitor_audio(edid); |
| 1690 | connector->display_info.raw_edid = NULL; |
| 1691 | kfree(edid); |
| 1692 | } |
Zhenyu Wang | a9756bb | 2010-09-19 13:09:06 +0800 | [diff] [blame] | 1693 | } |
| 1694 | |
| 1695 | return connector_status_connected; |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 1696 | } |
| 1697 | |
| 1698 | static int intel_dp_get_modes(struct drm_connector *connector) |
| 1699 | { |
Chris Wilson | df0e924 | 2010-09-09 16:20:55 +0100 | [diff] [blame] | 1700 | struct intel_dp *intel_dp = intel_attached_dp(connector); |
Chris Wilson | 4ef69c7 | 2010-09-09 15:14:28 +0100 | [diff] [blame] | 1701 | struct drm_device *dev = intel_dp->base.base.dev; |
Zhenyu Wang | 32f9d65 | 2009-07-24 01:00:32 +0800 | [diff] [blame] | 1702 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 1703 | int ret; |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 1704 | |
| 1705 | /* We should parse the EDID data and find out if it has an audio sink |
| 1706 | */ |
| 1707 | |
Chris Wilson | f899fc6 | 2010-07-20 15:44:45 -0700 | [diff] [blame] | 1708 | ret = intel_ddc_get_modes(connector, &intel_dp->adapter); |
Zhao Yakui | b9efc48 | 2010-07-19 09:43:11 +0100 | [diff] [blame] | 1709 | if (ret) { |
Jesse Barnes | 4d92646 | 2010-10-07 16:01:07 -0700 | [diff] [blame] | 1710 | if (is_edp(intel_dp) && !dev_priv->panel_fixed_mode) { |
Zhao Yakui | b9efc48 | 2010-07-19 09:43:11 +0100 | [diff] [blame] | 1711 | struct drm_display_mode *newmode; |
| 1712 | list_for_each_entry(newmode, &connector->probed_modes, |
| 1713 | head) { |
| 1714 | if (newmode->type & DRM_MODE_TYPE_PREFERRED) { |
| 1715 | dev_priv->panel_fixed_mode = |
| 1716 | drm_mode_duplicate(dev, newmode); |
| 1717 | break; |
| 1718 | } |
| 1719 | } |
| 1720 | } |
| 1721 | |
Zhenyu Wang | 32f9d65 | 2009-07-24 01:00:32 +0800 | [diff] [blame] | 1722 | return ret; |
Zhao Yakui | b9efc48 | 2010-07-19 09:43:11 +0100 | [diff] [blame] | 1723 | } |
Zhenyu Wang | 32f9d65 | 2009-07-24 01:00:32 +0800 | [diff] [blame] | 1724 | |
| 1725 | /* if eDP has no EDID, try to use fixed panel mode from VBT */ |
Jesse Barnes | 4d92646 | 2010-10-07 16:01:07 -0700 | [diff] [blame] | 1726 | if (is_edp(intel_dp)) { |
Zhenyu Wang | 32f9d65 | 2009-07-24 01:00:32 +0800 | [diff] [blame] | 1727 | if (dev_priv->panel_fixed_mode != NULL) { |
| 1728 | struct drm_display_mode *mode; |
| 1729 | mode = drm_mode_duplicate(dev, dev_priv->panel_fixed_mode); |
| 1730 | drm_mode_probed_add(connector, mode); |
| 1731 | return 1; |
| 1732 | } |
| 1733 | } |
| 1734 | return 0; |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 1735 | } |
| 1736 | |
Chris Wilson | 1aad7ac | 2011-02-09 18:46:58 +0000 | [diff] [blame] | 1737 | static bool |
| 1738 | intel_dp_detect_audio(struct drm_connector *connector) |
| 1739 | { |
| 1740 | struct intel_dp *intel_dp = intel_attached_dp(connector); |
| 1741 | struct edid *edid; |
| 1742 | bool has_audio = false; |
| 1743 | |
| 1744 | edid = drm_get_edid(connector, &intel_dp->adapter); |
| 1745 | if (edid) { |
| 1746 | has_audio = drm_detect_monitor_audio(edid); |
| 1747 | |
| 1748 | connector->display_info.raw_edid = NULL; |
| 1749 | kfree(edid); |
| 1750 | } |
| 1751 | |
| 1752 | return has_audio; |
| 1753 | } |
| 1754 | |
Chris Wilson | f684960 | 2010-09-19 09:29:33 +0100 | [diff] [blame] | 1755 | static int |
| 1756 | intel_dp_set_property(struct drm_connector *connector, |
| 1757 | struct drm_property *property, |
| 1758 | uint64_t val) |
| 1759 | { |
Chris Wilson | e953fd7 | 2011-02-21 22:23:52 +0000 | [diff] [blame] | 1760 | struct drm_i915_private *dev_priv = connector->dev->dev_private; |
Chris Wilson | f684960 | 2010-09-19 09:29:33 +0100 | [diff] [blame] | 1761 | struct intel_dp *intel_dp = intel_attached_dp(connector); |
| 1762 | int ret; |
| 1763 | |
| 1764 | ret = drm_connector_property_set_value(connector, property, val); |
| 1765 | if (ret) |
| 1766 | return ret; |
| 1767 | |
Chris Wilson | 3f43c48 | 2011-05-12 22:17:24 +0100 | [diff] [blame] | 1768 | if (property == dev_priv->force_audio_property) { |
Chris Wilson | 1aad7ac | 2011-02-09 18:46:58 +0000 | [diff] [blame] | 1769 | int i = val; |
| 1770 | bool has_audio; |
| 1771 | |
| 1772 | if (i == intel_dp->force_audio) |
Chris Wilson | f684960 | 2010-09-19 09:29:33 +0100 | [diff] [blame] | 1773 | return 0; |
| 1774 | |
Chris Wilson | 1aad7ac | 2011-02-09 18:46:58 +0000 | [diff] [blame] | 1775 | intel_dp->force_audio = i; |
Chris Wilson | f684960 | 2010-09-19 09:29:33 +0100 | [diff] [blame] | 1776 | |
Chris Wilson | 1aad7ac | 2011-02-09 18:46:58 +0000 | [diff] [blame] | 1777 | if (i == 0) |
| 1778 | has_audio = intel_dp_detect_audio(connector); |
| 1779 | else |
| 1780 | has_audio = i > 0; |
| 1781 | |
| 1782 | if (has_audio == intel_dp->has_audio) |
Chris Wilson | f684960 | 2010-09-19 09:29:33 +0100 | [diff] [blame] | 1783 | return 0; |
| 1784 | |
Chris Wilson | 1aad7ac | 2011-02-09 18:46:58 +0000 | [diff] [blame] | 1785 | intel_dp->has_audio = has_audio; |
Chris Wilson | f684960 | 2010-09-19 09:29:33 +0100 | [diff] [blame] | 1786 | goto done; |
| 1787 | } |
| 1788 | |
Chris Wilson | e953fd7 | 2011-02-21 22:23:52 +0000 | [diff] [blame] | 1789 | if (property == dev_priv->broadcast_rgb_property) { |
| 1790 | if (val == !!intel_dp->color_range) |
| 1791 | return 0; |
| 1792 | |
| 1793 | intel_dp->color_range = val ? DP_COLOR_RANGE_16_235 : 0; |
| 1794 | goto done; |
| 1795 | } |
| 1796 | |
Chris Wilson | f684960 | 2010-09-19 09:29:33 +0100 | [diff] [blame] | 1797 | return -EINVAL; |
| 1798 | |
| 1799 | done: |
| 1800 | if (intel_dp->base.base.crtc) { |
| 1801 | struct drm_crtc *crtc = intel_dp->base.base.crtc; |
| 1802 | drm_crtc_helper_set_mode(crtc, &crtc->mode, |
| 1803 | crtc->x, crtc->y, |
| 1804 | crtc->fb); |
| 1805 | } |
| 1806 | |
| 1807 | return 0; |
| 1808 | } |
| 1809 | |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 1810 | static void |
| 1811 | intel_dp_destroy (struct drm_connector *connector) |
| 1812 | { |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 1813 | drm_sysfs_connector_remove(connector); |
| 1814 | drm_connector_cleanup(connector); |
Zhenyu Wang | 55f78c4 | 2010-03-29 16:13:57 +0800 | [diff] [blame] | 1815 | kfree(connector); |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 1816 | } |
| 1817 | |
Daniel Vetter | 24d0592 | 2010-08-20 18:08:28 +0200 | [diff] [blame] | 1818 | static void intel_dp_encoder_destroy(struct drm_encoder *encoder) |
| 1819 | { |
| 1820 | struct intel_dp *intel_dp = enc_to_intel_dp(encoder); |
| 1821 | |
| 1822 | i2c_del_adapter(&intel_dp->adapter); |
| 1823 | drm_encoder_cleanup(encoder); |
| 1824 | kfree(intel_dp); |
| 1825 | } |
| 1826 | |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 1827 | static const struct drm_encoder_helper_funcs intel_dp_helper_funcs = { |
| 1828 | .dpms = intel_dp_dpms, |
| 1829 | .mode_fixup = intel_dp_mode_fixup, |
Jesse Barnes | d240f20 | 2010-08-13 15:43:26 -0700 | [diff] [blame] | 1830 | .prepare = intel_dp_prepare, |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 1831 | .mode_set = intel_dp_mode_set, |
Jesse Barnes | d240f20 | 2010-08-13 15:43:26 -0700 | [diff] [blame] | 1832 | .commit = intel_dp_commit, |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 1833 | }; |
| 1834 | |
| 1835 | static const struct drm_connector_funcs intel_dp_connector_funcs = { |
| 1836 | .dpms = drm_helper_connector_dpms, |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 1837 | .detect = intel_dp_detect, |
| 1838 | .fill_modes = drm_helper_probe_single_connector_modes, |
Chris Wilson | f684960 | 2010-09-19 09:29:33 +0100 | [diff] [blame] | 1839 | .set_property = intel_dp_set_property, |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 1840 | .destroy = intel_dp_destroy, |
| 1841 | }; |
| 1842 | |
| 1843 | static const struct drm_connector_helper_funcs intel_dp_connector_helper_funcs = { |
| 1844 | .get_modes = intel_dp_get_modes, |
| 1845 | .mode_valid = intel_dp_mode_valid, |
Chris Wilson | df0e924 | 2010-09-09 16:20:55 +0100 | [diff] [blame] | 1846 | .best_encoder = intel_best_encoder, |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 1847 | }; |
| 1848 | |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 1849 | static const struct drm_encoder_funcs intel_dp_enc_funcs = { |
Daniel Vetter | 24d0592 | 2010-08-20 18:08:28 +0200 | [diff] [blame] | 1850 | .destroy = intel_dp_encoder_destroy, |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 1851 | }; |
| 1852 | |
Chris Wilson | 995b676 | 2010-08-20 13:23:26 +0100 | [diff] [blame] | 1853 | static void |
Eric Anholt | 21d40d3 | 2010-03-25 11:11:14 -0700 | [diff] [blame] | 1854 | intel_dp_hot_plug(struct intel_encoder *intel_encoder) |
Keith Packard | c8110e5 | 2009-05-06 11:51:10 -0700 | [diff] [blame] | 1855 | { |
Chris Wilson | ea5b213 | 2010-08-04 13:50:23 +0100 | [diff] [blame] | 1856 | struct intel_dp *intel_dp = container_of(intel_encoder, struct intel_dp, base); |
Keith Packard | c8110e5 | 2009-05-06 11:51:10 -0700 | [diff] [blame] | 1857 | |
Jesse Barnes | 885a501 | 2011-07-07 11:11:01 -0700 | [diff] [blame] | 1858 | intel_dp_check_link_status(intel_dp); |
Keith Packard | c8110e5 | 2009-05-06 11:51:10 -0700 | [diff] [blame] | 1859 | } |
| 1860 | |
Zhenyu Wang | e3421a1 | 2010-04-08 09:43:27 +0800 | [diff] [blame] | 1861 | /* Return which DP Port should be selected for Transcoder DP control */ |
| 1862 | int |
| 1863 | intel_trans_dp_port_sel (struct drm_crtc *crtc) |
| 1864 | { |
| 1865 | struct drm_device *dev = crtc->dev; |
| 1866 | struct drm_mode_config *mode_config = &dev->mode_config; |
| 1867 | struct drm_encoder *encoder; |
Zhenyu Wang | e3421a1 | 2010-04-08 09:43:27 +0800 | [diff] [blame] | 1868 | |
| 1869 | list_for_each_entry(encoder, &mode_config->encoder_list, head) { |
Chris Wilson | ea5b213 | 2010-08-04 13:50:23 +0100 | [diff] [blame] | 1870 | struct intel_dp *intel_dp; |
| 1871 | |
Dan Carpenter | d8201ab | 2010-05-07 10:39:00 +0200 | [diff] [blame] | 1872 | if (encoder->crtc != crtc) |
Zhenyu Wang | e3421a1 | 2010-04-08 09:43:27 +0800 | [diff] [blame] | 1873 | continue; |
| 1874 | |
Chris Wilson | ea5b213 | 2010-08-04 13:50:23 +0100 | [diff] [blame] | 1875 | intel_dp = enc_to_intel_dp(encoder); |
| 1876 | if (intel_dp->base.type == INTEL_OUTPUT_DISPLAYPORT) |
| 1877 | return intel_dp->output_reg; |
Zhenyu Wang | e3421a1 | 2010-04-08 09:43:27 +0800 | [diff] [blame] | 1878 | } |
Chris Wilson | ea5b213 | 2010-08-04 13:50:23 +0100 | [diff] [blame] | 1879 | |
Zhenyu Wang | e3421a1 | 2010-04-08 09:43:27 +0800 | [diff] [blame] | 1880 | return -1; |
| 1881 | } |
| 1882 | |
Zhao Yakui | 36e83a1 | 2010-06-12 14:32:21 +0800 | [diff] [blame] | 1883 | /* check the VBT to see whether the eDP is on DP-D port */ |
Adam Jackson | cb0953d | 2010-07-16 14:46:29 -0400 | [diff] [blame] | 1884 | bool intel_dpd_is_edp(struct drm_device *dev) |
Zhao Yakui | 36e83a1 | 2010-06-12 14:32:21 +0800 | [diff] [blame] | 1885 | { |
| 1886 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 1887 | struct child_device_config *p_child; |
| 1888 | int i; |
| 1889 | |
| 1890 | if (!dev_priv->child_dev_num) |
| 1891 | return false; |
| 1892 | |
| 1893 | for (i = 0; i < dev_priv->child_dev_num; i++) { |
| 1894 | p_child = dev_priv->child_dev + i; |
| 1895 | |
| 1896 | if (p_child->dvo_port == PORT_IDPD && |
| 1897 | p_child->device_type == DEVICE_TYPE_eDP) |
| 1898 | return true; |
| 1899 | } |
| 1900 | return false; |
| 1901 | } |
| 1902 | |
Chris Wilson | f684960 | 2010-09-19 09:29:33 +0100 | [diff] [blame] | 1903 | static void |
| 1904 | intel_dp_add_properties(struct intel_dp *intel_dp, struct drm_connector *connector) |
| 1905 | { |
Chris Wilson | 3f43c48 | 2011-05-12 22:17:24 +0100 | [diff] [blame] | 1906 | intel_attach_force_audio_property(connector); |
Chris Wilson | e953fd7 | 2011-02-21 22:23:52 +0000 | [diff] [blame] | 1907 | intel_attach_broadcast_rgb_property(connector); |
Chris Wilson | f684960 | 2010-09-19 09:29:33 +0100 | [diff] [blame] | 1908 | } |
| 1909 | |
Keith Packard | c8110e5 | 2009-05-06 11:51:10 -0700 | [diff] [blame] | 1910 | void |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 1911 | intel_dp_init(struct drm_device *dev, int output_reg) |
| 1912 | { |
| 1913 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 1914 | struct drm_connector *connector; |
Chris Wilson | ea5b213 | 2010-08-04 13:50:23 +0100 | [diff] [blame] | 1915 | struct intel_dp *intel_dp; |
Eric Anholt | 21d40d3 | 2010-03-25 11:11:14 -0700 | [diff] [blame] | 1916 | struct intel_encoder *intel_encoder; |
Zhenyu Wang | 55f78c4 | 2010-03-29 16:13:57 +0800 | [diff] [blame] | 1917 | struct intel_connector *intel_connector; |
Zhenyu Wang | 5eb08b6 | 2009-07-24 01:00:31 +0800 | [diff] [blame] | 1918 | const char *name = NULL; |
Adam Jackson | b329530 | 2010-07-16 14:46:28 -0400 | [diff] [blame] | 1919 | int type; |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 1920 | |
Chris Wilson | ea5b213 | 2010-08-04 13:50:23 +0100 | [diff] [blame] | 1921 | intel_dp = kzalloc(sizeof(struct intel_dp), GFP_KERNEL); |
| 1922 | if (!intel_dp) |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 1923 | return; |
| 1924 | |
Chris Wilson | 3d3dc14 | 2011-02-12 10:33:12 +0000 | [diff] [blame] | 1925 | intel_dp->output_reg = output_reg; |
Chris Wilson | 3d3dc14 | 2011-02-12 10:33:12 +0000 | [diff] [blame] | 1926 | |
Zhenyu Wang | 55f78c4 | 2010-03-29 16:13:57 +0800 | [diff] [blame] | 1927 | intel_connector = kzalloc(sizeof(struct intel_connector), GFP_KERNEL); |
| 1928 | if (!intel_connector) { |
Chris Wilson | ea5b213 | 2010-08-04 13:50:23 +0100 | [diff] [blame] | 1929 | kfree(intel_dp); |
Zhenyu Wang | 55f78c4 | 2010-03-29 16:13:57 +0800 | [diff] [blame] | 1930 | return; |
| 1931 | } |
Chris Wilson | ea5b213 | 2010-08-04 13:50:23 +0100 | [diff] [blame] | 1932 | intel_encoder = &intel_dp->base; |
Zhenyu Wang | 55f78c4 | 2010-03-29 16:13:57 +0800 | [diff] [blame] | 1933 | |
Chris Wilson | ea5b213 | 2010-08-04 13:50:23 +0100 | [diff] [blame] | 1934 | if (HAS_PCH_SPLIT(dev) && output_reg == PCH_DP_D) |
Adam Jackson | b329530 | 2010-07-16 14:46:28 -0400 | [diff] [blame] | 1935 | if (intel_dpd_is_edp(dev)) |
Chris Wilson | ea5b213 | 2010-08-04 13:50:23 +0100 | [diff] [blame] | 1936 | intel_dp->is_pch_edp = true; |
Adam Jackson | b329530 | 2010-07-16 14:46:28 -0400 | [diff] [blame] | 1937 | |
Jesse Barnes | cfcb0fc | 2010-10-07 16:01:06 -0700 | [diff] [blame] | 1938 | if (output_reg == DP_A || is_pch_edp(intel_dp)) { |
Adam Jackson | b329530 | 2010-07-16 14:46:28 -0400 | [diff] [blame] | 1939 | type = DRM_MODE_CONNECTOR_eDP; |
| 1940 | intel_encoder->type = INTEL_OUTPUT_EDP; |
| 1941 | } else { |
| 1942 | type = DRM_MODE_CONNECTOR_DisplayPort; |
| 1943 | intel_encoder->type = INTEL_OUTPUT_DISPLAYPORT; |
| 1944 | } |
| 1945 | |
Zhenyu Wang | 55f78c4 | 2010-03-29 16:13:57 +0800 | [diff] [blame] | 1946 | connector = &intel_connector->base; |
Adam Jackson | b329530 | 2010-07-16 14:46:28 -0400 | [diff] [blame] | 1947 | drm_connector_init(dev, connector, &intel_dp_connector_funcs, type); |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 1948 | drm_connector_helper_add(connector, &intel_dp_connector_helper_funcs); |
| 1949 | |
Dave Airlie | eb1f8e4 | 2010-05-07 06:42:51 +0000 | [diff] [blame] | 1950 | connector->polled = DRM_CONNECTOR_POLL_HPD; |
| 1951 | |
Zhao Yakui | 652af9d | 2009-12-02 10:03:33 +0800 | [diff] [blame] | 1952 | if (output_reg == DP_B || output_reg == PCH_DP_B) |
Eric Anholt | 21d40d3 | 2010-03-25 11:11:14 -0700 | [diff] [blame] | 1953 | intel_encoder->clone_mask = (1 << INTEL_DP_B_CLONE_BIT); |
Zhao Yakui | 652af9d | 2009-12-02 10:03:33 +0800 | [diff] [blame] | 1954 | else if (output_reg == DP_C || output_reg == PCH_DP_C) |
Eric Anholt | 21d40d3 | 2010-03-25 11:11:14 -0700 | [diff] [blame] | 1955 | intel_encoder->clone_mask = (1 << INTEL_DP_C_CLONE_BIT); |
Zhao Yakui | 652af9d | 2009-12-02 10:03:33 +0800 | [diff] [blame] | 1956 | else if (output_reg == DP_D || output_reg == PCH_DP_D) |
Eric Anholt | 21d40d3 | 2010-03-25 11:11:14 -0700 | [diff] [blame] | 1957 | intel_encoder->clone_mask = (1 << INTEL_DP_D_CLONE_BIT); |
Ma Ling | f8aed70 | 2009-08-24 13:50:24 +0800 | [diff] [blame] | 1958 | |
Jesse Barnes | cfcb0fc | 2010-10-07 16:01:06 -0700 | [diff] [blame] | 1959 | if (is_edp(intel_dp)) |
Eric Anholt | 21d40d3 | 2010-03-25 11:11:14 -0700 | [diff] [blame] | 1960 | intel_encoder->clone_mask = (1 << INTEL_EDP_CLONE_BIT); |
Zhenyu Wang | 6251ec0 | 2010-01-12 05:38:32 +0800 | [diff] [blame] | 1961 | |
Eric Anholt | 21d40d3 | 2010-03-25 11:11:14 -0700 | [diff] [blame] | 1962 | intel_encoder->crtc_mask = (1 << 0) | (1 << 1); |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 1963 | connector->interlace_allowed = true; |
| 1964 | connector->doublescan_allowed = 0; |
| 1965 | |
Chris Wilson | 4ef69c7 | 2010-09-09 15:14:28 +0100 | [diff] [blame] | 1966 | drm_encoder_init(dev, &intel_encoder->base, &intel_dp_enc_funcs, |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 1967 | DRM_MODE_ENCODER_TMDS); |
Chris Wilson | 4ef69c7 | 2010-09-09 15:14:28 +0100 | [diff] [blame] | 1968 | drm_encoder_helper_add(&intel_encoder->base, &intel_dp_helper_funcs); |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 1969 | |
Chris Wilson | df0e924 | 2010-09-09 16:20:55 +0100 | [diff] [blame] | 1970 | intel_connector_attach_encoder(intel_connector, intel_encoder); |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 1971 | drm_sysfs_connector_add(connector); |
| 1972 | |
| 1973 | /* Set up the DDC bus. */ |
Zhenyu Wang | 5eb08b6 | 2009-07-24 01:00:31 +0800 | [diff] [blame] | 1974 | switch (output_reg) { |
Zhenyu Wang | 32f9d65 | 2009-07-24 01:00:32 +0800 | [diff] [blame] | 1975 | case DP_A: |
| 1976 | name = "DPDDC-A"; |
| 1977 | break; |
Zhenyu Wang | 5eb08b6 | 2009-07-24 01:00:31 +0800 | [diff] [blame] | 1978 | case DP_B: |
| 1979 | case PCH_DP_B: |
Jesse Barnes | b01f2c3 | 2009-12-11 11:07:17 -0800 | [diff] [blame] | 1980 | dev_priv->hotplug_supported_mask |= |
| 1981 | HDMIB_HOTPLUG_INT_STATUS; |
Zhenyu Wang | 5eb08b6 | 2009-07-24 01:00:31 +0800 | [diff] [blame] | 1982 | name = "DPDDC-B"; |
| 1983 | break; |
| 1984 | case DP_C: |
| 1985 | case PCH_DP_C: |
Jesse Barnes | b01f2c3 | 2009-12-11 11:07:17 -0800 | [diff] [blame] | 1986 | dev_priv->hotplug_supported_mask |= |
| 1987 | HDMIC_HOTPLUG_INT_STATUS; |
Zhenyu Wang | 5eb08b6 | 2009-07-24 01:00:31 +0800 | [diff] [blame] | 1988 | name = "DPDDC-C"; |
| 1989 | break; |
| 1990 | case DP_D: |
| 1991 | case PCH_DP_D: |
Jesse Barnes | b01f2c3 | 2009-12-11 11:07:17 -0800 | [diff] [blame] | 1992 | dev_priv->hotplug_supported_mask |= |
| 1993 | HDMID_HOTPLUG_INT_STATUS; |
Zhenyu Wang | 5eb08b6 | 2009-07-24 01:00:31 +0800 | [diff] [blame] | 1994 | name = "DPDDC-D"; |
| 1995 | break; |
| 1996 | } |
| 1997 | |
Chris Wilson | ea5b213 | 2010-08-04 13:50:23 +0100 | [diff] [blame] | 1998 | intel_dp_i2c_init(intel_dp, intel_connector, name); |
Zhenyu Wang | 32f9d65 | 2009-07-24 01:00:32 +0800 | [diff] [blame] | 1999 | |
Jesse Barnes | 8966738 | 2010-10-07 16:01:21 -0700 | [diff] [blame] | 2000 | /* Cache some DPCD data in the eDP case */ |
| 2001 | if (is_edp(intel_dp)) { |
| 2002 | int ret; |
Jesse Barnes | 5d61350 | 2011-01-24 17:10:54 -0800 | [diff] [blame] | 2003 | u32 pp_on, pp_div; |
Jesse Barnes | 8966738 | 2010-10-07 16:01:21 -0700 | [diff] [blame] | 2004 | |
Jesse Barnes | 5d61350 | 2011-01-24 17:10:54 -0800 | [diff] [blame] | 2005 | pp_on = I915_READ(PCH_PP_ON_DELAYS); |
| 2006 | pp_div = I915_READ(PCH_PP_DIVISOR); |
| 2007 | |
| 2008 | /* Get T3 & T12 values (note: VESA not bspec terminology) */ |
| 2009 | dev_priv->panel_t3 = (pp_on & 0x1fff0000) >> 16; |
| 2010 | dev_priv->panel_t3 /= 10; /* t3 in 100us units */ |
| 2011 | dev_priv->panel_t12 = pp_div & 0xf; |
| 2012 | dev_priv->panel_t12 *= 100; /* t12 in 100ms units */ |
| 2013 | |
| 2014 | ironlake_edp_panel_vdd_on(intel_dp); |
Jesse Barnes | 8966738 | 2010-10-07 16:01:21 -0700 | [diff] [blame] | 2015 | ret = intel_dp_aux_native_read(intel_dp, DP_DPCD_REV, |
| 2016 | intel_dp->dpcd, |
| 2017 | sizeof(intel_dp->dpcd)); |
Chris Wilson | 3d3dc14 | 2011-02-12 10:33:12 +0000 | [diff] [blame] | 2018 | ironlake_edp_panel_vdd_off(intel_dp); |
Jesse Barnes | 8966738 | 2010-10-07 16:01:21 -0700 | [diff] [blame] | 2019 | if (ret == sizeof(intel_dp->dpcd)) { |
Jesse Barnes | 7183dc2 | 2011-07-07 11:10:58 -0700 | [diff] [blame] | 2020 | if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11) |
| 2021 | dev_priv->no_aux_handshake = |
| 2022 | intel_dp->dpcd[DP_MAX_DOWNSPREAD] & |
Jesse Barnes | 8966738 | 2010-10-07 16:01:21 -0700 | [diff] [blame] | 2023 | DP_NO_AUX_HANDSHAKE_LINK_TRAINING; |
| 2024 | } else { |
Chris Wilson | 3d3dc14 | 2011-02-12 10:33:12 +0000 | [diff] [blame] | 2025 | /* if this fails, presume the device is a ghost */ |
Takashi Iwai | 48898b0 | 2011-03-18 09:06:49 +0000 | [diff] [blame] | 2026 | DRM_INFO("failed to retrieve link info, disabling eDP\n"); |
Chris Wilson | 3d3dc14 | 2011-02-12 10:33:12 +0000 | [diff] [blame] | 2027 | intel_dp_encoder_destroy(&intel_dp->base.base); |
Takashi Iwai | 48898b0 | 2011-03-18 09:06:49 +0000 | [diff] [blame] | 2028 | intel_dp_destroy(&intel_connector->base); |
Chris Wilson | 3d3dc14 | 2011-02-12 10:33:12 +0000 | [diff] [blame] | 2029 | return; |
Jesse Barnes | 8966738 | 2010-10-07 16:01:21 -0700 | [diff] [blame] | 2030 | } |
Jesse Barnes | 8966738 | 2010-10-07 16:01:21 -0700 | [diff] [blame] | 2031 | } |
| 2032 | |
Eric Anholt | 21d40d3 | 2010-03-25 11:11:14 -0700 | [diff] [blame] | 2033 | intel_encoder->hot_plug = intel_dp_hot_plug; |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 2034 | |
Jesse Barnes | 4d92646 | 2010-10-07 16:01:07 -0700 | [diff] [blame] | 2035 | if (is_edp(intel_dp)) { |
Zhenyu Wang | 32f9d65 | 2009-07-24 01:00:32 +0800 | [diff] [blame] | 2036 | /* initialize panel mode from VBT if available for eDP */ |
| 2037 | if (dev_priv->lfp_lvds_vbt_mode) { |
| 2038 | dev_priv->panel_fixed_mode = |
| 2039 | drm_mode_duplicate(dev, dev_priv->lfp_lvds_vbt_mode); |
| 2040 | if (dev_priv->panel_fixed_mode) { |
| 2041 | dev_priv->panel_fixed_mode->type |= |
| 2042 | DRM_MODE_TYPE_PREFERRED; |
| 2043 | } |
| 2044 | } |
| 2045 | } |
| 2046 | |
Chris Wilson | f684960 | 2010-09-19 09:29:33 +0100 | [diff] [blame] | 2047 | intel_dp_add_properties(intel_dp, connector); |
| 2048 | |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 2049 | /* For G4X desktop chip, PEG_BAND_GAP_DATA 3:0 must first be written |
| 2050 | * 0xd. Failure to do so will result in spurious interrupts being |
| 2051 | * generated on the port when a cable is not attached. |
| 2052 | */ |
| 2053 | if (IS_G4X(dev) && !IS_GM45(dev)) { |
| 2054 | u32 temp = I915_READ(PEG_BAND_GAP_DATA); |
| 2055 | I915_WRITE(PEG_BAND_GAP_DATA, (temp & ~0xf) | 0xd); |
| 2056 | } |
| 2057 | } |