blob: 57a5441ccabd4e3191265249008eaa2bac468333 [file] [log] [blame]
Dhaval Patel83e27fc2013-12-19 14:52:24 -08001/* Copyright (c) 2013-2014, The Linux Foundation. All rights reserved.
2 *
3 * This program is free software; you can redistribute it and/or modify
4 * it under the terms of the GNU General Public License version 2 and
5 * only version 2 as published by the Free Software Foundation.
6 *
7 * This program is distributed in the hope that it will be useful,
8 * but WITHOUT ANY WARRANTY; without even the implied warranty of
9 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
10 * GNU General Public License for more details.
11 */
12
13#ifndef __MDSS_PLL_H
14#define __MDSS_PLL_H
15
16#include <linux/mdss_io_util.h>
17#include <linux/io.h>
18
19#define MDSS_PLL_REG_W(base, offset, data) \
20 writel_relaxed((data), (base) + (offset))
21#define MDSS_PLL_REG_R(base, offset) readl_relaxed((base) + (offset))
22
23enum {
Padmanabhan Komandurua7b90d12014-03-27 20:03:11 +053024 MDSS_DSI_PLL_LPM,
25 MDSS_DSI_PLL_HPM,
Dhaval Patel83e27fc2013-12-19 14:52:24 -080026 MDSS_EDP_PLL,
27 MDSS_HDMI_PLL,
28 MDSS_UNKNOWN_PLL,
29};
30
Padmanabhan Komandurua7b90d12014-03-27 20:03:11 +053031enum {
32 MDSS_PLL_TARGET_8974,
33 MDSS_PLL_TARGET_8916,
34};
35
Dhaval Patel83e27fc2013-12-19 14:52:24 -080036struct mdss_pll_resources {
37
38 /* Pll specific resources like GPIO, power supply, clocks, etc*/
39 struct dss_module_power mp;
40
41 /* dsi/edp/hmdi plls' base register and phy register mapping */
42 void __iomem *pll_base;
43 void __iomem *phy_base;
44
45 /*
46 * Certain pll's needs to update the same vco rate after resume in
47 * suspend/resume scenario. Cached the vco rate for such plls.
48 */
49 unsigned long vco_cached_rate;
50
51 /* dsi/edp/hmdi pll interface type */
52 u32 pll_interface_type;
53
54 /*
Padmanabhan Komandurua7b90d12014-03-27 20:03:11 +053055 * Target ID. Used in pll_register API for valid target check before
56 * registering the PLL clocks.
57 */
58 u32 target_id;
59
60 /* HW recommended delay during configuration of vco clock rate */
61 u32 vco_delay;
62
Padmanabhan Komanduru99fa0d72014-05-05 19:48:23 +053063 /* Ref-count of the PLL resources */
64 u32 resource_ref_cnt;
65
Padmanabhan Komandurua7b90d12014-03-27 20:03:11 +053066 /*
Dhaval Patel83e27fc2013-12-19 14:52:24 -080067 * Keep track to resource status to avoid updating same status for the
68 * pll from different paths
69 */
70 bool resource_enable;
71
72 /*
73 * Certain plls' do not allow vco rate update if it is on. Keep track of
74 * status for them to turn on/off after set rate success.
75 */
76 bool pll_on;
77
78 /*
79 * handoff_status is true of pll is already enabled by bootloader with
80 * continuous splash enable case. Clock API will call the handoff API
81 * to enable the status. It is disabled if continuous splash
82 * feature is disabled.
83 */
84 bool handoff_resources;
Dhaval Patel83e27fc2013-12-19 14:52:24 -080085};
86
87int mdss_pll_resource_enable(struct mdss_pll_resources *pll_res, bool enable);
88int mdss_pll_util_resource_init(struct platform_device *pdev,
89 struct mdss_pll_resources *pll_res);
90void mdss_pll_util_resource_deinit(struct platform_device *pdev,
91 struct mdss_pll_resources *pll_res);
92void mdss_pll_util_resource_release(struct platform_device *pdev,
93 struct mdss_pll_resources *pll_res);
94int mdss_pll_util_resource_enable(struct mdss_pll_resources *pll_res,
95 bool enable);
96int mdss_pll_util_resource_parse(struct platform_device *pdev,
97 struct mdss_pll_resources *pll_res);
98#endif