blob: 5a40f2d78beb1a9114478ac9e0385556c29d30bf [file] [log] [blame]
Linus Torvalds1da177e2005-04-16 15:20:36 -07001/* starfire.c: Linux device driver for the Adaptec Starfire network adapter. */
2/*
3 Written 1998-2000 by Donald Becker.
4
Jeff Garzikfdecea62005-05-12 20:16:24 -04005 Current maintainer is Ion Badulescu <ionut ta badula tod org>. Please
Linus Torvalds1da177e2005-04-16 15:20:36 -07006 send all bug reports to me, and not to Donald Becker, as this code
7 has been heavily modified from Donald's original version.
8
9 This software may be used and distributed according to the terms of
10 the GNU General Public License (GPL), incorporated herein by reference.
11 Drivers based on or derived from this code fall under the GPL and must
12 retain the authorship, copyright and license notice. This file is not
13 a complete program and may only be used when the entire operating
14 system is licensed under the GPL.
15
16 The information below comes from Donald Becker's original driver:
17
18 The author may be reached as becker@scyld.com, or C/O
19 Scyld Computing Corporation
20 410 Severn Ave., Suite 210
21 Annapolis MD 21403
22
23 Support and updates available at
24 http://www.scyld.com/network/starfire.html
Jeff Garzik03a8c662006-06-27 07:57:22 -040025 [link no longer provides useful info -jgarzik]
Linus Torvalds1da177e2005-04-16 15:20:36 -070026
Linus Torvalds1da177e2005-04-16 15:20:36 -070027*/
28
29#define DRV_NAME "starfire"
Francois Romieua6676012008-07-06 20:54:45 -070030#define DRV_VERSION "2.1"
31#define DRV_RELDATE "July 6, 2008"
Linus Torvalds1da177e2005-04-16 15:20:36 -070032
Linus Torvalds1da177e2005-04-16 15:20:36 -070033#include <linux/module.h>
34#include <linux/kernel.h>
35#include <linux/pci.h>
36#include <linux/netdevice.h>
37#include <linux/etherdevice.h>
38#include <linux/init.h>
39#include <linux/delay.h>
Jeff Garzikfdecea62005-05-12 20:16:24 -040040#include <linux/crc32.h>
41#include <linux/ethtool.h>
42#include <linux/mii.h>
43#include <linux/if_vlan.h>
Al Virod7fe0f22006-12-03 23:15:30 -050044#include <linux/mm.h>
Linus Torvalds1da177e2005-04-16 15:20:36 -070045#include <asm/processor.h> /* Processor type for cache alignment. */
46#include <asm/uaccess.h>
47#include <asm/io.h>
48
Jeff Garzikfdecea62005-05-12 20:16:24 -040049#include "starfire_firmware.h"
Linus Torvalds1da177e2005-04-16 15:20:36 -070050/*
51 * The current frame processor firmware fails to checksum a fragment
52 * of length 1. If and when this is fixed, the #define below can be removed.
53 */
54#define HAS_BROKEN_FIRMWARE
Ion Badulescu67974232005-10-03 22:31:36 -040055
56/*
57 * If using the broken firmware, data must be padded to the next 32-bit boundary.
58 */
59#ifdef HAS_BROKEN_FIRMWARE
60#define PADDING_MASK 3
61#endif
62
Linus Torvalds1da177e2005-04-16 15:20:36 -070063/*
64 * Define this if using the driver with the zero-copy patch
65 */
Linus Torvalds1da177e2005-04-16 15:20:36 -070066#define ZEROCOPY
Linus Torvalds1da177e2005-04-16 15:20:36 -070067
68#if defined(CONFIG_VLAN_8021Q) || defined(CONFIG_VLAN_8021Q_MODULE)
69#define VLAN_SUPPORT
70#endif
71
Linus Torvalds1da177e2005-04-16 15:20:36 -070072/* The user-configurable values.
73 These may be modified when a driver module is loaded.*/
74
75/* Used for tuning interrupt latency vs. overhead. */
76static int intr_latency;
77static int small_frames;
78
79static int debug = 1; /* 1 normal messages, 0 quiet .. 7 verbose. */
80static int max_interrupt_work = 20;
81static int mtu;
82/* Maximum number of multicast addresses to filter (vs. rx-all-multicast).
83 The Starfire has a 512 element hash table based on the Ethernet CRC. */
Arjan van de Venf71e1302006-03-03 21:33:57 -050084static const int multicast_filter_limit = 512;
Linus Torvalds1da177e2005-04-16 15:20:36 -070085/* Whether to do TCP/UDP checksums in hardware */
Linus Torvalds1da177e2005-04-16 15:20:36 -070086static int enable_hw_cksum = 1;
Linus Torvalds1da177e2005-04-16 15:20:36 -070087
88#define PKT_BUF_SZ 1536 /* Size of each temporary Rx buffer.*/
89/*
90 * Set the copy breakpoint for the copy-only-tiny-frames scheme.
91 * Setting to > 1518 effectively disables this feature.
92 *
93 * NOTE:
94 * The ia64 doesn't allow for unaligned loads even of integers being
95 * misaligned on a 2 byte boundary. Thus always force copying of
96 * packets as the starfire doesn't allow for misaligned DMAs ;-(
97 * 23/10/2000 - Jes
98 *
99 * The Alpha and the Sparc don't like unaligned loads, either. On Sparc64,
100 * at least, having unaligned frames leads to a rather serious performance
101 * penalty. -Ion
102 */
103#if defined(__ia64__) || defined(__alpha__) || defined(__sparc__)
104static int rx_copybreak = PKT_BUF_SZ;
105#else
106static int rx_copybreak /* = 0 */;
107#endif
108
109/* PCI DMA burst size -- on sparc64 we want to force it to 64 bytes, on the others the default of 128 is fine. */
110#ifdef __sparc__
111#define DMA_BURST_SIZE 64
112#else
113#define DMA_BURST_SIZE 128
114#endif
115
116/* Used to pass the media type, etc.
117 Both 'options[]' and 'full_duplex[]' exist for driver interoperability.
118 The media type is usually passed in 'options[]'.
119 These variables are deprecated, use ethtool instead. -Ion
120*/
121#define MAX_UNITS 8 /* More are supported, limit only on options */
122static int options[MAX_UNITS] = {0, };
123static int full_duplex[MAX_UNITS] = {0, };
124
125/* Operational parameters that are set at compile time. */
126
127/* The "native" ring sizes are either 256 or 2048.
128 However in some modes a descriptor may be marked to wrap the ring earlier.
129*/
130#define RX_RING_SIZE 256
131#define TX_RING_SIZE 32
132/* The completion queues are fixed at 1024 entries i.e. 4K or 8KB. */
133#define DONE_Q_SIZE 1024
134/* All queues must be aligned on a 256-byte boundary */
135#define QUEUE_ALIGN 256
136
137#if RX_RING_SIZE > 256
138#define RX_Q_ENTRIES Rx2048QEntries
139#else
140#define RX_Q_ENTRIES Rx256QEntries
141#endif
142
143/* Operational parameters that usually are not changed. */
144/* Time in jiffies before concluding the transmitter is hung. */
145#define TX_TIMEOUT (2 * HZ)
146
147/*
148 * This SUCKS.
149 * We need a much better method to determine if dma_addr_t is 64-bit.
150 */
maximilian attems983b7dc2007-06-24 23:36:45 +0200151#if (defined(__i386__) && defined(CONFIG_HIGHMEM64G)) || defined(__x86_64__) || defined (__ia64__) || defined(__alpha__) || defined(__mips64__) || (defined(__mips__) && defined(CONFIG_HIGHMEM) && defined(CONFIG_64BIT_PHYS_ADDR))
Linus Torvalds1da177e2005-04-16 15:20:36 -0700152/* 64-bit dma_addr_t */
153#define ADDR_64BITS /* This chip uses 64 bit addresses. */
Al Viro88b19432007-08-23 02:29:45 -0400154#define netdrv_addr_t __le64
Linus Torvalds1da177e2005-04-16 15:20:36 -0700155#define cpu_to_dma(x) cpu_to_le64(x)
156#define dma_to_cpu(x) le64_to_cpu(x)
157#define RX_DESC_Q_ADDR_SIZE RxDescQAddr64bit
158#define TX_DESC_Q_ADDR_SIZE TxDescQAddr64bit
159#define RX_COMPL_Q_ADDR_SIZE RxComplQAddr64bit
160#define TX_COMPL_Q_ADDR_SIZE TxComplQAddr64bit
161#define RX_DESC_ADDR_SIZE RxDescAddr64bit
162#else /* 32-bit dma_addr_t */
Al Viro88b19432007-08-23 02:29:45 -0400163#define netdrv_addr_t __le32
Linus Torvalds1da177e2005-04-16 15:20:36 -0700164#define cpu_to_dma(x) cpu_to_le32(x)
165#define dma_to_cpu(x) le32_to_cpu(x)
166#define RX_DESC_Q_ADDR_SIZE RxDescQAddr32bit
167#define TX_DESC_Q_ADDR_SIZE TxDescQAddr32bit
168#define RX_COMPL_Q_ADDR_SIZE RxComplQAddr32bit
169#define TX_COMPL_Q_ADDR_SIZE TxComplQAddr32bit
170#define RX_DESC_ADDR_SIZE RxDescAddr32bit
171#endif
172
Linus Torvalds1da177e2005-04-16 15:20:36 -0700173#define skb_first_frag_len(skb) skb_headlen(skb)
174#define skb_num_frags(skb) (skb_shinfo(skb)->nr_frags + 1)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700175
Linus Torvalds1da177e2005-04-16 15:20:36 -0700176/* These identify the driver base version and may not be removed. */
Andrew Mortonda219b72008-02-09 23:42:17 -0800177static char version[] =
Linus Torvalds1da177e2005-04-16 15:20:36 -0700178KERN_INFO "starfire.c:v1.03 7/26/2000 Written by Donald Becker <becker@scyld.com>\n"
179KERN_INFO " (unofficial 2.2/2.4 kernel port, version " DRV_VERSION ", " DRV_RELDATE ")\n";
180
181MODULE_AUTHOR("Donald Becker <becker@scyld.com>");
182MODULE_DESCRIPTION("Adaptec Starfire Ethernet driver");
183MODULE_LICENSE("GPL");
Jeff Garzikfdecea62005-05-12 20:16:24 -0400184MODULE_VERSION(DRV_VERSION);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700185
186module_param(max_interrupt_work, int, 0);
187module_param(mtu, int, 0);
188module_param(debug, int, 0);
189module_param(rx_copybreak, int, 0);
190module_param(intr_latency, int, 0);
191module_param(small_frames, int, 0);
192module_param_array(options, int, NULL, 0);
193module_param_array(full_duplex, int, NULL, 0);
194module_param(enable_hw_cksum, int, 0);
195MODULE_PARM_DESC(max_interrupt_work, "Maximum events handled per interrupt");
196MODULE_PARM_DESC(mtu, "MTU (all boards)");
197MODULE_PARM_DESC(debug, "Debug level (0-6)");
198MODULE_PARM_DESC(rx_copybreak, "Copy breakpoint for copy-only-tiny-frames");
199MODULE_PARM_DESC(intr_latency, "Maximum interrupt latency, in microseconds");
200MODULE_PARM_DESC(small_frames, "Maximum size of receive frames that bypass interrupt latency (0,64,128,256,512)");
201MODULE_PARM_DESC(options, "Deprecated: Bits 0-3: media type, bit 17: full duplex");
202MODULE_PARM_DESC(full_duplex, "Deprecated: Forced full-duplex setting (0/1)");
203MODULE_PARM_DESC(enable_hw_cksum, "Enable/disable hardware cksum support (0/1)");
204
205/*
206 Theory of Operation
207
208I. Board Compatibility
209
210This driver is for the Adaptec 6915 "Starfire" 64 bit PCI Ethernet adapter.
211
212II. Board-specific settings
213
214III. Driver operation
215
216IIIa. Ring buffers
217
218The Starfire hardware uses multiple fixed-size descriptor queues/rings. The
219ring sizes are set fixed by the hardware, but may optionally be wrapped
220earlier by the END bit in the descriptor.
221This driver uses that hardware queue size for the Rx ring, where a large
222number of entries has no ill effect beyond increases the potential backlog.
223The Tx ring is wrapped with the END bit, since a large hardware Tx queue
224disables the queue layer priority ordering and we have no mechanism to
225utilize the hardware two-level priority queue. When modifying the
226RX/TX_RING_SIZE pay close attention to page sizes and the ring-empty warning
227levels.
228
229IIIb/c. Transmit/Receive Structure
230
231See the Adaptec manual for the many possible structures, and options for
232each structure. There are far too many to document all of them here.
233
234For transmit this driver uses type 0/1 transmit descriptors (depending
235on the 32/64 bitness of the architecture), and relies on automatic
236minimum-length padding. It does not use the completion queue
237consumer index, but instead checks for non-zero status entries.
238
Jeff Garzikfdecea62005-05-12 20:16:24 -0400239For receive this driver uses type 2/3 receive descriptors. The driver
Linus Torvalds1da177e2005-04-16 15:20:36 -0700240allocates full frame size skbuffs for the Rx ring buffers, so all frames
241should fit in a single descriptor. The driver does not use the completion
242queue consumer index, but instead checks for non-zero status entries.
243
244When an incoming frame is less than RX_COPYBREAK bytes long, a fresh skbuff
245is allocated and the frame is copied to the new skbuff. When the incoming
246frame is larger, the skbuff is passed directly up the protocol stack.
247Buffers consumed this way are replaced by newly allocated skbuffs in a later
248phase of receive.
249
250A notable aspect of operation is that unaligned buffers are not permitted by
251the Starfire hardware. Thus the IP header at offset 14 in an ethernet frame
252isn't longword aligned, which may cause problems on some machine
253e.g. Alphas and IA64. For these architectures, the driver is forced to copy
254the frame into a new skbuff unconditionally. Copied frames are put into the
255skbuff at an offset of "+2", thus 16-byte aligning the IP header.
256
257IIId. Synchronization
258
259The driver runs as two independent, single-threaded flows of control. One
260is the send-packet routine, which enforces single-threaded use by the
261dev->tbusy flag. The other thread is the interrupt handler, which is single
262threaded by the hardware and interrupt handling software.
263
264The send packet thread has partial control over the Tx ring and the netif_queue
265status. If the number of free Tx slots in the ring falls below a certain number
266(currently hardcoded to 4), it signals the upper layer to stop the queue.
267
268The interrupt handler has exclusive control over the Rx ring and records stats
269from the Tx ring. After reaping the stats, it marks the Tx queue entry as
270empty by incrementing the dirty_tx mark. Iff the netif_queue is stopped and the
271number of free Tx slow is above the threshold, it signals the upper layer to
272restart the queue.
273
274IV. Notes
275
276IVb. References
277
278The Adaptec Starfire manuals, available only from Adaptec.
279http://www.scyld.com/expert/100mbps.html
280http://www.scyld.com/expert/NWay.html
281
282IVc. Errata
283
284- StopOnPerr is broken, don't enable
285- Hardware ethernet padding exposes random data, perform software padding
286 instead (unverified -- works correctly for all the hardware I have)
287
288*/
289
Jeff Garzikfdecea62005-05-12 20:16:24 -0400290
Linus Torvalds1da177e2005-04-16 15:20:36 -0700291
292enum chip_capability_flags {CanHaveMII=1, };
293
294enum chipset {
295 CH_6915 = 0,
296};
297
298static struct pci_device_id starfire_pci_tbl[] = {
299 { 0x9004, 0x6915, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_6915 },
300 { 0, }
301};
302MODULE_DEVICE_TABLE(pci, starfire_pci_tbl);
303
304/* A chip capabilities table, matching the CH_xxx entries in xxx_pci_tbl[] above. */
Arjan van de Venf71e1302006-03-03 21:33:57 -0500305static const struct chip_info {
Linus Torvalds1da177e2005-04-16 15:20:36 -0700306 const char *name;
307 int drv_flags;
308} netdrv_tbl[] __devinitdata = {
309 { "Adaptec Starfire 6915", CanHaveMII },
310};
311
312
313/* Offsets to the device registers.
314 Unlike software-only systems, device drivers interact with complex hardware.
315 It's not useful to define symbolic names for every register bit in the
316 device. The name can only partially document the semantics and make
317 the driver longer and more difficult to read.
318 In general, only the important configuration values or bits changed
319 multiple times should be defined symbolically.
320*/
321enum register_offsets {
322 PCIDeviceConfig=0x50040, GenCtrl=0x50070, IntrTimerCtrl=0x50074,
323 IntrClear=0x50080, IntrStatus=0x50084, IntrEnable=0x50088,
324 MIICtrl=0x52000, TxStationAddr=0x50120, EEPROMCtrl=0x51000,
325 GPIOCtrl=0x5008C, TxDescCtrl=0x50090,
326 TxRingPtr=0x50098, HiPriTxRingPtr=0x50094, /* Low and High priority. */
327 TxRingHiAddr=0x5009C, /* 64 bit address extension. */
328 TxProducerIdx=0x500A0, TxConsumerIdx=0x500A4,
329 TxThreshold=0x500B0,
330 CompletionHiAddr=0x500B4, TxCompletionAddr=0x500B8,
331 RxCompletionAddr=0x500BC, RxCompletionQ2Addr=0x500C0,
332 CompletionQConsumerIdx=0x500C4, RxDMACtrl=0x500D0,
333 RxDescQCtrl=0x500D4, RxDescQHiAddr=0x500DC, RxDescQAddr=0x500E0,
334 RxDescQIdx=0x500E8, RxDMAStatus=0x500F0, RxFilterMode=0x500F4,
335 TxMode=0x55000, VlanType=0x55064,
336 PerfFilterTable=0x56000, HashTable=0x56100,
337 TxGfpMem=0x58000, RxGfpMem=0x5a000,
338};
339
340/*
341 * Bits in the interrupt status/mask registers.
342 * Warning: setting Intr[Ab]NormalSummary in the IntrEnable register
343 * enables all the interrupt sources that are or'ed into those status bits.
344 */
345enum intr_status_bits {
346 IntrLinkChange=0xf0000000, IntrStatsMax=0x08000000,
347 IntrAbnormalSummary=0x02000000, IntrGeneralTimer=0x01000000,
348 IntrSoftware=0x800000, IntrRxComplQ1Low=0x400000,
349 IntrTxComplQLow=0x200000, IntrPCI=0x100000,
350 IntrDMAErr=0x080000, IntrTxDataLow=0x040000,
351 IntrRxComplQ2Low=0x020000, IntrRxDescQ1Low=0x010000,
352 IntrNormalSummary=0x8000, IntrTxDone=0x4000,
353 IntrTxDMADone=0x2000, IntrTxEmpty=0x1000,
354 IntrEarlyRxQ2=0x0800, IntrEarlyRxQ1=0x0400,
355 IntrRxQ2Done=0x0200, IntrRxQ1Done=0x0100,
356 IntrRxGFPDead=0x80, IntrRxDescQ2Low=0x40,
357 IntrNoTxCsum=0x20, IntrTxBadID=0x10,
358 IntrHiPriTxBadID=0x08, IntrRxGfp=0x04,
359 IntrTxGfp=0x02, IntrPCIPad=0x01,
360 /* not quite bits */
361 IntrRxDone=IntrRxQ2Done | IntrRxQ1Done,
362 IntrRxEmpty=IntrRxDescQ1Low | IntrRxDescQ2Low,
363 IntrNormalMask=0xff00, IntrAbnormalMask=0x3ff00fe,
364};
365
366/* Bits in the RxFilterMode register. */
367enum rx_mode_bits {
368 AcceptBroadcast=0x04, AcceptAllMulticast=0x02, AcceptAll=0x01,
369 AcceptMulticast=0x10, PerfectFilter=0x40, HashFilter=0x30,
370 PerfectFilterVlan=0x80, MinVLANPrio=0xE000, VlanMode=0x0200,
371 WakeupOnGFP=0x0800,
372};
373
374/* Bits in the TxMode register */
375enum tx_mode_bits {
376 MiiSoftReset=0x8000, MIILoopback=0x4000,
377 TxFlowEnable=0x0800, RxFlowEnable=0x0400,
378 PadEnable=0x04, FullDuplex=0x02, HugeFrame=0x01,
379};
380
381/* Bits in the TxDescCtrl register. */
382enum tx_ctrl_bits {
383 TxDescSpaceUnlim=0x00, TxDescSpace32=0x10, TxDescSpace64=0x20,
384 TxDescSpace128=0x30, TxDescSpace256=0x40,
385 TxDescType0=0x00, TxDescType1=0x01, TxDescType2=0x02,
386 TxDescType3=0x03, TxDescType4=0x04,
387 TxNoDMACompletion=0x08,
388 TxDescQAddr64bit=0x80, TxDescQAddr32bit=0,
389 TxHiPriFIFOThreshShift=24, TxPadLenShift=16,
390 TxDMABurstSizeShift=8,
391};
392
393/* Bits in the RxDescQCtrl register. */
394enum rx_ctrl_bits {
395 RxBufferLenShift=16, RxMinDescrThreshShift=0,
396 RxPrefetchMode=0x8000, RxVariableQ=0x2000,
397 Rx2048QEntries=0x4000, Rx256QEntries=0,
398 RxDescAddr64bit=0x1000, RxDescAddr32bit=0,
399 RxDescQAddr64bit=0x0100, RxDescQAddr32bit=0,
400 RxDescSpace4=0x000, RxDescSpace8=0x100,
401 RxDescSpace16=0x200, RxDescSpace32=0x300,
402 RxDescSpace64=0x400, RxDescSpace128=0x500,
403 RxConsumerWrEn=0x80,
404};
405
406/* Bits in the RxDMACtrl register. */
407enum rx_dmactrl_bits {
408 RxReportBadFrames=0x80000000, RxDMAShortFrames=0x40000000,
409 RxDMABadFrames=0x20000000, RxDMACrcErrorFrames=0x10000000,
410 RxDMAControlFrame=0x08000000, RxDMAPauseFrame=0x04000000,
411 RxChecksumIgnore=0, RxChecksumRejectTCPUDP=0x02000000,
412 RxChecksumRejectTCPOnly=0x01000000,
413 RxCompletionQ2Enable=0x800000,
414 RxDMAQ2Disable=0, RxDMAQ2FPOnly=0x100000,
415 RxDMAQ2SmallPkt=0x200000, RxDMAQ2HighPrio=0x300000,
416 RxDMAQ2NonIP=0x400000,
417 RxUseBackupQueue=0x080000, RxDMACRC=0x040000,
418 RxEarlyIntThreshShift=12, RxHighPrioThreshShift=8,
419 RxBurstSizeShift=0,
420};
421
422/* Bits in the RxCompletionAddr register */
423enum rx_compl_bits {
424 RxComplQAddr64bit=0x80, RxComplQAddr32bit=0,
425 RxComplProducerWrEn=0x40,
426 RxComplType0=0x00, RxComplType1=0x10,
427 RxComplType2=0x20, RxComplType3=0x30,
428 RxComplThreshShift=0,
429};
430
431/* Bits in the TxCompletionAddr register */
432enum tx_compl_bits {
433 TxComplQAddr64bit=0x80, TxComplQAddr32bit=0,
434 TxComplProducerWrEn=0x40,
435 TxComplIntrStatus=0x20,
436 CommonQueueMode=0x10,
437 TxComplThreshShift=0,
438};
439
440/* Bits in the GenCtrl register */
441enum gen_ctrl_bits {
442 RxEnable=0x05, TxEnable=0x0a,
443 RxGFPEnable=0x10, TxGFPEnable=0x20,
444};
445
446/* Bits in the IntrTimerCtrl register */
447enum intr_ctrl_bits {
448 Timer10X=0x800, EnableIntrMasking=0x60, SmallFrameBypass=0x100,
449 SmallFrame64=0, SmallFrame128=0x200, SmallFrame256=0x400, SmallFrame512=0x600,
450 IntrLatencyMask=0x1f,
451};
452
453/* The Rx and Tx buffer descriptors. */
454struct starfire_rx_desc {
Al Viro88b19432007-08-23 02:29:45 -0400455 netdrv_addr_t rxaddr;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700456};
457enum rx_desc_bits {
458 RxDescValid=1, RxDescEndRing=2,
459};
460
461/* Completion queue entry. */
462struct short_rx_done_desc {
Al Viro88b19432007-08-23 02:29:45 -0400463 __le32 status; /* Low 16 bits is length. */
Linus Torvalds1da177e2005-04-16 15:20:36 -0700464};
465struct basic_rx_done_desc {
Al Viro88b19432007-08-23 02:29:45 -0400466 __le32 status; /* Low 16 bits is length. */
467 __le16 vlanid;
468 __le16 status2;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700469};
470struct csum_rx_done_desc {
Al Viro88b19432007-08-23 02:29:45 -0400471 __le32 status; /* Low 16 bits is length. */
472 __le16 csum; /* Partial checksum */
473 __le16 status2;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700474};
475struct full_rx_done_desc {
Al Viro88b19432007-08-23 02:29:45 -0400476 __le32 status; /* Low 16 bits is length. */
477 __le16 status3;
478 __le16 status2;
479 __le16 vlanid;
480 __le16 csum; /* partial checksum */
481 __le32 timestamp;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700482};
483/* XXX: this is ugly and I'm not sure it's worth the trouble -Ion */
Linus Torvalds1da177e2005-04-16 15:20:36 -0700484#ifdef VLAN_SUPPORT
485typedef struct full_rx_done_desc rx_done_desc;
486#define RxComplType RxComplType3
487#else /* not VLAN_SUPPORT */
488typedef struct csum_rx_done_desc rx_done_desc;
489#define RxComplType RxComplType2
490#endif /* not VLAN_SUPPORT */
Linus Torvalds1da177e2005-04-16 15:20:36 -0700491
492enum rx_done_bits {
493 RxOK=0x20000000, RxFIFOErr=0x10000000, RxBufQ2=0x08000000,
494};
495
496/* Type 1 Tx descriptor. */
497struct starfire_tx_desc_1 {
Al Viro88b19432007-08-23 02:29:45 -0400498 __le32 status; /* Upper bits are status, lower 16 length. */
499 __le32 addr;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700500};
501
502/* Type 2 Tx descriptor. */
503struct starfire_tx_desc_2 {
Al Viro88b19432007-08-23 02:29:45 -0400504 __le32 status; /* Upper bits are status, lower 16 length. */
505 __le32 reserved;
506 __le64 addr;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700507};
508
509#ifdef ADDR_64BITS
510typedef struct starfire_tx_desc_2 starfire_tx_desc;
511#define TX_DESC_TYPE TxDescType2
512#else /* not ADDR_64BITS */
513typedef struct starfire_tx_desc_1 starfire_tx_desc;
514#define TX_DESC_TYPE TxDescType1
515#endif /* not ADDR_64BITS */
516#define TX_DESC_SPACING TxDescSpaceUnlim
517
518enum tx_desc_bits {
519 TxDescID=0xB0000000,
520 TxCRCEn=0x01000000, TxDescIntr=0x08000000,
521 TxRingWrap=0x04000000, TxCalTCP=0x02000000,
522};
523struct tx_done_desc {
Al Viro88b19432007-08-23 02:29:45 -0400524 __le32 status; /* timestamp, index. */
Linus Torvalds1da177e2005-04-16 15:20:36 -0700525#if 0
Al Viro88b19432007-08-23 02:29:45 -0400526 __le32 intrstatus; /* interrupt status */
Linus Torvalds1da177e2005-04-16 15:20:36 -0700527#endif
528};
529
530struct rx_ring_info {
531 struct sk_buff *skb;
532 dma_addr_t mapping;
533};
534struct tx_ring_info {
535 struct sk_buff *skb;
536 dma_addr_t mapping;
537 unsigned int used_slots;
538};
539
540#define PHY_CNT 2
541struct netdev_private {
542 /* Descriptor rings first for alignment. */
543 struct starfire_rx_desc *rx_ring;
544 starfire_tx_desc *tx_ring;
545 dma_addr_t rx_ring_dma;
546 dma_addr_t tx_ring_dma;
547 /* The addresses of rx/tx-in-place skbuffs. */
548 struct rx_ring_info rx_info[RX_RING_SIZE];
549 struct tx_ring_info tx_info[TX_RING_SIZE];
550 /* Pointers to completion queues (full pages). */
551 rx_done_desc *rx_done_q;
552 dma_addr_t rx_done_q_dma;
553 unsigned int rx_done;
554 struct tx_done_desc *tx_done_q;
555 dma_addr_t tx_done_q_dma;
556 unsigned int tx_done;
Stephen Hemmingerbea33482007-10-03 16:41:36 -0700557 struct napi_struct napi;
558 struct net_device *dev;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700559 struct net_device_stats stats;
560 struct pci_dev *pci_dev;
561#ifdef VLAN_SUPPORT
562 struct vlan_group *vlgrp;
563#endif
564 void *queue_mem;
565 dma_addr_t queue_mem_dma;
566 size_t queue_mem_size;
567
568 /* Frequently used values: keep some adjacent for cache effect. */
569 spinlock_t lock;
570 unsigned int cur_rx, dirty_rx; /* Producer/consumer ring indices */
571 unsigned int cur_tx, dirty_tx, reap_tx;
572 unsigned int rx_buf_sz; /* Based on MTU+slack. */
573 /* These values keep track of the transceiver/media in use. */
574 int speed100; /* Set if speed == 100MBit. */
575 u32 tx_mode;
576 u32 intr_timer_ctrl;
577 u8 tx_threshold;
578 /* MII transceiver section. */
579 struct mii_if_info mii_if; /* MII lib hooks/info */
580 int phy_cnt; /* MII device addresses. */
581 unsigned char phys[PHY_CNT]; /* MII device addresses. */
582 void __iomem *base;
583};
584
585
586static int mdio_read(struct net_device *dev, int phy_id, int location);
587static void mdio_write(struct net_device *dev, int phy_id, int location, int value);
588static int netdev_open(struct net_device *dev);
589static void check_duplex(struct net_device *dev);
590static void tx_timeout(struct net_device *dev);
591static void init_ring(struct net_device *dev);
592static int start_tx(struct sk_buff *skb, struct net_device *dev);
David Howells7d12e782006-10-05 14:55:46 +0100593static irqreturn_t intr_handler(int irq, void *dev_instance);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700594static void netdev_error(struct net_device *dev, int intr_status);
595static int __netdev_rx(struct net_device *dev, int *quota);
Francois Romieua6676012008-07-06 20:54:45 -0700596static int netdev_poll(struct napi_struct *napi, int budget);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700597static void refill_rx_ring(struct net_device *dev);
598static void netdev_error(struct net_device *dev, int intr_status);
599static void set_rx_mode(struct net_device *dev);
600static struct net_device_stats *get_stats(struct net_device *dev);
601static int netdev_ioctl(struct net_device *dev, struct ifreq *rq, int cmd);
602static int netdev_close(struct net_device *dev);
603static void netdev_media_change(struct net_device *dev);
Jeff Garzik7282d492006-09-13 14:30:00 -0400604static const struct ethtool_ops ethtool_ops;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700605
606
607#ifdef VLAN_SUPPORT
608static void netdev_vlan_rx_register(struct net_device *dev, struct vlan_group *grp)
609{
610 struct netdev_private *np = netdev_priv(dev);
611
612 spin_lock(&np->lock);
613 if (debug > 2)
614 printk("%s: Setting vlgrp to %p\n", dev->name, grp);
615 np->vlgrp = grp;
616 set_rx_mode(dev);
617 spin_unlock(&np->lock);
618}
619
620static void netdev_vlan_rx_add_vid(struct net_device *dev, unsigned short vid)
621{
622 struct netdev_private *np = netdev_priv(dev);
623
624 spin_lock(&np->lock);
625 if (debug > 1)
626 printk("%s: Adding vlanid %d to vlan filter\n", dev->name, vid);
627 set_rx_mode(dev);
628 spin_unlock(&np->lock);
629}
630
631static void netdev_vlan_rx_kill_vid(struct net_device *dev, unsigned short vid)
632{
633 struct netdev_private *np = netdev_priv(dev);
634
635 spin_lock(&np->lock);
636 if (debug > 1)
637 printk("%s: removing vlanid %d from vlan filter\n", dev->name, vid);
Dan Aloni5c15bde2007-03-02 20:44:51 -0800638 vlan_group_set_device(np->vlgrp, vid, NULL);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700639 set_rx_mode(dev);
640 spin_unlock(&np->lock);
641}
642#endif /* VLAN_SUPPORT */
643
644
645static int __devinit starfire_init_one(struct pci_dev *pdev,
646 const struct pci_device_id *ent)
647{
648 struct netdev_private *np;
649 int i, irq, option, chip_idx = ent->driver_data;
650 struct net_device *dev;
651 static int card_idx = -1;
652 long ioaddr;
653 void __iomem *base;
654 int drv_flags, io_size;
655 int boguscnt;
Joe Perches0795af52007-10-03 17:59:30 -0700656 DECLARE_MAC_BUF(mac);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700657
658/* when built into the kernel, we only print version if device is found */
659#ifndef MODULE
660 static int printed_version;
661 if (!printed_version++)
662 printk(version);
663#endif
664
665 card_idx++;
666
667 if (pci_enable_device (pdev))
668 return -EIO;
669
670 ioaddr = pci_resource_start(pdev, 0);
671 io_size = pci_resource_len(pdev, 0);
672 if (!ioaddr || ((pci_resource_flags(pdev, 0) & IORESOURCE_MEM) == 0)) {
673 printk(KERN_ERR DRV_NAME " %d: no PCI MEM resources, aborting\n", card_idx);
674 return -ENODEV;
675 }
676
677 dev = alloc_etherdev(sizeof(*np));
678 if (!dev) {
679 printk(KERN_ERR DRV_NAME " %d: cannot alloc etherdev, aborting\n", card_idx);
680 return -ENOMEM;
681 }
Linus Torvalds1da177e2005-04-16 15:20:36 -0700682 SET_NETDEV_DEV(dev, &pdev->dev);
683
684 irq = pdev->irq;
685
686 if (pci_request_regions (pdev, DRV_NAME)) {
687 printk(KERN_ERR DRV_NAME " %d: cannot reserve PCI resources, aborting\n", card_idx);
688 goto err_out_free_netdev;
689 }
690
Linus Torvalds1da177e2005-04-16 15:20:36 -0700691 base = ioremap(ioaddr, io_size);
692 if (!base) {
693 printk(KERN_ERR DRV_NAME " %d: cannot remap %#x @ %#lx, aborting\n",
694 card_idx, io_size, ioaddr);
695 goto err_out_free_res;
696 }
697
698 pci_set_master(pdev);
699
700 /* enable MWI -- it vastly improves Rx performance on sparc64 */
Randy Dunlap694625c2007-07-09 11:55:54 -0700701 pci_try_set_mwi(pdev);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700702
Linus Torvalds1da177e2005-04-16 15:20:36 -0700703#ifdef ZEROCOPY
704 /* Starfire can do TCP/UDP checksumming */
705 if (enable_hw_cksum)
Jeff Garzikfdecea62005-05-12 20:16:24 -0400706 dev->features |= NETIF_F_IP_CSUM | NETIF_F_SG;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700707#endif /* ZEROCOPY */
708#ifdef VLAN_SUPPORT
709 dev->features |= NETIF_F_HW_VLAN_RX | NETIF_F_HW_VLAN_FILTER;
710 dev->vlan_rx_register = netdev_vlan_rx_register;
711 dev->vlan_rx_add_vid = netdev_vlan_rx_add_vid;
712 dev->vlan_rx_kill_vid = netdev_vlan_rx_kill_vid;
713#endif /* VLAN_RX_KILL_VID */
714#ifdef ADDR_64BITS
715 dev->features |= NETIF_F_HIGHDMA;
716#endif /* ADDR_64BITS */
717
718 /* Serial EEPROM reads are hidden by the hardware. */
719 for (i = 0; i < 6; i++)
720 dev->dev_addr[i] = readb(base + EEPROMCtrl + 20 - i);
721
722#if ! defined(final_version) /* Dump the EEPROM contents during development. */
723 if (debug > 4)
724 for (i = 0; i < 0x20; i++)
725 printk("%2.2x%s",
726 (unsigned int)readb(base + EEPROMCtrl + i),
727 i % 16 != 15 ? " " : "\n");
728#endif
729
730 /* Issue soft reset */
731 writel(MiiSoftReset, base + TxMode);
732 udelay(1000);
733 writel(0, base + TxMode);
734
735 /* Reset the chip to erase previous misconfiguration. */
736 writel(1, base + PCIDeviceConfig);
737 boguscnt = 1000;
738 while (--boguscnt > 0) {
739 udelay(10);
740 if ((readl(base + PCIDeviceConfig) & 1) == 0)
741 break;
742 }
743 if (boguscnt == 0)
744 printk("%s: chipset reset never completed!\n", dev->name);
745 /* wait a little longer */
746 udelay(1000);
747
748 dev->base_addr = (unsigned long)base;
749 dev->irq = irq;
750
751 np = netdev_priv(dev);
Stephen Hemmingerbea33482007-10-03 16:41:36 -0700752 np->dev = dev;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700753 np->base = base;
754 spin_lock_init(&np->lock);
755 pci_set_drvdata(pdev, dev);
756
757 np->pci_dev = pdev;
758
759 np->mii_if.dev = dev;
760 np->mii_if.mdio_read = mdio_read;
761 np->mii_if.mdio_write = mdio_write;
762 np->mii_if.phy_id_mask = 0x1f;
763 np->mii_if.reg_num_mask = 0x1f;
764
765 drv_flags = netdrv_tbl[chip_idx].drv_flags;
766
767 option = card_idx < MAX_UNITS ? options[card_idx] : 0;
768 if (dev->mem_start)
769 option = dev->mem_start;
770
771 /* The lower four bits are the media type. */
772 if (option & 0x200)
773 np->mii_if.full_duplex = 1;
774
775 if (card_idx < MAX_UNITS && full_duplex[card_idx] > 0)
776 np->mii_if.full_duplex = 1;
777
778 if (np->mii_if.full_duplex)
779 np->mii_if.force_media = 1;
780 else
781 np->mii_if.force_media = 0;
782 np->speed100 = 1;
783
784 /* timer resolution is 128 * 0.8us */
785 np->intr_timer_ctrl = (((intr_latency * 10) / 1024) & IntrLatencyMask) |
786 Timer10X | EnableIntrMasking;
787
788 if (small_frames > 0) {
789 np->intr_timer_ctrl |= SmallFrameBypass;
790 switch (small_frames) {
791 case 1 ... 64:
792 np->intr_timer_ctrl |= SmallFrame64;
793 break;
794 case 65 ... 128:
795 np->intr_timer_ctrl |= SmallFrame128;
796 break;
797 case 129 ... 256:
798 np->intr_timer_ctrl |= SmallFrame256;
799 break;
800 default:
801 np->intr_timer_ctrl |= SmallFrame512;
802 if (small_frames > 512)
803 printk("Adjusting small_frames down to 512\n");
804 break;
805 }
806 }
807
808 /* The chip-specific entries in the device structure. */
809 dev->open = &netdev_open;
810 dev->hard_start_xmit = &start_tx;
Jeff Garzikfdecea62005-05-12 20:16:24 -0400811 dev->tx_timeout = tx_timeout;
812 dev->watchdog_timeo = TX_TIMEOUT;
Francois Romieua6676012008-07-06 20:54:45 -0700813 netif_napi_add(dev, &np->napi, netdev_poll, max_interrupt_work);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700814 dev->stop = &netdev_close;
815 dev->get_stats = &get_stats;
816 dev->set_multicast_list = &set_rx_mode;
817 dev->do_ioctl = &netdev_ioctl;
818 SET_ETHTOOL_OPS(dev, &ethtool_ops);
819
820 if (mtu)
821 dev->mtu = mtu;
822
823 if (register_netdev(dev))
824 goto err_out_cleardev;
825
Joe Perches0795af52007-10-03 17:59:30 -0700826 printk(KERN_INFO "%s: %s at %p, %s, IRQ %d.\n",
827 dev->name, netdrv_tbl[chip_idx].name, base,
828 print_mac(mac, dev->dev_addr), irq);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700829
830 if (drv_flags & CanHaveMII) {
831 int phy, phy_idx = 0;
832 int mii_status;
833 for (phy = 0; phy < 32 && phy_idx < PHY_CNT; phy++) {
834 mdio_write(dev, phy, MII_BMCR, BMCR_RESET);
835 mdelay(100);
836 boguscnt = 1000;
837 while (--boguscnt > 0)
838 if ((mdio_read(dev, phy, MII_BMCR) & BMCR_RESET) == 0)
839 break;
840 if (boguscnt == 0) {
Jeff Garzikfdecea62005-05-12 20:16:24 -0400841 printk("%s: PHY#%d reset never completed!\n", dev->name, phy);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700842 continue;
843 }
844 mii_status = mdio_read(dev, phy, MII_BMSR);
845 if (mii_status != 0) {
846 np->phys[phy_idx++] = phy;
847 np->mii_if.advertising = mdio_read(dev, phy, MII_ADVERTISE);
848 printk(KERN_INFO "%s: MII PHY found at address %d, status "
849 "%#4.4x advertising %#4.4x.\n",
850 dev->name, phy, mii_status, np->mii_if.advertising);
851 /* there can be only one PHY on-board */
852 break;
853 }
854 }
855 np->phy_cnt = phy_idx;
856 if (np->phy_cnt > 0)
857 np->mii_if.phy_id = np->phys[0];
858 else
859 memset(&np->mii_if, 0, sizeof(np->mii_if));
860 }
861
862 printk(KERN_INFO "%s: scatter-gather and hardware TCP cksumming %s.\n",
863 dev->name, enable_hw_cksum ? "enabled" : "disabled");
864 return 0;
865
866err_out_cleardev:
867 pci_set_drvdata(pdev, NULL);
868 iounmap(base);
869err_out_free_res:
870 pci_release_regions (pdev);
871err_out_free_netdev:
872 free_netdev(dev);
873 return -ENODEV;
874}
875
876
877/* Read the MII Management Data I/O (MDIO) interfaces. */
878static int mdio_read(struct net_device *dev, int phy_id, int location)
879{
880 struct netdev_private *np = netdev_priv(dev);
881 void __iomem *mdio_addr = np->base + MIICtrl + (phy_id<<7) + (location<<2);
882 int result, boguscnt=1000;
883 /* ??? Should we add a busy-wait here? */
884 do
885 result = readl(mdio_addr);
886 while ((result & 0xC0000000) != 0x80000000 && --boguscnt > 0);
887 if (boguscnt == 0)
888 return 0;
889 if ((result & 0xffff) == 0xffff)
890 return 0;
891 return result & 0xffff;
892}
893
894
895static void mdio_write(struct net_device *dev, int phy_id, int location, int value)
896{
897 struct netdev_private *np = netdev_priv(dev);
898 void __iomem *mdio_addr = np->base + MIICtrl + (phy_id<<7) + (location<<2);
899 writel(value, mdio_addr);
900 /* The busy-wait will occur before a read. */
901}
902
903
904static int netdev_open(struct net_device *dev)
905{
906 struct netdev_private *np = netdev_priv(dev);
907 void __iomem *ioaddr = np->base;
908 int i, retval;
909 size_t tx_done_q_size, rx_done_q_size, tx_ring_size, rx_ring_size;
910
911 /* Do we ever need to reset the chip??? */
Jeff Garzikfdecea62005-05-12 20:16:24 -0400912
Thomas Gleixner1fb9df52006-07-01 19:29:39 -0700913 retval = request_irq(dev->irq, &intr_handler, IRQF_SHARED, dev->name, dev);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700914 if (retval)
915 return retval;
916
917 /* Disable the Rx and Tx, and reset the chip. */
918 writel(0, ioaddr + GenCtrl);
919 writel(1, ioaddr + PCIDeviceConfig);
920 if (debug > 1)
921 printk(KERN_DEBUG "%s: netdev_open() irq %d.\n",
922 dev->name, dev->irq);
923
924 /* Allocate the various queues. */
Al Viro88b19432007-08-23 02:29:45 -0400925 if (!np->queue_mem) {
Linus Torvalds1da177e2005-04-16 15:20:36 -0700926 tx_done_q_size = ((sizeof(struct tx_done_desc) * DONE_Q_SIZE + QUEUE_ALIGN - 1) / QUEUE_ALIGN) * QUEUE_ALIGN;
927 rx_done_q_size = ((sizeof(rx_done_desc) * DONE_Q_SIZE + QUEUE_ALIGN - 1) / QUEUE_ALIGN) * QUEUE_ALIGN;
928 tx_ring_size = ((sizeof(starfire_tx_desc) * TX_RING_SIZE + QUEUE_ALIGN - 1) / QUEUE_ALIGN) * QUEUE_ALIGN;
929 rx_ring_size = sizeof(struct starfire_rx_desc) * RX_RING_SIZE;
930 np->queue_mem_size = tx_done_q_size + rx_done_q_size + tx_ring_size + rx_ring_size;
931 np->queue_mem = pci_alloc_consistent(np->pci_dev, np->queue_mem_size, &np->queue_mem_dma);
Alexey Dobriyand8840ac2005-10-07 02:05:23 +0400932 if (np->queue_mem == NULL) {
933 free_irq(dev->irq, dev);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700934 return -ENOMEM;
Alexey Dobriyand8840ac2005-10-07 02:05:23 +0400935 }
Linus Torvalds1da177e2005-04-16 15:20:36 -0700936
937 np->tx_done_q = np->queue_mem;
938 np->tx_done_q_dma = np->queue_mem_dma;
939 np->rx_done_q = (void *) np->tx_done_q + tx_done_q_size;
940 np->rx_done_q_dma = np->tx_done_q_dma + tx_done_q_size;
941 np->tx_ring = (void *) np->rx_done_q + rx_done_q_size;
942 np->tx_ring_dma = np->rx_done_q_dma + rx_done_q_size;
943 np->rx_ring = (void *) np->tx_ring + tx_ring_size;
944 np->rx_ring_dma = np->tx_ring_dma + tx_ring_size;
945 }
946
947 /* Start with no carrier, it gets adjusted later */
948 netif_carrier_off(dev);
949 init_ring(dev);
950 /* Set the size of the Rx buffers. */
951 writel((np->rx_buf_sz << RxBufferLenShift) |
952 (0 << RxMinDescrThreshShift) |
953 RxPrefetchMode | RxVariableQ |
954 RX_Q_ENTRIES |
955 RX_DESC_Q_ADDR_SIZE | RX_DESC_ADDR_SIZE |
956 RxDescSpace4,
957 ioaddr + RxDescQCtrl);
958
959 /* Set up the Rx DMA controller. */
960 writel(RxChecksumIgnore |
961 (0 << RxEarlyIntThreshShift) |
962 (6 << RxHighPrioThreshShift) |
963 ((DMA_BURST_SIZE / 32) << RxBurstSizeShift),
964 ioaddr + RxDMACtrl);
965
966 /* Set Tx descriptor */
967 writel((2 << TxHiPriFIFOThreshShift) |
968 (0 << TxPadLenShift) |
969 ((DMA_BURST_SIZE / 32) << TxDMABurstSizeShift) |
970 TX_DESC_Q_ADDR_SIZE |
971 TX_DESC_SPACING | TX_DESC_TYPE,
972 ioaddr + TxDescCtrl);
973
974 writel( (np->queue_mem_dma >> 16) >> 16, ioaddr + RxDescQHiAddr);
975 writel( (np->queue_mem_dma >> 16) >> 16, ioaddr + TxRingHiAddr);
976 writel( (np->queue_mem_dma >> 16) >> 16, ioaddr + CompletionHiAddr);
977 writel(np->rx_ring_dma, ioaddr + RxDescQAddr);
978 writel(np->tx_ring_dma, ioaddr + TxRingPtr);
979
980 writel(np->tx_done_q_dma, ioaddr + TxCompletionAddr);
981 writel(np->rx_done_q_dma |
982 RxComplType |
983 (0 << RxComplThreshShift),
984 ioaddr + RxCompletionAddr);
985
986 if (debug > 1)
987 printk(KERN_DEBUG "%s: Filling in the station address.\n", dev->name);
988
989 /* Fill both the Tx SA register and the Rx perfect filter. */
990 for (i = 0; i < 6; i++)
991 writeb(dev->dev_addr[i], ioaddr + TxStationAddr + 5 - i);
992 /* The first entry is special because it bypasses the VLAN filter.
993 Don't use it. */
994 writew(0, ioaddr + PerfFilterTable);
995 writew(0, ioaddr + PerfFilterTable + 4);
996 writew(0, ioaddr + PerfFilterTable + 8);
997 for (i = 1; i < 16; i++) {
Al Viro88b19432007-08-23 02:29:45 -0400998 __be16 *eaddrs = (__be16 *)dev->dev_addr;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700999 void __iomem *setup_frm = ioaddr + PerfFilterTable + i * 16;
Al Viro88b19432007-08-23 02:29:45 -04001000 writew(be16_to_cpu(eaddrs[2]), setup_frm); setup_frm += 4;
1001 writew(be16_to_cpu(eaddrs[1]), setup_frm); setup_frm += 4;
1002 writew(be16_to_cpu(eaddrs[0]), setup_frm); setup_frm += 8;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001003 }
1004
1005 /* Initialize other registers. */
1006 /* Configure the PCI bus bursts and FIFO thresholds. */
1007 np->tx_mode = TxFlowEnable|RxFlowEnable|PadEnable; /* modified when link is up. */
1008 writel(MiiSoftReset | np->tx_mode, ioaddr + TxMode);
1009 udelay(1000);
1010 writel(np->tx_mode, ioaddr + TxMode);
1011 np->tx_threshold = 4;
1012 writel(np->tx_threshold, ioaddr + TxThreshold);
1013
1014 writel(np->intr_timer_ctrl, ioaddr + IntrTimerCtrl);
1015
Stephen Hemmingerbea33482007-10-03 16:41:36 -07001016 napi_enable(&np->napi);
Francois Romieua6676012008-07-06 20:54:45 -07001017
Linus Torvalds1da177e2005-04-16 15:20:36 -07001018 netif_start_queue(dev);
1019
1020 if (debug > 1)
1021 printk(KERN_DEBUG "%s: Setting the Rx and Tx modes.\n", dev->name);
1022 set_rx_mode(dev);
1023
1024 np->mii_if.advertising = mdio_read(dev, np->phys[0], MII_ADVERTISE);
1025 check_duplex(dev);
1026
1027 /* Enable GPIO interrupts on link change */
1028 writel(0x0f00ff00, ioaddr + GPIOCtrl);
1029
1030 /* Set the interrupt mask */
1031 writel(IntrRxDone | IntrRxEmpty | IntrDMAErr |
1032 IntrTxDMADone | IntrStatsMax | IntrLinkChange |
1033 IntrRxGFPDead | IntrNoTxCsum | IntrTxBadID,
1034 ioaddr + IntrEnable);
1035 /* Enable PCI interrupts. */
1036 writel(0x00800000 | readl(ioaddr + PCIDeviceConfig),
1037 ioaddr + PCIDeviceConfig);
1038
1039#ifdef VLAN_SUPPORT
1040 /* Set VLAN type to 802.1q */
1041 writel(ETH_P_8021Q, ioaddr + VlanType);
1042#endif /* VLAN_SUPPORT */
1043
Linus Torvalds1da177e2005-04-16 15:20:36 -07001044 /* Load Rx/Tx firmware into the frame processors */
1045 for (i = 0; i < FIRMWARE_RX_SIZE * 2; i++)
1046 writel(firmware_rx[i], ioaddr + RxGfpMem + i * 4);
1047 for (i = 0; i < FIRMWARE_TX_SIZE * 2; i++)
1048 writel(firmware_tx[i], ioaddr + TxGfpMem + i * 4);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001049 if (enable_hw_cksum)
1050 /* Enable the Rx and Tx units, and the Rx/Tx frame processors. */
1051 writel(TxEnable|TxGFPEnable|RxEnable|RxGFPEnable, ioaddr + GenCtrl);
1052 else
1053 /* Enable the Rx and Tx units only. */
1054 writel(TxEnable|RxEnable, ioaddr + GenCtrl);
1055
1056 if (debug > 1)
1057 printk(KERN_DEBUG "%s: Done netdev_open().\n",
1058 dev->name);
1059
1060 return 0;
1061}
1062
1063
1064static void check_duplex(struct net_device *dev)
1065{
1066 struct netdev_private *np = netdev_priv(dev);
1067 u16 reg0;
1068 int silly_count = 1000;
1069
1070 mdio_write(dev, np->phys[0], MII_ADVERTISE, np->mii_if.advertising);
1071 mdio_write(dev, np->phys[0], MII_BMCR, BMCR_RESET);
1072 udelay(500);
1073 while (--silly_count && mdio_read(dev, np->phys[0], MII_BMCR) & BMCR_RESET)
1074 /* do nothing */;
1075 if (!silly_count) {
1076 printk("%s: MII reset failed!\n", dev->name);
1077 return;
1078 }
1079
1080 reg0 = mdio_read(dev, np->phys[0], MII_BMCR);
1081
1082 if (!np->mii_if.force_media) {
1083 reg0 |= BMCR_ANENABLE | BMCR_ANRESTART;
1084 } else {
1085 reg0 &= ~(BMCR_ANENABLE | BMCR_ANRESTART);
1086 if (np->speed100)
1087 reg0 |= BMCR_SPEED100;
1088 if (np->mii_if.full_duplex)
1089 reg0 |= BMCR_FULLDPLX;
1090 printk(KERN_DEBUG "%s: Link forced to %sMbit %s-duplex\n",
1091 dev->name,
1092 np->speed100 ? "100" : "10",
1093 np->mii_if.full_duplex ? "full" : "half");
1094 }
1095 mdio_write(dev, np->phys[0], MII_BMCR, reg0);
1096}
1097
1098
1099static void tx_timeout(struct net_device *dev)
1100{
1101 struct netdev_private *np = netdev_priv(dev);
1102 void __iomem *ioaddr = np->base;
1103 int old_debug;
1104
1105 printk(KERN_WARNING "%s: Transmit timed out, status %#8.8x, "
1106 "resetting...\n", dev->name, (int) readl(ioaddr + IntrStatus));
1107
1108 /* Perhaps we should reinitialize the hardware here. */
1109
1110 /*
1111 * Stop and restart the interface.
1112 * Cheat and increase the debug level temporarily.
1113 */
1114 old_debug = debug;
1115 debug = 2;
1116 netdev_close(dev);
1117 netdev_open(dev);
1118 debug = old_debug;
1119
1120 /* Trigger an immediate transmit demand. */
1121
1122 dev->trans_start = jiffies;
1123 np->stats.tx_errors++;
1124 netif_wake_queue(dev);
1125}
1126
1127
1128/* Initialize the Rx and Tx rings, along with various 'dev' bits. */
1129static void init_ring(struct net_device *dev)
1130{
1131 struct netdev_private *np = netdev_priv(dev);
1132 int i;
1133
1134 np->cur_rx = np->cur_tx = np->reap_tx = 0;
1135 np->dirty_rx = np->dirty_tx = np->rx_done = np->tx_done = 0;
1136
1137 np->rx_buf_sz = (dev->mtu <= 1500 ? PKT_BUF_SZ : dev->mtu + 32);
1138
1139 /* Fill in the Rx buffers. Handle allocation failure gracefully. */
1140 for (i = 0; i < RX_RING_SIZE; i++) {
1141 struct sk_buff *skb = dev_alloc_skb(np->rx_buf_sz);
1142 np->rx_info[i].skb = skb;
1143 if (skb == NULL)
1144 break;
David S. Miller689be432005-06-28 15:25:31 -07001145 np->rx_info[i].mapping = pci_map_single(np->pci_dev, skb->data, np->rx_buf_sz, PCI_DMA_FROMDEVICE);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001146 skb->dev = dev; /* Mark as being used by this device. */
1147 /* Grrr, we cannot offset to correctly align the IP header. */
1148 np->rx_ring[i].rxaddr = cpu_to_dma(np->rx_info[i].mapping | RxDescValid);
1149 }
1150 writew(i - 1, np->base + RxDescQIdx);
1151 np->dirty_rx = (unsigned int)(i - RX_RING_SIZE);
1152
1153 /* Clear the remainder of the Rx buffer ring. */
1154 for ( ; i < RX_RING_SIZE; i++) {
1155 np->rx_ring[i].rxaddr = 0;
1156 np->rx_info[i].skb = NULL;
1157 np->rx_info[i].mapping = 0;
1158 }
1159 /* Mark the last entry as wrapping the ring. */
1160 np->rx_ring[RX_RING_SIZE - 1].rxaddr |= cpu_to_dma(RxDescEndRing);
1161
1162 /* Clear the completion rings. */
1163 for (i = 0; i < DONE_Q_SIZE; i++) {
1164 np->rx_done_q[i].status = 0;
1165 np->tx_done_q[i].status = 0;
1166 }
1167
1168 for (i = 0; i < TX_RING_SIZE; i++)
1169 memset(&np->tx_info[i], 0, sizeof(np->tx_info[i]));
1170
1171 return;
1172}
1173
1174
1175static int start_tx(struct sk_buff *skb, struct net_device *dev)
1176{
1177 struct netdev_private *np = netdev_priv(dev);
1178 unsigned int entry;
1179 u32 status;
1180 int i;
1181
Linus Torvalds1da177e2005-04-16 15:20:36 -07001182 /*
1183 * be cautious here, wrapping the queue has weird semantics
1184 * and we may not have enough slots even when it seems we do.
1185 */
1186 if ((np->cur_tx - np->dirty_tx) + skb_num_frags(skb) * 2 > TX_RING_SIZE) {
1187 netif_stop_queue(dev);
1188 return 1;
1189 }
1190
1191#if defined(ZEROCOPY) && defined(HAS_BROKEN_FIRMWARE)
Patrick McHardy84fa7932006-08-29 16:44:56 -07001192 if (skb->ip_summed == CHECKSUM_PARTIAL) {
Herbert Xu5b057c62006-06-23 02:06:41 -07001193 if (skb_padto(skb, (skb->len + PADDING_MASK) & ~PADDING_MASK))
Ion Badulescu67974232005-10-03 22:31:36 -04001194 return NETDEV_TX_OK;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001195 }
1196#endif /* ZEROCOPY && HAS_BROKEN_FIRMWARE */
1197
1198 entry = np->cur_tx % TX_RING_SIZE;
1199 for (i = 0; i < skb_num_frags(skb); i++) {
1200 int wrap_ring = 0;
1201 status = TxDescID;
1202
1203 if (i == 0) {
1204 np->tx_info[entry].skb = skb;
1205 status |= TxCRCEn;
1206 if (entry >= TX_RING_SIZE - skb_num_frags(skb)) {
1207 status |= TxRingWrap;
1208 wrap_ring = 1;
1209 }
1210 if (np->reap_tx) {
1211 status |= TxDescIntr;
1212 np->reap_tx = 0;
1213 }
Patrick McHardy84fa7932006-08-29 16:44:56 -07001214 if (skb->ip_summed == CHECKSUM_PARTIAL) {
Linus Torvalds1da177e2005-04-16 15:20:36 -07001215 status |= TxCalTCP;
1216 np->stats.tx_compressed++;
1217 }
1218 status |= skb_first_frag_len(skb) | (skb_num_frags(skb) << 16);
1219
1220 np->tx_info[entry].mapping =
1221 pci_map_single(np->pci_dev, skb->data, skb_first_frag_len(skb), PCI_DMA_TODEVICE);
1222 } else {
Linus Torvalds1da177e2005-04-16 15:20:36 -07001223 skb_frag_t *this_frag = &skb_shinfo(skb)->frags[i - 1];
1224 status |= this_frag->size;
1225 np->tx_info[entry].mapping =
1226 pci_map_single(np->pci_dev, page_address(this_frag->page) + this_frag->page_offset, this_frag->size, PCI_DMA_TODEVICE);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001227 }
1228
1229 np->tx_ring[entry].addr = cpu_to_dma(np->tx_info[entry].mapping);
1230 np->tx_ring[entry].status = cpu_to_le32(status);
1231 if (debug > 3)
1232 printk(KERN_DEBUG "%s: Tx #%d/#%d slot %d status %#8.8x.\n",
1233 dev->name, np->cur_tx, np->dirty_tx,
1234 entry, status);
1235 if (wrap_ring) {
1236 np->tx_info[entry].used_slots = TX_RING_SIZE - entry;
1237 np->cur_tx += np->tx_info[entry].used_slots;
1238 entry = 0;
1239 } else {
1240 np->tx_info[entry].used_slots = 1;
1241 np->cur_tx += np->tx_info[entry].used_slots;
1242 entry++;
1243 }
1244 /* scavenge the tx descriptors twice per TX_RING_SIZE */
1245 if (np->cur_tx % (TX_RING_SIZE / 2) == 0)
1246 np->reap_tx = 1;
1247 }
1248
1249 /* Non-x86: explicitly flush descriptor cache lines here. */
1250 /* Ensure all descriptors are written back before the transmit is
1251 initiated. - Jes */
1252 wmb();
1253
1254 /* Update the producer index. */
1255 writel(entry * (sizeof(starfire_tx_desc) / 8), np->base + TxProducerIdx);
1256
1257 /* 4 is arbitrary, but should be ok */
1258 if ((np->cur_tx - np->dirty_tx) + 4 > TX_RING_SIZE)
1259 netif_stop_queue(dev);
1260
1261 dev->trans_start = jiffies;
1262
1263 return 0;
1264}
1265
1266
1267/* The interrupt handler does all of the Rx thread work and cleans up
1268 after the Tx thread. */
David Howells7d12e782006-10-05 14:55:46 +01001269static irqreturn_t intr_handler(int irq, void *dev_instance)
Linus Torvalds1da177e2005-04-16 15:20:36 -07001270{
1271 struct net_device *dev = dev_instance;
1272 struct netdev_private *np = netdev_priv(dev);
1273 void __iomem *ioaddr = np->base;
1274 int boguscnt = max_interrupt_work;
1275 int consumer;
1276 int tx_status;
1277 int handled = 0;
1278
1279 do {
1280 u32 intr_status = readl(ioaddr + IntrClear);
1281
1282 if (debug > 4)
1283 printk(KERN_DEBUG "%s: Interrupt status %#8.8x.\n",
1284 dev->name, intr_status);
1285
1286 if (intr_status == 0 || intr_status == (u32) -1)
1287 break;
1288
1289 handled = 1;
1290
Francois Romieua6676012008-07-06 20:54:45 -07001291 if (intr_status & (IntrRxDone | IntrRxEmpty)) {
1292 u32 enable;
1293
1294 if (likely(netif_rx_schedule_prep(dev, &np->napi))) {
1295 __netif_rx_schedule(dev, &np->napi);
1296 enable = readl(ioaddr + IntrEnable);
1297 enable &= ~(IntrRxDone | IntrRxEmpty);
1298 writel(enable, ioaddr + IntrEnable);
1299 /* flush PCI posting buffers */
1300 readl(ioaddr + IntrEnable);
1301 } else {
1302 /* Paranoia check */
1303 enable = readl(ioaddr + IntrEnable);
1304 if (enable & (IntrRxDone | IntrRxEmpty)) {
1305 printk(KERN_INFO
1306 "%s: interrupt while in poll!\n",
1307 dev->name);
1308 enable &= ~(IntrRxDone | IntrRxEmpty);
1309 writel(enable, ioaddr + IntrEnable);
1310 }
1311 }
1312 }
Linus Torvalds1da177e2005-04-16 15:20:36 -07001313
1314 /* Scavenge the skbuff list based on the Tx-done queue.
1315 There are redundant checks here that may be cleaned up
1316 after the driver has proven to be reliable. */
1317 consumer = readl(ioaddr + TxConsumerIdx);
1318 if (debug > 3)
1319 printk(KERN_DEBUG "%s: Tx Consumer index is %d.\n",
1320 dev->name, consumer);
1321
1322 while ((tx_status = le32_to_cpu(np->tx_done_q[np->tx_done].status)) != 0) {
1323 if (debug > 3)
1324 printk(KERN_DEBUG "%s: Tx completion #%d entry %d is %#8.8x.\n",
1325 dev->name, np->dirty_tx, np->tx_done, tx_status);
1326 if ((tx_status & 0xe0000000) == 0xa0000000) {
1327 np->stats.tx_packets++;
1328 } else if ((tx_status & 0xe0000000) == 0x80000000) {
1329 u16 entry = (tx_status & 0x7fff) / sizeof(starfire_tx_desc);
1330 struct sk_buff *skb = np->tx_info[entry].skb;
1331 np->tx_info[entry].skb = NULL;
1332 pci_unmap_single(np->pci_dev,
1333 np->tx_info[entry].mapping,
1334 skb_first_frag_len(skb),
1335 PCI_DMA_TODEVICE);
1336 np->tx_info[entry].mapping = 0;
1337 np->dirty_tx += np->tx_info[entry].used_slots;
1338 entry = (entry + np->tx_info[entry].used_slots) % TX_RING_SIZE;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001339 {
1340 int i;
1341 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
1342 pci_unmap_single(np->pci_dev,
1343 np->tx_info[entry].mapping,
1344 skb_shinfo(skb)->frags[i].size,
1345 PCI_DMA_TODEVICE);
1346 np->dirty_tx++;
1347 entry++;
1348 }
1349 }
Jeff Garzikfdecea62005-05-12 20:16:24 -04001350
Linus Torvalds1da177e2005-04-16 15:20:36 -07001351 dev_kfree_skb_irq(skb);
1352 }
1353 np->tx_done_q[np->tx_done].status = 0;
1354 np->tx_done = (np->tx_done + 1) % DONE_Q_SIZE;
1355 }
1356 writew(np->tx_done, ioaddr + CompletionQConsumerIdx + 2);
1357
1358 if (netif_queue_stopped(dev) &&
1359 (np->cur_tx - np->dirty_tx + 4 < TX_RING_SIZE)) {
1360 /* The ring is no longer full, wake the queue. */
1361 netif_wake_queue(dev);
1362 }
1363
1364 /* Stats overflow */
1365 if (intr_status & IntrStatsMax)
1366 get_stats(dev);
1367
1368 /* Media change interrupt. */
1369 if (intr_status & IntrLinkChange)
1370 netdev_media_change(dev);
1371
1372 /* Abnormal error summary/uncommon events handlers. */
1373 if (intr_status & IntrAbnormalSummary)
1374 netdev_error(dev, intr_status);
1375
1376 if (--boguscnt < 0) {
1377 if (debug > 1)
1378 printk(KERN_WARNING "%s: Too much work at interrupt, "
1379 "status=%#8.8x.\n",
1380 dev->name, intr_status);
1381 break;
1382 }
1383 } while (1);
1384
1385 if (debug > 4)
1386 printk(KERN_DEBUG "%s: exiting interrupt, status=%#8.8x.\n",
1387 dev->name, (int) readl(ioaddr + IntrStatus));
1388 return IRQ_RETVAL(handled);
1389}
1390
1391
Francois Romieua6676012008-07-06 20:54:45 -07001392/*
1393 * This routine is logically part of the interrupt/poll handler, but separated
1394 * for clarity and better register allocation.
1395 */
Linus Torvalds1da177e2005-04-16 15:20:36 -07001396static int __netdev_rx(struct net_device *dev, int *quota)
1397{
1398 struct netdev_private *np = netdev_priv(dev);
1399 u32 desc_status;
1400 int retcode = 0;
1401
1402 /* If EOP is set on the next entry, it's a new packet. Send it up. */
1403 while ((desc_status = le32_to_cpu(np->rx_done_q[np->rx_done].status)) != 0) {
1404 struct sk_buff *skb;
1405 u16 pkt_len;
1406 int entry;
1407 rx_done_desc *desc = &np->rx_done_q[np->rx_done];
1408
1409 if (debug > 4)
1410 printk(KERN_DEBUG " netdev_rx() status of %d was %#8.8x.\n", np->rx_done, desc_status);
1411 if (!(desc_status & RxOK)) {
Jeff Garzikfdecea62005-05-12 20:16:24 -04001412 /* There was an error. */
Linus Torvalds1da177e2005-04-16 15:20:36 -07001413 if (debug > 2)
1414 printk(KERN_DEBUG " netdev_rx() Rx error was %#8.8x.\n", desc_status);
1415 np->stats.rx_errors++;
1416 if (desc_status & RxFIFOErr)
1417 np->stats.rx_fifo_errors++;
1418 goto next_rx;
1419 }
1420
1421 if (*quota <= 0) { /* out of rx quota */
1422 retcode = 1;
1423 goto out;
1424 }
1425 (*quota)--;
1426
1427 pkt_len = desc_status; /* Implicitly Truncate */
1428 entry = (desc_status >> 16) & 0x7ff;
1429
1430 if (debug > 4)
1431 printk(KERN_DEBUG " netdev_rx() normal Rx pkt length %d, quota %d.\n", pkt_len, *quota);
1432 /* Check if the packet is long enough to accept without copying
1433 to a minimally-sized skbuff. */
1434 if (pkt_len < rx_copybreak
1435 && (skb = dev_alloc_skb(pkt_len + 2)) != NULL) {
Linus Torvalds1da177e2005-04-16 15:20:36 -07001436 skb_reserve(skb, 2); /* 16 byte align the IP header */
1437 pci_dma_sync_single_for_cpu(np->pci_dev,
1438 np->rx_info[entry].mapping,
1439 pkt_len, PCI_DMA_FROMDEVICE);
David S. Miller8c7b7fa2007-07-10 22:08:12 -07001440 skb_copy_to_linear_data(skb, np->rx_info[entry].skb->data, pkt_len);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001441 pci_dma_sync_single_for_device(np->pci_dev,
1442 np->rx_info[entry].mapping,
1443 pkt_len, PCI_DMA_FROMDEVICE);
1444 skb_put(skb, pkt_len);
1445 } else {
1446 pci_unmap_single(np->pci_dev, np->rx_info[entry].mapping, np->rx_buf_sz, PCI_DMA_FROMDEVICE);
1447 skb = np->rx_info[entry].skb;
1448 skb_put(skb, pkt_len);
1449 np->rx_info[entry].skb = NULL;
1450 np->rx_info[entry].mapping = 0;
1451 }
1452#ifndef final_version /* Remove after testing. */
1453 /* You will want this info for the initial debug. */
Joe Perches0795af52007-10-03 17:59:30 -07001454 if (debug > 5) {
David S. Miller21f644f2008-04-08 16:50:44 -07001455 printk(KERN_DEBUG " Rx data " MAC_FMT " " MAC_FMT
Joe Perches0795af52007-10-03 17:59:30 -07001456 " %2.2x%2.2x.\n",
David S. Miller21f644f2008-04-08 16:50:44 -07001457 skb->data[0], skb->data[1], skb->data[2],
1458 skb->data[3], skb->data[4], skb->data[5],
1459 skb->data[6], skb->data[7], skb->data[8],
1460 skb->data[9], skb->data[10], skb->data[11],
Joe Perches0795af52007-10-03 17:59:30 -07001461 skb->data[12], skb->data[13]);
1462 }
Linus Torvalds1da177e2005-04-16 15:20:36 -07001463#endif
1464
1465 skb->protocol = eth_type_trans(skb, dev);
Jeff Garzikfdecea62005-05-12 20:16:24 -04001466#ifdef VLAN_SUPPORT
Linus Torvalds1da177e2005-04-16 15:20:36 -07001467 if (debug > 4)
1468 printk(KERN_DEBUG " netdev_rx() status2 of %d was %#4.4x.\n", np->rx_done, le16_to_cpu(desc->status2));
1469#endif
Linus Torvalds1da177e2005-04-16 15:20:36 -07001470 if (le16_to_cpu(desc->status2) & 0x0100) {
1471 skb->ip_summed = CHECKSUM_UNNECESSARY;
1472 np->stats.rx_compressed++;
1473 }
1474 /*
1475 * This feature doesn't seem to be working, at least
1476 * with the two firmware versions I have. If the GFP sees
1477 * an IP fragment, it either ignores it completely, or reports
1478 * "bad checksum" on it.
1479 *
1480 * Maybe I missed something -- corrections are welcome.
1481 * Until then, the printk stays. :-) -Ion
1482 */
1483 else if (le16_to_cpu(desc->status2) & 0x0040) {
Patrick McHardy84fa7932006-08-29 16:44:56 -07001484 skb->ip_summed = CHECKSUM_COMPLETE;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001485 skb->csum = le16_to_cpu(desc->csum);
1486 printk(KERN_DEBUG "%s: checksum_hw, status2 = %#x\n", dev->name, le16_to_cpu(desc->status2));
1487 }
Linus Torvalds1da177e2005-04-16 15:20:36 -07001488#ifdef VLAN_SUPPORT
1489 if (np->vlgrp && le16_to_cpu(desc->status2) & 0x0200) {
Francois Romieua6676012008-07-06 20:54:45 -07001490 u16 vlid = le16_to_cpu(desc->vlanid);
1491
1492 if (debug > 4) {
1493 printk(KERN_DEBUG " netdev_rx() vlanid = %d\n",
1494 vlid);
1495 }
1496 /*
1497 * vlan_hwaccel_rx expects a packet with the VLAN tag
1498 * stripped out.
1499 */
1500 vlan_hwaccel_rx(skb, np->vlgrp, vlid);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001501 } else
1502#endif /* VLAN_SUPPORT */
Francois Romieua6676012008-07-06 20:54:45 -07001503 netif_receive_skb(skb);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001504 dev->last_rx = jiffies;
1505 np->stats.rx_packets++;
1506
1507 next_rx:
1508 np->cur_rx++;
1509 desc->status = 0;
1510 np->rx_done = (np->rx_done + 1) % DONE_Q_SIZE;
1511 }
Jarek Poplawski9a3de252008-12-16 15:42:20 -08001512
1513 if (*quota == 0) { /* out of rx quota */
1514 retcode = 1;
1515 goto out;
1516 }
Linus Torvalds1da177e2005-04-16 15:20:36 -07001517 writew(np->rx_done, np->base + CompletionQConsumerIdx);
1518
1519 out:
1520 refill_rx_ring(dev);
1521 if (debug > 5)
1522 printk(KERN_DEBUG " exiting netdev_rx(): %d, status of %d was %#8.8x.\n",
1523 retcode, np->rx_done, desc_status);
1524 return retcode;
1525}
1526
Stephen Hemmingerbea33482007-10-03 16:41:36 -07001527static int netdev_poll(struct napi_struct *napi, int budget)
Linus Torvalds1da177e2005-04-16 15:20:36 -07001528{
Stephen Hemmingerbea33482007-10-03 16:41:36 -07001529 struct netdev_private *np = container_of(napi, struct netdev_private, napi);
1530 struct net_device *dev = np->dev;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001531 u32 intr_status;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001532 void __iomem *ioaddr = np->base;
Stephen Hemmingerbea33482007-10-03 16:41:36 -07001533 int quota = budget;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001534
1535 do {
1536 writel(IntrRxDone | IntrRxEmpty, ioaddr + IntrClear);
1537
Stephen Hemmingerbea33482007-10-03 16:41:36 -07001538 if (__netdev_rx(dev, &quota))
Linus Torvalds1da177e2005-04-16 15:20:36 -07001539 goto out;
1540
1541 intr_status = readl(ioaddr + IntrStatus);
1542 } while (intr_status & (IntrRxDone | IntrRxEmpty));
1543
Stephen Hemmingerbea33482007-10-03 16:41:36 -07001544 netif_rx_complete(dev, napi);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001545 intr_status = readl(ioaddr + IntrEnable);
1546 intr_status |= IntrRxDone | IntrRxEmpty;
1547 writel(intr_status, ioaddr + IntrEnable);
1548
1549 out:
1550 if (debug > 5)
Stephen Hemmingerbea33482007-10-03 16:41:36 -07001551 printk(KERN_DEBUG " exiting netdev_poll(): %d.\n",
1552 budget - quota);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001553
1554 /* Restart Rx engine if stopped. */
Stephen Hemmingerbea33482007-10-03 16:41:36 -07001555 return budget - quota;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001556}
Linus Torvalds1da177e2005-04-16 15:20:36 -07001557
1558static void refill_rx_ring(struct net_device *dev)
1559{
1560 struct netdev_private *np = netdev_priv(dev);
1561 struct sk_buff *skb;
1562 int entry = -1;
1563
1564 /* Refill the Rx ring buffers. */
1565 for (; np->cur_rx - np->dirty_rx > 0; np->dirty_rx++) {
1566 entry = np->dirty_rx % RX_RING_SIZE;
1567 if (np->rx_info[entry].skb == NULL) {
1568 skb = dev_alloc_skb(np->rx_buf_sz);
1569 np->rx_info[entry].skb = skb;
1570 if (skb == NULL)
1571 break; /* Better luck next round. */
1572 np->rx_info[entry].mapping =
David S. Miller689be432005-06-28 15:25:31 -07001573 pci_map_single(np->pci_dev, skb->data, np->rx_buf_sz, PCI_DMA_FROMDEVICE);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001574 skb->dev = dev; /* Mark as being used by this device. */
1575 np->rx_ring[entry].rxaddr =
1576 cpu_to_dma(np->rx_info[entry].mapping | RxDescValid);
1577 }
1578 if (entry == RX_RING_SIZE - 1)
1579 np->rx_ring[entry].rxaddr |= cpu_to_dma(RxDescEndRing);
1580 }
1581 if (entry >= 0)
1582 writew(entry, np->base + RxDescQIdx);
1583}
1584
1585
1586static void netdev_media_change(struct net_device *dev)
1587{
1588 struct netdev_private *np = netdev_priv(dev);
1589 void __iomem *ioaddr = np->base;
1590 u16 reg0, reg1, reg4, reg5;
1591 u32 new_tx_mode;
1592 u32 new_intr_timer_ctrl;
1593
1594 /* reset status first */
1595 mdio_read(dev, np->phys[0], MII_BMCR);
1596 mdio_read(dev, np->phys[0], MII_BMSR);
1597
1598 reg0 = mdio_read(dev, np->phys[0], MII_BMCR);
1599 reg1 = mdio_read(dev, np->phys[0], MII_BMSR);
1600
1601 if (reg1 & BMSR_LSTATUS) {
1602 /* link is up */
1603 if (reg0 & BMCR_ANENABLE) {
1604 /* autonegotiation is enabled */
1605 reg4 = mdio_read(dev, np->phys[0], MII_ADVERTISE);
1606 reg5 = mdio_read(dev, np->phys[0], MII_LPA);
1607 if (reg4 & ADVERTISE_100FULL && reg5 & LPA_100FULL) {
1608 np->speed100 = 1;
1609 np->mii_if.full_duplex = 1;
1610 } else if (reg4 & ADVERTISE_100HALF && reg5 & LPA_100HALF) {
1611 np->speed100 = 1;
1612 np->mii_if.full_duplex = 0;
1613 } else if (reg4 & ADVERTISE_10FULL && reg5 & LPA_10FULL) {
1614 np->speed100 = 0;
1615 np->mii_if.full_duplex = 1;
1616 } else {
1617 np->speed100 = 0;
1618 np->mii_if.full_duplex = 0;
1619 }
1620 } else {
1621 /* autonegotiation is disabled */
1622 if (reg0 & BMCR_SPEED100)
1623 np->speed100 = 1;
1624 else
1625 np->speed100 = 0;
1626 if (reg0 & BMCR_FULLDPLX)
1627 np->mii_if.full_duplex = 1;
1628 else
1629 np->mii_if.full_duplex = 0;
1630 }
1631 netif_carrier_on(dev);
1632 printk(KERN_DEBUG "%s: Link is up, running at %sMbit %s-duplex\n",
1633 dev->name,
1634 np->speed100 ? "100" : "10",
1635 np->mii_if.full_duplex ? "full" : "half");
1636
1637 new_tx_mode = np->tx_mode & ~FullDuplex; /* duplex setting */
1638 if (np->mii_if.full_duplex)
1639 new_tx_mode |= FullDuplex;
1640 if (np->tx_mode != new_tx_mode) {
1641 np->tx_mode = new_tx_mode;
1642 writel(np->tx_mode | MiiSoftReset, ioaddr + TxMode);
1643 udelay(1000);
1644 writel(np->tx_mode, ioaddr + TxMode);
1645 }
1646
1647 new_intr_timer_ctrl = np->intr_timer_ctrl & ~Timer10X;
1648 if (np->speed100)
1649 new_intr_timer_ctrl |= Timer10X;
1650 if (np->intr_timer_ctrl != new_intr_timer_ctrl) {
1651 np->intr_timer_ctrl = new_intr_timer_ctrl;
1652 writel(new_intr_timer_ctrl, ioaddr + IntrTimerCtrl);
1653 }
1654 } else {
1655 netif_carrier_off(dev);
1656 printk(KERN_DEBUG "%s: Link is down\n", dev->name);
1657 }
1658}
1659
1660
1661static void netdev_error(struct net_device *dev, int intr_status)
1662{
1663 struct netdev_private *np = netdev_priv(dev);
1664
1665 /* Came close to underrunning the Tx FIFO, increase threshold. */
1666 if (intr_status & IntrTxDataLow) {
1667 if (np->tx_threshold <= PKT_BUF_SZ / 16) {
1668 writel(++np->tx_threshold, np->base + TxThreshold);
1669 printk(KERN_NOTICE "%s: PCI bus congestion, increasing Tx FIFO threshold to %d bytes\n",
1670 dev->name, np->tx_threshold * 16);
1671 } else
1672 printk(KERN_WARNING "%s: PCI Tx underflow -- adapter is probably malfunctioning\n", dev->name);
1673 }
1674 if (intr_status & IntrRxGFPDead) {
1675 np->stats.rx_fifo_errors++;
1676 np->stats.rx_errors++;
1677 }
1678 if (intr_status & (IntrNoTxCsum | IntrDMAErr)) {
1679 np->stats.tx_fifo_errors++;
1680 np->stats.tx_errors++;
1681 }
1682 if ((intr_status & ~(IntrNormalMask | IntrAbnormalSummary | IntrLinkChange | IntrStatsMax | IntrTxDataLow | IntrRxGFPDead | IntrNoTxCsum | IntrPCIPad)) && debug)
1683 printk(KERN_ERR "%s: Something Wicked happened! %#8.8x.\n",
1684 dev->name, intr_status);
1685}
1686
1687
1688static struct net_device_stats *get_stats(struct net_device *dev)
1689{
1690 struct netdev_private *np = netdev_priv(dev);
1691 void __iomem *ioaddr = np->base;
1692
1693 /* This adapter architecture needs no SMP locks. */
1694 np->stats.tx_bytes = readl(ioaddr + 0x57010);
1695 np->stats.rx_bytes = readl(ioaddr + 0x57044);
1696 np->stats.tx_packets = readl(ioaddr + 0x57000);
1697 np->stats.tx_aborted_errors =
1698 readl(ioaddr + 0x57024) + readl(ioaddr + 0x57028);
1699 np->stats.tx_window_errors = readl(ioaddr + 0x57018);
1700 np->stats.collisions =
1701 readl(ioaddr + 0x57004) + readl(ioaddr + 0x57008);
1702
1703 /* The chip only need report frame silently dropped. */
1704 np->stats.rx_dropped += readw(ioaddr + RxDMAStatus);
1705 writew(0, ioaddr + RxDMAStatus);
1706 np->stats.rx_crc_errors = readl(ioaddr + 0x5703C);
1707 np->stats.rx_frame_errors = readl(ioaddr + 0x57040);
1708 np->stats.rx_length_errors = readl(ioaddr + 0x57058);
1709 np->stats.rx_missed_errors = readl(ioaddr + 0x5707C);
1710
1711 return &np->stats;
1712}
1713
1714
Linus Torvalds1da177e2005-04-16 15:20:36 -07001715static void set_rx_mode(struct net_device *dev)
1716{
1717 struct netdev_private *np = netdev_priv(dev);
1718 void __iomem *ioaddr = np->base;
1719 u32 rx_mode = MinVLANPrio;
1720 struct dev_mc_list *mclist;
1721 int i;
1722#ifdef VLAN_SUPPORT
1723
1724 rx_mode |= VlanMode;
1725 if (np->vlgrp) {
1726 int vlan_count = 0;
1727 void __iomem *filter_addr = ioaddr + HashTable + 8;
1728 for (i = 0; i < VLAN_VID_MASK; i++) {
Dan Aloni5c15bde2007-03-02 20:44:51 -08001729 if (vlan_group_get_device(np->vlgrp, i)) {
Linus Torvalds1da177e2005-04-16 15:20:36 -07001730 if (vlan_count >= 32)
1731 break;
Al Viro813820b2007-12-09 17:00:54 +00001732 writew(i, filter_addr);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001733 filter_addr += 16;
1734 vlan_count++;
1735 }
1736 }
1737 if (i == VLAN_VID_MASK) {
1738 rx_mode |= PerfectFilterVlan;
1739 while (vlan_count < 32) {
1740 writew(0, filter_addr);
1741 filter_addr += 16;
1742 vlan_count++;
1743 }
1744 }
1745 }
1746#endif /* VLAN_SUPPORT */
1747
1748 if (dev->flags & IFF_PROMISC) { /* Set promiscuous. */
1749 rx_mode |= AcceptAll;
1750 } else if ((dev->mc_count > multicast_filter_limit)
1751 || (dev->flags & IFF_ALLMULTI)) {
1752 /* Too many to match, or accept all multicasts. */
1753 rx_mode |= AcceptBroadcast|AcceptAllMulticast|PerfectFilter;
1754 } else if (dev->mc_count <= 14) {
1755 /* Use the 16 element perfect filter, skip first two entries. */
1756 void __iomem *filter_addr = ioaddr + PerfFilterTable + 2 * 16;
Al Viro88b19432007-08-23 02:29:45 -04001757 __be16 *eaddrs;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001758 for (i = 2, mclist = dev->mc_list; mclist && i < dev->mc_count + 2;
1759 i++, mclist = mclist->next) {
Al Viro88b19432007-08-23 02:29:45 -04001760 eaddrs = (__be16 *)mclist->dmi_addr;
1761 writew(be16_to_cpu(eaddrs[2]), filter_addr); filter_addr += 4;
1762 writew(be16_to_cpu(eaddrs[1]), filter_addr); filter_addr += 4;
1763 writew(be16_to_cpu(eaddrs[0]), filter_addr); filter_addr += 8;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001764 }
Al Viro88b19432007-08-23 02:29:45 -04001765 eaddrs = (__be16 *)dev->dev_addr;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001766 while (i++ < 16) {
Al Viro88b19432007-08-23 02:29:45 -04001767 writew(be16_to_cpu(eaddrs[0]), filter_addr); filter_addr += 4;
1768 writew(be16_to_cpu(eaddrs[1]), filter_addr); filter_addr += 4;
1769 writew(be16_to_cpu(eaddrs[2]), filter_addr); filter_addr += 8;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001770 }
1771 rx_mode |= AcceptBroadcast|PerfectFilter;
1772 } else {
1773 /* Must use a multicast hash table. */
1774 void __iomem *filter_addr;
Al Viro88b19432007-08-23 02:29:45 -04001775 __be16 *eaddrs;
1776 __le16 mc_filter[32] __attribute__ ((aligned(sizeof(long)))); /* Multicast hash filter */
Linus Torvalds1da177e2005-04-16 15:20:36 -07001777
1778 memset(mc_filter, 0, sizeof(mc_filter));
1779 for (i = 0, mclist = dev->mc_list; mclist && i < dev->mc_count;
1780 i++, mclist = mclist->next) {
Jeff Garzikfdecea62005-05-12 20:16:24 -04001781 /* The chip uses the upper 9 CRC bits
1782 as index into the hash table */
Linus Torvalds1da177e2005-04-16 15:20:36 -07001783 int bit_nr = ether_crc_le(ETH_ALEN, mclist->dmi_addr) >> 23;
Al Viro88b19432007-08-23 02:29:45 -04001784 __le32 *fptr = (__le32 *) &mc_filter[(bit_nr >> 4) & ~1];
Linus Torvalds1da177e2005-04-16 15:20:36 -07001785
1786 *fptr |= cpu_to_le32(1 << (bit_nr & 31));
1787 }
1788 /* Clear the perfect filter list, skip first two entries. */
1789 filter_addr = ioaddr + PerfFilterTable + 2 * 16;
Al Viro88b19432007-08-23 02:29:45 -04001790 eaddrs = (__be16 *)dev->dev_addr;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001791 for (i = 2; i < 16; i++) {
Al Viro88b19432007-08-23 02:29:45 -04001792 writew(be16_to_cpu(eaddrs[0]), filter_addr); filter_addr += 4;
1793 writew(be16_to_cpu(eaddrs[1]), filter_addr); filter_addr += 4;
1794 writew(be16_to_cpu(eaddrs[2]), filter_addr); filter_addr += 8;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001795 }
1796 for (filter_addr = ioaddr + HashTable, i = 0; i < 32; filter_addr+= 16, i++)
1797 writew(mc_filter[i], filter_addr);
1798 rx_mode |= AcceptBroadcast|PerfectFilter|HashFilter;
1799 }
1800 writel(rx_mode, ioaddr + RxFilterMode);
1801}
1802
1803static int check_if_running(struct net_device *dev)
1804{
1805 if (!netif_running(dev))
1806 return -EINVAL;
1807 return 0;
1808}
1809
1810static void get_drvinfo(struct net_device *dev, struct ethtool_drvinfo *info)
1811{
1812 struct netdev_private *np = netdev_priv(dev);
1813 strcpy(info->driver, DRV_NAME);
1814 strcpy(info->version, DRV_VERSION);
Jeff Garzikfdecea62005-05-12 20:16:24 -04001815 strcpy(info->bus_info, pci_name(np->pci_dev));
Linus Torvalds1da177e2005-04-16 15:20:36 -07001816}
1817
1818static int get_settings(struct net_device *dev, struct ethtool_cmd *ecmd)
1819{
1820 struct netdev_private *np = netdev_priv(dev);
1821 spin_lock_irq(&np->lock);
1822 mii_ethtool_gset(&np->mii_if, ecmd);
1823 spin_unlock_irq(&np->lock);
1824 return 0;
1825}
1826
1827static int set_settings(struct net_device *dev, struct ethtool_cmd *ecmd)
1828{
1829 struct netdev_private *np = netdev_priv(dev);
1830 int res;
1831 spin_lock_irq(&np->lock);
1832 res = mii_ethtool_sset(&np->mii_if, ecmd);
1833 spin_unlock_irq(&np->lock);
1834 check_duplex(dev);
1835 return res;
1836}
1837
1838static int nway_reset(struct net_device *dev)
1839{
1840 struct netdev_private *np = netdev_priv(dev);
1841 return mii_nway_restart(&np->mii_if);
1842}
1843
1844static u32 get_link(struct net_device *dev)
1845{
1846 struct netdev_private *np = netdev_priv(dev);
1847 return mii_link_ok(&np->mii_if);
1848}
1849
1850static u32 get_msglevel(struct net_device *dev)
1851{
1852 return debug;
1853}
1854
1855static void set_msglevel(struct net_device *dev, u32 val)
1856{
1857 debug = val;
1858}
1859
Jeff Garzik7282d492006-09-13 14:30:00 -04001860static const struct ethtool_ops ethtool_ops = {
Linus Torvalds1da177e2005-04-16 15:20:36 -07001861 .begin = check_if_running,
1862 .get_drvinfo = get_drvinfo,
1863 .get_settings = get_settings,
1864 .set_settings = set_settings,
1865 .nway_reset = nway_reset,
1866 .get_link = get_link,
1867 .get_msglevel = get_msglevel,
1868 .set_msglevel = set_msglevel,
1869};
1870
1871static int netdev_ioctl(struct net_device *dev, struct ifreq *rq, int cmd)
1872{
1873 struct netdev_private *np = netdev_priv(dev);
1874 struct mii_ioctl_data *data = if_mii(rq);
1875 int rc;
1876
1877 if (!netif_running(dev))
1878 return -EINVAL;
1879
1880 spin_lock_irq(&np->lock);
1881 rc = generic_mii_ioctl(&np->mii_if, data, cmd, NULL);
1882 spin_unlock_irq(&np->lock);
1883
1884 if ((cmd == SIOCSMIIREG) && (data->phy_id == np->phys[0]))
1885 check_duplex(dev);
1886
1887 return rc;
1888}
1889
1890static int netdev_close(struct net_device *dev)
1891{
1892 struct netdev_private *np = netdev_priv(dev);
1893 void __iomem *ioaddr = np->base;
1894 int i;
1895
1896 netif_stop_queue(dev);
Francois Romieua6676012008-07-06 20:54:45 -07001897
Stephen Hemmingerbea33482007-10-03 16:41:36 -07001898 napi_disable(&np->napi);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001899
1900 if (debug > 1) {
1901 printk(KERN_DEBUG "%s: Shutting down ethercard, Intr status %#8.8x.\n",
1902 dev->name, (int) readl(ioaddr + IntrStatus));
1903 printk(KERN_DEBUG "%s: Queue pointers were Tx %d / %d, Rx %d / %d.\n",
1904 dev->name, np->cur_tx, np->dirty_tx,
1905 np->cur_rx, np->dirty_rx);
1906 }
1907
1908 /* Disable interrupts by clearing the interrupt mask. */
1909 writel(0, ioaddr + IntrEnable);
1910
1911 /* Stop the chip's Tx and Rx processes. */
1912 writel(0, ioaddr + GenCtrl);
1913 readl(ioaddr + GenCtrl);
1914
1915 if (debug > 5) {
1916 printk(KERN_DEBUG" Tx ring at %#llx:\n",
1917 (long long) np->tx_ring_dma);
1918 for (i = 0; i < 8 /* TX_RING_SIZE is huge! */; i++)
1919 printk(KERN_DEBUG " #%d desc. %#8.8x %#llx -> %#8.8x.\n",
1920 i, le32_to_cpu(np->tx_ring[i].status),
1921 (long long) dma_to_cpu(np->tx_ring[i].addr),
1922 le32_to_cpu(np->tx_done_q[i].status));
1923 printk(KERN_DEBUG " Rx ring at %#llx -> %p:\n",
1924 (long long) np->rx_ring_dma, np->rx_done_q);
1925 if (np->rx_done_q)
1926 for (i = 0; i < 8 /* RX_RING_SIZE */; i++) {
1927 printk(KERN_DEBUG " #%d desc. %#llx -> %#8.8x\n",
1928 i, (long long) dma_to_cpu(np->rx_ring[i].rxaddr), le32_to_cpu(np->rx_done_q[i].status));
1929 }
1930 }
1931
1932 free_irq(dev->irq, dev);
1933
1934 /* Free all the skbuffs in the Rx queue. */
1935 for (i = 0; i < RX_RING_SIZE; i++) {
1936 np->rx_ring[i].rxaddr = cpu_to_dma(0xBADF00D0); /* An invalid address. */
1937 if (np->rx_info[i].skb != NULL) {
1938 pci_unmap_single(np->pci_dev, np->rx_info[i].mapping, np->rx_buf_sz, PCI_DMA_FROMDEVICE);
1939 dev_kfree_skb(np->rx_info[i].skb);
1940 }
1941 np->rx_info[i].skb = NULL;
1942 np->rx_info[i].mapping = 0;
1943 }
1944 for (i = 0; i < TX_RING_SIZE; i++) {
1945 struct sk_buff *skb = np->tx_info[i].skb;
1946 if (skb == NULL)
1947 continue;
1948 pci_unmap_single(np->pci_dev,
1949 np->tx_info[i].mapping,
1950 skb_first_frag_len(skb), PCI_DMA_TODEVICE);
1951 np->tx_info[i].mapping = 0;
1952 dev_kfree_skb(skb);
1953 np->tx_info[i].skb = NULL;
1954 }
1955
1956 return 0;
1957}
1958
Stefan Rompfd4fbeab2006-01-17 22:52:51 +01001959#ifdef CONFIG_PM
1960static int starfire_suspend(struct pci_dev *pdev, pm_message_t state)
1961{
1962 struct net_device *dev = pci_get_drvdata(pdev);
1963
1964 if (netif_running(dev)) {
1965 netif_device_detach(dev);
1966 netdev_close(dev);
1967 }
1968
1969 pci_save_state(pdev);
1970 pci_set_power_state(pdev, pci_choose_state(pdev,state));
1971
1972 return 0;
1973}
1974
1975static int starfire_resume(struct pci_dev *pdev)
1976{
1977 struct net_device *dev = pci_get_drvdata(pdev);
Jeff Garzik6aa20a22006-09-13 13:24:59 -04001978
Stefan Rompfd4fbeab2006-01-17 22:52:51 +01001979 pci_set_power_state(pdev, PCI_D0);
1980 pci_restore_state(pdev);
1981
1982 if (netif_running(dev)) {
1983 netdev_open(dev);
1984 netif_device_attach(dev);
1985 }
1986
1987 return 0;
1988}
1989#endif /* CONFIG_PM */
1990
Linus Torvalds1da177e2005-04-16 15:20:36 -07001991
1992static void __devexit starfire_remove_one (struct pci_dev *pdev)
1993{
1994 struct net_device *dev = pci_get_drvdata(pdev);
1995 struct netdev_private *np = netdev_priv(dev);
1996
Eric Sesterhenn5d9428d2006-04-02 13:52:48 +02001997 BUG_ON(!dev);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001998
1999 unregister_netdev(dev);
2000
2001 if (np->queue_mem)
2002 pci_free_consistent(pdev, np->queue_mem_size, np->queue_mem, np->queue_mem_dma);
2003
2004
2005 /* XXX: add wakeup code -- requires firmware for MagicPacket */
2006 pci_set_power_state(pdev, PCI_D3hot); /* go to sleep in D3 mode */
2007 pci_disable_device(pdev);
2008
2009 iounmap(np->base);
2010 pci_release_regions(pdev);
2011
2012 pci_set_drvdata(pdev, NULL);
2013 free_netdev(dev); /* Will also free np!! */
2014}
2015
2016
2017static struct pci_driver starfire_driver = {
2018 .name = DRV_NAME,
2019 .probe = starfire_init_one,
2020 .remove = __devexit_p(starfire_remove_one),
Stefan Rompfd4fbeab2006-01-17 22:52:51 +01002021#ifdef CONFIG_PM
2022 .suspend = starfire_suspend,
2023 .resume = starfire_resume,
2024#endif /* CONFIG_PM */
Linus Torvalds1da177e2005-04-16 15:20:36 -07002025 .id_table = starfire_pci_tbl,
2026};
2027
2028
2029static int __init starfire_init (void)
2030{
2031/* when a module, this is printed whether or not devices are found in probe */
2032#ifdef MODULE
2033 printk(version);
Francois Romieua6676012008-07-06 20:54:45 -07002034
Jeff Garzikfdecea62005-05-12 20:16:24 -04002035 printk(KERN_INFO DRV_NAME ": polling (NAPI) enabled\n");
Jeff Garzikfdecea62005-05-12 20:16:24 -04002036#endif
2037
Linus Torvalds1da177e2005-04-16 15:20:36 -07002038 /* we can do this test only at run-time... sigh */
Ion Badulescu67974232005-10-03 22:31:36 -04002039 if (sizeof(dma_addr_t) != sizeof(netdrv_addr_t)) {
2040 printk("This driver has dma_addr_t issues, please send email to maintainer\n");
Linus Torvalds1da177e2005-04-16 15:20:36 -07002041 return -ENODEV;
2042 }
Ion Badulescu67974232005-10-03 22:31:36 -04002043
Jeff Garzik29917622006-08-19 17:48:59 -04002044 return pci_register_driver(&starfire_driver);
Linus Torvalds1da177e2005-04-16 15:20:36 -07002045}
2046
2047
2048static void __exit starfire_cleanup (void)
2049{
2050 pci_unregister_driver (&starfire_driver);
2051}
2052
2053
2054module_init(starfire_init);
2055module_exit(starfire_cleanup);
2056
2057
2058/*
2059 * Local variables:
2060 * c-basic-offset: 8
2061 * tab-width: 8
2062 * End:
2063 */