blob: 473155d34d7b7c500a1a1827589b4825712bf59a [file] [log] [blame]
Matt Porterc2dde5f2012-08-22 21:09:34 -04001/*
2 * TI EDMA DMA engine driver
3 *
4 * Copyright 2012 Texas Instruments
5 *
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License as
8 * published by the Free Software Foundation version 2.
9 *
10 * This program is distributed "as is" WITHOUT ANY WARRANTY of any
11 * kind, whether express or implied; without even the implied warranty
12 * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 */
15
16#include <linux/dmaengine.h>
17#include <linux/dma-mapping.h>
18#include <linux/err.h>
19#include <linux/init.h>
20#include <linux/interrupt.h>
21#include <linux/list.h>
22#include <linux/module.h>
23#include <linux/platform_device.h>
24#include <linux/slab.h>
25#include <linux/spinlock.h>
26
Matt Porter3ad7a422013-03-06 11:15:31 -050027#include <linux/platform_data/edma.h>
Matt Porterc2dde5f2012-08-22 21:09:34 -040028
29#include "dmaengine.h"
30#include "virt-dma.h"
31
32/*
33 * This will go away when the private EDMA API is folded
34 * into this driver and the platform device(s) are
35 * instantiated in the arch code. We can only get away
36 * with this simplification because DA8XX may not be built
37 * in the same kernel image with other DaVinci parts. This
38 * avoids having to sprinkle dmaengine driver platform devices
39 * and data throughout all the existing board files.
40 */
41#ifdef CONFIG_ARCH_DAVINCI_DA8XX
42#define EDMA_CTLRS 2
43#define EDMA_CHANS 32
44#else
45#define EDMA_CTLRS 1
46#define EDMA_CHANS 64
47#endif /* CONFIG_ARCH_DAVINCI_DA8XX */
48
Joel Fernandes2abd5f12013-09-23 18:05:15 -050049/*
50 * Max of 20 segments per channel to conserve PaRAM slots
51 * Also note that MAX_NR_SG should be atleast the no.of periods
52 * that are required for ASoC, otherwise DMA prep calls will
53 * fail. Today davinci-pcm is the only user of this driver and
54 * requires atleast 17 slots, so we setup the default to 20.
55 */
56#define MAX_NR_SG 20
Matt Porterc2dde5f2012-08-22 21:09:34 -040057#define EDMA_MAX_SLOTS MAX_NR_SG
58#define EDMA_DESCRIPTORS 16
59
60struct edma_desc {
61 struct virt_dma_desc vdesc;
62 struct list_head node;
Joel Fernandes50a9c702013-10-31 16:31:23 -050063 int cyclic;
Matt Porterc2dde5f2012-08-22 21:09:34 -040064 int absync;
65 int pset_nr;
Joel Fernandes53407062013-09-03 10:02:46 -050066 int processed;
Matt Porterc2dde5f2012-08-22 21:09:34 -040067 struct edmacc_param pset[0];
68};
69
70struct edma_cc;
71
72struct edma_chan {
73 struct virt_dma_chan vchan;
74 struct list_head node;
75 struct edma_desc *edesc;
76 struct edma_cc *ecc;
77 int ch_num;
78 bool alloced;
79 int slot[EDMA_MAX_SLOTS];
Joel Fernandesc5f47992013-08-29 18:05:43 -050080 int missed;
Matt Porter661f7cb2013-01-10 13:41:04 -050081 struct dma_slave_config cfg;
Matt Porterc2dde5f2012-08-22 21:09:34 -040082};
83
84struct edma_cc {
85 int ctlr;
86 struct dma_device dma_slave;
87 struct edma_chan slave_chans[EDMA_CHANS];
88 int num_slave_chans;
89 int dummy_slot;
90};
91
92static inline struct edma_cc *to_edma_cc(struct dma_device *d)
93{
94 return container_of(d, struct edma_cc, dma_slave);
95}
96
97static inline struct edma_chan *to_edma_chan(struct dma_chan *c)
98{
99 return container_of(c, struct edma_chan, vchan.chan);
100}
101
102static inline struct edma_desc
103*to_edma_desc(struct dma_async_tx_descriptor *tx)
104{
105 return container_of(tx, struct edma_desc, vdesc.tx);
106}
107
108static void edma_desc_free(struct virt_dma_desc *vdesc)
109{
110 kfree(container_of(vdesc, struct edma_desc, vdesc));
111}
112
113/* Dispatch a queued descriptor to the controller (caller holds lock) */
114static void edma_execute(struct edma_chan *echan)
115{
Joel Fernandes53407062013-09-03 10:02:46 -0500116 struct virt_dma_desc *vdesc;
Matt Porterc2dde5f2012-08-22 21:09:34 -0400117 struct edma_desc *edesc;
Joel Fernandes53407062013-09-03 10:02:46 -0500118 struct device *dev = echan->vchan.chan.device->dev;
119 int i, j, left, nslots;
Matt Porterc2dde5f2012-08-22 21:09:34 -0400120
Joel Fernandes53407062013-09-03 10:02:46 -0500121 /* If either we processed all psets or we're still not started */
122 if (!echan->edesc ||
123 echan->edesc->pset_nr == echan->edesc->processed) {
124 /* Get next vdesc */
125 vdesc = vchan_next_desc(&echan->vchan);
126 if (!vdesc) {
127 echan->edesc = NULL;
128 return;
129 }
130 list_del(&vdesc->node);
131 echan->edesc = to_edma_desc(&vdesc->tx);
Matt Porterc2dde5f2012-08-22 21:09:34 -0400132 }
133
Joel Fernandes53407062013-09-03 10:02:46 -0500134 edesc = echan->edesc;
Matt Porterc2dde5f2012-08-22 21:09:34 -0400135
Joel Fernandes53407062013-09-03 10:02:46 -0500136 /* Find out how many left */
137 left = edesc->pset_nr - edesc->processed;
138 nslots = min(MAX_NR_SG, left);
Matt Porterc2dde5f2012-08-22 21:09:34 -0400139
140 /* Write descriptor PaRAM set(s) */
Joel Fernandes53407062013-09-03 10:02:46 -0500141 for (i = 0; i < nslots; i++) {
142 j = i + edesc->processed;
143 edma_write_slot(echan->slot[i], &edesc->pset[j]);
Peter Ujfalusi83bb3122014-04-14 14:42:02 +0300144 dev_vdbg(echan->vchan.chan.device->dev,
Matt Porterc2dde5f2012-08-22 21:09:34 -0400145 "\n pset[%d]:\n"
146 " chnum\t%d\n"
147 " slot\t%d\n"
148 " opt\t%08x\n"
149 " src\t%08x\n"
150 " dst\t%08x\n"
151 " abcnt\t%08x\n"
152 " ccnt\t%08x\n"
153 " bidx\t%08x\n"
154 " cidx\t%08x\n"
155 " lkrld\t%08x\n",
Joel Fernandes53407062013-09-03 10:02:46 -0500156 j, echan->ch_num, echan->slot[i],
157 edesc->pset[j].opt,
158 edesc->pset[j].src,
159 edesc->pset[j].dst,
160 edesc->pset[j].a_b_cnt,
161 edesc->pset[j].ccnt,
162 edesc->pset[j].src_dst_bidx,
163 edesc->pset[j].src_dst_cidx,
164 edesc->pset[j].link_bcntrld);
Matt Porterc2dde5f2012-08-22 21:09:34 -0400165 /* Link to the previous slot if not the last set */
Joel Fernandes53407062013-09-03 10:02:46 -0500166 if (i != (nslots - 1))
Matt Porterc2dde5f2012-08-22 21:09:34 -0400167 edma_link(echan->slot[i], echan->slot[i+1]);
Matt Porterc2dde5f2012-08-22 21:09:34 -0400168 }
169
Joel Fernandes53407062013-09-03 10:02:46 -0500170 edesc->processed += nslots;
171
Joel Fernandesb267b3b2013-08-29 18:05:44 -0500172 /*
173 * If this is either the last set in a set of SG-list transactions
174 * then setup a link to the dummy slot, this results in all future
175 * events being absorbed and that's OK because we're done
176 */
Joel Fernandes50a9c702013-10-31 16:31:23 -0500177 if (edesc->processed == edesc->pset_nr) {
178 if (edesc->cyclic)
179 edma_link(echan->slot[nslots-1], echan->slot[1]);
180 else
181 edma_link(echan->slot[nslots-1],
182 echan->ecc->dummy_slot);
183 }
Joel Fernandesb267b3b2013-08-29 18:05:44 -0500184
Joel Fernandes53407062013-09-03 10:02:46 -0500185 if (edesc->processed <= MAX_NR_SG) {
Peter Ujfalusi9aac9092014-04-24 10:29:50 +0300186 dev_dbg(dev, "first transfer starting on channel %d\n",
187 echan->ch_num);
Joel Fernandes53407062013-09-03 10:02:46 -0500188 edma_start(echan->ch_num);
Sekhar Nori5fc68a62014-03-19 11:25:50 +0530189 } else {
190 dev_dbg(dev, "chan: %d: completed %d elements, resuming\n",
191 echan->ch_num, edesc->processed);
192 edma_resume(echan->ch_num);
Joel Fernandes53407062013-09-03 10:02:46 -0500193 }
Joel Fernandesc5f47992013-08-29 18:05:43 -0500194
195 /*
196 * This happens due to setup times between intermediate transfers
197 * in long SG lists which have to be broken up into transfers of
198 * MAX_NR_SG
199 */
200 if (echan->missed) {
Peter Ujfalusi9aac9092014-04-24 10:29:50 +0300201 dev_dbg(dev, "missed event on channel %d\n", echan->ch_num);
Joel Fernandesc5f47992013-08-29 18:05:43 -0500202 edma_clean_channel(echan->ch_num);
203 edma_stop(echan->ch_num);
204 edma_start(echan->ch_num);
205 edma_trigger_channel(echan->ch_num);
206 echan->missed = 0;
207 }
Matt Porterc2dde5f2012-08-22 21:09:34 -0400208}
209
210static int edma_terminate_all(struct edma_chan *echan)
211{
212 unsigned long flags;
213 LIST_HEAD(head);
214
215 spin_lock_irqsave(&echan->vchan.lock, flags);
216
217 /*
218 * Stop DMA activity: we assume the callback will not be called
219 * after edma_dma() returns (even if it does, it will see
220 * echan->edesc is NULL and exit.)
221 */
222 if (echan->edesc) {
223 echan->edesc = NULL;
224 edma_stop(echan->ch_num);
225 }
226
227 vchan_get_all_descriptors(&echan->vchan, &head);
228 spin_unlock_irqrestore(&echan->vchan.lock, flags);
229 vchan_dma_desc_free_list(&echan->vchan, &head);
230
231 return 0;
232}
233
Matt Porterc2dde5f2012-08-22 21:09:34 -0400234static int edma_slave_config(struct edma_chan *echan,
Matt Porter661f7cb2013-01-10 13:41:04 -0500235 struct dma_slave_config *cfg)
Matt Porterc2dde5f2012-08-22 21:09:34 -0400236{
Matt Porter661f7cb2013-01-10 13:41:04 -0500237 if (cfg->src_addr_width == DMA_SLAVE_BUSWIDTH_8_BYTES ||
238 cfg->dst_addr_width == DMA_SLAVE_BUSWIDTH_8_BYTES)
Matt Porterc2dde5f2012-08-22 21:09:34 -0400239 return -EINVAL;
240
Matt Porter661f7cb2013-01-10 13:41:04 -0500241 memcpy(&echan->cfg, cfg, sizeof(echan->cfg));
Matt Porterc2dde5f2012-08-22 21:09:34 -0400242
243 return 0;
244}
245
Peter Ujfalusi72c7b672014-04-14 14:41:59 +0300246static int edma_dma_pause(struct edma_chan *echan)
247{
248 /* Pause/Resume only allowed with cyclic mode */
249 if (!echan->edesc->cyclic)
250 return -EINVAL;
251
252 edma_pause(echan->ch_num);
253 return 0;
254}
255
256static int edma_dma_resume(struct edma_chan *echan)
257{
258 /* Pause/Resume only allowed with cyclic mode */
259 if (!echan->edesc->cyclic)
260 return -EINVAL;
261
262 edma_resume(echan->ch_num);
263 return 0;
264}
265
Matt Porterc2dde5f2012-08-22 21:09:34 -0400266static int edma_control(struct dma_chan *chan, enum dma_ctrl_cmd cmd,
267 unsigned long arg)
268{
269 int ret = 0;
270 struct dma_slave_config *config;
271 struct edma_chan *echan = to_edma_chan(chan);
272
273 switch (cmd) {
274 case DMA_TERMINATE_ALL:
275 edma_terminate_all(echan);
276 break;
277 case DMA_SLAVE_CONFIG:
278 config = (struct dma_slave_config *)arg;
279 ret = edma_slave_config(echan, config);
280 break;
Peter Ujfalusi72c7b672014-04-14 14:41:59 +0300281 case DMA_PAUSE:
282 ret = edma_dma_pause(echan);
283 break;
284
285 case DMA_RESUME:
286 ret = edma_dma_resume(echan);
287 break;
288
Matt Porterc2dde5f2012-08-22 21:09:34 -0400289 default:
290 ret = -ENOSYS;
291 }
292
293 return ret;
294}
295
Joel Fernandesfd009032013-09-23 18:05:13 -0500296/*
297 * A PaRAM set configuration abstraction used by other modes
298 * @chan: Channel who's PaRAM set we're configuring
299 * @pset: PaRAM set to initialize and setup.
300 * @src_addr: Source address of the DMA
301 * @dst_addr: Destination address of the DMA
302 * @burst: In units of dev_width, how much to send
303 * @dev_width: How much is the dev_width
304 * @dma_length: Total length of the DMA transfer
305 * @direction: Direction of the transfer
306 */
307static int edma_config_pset(struct dma_chan *chan, struct edmacc_param *pset,
308 dma_addr_t src_addr, dma_addr_t dst_addr, u32 burst,
309 enum dma_slave_buswidth dev_width, unsigned int dma_length,
310 enum dma_transfer_direction direction)
311{
312 struct edma_chan *echan = to_edma_chan(chan);
313 struct device *dev = chan->device->dev;
314 int acnt, bcnt, ccnt, cidx;
315 int src_bidx, dst_bidx, src_cidx, dst_cidx;
316 int absync;
317
318 acnt = dev_width;
Peter Ujfalusib2b617d2014-04-14 14:41:58 +0300319
320 /* src/dst_maxburst == 0 is the same case as src/dst_maxburst == 1 */
321 if (!burst)
322 burst = 1;
Joel Fernandesfd009032013-09-23 18:05:13 -0500323 /*
324 * If the maxburst is equal to the fifo width, use
325 * A-synced transfers. This allows for large contiguous
326 * buffer transfers using only one PaRAM set.
327 */
328 if (burst == 1) {
329 /*
330 * For the A-sync case, bcnt and ccnt are the remainder
331 * and quotient respectively of the division of:
332 * (dma_length / acnt) by (SZ_64K -1). This is so
333 * that in case bcnt over flows, we have ccnt to use.
334 * Note: In A-sync tranfer only, bcntrld is used, but it
335 * only applies for sg_dma_len(sg) >= SZ_64K.
336 * In this case, the best way adopted is- bccnt for the
337 * first frame will be the remainder below. Then for
338 * every successive frame, bcnt will be SZ_64K-1. This
339 * is assured as bcntrld = 0xffff in end of function.
340 */
341 absync = false;
342 ccnt = dma_length / acnt / (SZ_64K - 1);
343 bcnt = dma_length / acnt - ccnt * (SZ_64K - 1);
344 /*
345 * If bcnt is non-zero, we have a remainder and hence an
346 * extra frame to transfer, so increment ccnt.
347 */
348 if (bcnt)
349 ccnt++;
350 else
351 bcnt = SZ_64K - 1;
352 cidx = acnt;
353 } else {
354 /*
355 * If maxburst is greater than the fifo address_width,
356 * use AB-synced transfers where A count is the fifo
357 * address_width and B count is the maxburst. In this
358 * case, we are limited to transfers of C count frames
359 * of (address_width * maxburst) where C count is limited
360 * to SZ_64K-1. This places an upper bound on the length
361 * of an SG segment that can be handled.
362 */
363 absync = true;
364 bcnt = burst;
365 ccnt = dma_length / (acnt * bcnt);
366 if (ccnt > (SZ_64K - 1)) {
367 dev_err(dev, "Exceeded max SG segment size\n");
368 return -EINVAL;
369 }
370 cidx = acnt * bcnt;
371 }
372
373 if (direction == DMA_MEM_TO_DEV) {
374 src_bidx = acnt;
375 src_cidx = cidx;
376 dst_bidx = 0;
377 dst_cidx = 0;
378 } else if (direction == DMA_DEV_TO_MEM) {
379 src_bidx = 0;
380 src_cidx = 0;
381 dst_bidx = acnt;
382 dst_cidx = cidx;
Joel Fernandes8cc3e302014-04-18 21:50:33 -0500383 } else if (direction == DMA_MEM_TO_MEM) {
384 src_bidx = acnt;
385 src_cidx = cidx;
386 dst_bidx = acnt;
387 dst_cidx = cidx;
Joel Fernandesfd009032013-09-23 18:05:13 -0500388 } else {
389 dev_err(dev, "%s: direction not implemented yet\n", __func__);
390 return -EINVAL;
391 }
392
393 pset->opt = EDMA_TCC(EDMA_CHAN_SLOT(echan->ch_num));
394 /* Configure A or AB synchronized transfers */
395 if (absync)
396 pset->opt |= SYNCDIM;
397
398 pset->src = src_addr;
399 pset->dst = dst_addr;
400
401 pset->src_dst_bidx = (dst_bidx << 16) | src_bidx;
402 pset->src_dst_cidx = (dst_cidx << 16) | src_cidx;
403
404 pset->a_b_cnt = bcnt << 16 | acnt;
405 pset->ccnt = ccnt;
406 /*
407 * Only time when (bcntrld) auto reload is required is for
408 * A-sync case, and in this case, a requirement of reload value
409 * of SZ_64K-1 only is assured. 'link' is initially set to NULL
410 * and then later will be populated by edma_execute.
411 */
412 pset->link_bcntrld = 0xffffffff;
413 return absync;
414}
415
Matt Porterc2dde5f2012-08-22 21:09:34 -0400416static struct dma_async_tx_descriptor *edma_prep_slave_sg(
417 struct dma_chan *chan, struct scatterlist *sgl,
418 unsigned int sg_len, enum dma_transfer_direction direction,
419 unsigned long tx_flags, void *context)
420{
421 struct edma_chan *echan = to_edma_chan(chan);
422 struct device *dev = chan->device->dev;
423 struct edma_desc *edesc;
Joel Fernandesfd009032013-09-23 18:05:13 -0500424 dma_addr_t src_addr = 0, dst_addr = 0;
Matt Porter661f7cb2013-01-10 13:41:04 -0500425 enum dma_slave_buswidth dev_width;
426 u32 burst;
Matt Porterc2dde5f2012-08-22 21:09:34 -0400427 struct scatterlist *sg;
Joel Fernandesfd009032013-09-23 18:05:13 -0500428 int i, nslots, ret;
Matt Porterc2dde5f2012-08-22 21:09:34 -0400429
430 if (unlikely(!echan || !sgl || !sg_len))
431 return NULL;
432
Matt Porter661f7cb2013-01-10 13:41:04 -0500433 if (direction == DMA_DEV_TO_MEM) {
Joel Fernandesfd009032013-09-23 18:05:13 -0500434 src_addr = echan->cfg.src_addr;
Matt Porter661f7cb2013-01-10 13:41:04 -0500435 dev_width = echan->cfg.src_addr_width;
436 burst = echan->cfg.src_maxburst;
437 } else if (direction == DMA_MEM_TO_DEV) {
Joel Fernandesfd009032013-09-23 18:05:13 -0500438 dst_addr = echan->cfg.dst_addr;
Matt Porter661f7cb2013-01-10 13:41:04 -0500439 dev_width = echan->cfg.dst_addr_width;
440 burst = echan->cfg.dst_maxburst;
441 } else {
Peter Ujfalusie6fad592014-04-14 14:42:05 +0300442 dev_err(dev, "%s: bad direction: %d\n", __func__, direction);
Matt Porter661f7cb2013-01-10 13:41:04 -0500443 return NULL;
444 }
445
446 if (dev_width == DMA_SLAVE_BUSWIDTH_UNDEFINED) {
Peter Ujfalusic594c892014-04-14 14:42:03 +0300447 dev_err(dev, "%s: Undefined slave buswidth\n", __func__);
Matt Porterc2dde5f2012-08-22 21:09:34 -0400448 return NULL;
449 }
450
Matt Porterc2dde5f2012-08-22 21:09:34 -0400451 edesc = kzalloc(sizeof(*edesc) + sg_len *
452 sizeof(edesc->pset[0]), GFP_ATOMIC);
453 if (!edesc) {
Peter Ujfalusic594c892014-04-14 14:42:03 +0300454 dev_err(dev, "%s: Failed to allocate a descriptor\n", __func__);
Matt Porterc2dde5f2012-08-22 21:09:34 -0400455 return NULL;
456 }
457
458 edesc->pset_nr = sg_len;
459
Joel Fernandes6fbe24d2013-08-29 18:05:40 -0500460 /* Allocate a PaRAM slot, if needed */
461 nslots = min_t(unsigned, MAX_NR_SG, sg_len);
462
463 for (i = 0; i < nslots; i++) {
Matt Porterc2dde5f2012-08-22 21:09:34 -0400464 if (echan->slot[i] < 0) {
465 echan->slot[i] =
466 edma_alloc_slot(EDMA_CTLR(echan->ch_num),
467 EDMA_SLOT_ANY);
468 if (echan->slot[i] < 0) {
Valentin Ilie4b6271a2013-10-24 16:14:22 +0300469 kfree(edesc);
Peter Ujfalusic594c892014-04-14 14:42:03 +0300470 dev_err(dev, "%s: Failed to allocate slot\n",
471 __func__);
Matt Porterc2dde5f2012-08-22 21:09:34 -0400472 return NULL;
473 }
474 }
Joel Fernandes6fbe24d2013-08-29 18:05:40 -0500475 }
476
477 /* Configure PaRAM sets for each SG */
478 for_each_sg(sgl, sg, sg_len, i) {
Joel Fernandesfd009032013-09-23 18:05:13 -0500479 /* Get address for each SG */
480 if (direction == DMA_DEV_TO_MEM)
481 dst_addr = sg_dma_address(sg);
482 else
483 src_addr = sg_dma_address(sg);
Matt Porterc2dde5f2012-08-22 21:09:34 -0400484
Joel Fernandesfd009032013-09-23 18:05:13 -0500485 ret = edma_config_pset(chan, &edesc->pset[i], src_addr,
486 dst_addr, burst, dev_width,
487 sg_dma_len(sg), direction);
Vinod Koulb967aec2013-10-30 13:07:18 +0530488 if (ret < 0) {
489 kfree(edesc);
Joel Fernandesfd009032013-09-23 18:05:13 -0500490 return NULL;
Matt Porterc2dde5f2012-08-22 21:09:34 -0400491 }
492
Joel Fernandesfd009032013-09-23 18:05:13 -0500493 edesc->absync = ret;
Joel Fernandes6fbe24d2013-08-29 18:05:40 -0500494
495 /* If this is the last in a current SG set of transactions,
496 enable interrupts so that next set is processed */
497 if (!((i+1) % MAX_NR_SG))
498 edesc->pset[i].opt |= TCINTEN;
499
Matt Porterc2dde5f2012-08-22 21:09:34 -0400500 /* If this is the last set, enable completion interrupt flag */
501 if (i == sg_len - 1)
502 edesc->pset[i].opt |= TCINTEN;
Matt Porterc2dde5f2012-08-22 21:09:34 -0400503 }
Matt Porterc2dde5f2012-08-22 21:09:34 -0400504
Matt Porterc2dde5f2012-08-22 21:09:34 -0400505 return vchan_tx_prep(&echan->vchan, &edesc->vdesc, tx_flags);
506}
Matt Porterc2dde5f2012-08-22 21:09:34 -0400507
Joel Fernandes8cc3e302014-04-18 21:50:33 -0500508struct dma_async_tx_descriptor *edma_prep_dma_memcpy(
509 struct dma_chan *chan, dma_addr_t dest, dma_addr_t src,
510 size_t len, unsigned long tx_flags)
511{
512 int ret;
513 struct edma_desc *edesc;
514 struct device *dev = chan->device->dev;
515 struct edma_chan *echan = to_edma_chan(chan);
516
517 if (unlikely(!echan || !len))
518 return NULL;
519
520 edesc = kzalloc(sizeof(*edesc) + sizeof(edesc->pset[0]), GFP_ATOMIC);
521 if (!edesc) {
522 dev_dbg(dev, "Failed to allocate a descriptor\n");
523 return NULL;
524 }
525
526 edesc->pset_nr = 1;
527
528 ret = edma_config_pset(chan, &edesc->pset[0], src, dest, 1,
529 DMA_SLAVE_BUSWIDTH_4_BYTES, len, DMA_MEM_TO_MEM);
530 if (ret < 0)
531 return NULL;
532
533 edesc->absync = ret;
534
535 /*
536 * Enable intermediate transfer chaining to re-trigger channel
537 * on completion of every TR, and enable transfer-completion
538 * interrupt on completion of the whole transfer.
539 */
540 edesc->pset[0].opt |= ITCCHEN;
541 edesc->pset[0].opt |= TCINTEN;
542
543 return vchan_tx_prep(&echan->vchan, &edesc->vdesc, tx_flags);
544}
545
Joel Fernandes50a9c702013-10-31 16:31:23 -0500546static struct dma_async_tx_descriptor *edma_prep_dma_cyclic(
547 struct dma_chan *chan, dma_addr_t buf_addr, size_t buf_len,
548 size_t period_len, enum dma_transfer_direction direction,
549 unsigned long tx_flags, void *context)
550{
551 struct edma_chan *echan = to_edma_chan(chan);
552 struct device *dev = chan->device->dev;
553 struct edma_desc *edesc;
554 dma_addr_t src_addr, dst_addr;
555 enum dma_slave_buswidth dev_width;
556 u32 burst;
557 int i, ret, nslots;
Matt Porterc2dde5f2012-08-22 21:09:34 -0400558
Joel Fernandes50a9c702013-10-31 16:31:23 -0500559 if (unlikely(!echan || !buf_len || !period_len))
560 return NULL;
Matt Porterc2dde5f2012-08-22 21:09:34 -0400561
Joel Fernandes50a9c702013-10-31 16:31:23 -0500562 if (direction == DMA_DEV_TO_MEM) {
563 src_addr = echan->cfg.src_addr;
564 dst_addr = buf_addr;
565 dev_width = echan->cfg.src_addr_width;
566 burst = echan->cfg.src_maxburst;
567 } else if (direction == DMA_MEM_TO_DEV) {
568 src_addr = buf_addr;
569 dst_addr = echan->cfg.dst_addr;
570 dev_width = echan->cfg.dst_addr_width;
571 burst = echan->cfg.dst_maxburst;
572 } else {
Peter Ujfalusie6fad592014-04-14 14:42:05 +0300573 dev_err(dev, "%s: bad direction: %d\n", __func__, direction);
Joel Fernandes50a9c702013-10-31 16:31:23 -0500574 return NULL;
575 }
576
577 if (dev_width == DMA_SLAVE_BUSWIDTH_UNDEFINED) {
Peter Ujfalusic594c892014-04-14 14:42:03 +0300578 dev_err(dev, "%s: Undefined slave buswidth\n", __func__);
Joel Fernandes50a9c702013-10-31 16:31:23 -0500579 return NULL;
580 }
581
582 if (unlikely(buf_len % period_len)) {
583 dev_err(dev, "Period should be multiple of Buffer length\n");
584 return NULL;
585 }
586
587 nslots = (buf_len / period_len) + 1;
588
589 /*
590 * Cyclic DMA users such as audio cannot tolerate delays introduced
591 * by cases where the number of periods is more than the maximum
592 * number of SGs the EDMA driver can handle at a time. For DMA types
593 * such as Slave SGs, such delays are tolerable and synchronized,
594 * but the synchronization is difficult to achieve with Cyclic and
595 * cannot be guaranteed, so we error out early.
596 */
597 if (nslots > MAX_NR_SG)
598 return NULL;
599
600 edesc = kzalloc(sizeof(*edesc) + nslots *
601 sizeof(edesc->pset[0]), GFP_ATOMIC);
602 if (!edesc) {
Peter Ujfalusic594c892014-04-14 14:42:03 +0300603 dev_err(dev, "%s: Failed to allocate a descriptor\n", __func__);
Joel Fernandes50a9c702013-10-31 16:31:23 -0500604 return NULL;
605 }
606
607 edesc->cyclic = 1;
608 edesc->pset_nr = nslots;
609
Peter Ujfalusi83bb3122014-04-14 14:42:02 +0300610 dev_dbg(dev, "%s: channel=%d nslots=%d period_len=%zu buf_len=%zu\n",
611 __func__, echan->ch_num, nslots, period_len, buf_len);
Joel Fernandes50a9c702013-10-31 16:31:23 -0500612
613 for (i = 0; i < nslots; i++) {
614 /* Allocate a PaRAM slot, if needed */
615 if (echan->slot[i] < 0) {
616 echan->slot[i] =
617 edma_alloc_slot(EDMA_CTLR(echan->ch_num),
618 EDMA_SLOT_ANY);
619 if (echan->slot[i] < 0) {
Christian Engelmayere3ddc972013-12-30 20:48:39 +0100620 kfree(edesc);
Peter Ujfalusic594c892014-04-14 14:42:03 +0300621 dev_err(dev, "%s: Failed to allocate slot\n",
622 __func__);
Joel Fernandes50a9c702013-10-31 16:31:23 -0500623 return NULL;
624 }
625 }
626
627 if (i == nslots - 1) {
628 memcpy(&edesc->pset[i], &edesc->pset[0],
629 sizeof(edesc->pset[0]));
630 break;
631 }
632
633 ret = edma_config_pset(chan, &edesc->pset[i], src_addr,
634 dst_addr, burst, dev_width, period_len,
635 direction);
Christian Engelmayere3ddc972013-12-30 20:48:39 +0100636 if (ret < 0) {
637 kfree(edesc);
Joel Fernandes50a9c702013-10-31 16:31:23 -0500638 return NULL;
Christian Engelmayere3ddc972013-12-30 20:48:39 +0100639 }
Joel Fernandes50a9c702013-10-31 16:31:23 -0500640
641 if (direction == DMA_DEV_TO_MEM)
642 dst_addr += period_len;
643 else
644 src_addr += period_len;
645
Peter Ujfalusi83bb3122014-04-14 14:42:02 +0300646 dev_vdbg(dev, "%s: Configure period %d of buf:\n", __func__, i);
647 dev_vdbg(dev,
Joel Fernandes50a9c702013-10-31 16:31:23 -0500648 "\n pset[%d]:\n"
649 " chnum\t%d\n"
650 " slot\t%d\n"
651 " opt\t%08x\n"
652 " src\t%08x\n"
653 " dst\t%08x\n"
654 " abcnt\t%08x\n"
655 " ccnt\t%08x\n"
656 " bidx\t%08x\n"
657 " cidx\t%08x\n"
658 " lkrld\t%08x\n",
659 i, echan->ch_num, echan->slot[i],
660 edesc->pset[i].opt,
661 edesc->pset[i].src,
662 edesc->pset[i].dst,
663 edesc->pset[i].a_b_cnt,
664 edesc->pset[i].ccnt,
665 edesc->pset[i].src_dst_bidx,
666 edesc->pset[i].src_dst_cidx,
667 edesc->pset[i].link_bcntrld);
668
669 edesc->absync = ret;
670
671 /*
672 * Enable interrupts for every period because callback
673 * has to be called for every period.
674 */
675 edesc->pset[i].opt |= TCINTEN;
Matt Porterc2dde5f2012-08-22 21:09:34 -0400676 }
677
678 return vchan_tx_prep(&echan->vchan, &edesc->vdesc, tx_flags);
679}
680
681static void edma_callback(unsigned ch_num, u16 ch_status, void *data)
682{
683 struct edma_chan *echan = data;
684 struct device *dev = echan->vchan.chan.device->dev;
685 struct edma_desc *edesc;
Joel Fernandesc5f47992013-08-29 18:05:43 -0500686 struct edmacc_param p;
Matt Porterc2dde5f2012-08-22 21:09:34 -0400687
Joel Fernandes50a9c702013-10-31 16:31:23 -0500688 edesc = echan->edesc;
689
690 /* Pause the channel for non-cyclic */
691 if (!edesc || (edesc && !edesc->cyclic))
692 edma_pause(echan->ch_num);
Matt Porterc2dde5f2012-08-22 21:09:34 -0400693
694 switch (ch_status) {
Vinod Kouldb60d8d2013-10-30 18:22:30 +0530695 case EDMA_DMA_COMPLETE:
Joel Fernandes406efb12014-04-17 00:58:33 -0500696 spin_lock(&echan->vchan.lock);
Matt Porterc2dde5f2012-08-22 21:09:34 -0400697
Matt Porterc2dde5f2012-08-22 21:09:34 -0400698 if (edesc) {
Joel Fernandes50a9c702013-10-31 16:31:23 -0500699 if (edesc->cyclic) {
700 vchan_cyclic_callback(&edesc->vdesc);
701 } else if (edesc->processed == edesc->pset_nr) {
Joel Fernandes53407062013-09-03 10:02:46 -0500702 dev_dbg(dev, "Transfer complete, stopping channel %d\n", ch_num);
703 edma_stop(echan->ch_num);
704 vchan_cookie_complete(&edesc->vdesc);
Joel Fernandes50a9c702013-10-31 16:31:23 -0500705 edma_execute(echan);
Joel Fernandes53407062013-09-03 10:02:46 -0500706 } else {
707 dev_dbg(dev, "Intermediate transfer complete on channel %d\n", ch_num);
Joel Fernandes50a9c702013-10-31 16:31:23 -0500708 edma_execute(echan);
Joel Fernandes53407062013-09-03 10:02:46 -0500709 }
Matt Porterc2dde5f2012-08-22 21:09:34 -0400710 }
711
Joel Fernandes406efb12014-04-17 00:58:33 -0500712 spin_unlock(&echan->vchan.lock);
Matt Porterc2dde5f2012-08-22 21:09:34 -0400713
714 break;
Vinod Kouldb60d8d2013-10-30 18:22:30 +0530715 case EDMA_DMA_CC_ERROR:
Joel Fernandes406efb12014-04-17 00:58:33 -0500716 spin_lock(&echan->vchan.lock);
Joel Fernandesc5f47992013-08-29 18:05:43 -0500717
718 edma_read_slot(EDMA_CHAN_SLOT(echan->slot[0]), &p);
719
720 /*
721 * Issue later based on missed flag which will be sure
722 * to happen as:
723 * (1) we finished transmitting an intermediate slot and
724 * edma_execute is coming up.
725 * (2) or we finished current transfer and issue will
726 * call edma_execute.
727 *
728 * Important note: issuing can be dangerous here and
729 * lead to some nasty recursion when we are in a NULL
730 * slot. So we avoid doing so and set the missed flag.
731 */
732 if (p.a_b_cnt == 0 && p.ccnt == 0) {
733 dev_dbg(dev, "Error occurred, looks like slot is null, just setting miss\n");
734 echan->missed = 1;
735 } else {
736 /*
737 * The slot is already programmed but the event got
738 * missed, so its safe to issue it here.
739 */
740 dev_dbg(dev, "Error occurred but slot is non-null, TRIGGERING\n");
741 edma_clean_channel(echan->ch_num);
742 edma_stop(echan->ch_num);
743 edma_start(echan->ch_num);
744 edma_trigger_channel(echan->ch_num);
745 }
746
Joel Fernandes406efb12014-04-17 00:58:33 -0500747 spin_unlock(&echan->vchan.lock);
Joel Fernandesc5f47992013-08-29 18:05:43 -0500748
Matt Porterc2dde5f2012-08-22 21:09:34 -0400749 break;
750 default:
751 break;
752 }
753}
754
755/* Alloc channel resources */
756static int edma_alloc_chan_resources(struct dma_chan *chan)
757{
758 struct edma_chan *echan = to_edma_chan(chan);
759 struct device *dev = chan->device->dev;
760 int ret;
761 int a_ch_num;
762 LIST_HEAD(descs);
763
764 a_ch_num = edma_alloc_channel(echan->ch_num, edma_callback,
765 chan, EVENTQ_DEFAULT);
766
767 if (a_ch_num < 0) {
768 ret = -ENODEV;
769 goto err_no_chan;
770 }
771
772 if (a_ch_num != echan->ch_num) {
773 dev_err(dev, "failed to allocate requested channel %u:%u\n",
774 EDMA_CTLR(echan->ch_num),
775 EDMA_CHAN_SLOT(echan->ch_num));
776 ret = -ENODEV;
777 goto err_wrong_chan;
778 }
779
780 echan->alloced = true;
781 echan->slot[0] = echan->ch_num;
782
Peter Ujfalusi9aac9092014-04-24 10:29:50 +0300783 dev_dbg(dev, "allocated channel %d for %u:%u\n", echan->ch_num,
Ezequiel Garcia0e772c62013-12-13 11:06:18 -0300784 EDMA_CTLR(echan->ch_num), EDMA_CHAN_SLOT(echan->ch_num));
Matt Porterc2dde5f2012-08-22 21:09:34 -0400785
786 return 0;
787
788err_wrong_chan:
789 edma_free_channel(a_ch_num);
790err_no_chan:
791 return ret;
792}
793
794/* Free channel resources */
795static void edma_free_chan_resources(struct dma_chan *chan)
796{
797 struct edma_chan *echan = to_edma_chan(chan);
798 struct device *dev = chan->device->dev;
799 int i;
800
801 /* Terminate transfers */
802 edma_stop(echan->ch_num);
803
804 vchan_free_chan_resources(&echan->vchan);
805
806 /* Free EDMA PaRAM slots */
807 for (i = 1; i < EDMA_MAX_SLOTS; i++) {
808 if (echan->slot[i] >= 0) {
809 edma_free_slot(echan->slot[i]);
810 echan->slot[i] = -1;
811 }
812 }
813
814 /* Free EDMA channel */
815 if (echan->alloced) {
816 edma_free_channel(echan->ch_num);
817 echan->alloced = false;
818 }
819
Ezequiel Garcia0e772c62013-12-13 11:06:18 -0300820 dev_dbg(dev, "freeing channel for %u\n", echan->ch_num);
Matt Porterc2dde5f2012-08-22 21:09:34 -0400821}
822
823/* Send pending descriptor to hardware */
824static void edma_issue_pending(struct dma_chan *chan)
825{
826 struct edma_chan *echan = to_edma_chan(chan);
827 unsigned long flags;
828
829 spin_lock_irqsave(&echan->vchan.lock, flags);
830 if (vchan_issue_pending(&echan->vchan) && !echan->edesc)
831 edma_execute(echan);
832 spin_unlock_irqrestore(&echan->vchan.lock, flags);
833}
834
835static size_t edma_desc_size(struct edma_desc *edesc)
836{
837 int i;
838 size_t size;
839
840 if (edesc->absync)
841 for (size = i = 0; i < edesc->pset_nr; i++)
842 size += (edesc->pset[i].a_b_cnt & 0xffff) *
843 (edesc->pset[i].a_b_cnt >> 16) *
844 edesc->pset[i].ccnt;
845 else
846 size = (edesc->pset[0].a_b_cnt & 0xffff) *
847 (edesc->pset[0].a_b_cnt >> 16) +
848 (edesc->pset[0].a_b_cnt & 0xffff) *
849 (SZ_64K - 1) * edesc->pset[0].ccnt;
850
851 return size;
852}
853
854/* Check request completion status */
855static enum dma_status edma_tx_status(struct dma_chan *chan,
856 dma_cookie_t cookie,
857 struct dma_tx_state *txstate)
858{
859 struct edma_chan *echan = to_edma_chan(chan);
860 struct virt_dma_desc *vdesc;
861 enum dma_status ret;
862 unsigned long flags;
863
864 ret = dma_cookie_status(chan, cookie, txstate);
Vinod Koul9d386ec2013-10-16 13:42:15 +0530865 if (ret == DMA_COMPLETE || !txstate)
Matt Porterc2dde5f2012-08-22 21:09:34 -0400866 return ret;
867
868 spin_lock_irqsave(&echan->vchan.lock, flags);
869 vdesc = vchan_find_desc(&echan->vchan, cookie);
870 if (vdesc) {
871 txstate->residue = edma_desc_size(to_edma_desc(&vdesc->tx));
872 } else if (echan->edesc && echan->edesc->vdesc.tx.cookie == cookie) {
873 struct edma_desc *edesc = echan->edesc;
874 txstate->residue = edma_desc_size(edesc);
Matt Porterc2dde5f2012-08-22 21:09:34 -0400875 }
876 spin_unlock_irqrestore(&echan->vchan.lock, flags);
877
878 return ret;
879}
880
881static void __init edma_chan_init(struct edma_cc *ecc,
882 struct dma_device *dma,
883 struct edma_chan *echans)
884{
885 int i, j;
886
887 for (i = 0; i < EDMA_CHANS; i++) {
888 struct edma_chan *echan = &echans[i];
889 echan->ch_num = EDMA_CTLR_CHAN(ecc->ctlr, i);
890 echan->ecc = ecc;
891 echan->vchan.desc_free = edma_desc_free;
892
893 vchan_init(&echan->vchan, dma);
894
895 INIT_LIST_HEAD(&echan->node);
896 for (j = 0; j < EDMA_MAX_SLOTS; j++)
897 echan->slot[j] = -1;
898 }
899}
900
Peter Ujfalusi2c88ee62014-04-14 14:42:01 +0300901#define EDMA_DMA_BUSWIDTHS (BIT(DMA_SLAVE_BUSWIDTH_1_BYTE) | \
902 BIT(DMA_SLAVE_BUSWIDTH_2_BYTES) | \
903 BIT(DMA_SLAVE_BUSWIDTH_4_BYTES))
904
905static int edma_dma_device_slave_caps(struct dma_chan *dchan,
906 struct dma_slave_caps *caps)
907{
908 caps->src_addr_widths = EDMA_DMA_BUSWIDTHS;
909 caps->dstn_addr_widths = EDMA_DMA_BUSWIDTHS;
910 caps->directions = BIT(DMA_DEV_TO_MEM) | BIT(DMA_MEM_TO_DEV);
911 caps->cmd_pause = true;
912 caps->cmd_terminate = true;
913 caps->residue_granularity = DMA_RESIDUE_GRANULARITY_DESCRIPTOR;
914
915 return 0;
916}
917
Matt Porterc2dde5f2012-08-22 21:09:34 -0400918static void edma_dma_init(struct edma_cc *ecc, struct dma_device *dma,
919 struct device *dev)
920{
921 dma->device_prep_slave_sg = edma_prep_slave_sg;
Joel Fernandes50a9c702013-10-31 16:31:23 -0500922 dma->device_prep_dma_cyclic = edma_prep_dma_cyclic;
Joel Fernandes8cc3e302014-04-18 21:50:33 -0500923 dma->device_prep_dma_memcpy = edma_prep_dma_memcpy;
Matt Porterc2dde5f2012-08-22 21:09:34 -0400924 dma->device_alloc_chan_resources = edma_alloc_chan_resources;
925 dma->device_free_chan_resources = edma_free_chan_resources;
926 dma->device_issue_pending = edma_issue_pending;
927 dma->device_tx_status = edma_tx_status;
928 dma->device_control = edma_control;
Peter Ujfalusi2c88ee62014-04-14 14:42:01 +0300929 dma->device_slave_caps = edma_dma_device_slave_caps;
Matt Porterc2dde5f2012-08-22 21:09:34 -0400930 dma->dev = dev;
931
Joel Fernandes8cc3e302014-04-18 21:50:33 -0500932 /*
933 * code using dma memcpy must make sure alignment of
934 * length is at dma->copy_align boundary.
935 */
936 dma->copy_align = DMA_SLAVE_BUSWIDTH_4_BYTES;
937
Matt Porterc2dde5f2012-08-22 21:09:34 -0400938 INIT_LIST_HEAD(&dma->channels);
939}
940
Bill Pemberton463a1f82012-11-19 13:22:55 -0500941static int edma_probe(struct platform_device *pdev)
Matt Porterc2dde5f2012-08-22 21:09:34 -0400942{
943 struct edma_cc *ecc;
944 int ret;
945
Russell King94cb0e72013-06-27 13:45:16 +0100946 ret = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(32));
947 if (ret)
948 return ret;
949
Matt Porterc2dde5f2012-08-22 21:09:34 -0400950 ecc = devm_kzalloc(&pdev->dev, sizeof(*ecc), GFP_KERNEL);
951 if (!ecc) {
952 dev_err(&pdev->dev, "Can't allocate controller\n");
953 return -ENOMEM;
954 }
955
956 ecc->ctlr = pdev->id;
957 ecc->dummy_slot = edma_alloc_slot(ecc->ctlr, EDMA_SLOT_ANY);
958 if (ecc->dummy_slot < 0) {
959 dev_err(&pdev->dev, "Can't allocate PaRAM dummy slot\n");
960 return -EIO;
961 }
962
963 dma_cap_zero(ecc->dma_slave.cap_mask);
964 dma_cap_set(DMA_SLAVE, ecc->dma_slave.cap_mask);
Peter Ujfalusi232b223d2014-04-14 14:42:00 +0300965 dma_cap_set(DMA_CYCLIC, ecc->dma_slave.cap_mask);
Joel Fernandes8cc3e302014-04-18 21:50:33 -0500966 dma_cap_set(DMA_MEMCPY, ecc->dma_slave.cap_mask);
Matt Porterc2dde5f2012-08-22 21:09:34 -0400967
968 edma_dma_init(ecc, &ecc->dma_slave, &pdev->dev);
969
970 edma_chan_init(ecc, &ecc->dma_slave, ecc->slave_chans);
971
972 ret = dma_async_device_register(&ecc->dma_slave);
973 if (ret)
974 goto err_reg1;
975
976 platform_set_drvdata(pdev, ecc);
977
978 dev_info(&pdev->dev, "TI EDMA DMA engine driver\n");
979
980 return 0;
981
982err_reg1:
983 edma_free_slot(ecc->dummy_slot);
984 return ret;
985}
986
Greg Kroah-Hartman4bf27b82012-12-21 15:09:59 -0800987static int edma_remove(struct platform_device *pdev)
Matt Porterc2dde5f2012-08-22 21:09:34 -0400988{
989 struct device *dev = &pdev->dev;
990 struct edma_cc *ecc = dev_get_drvdata(dev);
991
992 dma_async_device_unregister(&ecc->dma_slave);
993 edma_free_slot(ecc->dummy_slot);
994
995 return 0;
996}
997
998static struct platform_driver edma_driver = {
999 .probe = edma_probe,
Bill Pembertona7d6e3e2012-11-19 13:20:04 -05001000 .remove = edma_remove,
Matt Porterc2dde5f2012-08-22 21:09:34 -04001001 .driver = {
1002 .name = "edma-dma-engine",
1003 .owner = THIS_MODULE,
1004 },
1005};
1006
1007bool edma_filter_fn(struct dma_chan *chan, void *param)
1008{
1009 if (chan->device->dev->driver == &edma_driver.driver) {
1010 struct edma_chan *echan = to_edma_chan(chan);
1011 unsigned ch_req = *(unsigned *)param;
1012 return ch_req == echan->ch_num;
1013 }
1014 return false;
1015}
1016EXPORT_SYMBOL(edma_filter_fn);
1017
1018static struct platform_device *pdev0, *pdev1;
1019
1020static const struct platform_device_info edma_dev_info0 = {
1021 .name = "edma-dma-engine",
1022 .id = 0,
Russell King94cb0e72013-06-27 13:45:16 +01001023 .dma_mask = DMA_BIT_MASK(32),
Matt Porterc2dde5f2012-08-22 21:09:34 -04001024};
1025
1026static const struct platform_device_info edma_dev_info1 = {
1027 .name = "edma-dma-engine",
1028 .id = 1,
Russell King94cb0e72013-06-27 13:45:16 +01001029 .dma_mask = DMA_BIT_MASK(32),
Matt Porterc2dde5f2012-08-22 21:09:34 -04001030};
1031
1032static int edma_init(void)
1033{
1034 int ret = platform_driver_register(&edma_driver);
1035
1036 if (ret == 0) {
1037 pdev0 = platform_device_register_full(&edma_dev_info0);
1038 if (IS_ERR(pdev0)) {
1039 platform_driver_unregister(&edma_driver);
1040 ret = PTR_ERR(pdev0);
1041 goto out;
1042 }
1043 }
1044
1045 if (EDMA_CTLRS == 2) {
1046 pdev1 = platform_device_register_full(&edma_dev_info1);
1047 if (IS_ERR(pdev1)) {
1048 platform_driver_unregister(&edma_driver);
1049 platform_device_unregister(pdev0);
1050 ret = PTR_ERR(pdev1);
1051 }
Matt Porterc2dde5f2012-08-22 21:09:34 -04001052 }
1053
1054out:
1055 return ret;
1056}
1057subsys_initcall(edma_init);
1058
1059static void __exit edma_exit(void)
1060{
1061 platform_device_unregister(pdev0);
1062 if (pdev1)
1063 platform_device_unregister(pdev1);
1064 platform_driver_unregister(&edma_driver);
1065}
1066module_exit(edma_exit);
1067
Josh Boyerd71505b2013-09-04 10:32:50 -04001068MODULE_AUTHOR("Matt Porter <matt.porter@linaro.org>");
Matt Porterc2dde5f2012-08-22 21:09:34 -04001069MODULE_DESCRIPTION("TI EDMA DMA engine driver");
1070MODULE_LICENSE("GPL v2");