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gerrit-public.fairphone.software / kernel / msm-4.9 / 9c096da775af00af83a929769a6ac74bd291b3fe / . / arch / arm / boot / dts / am33xx.dtsi
blob: 795c1467fa50311402fd7fb8d7dabda94081b022 [file] [log] [blame]
AnilKumar Ch5fc0b422012-06-22 15:10:48 +0530[diff] [blame]1/*
2 * Device Tree Source for AM33XX SoC
3 *
4 * Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com/
5 *
6 * This file is licensed under the terms of the GNU General Public License
7 * version 2. This program is licensed "as is" without any warranty of any
8 * kind, whether express or implied.
9 */
10
Florian Vaussarde94233c2013-06-03 16:12:23 +0200[diff] [blame]11#include <dt-bindings/gpio/gpio.h>
Florian Vaussard6a8a6b62013-06-03 16:12:25 +0200[diff] [blame]12#include <dt-bindings/pinctrl/am33xx.h>
Florian Vaussarde94233c2013-06-03 16:12:23 +0200[diff] [blame]13
AnilKumar Ch5fc0b422012-06-22 15:10:48 +0530[diff] [blame]14/ {
15 compatible = "ti,am33xx";
Benoit Cousson4c94ac22012-10-24 10:47:52 +0200[diff] [blame]16 interrupt-parent = <&intc>;
Javier Martinez Canillasf8bf0162016-08-31 12:35:21 +0200[diff] [blame]17 #address-cells = <1>;
18 #size-cells = <1>;
Javier Martinez Canillas355a8fc2016-12-19 11:44:37 -0300[diff] [blame]19 chosen { };
AnilKumar Ch5fc0b422012-06-22 15:10:48 +0530[diff] [blame]20
21 aliases {
Nishanth Menon6a968672013-10-16 15:21:04 -0500[diff] [blame]22 i2c0 = &i2c0;
23 i2c1 = &i2c1;
24 i2c2 = &i2c2;
Vaibhav Hiremathdde3b0d2013-03-28 11:36:05 +0530[diff] [blame]25 serial0 = &uart0;
26 serial1 = &uart1;
27 serial2 = &uart2;
28 serial3 = &uart3;
29 serial4 = &uart4;
30 serial5 = &uart5;
AnilKumar Ch7a57ee82012-11-14 23:38:24 +0530[diff] [blame]31 d_can0 = &dcan0;
32 d_can1 = &dcan1;
Sebastian Andrzej Siewior97238b32013-07-05 14:51:33 +0200[diff] [blame]33 usb0 = &usb0;
34 usb1 = &usb1;
35 phy0 = &usb0_phy;
36 phy1 = &usb1_phy;
Dan Murphy81700562013-10-02 12:58:33 -0500[diff] [blame]37 ethernet0 = &cpsw_emac0;
38 ethernet1 = &cpsw_emac1;
AnilKumar Ch5fc0b422012-06-22 15:10:48 +0530[diff] [blame]39 };
40
41 cpus {
Lorenzo Pieralisi2e0d5132013-04-18 18:35:59 +0100[diff] [blame]42 #address-cells = <1>;
43 #size-cells = <0>;
AnilKumar Ch5fc0b422012-06-22 15:10:48 +0530[diff] [blame]44 cpu@0 {
45 compatible = "arm,cortex-a8";
Lorenzo Pieralisi2e0d5132013-04-18 18:35:59 +0100[diff] [blame]46 device_type = "cpu";
47 reg = <0>;
AnilKumar Chefeedcf2012-08-31 15:07:20 +0530[diff] [blame]48
Dave Gerlach0f416d12016-09-14 16:26:53 -0700[diff] [blame]49 /*
50 * To consider voltage drop between PMIC and SoC,
51 * tolerance value is reduced to 2% from 4% and
52 * voltage value is increased as a precaution.
53 */
54 operating-points = <
55 /* kHz uV */
56 720000 1285000
57 600000 1225000
58 500000 1125000
59 275000 1125000
60 >;
61 voltage-tolerance = <2>; /* 2 percentage */
Nishanth Menon8d766fa2014-01-29 12:19:17 -0600[diff] [blame]62
63 clocks = <&dpll_mpu_ck>;
64 clock-names = "cpu";
65
AnilKumar Chefeedcf2012-08-31 15:07:20 +0530[diff] [blame]66 clock-latency = <300000>; /* From omap-cpufreq driver */
AnilKumar Ch5fc0b422012-06-22 15:10:48 +0530[diff] [blame]67 };
68 };
69
Alexandre Belloni6797cdb2013-08-03 20:00:54 +0200[diff] [blame]70 pmu {
71 compatible = "arm,cortex-a8-pmu";
72 interrupts = <3>;
73 };
74
AnilKumar Ch5fc0b422012-06-22 15:10:48 +0530[diff] [blame]75 /*
Geert Uytterhoeven5c5be9d2014-03-28 11:11:37 +0100[diff] [blame]76 * The soc node represents the soc top level view. It is used for IPs
AnilKumar Ch5fc0b422012-06-22 15:10:48 +0530[diff] [blame]77 * that are not memory mapped in the MPU view or for the MPU itself.
78 */
79 soc {
80 compatible = "ti,omap-infra";
81 mpu {
82 compatible = "ti,omap3-mpu";
83 ti,hwmods = "mpu";
84 };
85 };
86
87 /*
88 * XXX: Use a flat representation of the AM33XX interconnect.
Geert Uytterhoevenb7ab5242014-03-28 11:11:39 +0100[diff] [blame]89 * The real AM33XX interconnect network is quite complex. Since
90 * it will not bring real advantage to represent that in DT
AnilKumar Ch5fc0b422012-06-22 15:10:48 +0530[diff] [blame]91 * for the moment, just use a fake OCP bus entry to represent
92 * the whole bus hierarchy.
93 */
94 ocp {
95 compatible = "simple-bus";
96 #address-cells = <1>;
97 #size-cells = <1>;
98 ranges;
99 ti,hwmods = "l3_main";
100
Tero Kristoe3bc5352015-03-20 13:08:29 +0200[diff] [blame]101 l4_wkup: l4_wkup@44c00000 {
102 compatible = "ti,am3-l4-wkup", "simple-bus";
103 #address-cells = <1>;
104 #size-cells = <1>;
105 ranges = <0 0x44c00000 0x280000>;
Tero Kristoea291c92013-07-18 18:15:35 +0300[diff] [blame]106
Suman Annad129be22015-07-13 12:34:54 -0500[diff] [blame]107 wkup_m3: wkup_m3@100000 {
108 compatible = "ti,am3352-wkup-m3";
109 reg = <0x100000 0x4000>,
110 <0x180000 0x2000>;
111 reg-names = "umem", "dmem";
112 ti,hwmods = "wkup_m3";
113 ti,pm-firmware = "am335x-pm-firmware.elf";
114 };
115
Tero Kristoe3bc5352015-03-20 13:08:29 +0200[diff] [blame]116 prcm: prcm@200000 {
117 compatible = "ti,am3-prcm";
118 reg = <0x200000 0x4000>;
119
120 prcm_clocks: clocks {
121 #address-cells = <1>;
122 #size-cells = <0>;
123 };
124
125 prcm_clockdomains: clockdomains {
126 };
127 };
128
129 scm: scm@210000 {
130 compatible = "ti,am3-scm", "simple-bus";
131 reg = <0x210000 0x2000>;
Tero Kristoea291c92013-07-18 18:15:35 +0300[diff] [blame]132 #address-cells = <1>;
Tero Kristoe3bc5352015-03-20 13:08:29 +0200[diff] [blame]133 #size-cells = <1>;
134 ranges = <0 0x210000 0x2000>;
135
136 am33xx_pinmux: pinmux@800 {
137 compatible = "pinctrl-single";
138 reg = <0x800 0x238>;
139 #address-cells = <1>;
140 #size-cells = <0>;
141 pinctrl-single,register-width = <32>;
142 pinctrl-single,function-mask = <0x7f>;
143 };
144
145 scm_conf: scm_conf@0 {
146 compatible = "syscon";
147 reg = <0x0 0x800>;
148 #address-cells = <1>;
149 #size-cells = <1>;
150
151 scm_clocks: clocks {
152 #address-cells = <1>;
153 #size-cells = <0>;
154 };
155 };
156
Suman Anna99937122015-07-17 16:08:03 -0500[diff] [blame]157 wkup_m3_ipc: wkup_m3_ipc@1324 {
158 compatible = "ti,am3352-wkup-m3-ipc";
159 reg = <0x1324 0x24>;
160 interrupts = <78>;
161 ti,rproc = <&wkup_m3>;
162 mboxes = <&mailbox &mbox_wkupm3>;
163 };
164
Peter Ujfalusib5e50902015-12-17 15:33:36 +0200[diff] [blame]165 edma_xbar: dma-router@f90 {
166 compatible = "ti,am335x-edma-crossbar";
167 reg = <0xf90 0x40>;
168 #dma-cells = <3>;
169 dma-requests = <32>;
170 dma-masters = <&edma>;
171 };
172
Tero Kristoe3bc5352015-03-20 13:08:29 +0200[diff] [blame]173 scm_clockdomains: clockdomains {
174 };
Tero Kristoea291c92013-07-18 18:15:35 +0300[diff] [blame]175 };
Markus Pargmannc9aaf872014-09-29 08:53:18 +0200[diff] [blame]176 };
177
AnilKumar Ch5fc0b422012-06-22 15:10:48 +0530[diff] [blame]178 intc: interrupt-controller@48200000 {
Felipe Balbicab82b72014-09-08 17:54:48 -0700[diff] [blame]179 compatible = "ti,am33xx-intc";
AnilKumar Ch5fc0b422012-06-22 15:10:48 +0530[diff] [blame]180 interrupt-controller;
181 #interrupt-cells = <1>;
AnilKumar Ch5fc0b422012-06-22 15:10:48 +0530[diff] [blame]182 reg = <0x48200000 0x1000>;
183 };
184
Matt Porter505975d2013-09-10 14:24:37 -0500[diff] [blame]185 edma: edma@49000000 {
Peter Ujfalusib5e50902015-12-17 15:33:36 +0200[diff] [blame]186 compatible = "ti,edma3-tpcc";
187 ti,hwmods = "tpcc";
188 reg = <0x49000000 0x10000>;
189 reg-names = "edma3_cc";
Matt Porter505975d2013-09-10 14:24:37 -0500[diff] [blame]190 interrupts = <12 13 14>;
Robert P. J. Daya5206552016-05-24 17:20:28 -0400[diff] [blame]191 interrupt-names = "edma3_ccint", "edma3_mperr",
Peter Ujfalusib5e50902015-12-17 15:33:36 +0200[diff] [blame]192 "edma3_ccerrint";
193 dma-requests = <64>;
194 #dma-cells = <2>;
195
196 ti,tptcs = <&edma_tptc0 7>, <&edma_tptc1 5>,
197 <&edma_tptc2 0>;
198
199 ti,edma-memcpy-channels = <20 21>;
200 };
201
202 edma_tptc0: tptc@49800000 {
203 compatible = "ti,edma3-tptc";
204 ti,hwmods = "tptc0";
205 reg = <0x49800000 0x100000>;
206 interrupts = <112>;
207 interrupt-names = "edma3_tcerrint";
208 };
209
210 edma_tptc1: tptc@49900000 {
211 compatible = "ti,edma3-tptc";
212 ti,hwmods = "tptc1";
213 reg = <0x49900000 0x100000>;
214 interrupts = <113>;
215 interrupt-names = "edma3_tcerrint";
216 };
217
218 edma_tptc2: tptc@49a00000 {
219 compatible = "ti,edma3-tptc";
220 ti,hwmods = "tptc2";
221 reg = <0x49a00000 0x100000>;
222 interrupts = <114>;
223 interrupt-names = "edma3_tcerrint";
Matt Porter505975d2013-09-10 14:24:37 -0500[diff] [blame]224 };
225
AnilKumar Chb918e2c2012-11-21 17:22:17 +0530[diff] [blame]226 gpio0: gpio@44e07000 {
AnilKumar Ch5fc0b422012-06-22 15:10:48 +0530[diff] [blame]227 compatible = "ti,omap4-gpio";
228 ti,hwmods = "gpio1";
229 gpio-controller;
230 #gpio-cells = <2>;
231 interrupt-controller;
Lars Poeschel5eac0eb2013-08-07 13:06:32 +0200[diff] [blame]232 #interrupt-cells = <2>;
Vaibhav Hiremath4462b312012-08-27 17:21:01 +0530[diff] [blame]233 reg = <0x44e07000 0x1000>;
Vaibhav Hiremath4462b312012-08-27 17:21:01 +0530[diff] [blame]234 interrupts = <96>;
AnilKumar Ch5fc0b422012-06-22 15:10:48 +0530[diff] [blame]235 };
236
AnilKumar Chb918e2c2012-11-21 17:22:17 +0530[diff] [blame]237 gpio1: gpio@4804c000 {
AnilKumar Ch5fc0b422012-06-22 15:10:48 +0530[diff] [blame]238 compatible = "ti,omap4-gpio";
239 ti,hwmods = "gpio2";
240 gpio-controller;
241 #gpio-cells = <2>;
242 interrupt-controller;
Lars Poeschel5eac0eb2013-08-07 13:06:32 +0200[diff] [blame]243 #interrupt-cells = <2>;
Vaibhav Hiremath4462b312012-08-27 17:21:01 +0530[diff] [blame]244 reg = <0x4804c000 0x1000>;
Vaibhav Hiremath4462b312012-08-27 17:21:01 +0530[diff] [blame]245 interrupts = <98>;
AnilKumar Ch5fc0b422012-06-22 15:10:48 +0530[diff] [blame]246 };
247
AnilKumar Chb918e2c2012-11-21 17:22:17 +0530[diff] [blame]248 gpio2: gpio@481ac000 {
AnilKumar Ch5fc0b422012-06-22 15:10:48 +0530[diff] [blame]249 compatible = "ti,omap4-gpio";
250 ti,hwmods = "gpio3";
251 gpio-controller;
252 #gpio-cells = <2>;
253 interrupt-controller;
Lars Poeschel5eac0eb2013-08-07 13:06:32 +0200[diff] [blame]254 #interrupt-cells = <2>;
Vaibhav Hiremath4462b312012-08-27 17:21:01 +0530[diff] [blame]255 reg = <0x481ac000 0x1000>;
Vaibhav Hiremath4462b312012-08-27 17:21:01 +0530[diff] [blame]256 interrupts = <32>;
AnilKumar Ch5fc0b422012-06-22 15:10:48 +0530[diff] [blame]257 };
258
AnilKumar Chb918e2c2012-11-21 17:22:17 +0530[diff] [blame]259 gpio3: gpio@481ae000 {
AnilKumar Ch5fc0b422012-06-22 15:10:48 +0530[diff] [blame]260 compatible = "ti,omap4-gpio";
261 ti,hwmods = "gpio4";
262 gpio-controller;
263 #gpio-cells = <2>;
264 interrupt-controller;
Lars Poeschel5eac0eb2013-08-07 13:06:32 +0200[diff] [blame]265 #interrupt-cells = <2>;
Vaibhav Hiremath4462b312012-08-27 17:21:01 +0530[diff] [blame]266 reg = <0x481ae000 0x1000>;
Vaibhav Hiremath4462b312012-08-27 17:21:01 +0530[diff] [blame]267 interrupts = <62>;
AnilKumar Ch5fc0b422012-06-22 15:10:48 +0530[diff] [blame]268 };
269
Vaibhav Hiremathdde3b0d2013-03-28 11:36:05 +0530[diff] [blame]270 uart0: serial@44e09000 {
Sekhar Nori4fcdff92015-07-14 13:32:06 +0530[diff] [blame]271 compatible = "ti,am3352-uart", "ti,omap3-uart";
AnilKumar Ch5fc0b422012-06-22 15:10:48 +0530[diff] [blame]272 ti,hwmods = "uart1";
273 clock-frequency = <48000000>;
Vaibhav Hiremath4462b312012-08-27 17:21:01 +0530[diff] [blame]274 reg = <0x44e09000 0x2000>;
Vaibhav Hiremath4462b312012-08-27 17:21:01 +0530[diff] [blame]275 interrupts = <72>;
Vaibhav Hiremath53d91032012-08-15 16:53:25 +0530[diff] [blame]276 status = "disabled";
Peter Ujfalusib5e50902015-12-17 15:33:36 +0200[diff] [blame]277 dmas = <&edma 26 0>, <&edma 27 0>;
Sebastian Andrzej Siewior13fd3d52014-09-29 20:06:46 +0200[diff] [blame]278 dma-names = "tx", "rx";
AnilKumar Ch5fc0b422012-06-22 15:10:48 +0530[diff] [blame]279 };
280
Vaibhav Hiremathdde3b0d2013-03-28 11:36:05 +0530[diff] [blame]281 uart1: serial@48022000 {
Sekhar Nori4fcdff92015-07-14 13:32:06 +0530[diff] [blame]282 compatible = "ti,am3352-uart", "ti,omap3-uart";
AnilKumar Ch5fc0b422012-06-22 15:10:48 +0530[diff] [blame]283 ti,hwmods = "uart2";
284 clock-frequency = <48000000>;
Vaibhav Hiremath4462b312012-08-27 17:21:01 +0530[diff] [blame]285 reg = <0x48022000 0x2000>;
Vaibhav Hiremath4462b312012-08-27 17:21:01 +0530[diff] [blame]286 interrupts = <73>;
Vaibhav Hiremath53d91032012-08-15 16:53:25 +0530[diff] [blame]287 status = "disabled";
Peter Ujfalusib5e50902015-12-17 15:33:36 +0200[diff] [blame]288 dmas = <&edma 28 0>, <&edma 29 0>;
Sebastian Andrzej Siewior13fd3d52014-09-29 20:06:46 +0200[diff] [blame]289 dma-names = "tx", "rx";
AnilKumar Ch5fc0b422012-06-22 15:10:48 +0530[diff] [blame]290 };
291
Vaibhav Hiremathdde3b0d2013-03-28 11:36:05 +0530[diff] [blame]292 uart2: serial@48024000 {
Sekhar Nori4fcdff92015-07-14 13:32:06 +0530[diff] [blame]293 compatible = "ti,am3352-uart", "ti,omap3-uart";
AnilKumar Ch5fc0b422012-06-22 15:10:48 +0530[diff] [blame]294 ti,hwmods = "uart3";
295 clock-frequency = <48000000>;
Vaibhav Hiremath4462b312012-08-27 17:21:01 +0530[diff] [blame]296 reg = <0x48024000 0x2000>;
Vaibhav Hiremath4462b312012-08-27 17:21:01 +0530[diff] [blame]297 interrupts = <74>;
Vaibhav Hiremath53d91032012-08-15 16:53:25 +0530[diff] [blame]298 status = "disabled";
Peter Ujfalusib5e50902015-12-17 15:33:36 +0200[diff] [blame]299 dmas = <&edma 30 0>, <&edma 31 0>;
Sebastian Andrzej Siewior13fd3d52014-09-29 20:06:46 +0200[diff] [blame]300 dma-names = "tx", "rx";
AnilKumar Ch5fc0b422012-06-22 15:10:48 +0530[diff] [blame]301 };
302
Vaibhav Hiremathdde3b0d2013-03-28 11:36:05 +0530[diff] [blame]303 uart3: serial@481a6000 {
Sekhar Nori4fcdff92015-07-14 13:32:06 +0530[diff] [blame]304 compatible = "ti,am3352-uart", "ti,omap3-uart";
AnilKumar Ch5fc0b422012-06-22 15:10:48 +0530[diff] [blame]305 ti,hwmods = "uart4";
306 clock-frequency = <48000000>;
Vaibhav Hiremath4462b312012-08-27 17:21:01 +0530[diff] [blame]307 reg = <0x481a6000 0x2000>;
Vaibhav Hiremath4462b312012-08-27 17:21:01 +0530[diff] [blame]308 interrupts = <44>;
Vaibhav Hiremath53d91032012-08-15 16:53:25 +0530[diff] [blame]309 status = "disabled";
AnilKumar Ch5fc0b422012-06-22 15:10:48 +0530[diff] [blame]310 };
311
Vaibhav Hiremathdde3b0d2013-03-28 11:36:05 +0530[diff] [blame]312 uart4: serial@481a8000 {
Sekhar Nori4fcdff92015-07-14 13:32:06 +0530[diff] [blame]313 compatible = "ti,am3352-uart", "ti,omap3-uart";
AnilKumar Ch5fc0b422012-06-22 15:10:48 +0530[diff] [blame]314 ti,hwmods = "uart5";
315 clock-frequency = <48000000>;
Vaibhav Hiremath4462b312012-08-27 17:21:01 +0530[diff] [blame]316 reg = <0x481a8000 0x2000>;
Vaibhav Hiremath4462b312012-08-27 17:21:01 +0530[diff] [blame]317 interrupts = <45>;
Vaibhav Hiremath53d91032012-08-15 16:53:25 +0530[diff] [blame]318 status = "disabled";
AnilKumar Ch5fc0b422012-06-22 15:10:48 +0530[diff] [blame]319 };
320
Vaibhav Hiremathdde3b0d2013-03-28 11:36:05 +0530[diff] [blame]321 uart5: serial@481aa000 {
Sekhar Nori4fcdff92015-07-14 13:32:06 +0530[diff] [blame]322 compatible = "ti,am3352-uart", "ti,omap3-uart";
AnilKumar Ch5fc0b422012-06-22 15:10:48 +0530[diff] [blame]323 ti,hwmods = "uart6";
324 clock-frequency = <48000000>;
Vaibhav Hiremath4462b312012-08-27 17:21:01 +0530[diff] [blame]325 reg = <0x481aa000 0x2000>;
Vaibhav Hiremath4462b312012-08-27 17:21:01 +0530[diff] [blame]326 interrupts = <46>;
Vaibhav Hiremath53d91032012-08-15 16:53:25 +0530[diff] [blame]327 status = "disabled";
AnilKumar Ch5fc0b422012-06-22 15:10:48 +0530[diff] [blame]328 };
329
AnilKumar Chb918e2c2012-11-21 17:22:17 +0530[diff] [blame]330 i2c0: i2c@44e0b000 {
AnilKumar Ch5fc0b422012-06-22 15:10:48 +0530[diff] [blame]331 compatible = "ti,omap4-i2c";
332 #address-cells = <1>;
333 #size-cells = <0>;
334 ti,hwmods = "i2c1";
Vaibhav Hiremath4462b312012-08-27 17:21:01 +0530[diff] [blame]335 reg = <0x44e0b000 0x1000>;
Vaibhav Hiremath4462b312012-08-27 17:21:01 +0530[diff] [blame]336 interrupts = <70>;
Vaibhav Hiremath53d91032012-08-15 16:53:25 +0530[diff] [blame]337 status = "disabled";
AnilKumar Ch5fc0b422012-06-22 15:10:48 +0530[diff] [blame]338 };
339
AnilKumar Chb918e2c2012-11-21 17:22:17 +0530[diff] [blame]340 i2c1: i2c@4802a000 {
AnilKumar Ch5fc0b422012-06-22 15:10:48 +0530[diff] [blame]341 compatible = "ti,omap4-i2c";
342 #address-cells = <1>;
343 #size-cells = <0>;
344 ti,hwmods = "i2c2";
Vaibhav Hiremath4462b312012-08-27 17:21:01 +0530[diff] [blame]345 reg = <0x4802a000 0x1000>;
Vaibhav Hiremath4462b312012-08-27 17:21:01 +0530[diff] [blame]346 interrupts = <71>;
Vaibhav Hiremath53d91032012-08-15 16:53:25 +0530[diff] [blame]347 status = "disabled";
AnilKumar Ch5fc0b422012-06-22 15:10:48 +0530[diff] [blame]348 };
349
AnilKumar Chb918e2c2012-11-21 17:22:17 +0530[diff] [blame]350 i2c2: i2c@4819c000 {
AnilKumar Ch5fc0b422012-06-22 15:10:48 +0530[diff] [blame]351 compatible = "ti,omap4-i2c";
352 #address-cells = <1>;
353 #size-cells = <0>;
354 ti,hwmods = "i2c3";
Vaibhav Hiremath4462b312012-08-27 17:21:01 +0530[diff] [blame]355 reg = <0x4819c000 0x1000>;
Vaibhav Hiremath4462b312012-08-27 17:21:01 +0530[diff] [blame]356 interrupts = <30>;
Vaibhav Hiremath53d91032012-08-15 16:53:25 +0530[diff] [blame]357 status = "disabled";
AnilKumar Ch5fc0b422012-06-22 15:10:48 +0530[diff] [blame]358 };
Afzal Mohammed5f789eb2012-07-04 18:00:37 +0530[diff] [blame]359
Matt Porter55b44522013-09-10 14:24:39 -0500[diff] [blame]360 mmc1: mmc@48060000 {
361 compatible = "ti,omap4-hsmmc";
362 ti,hwmods = "mmc1";
363 ti,dual-volt;
364 ti,needs-special-reset;
365 ti,needs-special-hs-handling;
Peter Ujfalusib5e50902015-12-17 15:33:36 +0200[diff] [blame]366 dmas = <&edma_xbar 24 0 0
367 &edma_xbar 25 0 0>;
Matt Porter55b44522013-09-10 14:24:39 -0500[diff] [blame]368 dma-names = "tx", "rx";
369 interrupts = <64>;
370 interrupt-parent = <&intc>;
371 reg = <0x48060000 0x1000>;
372 status = "disabled";
373 };
374
375 mmc2: mmc@481d8000 {
376 compatible = "ti,omap4-hsmmc";
377 ti,hwmods = "mmc2";
378 ti,needs-special-reset;
Peter Ujfalusib5e50902015-12-17 15:33:36 +0200[diff] [blame]379 dmas = <&edma 2 0
380 &edma 3 0>;
Matt Porter55b44522013-09-10 14:24:39 -0500[diff] [blame]381 dma-names = "tx", "rx";
382 interrupts = <28>;
383 interrupt-parent = <&intc>;
384 reg = <0x481d8000 0x1000>;
385 status = "disabled";
386 };
387
388 mmc3: mmc@47810000 {
389 compatible = "ti,omap4-hsmmc";
390 ti,hwmods = "mmc3";
391 ti,needs-special-reset;
392 interrupts = <29>;
393 interrupt-parent = <&intc>;
394 reg = <0x47810000 0x1000>;
395 status = "disabled";
396 };
397
Suman Annad4cbe802013-10-10 16:15:35 -0500[diff] [blame]398 hwspinlock: spinlock@480ca000 {
399 compatible = "ti,omap4-hwspinlock";
400 reg = <0x480ca000 0x1000>;
401 ti,hwmods = "spinlock";
Suman Anna34054212014-01-13 18:26:45 -0600[diff] [blame]402 #hwlock-cells = <1>;
Suman Annad4cbe802013-10-10 16:15:35 -0500[diff] [blame]403 };
404
Afzal Mohammed5f789eb2012-07-04 18:00:37 +0530[diff] [blame]405 wdt2: wdt@44e35000 {
406 compatible = "ti,omap3-wdt";
407 ti,hwmods = "wd_timer2";
Vaibhav Hiremath4462b312012-08-27 17:21:01 +0530[diff] [blame]408 reg = <0x44e35000 0x1000>;
Vaibhav Hiremath4462b312012-08-27 17:21:01 +0530[diff] [blame]409 interrupts = <91>;
Afzal Mohammed5f789eb2012-07-04 18:00:37 +0530[diff] [blame]410 };
AnilKumar Ch059b1852012-09-20 02:49:27 +0530[diff] [blame]411
Roger Quadrose23aabc2014-09-09 16:15:35 +0300[diff] [blame]412 dcan0: can@481cc000 {
413 compatible = "ti,am3352-d_can";
AnilKumar Ch059b1852012-09-20 02:49:27 +0530[diff] [blame]414 ti,hwmods = "d_can0";
Roger Quadrose23aabc2014-09-09 16:15:35 +0300[diff] [blame]415 reg = <0x481cc000 0x2000>;
416 clocks = <&dcan0_fck>;
417 clock-names = "fck";
Tero Kristoe3bc5352015-03-20 13:08:29 +0200[diff] [blame]418 syscon-raminit = <&scm_conf 0x644 0>;
AnilKumar Ch059b1852012-09-20 02:49:27 +0530[diff] [blame]419 interrupts = <52>;
AnilKumar Ch059b1852012-09-20 02:49:27 +0530[diff] [blame]420 status = "disabled";
421 };
422
Roger Quadrose23aabc2014-09-09 16:15:35 +0300[diff] [blame]423 dcan1: can@481d0000 {
424 compatible = "ti,am3352-d_can";
AnilKumar Ch059b1852012-09-20 02:49:27 +0530[diff] [blame]425 ti,hwmods = "d_can1";
Roger Quadrose23aabc2014-09-09 16:15:35 +0300[diff] [blame]426 reg = <0x481d0000 0x2000>;
427 clocks = <&dcan1_fck>;
428 clock-names = "fck";
Tero Kristoe3bc5352015-03-20 13:08:29 +0200[diff] [blame]429 syscon-raminit = <&scm_conf 0x644 1>;
AnilKumar Ch059b1852012-09-20 02:49:27 +0530[diff] [blame]430 interrupts = <55>;
AnilKumar Ch059b1852012-09-20 02:49:27 +0530[diff] [blame]431 status = "disabled";
432 };
Jon Hunterfab8ad02012-10-19 09:59:00 -0500[diff] [blame]433
Suman Anna40242302014-07-11 16:44:36 -0500[diff] [blame]434 mailbox: mailbox@480C8000 {
435 compatible = "ti,omap4-mailbox";
436 reg = <0x480C8000 0x200>;
437 interrupts = <77>;
438 ti,hwmods = "mailbox";
Suman Anna24df0452014-11-03 17:07:35 -0600[diff] [blame]439 #mbox-cells = <1>;
Suman Anna40242302014-07-11 16:44:36 -0500[diff] [blame]440 ti,mbox-num-users = <4>;
441 ti,mbox-num-fifos = <8>;
Suman Annad27704d2014-09-10 14:27:23 -0500[diff] [blame]442 mbox_wkupm3: wkup_m3 {
Dave Gerlach2800971f2015-07-17 16:08:01 -0500[diff] [blame]443 ti,mbox-send-noirq;
Suman Annad27704d2014-09-10 14:27:23 -0500[diff] [blame]444 ti,mbox-tx = <0 0 0>;
445 ti,mbox-rx = <0 0 3>;
446 };
Suman Anna40242302014-07-11 16:44:36 -0500[diff] [blame]447 };
448
Jon Hunterfab8ad02012-10-19 09:59:00 -0500[diff] [blame]449 timer1: timer@44e31000 {
Jon Hunter002e1ec2013-03-19 12:38:18 -0500[diff] [blame]450 compatible = "ti,am335x-timer-1ms";
Jon Hunterfab8ad02012-10-19 09:59:00 -0500[diff] [blame]451 reg = <0x44e31000 0x400>;
452 interrupts = <67>;
453 ti,hwmods = "timer1";
454 ti,timer-alwon;
455 };
456
457 timer2: timer@48040000 {
Jon Hunter002e1ec2013-03-19 12:38:18 -0500[diff] [blame]458 compatible = "ti,am335x-timer";
Jon Hunterfab8ad02012-10-19 09:59:00 -0500[diff] [blame]459 reg = <0x48040000 0x400>;
460 interrupts = <68>;
461 ti,hwmods = "timer2";
462 };
463
464 timer3: timer@48042000 {
Jon Hunter002e1ec2013-03-19 12:38:18 -0500[diff] [blame]465 compatible = "ti,am335x-timer";
Jon Hunterfab8ad02012-10-19 09:59:00 -0500[diff] [blame]466 reg = <0x48042000 0x400>;
467 interrupts = <69>;
468 ti,hwmods = "timer3";
469 };
470
471 timer4: timer@48044000 {
Jon Hunter002e1ec2013-03-19 12:38:18 -0500[diff] [blame]472 compatible = "ti,am335x-timer";
Jon Hunterfab8ad02012-10-19 09:59:00 -0500[diff] [blame]473 reg = <0x48044000 0x400>;
474 interrupts = <92>;
475 ti,hwmods = "timer4";
476 ti,timer-pwm;
477 };
478
479 timer5: timer@48046000 {
Jon Hunter002e1ec2013-03-19 12:38:18 -0500[diff] [blame]480 compatible = "ti,am335x-timer";
Jon Hunterfab8ad02012-10-19 09:59:00 -0500[diff] [blame]481 reg = <0x48046000 0x400>;
482 interrupts = <93>;
483 ti,hwmods = "timer5";
484 ti,timer-pwm;
485 };
486
487 timer6: timer@48048000 {
Jon Hunter002e1ec2013-03-19 12:38:18 -0500[diff] [blame]488 compatible = "ti,am335x-timer";
Jon Hunterfab8ad02012-10-19 09:59:00 -0500[diff] [blame]489 reg = <0x48048000 0x400>;
490 interrupts = <94>;
491 ti,hwmods = "timer6";
492 ti,timer-pwm;
493 };
494
495 timer7: timer@4804a000 {
Jon Hunter002e1ec2013-03-19 12:38:18 -0500[diff] [blame]496 compatible = "ti,am335x-timer";
Jon Hunterfab8ad02012-10-19 09:59:00 -0500[diff] [blame]497 reg = <0x4804a000 0x400>;
498 interrupts = <95>;
499 ti,hwmods = "timer7";
500 ti,timer-pwm;
501 };
Afzal Mohammed0d935c12012-10-30 15:04:01 +0530[diff] [blame]502
Stefan Roeseccd8b9e2014-02-05 13:12:39 +0100[diff] [blame]503 rtc: rtc@44e3e000 {
Johan Hovold6ac7b4a2014-12-10 15:53:25 -0800[diff] [blame]504 compatible = "ti,am3352-rtc", "ti,da830-rtc";
Afzal Mohammed0d935c12012-10-30 15:04:01 +0530[diff] [blame]505 reg = <0x44e3e000 0x1000>;
506 interrupts = <75
507 76>;
508 ti,hwmods = "rtc";
509 };
Philip, Avinash9fd3c742012-10-31 16:21:09 +0530[diff] [blame]510
511 spi0: spi@48030000 {
512 compatible = "ti,omap4-mcspi";
513 #address-cells = <1>;
514 #size-cells = <0>;
515 reg = <0x48030000 0x400>;
Philip Avinash7b3754c2013-02-01 11:07:27 +0530[diff] [blame]516 interrupts = <65>;
Philip, Avinash9fd3c742012-10-31 16:21:09 +0530[diff] [blame]517 ti,spi-num-cs = <2>;
518 ti,hwmods = "spi0";
Peter Ujfalusib5e50902015-12-17 15:33:36 +0200[diff] [blame]519 dmas = <&edma 16 0
520 &edma 17 0
521 &edma 18 0
522 &edma 19 0>;
Matt Porterf5e2f802013-09-10 14:24:38 -0500[diff] [blame]523 dma-names = "tx0", "rx0", "tx1", "rx1";
Philip, Avinash9fd3c742012-10-31 16:21:09 +0530[diff] [blame]524 status = "disabled";
525 };
526
527 spi1: spi@481a0000 {
528 compatible = "ti,omap4-mcspi";
529 #address-cells = <1>;
530 #size-cells = <0>;
531 reg = <0x481a0000 0x400>;
Philip Avinash7b3754c2013-02-01 11:07:27 +0530[diff] [blame]532 interrupts = <125>;
Philip, Avinash9fd3c742012-10-31 16:21:09 +0530[diff] [blame]533 ti,spi-num-cs = <2>;
534 ti,hwmods = "spi1";
Peter Ujfalusib5e50902015-12-17 15:33:36 +0200[diff] [blame]535 dmas = <&edma 42 0
536 &edma 43 0
537 &edma 44 0
538 &edma 45 0>;
Matt Porterf5e2f802013-09-10 14:24:38 -0500[diff] [blame]539 dma-names = "tx0", "rx0", "tx1", "rx1";
Philip, Avinash9fd3c742012-10-31 16:21:09 +0530[diff] [blame]540 status = "disabled";
541 };
Ajay Kumar Gupta35b47fb2012-11-06 19:59:38 +0530[diff] [blame]542
Sebastian Andrzej Siewior97238b32013-07-05 14:51:33 +0200[diff] [blame]543 usb: usb@47400000 {
544 compatible = "ti,am33xx-usb";
545 reg = <0x47400000 0x1000>;
546 ranges;
547 #address-cells = <1>;
548 #size-cells = <1>;
Ajay Kumar Gupta35b47fb2012-11-06 19:59:38 +0530[diff] [blame]549 ti,hwmods = "usb_otg_hs";
Sebastian Andrzej Siewior97238b32013-07-05 14:51:33 +0200[diff] [blame]550 status = "disabled";
551
Mugunthan V N8abcdd62014-03-06 18:01:34 +0530[diff] [blame]552 usb_ctrl_mod: control@44e10620 {
Sebastian Andrzej Siewior97238b32013-07-05 14:51:33 +0200[diff] [blame]553 compatible = "ti,am335x-usb-ctrl-module";
554 reg = <0x44e10620 0x10
555 0x44e10648 0x4>;
556 reg-names = "phy_ctrl", "wakeup";
557 status = "disabled";
558 };
559
Sebastian Andrzej Siewiorc031a7d2013-08-20 18:35:47 +0200[diff] [blame]560 usb0_phy: usb-phy@47401300 {
Sebastian Andrzej Siewior97238b32013-07-05 14:51:33 +0200[diff] [blame]561 compatible = "ti,am335x-usb-phy";
562 reg = <0x47401300 0x100>;
563 reg-names = "phy";
564 status = "disabled";
Markus Pargmanne7243b72013-10-14 14:49:21 +0200[diff] [blame]565 ti,ctrl_mod = <&usb_ctrl_mod>;
Sebastian Andrzej Siewior97238b32013-07-05 14:51:33 +0200[diff] [blame]566 };
567
568 usb0: usb@47401000 {
569 compatible = "ti,musb-am33xx";
Sebastian Andrzej Siewior97238b32013-07-05 14:51:33 +0200[diff] [blame]570 status = "disabled";
Sebastian Andrzej Siewiorc031a7d2013-08-20 18:35:47 +0200[diff] [blame]571 reg = <0x47401400 0x400
572 0x47401000 0x200>;
573 reg-names = "mc", "control";
Sebastian Andrzej Siewior97238b32013-07-05 14:51:33 +0200[diff] [blame]574
Sebastian Andrzej Siewiorc031a7d2013-08-20 18:35:47 +0200[diff] [blame]575 interrupts = <18>;
576 interrupt-names = "mc";
577 dr_mode = "otg";
578 mentor,multipoint = <1>;
579 mentor,num-eps = <16>;
580 mentor,ram-bits = <12>;
581 mentor,power = <500>;
582 phys = <&usb0_phy>;
Sebastian Andrzej Siewior9b3452d2013-06-20 12:13:04 +0200[diff] [blame]583
584 dmas = <&cppi41dma 0 0 &cppi41dma 1 0
585 &cppi41dma 2 0 &cppi41dma 3 0
586 &cppi41dma 4 0 &cppi41dma 5 0
587 &cppi41dma 6 0 &cppi41dma 7 0
588 &cppi41dma 8 0 &cppi41dma 9 0
589 &cppi41dma 10 0 &cppi41dma 11 0
590 &cppi41dma 12 0 &cppi41dma 13 0
591 &cppi41dma 14 0 &cppi41dma 0 1
592 &cppi41dma 1 1 &cppi41dma 2 1
593 &cppi41dma 3 1 &cppi41dma 4 1
594 &cppi41dma 5 1 &cppi41dma 6 1
595 &cppi41dma 7 1 &cppi41dma 8 1
596 &cppi41dma 9 1 &cppi41dma 10 1
597 &cppi41dma 11 1 &cppi41dma 12 1
598 &cppi41dma 13 1 &cppi41dma 14 1>;
599 dma-names =
600 "rx1", "rx2", "rx3", "rx4", "rx5", "rx6", "rx7",
601 "rx8", "rx9", "rx10", "rx11", "rx12", "rx13",
602 "rx14", "rx15",
603 "tx1", "tx2", "tx3", "tx4", "tx5", "tx6", "tx7",
604 "tx8", "tx9", "tx10", "tx11", "tx12", "tx13",
605 "tx14", "tx15";
Sebastian Andrzej Siewior97238b32013-07-05 14:51:33 +0200[diff] [blame]606 };
607
Sebastian Andrzej Siewiorc031a7d2013-08-20 18:35:47 +0200[diff] [blame]608 usb1_phy: usb-phy@47401b00 {
Sebastian Andrzej Siewior97238b32013-07-05 14:51:33 +0200[diff] [blame]609 compatible = "ti,am335x-usb-phy";
610 reg = <0x47401b00 0x100>;
611 reg-names = "phy";
612 status = "disabled";
Markus Pargmanne7243b72013-10-14 14:49:21 +0200[diff] [blame]613 ti,ctrl_mod = <&usb_ctrl_mod>;
Sebastian Andrzej Siewior97238b32013-07-05 14:51:33 +0200[diff] [blame]614 };
615
616 usb1: usb@47401800 {
617 compatible = "ti,musb-am33xx";
Sebastian Andrzej Siewior97238b32013-07-05 14:51:33 +0200[diff] [blame]618 status = "disabled";
Sebastian Andrzej Siewiorc031a7d2013-08-20 18:35:47 +0200[diff] [blame]619 reg = <0x47401c00 0x400
620 0x47401800 0x200>;
621 reg-names = "mc", "control";
622 interrupts = <19>;
623 interrupt-names = "mc";
624 dr_mode = "otg";
625 mentor,multipoint = <1>;
626 mentor,num-eps = <16>;
627 mentor,ram-bits = <12>;
628 mentor,power = <500>;
629 phys = <&usb1_phy>;
Sebastian Andrzej Siewior9b3452d2013-06-20 12:13:04 +0200[diff] [blame]630
631 dmas = <&cppi41dma 15 0 &cppi41dma 16 0
632 &cppi41dma 17 0 &cppi41dma 18 0
633 &cppi41dma 19 0 &cppi41dma 20 0
634 &cppi41dma 21 0 &cppi41dma 22 0
635 &cppi41dma 23 0 &cppi41dma 24 0
636 &cppi41dma 25 0 &cppi41dma 26 0
637 &cppi41dma 27 0 &cppi41dma 28 0
638 &cppi41dma 29 0 &cppi41dma 15 1
639 &cppi41dma 16 1 &cppi41dma 17 1
640 &cppi41dma 18 1 &cppi41dma 19 1
641 &cppi41dma 20 1 &cppi41dma 21 1
642 &cppi41dma 22 1 &cppi41dma 23 1
643 &cppi41dma 24 1 &cppi41dma 25 1
644 &cppi41dma 26 1 &cppi41dma 27 1
645 &cppi41dma 28 1 &cppi41dma 29 1>;
646 dma-names =
647 "rx1", "rx2", "rx3", "rx4", "rx5", "rx6", "rx7",
648 "rx8", "rx9", "rx10", "rx11", "rx12", "rx13",
649 "rx14", "rx15",
650 "tx1", "tx2", "tx3", "tx4", "tx5", "tx6", "tx7",
651 "tx8", "tx9", "tx10", "tx11", "tx12", "tx13",
652 "tx14", "tx15";
Sebastian Andrzej Siewior97238b32013-07-05 14:51:33 +0200[diff] [blame]653 };
Sebastian Andrzej Siewior9b3452d2013-06-20 12:13:04 +0200[diff] [blame]654
Mugunthan V N8abcdd62014-03-06 18:01:34 +0530[diff] [blame]655 cppi41dma: dma-controller@47402000 {
Sebastian Andrzej Siewior9b3452d2013-06-20 12:13:04 +0200[diff] [blame]656 compatible = "ti,am3359-cppi41";
657 reg = <0x47400000 0x1000
658 0x47402000 0x1000
659 0x47403000 0x1000
660 0x47404000 0x4000>;
Sebastian Andrzej Siewior3b6394b2013-08-20 18:35:45 +0200[diff] [blame]661 reg-names = "glue", "controller", "scheduler", "queuemgr";
Sebastian Andrzej Siewior9b3452d2013-06-20 12:13:04 +0200[diff] [blame]662 interrupts = <17>;
663 interrupt-names = "glue";
664 #dma-cells = <2>;
665 #dma-channels = <30>;
666 #dma-requests = <256>;
667 status = "disabled";
668 };
Ajay Kumar Gupta35b47fb2012-11-06 19:59:38 +0530[diff] [blame]669 };
Linus Torvalds6be35c72012-12-12 18:07:07 -0800[diff] [blame]670
Philip Avinash0a7486c2013-06-06 15:52:37 +0200[diff] [blame]671 epwmss0: epwmss@48300000 {
672 compatible = "ti,am33xx-pwmss";
673 reg = <0x48300000 0x10>;
674 ti,hwmods = "epwmss0";
675 #address-cells = <1>;
676 #size-cells = <1>;
677 status = "disabled";
678 ranges = <0x48300100 0x48300100 0x80 /* ECAP */
679 0x48300180 0x48300180 0x80 /* EQEP */
680 0x48300200 0x48300200 0x80>; /* EHRPWM */
681
682 ecap0: ecap@48300100 {
Franklin S Cooper Jr229110c2016-05-03 10:56:51 -0500[diff] [blame]683 compatible = "ti,am3352-ecap",
684 "ti,am33xx-ecap";
Philip Avinash0a7486c2013-06-06 15:52:37 +0200[diff] [blame]685 #pwm-cells = <3>;
686 reg = <0x48300100 0x80>;
Franklin S Cooper Jr229110c2016-05-03 10:56:51 -0500[diff] [blame]687 clocks = <&l4ls_gclk>;
688 clock-names = "fck";
Matt Portere8c85a32014-01-29 15:59:59 -0500[diff] [blame]689 interrupts = <31>;
690 interrupt-names = "ecap0";
Philip Avinash0a7486c2013-06-06 15:52:37 +0200[diff] [blame]691 status = "disabled";
692 };
693
Franklin S Cooper Jrdce2a652016-03-17 20:15:22 -0500[diff] [blame]694 ehrpwm0: pwm@48300200 {
Franklin S Cooper Jr229110c2016-05-03 10:56:51 -0500[diff] [blame]695 compatible = "ti,am3352-ehrpwm",
696 "ti,am33xx-ehrpwm";
Philip Avinash0a7486c2013-06-06 15:52:37 +0200[diff] [blame]697 #pwm-cells = <3>;
698 reg = <0x48300200 0x80>;
Franklin S Cooper Jr229110c2016-05-03 10:56:51 -0500[diff] [blame]699 clocks = <&ehrpwm0_tbclk>, <&l4ls_gclk>;
700 clock-names = "tbclk", "fck";
Philip Avinash0a7486c2013-06-06 15:52:37 +0200[diff] [blame]701 status = "disabled";
702 };
703 };
704
705 epwmss1: epwmss@48302000 {
706 compatible = "ti,am33xx-pwmss";
707 reg = <0x48302000 0x10>;
708 ti,hwmods = "epwmss1";
709 #address-cells = <1>;
710 #size-cells = <1>;
711 status = "disabled";
712 ranges = <0x48302100 0x48302100 0x80 /* ECAP */
713 0x48302180 0x48302180 0x80 /* EQEP */
714 0x48302200 0x48302200 0x80>; /* EHRPWM */
715
716 ecap1: ecap@48302100 {
Franklin S Cooper Jr229110c2016-05-03 10:56:51 -0500[diff] [blame]717 compatible = "ti,am3352-ecap",
718 "ti,am33xx-ecap";
Philip Avinash0a7486c2013-06-06 15:52:37 +0200[diff] [blame]719 #pwm-cells = <3>;
720 reg = <0x48302100 0x80>;
Franklin S Cooper Jr229110c2016-05-03 10:56:51 -0500[diff] [blame]721 clocks = <&l4ls_gclk>;
722 clock-names = "fck";
Matt Portere8c85a32014-01-29 15:59:59 -0500[diff] [blame]723 interrupts = <47>;
724 interrupt-names = "ecap1";
Philip Avinash0a7486c2013-06-06 15:52:37 +0200[diff] [blame]725 status = "disabled";
726 };
727
Franklin S Cooper Jrdce2a652016-03-17 20:15:22 -0500[diff] [blame]728 ehrpwm1: pwm@48302200 {
Franklin S Cooper Jr229110c2016-05-03 10:56:51 -0500[diff] [blame]729 compatible = "ti,am3352-ehrpwm",
730 "ti,am33xx-ehrpwm";
Philip Avinash0a7486c2013-06-06 15:52:37 +0200[diff] [blame]731 #pwm-cells = <3>;
732 reg = <0x48302200 0x80>;
Franklin S Cooper Jr229110c2016-05-03 10:56:51 -0500[diff] [blame]733 clocks = <&ehrpwm1_tbclk>, <&l4ls_gclk>;
734 clock-names = "tbclk", "fck";
Philip Avinash0a7486c2013-06-06 15:52:37 +0200[diff] [blame]735 status = "disabled";
736 };
737 };
738
739 epwmss2: epwmss@48304000 {
740 compatible = "ti,am33xx-pwmss";
741 reg = <0x48304000 0x10>;
742 ti,hwmods = "epwmss2";
743 #address-cells = <1>;
744 #size-cells = <1>;
745 status = "disabled";
746 ranges = <0x48304100 0x48304100 0x80 /* ECAP */
747 0x48304180 0x48304180 0x80 /* EQEP */
748 0x48304200 0x48304200 0x80>; /* EHRPWM */
749
750 ecap2: ecap@48304100 {
Franklin S Cooper Jr229110c2016-05-03 10:56:51 -0500[diff] [blame]751 compatible = "ti,am3352-ecap",
752 "ti,am33xx-ecap";
Philip Avinash0a7486c2013-06-06 15:52:37 +0200[diff] [blame]753 #pwm-cells = <3>;
754 reg = <0x48304100 0x80>;
Franklin S Cooper Jr229110c2016-05-03 10:56:51 -0500[diff] [blame]755 clocks = <&l4ls_gclk>;
756 clock-names = "fck";
Matt Portere8c85a32014-01-29 15:59:59 -0500[diff] [blame]757 interrupts = <61>;
758 interrupt-names = "ecap2";
Philip Avinash0a7486c2013-06-06 15:52:37 +0200[diff] [blame]759 status = "disabled";
760 };
761
Franklin S Cooper Jrdce2a652016-03-17 20:15:22 -0500[diff] [blame]762 ehrpwm2: pwm@48304200 {
Franklin S Cooper Jr229110c2016-05-03 10:56:51 -0500[diff] [blame]763 compatible = "ti,am3352-ehrpwm",
764 "ti,am33xx-ehrpwm";
Philip Avinash0a7486c2013-06-06 15:52:37 +0200[diff] [blame]765 #pwm-cells = <3>;
766 reg = <0x48304200 0x80>;
Franklin S Cooper Jr229110c2016-05-03 10:56:51 -0500[diff] [blame]767 clocks = <&ehrpwm2_tbclk>, <&l4ls_gclk>;
768 clock-names = "tbclk", "fck";
Philip Avinash0a7486c2013-06-06 15:52:37 +0200[diff] [blame]769 status = "disabled";
770 };
771 };
772
Mugunthan V N1a39a652012-11-14 09:08:00 +0000[diff] [blame]773 mac: ethernet@4a100000 {
Mugunthan V N21696f72015-08-12 15:22:55 +0530[diff] [blame]774 compatible = "ti,am335x-cpsw","ti,cpsw";
Mugunthan V N1a39a652012-11-14 09:08:00 +0000[diff] [blame]775 ti,hwmods = "cpgmac0";
George Cherian0987a6e2014-05-02 12:01:59 +0530[diff] [blame]776 clocks = <&cpsw_125mhz_gclk>, <&cpsw_cpts_rft_clk>;
777 clock-names = "fck", "cpts";
Mugunthan V N1a39a652012-11-14 09:08:00 +0000[diff] [blame]778 cpdma_channels = <8>;
779 ale_entries = <1024>;
780 bd_ram_size = <0x2000>;
781 no_bd_ram = <0>;
Mugunthan V N1a39a652012-11-14 09:08:00 +0000[diff] [blame]782 mac_control = <0x20>;
783 slaves = <2>;
Mugunthan V Ne86ac132013-03-11 23:16:35 +0000[diff] [blame]784 active_slave = <0>;
Mugunthan V N1a39a652012-11-14 09:08:00 +0000[diff] [blame]785 cpts_clock_mult = <0x80000000>;
786 cpts_clock_shift = <29>;
787 reg = <0x4a100000 0x800
788 0x4a101200 0x100>;
789 #address-cells = <1>;
790 #size-cells = <1>;
791 interrupt-parent = <&intc>;
792 /*
793 * c0_rx_thresh_pend
794 * c0_rx_pend
795 * c0_tx_pend
796 * c0_misc_pend
797 */
798 interrupts = <40 41 42 43>;
799 ranges;
Tero Kristoe3bc5352015-03-20 13:08:29 +0200[diff] [blame]800 syscon = <&scm_conf>;
Johan Hovold16c75a12014-05-08 10:57:36 +0200[diff] [blame]801 status = "disabled";
Mugunthan V N1a39a652012-11-14 09:08:00 +0000[diff] [blame]802
803 davinci_mdio: mdio@4a101000 {
Grygorii Strashko9efd1a62016-06-24 21:23:55 +0300[diff] [blame]804 compatible = "ti,cpsw-mdio","ti,davinci_mdio";
Mugunthan V N1a39a652012-11-14 09:08:00 +0000[diff] [blame]805 #address-cells = <1>;
806 #size-cells = <0>;
807 ti,hwmods = "davinci_mdio";
808 bus_freq = <1000000>;
809 reg = <0x4a101000 0x100>;
Johan Hovold16c75a12014-05-08 10:57:36 +0200[diff] [blame]810 status = "disabled";
Mugunthan V N1a39a652012-11-14 09:08:00 +0000[diff] [blame]811 };
812
813 cpsw_emac0: slave@4a100200 {
814 /* Filled in by U-Boot */
815 mac-address = [ 00 00 00 00 00 00 ];
816 };
817
818 cpsw_emac1: slave@4a100300 {
819 /* Filled in by U-Boot */
820 mac-address = [ 00 00 00 00 00 00 ];
821 };
Mugunthan V N39ffbd92013-09-21 00:50:41 +0530[diff] [blame]822
823 phy_sel: cpsw-phy-sel@44e10650 {
824 compatible = "ti,am3352-cpsw-phy-sel";
825 reg= <0x44e10650 0x4>;
826 reg-names = "gmii-sel";
827 };
Mugunthan V N1a39a652012-11-14 09:08:00 +0000[diff] [blame]828 };
Vaibhav Bediaf6575c92013-01-29 16:45:07 +0530[diff] [blame]829
830 ocmcram: ocmcram@40300000 {
Rajendra Nayak8b9a2812014-09-10 11:04:03 -0500[diff] [blame]831 compatible = "mmio-sram";
832 reg = <0x40300000 0x10000>; /* 64k */
Vaibhav Bediaf6575c92013-01-29 16:45:07 +0530[diff] [blame]833 };
834
Philip, Avinash15e82462013-05-31 13:19:03 +0530[diff] [blame]835 elm: elm@48080000 {
836 compatible = "ti,am3352-elm";
837 reg = <0x48080000 0x2000>;
838 interrupts = <4>;
839 ti,hwmods = "elm";
840 status = "disabled";
841 };
842
Benoit Parrotd6cfc1e2013-08-08 18:28:14 -0500[diff] [blame]843 lcdc: lcdc@4830e000 {
844 compatible = "ti,am33xx-tilcdc";
845 reg = <0x4830e000 0x1000>;
846 interrupt-parent = <&intc>;
847 interrupts = <36>;
848 ti,hwmods = "lcdc";
849 status = "disabled";
850 };
851
Patil, Rachnaa82279d2013-01-24 03:45:12 +0000[diff] [blame]852 tscadc: tscadc@44e0d000 {
853 compatible = "ti,am3359-tscadc";
854 reg = <0x44e0d000 0x1000>;
855 interrupt-parent = <&intc>;
856 interrupts = <16>;
857 ti,hwmods = "adc_tsc";
858 status = "disabled";
859
860 tsc {
861 compatible = "ti,am3359-tsc";
862 };
863 am335x_adc: adc {
864 #io-channel-cells = <1>;
865 compatible = "ti,am3359-adc";
866 };
Patil, Rachnaa82279d2013-01-24 03:45:12 +0000[diff] [blame]867 };
868
Philip Avinashe45879e2013-05-02 15:14:03 +0530[diff] [blame]869 gpmc: gpmc@50000000 {
870 compatible = "ti,am3352-gpmc";
871 ti,hwmods = "gpmc";
Rajendra Nayakf12ecbe2013-10-15 12:37:50 +0530[diff] [blame]872 ti,no-idle-on-init;
Philip Avinashe45879e2013-05-02 15:14:03 +0530[diff] [blame]873 reg = <0x50000000 0x2000>;
874 interrupts = <100>;
Franklin S Cooper Jra2abf902016-03-10 17:56:38 -0600[diff] [blame]875 dmas = <&edma 52 0>;
Franklin S Cooper Jr201c7e32015-10-15 12:37:27 -0500[diff] [blame]876 dma-names = "rxtx";
Lars Poeschel00dddca2013-05-28 10:24:57 +0200[diff] [blame]877 gpmc,num-cs = <7>;
878 gpmc,num-waitpins = <2>;
Philip Avinashe45879e2013-05-02 15:14:03 +0530[diff] [blame]879 #address-cells = <2>;
880 #size-cells = <1>;
Roger Quadros03752142016-02-23 18:37:21 +0200[diff] [blame]881 interrupt-controller;
882 #interrupt-cells = <2>;
Roger Quadros4eb4dd52016-04-07 13:25:32 +0300[diff] [blame]883 gpio-controller;
884 #gpio-cells = <2>;
Philip Avinashe45879e2013-05-02 15:14:03 +0530[diff] [blame]885 status = "disabled";
886 };
Mark A. Greerf8302e12013-08-23 14:12:35 -0700[diff] [blame]887
888 sham: sham@53100000 {
889 compatible = "ti,omap4-sham";
890 ti,hwmods = "sham";
891 reg = <0x53100000 0x200>;
892 interrupts = <109>;
Peter Ujfalusib5e50902015-12-17 15:33:36 +0200[diff] [blame]893 dmas = <&edma 36 0>;
Mark A. Greerf8302e12013-08-23 14:12:35 -0700[diff] [blame]894 dma-names = "rx";
895 };
Mark A. Greer99919e5e2013-08-23 14:12:36 -0700[diff] [blame]896
897 aes: aes@53500000 {
898 compatible = "ti,omap4-aes";
899 ti,hwmods = "aes";
900 reg = <0x53500000 0xa0>;
Joel Fernandes7af88842013-07-17 19:07:52 -0500[diff] [blame]901 interrupts = <103>;
Peter Ujfalusib5e50902015-12-17 15:33:36 +0200[diff] [blame]902 dmas = <&edma 6 0>,
903 <&edma 5 0>;
Mark A. Greer99919e5e2013-08-23 14:12:36 -0700[diff] [blame]904 dma-names = "tx", "rx";
905 };
Pantelis Antoniou3f72f872013-10-20 20:04:08 +0300[diff] [blame]906
907 mcasp0: mcasp@48038000 {
908 compatible = "ti,am33xx-mcasp-audio";
909 ti,hwmods = "mcasp0";
Jyri Sarha0bee55a2013-10-20 20:04:09 +0300[diff] [blame]910 reg = <0x48038000 0x2000>,
911 <0x46000000 0x400000>;
912 reg-names = "mpu", "dat";
Pantelis Antoniou3f72f872013-10-20 20:04:08 +0300[diff] [blame]913 interrupts = <80>, <81>;
Geert Uytterhoevenae107d02014-04-22 20:40:25 +0200[diff] [blame]914 interrupt-names = "tx", "rx";
Pantelis Antoniou3f72f872013-10-20 20:04:08 +0300[diff] [blame]915 status = "disabled";
Peter Ujfalusib5e50902015-12-17 15:33:36 +0200[diff] [blame]916 dmas = <&edma 8 2>,
917 <&edma 9 2>;
Pantelis Antoniou3f72f872013-10-20 20:04:08 +0300[diff] [blame]918 dma-names = "tx", "rx";
919 };
920
921 mcasp1: mcasp@4803C000 {
922 compatible = "ti,am33xx-mcasp-audio";
923 ti,hwmods = "mcasp1";
Jyri Sarha0bee55a2013-10-20 20:04:09 +0300[diff] [blame]924 reg = <0x4803C000 0x2000>,
925 <0x46400000 0x400000>;
926 reg-names = "mpu", "dat";
Pantelis Antoniou3f72f872013-10-20 20:04:08 +0300[diff] [blame]927 interrupts = <82>, <83>;
Geert Uytterhoevenae107d02014-04-22 20:40:25 +0200[diff] [blame]928 interrupt-names = "tx", "rx";
Pantelis Antoniou3f72f872013-10-20 20:04:08 +0300[diff] [blame]929 status = "disabled";
Peter Ujfalusib5e50902015-12-17 15:33:36 +0200[diff] [blame]930 dmas = <&edma 10 2>,
931 <&edma 11 2>;
Pantelis Antoniou3f72f872013-10-20 20:04:08 +0300[diff] [blame]932 dma-names = "tx", "rx";
933 };
Lokesh Vutlaed845d62013-08-29 18:22:09 +0530[diff] [blame]934
935 rng: rng@48310000 {
936 compatible = "ti,omap4-rng";
937 ti,hwmods = "rng";
938 reg = <0x48310000 0x2000>;
939 interrupts = <111>;
940 };
AnilKumar Ch5fc0b422012-06-22 15:10:48 +0530[diff] [blame]941 };
942};
Tero Kristoea291c92013-07-18 18:15:35 +0300[diff] [blame]943
944/include/ "am33xx-clocks.dtsi"