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gerrit-public.fairphone.software / kernel / msm-4.9 / 9d17601c4e132eee9fe450191f6866fb9fb5a762 / . / drivers / char / drm / radeon_drm.h
blob: 67a8bf04970e3d6b1e7e910d368793267b5983bf [file] [log] [blame]
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]1/* radeon_drm.h -- Public header for the radeon driver -*- linux-c -*-
2 *
3 * Copyright 2000 Precision Insight, Inc., Cedar Park, Texas.
4 * Copyright 2000 VA Linux Systems, Inc., Fremont, California.
5 * Copyright 2002 Tungsten Graphics, Inc., Cedar Park, Texas.
6 * All rights reserved.
7 *
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the "Software"),
10 * to deal in the Software without restriction, including without limitation
11 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
12 * and/or sell copies of the Software, and to permit persons to whom the
13 * Software is furnished to do so, subject to the following conditions:
14 *
15 * The above copyright notice and this permission notice (including the next
16 * paragraph) shall be included in all copies or substantial portions of the
17 * Software.
18 *
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
20 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
21 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
22 * PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
23 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
24 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
25 * DEALINGS IN THE SOFTWARE.
26 *
27 * Authors:
28 * Kevin E. Martin <martin@valinux.com>
29 * Gareth Hughes <gareth@valinux.com>
30 * Keith Whitwell <keith@tungstengraphics.com>
31 */
32
33#ifndef __RADEON_DRM_H__
34#define __RADEON_DRM_H__
35
36/* WARNING: If you change any of these defines, make sure to change the
37 * defines in the X server file (radeon_sarea.h)
38 */
39#ifndef __RADEON_SAREA_DEFINES__
40#define __RADEON_SAREA_DEFINES__
41
42/* Old style state flags, required for sarea interface (1.1 and 1.2
43 * clears) and 1.2 drm_vertex2 ioctl.
44 */
45#define RADEON_UPLOAD_CONTEXT 0x00000001
46#define RADEON_UPLOAD_VERTFMT 0x00000002
47#define RADEON_UPLOAD_LINE 0x00000004
48#define RADEON_UPLOAD_BUMPMAP 0x00000008
49#define RADEON_UPLOAD_MASKS 0x00000010
50#define RADEON_UPLOAD_VIEWPORT 0x00000020
51#define RADEON_UPLOAD_SETUP 0x00000040
52#define RADEON_UPLOAD_TCL 0x00000080
53#define RADEON_UPLOAD_MISC 0x00000100
54#define RADEON_UPLOAD_TEX0 0x00000200
55#define RADEON_UPLOAD_TEX1 0x00000400
56#define RADEON_UPLOAD_TEX2 0x00000800
57#define RADEON_UPLOAD_TEX0IMAGES 0x00001000
58#define RADEON_UPLOAD_TEX1IMAGES 0x00002000
59#define RADEON_UPLOAD_TEX2IMAGES 0x00004000
60#define RADEON_UPLOAD_CLIPRECTS 0x00008000 /* handled client-side */
61#define RADEON_REQUIRE_QUIESCENCE 0x00010000
62#define RADEON_UPLOAD_ZBIAS 0x00020000 /* version 1.2 and newer */
63#define RADEON_UPLOAD_ALL 0x003effff
64#define RADEON_UPLOAD_CONTEXT_ALL 0x003e01ff
65
66
67/* New style per-packet identifiers for use in cmd_buffer ioctl with
68 * the RADEON_EMIT_PACKET command. Comments relate new packets to old
69 * state bits and the packet size:
70 */
71#define RADEON_EMIT_PP_MISC 0 /* context/7 */
72#define RADEON_EMIT_PP_CNTL 1 /* context/3 */
73#define RADEON_EMIT_RB3D_COLORPITCH 2 /* context/1 */
74#define RADEON_EMIT_RE_LINE_PATTERN 3 /* line/2 */
75#define RADEON_EMIT_SE_LINE_WIDTH 4 /* line/1 */
76#define RADEON_EMIT_PP_LUM_MATRIX 5 /* bumpmap/1 */
77#define RADEON_EMIT_PP_ROT_MATRIX_0 6 /* bumpmap/2 */
78#define RADEON_EMIT_RB3D_STENCILREFMASK 7 /* masks/3 */
79#define RADEON_EMIT_SE_VPORT_XSCALE 8 /* viewport/6 */
80#define RADEON_EMIT_SE_CNTL 9 /* setup/2 */
81#define RADEON_EMIT_SE_CNTL_STATUS 10 /* setup/1 */
82#define RADEON_EMIT_RE_MISC 11 /* misc/1 */
83#define RADEON_EMIT_PP_TXFILTER_0 12 /* tex0/6 */
84#define RADEON_EMIT_PP_BORDER_COLOR_0 13 /* tex0/1 */
85#define RADEON_EMIT_PP_TXFILTER_1 14 /* tex1/6 */
86#define RADEON_EMIT_PP_BORDER_COLOR_1 15 /* tex1/1 */
87#define RADEON_EMIT_PP_TXFILTER_2 16 /* tex2/6 */
88#define RADEON_EMIT_PP_BORDER_COLOR_2 17 /* tex2/1 */
89#define RADEON_EMIT_SE_ZBIAS_FACTOR 18 /* zbias/2 */
90#define RADEON_EMIT_SE_TCL_OUTPUT_VTX_FMT 19 /* tcl/11 */
91#define RADEON_EMIT_SE_TCL_MATERIAL_EMMISSIVE_RED 20 /* material/17 */
92#define R200_EMIT_PP_TXCBLEND_0 21 /* tex0/4 */
93#define R200_EMIT_PP_TXCBLEND_1 22 /* tex1/4 */
94#define R200_EMIT_PP_TXCBLEND_2 23 /* tex2/4 */
95#define R200_EMIT_PP_TXCBLEND_3 24 /* tex3/4 */
96#define R200_EMIT_PP_TXCBLEND_4 25 /* tex4/4 */
97#define R200_EMIT_PP_TXCBLEND_5 26 /* tex5/4 */
98#define R200_EMIT_PP_TXCBLEND_6 27 /* /4 */
99#define R200_EMIT_PP_TXCBLEND_7 28 /* /4 */
100#define R200_EMIT_TCL_LIGHT_MODEL_CTL_0 29 /* tcl/7 */
101#define R200_EMIT_TFACTOR_0 30 /* tf/7 */
102#define R200_EMIT_VTX_FMT_0 31 /* vtx/5 */
103#define R200_EMIT_VAP_CTL 32 /* vap/1 */
104#define R200_EMIT_MATRIX_SELECT_0 33 /* msl/5 */
105#define R200_EMIT_TEX_PROC_CTL_2 34 /* tcg/5 */
106#define R200_EMIT_TCL_UCP_VERT_BLEND_CTL 35 /* tcl/1 */
107#define R200_EMIT_PP_TXFILTER_0 36 /* tex0/6 */
108#define R200_EMIT_PP_TXFILTER_1 37 /* tex1/6 */
109#define R200_EMIT_PP_TXFILTER_2 38 /* tex2/6 */
110#define R200_EMIT_PP_TXFILTER_3 39 /* tex3/6 */
111#define R200_EMIT_PP_TXFILTER_4 40 /* tex4/6 */
112#define R200_EMIT_PP_TXFILTER_5 41 /* tex5/6 */
113#define R200_EMIT_PP_TXOFFSET_0 42 /* tex0/1 */
114#define R200_EMIT_PP_TXOFFSET_1 43 /* tex1/1 */
115#define R200_EMIT_PP_TXOFFSET_2 44 /* tex2/1 */
116#define R200_EMIT_PP_TXOFFSET_3 45 /* tex3/1 */
117#define R200_EMIT_PP_TXOFFSET_4 46 /* tex4/1 */
118#define R200_EMIT_PP_TXOFFSET_5 47 /* tex5/1 */
119#define R200_EMIT_VTE_CNTL 48 /* vte/1 */
120#define R200_EMIT_OUTPUT_VTX_COMP_SEL 49 /* vtx/1 */
121#define R200_EMIT_PP_TAM_DEBUG3 50 /* tam/1 */
122#define R200_EMIT_PP_CNTL_X 51 /* cst/1 */
123#define R200_EMIT_RB3D_DEPTHXY_OFFSET 52 /* cst/1 */
124#define R200_EMIT_RE_AUX_SCISSOR_CNTL 53 /* cst/1 */
125#define R200_EMIT_RE_SCISSOR_TL_0 54 /* cst/2 */
126#define R200_EMIT_RE_SCISSOR_TL_1 55 /* cst/2 */
127#define R200_EMIT_RE_SCISSOR_TL_2 56 /* cst/2 */
128#define R200_EMIT_SE_VAP_CNTL_STATUS 57 /* cst/1 */
129#define R200_EMIT_SE_VTX_STATE_CNTL 58 /* cst/1 */
130#define R200_EMIT_RE_POINTSIZE 59 /* cst/1 */
131#define R200_EMIT_TCL_INPUT_VTX_VECTOR_ADDR_0 60 /* cst/4 */
132#define R200_EMIT_PP_CUBIC_FACES_0 61
133#define R200_EMIT_PP_CUBIC_OFFSETS_0 62
134#define R200_EMIT_PP_CUBIC_FACES_1 63
135#define R200_EMIT_PP_CUBIC_OFFSETS_1 64
136#define R200_EMIT_PP_CUBIC_FACES_2 65
137#define R200_EMIT_PP_CUBIC_OFFSETS_2 66
138#define R200_EMIT_PP_CUBIC_FACES_3 67
139#define R200_EMIT_PP_CUBIC_OFFSETS_3 68
140#define R200_EMIT_PP_CUBIC_FACES_4 69
141#define R200_EMIT_PP_CUBIC_OFFSETS_4 70
142#define R200_EMIT_PP_CUBIC_FACES_5 71
143#define R200_EMIT_PP_CUBIC_OFFSETS_5 72
144#define RADEON_EMIT_PP_TEX_SIZE_0 73
145#define RADEON_EMIT_PP_TEX_SIZE_1 74
146#define RADEON_EMIT_PP_TEX_SIZE_2 75
147#define R200_EMIT_RB3D_BLENDCOLOR 76
148#define R200_EMIT_TCL_POINT_SPRITE_CNTL 77
149#define RADEON_EMIT_PP_CUBIC_FACES_0 78
150#define RADEON_EMIT_PP_CUBIC_OFFSETS_T0 79
151#define RADEON_EMIT_PP_CUBIC_FACES_1 80
152#define RADEON_EMIT_PP_CUBIC_OFFSETS_T1 81
153#define RADEON_EMIT_PP_CUBIC_FACES_2 82
154#define RADEON_EMIT_PP_CUBIC_OFFSETS_T2 83
155#define R200_EMIT_PP_TRI_PERF_CNTL 84
Dave Airlie9d176012005-09-11 19:55:53 +1000[diff] [blame^]156#define R200_EMIT_PP_AFS_0 85
157#define R200_EMIT_PP_AFS_1 86
158#define R200_EMIT_ATF_TFACTOR 87
159#define R200_EMIT_PP_TXCTLALL_0 88
160#define R200_EMIT_PP_TXCTLALL_1 89
161#define R200_EMIT_PP_TXCTLALL_2 90
162#define R200_EMIT_PP_TXCTLALL_3 91
163#define R200_EMIT_PP_TXCTLALL_4 92
164#define R200_EMIT_PP_TXCTLALL_5 93
165#define RADEON_MAX_STATE_PACKETS 94
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]166
167/* Commands understood by cmd_buffer ioctl. More can be added but
168 * obviously these can't be removed or changed:
169 */
170#define RADEON_CMD_PACKET 1 /* emit one of the register packets above */
171#define RADEON_CMD_SCALARS 2 /* emit scalar data */
172#define RADEON_CMD_VECTORS 3 /* emit vector data */
173#define RADEON_CMD_DMA_DISCARD 4 /* discard current dma buf */
174#define RADEON_CMD_PACKET3 5 /* emit hw packet */
175#define RADEON_CMD_PACKET3_CLIP 6 /* emit hw packet wrapped in cliprects */
176#define RADEON_CMD_SCALARS2 7 /* r200 stopgap */
177#define RADEON_CMD_WAIT 8 /* emit hw wait commands -- note:
178 * doesn't make the cpu wait, just
179 * the graphics hardware */
180
181
182typedef union {
183 int i;
184 struct {
185 unsigned char cmd_type, pad0, pad1, pad2;
186 } header;
187 struct {
188 unsigned char cmd_type, packet_id, pad0, pad1;
189 } packet;
190 struct {
191 unsigned char cmd_type, offset, stride, count;
192 } scalars;
193 struct {
194 unsigned char cmd_type, offset, stride, count;
195 } vectors;
196 struct {
197 unsigned char cmd_type, buf_idx, pad0, pad1;
198 } dma;
199 struct {
200 unsigned char cmd_type, flags, pad0, pad1;
201 } wait;
202} drm_radeon_cmd_header_t;
203
204#define RADEON_WAIT_2D 0x1
205#define RADEON_WAIT_3D 0x2
206
Dave Airlie414ed532005-08-16 20:43:16 +1000[diff] [blame]207/* Allowed parameters for R300_CMD_PACKET3
208 */
209#define R300_CMD_PACKET3_CLEAR 0
210#define R300_CMD_PACKET3_RAW 1
211
212/* Commands understood by cmd_buffer ioctl for R300.
213 * The interface has not been stabilized, so some of these may be removed
214 * and eventually reordered before stabilization.
215 */
216#define R300_CMD_PACKET0 1
217#define R300_CMD_VPU 2 /* emit vertex program upload */
218#define R300_CMD_PACKET3 3 /* emit a packet3 */
219#define R300_CMD_END3D 4 /* emit sequence ending 3d rendering */
220#define R300_CMD_CP_DELAY 5
221#define R300_CMD_DMA_DISCARD 6
222#define R300_CMD_WAIT 7
223# define R300_WAIT_2D 0x1
224# define R300_WAIT_3D 0x2
225# define R300_WAIT_2D_CLEAN 0x3
226# define R300_WAIT_3D_CLEAN 0x4
227
228typedef union {
229 unsigned int u;
230 struct {
231 unsigned char cmd_type, pad0, pad1, pad2;
232 } header;
233 struct {
234 unsigned char cmd_type, count, reglo, reghi;
235 } packet0;
236 struct {
237 unsigned char cmd_type, count, adrlo, adrhi;
238 } vpu;
239 struct {
240 unsigned char cmd_type, packet, pad0, pad1;
241 } packet3;
242 struct {
243 unsigned char cmd_type, packet;
244 unsigned short count; /* amount of packet2 to emit */
245 } delay;
246 struct {
247 unsigned char cmd_type, buf_idx, pad0, pad1;
248 } dma;
249 struct {
250 unsigned char cmd_type, flags, pad0, pad1;
251 } wait;
252} drm_r300_cmd_header_t;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]253
254#define RADEON_FRONT 0x1
255#define RADEON_BACK 0x2
256#define RADEON_DEPTH 0x4
257#define RADEON_STENCIL 0x8
258#define RADEON_CLEAR_FASTZ 0x80000000
259#define RADEON_USE_HIERZ 0x40000000
260#define RADEON_USE_COMP_ZBUF 0x20000000
261
262/* Primitive types
263 */
264#define RADEON_POINTS 0x1
265#define RADEON_LINES 0x2
266#define RADEON_LINE_STRIP 0x3
267#define RADEON_TRIANGLES 0x4
268#define RADEON_TRIANGLE_FAN 0x5
269#define RADEON_TRIANGLE_STRIP 0x6
270
271/* Vertex/indirect buffer size
272 */
273#define RADEON_BUFFER_SIZE 65536
274
275/* Byte offsets for indirect buffer data
276 */
277#define RADEON_INDEX_PRIM_OFFSET 20
278
279#define RADEON_SCRATCH_REG_OFFSET 32
280
281#define RADEON_NR_SAREA_CLIPRECTS 12
282
283/* There are 2 heaps (local/GART). Each region within a heap is a
284 * minimum of 64k, and there are at most 64 of them per heap.
285 */
286#define RADEON_LOCAL_TEX_HEAP 0
287#define RADEON_GART_TEX_HEAP 1
288#define RADEON_NR_TEX_HEAPS 2
289#define RADEON_NR_TEX_REGIONS 64
290#define RADEON_LOG_TEX_GRANULARITY 16
291
292#define RADEON_MAX_TEXTURE_LEVELS 12
293#define RADEON_MAX_TEXTURE_UNITS 3
294
295#define RADEON_MAX_SURFACES 8
296
297/* Blits have strict offset rules. All blit offset must be aligned on
298 * a 1K-byte boundary.
299 */
300#define RADEON_OFFSET_SHIFT 10
301#define RADEON_OFFSET_ALIGN (1 << RADEON_OFFSET_SHIFT)
302#define RADEON_OFFSET_MASK (RADEON_OFFSET_ALIGN - 1)
303
304#endif /* __RADEON_SAREA_DEFINES__ */
305
306typedef struct {
307 unsigned int red;
308 unsigned int green;
309 unsigned int blue;
310 unsigned int alpha;
311} radeon_color_regs_t;
312
313typedef struct {
314 /* Context state */
315 unsigned int pp_misc; /* 0x1c14 */
316 unsigned int pp_fog_color;
317 unsigned int re_solid_color;
318 unsigned int rb3d_blendcntl;
319 unsigned int rb3d_depthoffset;
320 unsigned int rb3d_depthpitch;
321 unsigned int rb3d_zstencilcntl;
322
323 unsigned int pp_cntl; /* 0x1c38 */
324 unsigned int rb3d_cntl;
325 unsigned int rb3d_coloroffset;
326 unsigned int re_width_height;
327 unsigned int rb3d_colorpitch;
328 unsigned int se_cntl;
329
330 /* Vertex format state */
331 unsigned int se_coord_fmt; /* 0x1c50 */
332
333 /* Line state */
334 unsigned int re_line_pattern; /* 0x1cd0 */
335 unsigned int re_line_state;
336
337 unsigned int se_line_width; /* 0x1db8 */
338
339 /* Bumpmap state */
340 unsigned int pp_lum_matrix; /* 0x1d00 */
341
342 unsigned int pp_rot_matrix_0; /* 0x1d58 */
343 unsigned int pp_rot_matrix_1;
344
345 /* Mask state */
346 unsigned int rb3d_stencilrefmask; /* 0x1d7c */
347 unsigned int rb3d_ropcntl;
348 unsigned int rb3d_planemask;
349
350 /* Viewport state */
351 unsigned int se_vport_xscale; /* 0x1d98 */
352 unsigned int se_vport_xoffset;
353 unsigned int se_vport_yscale;
354 unsigned int se_vport_yoffset;
355 unsigned int se_vport_zscale;
356 unsigned int se_vport_zoffset;
357
358 /* Setup state */
359 unsigned int se_cntl_status; /* 0x2140 */
360
361 /* Misc state */
362 unsigned int re_top_left; /* 0x26c0 */
363 unsigned int re_misc;
364} drm_radeon_context_regs_t;
365
366typedef struct {
367 /* Zbias state */
368 unsigned int se_zbias_factor; /* 0x1dac */
369 unsigned int se_zbias_constant;
370} drm_radeon_context2_regs_t;
371
372
373/* Setup registers for each texture unit
374 */
375typedef struct {
376 unsigned int pp_txfilter;
377 unsigned int pp_txformat;
378 unsigned int pp_txoffset;
379 unsigned int pp_txcblend;
380 unsigned int pp_txablend;
381 unsigned int pp_tfactor;
382 unsigned int pp_border_color;
383} drm_radeon_texture_regs_t;
384
385typedef struct {
386 unsigned int start;
387 unsigned int finish;
388 unsigned int prim:8;
389 unsigned int stateidx:8;
390 unsigned int numverts:16; /* overloaded as offset/64 for elt prims */
391 unsigned int vc_format; /* vertex format */
392} drm_radeon_prim_t;
393
394
395typedef struct {
396 drm_radeon_context_regs_t context;
397 drm_radeon_texture_regs_t tex[RADEON_MAX_TEXTURE_UNITS];
398 drm_radeon_context2_regs_t context2;
399 unsigned int dirty;
400} drm_radeon_state_t;
401
402
403typedef struct {
404 /* The channel for communication of state information to the
405 * kernel on firing a vertex buffer with either of the
406 * obsoleted vertex/index ioctls.
407 */
408 drm_radeon_context_regs_t context_state;
409 drm_radeon_texture_regs_t tex_state[RADEON_MAX_TEXTURE_UNITS];
410 unsigned int dirty;
411 unsigned int vertsize;
412 unsigned int vc_format;
413
414 /* The current cliprects, or a subset thereof.
415 */
416 drm_clip_rect_t boxes[RADEON_NR_SAREA_CLIPRECTS];
417 unsigned int nbox;
418
419 /* Counters for client-side throttling of rendering clients.
420 */
421 unsigned int last_frame;
422 unsigned int last_dispatch;
423 unsigned int last_clear;
424
425 drm_tex_region_t tex_list[RADEON_NR_TEX_HEAPS][RADEON_NR_TEX_REGIONS+1];
426 unsigned int tex_age[RADEON_NR_TEX_HEAPS];
427 int ctx_owner;
428 int pfState; /* number of 3d windows (0,1,2ormore) */
429 int pfCurrentPage; /* which buffer is being displayed? */
430 int crtc2_base; /* CRTC2 frame offset */
431 int tiling_enabled; /* set by drm, read by 2d + 3d clients */
432} drm_radeon_sarea_t;
433
434
435/* WARNING: If you change any of these defines, make sure to change the
436 * defines in the Xserver file (xf86drmRadeon.h)
437 *
438 * KW: actually it's illegal to change any of this (backwards compatibility).
439 */
440
441/* Radeon specific ioctls
442 * The device specific ioctl range is 0x40 to 0x79.
443 */
444#define DRM_RADEON_CP_INIT 0x00
445#define DRM_RADEON_CP_START 0x01
446#define DRM_RADEON_CP_STOP 0x02
447#define DRM_RADEON_CP_RESET 0x03
448#define DRM_RADEON_CP_IDLE 0x04
449#define DRM_RADEON_RESET 0x05
450#define DRM_RADEON_FULLSCREEN 0x06
451#define DRM_RADEON_SWAP 0x07
452#define DRM_RADEON_CLEAR 0x08
453#define DRM_RADEON_VERTEX 0x09
454#define DRM_RADEON_INDICES 0x0A
455#define DRM_RADEON_NOT_USED
456#define DRM_RADEON_STIPPLE 0x0C
457#define DRM_RADEON_INDIRECT 0x0D
458#define DRM_RADEON_TEXTURE 0x0E
459#define DRM_RADEON_VERTEX2 0x0F
460#define DRM_RADEON_CMDBUF 0x10
461#define DRM_RADEON_GETPARAM 0x11
462#define DRM_RADEON_FLIP 0x12
463#define DRM_RADEON_ALLOC 0x13
464#define DRM_RADEON_FREE 0x14
465#define DRM_RADEON_INIT_HEAP 0x15
466#define DRM_RADEON_IRQ_EMIT 0x16
467#define DRM_RADEON_IRQ_WAIT 0x17
468#define DRM_RADEON_CP_RESUME 0x18
469#define DRM_RADEON_SETPARAM 0x19
470#define DRM_RADEON_SURF_ALLOC 0x1a
471#define DRM_RADEON_SURF_FREE 0x1b
472
473#define DRM_IOCTL_RADEON_CP_INIT DRM_IOW( DRM_COMMAND_BASE + DRM_RADEON_CP_INIT, drm_radeon_init_t)
474#define DRM_IOCTL_RADEON_CP_START DRM_IO( DRM_COMMAND_BASE + DRM_RADEON_CP_START)
475#define DRM_IOCTL_RADEON_CP_STOP DRM_IOW( DRM_COMMAND_BASE + DRM_RADEON_CP_STOP, drm_radeon_cp_stop_t)
476#define DRM_IOCTL_RADEON_CP_RESET DRM_IO( DRM_COMMAND_BASE + DRM_RADEON_CP_RESET)
477#define DRM_IOCTL_RADEON_CP_IDLE DRM_IO( DRM_COMMAND_BASE + DRM_RADEON_CP_IDLE)
478#define DRM_IOCTL_RADEON_RESET DRM_IO( DRM_COMMAND_BASE + DRM_RADEON_RESET)
479#define DRM_IOCTL_RADEON_FULLSCREEN DRM_IOW( DRM_COMMAND_BASE + DRM_RADEON_FULLSCREEN, drm_radeon_fullscreen_t)
480#define DRM_IOCTL_RADEON_SWAP DRM_IO( DRM_COMMAND_BASE + DRM_RADEON_SWAP)
481#define DRM_IOCTL_RADEON_CLEAR DRM_IOW( DRM_COMMAND_BASE + DRM_RADEON_CLEAR, drm_radeon_clear_t)
482#define DRM_IOCTL_RADEON_VERTEX DRM_IOW( DRM_COMMAND_BASE + DRM_RADEON_VERTEX, drm_radeon_vertex_t)
483#define DRM_IOCTL_RADEON_INDICES DRM_IOW( DRM_COMMAND_BASE + DRM_RADEON_INDICES, drm_radeon_indices_t)
484#define DRM_IOCTL_RADEON_STIPPLE DRM_IOW( DRM_COMMAND_BASE + DRM_RADEON_STIPPLE, drm_radeon_stipple_t)
485#define DRM_IOCTL_RADEON_INDIRECT DRM_IOWR(DRM_COMMAND_BASE + DRM_RADEON_INDIRECT, drm_radeon_indirect_t)
486#define DRM_IOCTL_RADEON_TEXTURE DRM_IOWR(DRM_COMMAND_BASE + DRM_RADEON_TEXTURE, drm_radeon_texture_t)
487#define DRM_IOCTL_RADEON_VERTEX2 DRM_IOW( DRM_COMMAND_BASE + DRM_RADEON_VERTEX2, drm_radeon_vertex2_t)
488#define DRM_IOCTL_RADEON_CMDBUF DRM_IOW( DRM_COMMAND_BASE + DRM_RADEON_CMDBUF, drm_radeon_cmd_buffer_t)
489#define DRM_IOCTL_RADEON_GETPARAM DRM_IOWR(DRM_COMMAND_BASE + DRM_RADEON_GETPARAM, drm_radeon_getparam_t)
490#define DRM_IOCTL_RADEON_FLIP DRM_IO( DRM_COMMAND_BASE + DRM_RADEON_FLIP)
491#define DRM_IOCTL_RADEON_ALLOC DRM_IOWR(DRM_COMMAND_BASE + DRM_RADEON_ALLOC, drm_radeon_mem_alloc_t)
492#define DRM_IOCTL_RADEON_FREE DRM_IOW( DRM_COMMAND_BASE + DRM_RADEON_FREE, drm_radeon_mem_free_t)
493#define DRM_IOCTL_RADEON_INIT_HEAP DRM_IOW( DRM_COMMAND_BASE + DRM_RADEON_INIT_HEAP, drm_radeon_mem_init_heap_t)
494#define DRM_IOCTL_RADEON_IRQ_EMIT DRM_IOWR(DRM_COMMAND_BASE + DRM_RADEON_IRQ_EMIT, drm_radeon_irq_emit_t)
495#define DRM_IOCTL_RADEON_IRQ_WAIT DRM_IOW( DRM_COMMAND_BASE + DRM_RADEON_IRQ_WAIT, drm_radeon_irq_wait_t)
496#define DRM_IOCTL_RADEON_CP_RESUME DRM_IO( DRM_COMMAND_BASE + DRM_RADEON_CP_RESUME)
497#define DRM_IOCTL_RADEON_SETPARAM DRM_IOW( DRM_COMMAND_BASE + DRM_RADEON_SETPARAM, drm_radeon_setparam_t)
498#define DRM_IOCTL_RADEON_SURF_ALLOC DRM_IOW( DRM_COMMAND_BASE + DRM_RADEON_SURF_ALLOC, drm_radeon_surface_alloc_t)
499#define DRM_IOCTL_RADEON_SURF_FREE DRM_IOW( DRM_COMMAND_BASE + DRM_RADEON_SURF_FREE, drm_radeon_surface_free_t)
500
501typedef struct drm_radeon_init {
502 enum {
503 RADEON_INIT_CP = 0x01,
504 RADEON_CLEANUP_CP = 0x02,
505 RADEON_INIT_R200_CP = 0x03,
506 RADEON_INIT_R300_CP = 0x04
507 } func;
508 unsigned long sarea_priv_offset;
509 int is_pci;
510 int cp_mode;
511 int gart_size;
512 int ring_size;
513 int usec_timeout;
514
515 unsigned int fb_bpp;
516 unsigned int front_offset, front_pitch;
517 unsigned int back_offset, back_pitch;
518 unsigned int depth_bpp;
519 unsigned int depth_offset, depth_pitch;
520
521 unsigned long fb_offset;
522 unsigned long mmio_offset;
523 unsigned long ring_offset;
524 unsigned long ring_rptr_offset;
525 unsigned long buffers_offset;
526 unsigned long gart_textures_offset;
527} drm_radeon_init_t;
528
529typedef struct drm_radeon_cp_stop {
530 int flush;
531 int idle;
532} drm_radeon_cp_stop_t;
533
534typedef struct drm_radeon_fullscreen {
535 enum {
536 RADEON_INIT_FULLSCREEN = 0x01,
537 RADEON_CLEANUP_FULLSCREEN = 0x02
538 } func;
539} drm_radeon_fullscreen_t;
540
541#define CLEAR_X1 0
542#define CLEAR_Y1 1
543#define CLEAR_X2 2
544#define CLEAR_Y2 3
545#define CLEAR_DEPTH 4
546
547typedef union drm_radeon_clear_rect {
548 float f[5];
549 unsigned int ui[5];
550} drm_radeon_clear_rect_t;
551
552typedef struct drm_radeon_clear {
553 unsigned int flags;
554 unsigned int clear_color;
555 unsigned int clear_depth;
556 unsigned int color_mask;
557 unsigned int depth_mask; /* misnamed field: should be stencil */
558 drm_radeon_clear_rect_t __user *depth_boxes;
559} drm_radeon_clear_t;
560
561typedef struct drm_radeon_vertex {
562 int prim;
563 int idx; /* Index of vertex buffer */
564 int count; /* Number of vertices in buffer */
565 int discard; /* Client finished with buffer? */
566} drm_radeon_vertex_t;
567
568typedef struct drm_radeon_indices {
569 int prim;
570 int idx;
571 int start;
572 int end;
573 int discard; /* Client finished with buffer? */
574} drm_radeon_indices_t;
575
576/* v1.2 - obsoletes drm_radeon_vertex and drm_radeon_indices
577 * - allows multiple primitives and state changes in a single ioctl
578 * - supports driver change to emit native primitives
579 */
580typedef struct drm_radeon_vertex2 {
581 int idx; /* Index of vertex buffer */
582 int discard; /* Client finished with buffer? */
583 int nr_states;
584 drm_radeon_state_t __user *state;
585 int nr_prims;
586 drm_radeon_prim_t __user *prim;
587} drm_radeon_vertex2_t;
588
589/* v1.3 - obsoletes drm_radeon_vertex2
590 * - allows arbitarily large cliprect list
591 * - allows updating of tcl packet, vector and scalar state
592 * - allows memory-efficient description of state updates
593 * - allows state to be emitted without a primitive
594 * (for clears, ctx switches)
595 * - allows more than one dma buffer to be referenced per ioctl
596 * - supports tcl driver
597 * - may be extended in future versions with new cmd types, packets
598 */
599typedef struct drm_radeon_cmd_buffer {
600 int bufsz;
601 char __user *buf;
602 int nbox;
603 drm_clip_rect_t __user *boxes;
604} drm_radeon_cmd_buffer_t;
605
606typedef struct drm_radeon_tex_image {
607 unsigned int x, y; /* Blit coordinates */
608 unsigned int width, height;
609 const void __user *data;
610} drm_radeon_tex_image_t;
611
612typedef struct drm_radeon_texture {
613 unsigned int offset;
614 int pitch;
615 int format;
616 int width; /* Texture image coordinates */
617 int height;
618 drm_radeon_tex_image_t __user *image;
619} drm_radeon_texture_t;
620
621typedef struct drm_radeon_stipple {
622 unsigned int __user *mask;
623} drm_radeon_stipple_t;
624
625typedef struct drm_radeon_indirect {
626 int idx;
627 int start;
628 int end;
629 int discard;
630} drm_radeon_indirect_t;
631
632
633/* 1.3: An ioctl to get parameters that aren't available to the 3d
634 * client any other way.
635 */
636#define RADEON_PARAM_GART_BUFFER_OFFSET 1 /* card offset of 1st GART buffer */
637#define RADEON_PARAM_LAST_FRAME 2
638#define RADEON_PARAM_LAST_DISPATCH 3
639#define RADEON_PARAM_LAST_CLEAR 4
640/* Added with DRM version 1.6. */
641#define RADEON_PARAM_IRQ_NR 5
642#define RADEON_PARAM_GART_BASE 6 /* card offset of GART base */
643/* Added with DRM version 1.8. */
644#define RADEON_PARAM_REGISTER_HANDLE 7 /* for drmMap() */
645#define RADEON_PARAM_STATUS_HANDLE 8
646#define RADEON_PARAM_SAREA_HANDLE 9
647#define RADEON_PARAM_GART_TEX_HANDLE 10
648#define RADEON_PARAM_SCRATCH_OFFSET 11
649
650typedef struct drm_radeon_getparam {
651 int param;
652 void __user *value;
653} drm_radeon_getparam_t;
654
655/* 1.6: Set up a memory manager for regions of shared memory:
656 */
657#define RADEON_MEM_REGION_GART 1
658#define RADEON_MEM_REGION_FB 2
659
660typedef struct drm_radeon_mem_alloc {
661 int region;
662 int alignment;
663 int size;
664 int __user *region_offset; /* offset from start of fb or GART */
665} drm_radeon_mem_alloc_t;
666
667typedef struct drm_radeon_mem_free {
668 int region;
669 int region_offset;
670} drm_radeon_mem_free_t;
671
672typedef struct drm_radeon_mem_init_heap {
673 int region;
674 int size;
675 int start;
676} drm_radeon_mem_init_heap_t;
677
678
679/* 1.6: Userspace can request & wait on irq's:
680 */
681typedef struct drm_radeon_irq_emit {
682 int __user *irq_seq;
683} drm_radeon_irq_emit_t;
684
685typedef struct drm_radeon_irq_wait {
686 int irq_seq;
687} drm_radeon_irq_wait_t;
688
689
690/* 1.10: Clients tell the DRM where they think the framebuffer is located in
691 * the card's address space, via a new generic ioctl to set parameters
692 */
693
694typedef struct drm_radeon_setparam {
695 unsigned int param;
696 int64_t value;
697} drm_radeon_setparam_t;
698
699#define RADEON_SETPARAM_FB_LOCATION 1 /* determined framebuffer location */
700#define RADEON_SETPARAM_SWITCH_TILING 2 /* enable/disable color tiling */
701
702/* 1.14: Clients can allocate/free a surface
703 */
704typedef struct drm_radeon_surface_alloc {
705 unsigned int address;
706 unsigned int size;
707 unsigned int flags;
708} drm_radeon_surface_alloc_t;
709
710typedef struct drm_radeon_surface_free {
711 unsigned int address;
712} drm_radeon_surface_free_t;
713
714#endif