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Tony Lindgrenb824efa2006-04-02 17:46:20 +01001/*
Paul Walmsley96609ef2009-01-28 12:27:34 -07002 * linux/arch/arm/mach-omap2/sdrc2xxx.c
Tony Lindgrenb824efa2006-04-02 17:46:20 +01003 *
Paul Walmsley96609ef2009-01-28 12:27:34 -07004 * SDRAM timing related functions for OMAP2xxx
Tony Lindgrenb824efa2006-04-02 17:46:20 +01005 *
Paul Walmsleyf2ab9972009-01-28 12:27:37 -07006 * Copyright (C) 2005, 2008 Texas Instruments Inc.
7 * Copyright (C) 2005, 2008 Nokia Corporation
Tony Lindgrenb824efa2006-04-02 17:46:20 +01008 *
Tony Lindgrenb824efa2006-04-02 17:46:20 +01009 * Tony Lindgren <tony@atomide.com>
Paul Walmsleyf2ab9972009-01-28 12:27:37 -070010 * Paul Walmsley
11 * Richard Woodruff <r-woodruff2@ti.com>
Tony Lindgrenb824efa2006-04-02 17:46:20 +010012 *
13 * This program is free software; you can redistribute it and/or modify
14 * it under the terms of the GNU General Public License version 2 as
15 * published by the Free Software Foundation.
16 */
17
Tony Lindgrenb824efa2006-04-02 17:46:20 +010018#include <linux/module.h>
19#include <linux/kernel.h>
20#include <linux/device.h>
21#include <linux/list.h>
22#include <linux/errno.h>
23#include <linux/delay.h>
24#include <linux/clk.h>
Russell Kingfced80c2008-09-06 12:10:45 +010025#include <linux/io.h>
Tony Lindgrenb824efa2006-04-02 17:46:20 +010026
Tony Lindgrendbc04162012-08-31 10:59:07 -070027#include "soc.h"
Tony Lindgrenee0839c2012-02-24 10:34:35 -080028#include "iomap.h"
29#include "common.h"
Paul Walmsley139563a2012-10-21 01:01:10 -060030#include "prm2xxx.h"
Russell Kingc0bf3132009-02-19 13:29:22 +000031#include "clock.h"
Paul Walmsley44595982008-03-18 10:04:51 +020032#include "sdrc.h"
Tony Lindgrenbf027ca2012-10-29 13:54:06 -070033#include "sram.h"
Paul Walmsley44595982008-03-18 10:04:51 +020034
Paul Walmsleyf8de9b22009-01-28 12:27:31 -070035/* Memory timing, DLL mode flags */
36#define M_DDR 1
37#define M_LOCK_CTRL (1 << 2)
38#define M_UNLOCK 0
39#define M_LOCK 1
40
41
Tony Lindgrenb824efa2006-04-02 17:46:20 +010042static struct memory_timings mem_timings;
Paul Walmsley44595982008-03-18 10:04:51 +020043static u32 curr_perf_level = CORE_CLK_SRC_DPLL_X2;
Tony Lindgrenb824efa2006-04-02 17:46:20 +010044
Paul Walmsleyf2ab9972009-01-28 12:27:37 -070045static u32 omap2xxx_sdrc_get_slow_dll_ctrl(void)
Tony Lindgrenb824efa2006-04-02 17:46:20 +010046{
47 return mem_timings.slow_dll_ctrl;
48}
49
Paul Walmsleyf2ab9972009-01-28 12:27:37 -070050static u32 omap2xxx_sdrc_get_fast_dll_ctrl(void)
Tony Lindgrenb824efa2006-04-02 17:46:20 +010051{
52 return mem_timings.fast_dll_ctrl;
53}
54
Paul Walmsleyf2ab9972009-01-28 12:27:37 -070055static u32 omap2xxx_sdrc_get_type(void)
Tony Lindgrenb824efa2006-04-02 17:46:20 +010056{
57 return mem_timings.m_type;
58}
59
Paul Walmsley6b8858a2008-03-18 10:35:15 +020060/*
61 * Check the DLL lock state, and return tue if running in unlock mode.
62 * This is needed to compensate for the shifted DLL value in unlock mode.
63 */
Paul Walmsleyf2ab9972009-01-28 12:27:37 -070064u32 omap2xxx_sdrc_dll_is_unlocked(void)
Paul Walmsley6b8858a2008-03-18 10:35:15 +020065{
66 /* dlla and dllb are a set */
67 u32 dll_state = sdrc_read_reg(SDRC_DLLA_CTRL);
68
69 if ((dll_state & (1 << 2)) == (1 << 2))
70 return 1;
71 else
72 return 0;
73}
74
75/*
76 * 'level' is the value to store to CM_CLKSEL2_PLL.CORE_CLK_SRC.
77 * Practical values are CORE_CLK_SRC_DPLL (for CORE_CLK = DPLL_CLK) or
78 * CORE_CLK_SRC_DPLL_X2 (for CORE_CLK = * DPLL_CLK * 2)
Paul Walmsleyf2ab9972009-01-28 12:27:37 -070079 *
80 * Used by the clock framework during CORE DPLL changes
Paul Walmsley6b8858a2008-03-18 10:35:15 +020081 */
Paul Walmsleyf2ab9972009-01-28 12:27:37 -070082u32 omap2xxx_sdrc_reprogram(u32 level, u32 force)
Paul Walmsley6b8858a2008-03-18 10:35:15 +020083{
84 u32 dll_ctrl, m_type;
85 u32 prev = curr_perf_level;
86 unsigned long flags;
87
88 if ((curr_perf_level == level) && !force)
89 return prev;
90
Paul Walmsley96609ef2009-01-28 12:27:34 -070091 if (level == CORE_CLK_SRC_DPLL)
Paul Walmsleyf2ab9972009-01-28 12:27:37 -070092 dll_ctrl = omap2xxx_sdrc_get_slow_dll_ctrl();
Paul Walmsley96609ef2009-01-28 12:27:34 -070093 else if (level == CORE_CLK_SRC_DPLL_X2)
Paul Walmsleyf2ab9972009-01-28 12:27:37 -070094 dll_ctrl = omap2xxx_sdrc_get_fast_dll_ctrl();
Paul Walmsley96609ef2009-01-28 12:27:34 -070095 else
Paul Walmsley6b8858a2008-03-18 10:35:15 +020096 return prev;
Paul Walmsley6b8858a2008-03-18 10:35:15 +020097
Paul Walmsleyf2ab9972009-01-28 12:27:37 -070098 m_type = omap2xxx_sdrc_get_type();
Paul Walmsley6b8858a2008-03-18 10:35:15 +020099
100 local_irq_save(flags);
Paul Walmsleyc4d7e582010-12-21 21:05:14 -0700101 /*
102 * XXX These calls should be abstracted out through a
103 * prm2xxx.c function
104 */
Tony Lindgren8e3bd352009-05-25 11:26:42 -0700105 if (cpu_is_omap2420())
Victor Kamenskyedfaf052014-04-15 20:37:46 +0300106 writel_relaxed(0xffff, OMAP2420_PRCM_VOLTSETUP);
Tony Lindgren8e3bd352009-05-25 11:26:42 -0700107 else
Victor Kamenskyedfaf052014-04-15 20:37:46 +0300108 writel_relaxed(0xffff, OMAP2430_PRCM_VOLTSETUP);
Paul Walmsley6b8858a2008-03-18 10:35:15 +0200109 omap2_sram_reprogram_sdrc(level, dll_ctrl, m_type);
110 curr_perf_level = level;
111 local_irq_restore(flags);
112
113 return prev;
114}
115
Paul Walmsleyf2ab9972009-01-28 12:27:37 -0700116/* Used by the clock framework during CORE DPLL changes */
117void omap2xxx_sdrc_init_params(u32 force_lock_to_unlock_mode)
Tony Lindgrenb824efa2006-04-02 17:46:20 +0100118{
119 unsigned long dll_cnt;
120 u32 fast_dll = 0;
121
Paul Walmsley96609ef2009-01-28 12:27:34 -0700122 /* DDR = 1, SDR = 0 */
123 mem_timings.m_type = !((sdrc_read_reg(SDRC_MR_0) & 0x3) == 0x1);
Tony Lindgrenb824efa2006-04-02 17:46:20 +0100124
125 /* 2422 es2.05 and beyond has a single SIP DDR instead of 2 like others.
126 * In the case of 2422, its ok to use CS1 instead of CS0.
127 */
128 if (cpu_is_omap2422())
129 mem_timings.base_cs = 1;
130 else
131 mem_timings.base_cs = 0;
132
133 if (mem_timings.m_type != M_DDR)
134 return;
135
136 /* With DDR we need to determine the low frequency DLL value */
137 if (((mem_timings.fast_dll_ctrl & (1 << 2)) == M_LOCK_CTRL))
138 mem_timings.dll_mode = M_UNLOCK;
139 else
140 mem_timings.dll_mode = M_LOCK;
141
142 if (mem_timings.base_cs == 0) {
Paul Walmsley44595982008-03-18 10:04:51 +0200143 fast_dll = sdrc_read_reg(SDRC_DLLA_CTRL);
144 dll_cnt = sdrc_read_reg(SDRC_DLLA_STATUS) & 0xff00;
Tony Lindgrenb824efa2006-04-02 17:46:20 +0100145 } else {
Paul Walmsley44595982008-03-18 10:04:51 +0200146 fast_dll = sdrc_read_reg(SDRC_DLLB_CTRL);
147 dll_cnt = sdrc_read_reg(SDRC_DLLB_STATUS) & 0xff00;
Tony Lindgrenb824efa2006-04-02 17:46:20 +0100148 }
149 if (force_lock_to_unlock_mode) {
150 fast_dll &= ~0xff00;
151 fast_dll |= dll_cnt; /* Current lock mode */
152 }
153 /* set fast timings with DLL filter disabled */
154 mem_timings.fast_dll_ctrl = (fast_dll | (3 << 8));
155
156 /* No disruptions, DDR will be offline & C-ABI not followed */
157 omap2_sram_ddr_init(&mem_timings.slow_dll_ctrl,
158 mem_timings.fast_dll_ctrl,
159 mem_timings.base_cs,
160 force_lock_to_unlock_mode);
161 mem_timings.slow_dll_ctrl &= 0xff00; /* Keep lock value */
162
163 /* Turn status into unlock ctrl */
164 mem_timings.slow_dll_ctrl |=
165 ((mem_timings.fast_dll_ctrl & 0xF) | (1 << 2));
166
167 /* 90 degree phase for anything below 133Mhz + disable DLL filter */
168 mem_timings.slow_dll_ctrl |= ((1 << 1) | (3 << 8));
169}