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Ben Hutchingsafd4aea2009-11-29 15:15:25 +00001/****************************************************************************
Ben Hutchingsf7a6d2c2013-08-29 23:32:48 +01002 * Driver for Solarflare network controllers and boards
Ben Hutchingsafd4aea2009-11-29 15:15:25 +00003 * Copyright 2005-2006 Fen Systems Ltd.
Ben Hutchingsf7a6d2c2013-08-29 23:32:48 +01004 * Copyright 2006-2013 Solarflare Communications Inc.
Ben Hutchingsafd4aea2009-11-29 15:15:25 +00005 *
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License version 2 as published
8 * by the Free Software Foundation, incorporated herein by reference.
9 */
10
11#include <linux/bitops.h>
12#include <linux/delay.h>
13#include <linux/pci.h>
14#include <linux/module.h>
Tejun Heo5a0e3ad2010-03-24 17:04:11 +090015#include <linux/slab.h>
Ben Hutchingsd614cfb2010-04-28 09:29:02 +000016#include <linux/random.h>
Ben Hutchingsafd4aea2009-11-29 15:15:25 +000017#include "net_driver.h"
18#include "bitfield.h"
19#include "efx.h"
20#include "nic.h"
Ben Hutchings8b8a95a2012-09-18 01:57:07 +010021#include "farch_regs.h"
Ben Hutchingsafd4aea2009-11-29 15:15:25 +000022#include "io.h"
23#include "phy.h"
24#include "workarounds.h"
25#include "mcdi.h"
26#include "mcdi_pcol.h"
Ben Hutchingsd4f2cec2012-07-04 03:58:33 +010027#include "selftest.h"
Ben Hutchingsafd4aea2009-11-29 15:15:25 +000028
29/* Hardware control for SFC9000 family including SFL9021 (aka Siena). */
30
31static void siena_init_wol(struct efx_nic *efx);
32
33
34static void siena_push_irq_moderation(struct efx_channel *channel)
35{
36 efx_dword_t timer_cmd;
37
38 if (channel->irq_moderation)
39 EFX_POPULATE_DWORD_2(timer_cmd,
40 FRF_CZ_TC_TIMER_MODE,
41 FFE_CZ_TIMER_MODE_INT_HLDOFF,
42 FRF_CZ_TC_TIMER_VAL,
43 channel->irq_moderation - 1);
44 else
45 EFX_POPULATE_DWORD_2(timer_cmd,
46 FRF_CZ_TC_TIMER_MODE,
47 FFE_CZ_TIMER_MODE_DIS,
48 FRF_CZ_TC_TIMER_VAL, 0);
49 efx_writed_page_locked(channel->efx, &timer_cmd, FR_BZ_TIMER_COMMAND_P0,
50 channel->channel);
51}
52
Ben Hutchingsd5e8cc62012-09-06 16:52:31 +010053void siena_prepare_flush(struct efx_nic *efx)
54{
55 if (efx->fc_disable++ == 0)
56 efx_mcdi_set_mac(efx);
57}
58
59void siena_finish_flush(struct efx_nic *efx)
60{
61 if (--efx->fc_disable == 0)
62 efx_mcdi_set_mac(efx);
63}
64
Ben Hutchings86094f72013-08-21 19:51:04 +010065static const struct efx_farch_register_test siena_register_tests[] = {
Ben Hutchingsafd4aea2009-11-29 15:15:25 +000066 { FR_AZ_ADR_REGION,
Steve Hodgson4cddca52010-02-03 09:31:40 +000067 EFX_OWORD32(0x0003FFFF, 0x0003FFFF, 0x0003FFFF, 0x0003FFFF) },
Ben Hutchingsafd4aea2009-11-29 15:15:25 +000068 { FR_CZ_USR_EV_CFG,
69 EFX_OWORD32(0x000103FF, 0x00000000, 0x00000000, 0x00000000) },
70 { FR_AZ_RX_CFG,
71 EFX_OWORD32(0xFFFFFFFE, 0xFFFFFFFF, 0x0003FFFF, 0x00000000) },
72 { FR_AZ_TX_CFG,
73 EFX_OWORD32(0x7FFF0037, 0xFFFF8000, 0xFFFFFFFF, 0x03FFFFFF) },
74 { FR_AZ_TX_RESERVED,
75 EFX_OWORD32(0xFFFEFE80, 0x1FFFFFFF, 0x020000FE, 0x007FFFFF) },
76 { FR_AZ_SRM_TX_DC_CFG,
77 EFX_OWORD32(0x001FFFFF, 0x00000000, 0x00000000, 0x00000000) },
78 { FR_AZ_RX_DC_CFG,
79 EFX_OWORD32(0x00000003, 0x00000000, 0x00000000, 0x00000000) },
80 { FR_AZ_RX_DC_PF_WM,
81 EFX_OWORD32(0x000003FF, 0x00000000, 0x00000000, 0x00000000) },
82 { FR_BZ_DP_CTRL,
83 EFX_OWORD32(0x00000FFF, 0x00000000, 0x00000000, 0x00000000) },
84 { FR_BZ_RX_RSS_TKEY,
85 EFX_OWORD32(0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF) },
86 { FR_CZ_RX_RSS_IPV6_REG1,
87 EFX_OWORD32(0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF) },
88 { FR_CZ_RX_RSS_IPV6_REG2,
89 EFX_OWORD32(0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF) },
90 { FR_CZ_RX_RSS_IPV6_REG3,
91 EFX_OWORD32(0xFFFFFFFF, 0xFFFFFFFF, 0x00000007, 0x00000000) },
92};
93
Ben Hutchingsd4f2cec2012-07-04 03:58:33 +010094static int siena_test_chip(struct efx_nic *efx, struct efx_self_tests *tests)
Ben Hutchingsafd4aea2009-11-29 15:15:25 +000095{
Ben Hutchingsef492f12012-12-01 01:55:27 +000096 enum reset_type reset_method = RESET_TYPE_ALL;
Ben Hutchingsd4f2cec2012-07-04 03:58:33 +010097 int rc, rc2;
98
99 efx_reset_down(efx, reset_method);
100
101 /* Reset the chip immediately so that it is completely
102 * quiescent regardless of what any VF driver does.
103 */
Ben Hutchings6bff8612012-09-18 02:33:52 +0100104 rc = efx_mcdi_reset(efx, reset_method);
Ben Hutchingsd4f2cec2012-07-04 03:58:33 +0100105 if (rc)
106 goto out;
107
108 tests->registers =
Ben Hutchings86094f72013-08-21 19:51:04 +0100109 efx_farch_test_registers(efx, siena_register_tests,
110 ARRAY_SIZE(siena_register_tests))
Ben Hutchingsd4f2cec2012-07-04 03:58:33 +0100111 ? -1 : 1;
112
Ben Hutchings6bff8612012-09-18 02:33:52 +0100113 rc = efx_mcdi_reset(efx, reset_method);
Ben Hutchingsd4f2cec2012-07-04 03:58:33 +0100114out:
115 rc2 = efx_reset_up(efx, reset_method, rc == 0);
116 return rc ? rc : rc2;
Ben Hutchingsafd4aea2009-11-29 15:15:25 +0000117}
118
119/**************************************************************************
120 *
Daniel Pieczko9ec06592013-11-21 17:11:25 +0000121 * PTP
122 *
123 **************************************************************************
124 */
125
126static void siena_ptp_write_host_time(struct efx_nic *efx, u32 host_time)
127{
128 _efx_writed(efx, cpu_to_le32(host_time),
129 FR_CZ_MC_TREG_SMEM + MC_SMEM_P0_PTP_TIME_OFST);
130}
131
132static int siena_ptp_set_ts_config(struct efx_nic *efx,
133 struct hwtstamp_config *init)
134{
135 int rc;
136
137 switch (init->rx_filter) {
138 case HWTSTAMP_FILTER_NONE:
139 /* if TX timestamping is still requested then leave PTP on */
140 return efx_ptp_change_mode(efx,
141 init->tx_type != HWTSTAMP_TX_OFF,
142 efx_ptp_get_mode(efx));
143 case HWTSTAMP_FILTER_PTP_V1_L4_EVENT:
144 case HWTSTAMP_FILTER_PTP_V1_L4_SYNC:
145 case HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ:
146 init->rx_filter = HWTSTAMP_FILTER_PTP_V1_L4_EVENT;
147 return efx_ptp_change_mode(efx, true, MC_CMD_PTP_MODE_V1);
148 case HWTSTAMP_FILTER_PTP_V2_L4_EVENT:
149 case HWTSTAMP_FILTER_PTP_V2_L4_SYNC:
150 case HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ:
151 init->rx_filter = HWTSTAMP_FILTER_PTP_V2_L4_EVENT;
152 rc = efx_ptp_change_mode(efx, true,
153 MC_CMD_PTP_MODE_V2_ENHANCED);
154 /* bug 33070 - old versions of the firmware do not support the
155 * improved UUID filtering option. Similarly old versions of the
156 * application do not expect it to be enabled. If the firmware
157 * does not accept the enhanced mode, fall back to the standard
158 * PTP v2 UUID filtering. */
159 if (rc != 0)
160 rc = efx_ptp_change_mode(efx, true, MC_CMD_PTP_MODE_V2);
161 return rc;
162 default:
163 return -ERANGE;
164 }
165}
166
167/**************************************************************************
168 *
Ben Hutchingsafd4aea2009-11-29 15:15:25 +0000169 * Device reset
170 *
171 **************************************************************************
172 */
173
Ben Hutchings0e2a9c72011-06-24 20:50:07 +0100174static int siena_map_reset_flags(u32 *flags)
175{
176 enum {
177 SIENA_RESET_PORT = (ETH_RESET_DMA | ETH_RESET_FILTER |
178 ETH_RESET_OFFLOAD | ETH_RESET_MAC |
179 ETH_RESET_PHY),
180 SIENA_RESET_MC = (SIENA_RESET_PORT |
181 ETH_RESET_MGMT << ETH_RESET_SHARED_SHIFT),
182 };
183
184 if ((*flags & SIENA_RESET_MC) == SIENA_RESET_MC) {
185 *flags &= ~SIENA_RESET_MC;
186 return RESET_TYPE_WORLD;
187 }
188
189 if ((*flags & SIENA_RESET_PORT) == SIENA_RESET_PORT) {
190 *flags &= ~SIENA_RESET_PORT;
191 return RESET_TYPE_ALL;
192 }
193
194 /* no invisible reset implemented */
195
196 return -EINVAL;
197}
198
Alexandre Rames626950d2013-01-14 17:20:22 +0000199#ifdef CONFIG_EEH
200/* When a PCI device is isolated from the bus, a subsequent MMIO read is
201 * required for the kernel EEH mechanisms to notice. As the Solarflare driver
202 * was written to minimise MMIO read (for latency) then a periodic call to check
203 * the EEH status of the device is required so that device recovery can happen
204 * in a timely fashion.
205 */
206static void siena_monitor(struct efx_nic *efx)
207{
208 struct eeh_dev *eehdev =
209 of_node_to_eeh_dev(pci_device_to_OF_node(efx->pci_dev));
210
211 eeh_dev_check_failure(eehdev);
212}
213#endif
214
Ben Hutchingsafd4aea2009-11-29 15:15:25 +0000215static int siena_probe_nvconfig(struct efx_nic *efx)
216{
Ben Hutchingscc180b62011-12-08 19:51:47 +0000217 u32 caps = 0;
218 int rc;
219
220 rc = efx_mcdi_get_board_cfg(efx, efx->net_dev->perm_addr, NULL, &caps);
221
222 efx->timer_quantum_ns =
223 (caps & (1 << MC_CMD_CAPABILITIES_TURBO_ACTIVE_LBN)) ?
224 3072 : 6144; /* 768 cycles */
225 return rc;
Ben Hutchingsafd4aea2009-11-29 15:15:25 +0000226}
227
Ben Hutchingsc15eed22013-08-29 00:45:48 +0100228static int siena_dimension_resources(struct efx_nic *efx)
Ben Hutchings28e47c42012-02-15 01:58:49 +0000229{
230 /* Each port has a small block of internal SRAM dedicated to
231 * the buffer table and descriptor caches. In theory we can
232 * map both blocks to one port, but we don't.
233 */
Ben Hutchings86094f72013-08-21 19:51:04 +0100234 efx_farch_dimension_resources(efx, FR_CZ_BUF_FULL_TBL_ROWS / 2);
Ben Hutchingsc15eed22013-08-29 00:45:48 +0100235 return 0;
Ben Hutchings28e47c42012-02-15 01:58:49 +0000236}
237
Ben Hutchingsb1057982012-09-19 00:56:47 +0100238static unsigned int siena_mem_map_size(struct efx_nic *efx)
239{
240 return FR_CZ_MC_TREG_SMEM +
241 FR_CZ_MC_TREG_SMEM_STEP * FR_CZ_MC_TREG_SMEM_ROWS;
242}
243
Ben Hutchingsafd4aea2009-11-29 15:15:25 +0000244static int siena_probe_nic(struct efx_nic *efx)
245{
246 struct siena_nic_data *nic_data;
Ben Hutchingsd42a8f42010-06-01 11:32:43 +0000247 efx_oword_t reg;
Ben Hutchingsafd4aea2009-11-29 15:15:25 +0000248 int rc;
249
250 /* Allocate storage for hardware specific data */
251 nic_data = kzalloc(sizeof(struct siena_nic_data), GFP_KERNEL);
252 if (!nic_data)
253 return -ENOMEM;
254 efx->nic_data = nic_data;
255
Ben Hutchings86094f72013-08-21 19:51:04 +0100256 if (efx_farch_fpga_ver(efx) != 0) {
Ben Hutchings62776d02010-06-23 11:30:07 +0000257 netif_err(efx, probe, efx->net_dev,
258 "Siena FPGA not supported\n");
Ben Hutchingsafd4aea2009-11-29 15:15:25 +0000259 rc = -ENODEV;
260 goto fail1;
261 }
262
Ben Hutchingsb1057982012-09-19 00:56:47 +0100263 efx->max_channels = EFX_MAX_CHANNELS;
264
Ben Hutchingsd42a8f42010-06-01 11:32:43 +0000265 efx_reado(efx, &reg, FR_AZ_CS_DEBUG);
Ben Hutchings66020412013-06-10 18:03:17 +0100266 efx->port_num = EFX_OWORD_FIELD(reg, FRF_CZ_CS_PORT_NUM) - 1;
Ben Hutchingsd42a8f42010-06-01 11:32:43 +0000267
Ben Hutchingsf073dde2012-09-18 02:33:55 +0100268 rc = efx_mcdi_init(efx);
Ben Hutchingsafd4aea2009-11-29 15:15:25 +0000269 if (rc)
David S. Miller8decf862011-09-22 03:23:13 -0400270 goto fail1;
Ben Hutchingsafd4aea2009-11-29 15:15:25 +0000271
Ben Hutchingsafd4aea2009-11-29 15:15:25 +0000272 /* Now we can reset the NIC */
Ben Hutchings6bff8612012-09-18 02:33:52 +0100273 rc = efx_mcdi_reset(efx, RESET_TYPE_ALL);
Ben Hutchingsafd4aea2009-11-29 15:15:25 +0000274 if (rc) {
Ben Hutchings62776d02010-06-23 11:30:07 +0000275 netif_err(efx, probe, efx->net_dev, "failed to reset NIC\n");
Ben Hutchingsafd4aea2009-11-29 15:15:25 +0000276 goto fail3;
277 }
278
279 siena_init_wol(efx);
280
281 /* Allocate memory for INT_KER */
Ben Hutchings0d19a542012-09-18 21:59:52 +0100282 rc = efx_nic_alloc_buffer(efx, &efx->irq_status, sizeof(efx_oword_t),
283 GFP_KERNEL);
Ben Hutchingsafd4aea2009-11-29 15:15:25 +0000284 if (rc)
285 goto fail4;
286 BUG_ON(efx->irq_status.dma_addr & 0x0f);
287
Ben Hutchings62776d02010-06-23 11:30:07 +0000288 netif_dbg(efx, probe, efx->net_dev,
289 "INT_KER at %llx (virt %p phys %llx)\n",
290 (unsigned long long)efx->irq_status.dma_addr,
291 efx->irq_status.addr,
292 (unsigned long long)virt_to_phys(efx->irq_status.addr));
Ben Hutchingsafd4aea2009-11-29 15:15:25 +0000293
294 /* Read in the non-volatile configuration */
295 rc = siena_probe_nvconfig(efx);
296 if (rc == -EINVAL) {
Ben Hutchings62776d02010-06-23 11:30:07 +0000297 netif_err(efx, probe, efx->net_dev,
298 "NVRAM is invalid therefore using defaults\n");
Ben Hutchingsafd4aea2009-11-29 15:15:25 +0000299 efx->phy_type = PHY_TYPE_NONE;
300 efx->mdio.prtad = MDIO_PRTAD_NONE;
301 } else if (rc) {
302 goto fail5;
303 }
304
Ben Hutchings55c5e0f2012-01-06 20:25:39 +0000305 rc = efx_mcdi_mon_probe(efx);
306 if (rc)
307 goto fail5;
308
Ben Hutchingscd2d5b52012-02-14 00:48:07 +0000309 efx_sriov_probe(efx);
Ben Hutchingsac36baf2013-10-15 17:54:56 +0100310 efx_ptp_defer_probe_with_channel(efx);
Ben Hutchingscd2d5b52012-02-14 00:48:07 +0000311
Ben Hutchingsafd4aea2009-11-29 15:15:25 +0000312 return 0;
313
314fail5:
315 efx_nic_free_buffer(efx, &efx->irq_status);
316fail4:
317fail3:
Ben Hutchingsf3ad5002012-09-18 02:33:56 +0100318 efx_mcdi_fini(efx);
Ben Hutchingsafd4aea2009-11-29 15:15:25 +0000319fail1:
320 kfree(efx->nic_data);
321 return rc;
322}
323
324/* This call performs hardware-specific global initialisation, such as
325 * defining the descriptor cache sizes and number of RSS channels.
326 * It does not set up any buffers, descriptor rings or event queues.
327 */
328static int siena_init_nic(struct efx_nic *efx)
329{
330 efx_oword_t temp;
331 int rc;
332
333 /* Recover from a failed assertion post-reset */
334 rc = efx_mcdi_handle_assertion(efx);
335 if (rc)
336 return rc;
337
338 /* Squash TX of packets of 16 bytes or less */
339 efx_reado(efx, &temp, FR_AZ_TX_RESERVED);
340 EFX_SET_OWORD_FIELD(temp, FRF_BZ_TX_FLUSH_MIN_LEN_EN, 1);
341 efx_writeo(efx, &temp, FR_AZ_TX_RESERVED);
342
343 /* Do not enable TX_NO_EOP_DISC_EN, since it limits packets to 16
344 * descriptors (which is bad).
345 */
346 efx_reado(efx, &temp, FR_AZ_TX_CFG);
347 EFX_SET_OWORD_FIELD(temp, FRF_AZ_TX_NO_EOP_DISC_EN, 0);
348 EFX_SET_OWORD_FIELD(temp, FRF_CZ_TX_FILTER_EN_BIT, 1);
349 efx_writeo(efx, &temp, FR_AZ_TX_CFG);
350
351 efx_reado(efx, &temp, FR_AZ_RX_CFG);
352 EFX_SET_OWORD_FIELD(temp, FRF_BZ_RX_DESC_PUSH_EN, 0);
353 EFX_SET_OWORD_FIELD(temp, FRF_BZ_RX_INGR_EN, 1);
Ben Hutchings477e54e2010-06-25 07:05:56 +0000354 /* Enable hash insertion. This is broken for the 'Falcon' hash
355 * if IPv6 hashing is also enabled, so also select Toeplitz
356 * TCP/IPv4 and IPv4 hashes. */
357 EFX_SET_OWORD_FIELD(temp, FRF_BZ_RX_HASH_INSRT_HDR, 1);
358 EFX_SET_OWORD_FIELD(temp, FRF_BZ_RX_HASH_ALG, 1);
359 EFX_SET_OWORD_FIELD(temp, FRF_BZ_RX_IP_HASH, 1);
Ben Hutchings85740cdf2013-01-29 23:33:15 +0000360 EFX_SET_OWORD_FIELD(temp, FRF_BZ_RX_USR_BUF_SIZE,
361 EFX_RX_USR_BUF_SIZE >> 5);
Ben Hutchingsafd4aea2009-11-29 15:15:25 +0000362 efx_writeo(efx, &temp, FR_AZ_RX_CFG);
363
Ben Hutchings477e54e2010-06-25 07:05:56 +0000364 /* Set hash key for IPv4 */
365 memcpy(&temp, efx->rx_hash_key, sizeof(temp));
366 efx_writeo(efx, &temp, FR_BZ_RX_RSS_TKEY);
367
Ben Hutchingsd614cfb2010-04-28 09:29:02 +0000368 /* Enable IPv6 RSS */
Ben Hutchings5d3a6fc2010-06-25 07:05:43 +0000369 BUILD_BUG_ON(sizeof(efx->rx_hash_key) <
Ben Hutchingsd614cfb2010-04-28 09:29:02 +0000370 2 * sizeof(temp) + FRF_CZ_RX_RSS_IPV6_TKEY_HI_WIDTH / 8 ||
371 FRF_CZ_RX_RSS_IPV6_TKEY_HI_LBN != 0);
Ben Hutchings5d3a6fc2010-06-25 07:05:43 +0000372 memcpy(&temp, efx->rx_hash_key, sizeof(temp));
Ben Hutchingsd614cfb2010-04-28 09:29:02 +0000373 efx_writeo(efx, &temp, FR_CZ_RX_RSS_IPV6_REG1);
Ben Hutchings5d3a6fc2010-06-25 07:05:43 +0000374 memcpy(&temp, efx->rx_hash_key + sizeof(temp), sizeof(temp));
Ben Hutchingsd614cfb2010-04-28 09:29:02 +0000375 efx_writeo(efx, &temp, FR_CZ_RX_RSS_IPV6_REG2);
376 EFX_POPULATE_OWORD_2(temp, FRF_CZ_RX_RSS_IPV6_THASH_ENABLE, 1,
377 FRF_CZ_RX_RSS_IPV6_IP_THASH_ENABLE, 1);
Ben Hutchings5d3a6fc2010-06-25 07:05:43 +0000378 memcpy(&temp, efx->rx_hash_key + 2 * sizeof(temp),
Ben Hutchingsd614cfb2010-04-28 09:29:02 +0000379 FRF_CZ_RX_RSS_IPV6_TKEY_HI_WIDTH / 8);
380 efx_writeo(efx, &temp, FR_CZ_RX_RSS_IPV6_REG3);
381
Ben Hutchingsafd4aea2009-11-29 15:15:25 +0000382 /* Enable event logging */
383 rc = efx_mcdi_log_ctrl(efx, true, false, 0);
384 if (rc)
385 return rc;
386
387 /* Set destination of both TX and RX Flush events */
388 EFX_POPULATE_OWORD_1(temp, FRF_BZ_FLS_EVQ_ID, 0);
389 efx_writeo(efx, &temp, FR_BZ_DP_CTRL);
390
391 EFX_POPULATE_OWORD_1(temp, FRF_CZ_USREV_DIS, 1);
392 efx_writeo(efx, &temp, FR_CZ_USR_EV_CFG);
393
Ben Hutchings86094f72013-08-21 19:51:04 +0100394 efx_farch_init_common(efx);
Ben Hutchingsafd4aea2009-11-29 15:15:25 +0000395 return 0;
396}
397
398static void siena_remove_nic(struct efx_nic *efx)
399{
Ben Hutchings55c5e0f2012-01-06 20:25:39 +0000400 efx_mcdi_mon_remove(efx);
401
Ben Hutchingsafd4aea2009-11-29 15:15:25 +0000402 efx_nic_free_buffer(efx, &efx->irq_status);
403
Ben Hutchings6bff8612012-09-18 02:33:52 +0100404 efx_mcdi_reset(efx, RESET_TYPE_ALL);
Ben Hutchingsafd4aea2009-11-29 15:15:25 +0000405
Ben Hutchings4c75b43a2013-08-29 19:04:03 +0100406 efx_mcdi_fini(efx);
Ben Hutchingsafd4aea2009-11-29 15:15:25 +0000407
408 /* Tear down the private nic state */
David S. Miller8decf862011-09-22 03:23:13 -0400409 kfree(efx->nic_data);
Ben Hutchingsafd4aea2009-11-29 15:15:25 +0000410 efx->nic_data = NULL;
411}
412
Ben Hutchingscd0ecc92012-12-14 21:52:56 +0000413#define SIENA_DMA_STAT(ext_name, mcdi_name) \
414 [SIENA_STAT_ ## ext_name] = \
415 { #ext_name, 64, 8 * MC_CMD_MAC_ ## mcdi_name }
416#define SIENA_OTHER_STAT(ext_name) \
417 [SIENA_STAT_ ## ext_name] = { #ext_name, 0, 0 }
418
419static const struct efx_hw_stat_desc siena_stat_desc[SIENA_STAT_COUNT] = {
420 SIENA_DMA_STAT(tx_bytes, TX_BYTES),
421 SIENA_OTHER_STAT(tx_good_bytes),
422 SIENA_DMA_STAT(tx_bad_bytes, TX_BAD_BYTES),
423 SIENA_DMA_STAT(tx_packets, TX_PKTS),
424 SIENA_DMA_STAT(tx_bad, TX_BAD_FCS_PKTS),
425 SIENA_DMA_STAT(tx_pause, TX_PAUSE_PKTS),
426 SIENA_DMA_STAT(tx_control, TX_CONTROL_PKTS),
427 SIENA_DMA_STAT(tx_unicast, TX_UNICAST_PKTS),
428 SIENA_DMA_STAT(tx_multicast, TX_MULTICAST_PKTS),
429 SIENA_DMA_STAT(tx_broadcast, TX_BROADCAST_PKTS),
430 SIENA_DMA_STAT(tx_lt64, TX_LT64_PKTS),
431 SIENA_DMA_STAT(tx_64, TX_64_PKTS),
432 SIENA_DMA_STAT(tx_65_to_127, TX_65_TO_127_PKTS),
433 SIENA_DMA_STAT(tx_128_to_255, TX_128_TO_255_PKTS),
434 SIENA_DMA_STAT(tx_256_to_511, TX_256_TO_511_PKTS),
435 SIENA_DMA_STAT(tx_512_to_1023, TX_512_TO_1023_PKTS),
436 SIENA_DMA_STAT(tx_1024_to_15xx, TX_1024_TO_15XX_PKTS),
437 SIENA_DMA_STAT(tx_15xx_to_jumbo, TX_15XX_TO_JUMBO_PKTS),
438 SIENA_DMA_STAT(tx_gtjumbo, TX_GTJUMBO_PKTS),
439 SIENA_OTHER_STAT(tx_collision),
440 SIENA_DMA_STAT(tx_single_collision, TX_SINGLE_COLLISION_PKTS),
441 SIENA_DMA_STAT(tx_multiple_collision, TX_MULTIPLE_COLLISION_PKTS),
442 SIENA_DMA_STAT(tx_excessive_collision, TX_EXCESSIVE_COLLISION_PKTS),
443 SIENA_DMA_STAT(tx_deferred, TX_DEFERRED_PKTS),
444 SIENA_DMA_STAT(tx_late_collision, TX_LATE_COLLISION_PKTS),
445 SIENA_DMA_STAT(tx_excessive_deferred, TX_EXCESSIVE_DEFERRED_PKTS),
446 SIENA_DMA_STAT(tx_non_tcpudp, TX_NON_TCPUDP_PKTS),
447 SIENA_DMA_STAT(tx_mac_src_error, TX_MAC_SRC_ERR_PKTS),
448 SIENA_DMA_STAT(tx_ip_src_error, TX_IP_SRC_ERR_PKTS),
449 SIENA_DMA_STAT(rx_bytes, RX_BYTES),
450 SIENA_OTHER_STAT(rx_good_bytes),
451 SIENA_DMA_STAT(rx_bad_bytes, RX_BAD_BYTES),
452 SIENA_DMA_STAT(rx_packets, RX_PKTS),
453 SIENA_DMA_STAT(rx_good, RX_GOOD_PKTS),
454 SIENA_DMA_STAT(rx_bad, RX_BAD_FCS_PKTS),
455 SIENA_DMA_STAT(rx_pause, RX_PAUSE_PKTS),
456 SIENA_DMA_STAT(rx_control, RX_CONTROL_PKTS),
457 SIENA_DMA_STAT(rx_unicast, RX_UNICAST_PKTS),
458 SIENA_DMA_STAT(rx_multicast, RX_MULTICAST_PKTS),
459 SIENA_DMA_STAT(rx_broadcast, RX_BROADCAST_PKTS),
460 SIENA_DMA_STAT(rx_lt64, RX_UNDERSIZE_PKTS),
461 SIENA_DMA_STAT(rx_64, RX_64_PKTS),
462 SIENA_DMA_STAT(rx_65_to_127, RX_65_TO_127_PKTS),
463 SIENA_DMA_STAT(rx_128_to_255, RX_128_TO_255_PKTS),
464 SIENA_DMA_STAT(rx_256_to_511, RX_256_TO_511_PKTS),
465 SIENA_DMA_STAT(rx_512_to_1023, RX_512_TO_1023_PKTS),
466 SIENA_DMA_STAT(rx_1024_to_15xx, RX_1024_TO_15XX_PKTS),
467 SIENA_DMA_STAT(rx_15xx_to_jumbo, RX_15XX_TO_JUMBO_PKTS),
468 SIENA_DMA_STAT(rx_gtjumbo, RX_GTJUMBO_PKTS),
469 SIENA_DMA_STAT(rx_bad_gtjumbo, RX_JABBER_PKTS),
470 SIENA_DMA_STAT(rx_overflow, RX_OVERFLOW_PKTS),
471 SIENA_DMA_STAT(rx_false_carrier, RX_FALSE_CARRIER_PKTS),
472 SIENA_DMA_STAT(rx_symbol_error, RX_SYMBOL_ERROR_PKTS),
473 SIENA_DMA_STAT(rx_align_error, RX_ALIGN_ERROR_PKTS),
474 SIENA_DMA_STAT(rx_length_error, RX_LENGTH_ERROR_PKTS),
475 SIENA_DMA_STAT(rx_internal_error, RX_INTERNAL_ERROR_PKTS),
476 SIENA_DMA_STAT(rx_nodesc_drop_cnt, RX_NODESC_DROPS),
477};
478static const unsigned long siena_stat_mask[] = {
479 [0 ... BITS_TO_LONGS(SIENA_STAT_COUNT) - 1] = ~0UL,
480};
481
482static size_t siena_describe_nic_stats(struct efx_nic *efx, u8 *names)
483{
484 return efx_nic_describe_stats(siena_stat_desc, SIENA_STAT_COUNT,
485 siena_stat_mask, names);
486}
487
Ben Hutchingsafd4aea2009-11-29 15:15:25 +0000488static int siena_try_update_nic_stats(struct efx_nic *efx)
489{
Ben Hutchingscd0ecc92012-12-14 21:52:56 +0000490 struct siena_nic_data *nic_data = efx->nic_data;
491 u64 *stats = nic_data->stats;
Steve Hodgsona659b2a2011-06-22 12:11:33 +0100492 __le64 *dma_stats;
Steve Hodgsona659b2a2011-06-22 12:11:33 +0100493 __le64 generation_start, generation_end;
Ben Hutchingsafd4aea2009-11-29 15:15:25 +0000494
Joe Perches43d620c2011-06-16 19:08:06 +0000495 dma_stats = efx->stats_buffer.addr;
Ben Hutchingsafd4aea2009-11-29 15:15:25 +0000496
497 generation_end = dma_stats[MC_CMD_MAC_GENERATION_END];
Ben Hutchings43f775b22012-09-18 02:33:54 +0100498 if (generation_end == EFX_MC_STATS_GENERATION_INVALID)
Ben Hutchingsafd4aea2009-11-29 15:15:25 +0000499 return 0;
500 rmb();
Ben Hutchingscd0ecc92012-12-14 21:52:56 +0000501 efx_nic_update_stats(siena_stat_desc, SIENA_STAT_COUNT, siena_stat_mask,
502 stats, efx->stats_buffer.addr, false);
Ben Hutchingsafd4aea2009-11-29 15:15:25 +0000503 rmb();
504 generation_start = dma_stats[MC_CMD_MAC_GENERATION_START];
505 if (generation_end != generation_start)
506 return -EAGAIN;
507
Ben Hutchingscd0ecc92012-12-14 21:52:56 +0000508 /* Update derived statistics */
Jon Cooperf8f3b5a2013-09-30 17:36:50 +0100509 efx_nic_fix_nodesc_drop_stat(efx,
510 &stats[SIENA_STAT_rx_nodesc_drop_cnt]);
Ben Hutchingscd0ecc92012-12-14 21:52:56 +0000511 efx_update_diff_stat(&stats[SIENA_STAT_tx_good_bytes],
512 stats[SIENA_STAT_tx_bytes] -
513 stats[SIENA_STAT_tx_bad_bytes]);
514 stats[SIENA_STAT_tx_collision] =
515 stats[SIENA_STAT_tx_single_collision] +
516 stats[SIENA_STAT_tx_multiple_collision] +
517 stats[SIENA_STAT_tx_excessive_collision] +
518 stats[SIENA_STAT_tx_late_collision];
519 efx_update_diff_stat(&stats[SIENA_STAT_rx_good_bytes],
520 stats[SIENA_STAT_rx_bytes] -
521 stats[SIENA_STAT_rx_bad_bytes]);
Ben Hutchingsafd4aea2009-11-29 15:15:25 +0000522 return 0;
523}
524
Ben Hutchingscd0ecc92012-12-14 21:52:56 +0000525static size_t siena_update_nic_stats(struct efx_nic *efx, u64 *full_stats,
526 struct rtnl_link_stats64 *core_stats)
Ben Hutchingsafd4aea2009-11-29 15:15:25 +0000527{
Ben Hutchingscd0ecc92012-12-14 21:52:56 +0000528 struct siena_nic_data *nic_data = efx->nic_data;
529 u64 *stats = nic_data->stats;
Ben Hutchingsaabc5642010-04-28 09:00:35 +0000530 int retry;
531
532 /* If we're unlucky enough to read statistics wduring the DMA, wait
533 * up to 10ms for it to finish (typically takes <500us) */
534 for (retry = 0; retry < 100; ++retry) {
535 if (siena_try_update_nic_stats(efx) == 0)
Ben Hutchingscd0ecc92012-12-14 21:52:56 +0000536 break;
Ben Hutchingsaabc5642010-04-28 09:00:35 +0000537 udelay(100);
538 }
539
Ben Hutchingscd0ecc92012-12-14 21:52:56 +0000540 if (full_stats)
541 memcpy(full_stats, stats, sizeof(u64) * SIENA_STAT_COUNT);
542
543 if (core_stats) {
544 core_stats->rx_packets = stats[SIENA_STAT_rx_packets];
545 core_stats->tx_packets = stats[SIENA_STAT_tx_packets];
546 core_stats->rx_bytes = stats[SIENA_STAT_rx_bytes];
547 core_stats->tx_bytes = stats[SIENA_STAT_tx_bytes];
548 core_stats->rx_dropped = stats[SIENA_STAT_rx_nodesc_drop_cnt];
549 core_stats->multicast = stats[SIENA_STAT_rx_multicast];
550 core_stats->collisions = stats[SIENA_STAT_tx_collision];
551 core_stats->rx_length_errors =
552 stats[SIENA_STAT_rx_gtjumbo] +
553 stats[SIENA_STAT_rx_length_error];
554 core_stats->rx_crc_errors = stats[SIENA_STAT_rx_bad];
555 core_stats->rx_frame_errors = stats[SIENA_STAT_rx_align_error];
556 core_stats->rx_fifo_errors = stats[SIENA_STAT_rx_overflow];
557 core_stats->tx_window_errors =
558 stats[SIENA_STAT_tx_late_collision];
559
560 core_stats->rx_errors = (core_stats->rx_length_errors +
561 core_stats->rx_crc_errors +
562 core_stats->rx_frame_errors +
563 stats[SIENA_STAT_rx_symbol_error]);
564 core_stats->tx_errors = (core_stats->tx_window_errors +
565 stats[SIENA_STAT_tx_bad]);
566 }
567
568 return SIENA_STAT_COUNT;
Ben Hutchingsafd4aea2009-11-29 15:15:25 +0000569}
570
Ben Hutchings319ec642012-10-08 16:56:18 +0100571static int siena_mac_reconfigure(struct efx_nic *efx)
572{
573 MCDI_DECLARE_BUF(inbuf, MC_CMD_SET_MCAST_HASH_IN_LEN);
574 int rc;
575
576 BUILD_BUG_ON(MC_CMD_SET_MCAST_HASH_IN_LEN !=
577 MC_CMD_SET_MCAST_HASH_IN_HASH0_OFST +
578 sizeof(efx->multicast_hash));
579
Ben Hutchings964e6132012-11-19 23:08:22 +0000580 efx_farch_filter_sync_rx_mode(efx);
581
Ben Hutchings319ec642012-10-08 16:56:18 +0100582 WARN_ON(!mutex_is_locked(&efx->mac_lock));
583
584 rc = efx_mcdi_set_mac(efx);
585 if (rc != 0)
586 return rc;
587
588 memcpy(MCDI_PTR(inbuf, SET_MCAST_HASH_IN_HASH0),
589 efx->multicast_hash.byte, sizeof(efx->multicast_hash));
590 return efx_mcdi_rpc(efx, MC_CMD_SET_MCAST_HASH,
591 inbuf, sizeof(inbuf), NULL, 0, NULL);
592}
593
Ben Hutchingsafd4aea2009-11-29 15:15:25 +0000594/**************************************************************************
595 *
596 * Wake on LAN
597 *
598 **************************************************************************
599 */
600
601static void siena_get_wol(struct efx_nic *efx, struct ethtool_wolinfo *wol)
602{
603 struct siena_nic_data *nic_data = efx->nic_data;
604
605 wol->supported = WAKE_MAGIC;
606 if (nic_data->wol_filter_id != -1)
607 wol->wolopts = WAKE_MAGIC;
608 else
609 wol->wolopts = 0;
610 memset(&wol->sopass, 0, sizeof(wol->sopass));
611}
612
613
614static int siena_set_wol(struct efx_nic *efx, u32 type)
615{
616 struct siena_nic_data *nic_data = efx->nic_data;
617 int rc;
618
619 if (type & ~WAKE_MAGIC)
620 return -EINVAL;
621
622 if (type & WAKE_MAGIC) {
623 if (nic_data->wol_filter_id != -1)
624 efx_mcdi_wol_filter_remove(efx,
625 nic_data->wol_filter_id);
Ben Hutchings02ebc262010-12-02 13:48:20 +0000626 rc = efx_mcdi_wol_filter_set_magic(efx, efx->net_dev->dev_addr,
Ben Hutchingsafd4aea2009-11-29 15:15:25 +0000627 &nic_data->wol_filter_id);
628 if (rc)
629 goto fail;
630
631 pci_wake_from_d3(efx->pci_dev, true);
632 } else {
633 rc = efx_mcdi_wol_filter_reset(efx);
634 nic_data->wol_filter_id = -1;
635 pci_wake_from_d3(efx->pci_dev, false);
636 if (rc)
637 goto fail;
638 }
639
640 return 0;
641 fail:
Ben Hutchings62776d02010-06-23 11:30:07 +0000642 netif_err(efx, hw, efx->net_dev, "%s failed: type=%d rc=%d\n",
643 __func__, type, rc);
Ben Hutchingsafd4aea2009-11-29 15:15:25 +0000644 return rc;
645}
646
647
648static void siena_init_wol(struct efx_nic *efx)
649{
650 struct siena_nic_data *nic_data = efx->nic_data;
651 int rc;
652
653 rc = efx_mcdi_wol_filter_get_magic(efx, &nic_data->wol_filter_id);
654
655 if (rc != 0) {
656 /* If it failed, attempt to get into a synchronised
657 * state with MC by resetting any set WoL filters */
658 efx_mcdi_wol_filter_reset(efx);
659 nic_data->wol_filter_id = -1;
660 } else if (nic_data->wol_filter_id != -1) {
661 pci_wake_from_d3(efx->pci_dev, true);
662 }
663}
664
Ben Hutchingsf3ad5002012-09-18 02:33:56 +0100665/**************************************************************************
666 *
667 * MCDI
668 *
669 **************************************************************************
670 */
671
672#define MCDI_PDU(efx) \
673 (efx_port_num(efx) ? MC_SMEM_P1_PDU_OFST : MC_SMEM_P0_PDU_OFST)
674#define MCDI_DOORBELL(efx) \
675 (efx_port_num(efx) ? MC_SMEM_P1_DOORBELL_OFST : MC_SMEM_P0_DOORBELL_OFST)
676#define MCDI_STATUS(efx) \
677 (efx_port_num(efx) ? MC_SMEM_P1_STATUS_OFST : MC_SMEM_P0_STATUS_OFST)
678
679static void siena_mcdi_request(struct efx_nic *efx,
680 const efx_dword_t *hdr, size_t hdr_len,
681 const efx_dword_t *sdu, size_t sdu_len)
682{
683 unsigned pdu = FR_CZ_MC_TREG_SMEM + MCDI_PDU(efx);
684 unsigned doorbell = FR_CZ_MC_TREG_SMEM + MCDI_DOORBELL(efx);
685 unsigned int i;
686 unsigned int inlen_dw = DIV_ROUND_UP(sdu_len, 4);
687
688 EFX_BUG_ON_PARANOID(hdr_len != 4);
689
690 efx_writed(efx, hdr, pdu);
691
692 for (i = 0; i < inlen_dw; i++)
693 efx_writed(efx, &sdu[i], pdu + hdr_len + 4 * i);
694
695 /* Ensure the request is written out before the doorbell */
696 wmb();
697
698 /* ring the doorbell with a distinctive value */
699 _efx_writed(efx, (__force __le32) 0x45789abc, doorbell);
700}
701
702static bool siena_mcdi_poll_response(struct efx_nic *efx)
703{
704 unsigned int pdu = FR_CZ_MC_TREG_SMEM + MCDI_PDU(efx);
705 efx_dword_t hdr;
706
707 efx_readd(efx, &hdr, pdu);
708
709 /* All 1's indicates that shared memory is in reset (and is
710 * not a valid hdr). Wait for it to come out reset before
711 * completing the command
712 */
713 return EFX_DWORD_FIELD(hdr, EFX_DWORD_0) != 0xffffffff &&
714 EFX_DWORD_FIELD(hdr, MCDI_HEADER_RESPONSE);
715}
716
717static void siena_mcdi_read_response(struct efx_nic *efx, efx_dword_t *outbuf,
718 size_t offset, size_t outlen)
719{
720 unsigned int pdu = FR_CZ_MC_TREG_SMEM + MCDI_PDU(efx);
721 unsigned int outlen_dw = DIV_ROUND_UP(outlen, 4);
722 int i;
723
724 for (i = 0; i < outlen_dw; i++)
725 efx_readd(efx, &outbuf[i], pdu + offset + 4 * i);
726}
727
728static int siena_mcdi_poll_reboot(struct efx_nic *efx)
729{
Ben Hutchingscd0ecc92012-12-14 21:52:56 +0000730 struct siena_nic_data *nic_data = efx->nic_data;
Ben Hutchingsf3ad5002012-09-18 02:33:56 +0100731 unsigned int addr = FR_CZ_MC_TREG_SMEM + MCDI_STATUS(efx);
732 efx_dword_t reg;
733 u32 value;
734
735 efx_readd(efx, &reg, addr);
736 value = EFX_DWORD_FIELD(reg, EFX_DWORD_0);
737
738 if (value == 0)
739 return 0;
740
741 EFX_ZERO_DWORD(reg);
742 efx_writed(efx, &reg, addr);
743
Ben Hutchingscd0ecc92012-12-14 21:52:56 +0000744 /* MAC statistics have been cleared on the NIC; clear the local
745 * copies that we update with efx_update_diff_stat().
746 */
747 nic_data->stats[SIENA_STAT_tx_good_bytes] = 0;
748 nic_data->stats[SIENA_STAT_rx_good_bytes] = 0;
749
Ben Hutchingsf3ad5002012-09-18 02:33:56 +0100750 if (value == MC_STATUS_DWORD_ASSERT)
751 return -EINTR;
752 else
753 return -EIO;
754}
Ben Hutchingsafd4aea2009-11-29 15:15:25 +0000755
756/**************************************************************************
757 *
Ben Hutchings45a3fd52012-11-28 04:38:14 +0000758 * MTD
759 *
760 **************************************************************************
761 */
762
763#ifdef CONFIG_SFC_MTD
764
765struct siena_nvram_type_info {
766 int port;
767 const char *name;
768};
769
770static const struct siena_nvram_type_info siena_nvram_types[] = {
771 [MC_CMD_NVRAM_TYPE_DISABLED_CALLISTO] = { 0, "sfc_dummy_phy" },
772 [MC_CMD_NVRAM_TYPE_MC_FW] = { 0, "sfc_mcfw" },
773 [MC_CMD_NVRAM_TYPE_MC_FW_BACKUP] = { 0, "sfc_mcfw_backup" },
774 [MC_CMD_NVRAM_TYPE_STATIC_CFG_PORT0] = { 0, "sfc_static_cfg" },
775 [MC_CMD_NVRAM_TYPE_STATIC_CFG_PORT1] = { 1, "sfc_static_cfg" },
776 [MC_CMD_NVRAM_TYPE_DYNAMIC_CFG_PORT0] = { 0, "sfc_dynamic_cfg" },
777 [MC_CMD_NVRAM_TYPE_DYNAMIC_CFG_PORT1] = { 1, "sfc_dynamic_cfg" },
778 [MC_CMD_NVRAM_TYPE_EXP_ROM] = { 0, "sfc_exp_rom" },
779 [MC_CMD_NVRAM_TYPE_EXP_ROM_CFG_PORT0] = { 0, "sfc_exp_rom_cfg" },
780 [MC_CMD_NVRAM_TYPE_EXP_ROM_CFG_PORT1] = { 1, "sfc_exp_rom_cfg" },
781 [MC_CMD_NVRAM_TYPE_PHY_PORT0] = { 0, "sfc_phy_fw" },
782 [MC_CMD_NVRAM_TYPE_PHY_PORT1] = { 1, "sfc_phy_fw" },
783 [MC_CMD_NVRAM_TYPE_FPGA] = { 0, "sfc_fpga" },
784};
785
786static int siena_mtd_probe_partition(struct efx_nic *efx,
787 struct efx_mcdi_mtd_partition *part,
788 unsigned int type)
789{
790 const struct siena_nvram_type_info *info;
791 size_t size, erase_size;
792 bool protected;
793 int rc;
794
795 if (type >= ARRAY_SIZE(siena_nvram_types) ||
796 siena_nvram_types[type].name == NULL)
797 return -ENODEV;
798
799 info = &siena_nvram_types[type];
800
801 if (info->port != efx_port_num(efx))
802 return -ENODEV;
803
804 rc = efx_mcdi_nvram_info(efx, type, &size, &erase_size, &protected);
805 if (rc)
806 return rc;
807 if (protected)
808 return -ENODEV; /* hide it */
809
810 part->nvram_type = type;
811 part->common.dev_type_name = "Siena NVRAM manager";
812 part->common.type_name = info->name;
813
814 part->common.mtd.type = MTD_NORFLASH;
815 part->common.mtd.flags = MTD_CAP_NORFLASH;
816 part->common.mtd.size = size;
817 part->common.mtd.erasesize = erase_size;
818
819 return 0;
820}
821
822static int siena_mtd_get_fw_subtypes(struct efx_nic *efx,
823 struct efx_mcdi_mtd_partition *parts,
824 size_t n_parts)
825{
826 uint16_t fw_subtype_list[
827 MC_CMD_GET_BOARD_CFG_OUT_FW_SUBTYPE_LIST_MAXNUM];
828 size_t i;
829 int rc;
830
831 rc = efx_mcdi_get_board_cfg(efx, NULL, fw_subtype_list, NULL);
832 if (rc)
833 return rc;
834
835 for (i = 0; i < n_parts; i++)
836 parts[i].fw_subtype = fw_subtype_list[parts[i].nvram_type];
837
838 return 0;
839}
840
841static int siena_mtd_probe(struct efx_nic *efx)
842{
843 struct efx_mcdi_mtd_partition *parts;
844 u32 nvram_types;
845 unsigned int type;
846 size_t n_parts;
847 int rc;
848
849 ASSERT_RTNL();
850
851 rc = efx_mcdi_nvram_types(efx, &nvram_types);
852 if (rc)
853 return rc;
854
855 parts = kcalloc(hweight32(nvram_types), sizeof(*parts), GFP_KERNEL);
856 if (!parts)
857 return -ENOMEM;
858
859 type = 0;
860 n_parts = 0;
861
862 while (nvram_types != 0) {
863 if (nvram_types & 1) {
864 rc = siena_mtd_probe_partition(efx, &parts[n_parts],
865 type);
866 if (rc == 0)
867 n_parts++;
868 else if (rc != -ENODEV)
869 goto fail;
870 }
871 type++;
872 nvram_types >>= 1;
873 }
874
875 rc = siena_mtd_get_fw_subtypes(efx, parts, n_parts);
876 if (rc)
877 goto fail;
878
879 rc = efx_mtd_add(efx, &parts[0].common, n_parts, sizeof(*parts));
880fail:
881 if (rc)
882 kfree(parts);
883 return rc;
884}
885
886#endif /* CONFIG_SFC_MTD */
887
888/**************************************************************************
889 *
Ben Hutchingsafd4aea2009-11-29 15:15:25 +0000890 * Revision-dependent attributes used by efx.c and nic.c
891 *
892 **************************************************************************
893 */
894
stephen hemminger6c8c2512011-04-14 05:50:12 +0000895const struct efx_nic_type siena_a0_nic_type = {
Ben Hutchingsb1057982012-09-19 00:56:47 +0100896 .mem_map_size = siena_mem_map_size,
Ben Hutchingsafd4aea2009-11-29 15:15:25 +0000897 .probe = siena_probe_nic,
898 .remove = siena_remove_nic,
899 .init = siena_init_nic,
Ben Hutchings28e47c42012-02-15 01:58:49 +0000900 .dimension_resources = siena_dimension_resources,
Ben Hutchingsafd4aea2009-11-29 15:15:25 +0000901 .fini = efx_port_dummy_op_void,
Alexandre Rames626950d2013-01-14 17:20:22 +0000902#ifdef CONFIG_EEH
903 .monitor = siena_monitor,
904#else
Ben Hutchingsafd4aea2009-11-29 15:15:25 +0000905 .monitor = NULL,
Alexandre Rames626950d2013-01-14 17:20:22 +0000906#endif
Ben Hutchings6bff8612012-09-18 02:33:52 +0100907 .map_reset_reason = efx_mcdi_map_reset_reason,
Ben Hutchings0e2a9c72011-06-24 20:50:07 +0100908 .map_reset_flags = siena_map_reset_flags,
Ben Hutchings6bff8612012-09-18 02:33:52 +0100909 .reset = efx_mcdi_reset,
Ben Hutchings43f775b22012-09-18 02:33:54 +0100910 .probe_port = efx_mcdi_port_probe,
911 .remove_port = efx_mcdi_port_remove,
Ben Hutchingse42c3d82013-05-27 16:52:54 +0100912 .fini_dmaq = efx_farch_fini_dmaq,
Ben Hutchingsd5e8cc62012-09-06 16:52:31 +0100913 .prepare_flush = siena_prepare_flush,
914 .finish_flush = siena_finish_flush,
Ben Hutchingscd0ecc92012-12-14 21:52:56 +0000915 .describe_stats = siena_describe_nic_stats,
Ben Hutchingsafd4aea2009-11-29 15:15:25 +0000916 .update_stats = siena_update_nic_stats,
Ben Hutchings43f775b22012-09-18 02:33:54 +0100917 .start_stats = efx_mcdi_mac_start_stats,
Jon Cooperf8f3b5a2013-09-30 17:36:50 +0100918 .pull_stats = efx_mcdi_mac_pull_stats,
Ben Hutchings43f775b22012-09-18 02:33:54 +0100919 .stop_stats = efx_mcdi_mac_stop_stats,
Ben Hutchingsafd4aea2009-11-29 15:15:25 +0000920 .set_id_led = efx_mcdi_set_id_led,
921 .push_irq_moderation = siena_push_irq_moderation,
Ben Hutchings319ec642012-10-08 16:56:18 +0100922 .reconfigure_mac = siena_mac_reconfigure,
Ben Hutchings710b2082011-09-03 00:15:00 +0100923 .check_mac_fault = efx_mcdi_mac_check_fault,
Ben Hutchings43f775b22012-09-18 02:33:54 +0100924 .reconfigure_port = efx_mcdi_port_reconfigure,
Ben Hutchingsafd4aea2009-11-29 15:15:25 +0000925 .get_wol = siena_get_wol,
926 .set_wol = siena_set_wol,
927 .resume_wol = siena_init_wol,
Ben Hutchingsd4f2cec2012-07-04 03:58:33 +0100928 .test_chip = siena_test_chip,
Ben Hutchings2e803402010-02-03 09:31:01 +0000929 .test_nvram = efx_mcdi_nvram_test_all,
Ben Hutchingsf3ad5002012-09-18 02:33:56 +0100930 .mcdi_request = siena_mcdi_request,
931 .mcdi_poll_response = siena_mcdi_poll_response,
932 .mcdi_read_response = siena_mcdi_read_response,
933 .mcdi_poll_reboot = siena_mcdi_poll_reboot,
Ben Hutchings86094f72013-08-21 19:51:04 +0100934 .irq_enable_master = efx_farch_irq_enable_master,
935 .irq_test_generate = efx_farch_irq_test_generate,
936 .irq_disable_non_ev = efx_farch_irq_disable_master,
937 .irq_handle_msi = efx_farch_msi_interrupt,
938 .irq_handle_legacy = efx_farch_legacy_interrupt,
939 .tx_probe = efx_farch_tx_probe,
940 .tx_init = efx_farch_tx_init,
941 .tx_remove = efx_farch_tx_remove,
942 .tx_write = efx_farch_tx_write,
943 .rx_push_indir_table = efx_farch_rx_push_indir_table,
944 .rx_probe = efx_farch_rx_probe,
945 .rx_init = efx_farch_rx_init,
946 .rx_remove = efx_farch_rx_remove,
947 .rx_write = efx_farch_rx_write,
948 .rx_defer_refill = efx_farch_rx_defer_refill,
949 .ev_probe = efx_farch_ev_probe,
950 .ev_init = efx_farch_ev_init,
951 .ev_fini = efx_farch_ev_fini,
952 .ev_remove = efx_farch_ev_remove,
953 .ev_process = efx_farch_ev_process,
954 .ev_read_ack = efx_farch_ev_read_ack,
955 .ev_test_generate = efx_farch_ev_test_generate,
Ben Hutchingsadd72472012-11-08 01:46:53 +0000956 .filter_table_probe = efx_farch_filter_table_probe,
957 .filter_table_restore = efx_farch_filter_table_restore,
958 .filter_table_remove = efx_farch_filter_table_remove,
959 .filter_update_rx_scatter = efx_farch_filter_update_rx_scatter,
960 .filter_insert = efx_farch_filter_insert,
961 .filter_remove_safe = efx_farch_filter_remove_safe,
962 .filter_get_safe = efx_farch_filter_get_safe,
963 .filter_clear_rx = efx_farch_filter_clear_rx,
964 .filter_count_rx_used = efx_farch_filter_count_rx_used,
965 .filter_get_rx_id_limit = efx_farch_filter_get_rx_id_limit,
966 .filter_get_rx_ids = efx_farch_filter_get_rx_ids,
967#ifdef CONFIG_RFS_ACCEL
968 .filter_rfs_insert = efx_farch_filter_rfs_insert,
969 .filter_rfs_expire_one = efx_farch_filter_rfs_expire_one,
970#endif
Ben Hutchings45a3fd52012-11-28 04:38:14 +0000971#ifdef CONFIG_SFC_MTD
972 .mtd_probe = siena_mtd_probe,
973 .mtd_rename = efx_mcdi_mtd_rename,
974 .mtd_read = efx_mcdi_mtd_read,
975 .mtd_erase = efx_mcdi_mtd_erase,
976 .mtd_write = efx_mcdi_mtd_write,
977 .mtd_sync = efx_mcdi_mtd_sync,
978#endif
Laurence Evans977a5d52013-03-07 11:46:58 +0000979 .ptp_write_host_time = siena_ptp_write_host_time,
Daniel Pieczko9ec06592013-11-21 17:11:25 +0000980 .ptp_set_ts_config = siena_ptp_set_ts_config,
Ben Hutchingsafd4aea2009-11-29 15:15:25 +0000981
982 .revision = EFX_REV_SIENA_A0,
Ben Hutchingsafd4aea2009-11-29 15:15:25 +0000983 .txd_ptr_tbl_base = FR_BZ_TX_DESC_PTR_TBL,
984 .rxd_ptr_tbl_base = FR_BZ_RX_DESC_PTR_TBL,
985 .buf_tbl_base = FR_BZ_BUF_FULL_TBL,
986 .evq_ptr_tbl_base = FR_BZ_EVQ_PTR_TBL,
987 .evq_rptr_tbl_base = FR_BZ_EVQ_RPTR,
988 .max_dma_mask = DMA_BIT_MASK(FSF_AZ_TX_KER_BUF_ADDR_WIDTH),
Jon Cooper43a37392012-10-18 15:49:54 +0100989 .rx_prefix_size = FS_BZ_RX_PREFIX_SIZE,
990 .rx_hash_offset = FS_BZ_RX_PREFIX_HASH_OFST,
Ben Hutchingsafd4aea2009-11-29 15:15:25 +0000991 .rx_buffer_padding = 0,
Ben Hutchings85740cdf2013-01-29 23:33:15 +0000992 .can_rx_scatter = true,
Ben Hutchingsafd4aea2009-11-29 15:15:25 +0000993 .max_interrupt_mode = EFX_INT_MODE_MSIX,
Ben Hutchingscc180b62011-12-08 19:51:47 +0000994 .timer_period_max = 1 << FRF_CZ_TC_TIMER_VAL_WIDTH,
Ben Hutchings39c9cf02010-06-23 11:31:28 +0000995 .offload_features = (NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM |
Ben Hutchingsb4187e42010-09-20 08:43:42 +0000996 NETIF_F_RXHASH | NETIF_F_NTUPLE),
Ben Hutchingsdf2cd8a2012-09-19 00:56:18 +0100997 .mcdi_max_ver = 1,
Ben Hutchingsadd72472012-11-08 01:46:53 +0000998 .max_rx_ip_filters = FR_BZ_RX_FILTER_TBL0_ROWS,
Daniel Pieczko9ec06592013-11-21 17:11:25 +0000999 .hwtstamp_filters = (1 << HWTSTAMP_FILTER_NONE |
1000 1 << HWTSTAMP_FILTER_PTP_V1_L4_EVENT |
1001 1 << HWTSTAMP_FILTER_PTP_V1_L4_SYNC |
1002 1 << HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ |
1003 1 << HWTSTAMP_FILTER_PTP_V2_L4_EVENT |
1004 1 << HWTSTAMP_FILTER_PTP_V2_L4_SYNC |
1005 1 << HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ),
Ben Hutchingsafd4aea2009-11-29 15:15:25 +00001006};