Gavin Shan | 8747f36 | 2013-06-20 13:21:06 +0800 | [diff] [blame] | 1 | /* |
| 2 | * The file intends to implement the functions needed by EEH, which is |
| 3 | * built on IODA compliant chip. Actually, lots of functions related |
| 4 | * to EEH would be built based on the OPAL APIs. |
| 5 | * |
| 6 | * Copyright Benjamin Herrenschmidt & Gavin Shan, IBM Corporation 2013. |
| 7 | * |
| 8 | * This program is free software; you can redistribute it and/or modify |
| 9 | * it under the terms of the GNU General Public License as published by |
| 10 | * the Free Software Foundation; either version 2 of the License, or |
| 11 | * (at your option) any later version. |
| 12 | */ |
| 13 | |
| 14 | #include <linux/bootmem.h> |
Gavin Shan | 8998897 | 2013-06-20 18:13:26 +0800 | [diff] [blame] | 15 | #include <linux/debugfs.h> |
Gavin Shan | 8747f36 | 2013-06-20 13:21:06 +0800 | [diff] [blame] | 16 | #include <linux/delay.h> |
Gavin Shan | 8747f36 | 2013-06-20 13:21:06 +0800 | [diff] [blame] | 17 | #include <linux/io.h> |
| 18 | #include <linux/irq.h> |
| 19 | #include <linux/kernel.h> |
| 20 | #include <linux/msi.h> |
Gavin Shan | 7cb9d93 | 2013-06-20 18:13:24 +0800 | [diff] [blame] | 21 | #include <linux/notifier.h> |
Gavin Shan | 8747f36 | 2013-06-20 13:21:06 +0800 | [diff] [blame] | 22 | #include <linux/pci.h> |
| 23 | #include <linux/string.h> |
| 24 | |
| 25 | #include <asm/eeh.h> |
| 26 | #include <asm/eeh_event.h> |
| 27 | #include <asm/io.h> |
| 28 | #include <asm/iommu.h> |
| 29 | #include <asm/msi_bitmap.h> |
| 30 | #include <asm/opal.h> |
| 31 | #include <asm/pci-bridge.h> |
| 32 | #include <asm/ppc-pci.h> |
| 33 | #include <asm/tce.h> |
| 34 | |
| 35 | #include "powernv.h" |
| 36 | #include "pci.h" |
| 37 | |
Gavin Shan | 7cb9d93 | 2013-06-20 18:13:24 +0800 | [diff] [blame] | 38 | static int ioda_eeh_nb_init = 0; |
| 39 | |
| 40 | static int ioda_eeh_event(struct notifier_block *nb, |
| 41 | unsigned long events, void *change) |
| 42 | { |
| 43 | uint64_t changed_evts = (uint64_t)change; |
| 44 | |
| 45 | /* We simply send special EEH event */ |
| 46 | if ((changed_evts & OPAL_EVENT_PCI_ERROR) && |
Gavin Shan | 66f9af83 | 2014-02-12 15:24:56 +0800 | [diff] [blame] | 47 | (events & OPAL_EVENT_PCI_ERROR) && |
| 48 | eeh_enabled()) |
Gavin Shan | 7cb9d93 | 2013-06-20 18:13:24 +0800 | [diff] [blame] | 49 | eeh_send_failure_event(NULL); |
| 50 | |
| 51 | return 0; |
| 52 | } |
| 53 | |
| 54 | static struct notifier_block ioda_eeh_nb = { |
| 55 | .notifier_call = ioda_eeh_event, |
| 56 | .next = NULL, |
| 57 | .priority = 0 |
| 58 | }; |
Gavin Shan | 70f942d | 2013-06-20 13:21:12 +0800 | [diff] [blame] | 59 | |
Gavin Shan | 8998897 | 2013-06-20 18:13:26 +0800 | [diff] [blame] | 60 | #ifdef CONFIG_DEBUG_FS |
Gavin Shan | ff6bdcd | 2013-09-06 09:00:01 +0800 | [diff] [blame] | 61 | static int ioda_eeh_dbgfs_set(void *data, int offset, u64 val) |
Gavin Shan | 8998897 | 2013-06-20 18:13:26 +0800 | [diff] [blame] | 62 | { |
| 63 | struct pci_controller *hose = data; |
| 64 | struct pnv_phb *phb = hose->private_data; |
| 65 | |
Gavin Shan | ff6bdcd | 2013-09-06 09:00:01 +0800 | [diff] [blame] | 66 | out_be64(phb->regs + offset, val); |
Gavin Shan | 8998897 | 2013-06-20 18:13:26 +0800 | [diff] [blame] | 67 | return 0; |
| 68 | } |
| 69 | |
Gavin Shan | ff6bdcd | 2013-09-06 09:00:01 +0800 | [diff] [blame] | 70 | static int ioda_eeh_dbgfs_get(void *data, int offset, u64 *val) |
Gavin Shan | 8998897 | 2013-06-20 18:13:26 +0800 | [diff] [blame] | 71 | { |
| 72 | struct pci_controller *hose = data; |
| 73 | struct pnv_phb *phb = hose->private_data; |
| 74 | |
Gavin Shan | ff6bdcd | 2013-09-06 09:00:01 +0800 | [diff] [blame] | 75 | *val = in_be64(phb->regs + offset); |
Gavin Shan | 8998897 | 2013-06-20 18:13:26 +0800 | [diff] [blame] | 76 | return 0; |
| 77 | } |
| 78 | |
Gavin Shan | ff6bdcd | 2013-09-06 09:00:01 +0800 | [diff] [blame] | 79 | static int ioda_eeh_outb_dbgfs_set(void *data, u64 val) |
| 80 | { |
| 81 | return ioda_eeh_dbgfs_set(data, 0xD10, val); |
| 82 | } |
| 83 | |
| 84 | static int ioda_eeh_outb_dbgfs_get(void *data, u64 *val) |
| 85 | { |
| 86 | return ioda_eeh_dbgfs_get(data, 0xD10, val); |
| 87 | } |
| 88 | |
| 89 | static int ioda_eeh_inbA_dbgfs_set(void *data, u64 val) |
| 90 | { |
| 91 | return ioda_eeh_dbgfs_set(data, 0xD90, val); |
| 92 | } |
| 93 | |
| 94 | static int ioda_eeh_inbA_dbgfs_get(void *data, u64 *val) |
| 95 | { |
| 96 | return ioda_eeh_dbgfs_get(data, 0xD90, val); |
| 97 | } |
| 98 | |
| 99 | static int ioda_eeh_inbB_dbgfs_set(void *data, u64 val) |
| 100 | { |
| 101 | return ioda_eeh_dbgfs_set(data, 0xE10, val); |
| 102 | } |
| 103 | |
| 104 | static int ioda_eeh_inbB_dbgfs_get(void *data, u64 *val) |
| 105 | { |
| 106 | return ioda_eeh_dbgfs_get(data, 0xE10, val); |
| 107 | } |
| 108 | |
| 109 | DEFINE_SIMPLE_ATTRIBUTE(ioda_eeh_outb_dbgfs_ops, ioda_eeh_outb_dbgfs_get, |
| 110 | ioda_eeh_outb_dbgfs_set, "0x%llx\n"); |
| 111 | DEFINE_SIMPLE_ATTRIBUTE(ioda_eeh_inbA_dbgfs_ops, ioda_eeh_inbA_dbgfs_get, |
| 112 | ioda_eeh_inbA_dbgfs_set, "0x%llx\n"); |
| 113 | DEFINE_SIMPLE_ATTRIBUTE(ioda_eeh_inbB_dbgfs_ops, ioda_eeh_inbB_dbgfs_get, |
| 114 | ioda_eeh_inbB_dbgfs_set, "0x%llx\n"); |
Gavin Shan | 8998897 | 2013-06-20 18:13:26 +0800 | [diff] [blame] | 115 | #endif /* CONFIG_DEBUG_FS */ |
| 116 | |
Gavin Shan | 73370c6 | 2013-06-20 13:21:07 +0800 | [diff] [blame] | 117 | /** |
| 118 | * ioda_eeh_post_init - Chip dependent post initialization |
| 119 | * @hose: PCI controller |
| 120 | * |
| 121 | * The function will be called after eeh PEs and devices |
| 122 | * have been built. That means the EEH is ready to supply |
| 123 | * service with I/O cache. |
| 124 | */ |
| 125 | static int ioda_eeh_post_init(struct pci_controller *hose) |
| 126 | { |
| 127 | struct pnv_phb *phb = hose->private_data; |
Gavin Shan | 7cb9d93 | 2013-06-20 18:13:24 +0800 | [diff] [blame] | 128 | int ret; |
| 129 | |
| 130 | /* Register OPAL event notifier */ |
| 131 | if (!ioda_eeh_nb_init) { |
| 132 | ret = opal_notifier_register(&ioda_eeh_nb); |
| 133 | if (ret) { |
| 134 | pr_err("%s: Can't register OPAL event notifier (%d)\n", |
| 135 | __func__, ret); |
| 136 | return ret; |
| 137 | } |
| 138 | |
| 139 | ioda_eeh_nb_init = 1; |
| 140 | } |
Gavin Shan | 73370c6 | 2013-06-20 13:21:07 +0800 | [diff] [blame] | 141 | |
Gavin Shan | 8998897 | 2013-06-20 18:13:26 +0800 | [diff] [blame] | 142 | #ifdef CONFIG_DEBUG_FS |
Gavin Shan | ff6bdcd | 2013-09-06 09:00:01 +0800 | [diff] [blame] | 143 | if (phb->dbgfs) { |
| 144 | debugfs_create_file("err_injct_outbound", 0600, |
Gavin Shan | 20bb842 | 2013-09-06 09:00:00 +0800 | [diff] [blame] | 145 | phb->dbgfs, hose, |
Gavin Shan | ff6bdcd | 2013-09-06 09:00:01 +0800 | [diff] [blame] | 146 | &ioda_eeh_outb_dbgfs_ops); |
| 147 | debugfs_create_file("err_injct_inboundA", 0600, |
| 148 | phb->dbgfs, hose, |
| 149 | &ioda_eeh_inbA_dbgfs_ops); |
| 150 | debugfs_create_file("err_injct_inboundB", 0600, |
| 151 | phb->dbgfs, hose, |
| 152 | &ioda_eeh_inbB_dbgfs_ops); |
| 153 | } |
Gavin Shan | 8998897 | 2013-06-20 18:13:26 +0800 | [diff] [blame] | 154 | #endif |
| 155 | |
Gavin Shan | 20bb842 | 2013-09-06 09:00:00 +0800 | [diff] [blame] | 156 | phb->eeh_state |= PNV_EEH_STATE_ENABLED; |
Gavin Shan | 73370c6 | 2013-06-20 13:21:07 +0800 | [diff] [blame] | 157 | |
| 158 | return 0; |
| 159 | } |
| 160 | |
Gavin Shan | eb00598 | 2013-06-20 13:21:08 +0800 | [diff] [blame] | 161 | /** |
| 162 | * ioda_eeh_set_option - Set EEH operation or I/O setting |
| 163 | * @pe: EEH PE |
| 164 | * @option: options |
| 165 | * |
| 166 | * Enable or disable EEH option for the indicated PE. The |
| 167 | * function also can be used to enable I/O or DMA for the |
| 168 | * PE. |
| 169 | */ |
| 170 | static int ioda_eeh_set_option(struct eeh_pe *pe, int option) |
| 171 | { |
| 172 | s64 ret; |
| 173 | u32 pe_no; |
| 174 | struct pci_controller *hose = pe->phb; |
| 175 | struct pnv_phb *phb = hose->private_data; |
| 176 | |
| 177 | /* Check on PE number */ |
| 178 | if (pe->addr < 0 || pe->addr >= phb->ioda.total_pe) { |
| 179 | pr_err("%s: PE address %x out of range [0, %x] " |
| 180 | "on PHB#%x\n", |
| 181 | __func__, pe->addr, phb->ioda.total_pe, |
| 182 | hose->global_number); |
| 183 | return -EINVAL; |
| 184 | } |
| 185 | |
| 186 | pe_no = pe->addr; |
| 187 | switch (option) { |
| 188 | case EEH_OPT_DISABLE: |
| 189 | ret = -EEXIST; |
| 190 | break; |
| 191 | case EEH_OPT_ENABLE: |
| 192 | ret = 0; |
| 193 | break; |
| 194 | case EEH_OPT_THAW_MMIO: |
| 195 | ret = opal_pci_eeh_freeze_clear(phb->opal_id, pe_no, |
| 196 | OPAL_EEH_ACTION_CLEAR_FREEZE_MMIO); |
| 197 | if (ret) { |
| 198 | pr_warning("%s: Failed to enable MMIO for " |
| 199 | "PHB#%x-PE#%x, err=%lld\n", |
| 200 | __func__, hose->global_number, pe_no, ret); |
| 201 | return -EIO; |
| 202 | } |
| 203 | |
| 204 | break; |
| 205 | case EEH_OPT_THAW_DMA: |
| 206 | ret = opal_pci_eeh_freeze_clear(phb->opal_id, pe_no, |
| 207 | OPAL_EEH_ACTION_CLEAR_FREEZE_DMA); |
| 208 | if (ret) { |
| 209 | pr_warning("%s: Failed to enable DMA for " |
| 210 | "PHB#%x-PE#%x, err=%lld\n", |
| 211 | __func__, hose->global_number, pe_no, ret); |
| 212 | return -EIO; |
| 213 | } |
| 214 | |
| 215 | break; |
| 216 | default: |
| 217 | pr_warning("%s: Invalid option %d\n", __func__, option); |
| 218 | return -EINVAL; |
| 219 | } |
| 220 | |
| 221 | return ret; |
| 222 | } |
| 223 | |
Gavin Shan | 8c41a7f | 2013-06-20 13:21:09 +0800 | [diff] [blame] | 224 | /** |
| 225 | * ioda_eeh_get_state - Retrieve the state of PE |
| 226 | * @pe: EEH PE |
| 227 | * |
| 228 | * The PE's state should be retrieved from the PEEV, PEST |
| 229 | * IODA tables. Since the OPAL has exported the function |
| 230 | * to do it, it'd better to use that. |
| 231 | */ |
| 232 | static int ioda_eeh_get_state(struct eeh_pe *pe) |
| 233 | { |
| 234 | s64 ret = 0; |
| 235 | u8 fstate; |
| 236 | u16 pcierr; |
| 237 | u32 pe_no; |
| 238 | int result; |
| 239 | struct pci_controller *hose = pe->phb; |
| 240 | struct pnv_phb *phb = hose->private_data; |
| 241 | |
| 242 | /* |
| 243 | * Sanity check on PE address. The PHB PE address should |
| 244 | * be zero. |
| 245 | */ |
| 246 | if (pe->addr < 0 || pe->addr >= phb->ioda.total_pe) { |
| 247 | pr_err("%s: PE address %x out of range [0, %x] " |
| 248 | "on PHB#%x\n", |
| 249 | __func__, pe->addr, phb->ioda.total_pe, |
| 250 | hose->global_number); |
| 251 | return EEH_STATE_NOT_SUPPORT; |
| 252 | } |
| 253 | |
| 254 | /* Retrieve PE status through OPAL */ |
| 255 | pe_no = pe->addr; |
| 256 | ret = opal_pci_eeh_freeze_status(phb->opal_id, pe_no, |
| 257 | &fstate, &pcierr, NULL); |
| 258 | if (ret) { |
| 259 | pr_err("%s: Failed to get EEH status on " |
| 260 | "PHB#%x-PE#%x\n, err=%lld\n", |
| 261 | __func__, hose->global_number, pe_no, ret); |
| 262 | return EEH_STATE_NOT_SUPPORT; |
| 263 | } |
| 264 | |
| 265 | /* Check PHB status */ |
| 266 | if (pe->type & EEH_PE_PHB) { |
| 267 | result = 0; |
| 268 | result &= ~EEH_STATE_RESET_ACTIVE; |
| 269 | |
| 270 | if (pcierr != OPAL_EEH_PHB_ERROR) { |
| 271 | result |= EEH_STATE_MMIO_ACTIVE; |
| 272 | result |= EEH_STATE_DMA_ACTIVE; |
| 273 | result |= EEH_STATE_MMIO_ENABLED; |
| 274 | result |= EEH_STATE_DMA_ENABLED; |
| 275 | } |
| 276 | |
| 277 | return result; |
| 278 | } |
| 279 | |
| 280 | /* Parse result out */ |
| 281 | result = 0; |
| 282 | switch (fstate) { |
| 283 | case OPAL_EEH_STOPPED_NOT_FROZEN: |
| 284 | result &= ~EEH_STATE_RESET_ACTIVE; |
| 285 | result |= EEH_STATE_MMIO_ACTIVE; |
| 286 | result |= EEH_STATE_DMA_ACTIVE; |
| 287 | result |= EEH_STATE_MMIO_ENABLED; |
| 288 | result |= EEH_STATE_DMA_ENABLED; |
| 289 | break; |
| 290 | case OPAL_EEH_STOPPED_MMIO_FREEZE: |
| 291 | result &= ~EEH_STATE_RESET_ACTIVE; |
| 292 | result |= EEH_STATE_DMA_ACTIVE; |
| 293 | result |= EEH_STATE_DMA_ENABLED; |
| 294 | break; |
| 295 | case OPAL_EEH_STOPPED_DMA_FREEZE: |
| 296 | result &= ~EEH_STATE_RESET_ACTIVE; |
| 297 | result |= EEH_STATE_MMIO_ACTIVE; |
| 298 | result |= EEH_STATE_MMIO_ENABLED; |
| 299 | break; |
| 300 | case OPAL_EEH_STOPPED_MMIO_DMA_FREEZE: |
| 301 | result &= ~EEH_STATE_RESET_ACTIVE; |
| 302 | break; |
| 303 | case OPAL_EEH_STOPPED_RESET: |
| 304 | result |= EEH_STATE_RESET_ACTIVE; |
| 305 | break; |
| 306 | case OPAL_EEH_STOPPED_TEMP_UNAVAIL: |
| 307 | result |= EEH_STATE_UNAVAILABLE; |
| 308 | break; |
| 309 | case OPAL_EEH_STOPPED_PERM_UNAVAIL: |
| 310 | result |= EEH_STATE_NOT_SUPPORT; |
| 311 | break; |
| 312 | default: |
| 313 | pr_warning("%s: Unexpected EEH status 0x%x " |
| 314 | "on PHB#%x-PE#%x\n", |
| 315 | __func__, fstate, hose->global_number, pe_no); |
| 316 | } |
| 317 | |
| 318 | return result; |
| 319 | } |
| 320 | |
Gavin Shan | 9d5cab0 | 2013-06-20 13:21:10 +0800 | [diff] [blame] | 321 | static int ioda_eeh_pe_clear(struct eeh_pe *pe) |
| 322 | { |
| 323 | struct pci_controller *hose; |
| 324 | struct pnv_phb *phb; |
| 325 | u32 pe_no; |
| 326 | u8 fstate; |
| 327 | u16 pcierr; |
| 328 | s64 ret; |
| 329 | |
| 330 | pe_no = pe->addr; |
| 331 | hose = pe->phb; |
| 332 | phb = pe->phb->private_data; |
| 333 | |
| 334 | /* Clear the EEH error on the PE */ |
| 335 | ret = opal_pci_eeh_freeze_clear(phb->opal_id, |
| 336 | pe_no, OPAL_EEH_ACTION_CLEAR_FREEZE_ALL); |
| 337 | if (ret) { |
| 338 | pr_err("%s: Failed to clear EEH error for " |
| 339 | "PHB#%x-PE#%x, err=%lld\n", |
| 340 | __func__, hose->global_number, pe_no, ret); |
| 341 | return -EIO; |
| 342 | } |
| 343 | |
| 344 | /* |
| 345 | * Read the PE state back and verify that the frozen |
| 346 | * state has been removed. |
| 347 | */ |
| 348 | ret = opal_pci_eeh_freeze_status(phb->opal_id, pe_no, |
| 349 | &fstate, &pcierr, NULL); |
| 350 | if (ret) { |
| 351 | pr_err("%s: Failed to get EEH status on " |
| 352 | "PHB#%x-PE#%x\n, err=%lld\n", |
| 353 | __func__, hose->global_number, pe_no, ret); |
| 354 | return -EIO; |
| 355 | } |
| 356 | |
| 357 | if (fstate != OPAL_EEH_STOPPED_NOT_FROZEN) { |
| 358 | pr_err("%s: Frozen state not cleared on " |
| 359 | "PHB#%x-PE#%x, sts=%x\n", |
| 360 | __func__, hose->global_number, pe_no, fstate); |
| 361 | return -EIO; |
| 362 | } |
| 363 | |
| 364 | return 0; |
| 365 | } |
| 366 | |
| 367 | static s64 ioda_eeh_phb_poll(struct pnv_phb *phb) |
| 368 | { |
| 369 | s64 rc = OPAL_HARDWARE; |
| 370 | |
| 371 | while (1) { |
| 372 | rc = opal_pci_poll(phb->opal_id); |
| 373 | if (rc <= 0) |
| 374 | break; |
| 375 | |
| 376 | msleep(rc); |
| 377 | } |
| 378 | |
| 379 | return rc; |
| 380 | } |
| 381 | |
| 382 | static int ioda_eeh_phb_reset(struct pci_controller *hose, int option) |
| 383 | { |
| 384 | struct pnv_phb *phb = hose->private_data; |
| 385 | s64 rc = OPAL_HARDWARE; |
| 386 | |
| 387 | pr_debug("%s: Reset PHB#%x, option=%d\n", |
| 388 | __func__, hose->global_number, option); |
| 389 | |
| 390 | /* Issue PHB complete reset request */ |
| 391 | if (option == EEH_RESET_FUNDAMENTAL || |
| 392 | option == EEH_RESET_HOT) |
| 393 | rc = opal_pci_reset(phb->opal_id, |
| 394 | OPAL_PHB_COMPLETE, |
| 395 | OPAL_ASSERT_RESET); |
| 396 | else if (option == EEH_RESET_DEACTIVATE) |
| 397 | rc = opal_pci_reset(phb->opal_id, |
| 398 | OPAL_PHB_COMPLETE, |
| 399 | OPAL_DEASSERT_RESET); |
| 400 | if (rc < 0) |
| 401 | goto out; |
| 402 | |
| 403 | /* |
| 404 | * Poll state of the PHB until the request is done |
| 405 | * successfully. |
| 406 | */ |
| 407 | rc = ioda_eeh_phb_poll(phb); |
| 408 | out: |
| 409 | if (rc != OPAL_SUCCESS) |
| 410 | return -EIO; |
| 411 | |
| 412 | return 0; |
| 413 | } |
| 414 | |
| 415 | static int ioda_eeh_root_reset(struct pci_controller *hose, int option) |
| 416 | { |
| 417 | struct pnv_phb *phb = hose->private_data; |
| 418 | s64 rc = OPAL_SUCCESS; |
| 419 | |
| 420 | pr_debug("%s: Reset PHB#%x, option=%d\n", |
| 421 | __func__, hose->global_number, option); |
| 422 | |
| 423 | /* |
| 424 | * During the reset deassert time, we needn't care |
| 425 | * the reset scope because the firmware does nothing |
| 426 | * for fundamental or hot reset during deassert phase. |
| 427 | */ |
| 428 | if (option == EEH_RESET_FUNDAMENTAL) |
| 429 | rc = opal_pci_reset(phb->opal_id, |
| 430 | OPAL_PCI_FUNDAMENTAL_RESET, |
| 431 | OPAL_ASSERT_RESET); |
| 432 | else if (option == EEH_RESET_HOT) |
| 433 | rc = opal_pci_reset(phb->opal_id, |
| 434 | OPAL_PCI_HOT_RESET, |
| 435 | OPAL_ASSERT_RESET); |
| 436 | else if (option == EEH_RESET_DEACTIVATE) |
| 437 | rc = opal_pci_reset(phb->opal_id, |
| 438 | OPAL_PCI_HOT_RESET, |
| 439 | OPAL_DEASSERT_RESET); |
| 440 | if (rc < 0) |
| 441 | goto out; |
| 442 | |
| 443 | /* Poll state of the PHB until the request is done */ |
| 444 | rc = ioda_eeh_phb_poll(phb); |
| 445 | out: |
| 446 | if (rc != OPAL_SUCCESS) |
| 447 | return -EIO; |
| 448 | |
| 449 | return 0; |
| 450 | } |
| 451 | |
| 452 | static int ioda_eeh_bridge_reset(struct pci_controller *hose, |
| 453 | struct pci_dev *dev, int option) |
| 454 | { |
| 455 | u16 ctrl; |
| 456 | |
| 457 | pr_debug("%s: Reset device %04x:%02x:%02x.%01x with option %d\n", |
| 458 | __func__, hose->global_number, dev->bus->number, |
| 459 | PCI_SLOT(dev->devfn), PCI_FUNC(dev->devfn), option); |
| 460 | |
| 461 | switch (option) { |
| 462 | case EEH_RESET_FUNDAMENTAL: |
| 463 | case EEH_RESET_HOT: |
| 464 | pci_read_config_word(dev, PCI_BRIDGE_CONTROL, &ctrl); |
| 465 | ctrl |= PCI_BRIDGE_CTL_BUS_RESET; |
| 466 | pci_write_config_word(dev, PCI_BRIDGE_CONTROL, ctrl); |
| 467 | break; |
| 468 | case EEH_RESET_DEACTIVATE: |
| 469 | pci_read_config_word(dev, PCI_BRIDGE_CONTROL, &ctrl); |
| 470 | ctrl &= ~PCI_BRIDGE_CTL_BUS_RESET; |
| 471 | pci_write_config_word(dev, PCI_BRIDGE_CONTROL, ctrl); |
| 472 | break; |
| 473 | } |
| 474 | |
| 475 | return 0; |
| 476 | } |
| 477 | |
| 478 | /** |
| 479 | * ioda_eeh_reset - Reset the indicated PE |
| 480 | * @pe: EEH PE |
| 481 | * @option: reset option |
| 482 | * |
| 483 | * Do reset on the indicated PE. For PCI bus sensitive PE, |
| 484 | * we need to reset the parent p2p bridge. The PHB has to |
| 485 | * be reinitialized if the p2p bridge is root bridge. For |
| 486 | * PCI device sensitive PE, we will try to reset the device |
| 487 | * through FLR. For now, we don't have OPAL APIs to do HARD |
| 488 | * reset yet, so all reset would be SOFT (HOT) reset. |
| 489 | */ |
| 490 | static int ioda_eeh_reset(struct eeh_pe *pe, int option) |
| 491 | { |
| 492 | struct pci_controller *hose = pe->phb; |
Gavin Shan | 5b2e198 | 2014-02-12 15:24:54 +0800 | [diff] [blame] | 493 | struct pci_bus *bus; |
Gavin Shan | 9d5cab0 | 2013-06-20 13:21:10 +0800 | [diff] [blame] | 494 | int ret; |
| 495 | |
| 496 | /* |
| 497 | * Anyway, we have to clear the problematic state for the |
| 498 | * corresponding PE. However, we needn't do it if the PE |
| 499 | * is PHB associated. That means the PHB is having fatal |
| 500 | * errors and it needs reset. Further more, the AIB interface |
| 501 | * isn't reliable any more. |
| 502 | */ |
| 503 | if (!(pe->type & EEH_PE_PHB) && |
| 504 | (option == EEH_RESET_HOT || |
| 505 | option == EEH_RESET_FUNDAMENTAL)) { |
| 506 | ret = ioda_eeh_pe_clear(pe); |
| 507 | if (ret) |
| 508 | return -EIO; |
| 509 | } |
| 510 | |
| 511 | /* |
| 512 | * The rules applied to reset, either fundamental or hot reset: |
| 513 | * |
| 514 | * We always reset the direct upstream bridge of the PE. If the |
| 515 | * direct upstream bridge isn't root bridge, we always take hot |
| 516 | * reset no matter what option (fundamental or hot) is. Otherwise, |
| 517 | * we should do the reset according to the required option. |
| 518 | */ |
| 519 | if (pe->type & EEH_PE_PHB) { |
| 520 | ret = ioda_eeh_phb_reset(hose, option); |
| 521 | } else { |
Gavin Shan | 5b2e198 | 2014-02-12 15:24:54 +0800 | [diff] [blame] | 522 | bus = eeh_pe_bus_get(pe); |
| 523 | if (pci_is_root_bus(bus)) |
Gavin Shan | 9d5cab0 | 2013-06-20 13:21:10 +0800 | [diff] [blame] | 524 | ret = ioda_eeh_root_reset(hose, option); |
| 525 | else |
Gavin Shan | 5b2e198 | 2014-02-12 15:24:54 +0800 | [diff] [blame] | 526 | ret = ioda_eeh_bridge_reset(hose, bus->self, option); |
Gavin Shan | 9d5cab0 | 2013-06-20 13:21:10 +0800 | [diff] [blame] | 527 | } |
| 528 | |
| 529 | return ret; |
| 530 | } |
| 531 | |
Gavin Shan | bf90dfe | 2013-06-20 13:21:11 +0800 | [diff] [blame] | 532 | /** |
| 533 | * ioda_eeh_get_log - Retrieve error log |
| 534 | * @pe: EEH PE |
| 535 | * @severity: Severity level of the log |
| 536 | * @drv_log: buffer to store the log |
| 537 | * @len: space of the log buffer |
| 538 | * |
| 539 | * The function is used to retrieve error log from P7IOC. |
| 540 | */ |
| 541 | static int ioda_eeh_get_log(struct eeh_pe *pe, int severity, |
| 542 | char *drv_log, unsigned long len) |
| 543 | { |
| 544 | s64 ret; |
| 545 | unsigned long flags; |
| 546 | struct pci_controller *hose = pe->phb; |
| 547 | struct pnv_phb *phb = hose->private_data; |
| 548 | |
| 549 | spin_lock_irqsave(&phb->lock, flags); |
| 550 | |
| 551 | ret = opal_pci_get_phb_diag_data2(phb->opal_id, |
| 552 | phb->diag.blob, PNV_PCI_DIAG_BUF_SIZE); |
| 553 | if (ret) { |
| 554 | spin_unlock_irqrestore(&phb->lock, flags); |
Gavin Shan | 98cea5f | 2013-09-06 09:00:02 +0800 | [diff] [blame] | 555 | pr_warning("%s: Can't get log for PHB#%x-PE#%x (%lld)\n", |
| 556 | __func__, hose->global_number, pe->addr, ret); |
Gavin Shan | bf90dfe | 2013-06-20 13:21:11 +0800 | [diff] [blame] | 557 | return -EIO; |
| 558 | } |
| 559 | |
Gavin Shan | 2c77e95 | 2013-11-22 16:28:46 +0800 | [diff] [blame] | 560 | /* The PHB diag-data is always indicative */ |
| 561 | pnv_pci_dump_phb_diag_data(hose, phb->diag.blob); |
Gavin Shan | bf90dfe | 2013-06-20 13:21:11 +0800 | [diff] [blame] | 562 | |
| 563 | spin_unlock_irqrestore(&phb->lock, flags); |
| 564 | |
| 565 | return 0; |
| 566 | } |
| 567 | |
| 568 | /** |
| 569 | * ioda_eeh_configure_bridge - Configure the PCI bridges for the indicated PE |
| 570 | * @pe: EEH PE |
| 571 | * |
| 572 | * For particular PE, it might have included PCI bridges. In order |
| 573 | * to make the PE work properly, those PCI bridges should be configured |
| 574 | * correctly. However, we need do nothing on P7IOC since the reset |
| 575 | * function will do everything that should be covered by the function. |
| 576 | */ |
| 577 | static int ioda_eeh_configure_bridge(struct eeh_pe *pe) |
| 578 | { |
| 579 | return 0; |
| 580 | } |
| 581 | |
Gavin Shan | 70f942d | 2013-06-20 13:21:12 +0800 | [diff] [blame] | 582 | static void ioda_eeh_hub_diag_common(struct OpalIoP7IOCErrorData *data) |
| 583 | { |
| 584 | /* GEM */ |
| 585 | pr_info(" GEM XFIR: %016llx\n", data->gemXfir); |
| 586 | pr_info(" GEM RFIR: %016llx\n", data->gemRfir); |
| 587 | pr_info(" GEM RIRQFIR: %016llx\n", data->gemRirqfir); |
| 588 | pr_info(" GEM Mask: %016llx\n", data->gemMask); |
| 589 | pr_info(" GEM RWOF: %016llx\n", data->gemRwof); |
| 590 | |
| 591 | /* LEM */ |
| 592 | pr_info(" LEM FIR: %016llx\n", data->lemFir); |
| 593 | pr_info(" LEM Error Mask: %016llx\n", data->lemErrMask); |
| 594 | pr_info(" LEM Action 0: %016llx\n", data->lemAction0); |
| 595 | pr_info(" LEM Action 1: %016llx\n", data->lemAction1); |
| 596 | pr_info(" LEM WOF: %016llx\n", data->lemWof); |
| 597 | } |
| 598 | |
| 599 | static void ioda_eeh_hub_diag(struct pci_controller *hose) |
| 600 | { |
| 601 | struct pnv_phb *phb = hose->private_data; |
Brian W Hart | ca1de5d | 2013-12-20 13:06:01 -0600 | [diff] [blame] | 602 | struct OpalIoP7IOCErrorData *data = &phb->diag.hub_diag; |
Gavin Shan | 70f942d | 2013-06-20 13:21:12 +0800 | [diff] [blame] | 603 | long rc; |
| 604 | |
Brian W Hart | ca1de5d | 2013-12-20 13:06:01 -0600 | [diff] [blame] | 605 | rc = opal_pci_get_hub_diag_data(phb->hub_id, data, sizeof(*data)); |
Gavin Shan | 70f942d | 2013-06-20 13:21:12 +0800 | [diff] [blame] | 606 | if (rc != OPAL_SUCCESS) { |
| 607 | pr_warning("%s: Failed to get HUB#%llx diag-data (%ld)\n", |
| 608 | __func__, phb->hub_id, rc); |
| 609 | return; |
| 610 | } |
| 611 | |
| 612 | switch (data->type) { |
| 613 | case OPAL_P7IOC_DIAG_TYPE_RGC: |
| 614 | pr_info("P7IOC diag-data for RGC\n\n"); |
| 615 | ioda_eeh_hub_diag_common(data); |
| 616 | pr_info(" RGC Status: %016llx\n", data->rgc.rgcStatus); |
| 617 | pr_info(" RGC LDCP: %016llx\n", data->rgc.rgcLdcp); |
| 618 | break; |
| 619 | case OPAL_P7IOC_DIAG_TYPE_BI: |
| 620 | pr_info("P7IOC diag-data for BI %s\n\n", |
| 621 | data->bi.biDownbound ? "Downbound" : "Upbound"); |
| 622 | ioda_eeh_hub_diag_common(data); |
| 623 | pr_info(" BI LDCP 0: %016llx\n", data->bi.biLdcp0); |
| 624 | pr_info(" BI LDCP 1: %016llx\n", data->bi.biLdcp1); |
| 625 | pr_info(" BI LDCP 2: %016llx\n", data->bi.biLdcp2); |
| 626 | pr_info(" BI Fence Status: %016llx\n", data->bi.biFenceStatus); |
| 627 | break; |
| 628 | case OPAL_P7IOC_DIAG_TYPE_CI: |
| 629 | pr_info("P7IOC diag-data for CI Port %d\\nn", |
| 630 | data->ci.ciPort); |
| 631 | ioda_eeh_hub_diag_common(data); |
| 632 | pr_info(" CI Port Status: %016llx\n", data->ci.ciPortStatus); |
| 633 | pr_info(" CI Port LDCP: %016llx\n", data->ci.ciPortLdcp); |
| 634 | break; |
| 635 | case OPAL_P7IOC_DIAG_TYPE_MISC: |
| 636 | pr_info("P7IOC diag-data for MISC\n\n"); |
| 637 | ioda_eeh_hub_diag_common(data); |
| 638 | break; |
| 639 | case OPAL_P7IOC_DIAG_TYPE_I2C: |
| 640 | pr_info("P7IOC diag-data for I2C\n\n"); |
| 641 | ioda_eeh_hub_diag_common(data); |
| 642 | break; |
| 643 | default: |
| 644 | pr_warning("%s: Invalid type of HUB#%llx diag-data (%d)\n", |
| 645 | __func__, phb->hub_id, data->type); |
| 646 | } |
| 647 | } |
| 648 | |
Gavin Shan | 70f942d | 2013-06-20 13:21:12 +0800 | [diff] [blame] | 649 | static void ioda_eeh_phb_diag(struct pci_controller *hose) |
| 650 | { |
| 651 | struct pnv_phb *phb = hose->private_data; |
Gavin Shan | 70f942d | 2013-06-20 13:21:12 +0800 | [diff] [blame] | 652 | long rc; |
| 653 | |
Gavin Shan | 93aef2a | 2013-11-22 16:28:45 +0800 | [diff] [blame] | 654 | rc = opal_pci_get_phb_diag_data2(phb->opal_id, phb->diag.blob, |
| 655 | PNV_PCI_DIAG_BUF_SIZE); |
Gavin Shan | 70f942d | 2013-06-20 13:21:12 +0800 | [diff] [blame] | 656 | if (rc != OPAL_SUCCESS) { |
| 657 | pr_warning("%s: Failed to get diag-data for PHB#%x (%ld)\n", |
| 658 | __func__, hose->global_number, rc); |
| 659 | return; |
| 660 | } |
| 661 | |
Gavin Shan | 93aef2a | 2013-11-22 16:28:45 +0800 | [diff] [blame] | 662 | pnv_pci_dump_phb_diag_data(hose, phb->diag.blob); |
Gavin Shan | 70f942d | 2013-06-20 13:21:12 +0800 | [diff] [blame] | 663 | } |
| 664 | |
| 665 | static int ioda_eeh_get_phb_pe(struct pci_controller *hose, |
| 666 | struct eeh_pe **pe) |
| 667 | { |
| 668 | struct eeh_pe *phb_pe; |
| 669 | |
| 670 | phb_pe = eeh_phb_pe_get(hose); |
| 671 | if (!phb_pe) { |
| 672 | pr_warning("%s Can't find PE for PHB#%d\n", |
| 673 | __func__, hose->global_number); |
| 674 | return -EEXIST; |
| 675 | } |
| 676 | |
| 677 | *pe = phb_pe; |
| 678 | return 0; |
| 679 | } |
| 680 | |
| 681 | static int ioda_eeh_get_pe(struct pci_controller *hose, |
| 682 | u16 pe_no, struct eeh_pe **pe) |
| 683 | { |
| 684 | struct eeh_pe *phb_pe, *dev_pe; |
| 685 | struct eeh_dev dev; |
| 686 | |
| 687 | /* Find the PHB PE */ |
| 688 | if (ioda_eeh_get_phb_pe(hose, &phb_pe)) |
| 689 | return -EEXIST; |
| 690 | |
| 691 | /* Find the PE according to PE# */ |
| 692 | memset(&dev, 0, sizeof(struct eeh_dev)); |
| 693 | dev.phb = hose; |
| 694 | dev.pe_config_addr = pe_no; |
| 695 | dev_pe = eeh_pe_get(&dev); |
Gavin Shan | cb5b242 | 2014-01-15 13:16:13 +0800 | [diff] [blame] | 696 | if (!dev_pe) return -EEXIST; |
Gavin Shan | 70f942d | 2013-06-20 13:21:12 +0800 | [diff] [blame] | 697 | |
| 698 | *pe = dev_pe; |
| 699 | return 0; |
| 700 | } |
| 701 | |
| 702 | /** |
| 703 | * ioda_eeh_next_error - Retrieve next error for EEH core to handle |
| 704 | * @pe: The affected PE |
| 705 | * |
| 706 | * The function is expected to be called by EEH core while it gets |
| 707 | * special EEH event (without binding PE). The function calls to |
| 708 | * OPAL APIs for next error to handle. The informational error is |
| 709 | * handled internally by platform. However, the dead IOC, dead PHB, |
| 710 | * fenced PHB and frozen PE should be handled by EEH core eventually. |
| 711 | */ |
| 712 | static int ioda_eeh_next_error(struct eeh_pe **pe) |
| 713 | { |
Gavin Shan | 7e4e786 | 2014-01-15 13:16:11 +0800 | [diff] [blame] | 714 | struct pci_controller *hose; |
Gavin Shan | 70f942d | 2013-06-20 13:21:12 +0800 | [diff] [blame] | 715 | struct pnv_phb *phb; |
| 716 | u64 frozen_pe_no; |
| 717 | u16 err_type, severity; |
| 718 | long rc; |
Gavin Shan | 7e4e786 | 2014-01-15 13:16:11 +0800 | [diff] [blame] | 719 | int ret = EEH_NEXT_ERR_NONE; |
Gavin Shan | 70f942d | 2013-06-20 13:21:12 +0800 | [diff] [blame] | 720 | |
Gavin Shan | 7cb9d93 | 2013-06-20 18:13:24 +0800 | [diff] [blame] | 721 | /* |
| 722 | * While running here, it's safe to purge the event queue. |
| 723 | * And we should keep the cached OPAL notifier event sychronized |
| 724 | * between the kernel and firmware. |
| 725 | */ |
Gavin Shan | 70f942d | 2013-06-20 13:21:12 +0800 | [diff] [blame] | 726 | eeh_remove_event(NULL); |
Gavin Shan | 7cb9d93 | 2013-06-20 18:13:24 +0800 | [diff] [blame] | 727 | opal_notifier_update_evt(OPAL_EVENT_PCI_ERROR, 0x0ul); |
Gavin Shan | 70f942d | 2013-06-20 13:21:12 +0800 | [diff] [blame] | 728 | |
Gavin Shan | 7e4e786 | 2014-01-15 13:16:11 +0800 | [diff] [blame] | 729 | list_for_each_entry(hose, &hose_list, list_node) { |
Gavin Shan | 70f942d | 2013-06-20 13:21:12 +0800 | [diff] [blame] | 730 | /* |
| 731 | * If the subordinate PCI buses of the PHB has been |
| 732 | * removed, we needn't take care of it any more. |
| 733 | */ |
| 734 | phb = hose->private_data; |
Gavin Shan | 0b9e267 | 2013-06-27 13:46:44 +0800 | [diff] [blame] | 735 | if (phb->eeh_state & PNV_EEH_STATE_REMOVED) |
Gavin Shan | 70f942d | 2013-06-20 13:21:12 +0800 | [diff] [blame] | 736 | continue; |
| 737 | |
| 738 | rc = opal_pci_next_error(phb->opal_id, |
| 739 | &frozen_pe_no, &err_type, &severity); |
| 740 | |
| 741 | /* If OPAL API returns error, we needn't proceed */ |
| 742 | if (rc != OPAL_SUCCESS) { |
Mike Qiu | 2021270 | 2013-08-12 02:15:36 -0400 | [diff] [blame] | 743 | pr_devel("%s: Invalid return value on " |
| 744 | "PHB#%x (0x%lx) from opal_pci_next_error", |
| 745 | __func__, hose->global_number, rc); |
Gavin Shan | 70f942d | 2013-06-20 13:21:12 +0800 | [diff] [blame] | 746 | continue; |
| 747 | } |
| 748 | |
| 749 | /* If the PHB doesn't have error, stop processing */ |
| 750 | if (err_type == OPAL_EEH_NO_ERROR || |
| 751 | severity == OPAL_EEH_SEV_NO_ERROR) { |
Mike Qiu | 2021270 | 2013-08-12 02:15:36 -0400 | [diff] [blame] | 752 | pr_devel("%s: No error found on PHB#%x\n", |
| 753 | __func__, hose->global_number); |
Gavin Shan | 70f942d | 2013-06-20 13:21:12 +0800 | [diff] [blame] | 754 | continue; |
| 755 | } |
| 756 | |
| 757 | /* |
| 758 | * Processing the error. We're expecting the error with |
| 759 | * highest priority reported upon multiple errors on the |
| 760 | * specific PHB. |
| 761 | */ |
Mike Qiu | 2021270 | 2013-08-12 02:15:36 -0400 | [diff] [blame] | 762 | pr_devel("%s: Error (%d, %d, %llu) on PHB#%x\n", |
| 763 | __func__, err_type, severity, |
| 764 | frozen_pe_no, hose->global_number); |
Gavin Shan | 70f942d | 2013-06-20 13:21:12 +0800 | [diff] [blame] | 765 | switch (err_type) { |
| 766 | case OPAL_EEH_IOC_ERROR: |
| 767 | if (severity == OPAL_EEH_SEV_IOC_DEAD) { |
Gavin Shan | 7e4e786 | 2014-01-15 13:16:11 +0800 | [diff] [blame] | 768 | list_for_each_entry(hose, &hose_list, |
| 769 | list_node) { |
Gavin Shan | 70f942d | 2013-06-20 13:21:12 +0800 | [diff] [blame] | 770 | phb = hose->private_data; |
Gavin Shan | 0b9e267 | 2013-06-27 13:46:44 +0800 | [diff] [blame] | 771 | phb->eeh_state |= PNV_EEH_STATE_REMOVED; |
Gavin Shan | 70f942d | 2013-06-20 13:21:12 +0800 | [diff] [blame] | 772 | } |
| 773 | |
Gavin Shan | 56ca4fd | 2013-06-27 13:46:46 +0800 | [diff] [blame] | 774 | pr_err("EEH: dead IOC detected\n"); |
Gavin Shan | 7e4e786 | 2014-01-15 13:16:11 +0800 | [diff] [blame] | 775 | ret = EEH_NEXT_ERR_DEAD_IOC; |
Gavin Shan | 56ca4fd | 2013-06-27 13:46:46 +0800 | [diff] [blame] | 776 | } else if (severity == OPAL_EEH_SEV_INF) { |
| 777 | pr_info("EEH: IOC informative error " |
| 778 | "detected\n"); |
Gavin Shan | 70f942d | 2013-06-20 13:21:12 +0800 | [diff] [blame] | 779 | ioda_eeh_hub_diag(hose); |
Gavin Shan | 7e4e786 | 2014-01-15 13:16:11 +0800 | [diff] [blame] | 780 | ret = EEH_NEXT_ERR_NONE; |
Gavin Shan | 56ca4fd | 2013-06-27 13:46:46 +0800 | [diff] [blame] | 781 | } |
Gavin Shan | 70f942d | 2013-06-20 13:21:12 +0800 | [diff] [blame] | 782 | |
| 783 | break; |
| 784 | case OPAL_EEH_PHB_ERROR: |
| 785 | if (severity == OPAL_EEH_SEV_PHB_DEAD) { |
| 786 | if (ioda_eeh_get_phb_pe(hose, pe)) |
| 787 | break; |
| 788 | |
Gavin Shan | 56ca4fd | 2013-06-27 13:46:46 +0800 | [diff] [blame] | 789 | pr_err("EEH: dead PHB#%x detected\n", |
| 790 | hose->global_number); |
Gavin Shan | 0b9e267 | 2013-06-27 13:46:44 +0800 | [diff] [blame] | 791 | phb->eeh_state |= PNV_EEH_STATE_REMOVED; |
Gavin Shan | 7e4e786 | 2014-01-15 13:16:11 +0800 | [diff] [blame] | 792 | ret = EEH_NEXT_ERR_DEAD_PHB; |
Gavin Shan | 70f942d | 2013-06-20 13:21:12 +0800 | [diff] [blame] | 793 | } else if (severity == OPAL_EEH_SEV_PHB_FENCED) { |
| 794 | if (ioda_eeh_get_phb_pe(hose, pe)) |
| 795 | break; |
| 796 | |
Gavin Shan | 56ca4fd | 2013-06-27 13:46:46 +0800 | [diff] [blame] | 797 | pr_err("EEH: fenced PHB#%x detected\n", |
| 798 | hose->global_number); |
Gavin Shan | 7e4e786 | 2014-01-15 13:16:11 +0800 | [diff] [blame] | 799 | ret = EEH_NEXT_ERR_FENCED_PHB; |
Gavin Shan | 56ca4fd | 2013-06-27 13:46:46 +0800 | [diff] [blame] | 800 | } else if (severity == OPAL_EEH_SEV_INF) { |
| 801 | pr_info("EEH: PHB#%x informative error " |
| 802 | "detected\n", |
| 803 | hose->global_number); |
Gavin Shan | 70f942d | 2013-06-20 13:21:12 +0800 | [diff] [blame] | 804 | ioda_eeh_phb_diag(hose); |
Gavin Shan | 7e4e786 | 2014-01-15 13:16:11 +0800 | [diff] [blame] | 805 | ret = EEH_NEXT_ERR_NONE; |
Gavin Shan | 56ca4fd | 2013-06-27 13:46:46 +0800 | [diff] [blame] | 806 | } |
Gavin Shan | 70f942d | 2013-06-20 13:21:12 +0800 | [diff] [blame] | 807 | |
| 808 | break; |
| 809 | case OPAL_EEH_PE_ERROR: |
Gavin Shan | cb5b242 | 2014-01-15 13:16:13 +0800 | [diff] [blame] | 810 | /* |
| 811 | * If we can't find the corresponding PE, the |
| 812 | * PEEV / PEST would be messy. So we force an |
| 813 | * fenced PHB so that it can be recovered. |
| 814 | */ |
| 815 | if (ioda_eeh_get_pe(hose, frozen_pe_no, pe)) { |
| 816 | if (!ioda_eeh_get_phb_pe(hose, pe)) { |
| 817 | pr_err("EEH: Escalated fenced PHB#%x " |
| 818 | "detected for PE#%llx\n", |
| 819 | hose->global_number, |
| 820 | frozen_pe_no); |
| 821 | ret = EEH_NEXT_ERR_FENCED_PHB; |
| 822 | } else { |
| 823 | ret = EEH_NEXT_ERR_NONE; |
| 824 | } |
| 825 | } else { |
| 826 | pr_err("EEH: Frozen PE#%x on PHB#%x detected\n", |
| 827 | (*pe)->addr, (*pe)->phb->global_number); |
| 828 | ret = EEH_NEXT_ERR_FROZEN_PE; |
| 829 | } |
Gavin Shan | 70f942d | 2013-06-20 13:21:12 +0800 | [diff] [blame] | 830 | |
Gavin Shan | 7e4e786 | 2014-01-15 13:16:11 +0800 | [diff] [blame] | 831 | break; |
| 832 | default: |
| 833 | pr_warn("%s: Unexpected error type %d\n", |
| 834 | __func__, err_type); |
Gavin Shan | 70f942d | 2013-06-20 13:21:12 +0800 | [diff] [blame] | 835 | } |
Gavin Shan | 7e4e786 | 2014-01-15 13:16:11 +0800 | [diff] [blame] | 836 | |
| 837 | /* |
| 838 | * If we have no errors on the specific PHB or only |
| 839 | * informative error there, we continue poking it. |
| 840 | * Otherwise, we need actions to be taken by upper |
| 841 | * layer. |
| 842 | */ |
| 843 | if (ret > EEH_NEXT_ERR_INF) |
| 844 | break; |
Gavin Shan | 70f942d | 2013-06-20 13:21:12 +0800 | [diff] [blame] | 845 | } |
| 846 | |
Gavin Shan | 70f942d | 2013-06-20 13:21:12 +0800 | [diff] [blame] | 847 | return ret; |
| 848 | } |
| 849 | |
Gavin Shan | 8747f36 | 2013-06-20 13:21:06 +0800 | [diff] [blame] | 850 | struct pnv_eeh_ops ioda_eeh_ops = { |
Gavin Shan | 73370c6 | 2013-06-20 13:21:07 +0800 | [diff] [blame] | 851 | .post_init = ioda_eeh_post_init, |
Gavin Shan | eb00598 | 2013-06-20 13:21:08 +0800 | [diff] [blame] | 852 | .set_option = ioda_eeh_set_option, |
Gavin Shan | 8c41a7f | 2013-06-20 13:21:09 +0800 | [diff] [blame] | 853 | .get_state = ioda_eeh_get_state, |
Gavin Shan | 9d5cab0 | 2013-06-20 13:21:10 +0800 | [diff] [blame] | 854 | .reset = ioda_eeh_reset, |
Gavin Shan | bf90dfe | 2013-06-20 13:21:11 +0800 | [diff] [blame] | 855 | .get_log = ioda_eeh_get_log, |
| 856 | .configure_bridge = ioda_eeh_configure_bridge, |
Gavin Shan | 70f942d | 2013-06-20 13:21:12 +0800 | [diff] [blame] | 857 | .next_error = ioda_eeh_next_error |
Gavin Shan | 8747f36 | 2013-06-20 13:21:06 +0800 | [diff] [blame] | 858 | }; |