Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1 | /* |
| 2 | * linux/arch/arm/mm/flush.c |
| 3 | * |
| 4 | * Copyright (C) 1995-2002 Russell King |
| 5 | * |
| 6 | * This program is free software; you can redistribute it and/or modify |
| 7 | * it under the terms of the GNU General Public License version 2 as |
| 8 | * published by the Free Software Foundation. |
| 9 | */ |
| 10 | #include <linux/module.h> |
| 11 | #include <linux/mm.h> |
| 12 | #include <linux/pagemap.h> |
Nicolas Pitre | 39af22a | 2010-12-15 15:14:45 -0500 | [diff] [blame] | 13 | #include <linux/highmem.h> |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 14 | |
| 15 | #include <asm/cacheflush.h> |
Russell King | 46097c7 | 2008-08-10 18:10:19 +0100 | [diff] [blame] | 16 | #include <asm/cachetype.h> |
Nicolas Pitre | 7e5a69e | 2010-03-29 21:46:02 +0100 | [diff] [blame] | 17 | #include <asm/highmem.h> |
Russell King | 2ef7f3d | 2009-11-05 13:29:36 +0000 | [diff] [blame] | 18 | #include <asm/smp_plat.h> |
Russell King | 8d802d2 | 2005-05-10 17:31:43 +0100 | [diff] [blame] | 19 | #include <asm/tlbflush.h> |
| 20 | |
Russell King | 1b2e2b7 | 2006-08-21 17:06:38 +0100 | [diff] [blame] | 21 | #include "mm.h" |
| 22 | |
Russell King | 8d802d2 | 2005-05-10 17:31:43 +0100 | [diff] [blame] | 23 | #ifdef CONFIG_CPU_CACHE_VIPT |
Russell King | d7b6b35 | 2005-09-08 15:32:23 +0100 | [diff] [blame] | 24 | |
Catalin Marinas | 481467d | 2005-09-30 16:07:04 +0100 | [diff] [blame] | 25 | #define ALIAS_FLUSH_START 0xffff4000 |
| 26 | |
Catalin Marinas | 481467d | 2005-09-30 16:07:04 +0100 | [diff] [blame] | 27 | static void flush_pfn_alias(unsigned long pfn, unsigned long vaddr) |
| 28 | { |
| 29 | unsigned long to = ALIAS_FLUSH_START + (CACHE_COLOUR(vaddr) << PAGE_SHIFT); |
Catalin Marinas | 141fa40 | 2006-03-10 22:26:47 +0000 | [diff] [blame] | 30 | const int zero = 0; |
Catalin Marinas | 481467d | 2005-09-30 16:07:04 +0100 | [diff] [blame] | 31 | |
Russell King | ad1ae2f | 2006-12-13 14:34:43 +0000 | [diff] [blame] | 32 | set_pte_ext(TOP_PTE(to), pfn_pte(pfn, PAGE_KERNEL), 0); |
Catalin Marinas | 481467d | 2005-09-30 16:07:04 +0100 | [diff] [blame] | 33 | flush_tlb_kernel_page(to); |
| 34 | |
| 35 | asm( "mcrr p15, 0, %1, %0, c14\n" |
Russell King | df71dfd | 2009-10-24 22:36:36 +0100 | [diff] [blame] | 36 | " mcr p15, 0, %2, c7, c10, 4" |
Catalin Marinas | 481467d | 2005-09-30 16:07:04 +0100 | [diff] [blame] | 37 | : |
Catalin Marinas | 141fa40 | 2006-03-10 22:26:47 +0000 | [diff] [blame] | 38 | : "r" (to), "r" (to + PAGE_SIZE - L1_CACHE_BYTES), "r" (zero) |
Catalin Marinas | 481467d | 2005-09-30 16:07:04 +0100 | [diff] [blame] | 39 | : "cc"); |
| 40 | } |
| 41 | |
Will Deacon | c4e259c | 2010-09-13 16:19:41 +0100 | [diff] [blame] | 42 | static void flush_icache_alias(unsigned long pfn, unsigned long vaddr, unsigned long len) |
| 43 | { |
| 44 | unsigned long colour = CACHE_COLOUR(vaddr); |
| 45 | unsigned long offset = vaddr & (PAGE_SIZE - 1); |
| 46 | unsigned long to; |
| 47 | |
| 48 | set_pte_ext(TOP_PTE(ALIAS_FLUSH_START) + colour, pfn_pte(pfn, PAGE_KERNEL), 0); |
| 49 | to = ALIAS_FLUSH_START + (colour << PAGE_SHIFT) + offset; |
| 50 | flush_tlb_kernel_page(to); |
| 51 | flush_icache_range(to, to + len); |
| 52 | } |
| 53 | |
Russell King | d7b6b35 | 2005-09-08 15:32:23 +0100 | [diff] [blame] | 54 | void flush_cache_mm(struct mm_struct *mm) |
| 55 | { |
| 56 | if (cache_is_vivt()) { |
Russell King | 2f0b192 | 2009-10-25 10:40:02 +0000 | [diff] [blame] | 57 | vivt_flush_cache_mm(mm); |
Russell King | d7b6b35 | 2005-09-08 15:32:23 +0100 | [diff] [blame] | 58 | return; |
| 59 | } |
| 60 | |
| 61 | if (cache_is_vipt_aliasing()) { |
| 62 | asm( "mcr p15, 0, %0, c7, c14, 0\n" |
Russell King | df71dfd | 2009-10-24 22:36:36 +0100 | [diff] [blame] | 63 | " mcr p15, 0, %0, c7, c10, 4" |
Russell King | d7b6b35 | 2005-09-08 15:32:23 +0100 | [diff] [blame] | 64 | : |
| 65 | : "r" (0) |
| 66 | : "cc"); |
| 67 | } |
| 68 | } |
| 69 | |
| 70 | void flush_cache_range(struct vm_area_struct *vma, unsigned long start, unsigned long end) |
| 71 | { |
| 72 | if (cache_is_vivt()) { |
Russell King | 2f0b192 | 2009-10-25 10:40:02 +0000 | [diff] [blame] | 73 | vivt_flush_cache_range(vma, start, end); |
Russell King | d7b6b35 | 2005-09-08 15:32:23 +0100 | [diff] [blame] | 74 | return; |
| 75 | } |
| 76 | |
| 77 | if (cache_is_vipt_aliasing()) { |
| 78 | asm( "mcr p15, 0, %0, c7, c14, 0\n" |
Russell King | df71dfd | 2009-10-24 22:36:36 +0100 | [diff] [blame] | 79 | " mcr p15, 0, %0, c7, c10, 4" |
Russell King | d7b6b35 | 2005-09-08 15:32:23 +0100 | [diff] [blame] | 80 | : |
| 81 | : "r" (0) |
| 82 | : "cc"); |
| 83 | } |
Russell King | 9e95922 | 2009-10-25 13:35:13 +0000 | [diff] [blame] | 84 | |
Russell King | 6060e8d | 2009-10-25 14:12:27 +0000 | [diff] [blame] | 85 | if (vma->vm_flags & VM_EXEC) |
Russell King | 9e95922 | 2009-10-25 13:35:13 +0000 | [diff] [blame] | 86 | __flush_icache_all(); |
Russell King | d7b6b35 | 2005-09-08 15:32:23 +0100 | [diff] [blame] | 87 | } |
| 88 | |
| 89 | void flush_cache_page(struct vm_area_struct *vma, unsigned long user_addr, unsigned long pfn) |
| 90 | { |
| 91 | if (cache_is_vivt()) { |
Russell King | 2f0b192 | 2009-10-25 10:40:02 +0000 | [diff] [blame] | 92 | vivt_flush_cache_page(vma, user_addr, pfn); |
Russell King | d7b6b35 | 2005-09-08 15:32:23 +0100 | [diff] [blame] | 93 | return; |
| 94 | } |
| 95 | |
Russell King | 2df341e | 2009-10-24 22:58:40 +0100 | [diff] [blame] | 96 | if (cache_is_vipt_aliasing()) { |
Russell King | d7b6b35 | 2005-09-08 15:32:23 +0100 | [diff] [blame] | 97 | flush_pfn_alias(pfn, user_addr); |
Russell King | 2df341e | 2009-10-24 22:58:40 +0100 | [diff] [blame] | 98 | __flush_icache_all(); |
| 99 | } |
Russell King | 9e95922 | 2009-10-25 13:35:13 +0000 | [diff] [blame] | 100 | |
| 101 | if (vma->vm_flags & VM_EXEC && icache_is_vivt_asid_tagged()) |
| 102 | __flush_icache_all(); |
Russell King | d7b6b35 | 2005-09-08 15:32:23 +0100 | [diff] [blame] | 103 | } |
Will Deacon | c4e259c | 2010-09-13 16:19:41 +0100 | [diff] [blame] | 104 | |
Russell King | 2ef7f3d | 2009-11-05 13:29:36 +0000 | [diff] [blame] | 105 | #else |
Will Deacon | c4e259c | 2010-09-13 16:19:41 +0100 | [diff] [blame] | 106 | #define flush_pfn_alias(pfn,vaddr) do { } while (0) |
| 107 | #define flush_icache_alias(pfn,vaddr,len) do { } while (0) |
Russell King | 2ef7f3d | 2009-11-05 13:29:36 +0000 | [diff] [blame] | 108 | #endif |
George G. Davis | a188ad2 | 2006-09-02 18:43:20 +0100 | [diff] [blame] | 109 | |
Russell King | 2ef7f3d | 2009-11-05 13:29:36 +0000 | [diff] [blame] | 110 | static void flush_ptrace_access_other(void *args) |
| 111 | { |
| 112 | __flush_icache_all(); |
| 113 | } |
Russell King | 2ef7f3d | 2009-11-05 13:29:36 +0000 | [diff] [blame] | 114 | |
| 115 | static |
George G. Davis | a188ad2 | 2006-09-02 18:43:20 +0100 | [diff] [blame] | 116 | void flush_ptrace_access(struct vm_area_struct *vma, struct page *page, |
Russell King | 2ef7f3d | 2009-11-05 13:29:36 +0000 | [diff] [blame] | 117 | unsigned long uaddr, void *kaddr, unsigned long len) |
George G. Davis | a188ad2 | 2006-09-02 18:43:20 +0100 | [diff] [blame] | 118 | { |
| 119 | if (cache_is_vivt()) { |
Russell King | 2ef7f3d | 2009-11-05 13:29:36 +0000 | [diff] [blame] | 120 | if (cpumask_test_cpu(smp_processor_id(), mm_cpumask(vma->vm_mm))) { |
| 121 | unsigned long addr = (unsigned long)kaddr; |
| 122 | __cpuc_coherent_kern_range(addr, addr + len); |
| 123 | } |
George G. Davis | a188ad2 | 2006-09-02 18:43:20 +0100 | [diff] [blame] | 124 | return; |
| 125 | } |
| 126 | |
| 127 | if (cache_is_vipt_aliasing()) { |
| 128 | flush_pfn_alias(page_to_pfn(page), uaddr); |
Russell King | 2df341e | 2009-10-24 22:58:40 +0100 | [diff] [blame] | 129 | __flush_icache_all(); |
George G. Davis | a188ad2 | 2006-09-02 18:43:20 +0100 | [diff] [blame] | 130 | return; |
| 131 | } |
| 132 | |
Will Deacon | c4e259c | 2010-09-13 16:19:41 +0100 | [diff] [blame] | 133 | /* VIPT non-aliasing D-cache */ |
Russell King | 2ef7f3d | 2009-11-05 13:29:36 +0000 | [diff] [blame] | 134 | if (vma->vm_flags & VM_EXEC) { |
George G. Davis | a188ad2 | 2006-09-02 18:43:20 +0100 | [diff] [blame] | 135 | unsigned long addr = (unsigned long)kaddr; |
Will Deacon | c4e259c | 2010-09-13 16:19:41 +0100 | [diff] [blame] | 136 | if (icache_is_vipt_aliasing()) |
| 137 | flush_icache_alias(page_to_pfn(page), uaddr, len); |
| 138 | else |
| 139 | __cpuc_coherent_kern_range(addr, addr + len); |
Russell King | 2ef7f3d | 2009-11-05 13:29:36 +0000 | [diff] [blame] | 140 | if (cache_ops_need_broadcast()) |
| 141 | smp_call_function(flush_ptrace_access_other, |
| 142 | NULL, 1); |
George G. Davis | a188ad2 | 2006-09-02 18:43:20 +0100 | [diff] [blame] | 143 | } |
| 144 | } |
Russell King | 2ef7f3d | 2009-11-05 13:29:36 +0000 | [diff] [blame] | 145 | |
| 146 | /* |
| 147 | * Copy user data from/to a page which is mapped into a different |
| 148 | * processes address space. Really, we want to allow our "user |
| 149 | * space" model to handle this. |
| 150 | * |
| 151 | * Note that this code needs to run on the current CPU. |
| 152 | */ |
| 153 | void copy_to_user_page(struct vm_area_struct *vma, struct page *page, |
| 154 | unsigned long uaddr, void *dst, const void *src, |
| 155 | unsigned long len) |
| 156 | { |
| 157 | #ifdef CONFIG_SMP |
| 158 | preempt_disable(); |
Russell King | 8d802d2 | 2005-05-10 17:31:43 +0100 | [diff] [blame] | 159 | #endif |
Russell King | 2ef7f3d | 2009-11-05 13:29:36 +0000 | [diff] [blame] | 160 | memcpy(dst, src, len); |
| 161 | flush_ptrace_access(vma, page, uaddr, dst, len); |
| 162 | #ifdef CONFIG_SMP |
| 163 | preempt_enable(); |
| 164 | #endif |
| 165 | } |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 166 | |
Russell King | 8830f04 | 2005-06-20 09:51:03 +0100 | [diff] [blame] | 167 | void __flush_dcache_page(struct address_space *mapping, struct page *page) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 168 | { |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 169 | /* |
| 170 | * Writeback any data associated with the kernel mapping of this |
| 171 | * page. This ensures that data in the physical page is mutually |
| 172 | * coherent with the kernels mapping. |
| 173 | */ |
Nicolas Pitre | 7e5a69e | 2010-03-29 21:46:02 +0100 | [diff] [blame] | 174 | if (!PageHighMem(page)) { |
| 175 | __cpuc_flush_dcache_area(page_address(page), PAGE_SIZE); |
| 176 | } else { |
| 177 | void *addr = kmap_high_get(page); |
| 178 | if (addr) { |
| 179 | __cpuc_flush_dcache_area(addr, PAGE_SIZE); |
| 180 | kunmap_high(page); |
| 181 | } else if (cache_is_vipt()) { |
Nicolas Pitre | 39af22a | 2010-12-15 15:14:45 -0500 | [diff] [blame] | 182 | /* unmapped pages might still be cached */ |
| 183 | addr = kmap_atomic(page); |
Nicolas Pitre | 7e5a69e | 2010-03-29 21:46:02 +0100 | [diff] [blame] | 184 | __cpuc_flush_dcache_area(addr, PAGE_SIZE); |
Nicolas Pitre | 39af22a | 2010-12-15 15:14:45 -0500 | [diff] [blame] | 185 | kunmap_atomic(addr); |
Nicolas Pitre | 7e5a69e | 2010-03-29 21:46:02 +0100 | [diff] [blame] | 186 | } |
| 187 | } |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 188 | |
| 189 | /* |
Russell King | 8830f04 | 2005-06-20 09:51:03 +0100 | [diff] [blame] | 190 | * If this is a page cache page, and we have an aliasing VIPT cache, |
| 191 | * we only need to do one flush - which would be at the relevant |
Russell King | 8d802d2 | 2005-05-10 17:31:43 +0100 | [diff] [blame] | 192 | * userspace colour, which is congruent with page->index. |
| 193 | */ |
Russell King | f91fb05 | 2009-10-24 23:05:34 +0100 | [diff] [blame] | 194 | if (mapping && cache_is_vipt_aliasing()) |
Russell King | 8830f04 | 2005-06-20 09:51:03 +0100 | [diff] [blame] | 195 | flush_pfn_alias(page_to_pfn(page), |
| 196 | page->index << PAGE_CACHE_SHIFT); |
| 197 | } |
| 198 | |
| 199 | static void __flush_dcache_aliases(struct address_space *mapping, struct page *page) |
| 200 | { |
| 201 | struct mm_struct *mm = current->active_mm; |
| 202 | struct vm_area_struct *mpnt; |
| 203 | struct prio_tree_iter iter; |
| 204 | pgoff_t pgoff; |
Russell King | 8d802d2 | 2005-05-10 17:31:43 +0100 | [diff] [blame] | 205 | |
| 206 | /* |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 207 | * There are possible user space mappings of this page: |
| 208 | * - VIVT cache: we need to also write back and invalidate all user |
| 209 | * data in the current VM view associated with this page. |
| 210 | * - aliasing VIPT: we only need to find one mapping of this page. |
| 211 | */ |
| 212 | pgoff = page->index << (PAGE_CACHE_SHIFT - PAGE_SHIFT); |
| 213 | |
| 214 | flush_dcache_mmap_lock(mapping); |
| 215 | vma_prio_tree_foreach(mpnt, &iter, &mapping->i_mmap, pgoff, pgoff) { |
| 216 | unsigned long offset; |
| 217 | |
| 218 | /* |
| 219 | * If this VMA is not in our MM, we can ignore it. |
| 220 | */ |
| 221 | if (mpnt->vm_mm != mm) |
| 222 | continue; |
| 223 | if (!(mpnt->vm_flags & VM_MAYSHARE)) |
| 224 | continue; |
| 225 | offset = (pgoff - mpnt->vm_pgoff) << PAGE_SHIFT; |
| 226 | flush_cache_page(mpnt, mpnt->vm_start + offset, page_to_pfn(page)); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 227 | } |
| 228 | flush_dcache_mmap_unlock(mapping); |
| 229 | } |
| 230 | |
Catalin Marinas | 6012191 | 2010-09-13 15:58:06 +0100 | [diff] [blame] | 231 | #if __LINUX_ARM_ARCH__ >= 6 |
| 232 | void __sync_icache_dcache(pte_t pteval) |
| 233 | { |
| 234 | unsigned long pfn; |
| 235 | struct page *page; |
| 236 | struct address_space *mapping; |
| 237 | |
| 238 | if (!pte_present_user(pteval)) |
| 239 | return; |
| 240 | if (cache_is_vipt_nonaliasing() && !pte_exec(pteval)) |
| 241 | /* only flush non-aliasing VIPT caches for exec mappings */ |
| 242 | return; |
| 243 | pfn = pte_pfn(pteval); |
| 244 | if (!pfn_valid(pfn)) |
| 245 | return; |
| 246 | |
| 247 | page = pfn_to_page(pfn); |
| 248 | if (cache_is_vipt_aliasing()) |
| 249 | mapping = page_mapping(page); |
| 250 | else |
| 251 | mapping = NULL; |
| 252 | |
| 253 | if (!test_and_set_bit(PG_dcache_clean, &page->flags)) |
| 254 | __flush_dcache_page(mapping, page); |
saeed bishara | 8373dc3 | 2011-05-16 15:41:15 +0100 | [diff] [blame] | 255 | |
| 256 | if (pte_exec(pteval)) |
Catalin Marinas | 6012191 | 2010-09-13 15:58:06 +0100 | [diff] [blame] | 257 | __flush_icache_all(); |
| 258 | } |
| 259 | #endif |
| 260 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 261 | /* |
| 262 | * Ensure cache coherency between kernel mapping and userspace mapping |
| 263 | * of this page. |
| 264 | * |
| 265 | * We have three cases to consider: |
| 266 | * - VIPT non-aliasing cache: fully coherent so nothing required. |
| 267 | * - VIVT: fully aliasing, so we need to handle every alias in our |
| 268 | * current VM view. |
| 269 | * - VIPT aliasing: need to handle one alias in our current VM view. |
| 270 | * |
| 271 | * If we need to handle aliasing: |
| 272 | * If the page only exists in the page cache and there are no user |
| 273 | * space mappings, we can be lazy and remember that we may have dirty |
| 274 | * kernel cache lines for later. Otherwise, we assume we have |
| 275 | * aliasing mappings. |
Russell King | df2f5e7 | 2005-11-30 16:02:54 +0000 | [diff] [blame] | 276 | * |
saeed bishara | 31bee4c | 2011-05-16 11:25:21 +0100 | [diff] [blame] | 277 | * Note that we disable the lazy flush for SMP configurations where |
| 278 | * the cache maintenance operations are not automatically broadcasted. |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 279 | */ |
| 280 | void flush_dcache_page(struct page *page) |
| 281 | { |
Russell King | 421fe93 | 2009-10-25 10:23:04 +0000 | [diff] [blame] | 282 | struct address_space *mapping; |
| 283 | |
| 284 | /* |
| 285 | * The zero page is never written to, so never has any dirty |
| 286 | * cache lines, and therefore never needs to be flushed. |
| 287 | */ |
| 288 | if (page == ZERO_PAGE(0)) |
| 289 | return; |
| 290 | |
| 291 | mapping = page_mapping(page); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 292 | |
Catalin Marinas | 85848dd | 2010-09-13 15:58:37 +0100 | [diff] [blame] | 293 | if (!cache_ops_need_broadcast() && |
| 294 | mapping && !mapping_mapped(mapping)) |
Catalin Marinas | c017780 | 2010-09-13 15:57:36 +0100 | [diff] [blame] | 295 | clear_bit(PG_dcache_clean, &page->flags); |
Catalin Marinas | 85848dd | 2010-09-13 15:58:37 +0100 | [diff] [blame] | 296 | else { |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 297 | __flush_dcache_page(mapping, page); |
Russell King | 8830f04 | 2005-06-20 09:51:03 +0100 | [diff] [blame] | 298 | if (mapping && cache_is_vivt()) |
| 299 | __flush_dcache_aliases(mapping, page); |
Catalin Marinas | 826cbda | 2008-06-13 10:28:36 +0100 | [diff] [blame] | 300 | else if (mapping) |
| 301 | __flush_icache_all(); |
Catalin Marinas | c017780 | 2010-09-13 15:57:36 +0100 | [diff] [blame] | 302 | set_bit(PG_dcache_clean, &page->flags); |
Russell King | 8830f04 | 2005-06-20 09:51:03 +0100 | [diff] [blame] | 303 | } |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 304 | } |
| 305 | EXPORT_SYMBOL(flush_dcache_page); |
Russell King | 6020dff | 2006-12-30 23:17:40 +0000 | [diff] [blame] | 306 | |
| 307 | /* |
| 308 | * Flush an anonymous page so that users of get_user_pages() |
| 309 | * can safely access the data. The expected sequence is: |
| 310 | * |
| 311 | * get_user_pages() |
| 312 | * -> flush_anon_page |
| 313 | * memcpy() to/from page |
| 314 | * if written to page, flush_dcache_page() |
| 315 | */ |
| 316 | void __flush_anon_page(struct vm_area_struct *vma, struct page *page, unsigned long vmaddr) |
| 317 | { |
| 318 | unsigned long pfn; |
| 319 | |
| 320 | /* VIPT non-aliasing caches need do nothing */ |
| 321 | if (cache_is_vipt_nonaliasing()) |
| 322 | return; |
| 323 | |
| 324 | /* |
| 325 | * Write back and invalidate userspace mapping. |
| 326 | */ |
| 327 | pfn = page_to_pfn(page); |
| 328 | if (cache_is_vivt()) { |
| 329 | flush_cache_page(vma, vmaddr, pfn); |
| 330 | } else { |
| 331 | /* |
| 332 | * For aliasing VIPT, we can flush an alias of the |
| 333 | * userspace address only. |
| 334 | */ |
| 335 | flush_pfn_alias(pfn, vmaddr); |
Russell King | 2df341e | 2009-10-24 22:58:40 +0100 | [diff] [blame] | 336 | __flush_icache_all(); |
Russell King | 6020dff | 2006-12-30 23:17:40 +0000 | [diff] [blame] | 337 | } |
| 338 | |
| 339 | /* |
| 340 | * Invalidate kernel mapping. No data should be contained |
| 341 | * in this mapping of the page. FIXME: this is overkill |
| 342 | * since we actually ask for a write-back and invalidate. |
| 343 | */ |
Russell King | 2c9b9c8 | 2009-11-26 12:56:21 +0000 | [diff] [blame] | 344 | __cpuc_flush_dcache_area(page_address(page), PAGE_SIZE); |
Russell King | 6020dff | 2006-12-30 23:17:40 +0000 | [diff] [blame] | 345 | } |