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gerrit-public.fairphone.software / kernel / msm-4.9 / 9fc114c5d7af6cfb72a2d983e16b83161716d6d0 / . / sound / soc / codecs / rt5645.c
blob: 5f5d8adf6f42245772b211d965b5506657e40e49 [file] [log] [blame]
Oder Chiou1319b2f2014-04-28 19:59:10 +0800[diff] [blame]1/*
2 * rt5645.c -- RT5645 ALSA SoC audio codec driver
3 *
4 * Copyright 2013 Realtek Semiconductor Corp.
5 * Author: Bard Liao <bardliao@realtek.com>
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
10 */
11
12#include <linux/module.h>
13#include <linux/moduleparam.h>
14#include <linux/init.h>
15#include <linux/delay.h>
16#include <linux/pm.h>
17#include <linux/i2c.h>
18#include <linux/platform_device.h>
19#include <linux/spi/spi.h>
Oder Chiouf3fa1bb2014-09-19 19:15:45 +0800[diff] [blame]20#include <linux/gpio.h>
Fang, Yang Abaf2a0e2015-04-27 15:54:30 -0700[diff] [blame]21#include <linux/gpio/consumer.h>
Fang, Yang A3168c202015-04-23 16:35:17 -0700[diff] [blame]22#include <linux/acpi.h>
Fang, Yang A78c34fd2015-04-24 17:50:54 -0700[diff] [blame]23#include <linux/dmi.h>
Koro Chen9fc114c2015-07-17 11:33:12 +0800[diff] [blame^]24#include <linux/regulator/consumer.h>
Oder Chiou1319b2f2014-04-28 19:59:10 +0800[diff] [blame]25#include <sound/core.h>
26#include <sound/pcm.h>
27#include <sound/pcm_params.h>
28#include <sound/jack.h>
29#include <sound/soc.h>
30#include <sound/soc-dapm.h>
31#include <sound/initval.h>
32#include <sound/tlv.h>
33
Oder Chiou49ef7922014-05-20 15:01:53 +0800[diff] [blame]34#include "rl6231.h"
Oder Chiou1319b2f2014-04-28 19:59:10 +0800[diff] [blame]35#include "rt5645.h"
36
37#define RT5645_DEVICE_ID 0x6308
Bard Liao5c4ca992015-01-21 20:50:15 +0800[diff] [blame]38#define RT5650_DEVICE_ID 0x6419
Oder Chiou1319b2f2014-04-28 19:59:10 +0800[diff] [blame]39
40#define RT5645_PR_RANGE_BASE (0xff + 1)
41#define RT5645_PR_SPACING 0x100
42
43#define RT5645_PR_BASE (RT5645_PR_RANGE_BASE + (0 * RT5645_PR_SPACING))
44
45static const struct regmap_range_cfg rt5645_ranges[] = {
46 {
47 .name = "PR",
48 .range_min = RT5645_PR_BASE,
49 .range_max = RT5645_PR_BASE + 0xf8,
50 .selector_reg = RT5645_PRIV_INDEX,
51 .selector_mask = 0xff,
52 .selector_shift = 0x0,
53 .window_start = RT5645_PRIV_DATA,
54 .window_len = 0x1,
55 },
56};
57
58static const struct reg_default init_list[] = {
59 {RT5645_PR_BASE + 0x3d, 0x3600},
Oder Chiou4809b962014-05-08 14:47:36 +0800[diff] [blame]60 {RT5645_PR_BASE + 0x1c, 0xfd20},
61 {RT5645_PR_BASE + 0x20, 0x611f},
62 {RT5645_PR_BASE + 0x21, 0x4040},
63 {RT5645_PR_BASE + 0x23, 0x0004},
Oder Chiou1319b2f2014-04-28 19:59:10 +0800[diff] [blame]64};
65#define RT5645_INIT_REG_LEN ARRAY_SIZE(init_list)
66
Bard Liao5c4ca992015-01-21 20:50:15 +0800[diff] [blame]67static const struct reg_default rt5650_init_list[] = {
68 {0xf6, 0x0100},
69};
70
Oder Chiou1319b2f2014-04-28 19:59:10 +0800[diff] [blame]71static const struct reg_default rt5645_reg[] = {
72 { 0x00, 0x0000 },
73 { 0x01, 0xc8c8 },
74 { 0x02, 0xc8c8 },
75 { 0x03, 0xc8c8 },
76 { 0x0a, 0x0002 },
77 { 0x0b, 0x2827 },
78 { 0x0c, 0xe000 },
79 { 0x0d, 0x0000 },
80 { 0x0e, 0x0000 },
81 { 0x0f, 0x0808 },
82 { 0x14, 0x3333 },
83 { 0x16, 0x4b00 },
84 { 0x18, 0x018b },
85 { 0x19, 0xafaf },
86 { 0x1a, 0xafaf },
87 { 0x1b, 0x0001 },
88 { 0x1c, 0x2f2f },
89 { 0x1d, 0x2f2f },
90 { 0x1e, 0x0000 },
91 { 0x20, 0x0000 },
92 { 0x27, 0x7060 },
93 { 0x28, 0x7070 },
94 { 0x29, 0x8080 },
95 { 0x2a, 0x5656 },
96 { 0x2b, 0x5454 },
97 { 0x2c, 0xaaa0 },
Bard Liao5c4ca992015-01-21 20:50:15 +0800[diff] [blame]98 { 0x2d, 0x0000 },
Oder Chiou1319b2f2014-04-28 19:59:10 +0800[diff] [blame]99 { 0x2f, 0x1002 },
100 { 0x31, 0x5000 },
101 { 0x32, 0x0000 },
102 { 0x33, 0x0000 },
103 { 0x34, 0x0000 },
104 { 0x35, 0x0000 },
105 { 0x3b, 0x0000 },
106 { 0x3c, 0x007f },
107 { 0x3d, 0x0000 },
108 { 0x3e, 0x007f },
109 { 0x3f, 0x0000 },
110 { 0x40, 0x001f },
111 { 0x41, 0x0000 },
112 { 0x42, 0x001f },
113 { 0x45, 0x6000 },
114 { 0x46, 0x003e },
115 { 0x47, 0x003e },
116 { 0x48, 0xf807 },
117 { 0x4a, 0x0004 },
118 { 0x4d, 0x0000 },
119 { 0x4e, 0x0000 },
120 { 0x4f, 0x01ff },
121 { 0x50, 0x0000 },
122 { 0x51, 0x0000 },
123 { 0x52, 0x01ff },
124 { 0x53, 0xf000 },
125 { 0x56, 0x0111 },
126 { 0x57, 0x0064 },
127 { 0x58, 0xef0e },
128 { 0x59, 0xf0f0 },
129 { 0x5a, 0xef0e },
130 { 0x5b, 0xf0f0 },
131 { 0x5c, 0xef0e },
132 { 0x5d, 0xf0f0 },
133 { 0x5e, 0xf000 },
134 { 0x5f, 0x0000 },
135 { 0x61, 0x0300 },
136 { 0x62, 0x0000 },
137 { 0x63, 0x00c2 },
138 { 0x64, 0x0000 },
139 { 0x65, 0x0000 },
140 { 0x66, 0x0000 },
141 { 0x6a, 0x0000 },
142 { 0x6c, 0x0aaa },
143 { 0x70, 0x8000 },
144 { 0x71, 0x8000 },
145 { 0x72, 0x8000 },
146 { 0x73, 0x7770 },
147 { 0x74, 0x3e00 },
148 { 0x75, 0x2409 },
149 { 0x76, 0x000a },
150 { 0x77, 0x0c00 },
151 { 0x78, 0x0000 },
Fang, Yang Adf078d22014-10-28 18:36:36 -0300[diff] [blame]152 { 0x79, 0x0123 },
Oder Chiou1319b2f2014-04-28 19:59:10 +0800[diff] [blame]153 { 0x80, 0x0000 },
154 { 0x81, 0x0000 },
155 { 0x82, 0x0000 },
156 { 0x83, 0x0000 },
157 { 0x84, 0x0000 },
158 { 0x85, 0x0000 },
159 { 0x8a, 0x0000 },
160 { 0x8e, 0x0004 },
161 { 0x8f, 0x1100 },
162 { 0x90, 0x0646 },
163 { 0x91, 0x0c06 },
164 { 0x93, 0x0000 },
165 { 0x94, 0x0200 },
166 { 0x95, 0x0000 },
167 { 0x9a, 0x2184 },
168 { 0x9b, 0x010a },
169 { 0x9c, 0x0aea },
170 { 0x9d, 0x000c },
171 { 0x9e, 0x0400 },
172 { 0xa0, 0xa0a8 },
173 { 0xa1, 0x0059 },
174 { 0xa2, 0x0001 },
175 { 0xae, 0x6000 },
176 { 0xaf, 0x0000 },
177 { 0xb0, 0x6000 },
178 { 0xb1, 0x0000 },
179 { 0xb2, 0x0000 },
180 { 0xb3, 0x001f },
181 { 0xb4, 0x020c },
182 { 0xb5, 0x1f00 },
183 { 0xb6, 0x0000 },
184 { 0xbb, 0x0000 },
185 { 0xbc, 0x0000 },
186 { 0xbd, 0x0000 },
187 { 0xbe, 0x0000 },
188 { 0xbf, 0x3100 },
189 { 0xc0, 0x0000 },
190 { 0xc1, 0x0000 },
191 { 0xc2, 0x0000 },
192 { 0xc3, 0x2000 },
193 { 0xcd, 0x0000 },
194 { 0xce, 0x0000 },
195 { 0xcf, 0x1813 },
196 { 0xd0, 0x0690 },
197 { 0xd1, 0x1c17 },
198 { 0xd3, 0xb320 },
199 { 0xd4, 0x0000 },
200 { 0xd6, 0x0400 },
201 { 0xd9, 0x0809 },
202 { 0xda, 0x0000 },
203 { 0xdb, 0x0003 },
204 { 0xdc, 0x0049 },
205 { 0xdd, 0x001b },
Bard Liao5c4ca992015-01-21 20:50:15 +0800[diff] [blame]206 { 0xdf, 0x0008 },
207 { 0xe0, 0x4000 },
Oder Chiou1319b2f2014-04-28 19:59:10 +0800[diff] [blame]208 { 0xe6, 0x8000 },
209 { 0xe7, 0x0200 },
210 { 0xec, 0xb300 },
211 { 0xed, 0x0000 },
212 { 0xf0, 0x001f },
213 { 0xf1, 0x020c },
214 { 0xf2, 0x1f00 },
215 { 0xf3, 0x0000 },
216 { 0xf4, 0x4000 },
217 { 0xf8, 0x0000 },
218 { 0xf9, 0x0000 },
219 { 0xfa, 0x2060 },
220 { 0xfb, 0x4040 },
221 { 0xfc, 0x0000 },
222 { 0xfd, 0x0002 },
223 { 0xfe, 0x10ec },
224 { 0xff, 0x6308 },
225};
226
Koro Chen9fc114c2015-07-17 11:33:12 +0800[diff] [blame^]227static const char *const rt5645_supply_names[] = {
228 "avdd",
229 "cpvdd",
230};
231
232struct rt5645_priv {
233 struct snd_soc_codec *codec;
234 struct rt5645_platform_data pdata;
235 struct regmap *regmap;
236 struct i2c_client *i2c;
237 struct gpio_desc *gpiod_hp_det;
238 struct snd_soc_jack *hp_jack;
239 struct snd_soc_jack *mic_jack;
240 struct snd_soc_jack *btn_jack;
241 struct delayed_work jack_detect_work;
242 struct regulator_bulk_data supplies[ARRAY_SIZE(rt5645_supply_names)];
243
244 int codec_type;
245 int sysclk;
246 int sysclk_src;
247 int lrck[RT5645_AIFS];
248 int bclk[RT5645_AIFS];
249 int master[RT5645_AIFS];
250
251 int pll_src;
252 int pll_in;
253 int pll_out;
254
255 int jack_type;
256 bool en_button_func;
257};
258
Oder Chiou1319b2f2014-04-28 19:59:10 +0800[diff] [blame]259static int rt5645_reset(struct snd_soc_codec *codec)
260{
261 return snd_soc_write(codec, RT5645_RESET, 0);
262}
263
264static bool rt5645_volatile_register(struct device *dev, unsigned int reg)
265{
266 int i;
267
268 for (i = 0; i < ARRAY_SIZE(rt5645_ranges); i++) {
269 if (reg >= rt5645_ranges[i].range_min &&
270 reg <= rt5645_ranges[i].range_max) {
271 return true;
272 }
273 }
274
275 switch (reg) {
276 case RT5645_RESET:
277 case RT5645_PRIV_DATA:
278 case RT5645_IN1_CTRL1:
279 case RT5645_IN1_CTRL2:
280 case RT5645_IN1_CTRL3:
281 case RT5645_A_JD_CTRL1:
282 case RT5645_ADC_EQ_CTRL1:
283 case RT5645_EQ_CTRL1:
284 case RT5645_ALC_CTRL_1:
285 case RT5645_IRQ_CTRL2:
286 case RT5645_IRQ_CTRL3:
287 case RT5645_INT_IRQ_ST:
288 case RT5645_IL_CMD:
Bard Liao5c4ca992015-01-21 20:50:15 +0800[diff] [blame]289 case RT5650_4BTN_IL_CMD1:
Oder Chiou1319b2f2014-04-28 19:59:10 +0800[diff] [blame]290 case RT5645_VENDOR_ID:
291 case RT5645_VENDOR_ID1:
292 case RT5645_VENDOR_ID2:
Oder Chiou71bfa9b2014-05-08 15:42:37 +0800[diff] [blame]293 return true;
Oder Chiou1319b2f2014-04-28 19:59:10 +0800[diff] [blame]294 default:
Oder Chiou71bfa9b2014-05-08 15:42:37 +0800[diff] [blame]295 return false;
Oder Chiou1319b2f2014-04-28 19:59:10 +0800[diff] [blame]296 }
297}
298
299static bool rt5645_readable_register(struct device *dev, unsigned int reg)
300{
301 int i;
302
303 for (i = 0; i < ARRAY_SIZE(rt5645_ranges); i++) {
304 if (reg >= rt5645_ranges[i].range_min &&
305 reg <= rt5645_ranges[i].range_max) {
306 return true;
307 }
308 }
309
310 switch (reg) {
311 case RT5645_RESET:
312 case RT5645_SPK_VOL:
313 case RT5645_HP_VOL:
314 case RT5645_LOUT1:
315 case RT5645_IN1_CTRL1:
316 case RT5645_IN1_CTRL2:
317 case RT5645_IN1_CTRL3:
318 case RT5645_IN2_CTRL:
319 case RT5645_INL1_INR1_VOL:
320 case RT5645_SPK_FUNC_LIM:
321 case RT5645_ADJ_HPF_CTRL:
322 case RT5645_DAC1_DIG_VOL:
323 case RT5645_DAC2_DIG_VOL:
324 case RT5645_DAC_CTRL:
325 case RT5645_STO1_ADC_DIG_VOL:
326 case RT5645_MONO_ADC_DIG_VOL:
327 case RT5645_ADC_BST_VOL1:
328 case RT5645_ADC_BST_VOL2:
329 case RT5645_STO1_ADC_MIXER:
330 case RT5645_MONO_ADC_MIXER:
331 case RT5645_AD_DA_MIXER:
332 case RT5645_STO_DAC_MIXER:
333 case RT5645_MONO_DAC_MIXER:
334 case RT5645_DIG_MIXER:
Bard Liao5c4ca992015-01-21 20:50:15 +0800[diff] [blame]335 case RT5650_A_DAC_SOUR:
Oder Chiou1319b2f2014-04-28 19:59:10 +0800[diff] [blame]336 case RT5645_DIG_INF1_DATA:
337 case RT5645_PDM_OUT_CTRL:
338 case RT5645_REC_L1_MIXER:
339 case RT5645_REC_L2_MIXER:
340 case RT5645_REC_R1_MIXER:
341 case RT5645_REC_R2_MIXER:
342 case RT5645_HPMIXL_CTRL:
343 case RT5645_HPOMIXL_CTRL:
344 case RT5645_HPMIXR_CTRL:
345 case RT5645_HPOMIXR_CTRL:
346 case RT5645_HPO_MIXER:
347 case RT5645_SPK_L_MIXER:
348 case RT5645_SPK_R_MIXER:
349 case RT5645_SPO_MIXER:
350 case RT5645_SPO_CLSD_RATIO:
351 case RT5645_OUT_L1_MIXER:
352 case RT5645_OUT_R1_MIXER:
353 case RT5645_OUT_L_GAIN1:
354 case RT5645_OUT_L_GAIN2:
355 case RT5645_OUT_R_GAIN1:
356 case RT5645_OUT_R_GAIN2:
357 case RT5645_LOUT_MIXER:
358 case RT5645_HAPTIC_CTRL1:
359 case RT5645_HAPTIC_CTRL2:
360 case RT5645_HAPTIC_CTRL3:
361 case RT5645_HAPTIC_CTRL4:
362 case RT5645_HAPTIC_CTRL5:
363 case RT5645_HAPTIC_CTRL6:
364 case RT5645_HAPTIC_CTRL7:
365 case RT5645_HAPTIC_CTRL8:
366 case RT5645_HAPTIC_CTRL9:
367 case RT5645_HAPTIC_CTRL10:
368 case RT5645_PWR_DIG1:
369 case RT5645_PWR_DIG2:
370 case RT5645_PWR_ANLG1:
371 case RT5645_PWR_ANLG2:
372 case RT5645_PWR_MIXER:
373 case RT5645_PWR_VOL:
374 case RT5645_PRIV_INDEX:
375 case RT5645_PRIV_DATA:
376 case RT5645_I2S1_SDP:
377 case RT5645_I2S2_SDP:
378 case RT5645_ADDA_CLK1:
379 case RT5645_ADDA_CLK2:
380 case RT5645_DMIC_CTRL1:
381 case RT5645_DMIC_CTRL2:
382 case RT5645_TDM_CTRL_1:
383 case RT5645_TDM_CTRL_2:
Fang, Yang Adf078d22014-10-28 18:36:36 -0300[diff] [blame]384 case RT5645_TDM_CTRL_3:
Oder Chiou1fcb76d2015-06-10 14:34:29 +0800[diff] [blame]385 case RT5650_TDM_CTRL_4:
Oder Chiou1319b2f2014-04-28 19:59:10 +0800[diff] [blame]386 case RT5645_GLB_CLK:
387 case RT5645_PLL_CTRL1:
388 case RT5645_PLL_CTRL2:
389 case RT5645_ASRC_1:
390 case RT5645_ASRC_2:
391 case RT5645_ASRC_3:
392 case RT5645_ASRC_4:
393 case RT5645_DEPOP_M1:
394 case RT5645_DEPOP_M2:
395 case RT5645_DEPOP_M3:
396 case RT5645_MICBIAS:
397 case RT5645_A_JD_CTRL1:
398 case RT5645_VAD_CTRL4:
399 case RT5645_CLSD_OUT_CTRL:
400 case RT5645_ADC_EQ_CTRL1:
401 case RT5645_ADC_EQ_CTRL2:
402 case RT5645_EQ_CTRL1:
403 case RT5645_EQ_CTRL2:
404 case RT5645_ALC_CTRL_1:
405 case RT5645_ALC_CTRL_2:
406 case RT5645_ALC_CTRL_3:
407 case RT5645_ALC_CTRL_4:
408 case RT5645_ALC_CTRL_5:
409 case RT5645_JD_CTRL:
410 case RT5645_IRQ_CTRL1:
411 case RT5645_IRQ_CTRL2:
412 case RT5645_IRQ_CTRL3:
413 case RT5645_INT_IRQ_ST:
414 case RT5645_GPIO_CTRL1:
415 case RT5645_GPIO_CTRL2:
416 case RT5645_GPIO_CTRL3:
417 case RT5645_BASS_BACK:
418 case RT5645_MP3_PLUS1:
419 case RT5645_MP3_PLUS2:
420 case RT5645_ADJ_HPF1:
421 case RT5645_ADJ_HPF2:
422 case RT5645_HP_CALIB_AMP_DET:
423 case RT5645_SV_ZCD1:
424 case RT5645_SV_ZCD2:
425 case RT5645_IL_CMD:
426 case RT5645_IL_CMD2:
427 case RT5645_IL_CMD3:
Bard Liao5c4ca992015-01-21 20:50:15 +0800[diff] [blame]428 case RT5650_4BTN_IL_CMD1:
429 case RT5650_4BTN_IL_CMD2:
Oder Chiou1319b2f2014-04-28 19:59:10 +0800[diff] [blame]430 case RT5645_DRC1_HL_CTRL1:
431 case RT5645_DRC2_HL_CTRL1:
432 case RT5645_ADC_MONO_HP_CTRL1:
433 case RT5645_ADC_MONO_HP_CTRL2:
434 case RT5645_DRC2_CTRL1:
435 case RT5645_DRC2_CTRL2:
436 case RT5645_DRC2_CTRL3:
437 case RT5645_DRC2_CTRL4:
438 case RT5645_DRC2_CTRL5:
439 case RT5645_JD_CTRL3:
440 case RT5645_JD_CTRL4:
441 case RT5645_GEN_CTRL1:
442 case RT5645_GEN_CTRL2:
443 case RT5645_GEN_CTRL3:
444 case RT5645_VENDOR_ID:
445 case RT5645_VENDOR_ID1:
446 case RT5645_VENDOR_ID2:
Oder Chiou71bfa9b2014-05-08 15:42:37 +0800[diff] [blame]447 return true;
Oder Chiou1319b2f2014-04-28 19:59:10 +0800[diff] [blame]448 default:
Oder Chiou71bfa9b2014-05-08 15:42:37 +0800[diff] [blame]449 return false;
Oder Chiou1319b2f2014-04-28 19:59:10 +0800[diff] [blame]450 }
451}
452
453static const DECLARE_TLV_DB_SCALE(out_vol_tlv, -4650, 150, 0);
Bard Liao177e1e12015-04-30 18:18:47 +0800[diff] [blame]454static const DECLARE_TLV_DB_SCALE(dac_vol_tlv, -6525, 75, 0);
Oder Chiou1319b2f2014-04-28 19:59:10 +0800[diff] [blame]455static const DECLARE_TLV_DB_SCALE(in_vol_tlv, -3450, 150, 0);
Bard Liao177e1e12015-04-30 18:18:47 +0800[diff] [blame]456static const DECLARE_TLV_DB_SCALE(adc_vol_tlv, -1725, 75, 0);
Oder Chiou1319b2f2014-04-28 19:59:10 +0800[diff] [blame]457static const DECLARE_TLV_DB_SCALE(adc_bst_tlv, 0, 1200, 0);
458
459/* {0, +20, +24, +30, +35, +40, +44, +50, +52} dB */
460static unsigned int bst_tlv[] = {
461 TLV_DB_RANGE_HEAD(7),
462 0, 0, TLV_DB_SCALE_ITEM(0, 0, 0),
463 1, 1, TLV_DB_SCALE_ITEM(2000, 0, 0),
464 2, 2, TLV_DB_SCALE_ITEM(2400, 0, 0),
465 3, 5, TLV_DB_SCALE_ITEM(3000, 500, 0),
466 6, 6, TLV_DB_SCALE_ITEM(4400, 0, 0),
467 7, 7, TLV_DB_SCALE_ITEM(5000, 0, 0),
468 8, 8, TLV_DB_SCALE_ITEM(5200, 0, 0),
469};
470
Oder Chiou1319b2f2014-04-28 19:59:10 +0800[diff] [blame]471static const struct snd_kcontrol_new rt5645_snd_controls[] = {
472 /* Speaker Output Volume */
473 SOC_DOUBLE("Speaker Channel Switch", RT5645_SPK_VOL,
474 RT5645_VOL_L_SFT, RT5645_VOL_R_SFT, 1, 1),
475 SOC_DOUBLE_TLV("Speaker Playback Volume", RT5645_SPK_VOL,
476 RT5645_L_VOL_SFT, RT5645_R_VOL_SFT, 39, 1, out_vol_tlv),
477
478 /* Headphone Output Volume */
Nicolas Boichat692768c2015-05-14 08:43:31 +0800[diff] [blame]479 SOC_DOUBLE("Headphone Channel Switch", RT5645_HP_VOL,
Oder Chiou1319b2f2014-04-28 19:59:10 +0800[diff] [blame]480 RT5645_VOL_L_SFT, RT5645_VOL_R_SFT, 1, 1),
Nicolas Boichat692768c2015-05-14 08:43:31 +0800[diff] [blame]481 SOC_DOUBLE_TLV("Headphone Playback Volume", RT5645_HP_VOL,
Oder Chiou1319b2f2014-04-28 19:59:10 +0800[diff] [blame]482 RT5645_L_VOL_SFT, RT5645_R_VOL_SFT, 39, 1, out_vol_tlv),
483
484 /* OUTPUT Control */
485 SOC_DOUBLE("OUT Playback Switch", RT5645_LOUT1,
486 RT5645_L_MUTE_SFT, RT5645_R_MUTE_SFT, 1, 1),
487 SOC_DOUBLE("OUT Channel Switch", RT5645_LOUT1,
488 RT5645_VOL_L_SFT, RT5645_VOL_R_SFT, 1, 1),
489 SOC_DOUBLE_TLV("OUT Playback Volume", RT5645_LOUT1,
490 RT5645_L_VOL_SFT, RT5645_R_VOL_SFT, 39, 1, out_vol_tlv),
491
492 /* DAC Digital Volume */
493 SOC_DOUBLE("DAC2 Playback Switch", RT5645_DAC_CTRL,
494 RT5645_M_DAC_L2_VOL_SFT, RT5645_M_DAC_R2_VOL_SFT, 1, 1),
495 SOC_DOUBLE_TLV("DAC1 Playback Volume", RT5645_DAC1_DIG_VOL,
Bard Liao177e1e12015-04-30 18:18:47 +0800[diff] [blame]496 RT5645_L_VOL_SFT + 1, RT5645_R_VOL_SFT + 1, 87, 0, dac_vol_tlv),
Oder Chiou1319b2f2014-04-28 19:59:10 +0800[diff] [blame]497 SOC_DOUBLE_TLV("Mono DAC Playback Volume", RT5645_DAC2_DIG_VOL,
Bard Liao177e1e12015-04-30 18:18:47 +0800[diff] [blame]498 RT5645_L_VOL_SFT + 1, RT5645_R_VOL_SFT + 1, 87, 0, dac_vol_tlv),
Oder Chiou1319b2f2014-04-28 19:59:10 +0800[diff] [blame]499
500 /* IN1/IN2 Control */
501 SOC_SINGLE_TLV("IN1 Boost", RT5645_IN1_CTRL1,
502 RT5645_BST_SFT1, 8, 0, bst_tlv),
503 SOC_SINGLE_TLV("IN2 Boost", RT5645_IN2_CTRL,
504 RT5645_BST_SFT2, 8, 0, bst_tlv),
505
506 /* INL/INR Volume Control */
507 SOC_DOUBLE_TLV("IN Capture Volume", RT5645_INL1_INR1_VOL,
508 RT5645_INL_VOL_SFT, RT5645_INR_VOL_SFT, 31, 1, in_vol_tlv),
509
510 /* ADC Digital Volume Control */
511 SOC_DOUBLE("ADC Capture Switch", RT5645_STO1_ADC_DIG_VOL,
512 RT5645_L_MUTE_SFT, RT5645_R_MUTE_SFT, 1, 1),
513 SOC_DOUBLE_TLV("ADC Capture Volume", RT5645_STO1_ADC_DIG_VOL,
Bard Liao177e1e12015-04-30 18:18:47 +0800[diff] [blame]514 RT5645_L_VOL_SFT + 1, RT5645_R_VOL_SFT + 1, 63, 0, adc_vol_tlv),
Oder Chiou1319b2f2014-04-28 19:59:10 +0800[diff] [blame]515 SOC_DOUBLE("Mono ADC Capture Switch", RT5645_MONO_ADC_DIG_VOL,
516 RT5645_L_MUTE_SFT, RT5645_R_MUTE_SFT, 1, 1),
517 SOC_DOUBLE_TLV("Mono ADC Capture Volume", RT5645_MONO_ADC_DIG_VOL,
Bard Liao177e1e12015-04-30 18:18:47 +0800[diff] [blame]518 RT5645_L_VOL_SFT + 1, RT5645_R_VOL_SFT + 1, 63, 0, adc_vol_tlv),
Oder Chiou1319b2f2014-04-28 19:59:10 +0800[diff] [blame]519
520 /* ADC Boost Volume Control */
521 SOC_DOUBLE_TLV("STO1 ADC Boost Gain", RT5645_ADC_BST_VOL1,
522 RT5645_STO1_ADC_L_BST_SFT, RT5645_STO1_ADC_R_BST_SFT, 3, 0,
523 adc_bst_tlv),
524 SOC_DOUBLE_TLV("STO2 ADC Boost Gain", RT5645_ADC_BST_VOL1,
525 RT5645_STO2_ADC_L_BST_SFT, RT5645_STO2_ADC_R_BST_SFT, 3, 0,
526 adc_bst_tlv),
527
528 /* I2S2 function select */
529 SOC_SINGLE("I2S2 Func Switch", RT5645_GPIO_CTRL1, RT5645_I2S2_SEL_SFT,
530 1, 1),
Oder Chiou1319b2f2014-04-28 19:59:10 +0800[diff] [blame]531};
532
533/**
534 * set_dmic_clk - Set parameter of dmic.
535 *
536 * @w: DAPM widget.
537 * @kcontrol: The kcontrol of this widget.
538 * @event: Event id.
539 *
Oder Chiou1319b2f2014-04-28 19:59:10 +0800[diff] [blame]540 */
541static int set_dmic_clk(struct snd_soc_dapm_widget *w,
542 struct snd_kcontrol *kcontrol, int event)
543{
Lars-Peter Clausenc5f596c2015-01-15 12:52:13 +0100[diff] [blame]544 struct snd_soc_codec *codec = snd_soc_dapm_to_codec(w->dapm);
Oder Chiou1319b2f2014-04-28 19:59:10 +0800[diff] [blame]545 struct rt5645_priv *rt5645 = snd_soc_codec_get_drvdata(codec);
Oder Chiou49ef7922014-05-20 15:01:53 +0800[diff] [blame]546 int idx = -EINVAL;
Oder Chiou1319b2f2014-04-28 19:59:10 +0800[diff] [blame]547
Oder Chiou49ef7922014-05-20 15:01:53 +0800[diff] [blame]548 idx = rl6231_calc_dmic_clk(rt5645->sysclk);
Oder Chiou1319b2f2014-04-28 19:59:10 +0800[diff] [blame]549
550 if (idx < 0)
551 dev_err(codec->dev, "Failed to set DMIC clock\n");
552 else
553 snd_soc_update_bits(codec, RT5645_DMIC_CTRL1,
554 RT5645_DMIC_CLK_MASK, idx << RT5645_DMIC_CLK_SFT);
555 return idx;
556}
557
558static int is_sys_clk_from_pll(struct snd_soc_dapm_widget *source,
559 struct snd_soc_dapm_widget *sink)
560{
Lars-Peter Clausenc5f596c2015-01-15 12:52:13 +0100[diff] [blame]561 struct snd_soc_codec *codec = snd_soc_dapm_to_codec(source->dapm);
Oder Chiou1319b2f2014-04-28 19:59:10 +0800[diff] [blame]562 unsigned int val;
563
Lars-Peter Clausenc5f596c2015-01-15 12:52:13 +0100[diff] [blame]564 val = snd_soc_read(codec, RT5645_GLB_CLK);
Oder Chiou1319b2f2014-04-28 19:59:10 +0800[diff] [blame]565 val &= RT5645_SCLK_SRC_MASK;
566 if (val == RT5645_SCLK_SRC_PLL1)
567 return 1;
568 else
569 return 0;
570}
571
Bard Liao9e268352014-10-31 15:37:55 +0800[diff] [blame]572static int is_using_asrc(struct snd_soc_dapm_widget *source,
573 struct snd_soc_dapm_widget *sink)
574{
Lars-Peter Clausenc5f596c2015-01-15 12:52:13 +0100[diff] [blame]575 struct snd_soc_codec *codec = snd_soc_dapm_to_codec(source->dapm);
Bard Liao9e268352014-10-31 15:37:55 +0800[diff] [blame]576 unsigned int reg, shift, val;
577
578 switch (source->shift) {
579 case 0:
580 reg = RT5645_ASRC_3;
581 shift = 0;
582 break;
583 case 1:
584 reg = RT5645_ASRC_3;
585 shift = 4;
586 break;
587 case 3:
588 reg = RT5645_ASRC_2;
589 shift = 0;
590 break;
591 case 8:
592 reg = RT5645_ASRC_2;
593 shift = 4;
594 break;
595 case 9:
596 reg = RT5645_ASRC_2;
597 shift = 8;
598 break;
599 case 10:
600 reg = RT5645_ASRC_2;
601 shift = 12;
602 break;
603 default:
604 return 0;
605 }
606
Lars-Peter Clausenc5f596c2015-01-15 12:52:13 +0100[diff] [blame]607 val = (snd_soc_read(codec, reg) >> shift) & 0xf;
Bard Liao9e268352014-10-31 15:37:55 +0800[diff] [blame]608 switch (val) {
609 case 1:
610 case 2:
611 case 3:
612 case 4:
613 return 1;
614 default:
615 return 0;
616 }
617
618}
619
Fang, Yang A79080a82015-02-04 18:19:31 -0800[diff] [blame]620/**
621 * rt5645_sel_asrc_clk_src - select ASRC clock source for a set of filters
622 * @codec: SoC audio codec device.
623 * @filter_mask: mask of filters.
624 * @clk_src: clock source
625 *
626 * The ASRC function is for asynchronous MCLK and LRCK. Also, since RT5645 can
627 * only support standard 32fs or 64fs i2s format, ASRC should be enabled to
628 * support special i2s clock format such as Intel's 100fs(100 * sampling rate).
629 * ASRC function will track i2s clock and generate a corresponding system clock
630 * for codec. This function provides an API to select the clock source for a
631 * set of filters specified by the mask. And the codec driver will turn on ASRC
632 * for these filters if ASRC is selected as their clock source.
633 */
634int rt5645_sel_asrc_clk_src(struct snd_soc_codec *codec,
635 unsigned int filter_mask, unsigned int clk_src)
636{
637 unsigned int asrc2_mask = 0;
638 unsigned int asrc2_value = 0;
639 unsigned int asrc3_mask = 0;
640 unsigned int asrc3_value = 0;
641
642 switch (clk_src) {
643 case RT5645_CLK_SEL_SYS:
644 case RT5645_CLK_SEL_I2S1_ASRC:
645 case RT5645_CLK_SEL_I2S2_ASRC:
646 case RT5645_CLK_SEL_SYS2:
647 break;
648
649 default:
650 return -EINVAL;
651 }
652
653 if (filter_mask & RT5645_DA_STEREO_FILTER) {
654 asrc2_mask |= RT5645_DA_STO_CLK_SEL_MASK;
655 asrc2_value = (asrc2_value & ~RT5645_DA_STO_CLK_SEL_MASK)
656 | (clk_src << RT5645_DA_STO_CLK_SEL_SFT);
657 }
658
659 if (filter_mask & RT5645_DA_MONO_L_FILTER) {
660 asrc2_mask |= RT5645_DA_MONOL_CLK_SEL_MASK;
661 asrc2_value = (asrc2_value & ~RT5645_DA_MONOL_CLK_SEL_MASK)
662 | (clk_src << RT5645_DA_MONOL_CLK_SEL_SFT);
663 }
664
665 if (filter_mask & RT5645_DA_MONO_R_FILTER) {
666 asrc2_mask |= RT5645_DA_MONOR_CLK_SEL_MASK;
667 asrc2_value = (asrc2_value & ~RT5645_DA_MONOR_CLK_SEL_MASK)
668 | (clk_src << RT5645_DA_MONOR_CLK_SEL_SFT);
669 }
670
671 if (filter_mask & RT5645_AD_STEREO_FILTER) {
672 asrc2_mask |= RT5645_AD_STO1_CLK_SEL_MASK;
673 asrc2_value = (asrc2_value & ~RT5645_AD_STO1_CLK_SEL_MASK)
674 | (clk_src << RT5645_AD_STO1_CLK_SEL_SFT);
675 }
676
677 if (filter_mask & RT5645_AD_MONO_L_FILTER) {
678 asrc3_mask |= RT5645_AD_MONOL_CLK_SEL_MASK;
679 asrc3_value = (asrc3_value & ~RT5645_AD_MONOL_CLK_SEL_MASK)
680 | (clk_src << RT5645_AD_MONOL_CLK_SEL_SFT);
681 }
682
683 if (filter_mask & RT5645_AD_MONO_R_FILTER) {
684 asrc3_mask |= RT5645_AD_MONOR_CLK_SEL_MASK;
685 asrc3_value = (asrc3_value & ~RT5645_AD_MONOR_CLK_SEL_MASK)
686 | (clk_src << RT5645_AD_MONOR_CLK_SEL_SFT);
687 }
688
689 if (asrc2_mask)
690 snd_soc_update_bits(codec, RT5645_ASRC_2,
691 asrc2_mask, asrc2_value);
692
693 if (asrc3_mask)
694 snd_soc_update_bits(codec, RT5645_ASRC_3,
695 asrc3_mask, asrc3_value);
696
697 return 0;
698}
699EXPORT_SYMBOL_GPL(rt5645_sel_asrc_clk_src);
700
Oder Chiou1319b2f2014-04-28 19:59:10 +0800[diff] [blame]701/* Digital Mixer */
702static const struct snd_kcontrol_new rt5645_sto1_adc_l_mix[] = {
703 SOC_DAPM_SINGLE("ADC1 Switch", RT5645_STO1_ADC_MIXER,
704 RT5645_M_ADC_L1_SFT, 1, 1),
705 SOC_DAPM_SINGLE("ADC2 Switch", RT5645_STO1_ADC_MIXER,
706 RT5645_M_ADC_L2_SFT, 1, 1),
707};
708
709static const struct snd_kcontrol_new rt5645_sto1_adc_r_mix[] = {
710 SOC_DAPM_SINGLE("ADC1 Switch", RT5645_STO1_ADC_MIXER,
711 RT5645_M_ADC_R1_SFT, 1, 1),
712 SOC_DAPM_SINGLE("ADC2 Switch", RT5645_STO1_ADC_MIXER,
713 RT5645_M_ADC_R2_SFT, 1, 1),
714};
715
716static const struct snd_kcontrol_new rt5645_mono_adc_l_mix[] = {
717 SOC_DAPM_SINGLE("ADC1 Switch", RT5645_MONO_ADC_MIXER,
718 RT5645_M_MONO_ADC_L1_SFT, 1, 1),
719 SOC_DAPM_SINGLE("ADC2 Switch", RT5645_MONO_ADC_MIXER,
720 RT5645_M_MONO_ADC_L2_SFT, 1, 1),
721};
722
723static const struct snd_kcontrol_new rt5645_mono_adc_r_mix[] = {
724 SOC_DAPM_SINGLE("ADC1 Switch", RT5645_MONO_ADC_MIXER,
725 RT5645_M_MONO_ADC_R1_SFT, 1, 1),
726 SOC_DAPM_SINGLE("ADC2 Switch", RT5645_MONO_ADC_MIXER,
727 RT5645_M_MONO_ADC_R2_SFT, 1, 1),
728};
729
730static const struct snd_kcontrol_new rt5645_dac_l_mix[] = {
731 SOC_DAPM_SINGLE("Stereo ADC Switch", RT5645_AD_DA_MIXER,
732 RT5645_M_ADCMIX_L_SFT, 1, 1),
733 SOC_DAPM_SINGLE("DAC1 Switch", RT5645_AD_DA_MIXER,
734 RT5645_M_DAC1_L_SFT, 1, 1),
735};
736
737static const struct snd_kcontrol_new rt5645_dac_r_mix[] = {
738 SOC_DAPM_SINGLE("Stereo ADC Switch", RT5645_AD_DA_MIXER,
739 RT5645_M_ADCMIX_R_SFT, 1, 1),
740 SOC_DAPM_SINGLE("DAC1 Switch", RT5645_AD_DA_MIXER,
741 RT5645_M_DAC1_R_SFT, 1, 1),
742};
743
744static const struct snd_kcontrol_new rt5645_sto_dac_l_mix[] = {
745 SOC_DAPM_SINGLE("DAC L1 Switch", RT5645_STO_DAC_MIXER,
746 RT5645_M_DAC_L1_SFT, 1, 1),
747 SOC_DAPM_SINGLE("DAC L2 Switch", RT5645_STO_DAC_MIXER,
748 RT5645_M_DAC_L2_SFT, 1, 1),
749 SOC_DAPM_SINGLE("DAC R1 Switch", RT5645_STO_DAC_MIXER,
750 RT5645_M_DAC_R1_STO_L_SFT, 1, 1),
751};
752
753static const struct snd_kcontrol_new rt5645_sto_dac_r_mix[] = {
754 SOC_DAPM_SINGLE("DAC R1 Switch", RT5645_STO_DAC_MIXER,
755 RT5645_M_DAC_R1_SFT, 1, 1),
756 SOC_DAPM_SINGLE("DAC R2 Switch", RT5645_STO_DAC_MIXER,
757 RT5645_M_DAC_R2_SFT, 1, 1),
758 SOC_DAPM_SINGLE("DAC L1 Switch", RT5645_STO_DAC_MIXER,
759 RT5645_M_DAC_L1_STO_R_SFT, 1, 1),
760};
761
762static const struct snd_kcontrol_new rt5645_mono_dac_l_mix[] = {
763 SOC_DAPM_SINGLE("DAC L1 Switch", RT5645_MONO_DAC_MIXER,
764 RT5645_M_DAC_L1_MONO_L_SFT, 1, 1),
765 SOC_DAPM_SINGLE("DAC L2 Switch", RT5645_MONO_DAC_MIXER,
766 RT5645_M_DAC_L2_MONO_L_SFT, 1, 1),
767 SOC_DAPM_SINGLE("DAC R2 Switch", RT5645_MONO_DAC_MIXER,
768 RT5645_M_DAC_R2_MONO_L_SFT, 1, 1),
769};
770
771static const struct snd_kcontrol_new rt5645_mono_dac_r_mix[] = {
772 SOC_DAPM_SINGLE("DAC R1 Switch", RT5645_MONO_DAC_MIXER,
773 RT5645_M_DAC_R1_MONO_R_SFT, 1, 1),
774 SOC_DAPM_SINGLE("DAC R2 Switch", RT5645_MONO_DAC_MIXER,
775 RT5645_M_DAC_R2_MONO_R_SFT, 1, 1),
776 SOC_DAPM_SINGLE("DAC L2 Switch", RT5645_MONO_DAC_MIXER,
777 RT5645_M_DAC_L2_MONO_R_SFT, 1, 1),
778};
779
780static const struct snd_kcontrol_new rt5645_dig_l_mix[] = {
781 SOC_DAPM_SINGLE("Sto DAC Mix L Switch", RT5645_DIG_MIXER,
782 RT5645_M_STO_L_DAC_L_SFT, 1, 1),
783 SOC_DAPM_SINGLE("DAC L2 Switch", RT5645_DIG_MIXER,
784 RT5645_M_DAC_L2_DAC_L_SFT, 1, 1),
785 SOC_DAPM_SINGLE("DAC R2 Switch", RT5645_DIG_MIXER,
786 RT5645_M_DAC_R2_DAC_L_SFT, 1, 1),
787};
788
789static const struct snd_kcontrol_new rt5645_dig_r_mix[] = {
790 SOC_DAPM_SINGLE("Sto DAC Mix R Switch", RT5645_DIG_MIXER,
791 RT5645_M_STO_R_DAC_R_SFT, 1, 1),
792 SOC_DAPM_SINGLE("DAC R2 Switch", RT5645_DIG_MIXER,
793 RT5645_M_DAC_R2_DAC_R_SFT, 1, 1),
794 SOC_DAPM_SINGLE("DAC L2 Switch", RT5645_DIG_MIXER,
795 RT5645_M_DAC_L2_DAC_R_SFT, 1, 1),
796};
797
798/* Analog Input Mixer */
799static const struct snd_kcontrol_new rt5645_rec_l_mix[] = {
800 SOC_DAPM_SINGLE("HPOL Switch", RT5645_REC_L2_MIXER,
801 RT5645_M_HP_L_RM_L_SFT, 1, 1),
802 SOC_DAPM_SINGLE("INL Switch", RT5645_REC_L2_MIXER,
803 RT5645_M_IN_L_RM_L_SFT, 1, 1),
804 SOC_DAPM_SINGLE("BST2 Switch", RT5645_REC_L2_MIXER,
805 RT5645_M_BST2_RM_L_SFT, 1, 1),
806 SOC_DAPM_SINGLE("BST1 Switch", RT5645_REC_L2_MIXER,
807 RT5645_M_BST1_RM_L_SFT, 1, 1),
808 SOC_DAPM_SINGLE("OUT MIXL Switch", RT5645_REC_L2_MIXER,
809 RT5645_M_OM_L_RM_L_SFT, 1, 1),
810};
811
812static const struct snd_kcontrol_new rt5645_rec_r_mix[] = {
813 SOC_DAPM_SINGLE("HPOR Switch", RT5645_REC_R2_MIXER,
814 RT5645_M_HP_R_RM_R_SFT, 1, 1),
815 SOC_DAPM_SINGLE("INR Switch", RT5645_REC_R2_MIXER,
816 RT5645_M_IN_R_RM_R_SFT, 1, 1),
817 SOC_DAPM_SINGLE("BST2 Switch", RT5645_REC_R2_MIXER,
818 RT5645_M_BST2_RM_R_SFT, 1, 1),
819 SOC_DAPM_SINGLE("BST1 Switch", RT5645_REC_R2_MIXER,
820 RT5645_M_BST1_RM_R_SFT, 1, 1),
821 SOC_DAPM_SINGLE("OUT MIXR Switch", RT5645_REC_R2_MIXER,
822 RT5645_M_OM_R_RM_R_SFT, 1, 1),
823};
824
825static const struct snd_kcontrol_new rt5645_spk_l_mix[] = {
826 SOC_DAPM_SINGLE("DAC L1 Switch", RT5645_SPK_L_MIXER,
827 RT5645_M_DAC_L1_SM_L_SFT, 1, 1),
828 SOC_DAPM_SINGLE("DAC L2 Switch", RT5645_SPK_L_MIXER,
829 RT5645_M_DAC_L2_SM_L_SFT, 1, 1),
830 SOC_DAPM_SINGLE("INL Switch", RT5645_SPK_L_MIXER,
831 RT5645_M_IN_L_SM_L_SFT, 1, 1),
832 SOC_DAPM_SINGLE("BST1 Switch", RT5645_SPK_L_MIXER,
833 RT5645_M_BST1_L_SM_L_SFT, 1, 1),
834};
835
836static const struct snd_kcontrol_new rt5645_spk_r_mix[] = {
837 SOC_DAPM_SINGLE("DAC R1 Switch", RT5645_SPK_R_MIXER,
838 RT5645_M_DAC_R1_SM_R_SFT, 1, 1),
839 SOC_DAPM_SINGLE("DAC R2 Switch", RT5645_SPK_R_MIXER,
840 RT5645_M_DAC_R2_SM_R_SFT, 1, 1),
841 SOC_DAPM_SINGLE("INR Switch", RT5645_SPK_R_MIXER,
842 RT5645_M_IN_R_SM_R_SFT, 1, 1),
843 SOC_DAPM_SINGLE("BST2 Switch", RT5645_SPK_R_MIXER,
844 RT5645_M_BST2_R_SM_R_SFT, 1, 1),
845};
846
847static const struct snd_kcontrol_new rt5645_out_l_mix[] = {
848 SOC_DAPM_SINGLE("BST1 Switch", RT5645_OUT_L1_MIXER,
849 RT5645_M_BST1_OM_L_SFT, 1, 1),
850 SOC_DAPM_SINGLE("INL Switch", RT5645_OUT_L1_MIXER,
851 RT5645_M_IN_L_OM_L_SFT, 1, 1),
852 SOC_DAPM_SINGLE("DAC L2 Switch", RT5645_OUT_L1_MIXER,
853 RT5645_M_DAC_L2_OM_L_SFT, 1, 1),
854 SOC_DAPM_SINGLE("DAC L1 Switch", RT5645_OUT_L1_MIXER,
855 RT5645_M_DAC_L1_OM_L_SFT, 1, 1),
856};
857
858static const struct snd_kcontrol_new rt5645_out_r_mix[] = {
859 SOC_DAPM_SINGLE("BST2 Switch", RT5645_OUT_R1_MIXER,
860 RT5645_M_BST2_OM_R_SFT, 1, 1),
861 SOC_DAPM_SINGLE("INR Switch", RT5645_OUT_R1_MIXER,
862 RT5645_M_IN_R_OM_R_SFT, 1, 1),
863 SOC_DAPM_SINGLE("DAC R2 Switch", RT5645_OUT_R1_MIXER,
864 RT5645_M_DAC_R2_OM_R_SFT, 1, 1),
865 SOC_DAPM_SINGLE("DAC R1 Switch", RT5645_OUT_R1_MIXER,
866 RT5645_M_DAC_R1_OM_R_SFT, 1, 1),
867};
868
869static const struct snd_kcontrol_new rt5645_spo_l_mix[] = {
870 SOC_DAPM_SINGLE("DAC R1 Switch", RT5645_SPO_MIXER,
871 RT5645_M_DAC_R1_SPM_L_SFT, 1, 1),
872 SOC_DAPM_SINGLE("DAC L1 Switch", RT5645_SPO_MIXER,
873 RT5645_M_DAC_L1_SPM_L_SFT, 1, 1),
874 SOC_DAPM_SINGLE("SPKVOL R Switch", RT5645_SPO_MIXER,
875 RT5645_M_SV_R_SPM_L_SFT, 1, 1),
876 SOC_DAPM_SINGLE("SPKVOL L Switch", RT5645_SPO_MIXER,
877 RT5645_M_SV_L_SPM_L_SFT, 1, 1),
878};
879
880static const struct snd_kcontrol_new rt5645_spo_r_mix[] = {
881 SOC_DAPM_SINGLE("DAC R1 Switch", RT5645_SPO_MIXER,
882 RT5645_M_DAC_R1_SPM_R_SFT, 1, 1),
883 SOC_DAPM_SINGLE("SPKVOL R Switch", RT5645_SPO_MIXER,
884 RT5645_M_SV_R_SPM_R_SFT, 1, 1),
885};
886
887static const struct snd_kcontrol_new rt5645_hpo_mix[] = {
888 SOC_DAPM_SINGLE("DAC1 Switch", RT5645_HPO_MIXER,
889 RT5645_M_DAC1_HM_SFT, 1, 1),
890 SOC_DAPM_SINGLE("HPVOL Switch", RT5645_HPO_MIXER,
891 RT5645_M_HPVOL_HM_SFT, 1, 1),
892};
893
894static const struct snd_kcontrol_new rt5645_hpvoll_mix[] = {
895 SOC_DAPM_SINGLE("DAC1 Switch", RT5645_HPOMIXL_CTRL,
896 RT5645_M_DAC1_HV_SFT, 1, 1),
897 SOC_DAPM_SINGLE("DAC2 Switch", RT5645_HPOMIXL_CTRL,
898 RT5645_M_DAC2_HV_SFT, 1, 1),
899 SOC_DAPM_SINGLE("INL Switch", RT5645_HPOMIXL_CTRL,
900 RT5645_M_IN_HV_SFT, 1, 1),
901 SOC_DAPM_SINGLE("BST1 Switch", RT5645_HPOMIXL_CTRL,
902 RT5645_M_BST1_HV_SFT, 1, 1),
903};
904
905static const struct snd_kcontrol_new rt5645_hpvolr_mix[] = {
906 SOC_DAPM_SINGLE("DAC1 Switch", RT5645_HPOMIXR_CTRL,
907 RT5645_M_DAC1_HV_SFT, 1, 1),
908 SOC_DAPM_SINGLE("DAC2 Switch", RT5645_HPOMIXR_CTRL,
909 RT5645_M_DAC2_HV_SFT, 1, 1),
910 SOC_DAPM_SINGLE("INR Switch", RT5645_HPOMIXR_CTRL,
911 RT5645_M_IN_HV_SFT, 1, 1),
912 SOC_DAPM_SINGLE("BST2 Switch", RT5645_HPOMIXR_CTRL,
913 RT5645_M_BST2_HV_SFT, 1, 1),
914};
915
916static const struct snd_kcontrol_new rt5645_lout_mix[] = {
917 SOC_DAPM_SINGLE("DAC L1 Switch", RT5645_LOUT_MIXER,
918 RT5645_M_DAC_L1_LM_SFT, 1, 1),
919 SOC_DAPM_SINGLE("DAC R1 Switch", RT5645_LOUT_MIXER,
920 RT5645_M_DAC_R1_LM_SFT, 1, 1),
921 SOC_DAPM_SINGLE("OUTMIX L Switch", RT5645_LOUT_MIXER,
922 RT5645_M_OV_L_LM_SFT, 1, 1),
923 SOC_DAPM_SINGLE("OUTMIX R Switch", RT5645_LOUT_MIXER,
924 RT5645_M_OV_R_LM_SFT, 1, 1),
925};
926
927/*DAC1 L/R source*/ /* MX-29 [9:8] [11:10] */
928static const char * const rt5645_dac1_src[] = {
929 "IF1 DAC", "IF2 DAC", "IF3 DAC"
930};
931
932static SOC_ENUM_SINGLE_DECL(
933 rt5645_dac1l_enum, RT5645_AD_DA_MIXER,
934 RT5645_DAC1_L_SEL_SFT, rt5645_dac1_src);
935
936static const struct snd_kcontrol_new rt5645_dac1l_mux =
937 SOC_DAPM_ENUM("DAC1 L source", rt5645_dac1l_enum);
938
939static SOC_ENUM_SINGLE_DECL(
940 rt5645_dac1r_enum, RT5645_AD_DA_MIXER,
941 RT5645_DAC1_R_SEL_SFT, rt5645_dac1_src);
942
943static const struct snd_kcontrol_new rt5645_dac1r_mux =
944 SOC_DAPM_ENUM("DAC1 R source", rt5645_dac1r_enum);
945
946/*DAC2 L/R source*/ /* MX-1B [6:4] [2:0] */
947static const char * const rt5645_dac12_src[] = {
948 "IF1 DAC", "IF2 DAC", "IF3 DAC", "Mono ADC", "VAD_ADC"
949};
950
951static SOC_ENUM_SINGLE_DECL(
952 rt5645_dac2l_enum, RT5645_DAC_CTRL,
953 RT5645_DAC2_L_SEL_SFT, rt5645_dac12_src);
954
955static const struct snd_kcontrol_new rt5645_dac_l2_mux =
956 SOC_DAPM_ENUM("DAC2 L source", rt5645_dac2l_enum);
957
958static const char * const rt5645_dacr2_src[] = {
959 "IF1 DAC", "IF2 DAC", "IF3 DAC", "Mono ADC", "Haptic"
960};
961
962static SOC_ENUM_SINGLE_DECL(
963 rt5645_dac2r_enum, RT5645_DAC_CTRL,
964 RT5645_DAC2_R_SEL_SFT, rt5645_dacr2_src);
965
966static const struct snd_kcontrol_new rt5645_dac_r2_mux =
967 SOC_DAPM_ENUM("DAC2 R source", rt5645_dac2r_enum);
968
969
970/* INL/R source */
971static const char * const rt5645_inl_src[] = {
972 "IN2P", "MonoP"
973};
974
975static SOC_ENUM_SINGLE_DECL(
976 rt5645_inl_enum, RT5645_INL1_INR1_VOL,
977 RT5645_INL_SEL_SFT, rt5645_inl_src);
978
979static const struct snd_kcontrol_new rt5645_inl_mux =
980 SOC_DAPM_ENUM("INL source", rt5645_inl_enum);
981
982static const char * const rt5645_inr_src[] = {
983 "IN2N", "MonoN"
984};
985
986static SOC_ENUM_SINGLE_DECL(
987 rt5645_inr_enum, RT5645_INL1_INR1_VOL,
988 RT5645_INR_SEL_SFT, rt5645_inr_src);
989
990static const struct snd_kcontrol_new rt5645_inr_mux =
991 SOC_DAPM_ENUM("INR source", rt5645_inr_enum);
992
993/* Stereo1 ADC source */
994/* MX-27 [12] */
995static const char * const rt5645_stereo_adc1_src[] = {
996 "DAC MIX", "ADC"
997};
998
999static SOC_ENUM_SINGLE_DECL(
1000 rt5645_stereo1_adc1_enum, RT5645_STO1_ADC_MIXER,
1001 RT5645_ADC_1_SRC_SFT, rt5645_stereo_adc1_src);
1002
1003static const struct snd_kcontrol_new rt5645_sto_adc1_mux =
1004 SOC_DAPM_ENUM("Stereo1 ADC1 Mux", rt5645_stereo1_adc1_enum);
1005
1006/* MX-27 [11] */
1007static const char * const rt5645_stereo_adc2_src[] = {
1008 "DAC MIX", "DMIC"
1009};
1010
1011static SOC_ENUM_SINGLE_DECL(
1012 rt5645_stereo1_adc2_enum, RT5645_STO1_ADC_MIXER,
1013 RT5645_ADC_2_SRC_SFT, rt5645_stereo_adc2_src);
1014
1015static const struct snd_kcontrol_new rt5645_sto_adc2_mux =
1016 SOC_DAPM_ENUM("Stereo1 ADC2 Mux", rt5645_stereo1_adc2_enum);
1017
1018/* MX-27 [8] */
1019static const char * const rt5645_stereo_dmic_src[] = {
1020 "DMIC1", "DMIC2"
1021};
1022
1023static SOC_ENUM_SINGLE_DECL(
1024 rt5645_stereo1_dmic_enum, RT5645_STO1_ADC_MIXER,
1025 RT5645_DMIC_SRC_SFT, rt5645_stereo_dmic_src);
1026
1027static const struct snd_kcontrol_new rt5645_sto1_dmic_mux =
1028 SOC_DAPM_ENUM("Stereo1 DMIC source", rt5645_stereo1_dmic_enum);
1029
1030/* Mono ADC source */
1031/* MX-28 [12] */
1032static const char * const rt5645_mono_adc_l1_src[] = {
1033 "Mono DAC MIXL", "ADC"
1034};
1035
1036static SOC_ENUM_SINGLE_DECL(
1037 rt5645_mono_adc_l1_enum, RT5645_MONO_ADC_MIXER,
1038 RT5645_MONO_ADC_L1_SRC_SFT, rt5645_mono_adc_l1_src);
1039
1040static const struct snd_kcontrol_new rt5645_mono_adc_l1_mux =
1041 SOC_DAPM_ENUM("Mono ADC1 left source", rt5645_mono_adc_l1_enum);
1042/* MX-28 [11] */
1043static const char * const rt5645_mono_adc_l2_src[] = {
1044 "Mono DAC MIXL", "DMIC"
1045};
1046
1047static SOC_ENUM_SINGLE_DECL(
1048 rt5645_mono_adc_l2_enum, RT5645_MONO_ADC_MIXER,
1049 RT5645_MONO_ADC_L2_SRC_SFT, rt5645_mono_adc_l2_src);
1050
1051static const struct snd_kcontrol_new rt5645_mono_adc_l2_mux =
1052 SOC_DAPM_ENUM("Mono ADC2 left source", rt5645_mono_adc_l2_enum);
1053
1054/* MX-28 [8] */
1055static const char * const rt5645_mono_dmic_src[] = {
1056 "DMIC1", "DMIC2"
1057};
1058
1059static SOC_ENUM_SINGLE_DECL(
1060 rt5645_mono_dmic_l_enum, RT5645_MONO_ADC_MIXER,
1061 RT5645_MONO_DMIC_L_SRC_SFT, rt5645_mono_dmic_src);
1062
1063static const struct snd_kcontrol_new rt5645_mono_dmic_l_mux =
1064 SOC_DAPM_ENUM("Mono DMIC left source", rt5645_mono_dmic_l_enum);
1065/* MX-28 [1:0] */
1066static SOC_ENUM_SINGLE_DECL(
1067 rt5645_mono_dmic_r_enum, RT5645_MONO_ADC_MIXER,
1068 RT5645_MONO_DMIC_R_SRC_SFT, rt5645_mono_dmic_src);
1069
1070static const struct snd_kcontrol_new rt5645_mono_dmic_r_mux =
1071 SOC_DAPM_ENUM("Mono DMIC Right source", rt5645_mono_dmic_r_enum);
1072/* MX-28 [4] */
1073static const char * const rt5645_mono_adc_r1_src[] = {
1074 "Mono DAC MIXR", "ADC"
1075};
1076
1077static SOC_ENUM_SINGLE_DECL(
1078 rt5645_mono_adc_r1_enum, RT5645_MONO_ADC_MIXER,
1079 RT5645_MONO_ADC_R1_SRC_SFT, rt5645_mono_adc_r1_src);
1080
1081static const struct snd_kcontrol_new rt5645_mono_adc_r1_mux =
1082 SOC_DAPM_ENUM("Mono ADC1 right source", rt5645_mono_adc_r1_enum);
1083/* MX-28 [3] */
1084static const char * const rt5645_mono_adc_r2_src[] = {
1085 "Mono DAC MIXR", "DMIC"
1086};
1087
1088static SOC_ENUM_SINGLE_DECL(
1089 rt5645_mono_adc_r2_enum, RT5645_MONO_ADC_MIXER,
1090 RT5645_MONO_ADC_R2_SRC_SFT, rt5645_mono_adc_r2_src);
1091
1092static const struct snd_kcontrol_new rt5645_mono_adc_r2_mux =
1093 SOC_DAPM_ENUM("Mono ADC2 right source", rt5645_mono_adc_r2_enum);
1094
1095/* MX-77 [9:8] */
1096static const char * const rt5645_if1_adc_in_src[] = {
Bard Liao21ab3f22015-04-30 18:18:44 +0800[diff] [blame]1097 "IF_ADC1/IF_ADC2/VAD_ADC", "IF_ADC2/IF_ADC1/VAD_ADC",
1098 "VAD_ADC/IF_ADC1/IF_ADC2", "VAD_ADC/IF_ADC2/IF_ADC1"
Oder Chiou1319b2f2014-04-28 19:59:10 +0800[diff] [blame]1099};
1100
1101static SOC_ENUM_SINGLE_DECL(
1102 rt5645_if1_adc_in_enum, RT5645_TDM_CTRL_1,
1103 RT5645_IF1_ADC_IN_SFT, rt5645_if1_adc_in_src);
1104
1105static const struct snd_kcontrol_new rt5645_if1_adc_in_mux =
1106 SOC_DAPM_ENUM("IF1 ADC IN source", rt5645_if1_adc_in_enum);
1107
Bard Liao21ab3f22015-04-30 18:18:44 +0800[diff] [blame]1108/* MX-78 [4:0] */
1109static const char * const rt5650_if1_adc_in_src[] = {
1110 "IF_ADC1/IF_ADC2/DAC_REF/Null",
1111 "IF_ADC1/IF_ADC2/Null/DAC_REF",
1112 "IF_ADC1/DAC_REF/IF_ADC2/Null",
1113 "IF_ADC1/DAC_REF/Null/IF_ADC2",
1114 "IF_ADC1/Null/DAC_REF/IF_ADC2",
1115 "IF_ADC1/Null/IF_ADC2/DAC_REF",
1116
1117 "IF_ADC2/IF_ADC1/DAC_REF/Null",
1118 "IF_ADC2/IF_ADC1/Null/DAC_REF",
1119 "IF_ADC2/DAC_REF/IF_ADC1/Null",
1120 "IF_ADC2/DAC_REF/Null/IF_ADC1",
1121 "IF_ADC2/Null/DAC_REF/IF_ADC1",
1122 "IF_ADC2/Null/IF_ADC1/DAC_REF",
1123
1124 "DAC_REF/IF_ADC1/IF_ADC2/Null",
1125 "DAC_REF/IF_ADC1/Null/IF_ADC2",
1126 "DAC_REF/IF_ADC2/IF_ADC1/Null",
1127 "DAC_REF/IF_ADC2/Null/IF_ADC1",
1128 "DAC_REF/Null/IF_ADC1/IF_ADC2",
1129 "DAC_REF/Null/IF_ADC2/IF_ADC1",
1130
1131 "Null/IF_ADC1/IF_ADC2/DAC_REF",
1132 "Null/IF_ADC1/DAC_REF/IF_ADC2",
1133 "Null/IF_ADC2/IF_ADC1/DAC_REF",
1134 "Null/IF_ADC2/DAC_REF/IF_ADC1",
1135 "Null/DAC_REF/IF_ADC1/IF_ADC2",
1136 "Null/DAC_REF/IF_ADC2/IF_ADC1",
1137};
1138
1139static SOC_ENUM_SINGLE_DECL(
1140 rt5650_if1_adc_in_enum, RT5645_TDM_CTRL_2,
1141 0, rt5650_if1_adc_in_src);
1142
1143static const struct snd_kcontrol_new rt5650_if1_adc_in_mux =
1144 SOC_DAPM_ENUM("IF1 ADC IN source", rt5650_if1_adc_in_enum);
1145
1146/* MX-78 [15:14][13:12][11:10] */
1147static const char * const rt5645_tdm_adc_swap_select[] = {
1148 "L/R", "R/L", "L/L", "R/R"
1149};
1150
1151static SOC_ENUM_SINGLE_DECL(rt5650_tdm_adc_slot0_1_enum,
1152 RT5645_TDM_CTRL_2, 14, rt5645_tdm_adc_swap_select);
1153
1154static const struct snd_kcontrol_new rt5650_if1_adc1_in_mux =
1155 SOC_DAPM_ENUM("IF1 ADC1 IN source", rt5650_tdm_adc_slot0_1_enum);
1156
1157static SOC_ENUM_SINGLE_DECL(rt5650_tdm_adc_slot2_3_enum,
1158 RT5645_TDM_CTRL_2, 12, rt5645_tdm_adc_swap_select);
1159
1160static const struct snd_kcontrol_new rt5650_if1_adc2_in_mux =
1161 SOC_DAPM_ENUM("IF1 ADC2 IN source", rt5650_tdm_adc_slot2_3_enum);
1162
1163static SOC_ENUM_SINGLE_DECL(rt5650_tdm_adc_slot4_5_enum,
1164 RT5645_TDM_CTRL_2, 10, rt5645_tdm_adc_swap_select);
1165
1166static const struct snd_kcontrol_new rt5650_if1_adc3_in_mux =
1167 SOC_DAPM_ENUM("IF1 ADC3 IN source", rt5650_tdm_adc_slot4_5_enum);
1168
1169/* MX-77 [7:6][5:4][3:2] */
1170static SOC_ENUM_SINGLE_DECL(rt5645_tdm_adc_slot0_1_enum,
1171 RT5645_TDM_CTRL_1, 6, rt5645_tdm_adc_swap_select);
1172
1173static const struct snd_kcontrol_new rt5645_if1_adc1_in_mux =
1174 SOC_DAPM_ENUM("IF1 ADC1 IN source", rt5645_tdm_adc_slot0_1_enum);
1175
1176static SOC_ENUM_SINGLE_DECL(rt5645_tdm_adc_slot2_3_enum,
1177 RT5645_TDM_CTRL_1, 4, rt5645_tdm_adc_swap_select);
1178
1179static const struct snd_kcontrol_new rt5645_if1_adc2_in_mux =
1180 SOC_DAPM_ENUM("IF1 ADC2 IN source", rt5645_tdm_adc_slot2_3_enum);
1181
1182static SOC_ENUM_SINGLE_DECL(rt5645_tdm_adc_slot4_5_enum,
1183 RT5645_TDM_CTRL_1, 2, rt5645_tdm_adc_swap_select);
1184
1185static const struct snd_kcontrol_new rt5645_if1_adc3_in_mux =
1186 SOC_DAPM_ENUM("IF1 ADC3 IN source", rt5645_tdm_adc_slot4_5_enum);
1187
1188/* MX-79 [14:12][10:8][6:4][2:0] */
1189static const char * const rt5645_tdm_dac_swap_select[] = {
1190 "Slot0", "Slot1", "Slot2", "Slot3"
1191};
1192
1193static SOC_ENUM_SINGLE_DECL(rt5645_tdm_dac0_enum,
1194 RT5645_TDM_CTRL_3, 12, rt5645_tdm_dac_swap_select);
1195
1196static const struct snd_kcontrol_new rt5645_if1_dac0_tdm_sel_mux =
1197 SOC_DAPM_ENUM("IF1 DAC0 source", rt5645_tdm_dac0_enum);
1198
1199static SOC_ENUM_SINGLE_DECL(rt5645_tdm_dac1_enum,
1200 RT5645_TDM_CTRL_3, 8, rt5645_tdm_dac_swap_select);
1201
1202static const struct snd_kcontrol_new rt5645_if1_dac1_tdm_sel_mux =
1203 SOC_DAPM_ENUM("IF1 DAC1 source", rt5645_tdm_dac1_enum);
1204
1205static SOC_ENUM_SINGLE_DECL(rt5645_tdm_dac2_enum,
1206 RT5645_TDM_CTRL_3, 4, rt5645_tdm_dac_swap_select);
1207
1208static const struct snd_kcontrol_new rt5645_if1_dac2_tdm_sel_mux =
1209 SOC_DAPM_ENUM("IF1 DAC2 source", rt5645_tdm_dac2_enum);
1210
1211static SOC_ENUM_SINGLE_DECL(rt5645_tdm_dac3_enum,
1212 RT5645_TDM_CTRL_3, 0, rt5645_tdm_dac_swap_select);
1213
1214static const struct snd_kcontrol_new rt5645_if1_dac3_tdm_sel_mux =
1215 SOC_DAPM_ENUM("IF1 DAC3 source", rt5645_tdm_dac3_enum);
1216
1217/* MX-7a [14:12][10:8][6:4][2:0] */
1218static SOC_ENUM_SINGLE_DECL(rt5650_tdm_dac0_enum,
1219 RT5650_TDM_CTRL_4, 12, rt5645_tdm_dac_swap_select);
1220
1221static const struct snd_kcontrol_new rt5650_if1_dac0_tdm_sel_mux =
1222 SOC_DAPM_ENUM("IF1 DAC0 source", rt5650_tdm_dac0_enum);
1223
1224static SOC_ENUM_SINGLE_DECL(rt5650_tdm_dac1_enum,
1225 RT5650_TDM_CTRL_4, 8, rt5645_tdm_dac_swap_select);
1226
1227static const struct snd_kcontrol_new rt5650_if1_dac1_tdm_sel_mux =
1228 SOC_DAPM_ENUM("IF1 DAC1 source", rt5650_tdm_dac1_enum);
1229
1230static SOC_ENUM_SINGLE_DECL(rt5650_tdm_dac2_enum,
1231 RT5650_TDM_CTRL_4, 4, rt5645_tdm_dac_swap_select);
1232
1233static const struct snd_kcontrol_new rt5650_if1_dac2_tdm_sel_mux =
1234 SOC_DAPM_ENUM("IF1 DAC2 source", rt5650_tdm_dac2_enum);
1235
1236static SOC_ENUM_SINGLE_DECL(rt5650_tdm_dac3_enum,
1237 RT5650_TDM_CTRL_4, 0, rt5645_tdm_dac_swap_select);
1238
1239static const struct snd_kcontrol_new rt5650_if1_dac3_tdm_sel_mux =
1240 SOC_DAPM_ENUM("IF1 DAC3 source", rt5650_tdm_dac3_enum);
1241
Bard Liao5c4ca992015-01-21 20:50:15 +0800[diff] [blame]1242/* MX-2d [3] [2] */
1243static const char * const rt5650_a_dac1_src[] = {
1244 "DAC1", "Stereo DAC Mixer"
1245};
1246
1247static SOC_ENUM_SINGLE_DECL(
1248 rt5650_a_dac1_l_enum, RT5650_A_DAC_SOUR,
1249 RT5650_A_DAC1_L_IN_SFT, rt5650_a_dac1_src);
1250
1251static const struct snd_kcontrol_new rt5650_a_dac1_l_mux =
1252 SOC_DAPM_ENUM("A DAC1 L source", rt5650_a_dac1_l_enum);
1253
1254static SOC_ENUM_SINGLE_DECL(
1255 rt5650_a_dac1_r_enum, RT5650_A_DAC_SOUR,
1256 RT5650_A_DAC1_R_IN_SFT, rt5650_a_dac1_src);
1257
1258static const struct snd_kcontrol_new rt5650_a_dac1_r_mux =
1259 SOC_DAPM_ENUM("A DAC1 R source", rt5650_a_dac1_r_enum);
1260
1261/* MX-2d [1] [0] */
1262static const char * const rt5650_a_dac2_src[] = {
1263 "Stereo DAC Mixer", "Mono DAC Mixer"
1264};
1265
1266static SOC_ENUM_SINGLE_DECL(
1267 rt5650_a_dac2_l_enum, RT5650_A_DAC_SOUR,
1268 RT5650_A_DAC2_L_IN_SFT, rt5650_a_dac2_src);
1269
1270static const struct snd_kcontrol_new rt5650_a_dac2_l_mux =
1271 SOC_DAPM_ENUM("A DAC2 L source", rt5650_a_dac2_l_enum);
1272
1273static SOC_ENUM_SINGLE_DECL(
1274 rt5650_a_dac2_r_enum, RT5650_A_DAC_SOUR,
1275 RT5650_A_DAC2_R_IN_SFT, rt5650_a_dac2_src);
1276
1277static const struct snd_kcontrol_new rt5650_a_dac2_r_mux =
1278 SOC_DAPM_ENUM("A DAC2 R source", rt5650_a_dac2_r_enum);
1279
Oder Chiou1319b2f2014-04-28 19:59:10 +0800[diff] [blame]1280/* MX-2F [13:12] */
1281static const char * const rt5645_if2_adc_in_src[] = {
1282 "IF_ADC1", "IF_ADC2", "VAD_ADC"
1283};
1284
1285static SOC_ENUM_SINGLE_DECL(
1286 rt5645_if2_adc_in_enum, RT5645_DIG_INF1_DATA,
1287 RT5645_IF2_ADC_IN_SFT, rt5645_if2_adc_in_src);
1288
1289static const struct snd_kcontrol_new rt5645_if2_adc_in_mux =
1290 SOC_DAPM_ENUM("IF2 ADC IN source", rt5645_if2_adc_in_enum);
1291
1292/* MX-2F [1:0] */
1293static const char * const rt5645_if3_adc_in_src[] = {
1294 "IF_ADC1", "IF_ADC2", "VAD_ADC"
1295};
1296
1297static SOC_ENUM_SINGLE_DECL(
1298 rt5645_if3_adc_in_enum, RT5645_DIG_INF1_DATA,
1299 RT5645_IF3_ADC_IN_SFT, rt5645_if3_adc_in_src);
1300
1301static const struct snd_kcontrol_new rt5645_if3_adc_in_mux =
1302 SOC_DAPM_ENUM("IF3 ADC IN source", rt5645_if3_adc_in_enum);
1303
1304/* MX-31 [15] [13] [11] [9] */
1305static const char * const rt5645_pdm_src[] = {
1306 "Mono DAC", "Stereo DAC"
1307};
1308
1309static SOC_ENUM_SINGLE_DECL(
1310 rt5645_pdm1_l_enum, RT5645_PDM_OUT_CTRL,
1311 RT5645_PDM1_L_SFT, rt5645_pdm_src);
1312
1313static const struct snd_kcontrol_new rt5645_pdm1_l_mux =
1314 SOC_DAPM_ENUM("PDM1 L source", rt5645_pdm1_l_enum);
1315
1316static SOC_ENUM_SINGLE_DECL(
1317 rt5645_pdm1_r_enum, RT5645_PDM_OUT_CTRL,
1318 RT5645_PDM1_R_SFT, rt5645_pdm_src);
1319
1320static const struct snd_kcontrol_new rt5645_pdm1_r_mux =
1321 SOC_DAPM_ENUM("PDM1 R source", rt5645_pdm1_r_enum);
1322
1323/* MX-9D [9:8] */
1324static const char * const rt5645_vad_adc_src[] = {
1325 "Sto1 ADC L", "Mono ADC L", "Mono ADC R"
1326};
1327
1328static SOC_ENUM_SINGLE_DECL(
1329 rt5645_vad_adc_enum, RT5645_VAD_CTRL4,
1330 RT5645_VAD_SEL_SFT, rt5645_vad_adc_src);
1331
1332static const struct snd_kcontrol_new rt5645_vad_adc_mux =
1333 SOC_DAPM_ENUM("VAD ADC source", rt5645_vad_adc_enum);
1334
1335static const struct snd_kcontrol_new spk_l_vol_control =
1336 SOC_DAPM_SINGLE_AUTODISABLE("Switch", RT5645_SPK_VOL,
1337 RT5645_L_MUTE_SFT, 1, 1);
1338
1339static const struct snd_kcontrol_new spk_r_vol_control =
1340 SOC_DAPM_SINGLE_AUTODISABLE("Switch", RT5645_SPK_VOL,
1341 RT5645_R_MUTE_SFT, 1, 1);
1342
1343static const struct snd_kcontrol_new hp_l_vol_control =
1344 SOC_DAPM_SINGLE_AUTODISABLE("Switch", RT5645_HP_VOL,
1345 RT5645_L_MUTE_SFT, 1, 1);
1346
1347static const struct snd_kcontrol_new hp_r_vol_control =
1348 SOC_DAPM_SINGLE_AUTODISABLE("Switch", RT5645_HP_VOL,
1349 RT5645_R_MUTE_SFT, 1, 1);
1350
1351static const struct snd_kcontrol_new pdm1_l_vol_control =
1352 SOC_DAPM_SINGLE_AUTODISABLE("Switch", RT5645_PDM_OUT_CTRL,
1353 RT5645_M_PDM1_L, 1, 1);
1354
1355static const struct snd_kcontrol_new pdm1_r_vol_control =
1356 SOC_DAPM_SINGLE_AUTODISABLE("Switch", RT5645_PDM_OUT_CTRL,
1357 RT5645_M_PDM1_R, 1, 1);
1358
1359static void hp_amp_power(struct snd_soc_codec *codec, int on)
1360{
1361 static int hp_amp_power_count;
1362 struct rt5645_priv *rt5645 = snd_soc_codec_get_drvdata(codec);
1363
1364 if (on) {
1365 if (hp_amp_power_count <= 0) {
John Lind12d6c42015-05-12 20:43:02 +0800[diff] [blame]1366 if (rt5645->codec_type == CODEC_TYPE_RT5650) {
1367 snd_soc_write(codec, RT5645_CHARGE_PUMP,
1368 0x0e06);
1369 snd_soc_write(codec, RT5645_DEPOP_M1, 0x001d);
1370 regmap_write(rt5645->regmap, RT5645_PR_BASE +
1371 0x3e, 0x7400);
1372 snd_soc_write(codec, RT5645_DEPOP_M3, 0x0737);
1373 regmap_write(rt5645->regmap, RT5645_PR_BASE +
1374 RT5645_MAMP_INT_REG2, 0xfc00);
1375 snd_soc_write(codec, RT5645_DEPOP_M2, 0x1140);
1376 } else {
1377 /* depop parameters */
1378 snd_soc_update_bits(codec, RT5645_DEPOP_M2,
1379 RT5645_DEPOP_MASK, RT5645_DEPOP_MAN);
1380 snd_soc_write(codec, RT5645_DEPOP_M1, 0x000d);
1381 regmap_write(rt5645->regmap, RT5645_PR_BASE +
1382 RT5645_HP_DCC_INT1, 0x9f01);
1383 mdelay(150);
1384 /* headphone amp power on */
1385 snd_soc_update_bits(codec, RT5645_PWR_ANLG1,
1386 RT5645_PWR_FV1 | RT5645_PWR_FV2, 0);
1387 snd_soc_update_bits(codec, RT5645_PWR_VOL,
1388 RT5645_PWR_HV_L | RT5645_PWR_HV_R,
1389 RT5645_PWR_HV_L | RT5645_PWR_HV_R);
1390 snd_soc_update_bits(codec, RT5645_PWR_ANLG1,
1391 RT5645_PWR_HP_L | RT5645_PWR_HP_R |
1392 RT5645_PWR_HA,
1393 RT5645_PWR_HP_L | RT5645_PWR_HP_R |
1394 RT5645_PWR_HA);
1395 mdelay(5);
1396 snd_soc_update_bits(codec, RT5645_PWR_ANLG1,
1397 RT5645_PWR_FV1 | RT5645_PWR_FV2,
1398 RT5645_PWR_FV1 | RT5645_PWR_FV2);
Oder Chiou1319b2f2014-04-28 19:59:10 +0800[diff] [blame]1399
John Lind12d6c42015-05-12 20:43:02 +0800[diff] [blame]1400 snd_soc_update_bits(codec, RT5645_DEPOP_M1,
1401 RT5645_HP_CO_MASK | RT5645_HP_SG_MASK,
1402 RT5645_HP_CO_EN | RT5645_HP_SG_EN);
1403 regmap_write(rt5645->regmap, RT5645_PR_BASE +
1404 0x14, 0x1aaa);
1405 regmap_write(rt5645->regmap, RT5645_PR_BASE +
1406 0x24, 0x0430);
1407 }
Oder Chiou1319b2f2014-04-28 19:59:10 +0800[diff] [blame]1408 }
1409 hp_amp_power_count++;
1410 } else {
1411 hp_amp_power_count--;
1412 if (hp_amp_power_count <= 0) {
John Lind12d6c42015-05-12 20:43:02 +0800[diff] [blame]1413 if (rt5645->codec_type == CODEC_TYPE_RT5650) {
1414 regmap_write(rt5645->regmap, RT5645_PR_BASE +
1415 0x3e, 0x7400);
1416 snd_soc_write(codec, RT5645_DEPOP_M3, 0x0737);
1417 regmap_write(rt5645->regmap, RT5645_PR_BASE +
1418 RT5645_MAMP_INT_REG2, 0xfc00);
1419 snd_soc_write(codec, RT5645_DEPOP_M2, 0x1140);
1420 msleep(100);
1421 snd_soc_write(codec, RT5645_DEPOP_M1, 0x0001);
1422
1423 } else {
1424 snd_soc_update_bits(codec, RT5645_DEPOP_M1,
1425 RT5645_HP_SG_MASK |
1426 RT5645_HP_L_SMT_MASK |
1427 RT5645_HP_R_SMT_MASK,
1428 RT5645_HP_SG_DIS |
1429 RT5645_HP_L_SMT_DIS |
1430 RT5645_HP_R_SMT_DIS);
1431 /* headphone amp power down */
1432 snd_soc_write(codec, RT5645_DEPOP_M1, 0x0000);
1433 snd_soc_update_bits(codec, RT5645_PWR_ANLG1,
1434 RT5645_PWR_HP_L | RT5645_PWR_HP_R |
1435 RT5645_PWR_HA, 0);
1436 snd_soc_update_bits(codec, RT5645_DEPOP_M2,
1437 RT5645_DEPOP_MASK, 0);
1438 }
Oder Chiou1319b2f2014-04-28 19:59:10 +0800[diff] [blame]1439 }
1440 }
1441}
1442
1443static int rt5645_hp_event(struct snd_soc_dapm_widget *w,
1444 struct snd_kcontrol *kcontrol, int event)
1445{
Lars-Peter Clausenc5f596c2015-01-15 12:52:13 +0100[diff] [blame]1446 struct snd_soc_codec *codec = snd_soc_dapm_to_codec(w->dapm);
Oder Chiou1319b2f2014-04-28 19:59:10 +0800[diff] [blame]1447 struct rt5645_priv *rt5645 = snd_soc_codec_get_drvdata(codec);
1448
1449 switch (event) {
1450 case SND_SOC_DAPM_POST_PMU:
1451 hp_amp_power(codec, 1);
1452 /* headphone unmute sequence */
John Lind12d6c42015-05-12 20:43:02 +0800[diff] [blame]1453 if (rt5645->codec_type == CODEC_TYPE_RT5645) {
Bard Liao5c4ca992015-01-21 20:50:15 +0800[diff] [blame]1454 snd_soc_update_bits(codec, RT5645_DEPOP_M3,
1455 RT5645_CP_FQ1_MASK | RT5645_CP_FQ2_MASK |
1456 RT5645_CP_FQ3_MASK,
1457 (RT5645_CP_FQ_192_KHZ << RT5645_CP_FQ1_SFT) |
1458 (RT5645_CP_FQ_12_KHZ << RT5645_CP_FQ2_SFT) |
1459 (RT5645_CP_FQ_192_KHZ << RT5645_CP_FQ3_SFT));
John Lind12d6c42015-05-12 20:43:02 +0800[diff] [blame]1460 regmap_write(rt5645->regmap, RT5645_PR_BASE +
1461 RT5645_MAMP_INT_REG2, 0xfc00);
1462 snd_soc_update_bits(codec, RT5645_DEPOP_M1,
1463 RT5645_SMT_TRIG_MASK, RT5645_SMT_TRIG_EN);
1464 snd_soc_update_bits(codec, RT5645_DEPOP_M1,
1465 RT5645_RSTN_MASK, RT5645_RSTN_EN);
1466 snd_soc_update_bits(codec, RT5645_DEPOP_M1,
1467 RT5645_RSTN_MASK | RT5645_HP_L_SMT_MASK |
1468 RT5645_HP_R_SMT_MASK, RT5645_RSTN_DIS |
1469 RT5645_HP_L_SMT_EN | RT5645_HP_R_SMT_EN);
1470 msleep(40);
1471 snd_soc_update_bits(codec, RT5645_DEPOP_M1,
1472 RT5645_HP_SG_MASK | RT5645_HP_L_SMT_MASK |
1473 RT5645_HP_R_SMT_MASK, RT5645_HP_SG_DIS |
1474 RT5645_HP_L_SMT_DIS | RT5645_HP_R_SMT_DIS);
Bard Liao5c4ca992015-01-21 20:50:15 +0800[diff] [blame]1475 }
Oder Chiou1319b2f2014-04-28 19:59:10 +0800[diff] [blame]1476 break;
1477
1478 case SND_SOC_DAPM_PRE_PMD:
1479 /* headphone mute sequence */
John Lind12d6c42015-05-12 20:43:02 +0800[diff] [blame]1480 if (rt5645->codec_type == CODEC_TYPE_RT5645) {
Bard Liao5c4ca992015-01-21 20:50:15 +0800[diff] [blame]1481 snd_soc_update_bits(codec, RT5645_DEPOP_M3,
1482 RT5645_CP_FQ1_MASK | RT5645_CP_FQ2_MASK |
1483 RT5645_CP_FQ3_MASK,
1484 (RT5645_CP_FQ_96_KHZ << RT5645_CP_FQ1_SFT) |
1485 (RT5645_CP_FQ_12_KHZ << RT5645_CP_FQ2_SFT) |
1486 (RT5645_CP_FQ_96_KHZ << RT5645_CP_FQ3_SFT));
John Lind12d6c42015-05-12 20:43:02 +0800[diff] [blame]1487 regmap_write(rt5645->regmap, RT5645_PR_BASE +
1488 RT5645_MAMP_INT_REG2, 0xfc00);
1489 snd_soc_update_bits(codec, RT5645_DEPOP_M1,
1490 RT5645_HP_SG_MASK, RT5645_HP_SG_EN);
1491 snd_soc_update_bits(codec, RT5645_DEPOP_M1,
1492 RT5645_RSTP_MASK, RT5645_RSTP_EN);
1493 snd_soc_update_bits(codec, RT5645_DEPOP_M1,
1494 RT5645_RSTP_MASK | RT5645_HP_L_SMT_MASK |
1495 RT5645_HP_R_SMT_MASK, RT5645_RSTP_DIS |
1496 RT5645_HP_L_SMT_EN | RT5645_HP_R_SMT_EN);
1497 msleep(30);
Bard Liao5c4ca992015-01-21 20:50:15 +0800[diff] [blame]1498 }
Oder Chiou1319b2f2014-04-28 19:59:10 +0800[diff] [blame]1499 hp_amp_power(codec, 0);
1500 break;
1501
1502 default:
1503 return 0;
1504 }
1505
1506 return 0;
1507}
1508
1509static int rt5645_spk_event(struct snd_soc_dapm_widget *w,
1510 struct snd_kcontrol *kcontrol, int event)
1511{
Lars-Peter Clausenc5f596c2015-01-15 12:52:13 +0100[diff] [blame]1512 struct snd_soc_codec *codec = snd_soc_dapm_to_codec(w->dapm);
Oder Chiou1319b2f2014-04-28 19:59:10 +0800[diff] [blame]1513
1514 switch (event) {
1515 case SND_SOC_DAPM_POST_PMU:
1516 snd_soc_update_bits(codec, RT5645_PWR_DIG1,
1517 RT5645_PWR_CLS_D | RT5645_PWR_CLS_D_R |
1518 RT5645_PWR_CLS_D_L,
1519 RT5645_PWR_CLS_D | RT5645_PWR_CLS_D_R |
1520 RT5645_PWR_CLS_D_L);
1521 break;
1522
1523 case SND_SOC_DAPM_PRE_PMD:
1524 snd_soc_update_bits(codec, RT5645_PWR_DIG1,
1525 RT5645_PWR_CLS_D | RT5645_PWR_CLS_D_R |
1526 RT5645_PWR_CLS_D_L, 0);
1527 break;
1528
1529 default:
1530 return 0;
1531 }
1532
1533 return 0;
1534}
1535
1536static int rt5645_lout_event(struct snd_soc_dapm_widget *w,
1537 struct snd_kcontrol *kcontrol, int event)
1538{
Lars-Peter Clausenc5f596c2015-01-15 12:52:13 +0100[diff] [blame]1539 struct snd_soc_codec *codec = snd_soc_dapm_to_codec(w->dapm);
Oder Chiou1319b2f2014-04-28 19:59:10 +0800[diff] [blame]1540
1541 switch (event) {
1542 case SND_SOC_DAPM_POST_PMU:
1543 hp_amp_power(codec, 1);
1544 snd_soc_update_bits(codec, RT5645_PWR_ANLG1,
1545 RT5645_PWR_LM, RT5645_PWR_LM);
1546 snd_soc_update_bits(codec, RT5645_LOUT1,
1547 RT5645_L_MUTE | RT5645_R_MUTE, 0);
1548 break;
1549
1550 case SND_SOC_DAPM_PRE_PMD:
1551 snd_soc_update_bits(codec, RT5645_LOUT1,
1552 RT5645_L_MUTE | RT5645_R_MUTE,
1553 RT5645_L_MUTE | RT5645_R_MUTE);
1554 snd_soc_update_bits(codec, RT5645_PWR_ANLG1,
1555 RT5645_PWR_LM, 0);
1556 hp_amp_power(codec, 0);
1557 break;
1558
1559 default:
1560 return 0;
1561 }
1562
1563 return 0;
1564}
1565
1566static int rt5645_bst2_event(struct snd_soc_dapm_widget *w,
1567 struct snd_kcontrol *kcontrol, int event)
1568{
Lars-Peter Clausenc5f596c2015-01-15 12:52:13 +0100[diff] [blame]1569 struct snd_soc_codec *codec = snd_soc_dapm_to_codec(w->dapm);
Oder Chiou1319b2f2014-04-28 19:59:10 +0800[diff] [blame]1570
1571 switch (event) {
1572 case SND_SOC_DAPM_POST_PMU:
1573 snd_soc_update_bits(codec, RT5645_PWR_ANLG2,
1574 RT5645_PWR_BST2_P, RT5645_PWR_BST2_P);
1575 break;
1576
1577 case SND_SOC_DAPM_PRE_PMD:
1578 snd_soc_update_bits(codec, RT5645_PWR_ANLG2,
1579 RT5645_PWR_BST2_P, 0);
1580 break;
1581
1582 default:
1583 return 0;
1584 }
1585
1586 return 0;
1587}
1588
1589static const struct snd_soc_dapm_widget rt5645_dapm_widgets[] = {
1590 SND_SOC_DAPM_SUPPLY("LDO2", RT5645_PWR_MIXER,
1591 RT5645_PWR_LDO2_BIT, 0, NULL, 0),
1592 SND_SOC_DAPM_SUPPLY("PLL1", RT5645_PWR_ANLG2,
1593 RT5645_PWR_PLL_BIT, 0, NULL, 0),
1594
1595 SND_SOC_DAPM_SUPPLY("JD Power", RT5645_PWR_ANLG2,
1596 RT5645_PWR_JD1_BIT, 0, NULL, 0),
1597 SND_SOC_DAPM_SUPPLY("Mic Det Power", RT5645_PWR_VOL,
1598 RT5645_PWR_MIC_DET_BIT, 0, NULL, 0),
1599
Bard Liao9e268352014-10-31 15:37:55 +0800[diff] [blame]1600 /* ASRC */
1601 SND_SOC_DAPM_SUPPLY_S("I2S1 ASRC", 1, RT5645_ASRC_1,
1602 11, 0, NULL, 0),
1603 SND_SOC_DAPM_SUPPLY_S("I2S2 ASRC", 1, RT5645_ASRC_1,
1604 12, 0, NULL, 0),
1605 SND_SOC_DAPM_SUPPLY_S("DAC STO ASRC", 1, RT5645_ASRC_1,
1606 10, 0, NULL, 0),
1607 SND_SOC_DAPM_SUPPLY_S("DAC MONO L ASRC", 1, RT5645_ASRC_1,
1608 9, 0, NULL, 0),
1609 SND_SOC_DAPM_SUPPLY_S("DAC MONO R ASRC", 1, RT5645_ASRC_1,
1610 8, 0, NULL, 0),
1611 SND_SOC_DAPM_SUPPLY_S("DMIC STO1 ASRC", 1, RT5645_ASRC_1,
1612 7, 0, NULL, 0),
1613 SND_SOC_DAPM_SUPPLY_S("DMIC MONO L ASRC", 1, RT5645_ASRC_1,
1614 5, 0, NULL, 0),
1615 SND_SOC_DAPM_SUPPLY_S("DMIC MONO R ASRC", 1, RT5645_ASRC_1,
1616 4, 0, NULL, 0),
1617 SND_SOC_DAPM_SUPPLY_S("ADC STO1 ASRC", 1, RT5645_ASRC_1,
1618 3, 0, NULL, 0),
1619 SND_SOC_DAPM_SUPPLY_S("ADC MONO L ASRC", 1, RT5645_ASRC_1,
1620 1, 0, NULL, 0),
1621 SND_SOC_DAPM_SUPPLY_S("ADC MONO R ASRC", 1, RT5645_ASRC_1,
1622 0, 0, NULL, 0),
1623
Oder Chiou1319b2f2014-04-28 19:59:10 +0800[diff] [blame]1624 /* Input Side */
1625 /* micbias */
1626 SND_SOC_DAPM_MICBIAS("micbias1", RT5645_PWR_ANLG2,
1627 RT5645_PWR_MB1_BIT, 0),
1628 SND_SOC_DAPM_MICBIAS("micbias2", RT5645_PWR_ANLG2,
1629 RT5645_PWR_MB2_BIT, 0),
1630 /* Input Lines */
1631 SND_SOC_DAPM_INPUT("DMIC L1"),
1632 SND_SOC_DAPM_INPUT("DMIC R1"),
1633 SND_SOC_DAPM_INPUT("DMIC L2"),
1634 SND_SOC_DAPM_INPUT("DMIC R2"),
1635
1636 SND_SOC_DAPM_INPUT("IN1P"),
1637 SND_SOC_DAPM_INPUT("IN1N"),
1638 SND_SOC_DAPM_INPUT("IN2P"),
1639 SND_SOC_DAPM_INPUT("IN2N"),
1640
1641 SND_SOC_DAPM_INPUT("Haptic Generator"),
1642
1643 SND_SOC_DAPM_PGA("DMIC1", SND_SOC_NOPM, 0, 0, NULL, 0),
1644 SND_SOC_DAPM_PGA("DMIC2", SND_SOC_NOPM, 0, 0, NULL, 0),
1645 SND_SOC_DAPM_SUPPLY("DMIC CLK", SND_SOC_NOPM, 0, 0,
1646 set_dmic_clk, SND_SOC_DAPM_PRE_PMU),
1647 SND_SOC_DAPM_SUPPLY("DMIC1 Power", RT5645_DMIC_CTRL1,
1648 RT5645_DMIC_1_EN_SFT, 0, NULL, 0),
1649 SND_SOC_DAPM_SUPPLY("DMIC2 Power", RT5645_DMIC_CTRL1,
1650 RT5645_DMIC_2_EN_SFT, 0, NULL, 0),
1651 /* Boost */
1652 SND_SOC_DAPM_PGA("BST1", RT5645_PWR_ANLG2,
1653 RT5645_PWR_BST1_BIT, 0, NULL, 0),
1654 SND_SOC_DAPM_PGA_E("BST2", RT5645_PWR_ANLG2,
1655 RT5645_PWR_BST2_BIT, 0, NULL, 0, rt5645_bst2_event,
1656 SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMU),
1657 /* Input Volume */
1658 SND_SOC_DAPM_PGA("INL VOL", RT5645_PWR_VOL,
1659 RT5645_PWR_IN_L_BIT, 0, NULL, 0),
1660 SND_SOC_DAPM_PGA("INR VOL", RT5645_PWR_VOL,
1661 RT5645_PWR_IN_R_BIT, 0, NULL, 0),
1662 /* REC Mixer */
1663 SND_SOC_DAPM_MIXER("RECMIXL", RT5645_PWR_MIXER, RT5645_PWR_RM_L_BIT,
1664 0, rt5645_rec_l_mix, ARRAY_SIZE(rt5645_rec_l_mix)),
1665 SND_SOC_DAPM_MIXER("RECMIXR", RT5645_PWR_MIXER, RT5645_PWR_RM_R_BIT,
1666 0, rt5645_rec_r_mix, ARRAY_SIZE(rt5645_rec_r_mix)),
1667 /* ADCs */
1668 SND_SOC_DAPM_ADC("ADC L", NULL, SND_SOC_NOPM, 0, 0),
1669 SND_SOC_DAPM_ADC("ADC R", NULL, SND_SOC_NOPM, 0, 0),
1670
1671 SND_SOC_DAPM_SUPPLY("ADC L power", RT5645_PWR_DIG1,
1672 RT5645_PWR_ADC_L_BIT, 0, NULL, 0),
1673 SND_SOC_DAPM_SUPPLY("ADC R power", RT5645_PWR_DIG1,
1674 RT5645_PWR_ADC_R_BIT, 0, NULL, 0),
1675
1676 /* ADC Mux */
1677 SND_SOC_DAPM_MUX("Stereo1 DMIC Mux", SND_SOC_NOPM, 0, 0,
1678 &rt5645_sto1_dmic_mux),
1679 SND_SOC_DAPM_MUX("Stereo1 ADC L2 Mux", SND_SOC_NOPM, 0, 0,
1680 &rt5645_sto_adc2_mux),
1681 SND_SOC_DAPM_MUX("Stereo1 ADC R2 Mux", SND_SOC_NOPM, 0, 0,
1682 &rt5645_sto_adc2_mux),
1683 SND_SOC_DAPM_MUX("Stereo1 ADC L1 Mux", SND_SOC_NOPM, 0, 0,
1684 &rt5645_sto_adc1_mux),
1685 SND_SOC_DAPM_MUX("Stereo1 ADC R1 Mux", SND_SOC_NOPM, 0, 0,
1686 &rt5645_sto_adc1_mux),
1687 SND_SOC_DAPM_MUX("Mono DMIC L Mux", SND_SOC_NOPM, 0, 0,
1688 &rt5645_mono_dmic_l_mux),
1689 SND_SOC_DAPM_MUX("Mono DMIC R Mux", SND_SOC_NOPM, 0, 0,
1690 &rt5645_mono_dmic_r_mux),
1691 SND_SOC_DAPM_MUX("Mono ADC L2 Mux", SND_SOC_NOPM, 0, 0,
1692 &rt5645_mono_adc_l2_mux),
1693 SND_SOC_DAPM_MUX("Mono ADC L1 Mux", SND_SOC_NOPM, 0, 0,
1694 &rt5645_mono_adc_l1_mux),
1695 SND_SOC_DAPM_MUX("Mono ADC R1 Mux", SND_SOC_NOPM, 0, 0,
1696 &rt5645_mono_adc_r1_mux),
1697 SND_SOC_DAPM_MUX("Mono ADC R2 Mux", SND_SOC_NOPM, 0, 0,
1698 &rt5645_mono_adc_r2_mux),
1699 /* ADC Mixer */
1700
1701 SND_SOC_DAPM_SUPPLY_S("adc stereo1 filter", 1, RT5645_PWR_DIG2,
1702 RT5645_PWR_ADC_S1F_BIT, 0, NULL, 0),
Oder Chiou1319b2f2014-04-28 19:59:10 +0800[diff] [blame]1703 SND_SOC_DAPM_MIXER_E("Sto1 ADC MIXL", SND_SOC_NOPM, 0, 0,
1704 rt5645_sto1_adc_l_mix, ARRAY_SIZE(rt5645_sto1_adc_l_mix),
1705 NULL, 0),
1706 SND_SOC_DAPM_MIXER_E("Sto1 ADC MIXR", SND_SOC_NOPM, 0, 0,
1707 rt5645_sto1_adc_r_mix, ARRAY_SIZE(rt5645_sto1_adc_r_mix),
1708 NULL, 0),
1709 SND_SOC_DAPM_SUPPLY_S("adc mono left filter", 1, RT5645_PWR_DIG2,
1710 RT5645_PWR_ADC_MF_L_BIT, 0, NULL, 0),
1711 SND_SOC_DAPM_MIXER_E("Mono ADC MIXL", SND_SOC_NOPM, 0, 0,
1712 rt5645_mono_adc_l_mix, ARRAY_SIZE(rt5645_mono_adc_l_mix),
1713 NULL, 0),
1714 SND_SOC_DAPM_SUPPLY_S("adc mono right filter", 1, RT5645_PWR_DIG2,
1715 RT5645_PWR_ADC_MF_R_BIT, 0, NULL, 0),
1716 SND_SOC_DAPM_MIXER_E("Mono ADC MIXR", SND_SOC_NOPM, 0, 0,
1717 rt5645_mono_adc_r_mix, ARRAY_SIZE(rt5645_mono_adc_r_mix),
1718 NULL, 0),
1719
1720 /* ADC PGA */
1721 SND_SOC_DAPM_PGA("Stereo1 ADC MIXL", SND_SOC_NOPM, 0, 0, NULL, 0),
1722 SND_SOC_DAPM_PGA("Stereo1 ADC MIXR", SND_SOC_NOPM, 0, 0, NULL, 0),
1723 SND_SOC_DAPM_PGA("Sto2 ADC LR MIX", SND_SOC_NOPM, 0, 0, NULL, 0),
1724 SND_SOC_DAPM_PGA("VAD_ADC", SND_SOC_NOPM, 0, 0, NULL, 0),
1725 SND_SOC_DAPM_PGA("IF_ADC1", SND_SOC_NOPM, 0, 0, NULL, 0),
1726 SND_SOC_DAPM_PGA("IF_ADC2", SND_SOC_NOPM, 0, 0, NULL, 0),
1727 SND_SOC_DAPM_PGA("IF1_ADC1", SND_SOC_NOPM, 0, 0, NULL, 0),
1728 SND_SOC_DAPM_PGA("IF1_ADC2", SND_SOC_NOPM, 0, 0, NULL, 0),
1729 SND_SOC_DAPM_PGA("IF1_ADC3", SND_SOC_NOPM, 0, 0, NULL, 0),
1730 SND_SOC_DAPM_PGA("IF1_ADC4", SND_SOC_NOPM, 0, 0, NULL, 0),
1731
1732 /* IF1 2 Mux */
Oder Chiou1319b2f2014-04-28 19:59:10 +0800[diff] [blame]1733 SND_SOC_DAPM_MUX("IF2 ADC Mux", SND_SOC_NOPM,
1734 0, 0, &rt5645_if2_adc_in_mux),
1735
1736 /* Digital Interface */
1737 SND_SOC_DAPM_SUPPLY("I2S1", RT5645_PWR_DIG1,
1738 RT5645_PWR_I2S1_BIT, 0, NULL, 0),
Bard Liao786aa092015-05-05 21:42:00 +0800[diff] [blame]1739 SND_SOC_DAPM_PGA("IF1 DAC0", SND_SOC_NOPM, 0, 0, NULL, 0),
Oder Chiou1319b2f2014-04-28 19:59:10 +0800[diff] [blame]1740 SND_SOC_DAPM_PGA("IF1 DAC1", SND_SOC_NOPM, 0, 0, NULL, 0),
1741 SND_SOC_DAPM_PGA("IF1 DAC2", SND_SOC_NOPM, 0, 0, NULL, 0),
Bard Liao786aa092015-05-05 21:42:00 +0800[diff] [blame]1742 SND_SOC_DAPM_PGA("IF1 DAC3", SND_SOC_NOPM, 0, 0, NULL, 0),
Oder Chiou1319b2f2014-04-28 19:59:10 +0800[diff] [blame]1743 SND_SOC_DAPM_PGA("IF1 ADC", SND_SOC_NOPM, 0, 0, NULL, 0),
1744 SND_SOC_DAPM_PGA("IF1 ADC L", SND_SOC_NOPM, 0, 0, NULL, 0),
1745 SND_SOC_DAPM_PGA("IF1 ADC R", SND_SOC_NOPM, 0, 0, NULL, 0),
1746 SND_SOC_DAPM_SUPPLY("I2S2", RT5645_PWR_DIG1,
1747 RT5645_PWR_I2S2_BIT, 0, NULL, 0),
1748 SND_SOC_DAPM_PGA("IF2 DAC", SND_SOC_NOPM, 0, 0, NULL, 0),
1749 SND_SOC_DAPM_PGA("IF2 DAC L", SND_SOC_NOPM, 0, 0, NULL, 0),
1750 SND_SOC_DAPM_PGA("IF2 DAC R", SND_SOC_NOPM, 0, 0, NULL, 0),
1751 SND_SOC_DAPM_PGA("IF2 ADC", SND_SOC_NOPM, 0, 0, NULL, 0),
1752
1753 /* Digital Interface Select */
1754 SND_SOC_DAPM_MUX("VAD ADC Mux", SND_SOC_NOPM,
1755 0, 0, &rt5645_vad_adc_mux),
1756
1757 /* Audio Interface */
1758 SND_SOC_DAPM_AIF_IN("AIF1RX", "AIF1 Playback", 0, SND_SOC_NOPM, 0, 0),
1759 SND_SOC_DAPM_AIF_OUT("AIF1TX", "AIF1 Capture", 0, SND_SOC_NOPM, 0, 0),
1760 SND_SOC_DAPM_AIF_IN("AIF2RX", "AIF2 Playback", 0, SND_SOC_NOPM, 0, 0),
1761 SND_SOC_DAPM_AIF_OUT("AIF2TX", "AIF2 Capture", 0, SND_SOC_NOPM, 0, 0),
1762
1763 /* Output Side */
1764 /* DAC mixer before sound effect */
1765 SND_SOC_DAPM_MIXER("DAC1 MIXL", SND_SOC_NOPM, 0, 0,
1766 rt5645_dac_l_mix, ARRAY_SIZE(rt5645_dac_l_mix)),
1767 SND_SOC_DAPM_MIXER("DAC1 MIXR", SND_SOC_NOPM, 0, 0,
1768 rt5645_dac_r_mix, ARRAY_SIZE(rt5645_dac_r_mix)),
1769
1770 /* DAC2 channel Mux */
1771 SND_SOC_DAPM_MUX("DAC L2 Mux", SND_SOC_NOPM, 0, 0, &rt5645_dac_l2_mux),
1772 SND_SOC_DAPM_MUX("DAC R2 Mux", SND_SOC_NOPM, 0, 0, &rt5645_dac_r2_mux),
1773 SND_SOC_DAPM_PGA("DAC L2 Volume", RT5645_PWR_DIG1,
1774 RT5645_PWR_DAC_L2_BIT, 0, NULL, 0),
1775 SND_SOC_DAPM_PGA("DAC R2 Volume", RT5645_PWR_DIG1,
1776 RT5645_PWR_DAC_R2_BIT, 0, NULL, 0),
1777
1778 SND_SOC_DAPM_MUX("DAC1 L Mux", SND_SOC_NOPM, 0, 0, &rt5645_dac1l_mux),
1779 SND_SOC_DAPM_MUX("DAC1 R Mux", SND_SOC_NOPM, 0, 0, &rt5645_dac1r_mux),
1780
1781 /* DAC Mixer */
1782 SND_SOC_DAPM_SUPPLY_S("dac stereo1 filter", 1, RT5645_PWR_DIG2,
1783 RT5645_PWR_DAC_S1F_BIT, 0, NULL, 0),
1784 SND_SOC_DAPM_SUPPLY_S("dac mono left filter", 1, RT5645_PWR_DIG2,
1785 RT5645_PWR_DAC_MF_L_BIT, 0, NULL, 0),
1786 SND_SOC_DAPM_SUPPLY_S("dac mono right filter", 1, RT5645_PWR_DIG2,
1787 RT5645_PWR_DAC_MF_R_BIT, 0, NULL, 0),
1788 SND_SOC_DAPM_MIXER("Stereo DAC MIXL", SND_SOC_NOPM, 0, 0,
1789 rt5645_sto_dac_l_mix, ARRAY_SIZE(rt5645_sto_dac_l_mix)),
1790 SND_SOC_DAPM_MIXER("Stereo DAC MIXR", SND_SOC_NOPM, 0, 0,
1791 rt5645_sto_dac_r_mix, ARRAY_SIZE(rt5645_sto_dac_r_mix)),
1792 SND_SOC_DAPM_MIXER("Mono DAC MIXL", SND_SOC_NOPM, 0, 0,
1793 rt5645_mono_dac_l_mix, ARRAY_SIZE(rt5645_mono_dac_l_mix)),
1794 SND_SOC_DAPM_MIXER("Mono DAC MIXR", SND_SOC_NOPM, 0, 0,
1795 rt5645_mono_dac_r_mix, ARRAY_SIZE(rt5645_mono_dac_r_mix)),
1796 SND_SOC_DAPM_MIXER("DAC MIXL", SND_SOC_NOPM, 0, 0,
1797 rt5645_dig_l_mix, ARRAY_SIZE(rt5645_dig_l_mix)),
1798 SND_SOC_DAPM_MIXER("DAC MIXR", SND_SOC_NOPM, 0, 0,
1799 rt5645_dig_r_mix, ARRAY_SIZE(rt5645_dig_r_mix)),
1800
1801 /* DACs */
1802 SND_SOC_DAPM_DAC("DAC L1", NULL, RT5645_PWR_DIG1, RT5645_PWR_DAC_L1_BIT,
1803 0),
1804 SND_SOC_DAPM_DAC("DAC L2", NULL, RT5645_PWR_DIG1, RT5645_PWR_DAC_L2_BIT,
1805 0),
1806 SND_SOC_DAPM_DAC("DAC R1", NULL, RT5645_PWR_DIG1, RT5645_PWR_DAC_R1_BIT,
1807 0),
1808 SND_SOC_DAPM_DAC("DAC R2", NULL, RT5645_PWR_DIG1, RT5645_PWR_DAC_R2_BIT,
1809 0),
1810 /* OUT Mixer */
1811 SND_SOC_DAPM_MIXER("SPK MIXL", RT5645_PWR_MIXER, RT5645_PWR_SM_L_BIT,
1812 0, rt5645_spk_l_mix, ARRAY_SIZE(rt5645_spk_l_mix)),
1813 SND_SOC_DAPM_MIXER("SPK MIXR", RT5645_PWR_MIXER, RT5645_PWR_SM_R_BIT,
1814 0, rt5645_spk_r_mix, ARRAY_SIZE(rt5645_spk_r_mix)),
1815 SND_SOC_DAPM_MIXER("OUT MIXL", RT5645_PWR_MIXER, RT5645_PWR_OM_L_BIT,
1816 0, rt5645_out_l_mix, ARRAY_SIZE(rt5645_out_l_mix)),
1817 SND_SOC_DAPM_MIXER("OUT MIXR", RT5645_PWR_MIXER, RT5645_PWR_OM_R_BIT,
1818 0, rt5645_out_r_mix, ARRAY_SIZE(rt5645_out_r_mix)),
1819 /* Ouput Volume */
1820 SND_SOC_DAPM_SWITCH("SPKVOL L", RT5645_PWR_VOL, RT5645_PWR_SV_L_BIT, 0,
1821 &spk_l_vol_control),
1822 SND_SOC_DAPM_SWITCH("SPKVOL R", RT5645_PWR_VOL, RT5645_PWR_SV_R_BIT, 0,
1823 &spk_r_vol_control),
1824 SND_SOC_DAPM_MIXER("HPOVOL MIXL", RT5645_PWR_VOL, RT5645_PWR_HV_L_BIT,
1825 0, rt5645_hpvoll_mix, ARRAY_SIZE(rt5645_hpvoll_mix)),
1826 SND_SOC_DAPM_MIXER("HPOVOL MIXR", RT5645_PWR_VOL, RT5645_PWR_HV_R_BIT,
1827 0, rt5645_hpvolr_mix, ARRAY_SIZE(rt5645_hpvolr_mix)),
1828 SND_SOC_DAPM_SUPPLY("HPOVOL MIXL Power", RT5645_PWR_MIXER,
1829 RT5645_PWR_HM_L_BIT, 0, NULL, 0),
1830 SND_SOC_DAPM_SUPPLY("HPOVOL MIXR Power", RT5645_PWR_MIXER,
1831 RT5645_PWR_HM_R_BIT, 0, NULL, 0),
1832 SND_SOC_DAPM_PGA("DAC 1", SND_SOC_NOPM, 0, 0, NULL, 0),
1833 SND_SOC_DAPM_PGA("DAC 2", SND_SOC_NOPM, 0, 0, NULL, 0),
1834 SND_SOC_DAPM_PGA("HPOVOL", SND_SOC_NOPM, 0, 0, NULL, 0),
1835 SND_SOC_DAPM_SWITCH("HPOVOL L", SND_SOC_NOPM, 0, 0, &hp_l_vol_control),
1836 SND_SOC_DAPM_SWITCH("HPOVOL R", SND_SOC_NOPM, 0, 0, &hp_r_vol_control),
1837
1838 /* HPO/LOUT/Mono Mixer */
1839 SND_SOC_DAPM_MIXER("SPOL MIX", SND_SOC_NOPM, 0, 0, rt5645_spo_l_mix,
1840 ARRAY_SIZE(rt5645_spo_l_mix)),
1841 SND_SOC_DAPM_MIXER("SPOR MIX", SND_SOC_NOPM, 0, 0, rt5645_spo_r_mix,
1842 ARRAY_SIZE(rt5645_spo_r_mix)),
1843 SND_SOC_DAPM_MIXER("HPO MIX", SND_SOC_NOPM, 0, 0, rt5645_hpo_mix,
1844 ARRAY_SIZE(rt5645_hpo_mix)),
1845 SND_SOC_DAPM_MIXER("LOUT MIX", SND_SOC_NOPM, 0, 0, rt5645_lout_mix,
1846 ARRAY_SIZE(rt5645_lout_mix)),
1847
1848 SND_SOC_DAPM_PGA_S("HP amp", 1, SND_SOC_NOPM, 0, 0, rt5645_hp_event,
1849 SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMU),
1850 SND_SOC_DAPM_PGA_S("LOUT amp", 1, SND_SOC_NOPM, 0, 0, rt5645_lout_event,
1851 SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMU),
1852 SND_SOC_DAPM_PGA_S("SPK amp", 2, SND_SOC_NOPM, 0, 0, rt5645_spk_event,
1853 SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMU),
1854
1855 /* PDM */
1856 SND_SOC_DAPM_SUPPLY("PDM1 Power", RT5645_PWR_DIG2, RT5645_PWR_PDM1_BIT,
1857 0, NULL, 0),
1858 SND_SOC_DAPM_MUX("PDM1 L Mux", SND_SOC_NOPM, 0, 0, &rt5645_pdm1_l_mux),
1859 SND_SOC_DAPM_MUX("PDM1 R Mux", SND_SOC_NOPM, 0, 0, &rt5645_pdm1_r_mux),
1860
1861 SND_SOC_DAPM_SWITCH("PDM1 L", SND_SOC_NOPM, 0, 0, &pdm1_l_vol_control),
1862 SND_SOC_DAPM_SWITCH("PDM1 R", SND_SOC_NOPM, 0, 0, &pdm1_r_vol_control),
1863
1864 /* Output Lines */
1865 SND_SOC_DAPM_OUTPUT("HPOL"),
1866 SND_SOC_DAPM_OUTPUT("HPOR"),
1867 SND_SOC_DAPM_OUTPUT("LOUTL"),
1868 SND_SOC_DAPM_OUTPUT("LOUTR"),
1869 SND_SOC_DAPM_OUTPUT("PDM1L"),
1870 SND_SOC_DAPM_OUTPUT("PDM1R"),
1871 SND_SOC_DAPM_OUTPUT("SPOL"),
1872 SND_SOC_DAPM_OUTPUT("SPOR"),
1873};
1874
Bard Liao83c09292015-06-29 14:20:50 +0800[diff] [blame]1875static const struct snd_soc_dapm_widget rt5645_specific_dapm_widgets[] = {
1876 SND_SOC_DAPM_MUX("RT5645 IF1 DAC1 L Mux", SND_SOC_NOPM, 0, 0,
1877 &rt5645_if1_dac0_tdm_sel_mux),
1878 SND_SOC_DAPM_MUX("RT5645 IF1 DAC1 R Mux", SND_SOC_NOPM, 0, 0,
1879 &rt5645_if1_dac1_tdm_sel_mux),
1880 SND_SOC_DAPM_MUX("RT5645 IF1 DAC2 L Mux", SND_SOC_NOPM, 0, 0,
1881 &rt5645_if1_dac2_tdm_sel_mux),
1882 SND_SOC_DAPM_MUX("RT5645 IF1 DAC2 R Mux", SND_SOC_NOPM, 0, 0,
1883 &rt5645_if1_dac3_tdm_sel_mux),
1884 SND_SOC_DAPM_MUX("RT5645 IF1 ADC Mux", SND_SOC_NOPM,
1885 0, 0, &rt5645_if1_adc_in_mux),
1886 SND_SOC_DAPM_MUX("RT5645 IF1 ADC1 Swap Mux", SND_SOC_NOPM,
1887 0, 0, &rt5645_if1_adc1_in_mux),
1888 SND_SOC_DAPM_MUX("RT5645 IF1 ADC2 Swap Mux", SND_SOC_NOPM,
1889 0, 0, &rt5645_if1_adc2_in_mux),
1890 SND_SOC_DAPM_MUX("RT5645 IF1 ADC3 Swap Mux", SND_SOC_NOPM,
1891 0, 0, &rt5645_if1_adc3_in_mux),
1892};
1893
Bard Liao5c4ca992015-01-21 20:50:15 +0800[diff] [blame]1894static const struct snd_soc_dapm_widget rt5650_specific_dapm_widgets[] = {
1895 SND_SOC_DAPM_MUX("A DAC1 L Mux", SND_SOC_NOPM,
1896 0, 0, &rt5650_a_dac1_l_mux),
1897 SND_SOC_DAPM_MUX("A DAC1 R Mux", SND_SOC_NOPM,
1898 0, 0, &rt5650_a_dac1_r_mux),
1899 SND_SOC_DAPM_MUX("A DAC2 L Mux", SND_SOC_NOPM,
1900 0, 0, &rt5650_a_dac2_l_mux),
1901 SND_SOC_DAPM_MUX("A DAC2 R Mux", SND_SOC_NOPM,
1902 0, 0, &rt5650_a_dac2_r_mux),
Michele Curti851b81e2015-06-15 10:44:11 +0800[diff] [blame]1903
1904 SND_SOC_DAPM_MUX("RT5650 IF1 ADC1 Swap Mux", SND_SOC_NOPM,
1905 0, 0, &rt5650_if1_adc1_in_mux),
1906 SND_SOC_DAPM_MUX("RT5650 IF1 ADC2 Swap Mux", SND_SOC_NOPM,
1907 0, 0, &rt5650_if1_adc2_in_mux),
1908 SND_SOC_DAPM_MUX("RT5650 IF1 ADC3 Swap Mux", SND_SOC_NOPM,
1909 0, 0, &rt5650_if1_adc3_in_mux),
1910 SND_SOC_DAPM_MUX("RT5650 IF1 ADC Mux", SND_SOC_NOPM,
1911 0, 0, &rt5650_if1_adc_in_mux),
1912
1913 SND_SOC_DAPM_MUX("RT5650 IF1 DAC1 L Mux", SND_SOC_NOPM, 0, 0,
1914 &rt5650_if1_dac0_tdm_sel_mux),
1915 SND_SOC_DAPM_MUX("RT5650 IF1 DAC1 R Mux", SND_SOC_NOPM, 0, 0,
1916 &rt5650_if1_dac1_tdm_sel_mux),
1917 SND_SOC_DAPM_MUX("RT5650 IF1 DAC2 L Mux", SND_SOC_NOPM, 0, 0,
1918 &rt5650_if1_dac2_tdm_sel_mux),
1919 SND_SOC_DAPM_MUX("RT5650 IF1 DAC2 R Mux", SND_SOC_NOPM, 0, 0,
1920 &rt5650_if1_dac3_tdm_sel_mux),
Bard Liao5c4ca992015-01-21 20:50:15 +0800[diff] [blame]1921};
1922
Oder Chiou1319b2f2014-04-28 19:59:10 +0800[diff] [blame]1923static const struct snd_soc_dapm_route rt5645_dapm_routes[] = {
Bard Liao9e268352014-10-31 15:37:55 +0800[diff] [blame]1924 { "adc stereo1 filter", NULL, "ADC STO1 ASRC", is_using_asrc },
Bard Liao9e268352014-10-31 15:37:55 +0800[diff] [blame]1925 { "adc mono left filter", NULL, "ADC MONO L ASRC", is_using_asrc },
1926 { "adc mono right filter", NULL, "ADC MONO R ASRC", is_using_asrc },
1927 { "dac mono left filter", NULL, "DAC MONO L ASRC", is_using_asrc },
1928 { "dac mono right filter", NULL, "DAC MONO R ASRC", is_using_asrc },
1929 { "dac stereo1 filter", NULL, "DAC STO ASRC", is_using_asrc },
1930
1931 { "I2S1", NULL, "I2S1 ASRC" },
1932 { "I2S2", NULL, "I2S2 ASRC" },
1933
Oder Chiou1319b2f2014-04-28 19:59:10 +0800[diff] [blame]1934 { "IN1P", NULL, "LDO2" },
1935 { "IN2P", NULL, "LDO2" },
1936
1937 { "DMIC1", NULL, "DMIC L1" },
1938 { "DMIC1", NULL, "DMIC R1" },
1939 { "DMIC2", NULL, "DMIC L2" },
1940 { "DMIC2", NULL, "DMIC R2" },
1941
1942 { "BST1", NULL, "IN1P" },
1943 { "BST1", NULL, "IN1N" },
1944 { "BST1", NULL, "JD Power" },
1945 { "BST1", NULL, "Mic Det Power" },
1946 { "BST2", NULL, "IN2P" },
1947 { "BST2", NULL, "IN2N" },
1948
1949 { "INL VOL", NULL, "IN2P" },
1950 { "INR VOL", NULL, "IN2N" },
1951
1952 { "RECMIXL", "HPOL Switch", "HPOL" },
1953 { "RECMIXL", "INL Switch", "INL VOL" },
1954 { "RECMIXL", "BST2 Switch", "BST2" },
1955 { "RECMIXL", "BST1 Switch", "BST1" },
1956 { "RECMIXL", "OUT MIXL Switch", "OUT MIXL" },
1957
1958 { "RECMIXR", "HPOR Switch", "HPOR" },
1959 { "RECMIXR", "INR Switch", "INR VOL" },
1960 { "RECMIXR", "BST2 Switch", "BST2" },
1961 { "RECMIXR", "BST1 Switch", "BST1" },
1962 { "RECMIXR", "OUT MIXR Switch", "OUT MIXR" },
1963
1964 { "ADC L", NULL, "RECMIXL" },
1965 { "ADC L", NULL, "ADC L power" },
1966 { "ADC R", NULL, "RECMIXR" },
1967 { "ADC R", NULL, "ADC R power" },
1968
1969 {"DMIC L1", NULL, "DMIC CLK"},
1970 {"DMIC L1", NULL, "DMIC1 Power"},
1971 {"DMIC R1", NULL, "DMIC CLK"},
1972 {"DMIC R1", NULL, "DMIC1 Power"},
1973 {"DMIC L2", NULL, "DMIC CLK"},
1974 {"DMIC L2", NULL, "DMIC2 Power"},
1975 {"DMIC R2", NULL, "DMIC CLK"},
1976 {"DMIC R2", NULL, "DMIC2 Power"},
1977
1978 { "Stereo1 DMIC Mux", "DMIC1", "DMIC1" },
1979 { "Stereo1 DMIC Mux", "DMIC2", "DMIC2" },
Bard Liao9e268352014-10-31 15:37:55 +0800[diff] [blame]1980 { "Stereo1 DMIC Mux", NULL, "DMIC STO1 ASRC" },
Oder Chiou1319b2f2014-04-28 19:59:10 +0800[diff] [blame]1981
1982 { "Mono DMIC L Mux", "DMIC1", "DMIC L1" },
1983 { "Mono DMIC L Mux", "DMIC2", "DMIC L2" },
Bard Liao9e268352014-10-31 15:37:55 +0800[diff] [blame]1984 { "Mono DMIC L Mux", NULL, "DMIC MONO L ASRC" },
Oder Chiou1319b2f2014-04-28 19:59:10 +0800[diff] [blame]1985
1986 { "Mono DMIC R Mux", "DMIC1", "DMIC R1" },
1987 { "Mono DMIC R Mux", "DMIC2", "DMIC R2" },
Bard Liao9e268352014-10-31 15:37:55 +0800[diff] [blame]1988 { "Mono DMIC R Mux", NULL, "DMIC MONO R ASRC" },
Oder Chiou1319b2f2014-04-28 19:59:10 +0800[diff] [blame]1989
1990 { "Stereo1 ADC L2 Mux", "DMIC", "Stereo1 DMIC Mux" },
1991 { "Stereo1 ADC L2 Mux", "DAC MIX", "DAC MIXL" },
1992 { "Stereo1 ADC L1 Mux", "ADC", "ADC L" },
1993 { "Stereo1 ADC L1 Mux", "DAC MIX", "DAC MIXL" },
1994
1995 { "Stereo1 ADC R1 Mux", "ADC", "ADC R" },
1996 { "Stereo1 ADC R1 Mux", "DAC MIX", "DAC MIXR" },
1997 { "Stereo1 ADC R2 Mux", "DMIC", "Stereo1 DMIC Mux" },
1998 { "Stereo1 ADC R2 Mux", "DAC MIX", "DAC MIXR" },
1999
2000 { "Mono ADC L2 Mux", "DMIC", "Mono DMIC L Mux" },
2001 { "Mono ADC L2 Mux", "Mono DAC MIXL", "Mono DAC MIXL" },
2002 { "Mono ADC L1 Mux", "Mono DAC MIXL", "Mono DAC MIXL" },
2003 { "Mono ADC L1 Mux", "ADC", "ADC L" },
2004
2005 { "Mono ADC R1 Mux", "Mono DAC MIXR", "Mono DAC MIXR" },
2006 { "Mono ADC R1 Mux", "ADC", "ADC R" },
2007 { "Mono ADC R2 Mux", "DMIC", "Mono DMIC R Mux" },
2008 { "Mono ADC R2 Mux", "Mono DAC MIXR", "Mono DAC MIXR" },
2009
2010 { "Sto1 ADC MIXL", "ADC1 Switch", "Stereo1 ADC L1 Mux" },
2011 { "Sto1 ADC MIXL", "ADC2 Switch", "Stereo1 ADC L2 Mux" },
2012 { "Sto1 ADC MIXR", "ADC1 Switch", "Stereo1 ADC R1 Mux" },
2013 { "Sto1 ADC MIXR", "ADC2 Switch", "Stereo1 ADC R2 Mux" },
2014
2015 { "Stereo1 ADC MIXL", NULL, "Sto1 ADC MIXL" },
2016 { "Stereo1 ADC MIXL", NULL, "adc stereo1 filter" },
2017 { "adc stereo1 filter", NULL, "PLL1", is_sys_clk_from_pll },
2018
2019 { "Stereo1 ADC MIXR", NULL, "Sto1 ADC MIXR" },
2020 { "Stereo1 ADC MIXR", NULL, "adc stereo1 filter" },
2021 { "adc stereo1 filter", NULL, "PLL1", is_sys_clk_from_pll },
2022
2023 { "Mono ADC MIXL", "ADC1 Switch", "Mono ADC L1 Mux" },
2024 { "Mono ADC MIXL", "ADC2 Switch", "Mono ADC L2 Mux" },
2025 { "Mono ADC MIXL", NULL, "adc mono left filter" },
2026 { "adc mono left filter", NULL, "PLL1", is_sys_clk_from_pll },
2027
2028 { "Mono ADC MIXR", "ADC1 Switch", "Mono ADC R1 Mux" },
2029 { "Mono ADC MIXR", "ADC2 Switch", "Mono ADC R2 Mux" },
2030 { "Mono ADC MIXR", NULL, "adc mono right filter" },
2031 { "adc mono right filter", NULL, "PLL1", is_sys_clk_from_pll },
2032
2033 { "VAD ADC Mux", "Sto1 ADC L", "Stereo1 ADC MIXL" },
2034 { "VAD ADC Mux", "Mono ADC L", "Mono ADC MIXL" },
2035 { "VAD ADC Mux", "Mono ADC R", "Mono ADC MIXR" },
2036
2037 { "IF_ADC1", NULL, "Stereo1 ADC MIXL" },
2038 { "IF_ADC1", NULL, "Stereo1 ADC MIXR" },
2039 { "IF_ADC2", NULL, "Mono ADC MIXL" },
2040 { "IF_ADC2", NULL, "Mono ADC MIXR" },
2041 { "VAD_ADC", NULL, "VAD ADC Mux" },
2042
Oder Chiou1319b2f2014-04-28 19:59:10 +0800[diff] [blame]2043 { "IF2 ADC Mux", "IF_ADC1", "IF_ADC1" },
2044 { "IF2 ADC Mux", "IF_ADC2", "IF_ADC2" },
2045 { "IF2 ADC Mux", "VAD_ADC", "VAD_ADC" },
2046
2047 { "IF1 ADC", NULL, "I2S1" },
Oder Chiou1319b2f2014-04-28 19:59:10 +0800[diff] [blame]2048 { "IF2 ADC", NULL, "I2S2" },
2049 { "IF2 ADC", NULL, "IF2 ADC Mux" },
2050
Oder Chiou1319b2f2014-04-28 19:59:10 +0800[diff] [blame]2051 { "AIF2TX", NULL, "IF2 ADC" },
2052
Bard Liao21ab3f22015-04-30 18:18:44 +0800[diff] [blame]2053 { "IF1 DAC0", NULL, "AIF1RX" },
Oder Chiou1319b2f2014-04-28 19:59:10 +0800[diff] [blame]2054 { "IF1 DAC1", NULL, "AIF1RX" },
2055 { "IF1 DAC2", NULL, "AIF1RX" },
Bard Liao21ab3f22015-04-30 18:18:44 +0800[diff] [blame]2056 { "IF1 DAC3", NULL, "AIF1RX" },
Oder Chiou1319b2f2014-04-28 19:59:10 +0800[diff] [blame]2057 { "IF2 DAC", NULL, "AIF2RX" },
2058
Bard Liao21ab3f22015-04-30 18:18:44 +0800[diff] [blame]2059 { "IF1 DAC0", NULL, "I2S1" },
Oder Chiou1319b2f2014-04-28 19:59:10 +0800[diff] [blame]2060 { "IF1 DAC1", NULL, "I2S1" },
2061 { "IF1 DAC2", NULL, "I2S1" },
Bard Liao21ab3f22015-04-30 18:18:44 +0800[diff] [blame]2062 { "IF1 DAC3", NULL, "I2S1" },
Oder Chiou1319b2f2014-04-28 19:59:10 +0800[diff] [blame]2063 { "IF2 DAC", NULL, "I2S2" },
2064
Oder Chiou1319b2f2014-04-28 19:59:10 +0800[diff] [blame]2065 { "IF2 DAC L", NULL, "IF2 DAC" },
2066 { "IF2 DAC R", NULL, "IF2 DAC" },
2067
Oder Chiou1319b2f2014-04-28 19:59:10 +0800[diff] [blame]2068 { "DAC1 L Mux", "IF2 DAC", "IF2 DAC L" },
Oder Chiou1319b2f2014-04-28 19:59:10 +0800[diff] [blame]2069 { "DAC1 R Mux", "IF2 DAC", "IF2 DAC R" },
2070
2071 { "DAC1 MIXL", "Stereo ADC Switch", "Stereo1 ADC MIXL" },
2072 { "DAC1 MIXL", "DAC1 Switch", "DAC1 L Mux" },
2073 { "DAC1 MIXL", NULL, "dac stereo1 filter" },
2074 { "DAC1 MIXR", "Stereo ADC Switch", "Stereo1 ADC MIXR" },
2075 { "DAC1 MIXR", "DAC1 Switch", "DAC1 R Mux" },
2076 { "DAC1 MIXR", NULL, "dac stereo1 filter" },
2077
Oder Chiou1319b2f2014-04-28 19:59:10 +0800[diff] [blame]2078 { "DAC L2 Mux", "IF2 DAC", "IF2 DAC L" },
2079 { "DAC L2 Mux", "Mono ADC", "Mono ADC MIXL" },
2080 { "DAC L2 Mux", "VAD_ADC", "VAD_ADC" },
2081 { "DAC L2 Volume", NULL, "DAC L2 Mux" },
2082 { "DAC L2 Volume", NULL, "dac mono left filter" },
2083
Oder Chiou1319b2f2014-04-28 19:59:10 +0800[diff] [blame]2084 { "DAC R2 Mux", "IF2 DAC", "IF2 DAC R" },
2085 { "DAC R2 Mux", "Mono ADC", "Mono ADC MIXR" },
2086 { "DAC R2 Mux", "Haptic", "Haptic Generator" },
2087 { "DAC R2 Volume", NULL, "DAC R2 Mux" },
2088 { "DAC R2 Volume", NULL, "dac mono right filter" },
2089
2090 { "Stereo DAC MIXL", "DAC L1 Switch", "DAC1 MIXL" },
2091 { "Stereo DAC MIXL", "DAC R1 Switch", "DAC1 MIXR" },
2092 { "Stereo DAC MIXL", "DAC L2 Switch", "DAC L2 Volume" },
2093 { "Stereo DAC MIXL", NULL, "dac stereo1 filter" },
2094 { "Stereo DAC MIXR", "DAC R1 Switch", "DAC1 MIXR" },
2095 { "Stereo DAC MIXR", "DAC L1 Switch", "DAC1 MIXL" },
2096 { "Stereo DAC MIXR", "DAC R2 Switch", "DAC R2 Volume" },
2097 { "Stereo DAC MIXR", NULL, "dac stereo1 filter" },
2098
2099 { "Mono DAC MIXL", "DAC L1 Switch", "DAC1 MIXL" },
2100 { "Mono DAC MIXL", "DAC L2 Switch", "DAC L2 Volume" },
2101 { "Mono DAC MIXL", "DAC R2 Switch", "DAC R2 Volume" },
2102 { "Mono DAC MIXL", NULL, "dac mono left filter" },
2103 { "Mono DAC MIXR", "DAC R1 Switch", "DAC1 MIXR" },
2104 { "Mono DAC MIXR", "DAC R2 Switch", "DAC R2 Volume" },
2105 { "Mono DAC MIXR", "DAC L2 Switch", "DAC L2 Volume" },
2106 { "Mono DAC MIXR", NULL, "dac mono right filter" },
2107
2108 { "DAC MIXL", "Sto DAC Mix L Switch", "Stereo DAC MIXL" },
2109 { "DAC MIXL", "DAC L2 Switch", "DAC L2 Volume" },
2110 { "DAC MIXL", "DAC R2 Switch", "DAC R2 Volume" },
2111 { "DAC MIXR", "Sto DAC Mix R Switch", "Stereo DAC MIXR" },
2112 { "DAC MIXR", "DAC R2 Switch", "DAC R2 Volume" },
2113 { "DAC MIXR", "DAC L2 Switch", "DAC L2 Volume" },
2114
Oder Chiou1319b2f2014-04-28 19:59:10 +0800[diff] [blame]2115 { "DAC L1", NULL, "PLL1", is_sys_clk_from_pll },
Oder Chiou1319b2f2014-04-28 19:59:10 +0800[diff] [blame]2116 { "DAC R1", NULL, "PLL1", is_sys_clk_from_pll },
Oder Chiou1319b2f2014-04-28 19:59:10 +0800[diff] [blame]2117 { "DAC L2", NULL, "PLL1", is_sys_clk_from_pll },
Oder Chiou1319b2f2014-04-28 19:59:10 +0800[diff] [blame]2118 { "DAC R2", NULL, "PLL1", is_sys_clk_from_pll },
2119
2120 { "SPK MIXL", "BST1 Switch", "BST1" },
2121 { "SPK MIXL", "INL Switch", "INL VOL" },
2122 { "SPK MIXL", "DAC L1 Switch", "DAC L1" },
2123 { "SPK MIXL", "DAC L2 Switch", "DAC L2" },
2124 { "SPK MIXR", "BST2 Switch", "BST2" },
2125 { "SPK MIXR", "INR Switch", "INR VOL" },
2126 { "SPK MIXR", "DAC R1 Switch", "DAC R1" },
2127 { "SPK MIXR", "DAC R2 Switch", "DAC R2" },
2128
2129 { "OUT MIXL", "BST1 Switch", "BST1" },
2130 { "OUT MIXL", "INL Switch", "INL VOL" },
2131 { "OUT MIXL", "DAC L2 Switch", "DAC L2" },
2132 { "OUT MIXL", "DAC L1 Switch", "DAC L1" },
2133
2134 { "OUT MIXR", "BST2 Switch", "BST2" },
2135 { "OUT MIXR", "INR Switch", "INR VOL" },
2136 { "OUT MIXR", "DAC R2 Switch", "DAC R2" },
2137 { "OUT MIXR", "DAC R1 Switch", "DAC R1" },
2138
2139 { "HPOVOL MIXL", "DAC1 Switch", "DAC L1" },
2140 { "HPOVOL MIXL", "DAC2 Switch", "DAC L2" },
2141 { "HPOVOL MIXL", "INL Switch", "INL VOL" },
2142 { "HPOVOL MIXL", "BST1 Switch", "BST1" },
2143 { "HPOVOL MIXL", NULL, "HPOVOL MIXL Power" },
2144 { "HPOVOL MIXR", "DAC1 Switch", "DAC R1" },
2145 { "HPOVOL MIXR", "DAC2 Switch", "DAC R2" },
2146 { "HPOVOL MIXR", "INR Switch", "INR VOL" },
2147 { "HPOVOL MIXR", "BST2 Switch", "BST2" },
2148 { "HPOVOL MIXR", NULL, "HPOVOL MIXR Power" },
2149
2150 { "DAC 2", NULL, "DAC L2" },
2151 { "DAC 2", NULL, "DAC R2" },
2152 { "DAC 1", NULL, "DAC L1" },
2153 { "DAC 1", NULL, "DAC R1" },
2154 { "HPOVOL L", "Switch", "HPOVOL MIXL" },
2155 { "HPOVOL R", "Switch", "HPOVOL MIXR" },
2156 { "HPOVOL", NULL, "HPOVOL L" },
2157 { "HPOVOL", NULL, "HPOVOL R" },
2158 { "HPO MIX", "DAC1 Switch", "DAC 1" },
2159 { "HPO MIX", "HPVOL Switch", "HPOVOL" },
2160
2161 { "SPKVOL L", "Switch", "SPK MIXL" },
2162 { "SPKVOL R", "Switch", "SPK MIXR" },
2163
2164 { "SPOL MIX", "DAC R1 Switch", "DAC R1" },
2165 { "SPOL MIX", "DAC L1 Switch", "DAC L1" },
2166 { "SPOL MIX", "SPKVOL R Switch", "SPKVOL R" },
2167 { "SPOL MIX", "SPKVOL L Switch", "SPKVOL L" },
2168 { "SPOR MIX", "DAC R1 Switch", "DAC R1" },
2169 { "SPOR MIX", "SPKVOL R Switch", "SPKVOL R" },
2170
2171 { "LOUT MIX", "DAC L1 Switch", "DAC L1" },
2172 { "LOUT MIX", "DAC R1 Switch", "DAC R1" },
2173 { "LOUT MIX", "OUTMIX L Switch", "OUT MIXL" },
2174 { "LOUT MIX", "OUTMIX R Switch", "OUT MIXR" },
2175
2176 { "PDM1 L Mux", "Stereo DAC", "Stereo DAC MIXL" },
2177 { "PDM1 L Mux", "Mono DAC", "Mono DAC MIXL" },
2178 { "PDM1 L Mux", NULL, "PDM1 Power" },
2179 { "PDM1 R Mux", "Stereo DAC", "Stereo DAC MIXR" },
2180 { "PDM1 R Mux", "Mono DAC", "Mono DAC MIXR" },
2181 { "PDM1 R Mux", NULL, "PDM1 Power" },
2182
2183 { "HP amp", NULL, "HPO MIX" },
2184 { "HP amp", NULL, "JD Power" },
2185 { "HP amp", NULL, "Mic Det Power" },
2186 { "HP amp", NULL, "LDO2" },
2187 { "HPOL", NULL, "HP amp" },
2188 { "HPOR", NULL, "HP amp" },
2189
2190 { "LOUT amp", NULL, "LOUT MIX" },
2191 { "LOUTL", NULL, "LOUT amp" },
2192 { "LOUTR", NULL, "LOUT amp" },
2193
2194 { "PDM1 L", "Switch", "PDM1 L Mux" },
2195 { "PDM1 R", "Switch", "PDM1 R Mux" },
2196
2197 { "PDM1L", NULL, "PDM1 L" },
2198 { "PDM1R", NULL, "PDM1 R" },
2199
2200 { "SPK amp", NULL, "SPOL MIX" },
2201 { "SPK amp", NULL, "SPOR MIX" },
2202 { "SPOL", NULL, "SPK amp" },
2203 { "SPOR", NULL, "SPK amp" },
2204};
2205
Bard Liao5c4ca992015-01-21 20:50:15 +0800[diff] [blame]2206static const struct snd_soc_dapm_route rt5650_specific_dapm_routes[] = {
2207 { "A DAC1 L Mux", "DAC1", "DAC1 MIXL"},
2208 { "A DAC1 L Mux", "Stereo DAC Mixer", "Stereo DAC MIXL"},
2209 { "A DAC1 R Mux", "DAC1", "DAC1 MIXR"},
2210 { "A DAC1 R Mux", "Stereo DAC Mixer", "Stereo DAC MIXR"},
2211
2212 { "A DAC2 L Mux", "Stereo DAC Mixer", "Stereo DAC MIXL"},
2213 { "A DAC2 L Mux", "Mono DAC Mixer", "Mono DAC MIXL"},
2214 { "A DAC2 R Mux", "Stereo DAC Mixer", "Stereo DAC MIXR"},
2215 { "A DAC2 R Mux", "Mono DAC Mixer", "Mono DAC MIXR"},
2216
2217 { "DAC L1", NULL, "A DAC1 L Mux" },
2218 { "DAC R1", NULL, "A DAC1 R Mux" },
2219 { "DAC L2", NULL, "A DAC2 L Mux" },
2220 { "DAC R2", NULL, "A DAC2 R Mux" },
Bard Liao21ab3f22015-04-30 18:18:44 +0800[diff] [blame]2221
2222 { "RT5650 IF1 ADC1 Swap Mux", "L/R", "IF_ADC1" },
2223 { "RT5650 IF1 ADC1 Swap Mux", "R/L", "IF_ADC1" },
2224 { "RT5650 IF1 ADC1 Swap Mux", "L/L", "IF_ADC1" },
2225 { "RT5650 IF1 ADC1 Swap Mux", "R/R", "IF_ADC1" },
2226
2227 { "RT5650 IF1 ADC2 Swap Mux", "L/R", "IF_ADC2" },
2228 { "RT5650 IF1 ADC2 Swap Mux", "R/L", "IF_ADC2" },
2229 { "RT5650 IF1 ADC2 Swap Mux", "L/L", "IF_ADC2" },
2230 { "RT5650 IF1 ADC2 Swap Mux", "R/R", "IF_ADC2" },
2231
2232 { "RT5650 IF1 ADC3 Swap Mux", "L/R", "VAD_ADC" },
2233 { "RT5650 IF1 ADC3 Swap Mux", "R/L", "VAD_ADC" },
2234 { "RT5650 IF1 ADC3 Swap Mux", "L/L", "VAD_ADC" },
2235 { "RT5650 IF1 ADC3 Swap Mux", "R/R", "VAD_ADC" },
2236
2237 { "IF1 ADC", NULL, "RT5650 IF1 ADC1 Swap Mux" },
2238 { "IF1 ADC", NULL, "RT5650 IF1 ADC2 Swap Mux" },
2239 { "IF1 ADC", NULL, "RT5650 IF1 ADC3 Swap Mux" },
2240
2241 { "RT5650 IF1 ADC Mux", "IF_ADC1/IF_ADC2/DAC_REF/Null", "IF1 ADC" },
2242 { "RT5650 IF1 ADC Mux", "IF_ADC1/IF_ADC2/Null/DAC_REF", "IF1 ADC" },
2243 { "RT5650 IF1 ADC Mux", "IF_ADC1/DAC_REF/IF_ADC2/Null", "IF1 ADC" },
2244 { "RT5650 IF1 ADC Mux", "IF_ADC1/DAC_REF/Null/IF_ADC2", "IF1 ADC" },
2245 { "RT5650 IF1 ADC Mux", "IF_ADC1/Null/DAC_REF/IF_ADC2", "IF1 ADC" },
2246 { "RT5650 IF1 ADC Mux", "IF_ADC1/Null/IF_ADC2/DAC_REF", "IF1 ADC" },
2247
2248 { "RT5650 IF1 ADC Mux", "IF_ADC2/IF_ADC1/DAC_REF/Null", "IF1 ADC" },
2249 { "RT5650 IF1 ADC Mux", "IF_ADC2/IF_ADC1/Null/DAC_REF", "IF1 ADC" },
2250 { "RT5650 IF1 ADC Mux", "IF_ADC2/DAC_REF/IF_ADC1/Null", "IF1 ADC" },
2251 { "RT5650 IF1 ADC Mux", "IF_ADC2/DAC_REF/Null/IF_ADC1", "IF1 ADC" },
2252 { "RT5650 IF1 ADC Mux", "IF_ADC2/Null/DAC_REF/IF_ADC1", "IF1 ADC" },
2253 { "RT5650 IF1 ADC Mux", "IF_ADC2/Null/IF_ADC1/DAC_REF", "IF1 ADC" },
2254
2255 { "RT5650 IF1 ADC Mux", "DAC_REF/IF_ADC1/IF_ADC2/Null", "IF1 ADC" },
2256 { "RT5650 IF1 ADC Mux", "DAC_REF/IF_ADC1/Null/IF_ADC2", "IF1 ADC" },
2257 { "RT5650 IF1 ADC Mux", "DAC_REF/IF_ADC2/IF_ADC1/Null", "IF1 ADC" },
2258 { "RT5650 IF1 ADC Mux", "DAC_REF/IF_ADC2/Null/IF_ADC1", "IF1 ADC" },
2259 { "RT5650 IF1 ADC Mux", "DAC_REF/Null/IF_ADC1/IF_ADC2", "IF1 ADC" },
2260 { "RT5650 IF1 ADC Mux", "DAC_REF/Null/IF_ADC2/IF_ADC1", "IF1 ADC" },
2261
2262 { "RT5650 IF1 ADC Mux", "Null/IF_ADC1/IF_ADC2/DAC_REF", "IF1 ADC" },
2263 { "RT5650 IF1 ADC Mux", "Null/IF_ADC1/DAC_REF/IF_ADC2", "IF1 ADC" },
2264 { "RT5650 IF1 ADC Mux", "Null/IF_ADC2/IF_ADC1/DAC_REF", "IF1 ADC" },
2265 { "RT5650 IF1 ADC Mux", "Null/IF_ADC2/DAC_REF/IF_ADC1", "IF1 ADC" },
2266 { "RT5650 IF1 ADC Mux", "Null/DAC_REF/IF_ADC1/IF_ADC2", "IF1 ADC" },
2267 { "RT5650 IF1 ADC Mux", "Null/DAC_REF/IF_ADC2/IF_ADC1", "IF1 ADC" },
2268 { "AIF1TX", NULL, "RT5650 IF1 ADC Mux" },
2269
2270 { "RT5650 IF1 DAC1 L Mux", "Slot0", "IF1 DAC0" },
2271 { "RT5650 IF1 DAC1 L Mux", "Slot1", "IF1 DAC1" },
2272 { "RT5650 IF1 DAC1 L Mux", "Slot2", "IF1 DAC2" },
2273 { "RT5650 IF1 DAC1 L Mux", "Slot3", "IF1 DAC3" },
2274
2275 { "RT5650 IF1 DAC1 R Mux", "Slot0", "IF1 DAC0" },
2276 { "RT5650 IF1 DAC1 R Mux", "Slot1", "IF1 DAC1" },
2277 { "RT5650 IF1 DAC1 R Mux", "Slot2", "IF1 DAC2" },
2278 { "RT5650 IF1 DAC1 R Mux", "Slot3", "IF1 DAC3" },
2279
2280 { "RT5650 IF1 DAC2 L Mux", "Slot0", "IF1 DAC0" },
2281 { "RT5650 IF1 DAC2 L Mux", "Slot1", "IF1 DAC1" },
2282 { "RT5650 IF1 DAC2 L Mux", "Slot2", "IF1 DAC2" },
2283 { "RT5650 IF1 DAC2 L Mux", "Slot3", "IF1 DAC3" },
2284
2285 { "RT5650 IF1 DAC2 R Mux", "Slot0", "IF1 DAC0" },
2286 { "RT5650 IF1 DAC2 R Mux", "Slot1", "IF1 DAC1" },
2287 { "RT5650 IF1 DAC2 R Mux", "Slot2", "IF1 DAC2" },
2288 { "RT5650 IF1 DAC2 R Mux", "Slot3", "IF1 DAC3" },
2289
2290 { "DAC1 L Mux", "IF1 DAC", "RT5650 IF1 DAC1 L Mux" },
2291 { "DAC1 R Mux", "IF1 DAC", "RT5650 IF1 DAC1 R Mux" },
2292
2293 { "DAC L2 Mux", "IF1 DAC", "RT5650 IF1 DAC2 L Mux" },
2294 { "DAC R2 Mux", "IF1 DAC", "RT5650 IF1 DAC2 R Mux" },
Bard Liao5c4ca992015-01-21 20:50:15 +0800[diff] [blame]2295};
2296
2297static const struct snd_soc_dapm_route rt5645_specific_dapm_routes[] = {
2298 { "DAC L1", NULL, "Stereo DAC MIXL" },
2299 { "DAC R1", NULL, "Stereo DAC MIXR" },
2300 { "DAC L2", NULL, "Mono DAC MIXL" },
2301 { "DAC R2", NULL, "Mono DAC MIXR" },
Bard Liao21ab3f22015-04-30 18:18:44 +0800[diff] [blame]2302
2303 { "RT5645 IF1 ADC1 Swap Mux", "L/R", "IF_ADC1" },
2304 { "RT5645 IF1 ADC1 Swap Mux", "R/L", "IF_ADC1" },
2305 { "RT5645 IF1 ADC1 Swap Mux", "L/L", "IF_ADC1" },
2306 { "RT5645 IF1 ADC1 Swap Mux", "R/R", "IF_ADC1" },
2307
2308 { "RT5645 IF1 ADC2 Swap Mux", "L/R", "IF_ADC2" },
2309 { "RT5645 IF1 ADC2 Swap Mux", "R/L", "IF_ADC2" },
2310 { "RT5645 IF1 ADC2 Swap Mux", "L/L", "IF_ADC2" },
2311 { "RT5645 IF1 ADC2 Swap Mux", "R/R", "IF_ADC2" },
2312
2313 { "RT5645 IF1 ADC3 Swap Mux", "L/R", "VAD_ADC" },
2314 { "RT5645 IF1 ADC3 Swap Mux", "R/L", "VAD_ADC" },
2315 { "RT5645 IF1 ADC3 Swap Mux", "L/L", "VAD_ADC" },
2316 { "RT5645 IF1 ADC3 Swap Mux", "R/R", "VAD_ADC" },
2317
2318 { "IF1 ADC", NULL, "RT5645 IF1 ADC1 Swap Mux" },
2319 { "IF1 ADC", NULL, "RT5645 IF1 ADC2 Swap Mux" },
2320 { "IF1 ADC", NULL, "RT5645 IF1 ADC3 Swap Mux" },
2321
2322 { "RT5645 IF1 ADC Mux", "IF_ADC1/IF_ADC2/VAD_ADC", "IF1 ADC" },
2323 { "RT5645 IF1 ADC Mux", "IF_ADC2/IF_ADC1/VAD_ADC", "IF1 ADC" },
2324 { "RT5645 IF1 ADC Mux", "VAD_ADC/IF_ADC1/IF_ADC2", "IF1 ADC" },
2325 { "RT5645 IF1 ADC Mux", "VAD_ADC/IF_ADC2/IF_ADC1", "IF1 ADC" },
2326 { "AIF1TX", NULL, "RT5645 IF1 ADC Mux" },
2327
2328 { "RT5645 IF1 DAC1 L Mux", "Slot0", "IF1 DAC0" },
2329 { "RT5645 IF1 DAC1 L Mux", "Slot1", "IF1 DAC1" },
2330 { "RT5645 IF1 DAC1 L Mux", "Slot2", "IF1 DAC2" },
2331 { "RT5645 IF1 DAC1 L Mux", "Slot3", "IF1 DAC3" },
2332
2333 { "RT5645 IF1 DAC1 R Mux", "Slot0", "IF1 DAC0" },
2334 { "RT5645 IF1 DAC1 R Mux", "Slot1", "IF1 DAC1" },
2335 { "RT5645 IF1 DAC1 R Mux", "Slot2", "IF1 DAC2" },
2336 { "RT5645 IF1 DAC1 R Mux", "Slot3", "IF1 DAC3" },
2337
2338 { "RT5645 IF1 DAC2 L Mux", "Slot0", "IF1 DAC0" },
2339 { "RT5645 IF1 DAC2 L Mux", "Slot1", "IF1 DAC1" },
2340 { "RT5645 IF1 DAC2 L Mux", "Slot2", "IF1 DAC2" },
2341 { "RT5645 IF1 DAC2 L Mux", "Slot3", "IF1 DAC3" },
2342
2343 { "RT5645 IF1 DAC2 R Mux", "Slot0", "IF1 DAC0" },
2344 { "RT5645 IF1 DAC2 R Mux", "Slot1", "IF1 DAC1" },
2345 { "RT5645 IF1 DAC2 R Mux", "Slot2", "IF1 DAC2" },
2346 { "RT5645 IF1 DAC2 R Mux", "Slot3", "IF1 DAC3" },
2347
2348 { "DAC1 L Mux", "IF1 DAC", "RT5645 IF1 DAC1 L Mux" },
2349 { "DAC1 R Mux", "IF1 DAC", "RT5645 IF1 DAC1 R Mux" },
2350
2351 { "DAC L2 Mux", "IF1 DAC", "RT5645 IF1 DAC2 L Mux" },
2352 { "DAC R2 Mux", "IF1 DAC", "RT5645 IF1 DAC2 R Mux" },
Bard Liao5c4ca992015-01-21 20:50:15 +0800[diff] [blame]2353};
2354
Oder Chiou1319b2f2014-04-28 19:59:10 +0800[diff] [blame]2355static int rt5645_hw_params(struct snd_pcm_substream *substream,
2356 struct snd_pcm_hw_params *params, struct snd_soc_dai *dai)
2357{
2358 struct snd_soc_codec *codec = dai->codec;
2359 struct rt5645_priv *rt5645 = snd_soc_codec_get_drvdata(codec);
Bard Liao57bf2732015-03-27 20:19:06 +0800[diff] [blame]2360 unsigned int val_len = 0, val_clk, mask_clk, dl_sft;
Oder Chiou1319b2f2014-04-28 19:59:10 +0800[diff] [blame]2361 int pre_div, bclk_ms, frame_size;
2362
2363 rt5645->lrck[dai->id] = params_rate(params);
Oder Chioud92950e2014-05-20 15:01:55 +0800[diff] [blame]2364 pre_div = rl6231_get_clk_info(rt5645->sysclk, rt5645->lrck[dai->id]);
Oder Chiou1319b2f2014-04-28 19:59:10 +0800[diff] [blame]2365 if (pre_div < 0) {
2366 dev_err(codec->dev, "Unsupported clock setting\n");
2367 return -EINVAL;
2368 }
2369 frame_size = snd_soc_params_to_frame_size(params);
2370 if (frame_size < 0) {
2371 dev_err(codec->dev, "Unsupported frame size: %d\n", frame_size);
2372 return -EINVAL;
2373 }
Bard Liao57bf2732015-03-27 20:19:06 +0800[diff] [blame]2374
2375 switch (rt5645->codec_type) {
2376 case CODEC_TYPE_RT5650:
2377 dl_sft = 4;
2378 break;
2379 default:
2380 dl_sft = 2;
2381 break;
2382 }
2383
Oder Chiou1319b2f2014-04-28 19:59:10 +0800[diff] [blame]2384 bclk_ms = frame_size > 32;
2385 rt5645->bclk[dai->id] = rt5645->lrck[dai->id] * (32 << bclk_ms);
2386
2387 dev_dbg(dai->dev, "bclk is %dHz and lrck is %dHz\n",
2388 rt5645->bclk[dai->id], rt5645->lrck[dai->id]);
2389 dev_dbg(dai->dev, "bclk_ms is %d and pre_div is %d for iis %d\n",
2390 bclk_ms, pre_div, dai->id);
2391
2392 switch (params_width(params)) {
2393 case 16:
2394 break;
2395 case 20:
Bard Liao57bf2732015-03-27 20:19:06 +0800[diff] [blame]2396 val_len = 0x1;
Oder Chiou1319b2f2014-04-28 19:59:10 +0800[diff] [blame]2397 break;
2398 case 24:
Bard Liao57bf2732015-03-27 20:19:06 +0800[diff] [blame]2399 val_len = 0x2;
Oder Chiou1319b2f2014-04-28 19:59:10 +0800[diff] [blame]2400 break;
2401 case 8:
Bard Liao57bf2732015-03-27 20:19:06 +0800[diff] [blame]2402 val_len = 0x3;
Oder Chiou1319b2f2014-04-28 19:59:10 +0800[diff] [blame]2403 break;
2404 default:
2405 return -EINVAL;
2406 }
2407
2408 switch (dai->id) {
2409 case RT5645_AIF1:
Bard Liao33de3d52015-04-30 18:18:42 +0800[diff] [blame]2410 mask_clk = RT5645_I2S_PD1_MASK;
2411 val_clk = pre_div << RT5645_I2S_PD1_SFT;
Oder Chiou1319b2f2014-04-28 19:59:10 +0800[diff] [blame]2412 snd_soc_update_bits(codec, RT5645_I2S1_SDP,
Bard Liao57bf2732015-03-27 20:19:06 +0800[diff] [blame]2413 (0x3 << dl_sft), (val_len << dl_sft));
Oder Chiou1319b2f2014-04-28 19:59:10 +0800[diff] [blame]2414 snd_soc_update_bits(codec, RT5645_ADDA_CLK1, mask_clk, val_clk);
2415 break;
2416 case RT5645_AIF2:
2417 mask_clk = RT5645_I2S_BCLK_MS2_MASK | RT5645_I2S_PD2_MASK;
2418 val_clk = bclk_ms << RT5645_I2S_BCLK_MS2_SFT |
2419 pre_div << RT5645_I2S_PD2_SFT;
2420 snd_soc_update_bits(codec, RT5645_I2S2_SDP,
Bard Liao57bf2732015-03-27 20:19:06 +0800[diff] [blame]2421 (0x3 << dl_sft), (val_len << dl_sft));
Oder Chiou1319b2f2014-04-28 19:59:10 +0800[diff] [blame]2422 snd_soc_update_bits(codec, RT5645_ADDA_CLK1, mask_clk, val_clk);
2423 break;
2424 default:
2425 dev_err(codec->dev, "Invalid dai->id: %d\n", dai->id);
2426 return -EINVAL;
2427 }
2428
2429 return 0;
2430}
2431
2432static int rt5645_set_dai_fmt(struct snd_soc_dai *dai, unsigned int fmt)
2433{
2434 struct snd_soc_codec *codec = dai->codec;
2435 struct rt5645_priv *rt5645 = snd_soc_codec_get_drvdata(codec);
Bard Liao57bf2732015-03-27 20:19:06 +0800[diff] [blame]2436 unsigned int reg_val = 0, pol_sft;
2437
2438 switch (rt5645->codec_type) {
2439 case CODEC_TYPE_RT5650:
2440 pol_sft = 8;
2441 break;
2442 default:
2443 pol_sft = 7;
2444 break;
2445 }
Oder Chiou1319b2f2014-04-28 19:59:10 +0800[diff] [blame]2446
2447 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
2448 case SND_SOC_DAIFMT_CBM_CFM:
2449 rt5645->master[dai->id] = 1;
2450 break;
2451 case SND_SOC_DAIFMT_CBS_CFS:
2452 reg_val |= RT5645_I2S_MS_S;
2453 rt5645->master[dai->id] = 0;
2454 break;
2455 default:
2456 return -EINVAL;
2457 }
2458
2459 switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
2460 case SND_SOC_DAIFMT_NB_NF:
2461 break;
2462 case SND_SOC_DAIFMT_IB_NF:
Bard Liao57bf2732015-03-27 20:19:06 +0800[diff] [blame]2463 reg_val |= (1 << pol_sft);
Oder Chiou1319b2f2014-04-28 19:59:10 +0800[diff] [blame]2464 break;
2465 default:
2466 return -EINVAL;
2467 }
2468
2469 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
2470 case SND_SOC_DAIFMT_I2S:
2471 break;
2472 case SND_SOC_DAIFMT_LEFT_J:
2473 reg_val |= RT5645_I2S_DF_LEFT;
2474 break;
2475 case SND_SOC_DAIFMT_DSP_A:
2476 reg_val |= RT5645_I2S_DF_PCM_A;
2477 break;
2478 case SND_SOC_DAIFMT_DSP_B:
2479 reg_val |= RT5645_I2S_DF_PCM_B;
2480 break;
2481 default:
2482 return -EINVAL;
2483 }
2484 switch (dai->id) {
2485 case RT5645_AIF1:
2486 snd_soc_update_bits(codec, RT5645_I2S1_SDP,
Bard Liao57bf2732015-03-27 20:19:06 +0800[diff] [blame]2487 RT5645_I2S_MS_MASK | (1 << pol_sft) |
Oder Chiou1319b2f2014-04-28 19:59:10 +0800[diff] [blame]2488 RT5645_I2S_DF_MASK, reg_val);
2489 break;
Axel Lin8c325702014-05-17 19:17:32 +0800[diff] [blame]2490 case RT5645_AIF2:
2491 snd_soc_update_bits(codec, RT5645_I2S2_SDP,
Bard Liao57bf2732015-03-27 20:19:06 +0800[diff] [blame]2492 RT5645_I2S_MS_MASK | (1 << pol_sft) |
Oder Chiou1319b2f2014-04-28 19:59:10 +0800[diff] [blame]2493 RT5645_I2S_DF_MASK, reg_val);
2494 break;
2495 default:
2496 dev_err(codec->dev, "Invalid dai->id: %d\n", dai->id);
2497 return -EINVAL;
2498 }
2499 return 0;
2500}
2501
2502static int rt5645_set_dai_sysclk(struct snd_soc_dai *dai,
2503 int clk_id, unsigned int freq, int dir)
2504{
2505 struct snd_soc_codec *codec = dai->codec;
2506 struct rt5645_priv *rt5645 = snd_soc_codec_get_drvdata(codec);
2507 unsigned int reg_val = 0;
2508
2509 if (freq == rt5645->sysclk && clk_id == rt5645->sysclk_src)
2510 return 0;
2511
2512 switch (clk_id) {
2513 case RT5645_SCLK_S_MCLK:
2514 reg_val |= RT5645_SCLK_SRC_MCLK;
2515 break;
2516 case RT5645_SCLK_S_PLL1:
2517 reg_val |= RT5645_SCLK_SRC_PLL1;
2518 break;
2519 case RT5645_SCLK_S_RCCLK:
2520 reg_val |= RT5645_SCLK_SRC_RCCLK;
2521 break;
2522 default:
2523 dev_err(codec->dev, "Invalid clock id (%d)\n", clk_id);
2524 return -EINVAL;
2525 }
2526 snd_soc_update_bits(codec, RT5645_GLB_CLK,
2527 RT5645_SCLK_SRC_MASK, reg_val);
2528 rt5645->sysclk = freq;
2529 rt5645->sysclk_src = clk_id;
2530
2531 dev_dbg(dai->dev, "Sysclk is %dHz and clock id is %d\n", freq, clk_id);
2532
2533 return 0;
2534}
2535
Oder Chiou1319b2f2014-04-28 19:59:10 +0800[diff] [blame]2536static int rt5645_set_dai_pll(struct snd_soc_dai *dai, int pll_id, int source,
2537 unsigned int freq_in, unsigned int freq_out)
2538{
2539 struct snd_soc_codec *codec = dai->codec;
2540 struct rt5645_priv *rt5645 = snd_soc_codec_get_drvdata(codec);
Oder Chiou71c7a2d2014-05-20 15:01:54 +0800[diff] [blame]2541 struct rl6231_pll_code pll_code;
Oder Chiou1319b2f2014-04-28 19:59:10 +0800[diff] [blame]2542 int ret;
2543
2544 if (source == rt5645->pll_src && freq_in == rt5645->pll_in &&
2545 freq_out == rt5645->pll_out)
2546 return 0;
2547
2548 if (!freq_in || !freq_out) {
2549 dev_dbg(codec->dev, "PLL disabled\n");
2550
2551 rt5645->pll_in = 0;
2552 rt5645->pll_out = 0;
2553 snd_soc_update_bits(codec, RT5645_GLB_CLK,
2554 RT5645_SCLK_SRC_MASK, RT5645_SCLK_SRC_MCLK);
2555 return 0;
2556 }
2557
2558 switch (source) {
2559 case RT5645_PLL1_S_MCLK:
2560 snd_soc_update_bits(codec, RT5645_GLB_CLK,
2561 RT5645_PLL1_SRC_MASK, RT5645_PLL1_SRC_MCLK);
2562 break;
2563 case RT5645_PLL1_S_BCLK1:
2564 case RT5645_PLL1_S_BCLK2:
2565 switch (dai->id) {
2566 case RT5645_AIF1:
2567 snd_soc_update_bits(codec, RT5645_GLB_CLK,
2568 RT5645_PLL1_SRC_MASK, RT5645_PLL1_SRC_BCLK1);
2569 break;
2570 case RT5645_AIF2:
2571 snd_soc_update_bits(codec, RT5645_GLB_CLK,
2572 RT5645_PLL1_SRC_MASK, RT5645_PLL1_SRC_BCLK2);
2573 break;
2574 default:
2575 dev_err(codec->dev, "Invalid dai->id: %d\n", dai->id);
2576 return -EINVAL;
2577 }
2578 break;
2579 default:
2580 dev_err(codec->dev, "Unknown PLL source %d\n", source);
2581 return -EINVAL;
2582 }
2583
Oder Chiou71c7a2d2014-05-20 15:01:54 +0800[diff] [blame]2584 ret = rl6231_pll_calc(freq_in, freq_out, &pll_code);
Oder Chiou1319b2f2014-04-28 19:59:10 +0800[diff] [blame]2585 if (ret < 0) {
2586 dev_err(codec->dev, "Unsupport input clock %d\n", freq_in);
2587 return ret;
2588 }
2589
2590 dev_dbg(codec->dev, "bypass=%d m=%d n=%d k=%d\n",
2591 pll_code.m_bp, (pll_code.m_bp ? 0 : pll_code.m_code),
2592 pll_code.n_code, pll_code.k_code);
2593
2594 snd_soc_write(codec, RT5645_PLL_CTRL1,
2595 pll_code.n_code << RT5645_PLL_N_SFT | pll_code.k_code);
2596 snd_soc_write(codec, RT5645_PLL_CTRL2,
2597 (pll_code.m_bp ? 0 : pll_code.m_code) << RT5645_PLL_M_SFT |
2598 pll_code.m_bp << RT5645_PLL_M_BP_SFT);
2599
2600 rt5645->pll_in = freq_in;
2601 rt5645->pll_out = freq_out;
2602 rt5645->pll_src = source;
2603
2604 return 0;
2605}
2606
2607static int rt5645_set_tdm_slot(struct snd_soc_dai *dai, unsigned int tx_mask,
2608 unsigned int rx_mask, int slots, int slot_width)
2609{
2610 struct snd_soc_codec *codec = dai->codec;
Bard Liao42ce5b82015-03-12 20:25:07 +0800[diff] [blame]2611 struct rt5645_priv *rt5645 = snd_soc_codec_get_drvdata(codec);
2612 unsigned int i_slot_sft, o_slot_sft, i_width_sht, o_width_sht, en_sft;
2613 unsigned int mask, val = 0;
Oder Chiou1319b2f2014-04-28 19:59:10 +0800[diff] [blame]2614
Bard Liao42ce5b82015-03-12 20:25:07 +0800[diff] [blame]2615 switch (rt5645->codec_type) {
2616 case CODEC_TYPE_RT5650:
2617 en_sft = 15;
2618 i_slot_sft = 10;
2619 o_slot_sft = 8;
2620 i_width_sht = 6;
2621 o_width_sht = 4;
2622 mask = 0x8ff0;
2623 break;
2624 default:
2625 en_sft = 14;
2626 i_slot_sft = o_slot_sft = 12;
2627 i_width_sht = o_width_sht = 10;
2628 mask = 0x7c00;
2629 break;
2630 }
Bard Liao850577d2014-11-13 09:55:22 +0800[diff] [blame]2631 if (rx_mask || tx_mask) {
Bard Liao42ce5b82015-03-12 20:25:07 +0800[diff] [blame]2632 val |= (1 << en_sft);
2633 if (rt5645->codec_type == CODEC_TYPE_RT5645)
2634 snd_soc_update_bits(codec, RT5645_BASS_BACK,
2635 RT5645_G_BB_BST_MASK, RT5645_G_BB_BST_25DB);
Bard Liao850577d2014-11-13 09:55:22 +0800[diff] [blame]2636 }
Oder Chiou1319b2f2014-04-28 19:59:10 +0800[diff] [blame]2637
2638 switch (slots) {
2639 case 4:
Bard Liao42ce5b82015-03-12 20:25:07 +0800[diff] [blame]2640 val |= (1 << i_slot_sft) | (1 << o_slot_sft);
Oder Chiou1319b2f2014-04-28 19:59:10 +0800[diff] [blame]2641 break;
2642 case 6:
Bard Liao42ce5b82015-03-12 20:25:07 +0800[diff] [blame]2643 val |= (2 << i_slot_sft) | (2 << o_slot_sft);
Oder Chiou1319b2f2014-04-28 19:59:10 +0800[diff] [blame]2644 break;
2645 case 8:
Bard Liao42ce5b82015-03-12 20:25:07 +0800[diff] [blame]2646 val |= (3 << i_slot_sft) | (3 << o_slot_sft);
Oder Chiou1319b2f2014-04-28 19:59:10 +0800[diff] [blame]2647 break;
2648 case 2:
2649 default:
2650 break;
2651 }
2652
2653 switch (slot_width) {
2654 case 20:
Bard Liao42ce5b82015-03-12 20:25:07 +0800[diff] [blame]2655 val |= (1 << i_width_sht) | (1 << o_width_sht);
Oder Chiou1319b2f2014-04-28 19:59:10 +0800[diff] [blame]2656 break;
2657 case 24:
Bard Liao42ce5b82015-03-12 20:25:07 +0800[diff] [blame]2658 val |= (2 << i_width_sht) | (2 << o_width_sht);
Oder Chiou1319b2f2014-04-28 19:59:10 +0800[diff] [blame]2659 break;
2660 case 32:
Bard Liao42ce5b82015-03-12 20:25:07 +0800[diff] [blame]2661 val |= (3 << i_width_sht) | (3 << o_width_sht);
Oder Chiou1319b2f2014-04-28 19:59:10 +0800[diff] [blame]2662 break;
2663 case 16:
2664 default:
2665 break;
2666 }
2667
Bard Liao42ce5b82015-03-12 20:25:07 +0800[diff] [blame]2668 snd_soc_update_bits(codec, RT5645_TDM_CTRL_1, mask, val);
Oder Chiou1319b2f2014-04-28 19:59:10 +0800[diff] [blame]2669
2670 return 0;
2671}
2672
2673static int rt5645_set_bias_level(struct snd_soc_codec *codec,
2674 enum snd_soc_bias_level level)
2675{
Bard Liao6e747d52015-04-28 09:59:43 +0800[diff] [blame]2676 struct rt5645_priv *rt5645 = snd_soc_codec_get_drvdata(codec);
2677
Oder Chiou1319b2f2014-04-28 19:59:10 +0800[diff] [blame]2678 switch (level) {
Bard Liao0b2e4952014-11-04 13:15:10 +0800[diff] [blame]2679 case SND_SOC_BIAS_PREPARE:
Lars-Peter Clausene2ada812015-07-06 15:38:06 +0200[diff] [blame]2680 if (SND_SOC_BIAS_STANDBY == snd_soc_codec_get_bias_level(codec)) {
Oder Chiou1319b2f2014-04-28 19:59:10 +0800[diff] [blame]2681 snd_soc_update_bits(codec, RT5645_PWR_ANLG1,
2682 RT5645_PWR_VREF1 | RT5645_PWR_MB |
2683 RT5645_PWR_BG | RT5645_PWR_VREF2,
2684 RT5645_PWR_VREF1 | RT5645_PWR_MB |
2685 RT5645_PWR_BG | RT5645_PWR_VREF2);
2686 mdelay(10);
2687 snd_soc_update_bits(codec, RT5645_PWR_ANLG1,
2688 RT5645_PWR_FV1 | RT5645_PWR_FV2,
2689 RT5645_PWR_FV1 | RT5645_PWR_FV2);
2690 snd_soc_update_bits(codec, RT5645_GEN_CTRL1,
2691 RT5645_DIG_GATE_CTRL, RT5645_DIG_GATE_CTRL);
2692 }
2693 break;
2694
Bard Liao0b2e4952014-11-04 13:15:10 +0800[diff] [blame]2695 case SND_SOC_BIAS_STANDBY:
2696 snd_soc_update_bits(codec, RT5645_PWR_ANLG1,
2697 RT5645_PWR_VREF1 | RT5645_PWR_MB |
2698 RT5645_PWR_BG | RT5645_PWR_VREF2,
2699 RT5645_PWR_VREF1 | RT5645_PWR_MB |
2700 RT5645_PWR_BG | RT5645_PWR_VREF2);
2701 snd_soc_update_bits(codec, RT5645_PWR_ANLG1,
2702 RT5645_PWR_FV1 | RT5645_PWR_FV2,
2703 RT5645_PWR_FV1 | RT5645_PWR_FV2);
2704 break;
2705
Oder Chiou1319b2f2014-04-28 19:59:10 +0800[diff] [blame]2706 case SND_SOC_BIAS_OFF:
2707 snd_soc_write(codec, RT5645_DEPOP_M2, 0x1100);
Bard Liao6e747d52015-04-28 09:59:43 +0800[diff] [blame]2708 if (!rt5645->en_button_func)
2709 snd_soc_update_bits(codec, RT5645_GEN_CTRL1,
2710 RT5645_DIG_GATE_CTRL, 0);
Bard Liao0b2e4952014-11-04 13:15:10 +0800[diff] [blame]2711 snd_soc_update_bits(codec, RT5645_PWR_ANLG1,
2712 RT5645_PWR_VREF1 | RT5645_PWR_MB |
2713 RT5645_PWR_BG | RT5645_PWR_VREF2 |
2714 RT5645_PWR_FV1 | RT5645_PWR_FV2, 0x0);
Oder Chiou1319b2f2014-04-28 19:59:10 +0800[diff] [blame]2715 break;
2716
2717 default:
2718 break;
2719 }
Oder Chiou1319b2f2014-04-28 19:59:10 +0800[diff] [blame]2720
2721 return 0;
2722}
2723
John Lind12d6c42015-05-12 20:43:02 +0800[diff] [blame]2724static int rt5650_calibration(struct rt5645_priv *rt5645)
2725{
2726 int val, i;
2727 int ret = -1;
2728
2729 regcache_cache_bypass(rt5645->regmap, true);
2730 regmap_write(rt5645->regmap, RT5645_RESET, 0);
2731 regmap_write(rt5645->regmap, RT5645_GEN_CTRL3, 0x0800);
2732 regmap_write(rt5645->regmap, RT5645_PR_BASE + RT5645_CHOP_DAC_ADC,
2733 0x3600);
2734 regmap_write(rt5645->regmap, RT5645_PR_BASE + 0x25, 0x7000);
2735 regmap_write(rt5645->regmap, RT5645_I2S1_SDP, 0x8008);
2736 /* headset type */
2737 regmap_write(rt5645->regmap, RT5645_GEN_CTRL1, 0x2061);
2738 regmap_write(rt5645->regmap, RT5645_CHARGE_PUMP, 0x0006);
2739 regmap_write(rt5645->regmap, RT5645_PWR_ANLG1, 0x2012);
2740 regmap_write(rt5645->regmap, RT5645_PWR_MIXER, 0x0002);
2741 regmap_write(rt5645->regmap, RT5645_PWR_VOL, 0x0020);
2742 regmap_write(rt5645->regmap, RT5645_JD_CTRL3, 0x00f0);
2743 regmap_write(rt5645->regmap, RT5645_IN1_CTRL1, 0x0006);
2744 regmap_write(rt5645->regmap, RT5645_IN1_CTRL2, 0x1827);
2745 regmap_write(rt5645->regmap, RT5645_IN1_CTRL2, 0x0827);
2746 msleep(400);
2747 /* Inline command */
2748 regmap_write(rt5645->regmap, RT5645_DEPOP_M1, 0x0001);
2749 regmap_write(rt5645->regmap, RT5650_4BTN_IL_CMD2, 0xc000);
2750 regmap_write(rt5645->regmap, RT5650_4BTN_IL_CMD1, 0x0008);
2751 /* Calbration */
2752 regmap_write(rt5645->regmap, RT5645_GLB_CLK, 0x8000);
2753 regmap_write(rt5645->regmap, RT5645_DEPOP_M1, 0x0000);
2754 regmap_write(rt5645->regmap, RT5650_4BTN_IL_CMD2, 0xc000);
2755 regmap_write(rt5645->regmap, RT5650_4BTN_IL_CMD1, 0x0008);
2756 regmap_write(rt5645->regmap, RT5645_PWR_DIG2, 0x8800);
2757 regmap_write(rt5645->regmap, RT5645_PWR_ANLG1, 0xe8fa);
2758 regmap_write(rt5645->regmap, RT5645_PWR_ANLG2, 0x8c04);
2759 regmap_write(rt5645->regmap, RT5645_DEPOP_M2, 0x3100);
2760 regmap_write(rt5645->regmap, RT5645_CHARGE_PUMP, 0x0e06);
2761 regmap_write(rt5645->regmap, RT5645_BASS_BACK, 0x8a13);
2762 regmap_write(rt5645->regmap, RT5645_GEN_CTRL3, 0x0820);
2763 regmap_write(rt5645->regmap, RT5645_DEPOP_M1, 0x000d);
2764 /* Power on and Calbration */
2765 regmap_write(rt5645->regmap, RT5645_PR_BASE + RT5645_HP_DCC_INT1,
2766 0x9f01);
2767 msleep(200);
2768 for (i = 0; i < 5; i++) {
2769 regmap_read(rt5645->regmap, RT5645_PR_BASE + 0x7a, &val);
2770 if (val != 0 && val != 0x3f3f) {
2771 ret = 0;
2772 break;
2773 }
2774 msleep(50);
2775 }
2776 pr_debug("%s: PR-7A = 0x%x\n", __func__, val);
2777
2778 /* mute */
2779 regmap_write(rt5645->regmap, RT5645_PR_BASE + 0x3e, 0x7400);
2780 regmap_write(rt5645->regmap, RT5645_DEPOP_M3, 0x0737);
2781 regmap_write(rt5645->regmap, RT5645_PR_BASE + RT5645_MAMP_INT_REG2,
2782 0xfc00);
2783 regmap_write(rt5645->regmap, RT5645_DEPOP_M2, 0x1140);
2784 regmap_write(rt5645->regmap, RT5645_DEPOP_M1, 0x0000);
2785 regmap_write(rt5645->regmap, RT5645_GEN_CTRL2, 0x4020);
2786 regmap_write(rt5645->regmap, RT5645_PWR_ANLG2, 0x0006);
2787 regmap_write(rt5645->regmap, RT5645_PWR_DIG2, 0x0000);
2788 msleep(350);
2789
2790 regcache_cache_bypass(rt5645->regmap, false);
2791
2792 return ret;
2793}
2794
Bard Liao6e747d52015-04-28 09:59:43 +0800[diff] [blame]2795static void rt5645_enable_push_button_irq(struct snd_soc_codec *codec,
2796 bool enable)
Oder Chiouf3fa1bb2014-09-19 19:15:45 +0800[diff] [blame]2797{
Lars-Peter Clausene2ada812015-07-06 15:38:06 +0200[diff] [blame]2798 struct snd_soc_dapm_context *dapm = snd_soc_codec_get_dapm(codec);
Bard Liao6e747d52015-04-28 09:59:43 +0800[diff] [blame]2799
2800 if (enable) {
Nicolas Boichata4e3c5f2015-07-16 13:42:34 +0800[diff] [blame]2801 snd_soc_dapm_force_enable_pin(dapm, "ADC L power");
2802 snd_soc_dapm_force_enable_pin(dapm, "ADC R power");
2803 snd_soc_dapm_sync(dapm);
Nicolas Boichat22f5d9f2015-06-10 11:54:13 +0800[diff] [blame]2804
Bard Liao6e747d52015-04-28 09:59:43 +0800[diff] [blame]2805 snd_soc_update_bits(codec,
2806 RT5645_INT_IRQ_ST, 0x8, 0x8);
2807 snd_soc_update_bits(codec,
2808 RT5650_4BTN_IL_CMD2, 0x8000, 0x8000);
2809 snd_soc_read(codec, RT5650_4BTN_IL_CMD1);
2810 pr_debug("%s read %x = %x\n", __func__, RT5650_4BTN_IL_CMD1,
2811 snd_soc_read(codec, RT5650_4BTN_IL_CMD1));
2812 } else {
2813 snd_soc_update_bits(codec, RT5650_4BTN_IL_CMD2, 0x8000, 0x0);
2814 snd_soc_update_bits(codec, RT5645_INT_IRQ_ST, 0x8, 0x0);
Nicolas Boichat22f5d9f2015-06-10 11:54:13 +0800[diff] [blame]2815
Nicolas Boichata4e3c5f2015-07-16 13:42:34 +0800[diff] [blame]2816 snd_soc_dapm_disable_pin(dapm, "ADC L power");
2817 snd_soc_dapm_disable_pin(dapm, "ADC R power");
2818 snd_soc_dapm_sync(dapm);
Bard Liao6e747d52015-04-28 09:59:43 +0800[diff] [blame]2819 }
2820}
2821
2822static int rt5645_jack_detect(struct snd_soc_codec *codec, int jack_insert)
2823{
Lars-Peter Clausene2ada812015-07-06 15:38:06 +0200[diff] [blame]2824 struct snd_soc_dapm_context *dapm = snd_soc_codec_get_dapm(codec);
Bard Liao6e747d52015-04-28 09:59:43 +0800[diff] [blame]2825 struct rt5645_priv *rt5645 = snd_soc_codec_get_drvdata(codec);
Oder Chiouf3fa1bb2014-09-19 19:15:45 +0800[diff] [blame]2826 unsigned int val;
2827
Bard Liao6e747d52015-04-28 09:59:43 +0800[diff] [blame]2828 if (jack_insert) {
John Lin05a9b462015-05-12 20:43:05 +0800[diff] [blame]2829 regmap_write(rt5645->regmap, RT5645_CHARGE_PUMP, 0x0006);
2830
Nicolas Boichatb14c9172015-07-16 13:42:33 +0800[diff] [blame]2831 /* for jack type detect */
2832 snd_soc_dapm_force_enable_pin(dapm, "LDO2");
2833 snd_soc_dapm_force_enable_pin(dapm, "Mic Det Power");
2834 snd_soc_dapm_sync(dapm);
2835 if (!dapm->card->instantiated) {
Bard Liao6e747d52015-04-28 09:59:43 +0800[diff] [blame]2836 /* Power up necessary bits for JD if dapm is
2837 not ready yet */
John Lin05a9b462015-05-12 20:43:05 +0800[diff] [blame]2838 regmap_update_bits(rt5645->regmap, RT5645_PWR_ANLG1,
2839 RT5645_PWR_MB | RT5645_PWR_VREF2,
2840 RT5645_PWR_MB | RT5645_PWR_VREF2);
2841 regmap_update_bits(rt5645->regmap, RT5645_PWR_MIXER,
Bard Liao6e747d52015-04-28 09:59:43 +0800[diff] [blame]2842 RT5645_PWR_LDO2, RT5645_PWR_LDO2);
John Lin05a9b462015-05-12 20:43:05 +0800[diff] [blame]2843 regmap_update_bits(rt5645->regmap, RT5645_PWR_VOL,
Bard Liao6e747d52015-04-28 09:59:43 +0800[diff] [blame]2844 RT5645_PWR_MIC_DET, RT5645_PWR_MIC_DET);
2845 }
Oder Chiouf3fa1bb2014-09-19 19:15:45 +0800[diff] [blame]2846
John Lin05a9b462015-05-12 20:43:05 +0800[diff] [blame]2847 regmap_write(rt5645->regmap, RT5645_JD_CTRL3, 0x00f0);
2848 regmap_write(rt5645->regmap, RT5645_IN1_CTRL1, 0x0006);
2849 regmap_update_bits(rt5645->regmap,
2850 RT5645_IN1_CTRL2, 0x1000, 0x1000);
2851 msleep(100);
2852 regmap_update_bits(rt5645->regmap,
2853 RT5645_IN1_CTRL2, 0x1000, 0x0000);
Oder Chiouf3fa1bb2014-09-19 19:15:45 +0800[diff] [blame]2854
John Lin05a9b462015-05-12 20:43:05 +0800[diff] [blame]2855 msleep(450);
2856 regmap_read(rt5645->regmap, RT5645_IN1_CTRL3, &val);
2857 val &= 0x7;
Oder Chiouf3fa1bb2014-09-19 19:15:45 +0800[diff] [blame]2858 dev_dbg(codec->dev, "val = %d\n", val);
2859
Bard Liao6e747d52015-04-28 09:59:43 +0800[diff] [blame]2860 if (val == 1 || val == 2) {
2861 rt5645->jack_type = SND_JACK_HEADSET;
2862 if (rt5645->en_button_func) {
Bard Liao6e747d52015-04-28 09:59:43 +0800[diff] [blame]2863 rt5645_enable_push_button_irq(codec, true);
2864 }
2865 } else {
Nicolas Boichatb14c9172015-07-16 13:42:33 +0800[diff] [blame]2866 snd_soc_dapm_disable_pin(dapm, "Mic Det Power");
2867 snd_soc_dapm_sync(dapm);
Bard Liao6e747d52015-04-28 09:59:43 +0800[diff] [blame]2868 rt5645->jack_type = SND_JACK_HEADPHONE;
2869 }
2870
2871 } else { /* jack out */
2872 rt5645->jack_type = 0;
Nicolas Boichata4e3c5f2015-07-16 13:42:34 +0800[diff] [blame]2873
Bard Liao6e747d52015-04-28 09:59:43 +0800[diff] [blame]2874 if (rt5645->en_button_func)
2875 rt5645_enable_push_button_irq(codec, false);
Nicolas Boichata4e3c5f2015-07-16 13:42:34 +0800[diff] [blame]2876
2877 if (rt5645->pdata.jd_mode == 0)
2878 snd_soc_dapm_disable_pin(dapm, "LDO2");
2879 snd_soc_dapm_disable_pin(dapm, "Mic Det Power");
2880 snd_soc_dapm_sync(dapm);
Oder Chiouf3fa1bb2014-09-19 19:15:45 +0800[diff] [blame]2881 }
2882
Bard Liao6e747d52015-04-28 09:59:43 +0800[diff] [blame]2883 return rt5645->jack_type;
Oder Chiouf3fa1bb2014-09-19 19:15:45 +0800[diff] [blame]2884}
2885
Nicolas Boichatf312bc52015-07-14 14:51:26 +0800[diff] [blame]2886static int rt5645_button_detect(struct snd_soc_codec *codec)
2887{
2888 int btn_type, val;
2889
2890 val = snd_soc_read(codec, RT5650_4BTN_IL_CMD1);
2891 pr_debug("val=0x%x\n", val);
2892 btn_type = val & 0xfff0;
2893 snd_soc_write(codec, RT5650_4BTN_IL_CMD1, val);
2894
2895 return btn_type;
2896}
2897
John Lin345b0f52015-05-18 10:34:03 +0800[diff] [blame]2898static irqreturn_t rt5645_irq(int irq, void *data);
Bard Liaod5660422015-04-30 10:30:01 +0800[diff] [blame]2899
Oder Chiouf3fa1bb2014-09-19 19:15:45 +0800[diff] [blame]2900int rt5645_set_jack_detect(struct snd_soc_codec *codec,
Bard Liao6e747d52015-04-28 09:59:43 +0800[diff] [blame]2901 struct snd_soc_jack *hp_jack, struct snd_soc_jack *mic_jack,
2902 struct snd_soc_jack *btn_jack)
Oder Chiouf3fa1bb2014-09-19 19:15:45 +0800[diff] [blame]2903{
2904 struct rt5645_priv *rt5645 = snd_soc_codec_get_drvdata(codec);
2905
Bard Liao471f2082014-11-14 14:25:37 +0800[diff] [blame]2906 rt5645->hp_jack = hp_jack;
2907 rt5645->mic_jack = mic_jack;
Bard Liao6e747d52015-04-28 09:59:43 +0800[diff] [blame]2908 rt5645->btn_jack = btn_jack;
2909 if (rt5645->btn_jack && rt5645->codec_type == CODEC_TYPE_RT5650) {
2910 rt5645->en_button_func = true;
2911 regmap_update_bits(rt5645->regmap, RT5645_GPIO_CTRL1,
2912 RT5645_GP1_PIN_IRQ, RT5645_GP1_PIN_IRQ);
2913 regmap_update_bits(rt5645->regmap, RT5645_DEPOP_M1,
2914 RT5645_HP_CB_MASK, RT5645_HP_CB_PU);
2915 regmap_update_bits(rt5645->regmap, RT5645_GEN_CTRL1,
2916 RT5645_DIG_GATE_CTRL, RT5645_DIG_GATE_CTRL);
2917 }
John Lin345b0f52015-05-18 10:34:03 +0800[diff] [blame]2918 rt5645_irq(0, rt5645);
Oder Chiouf3fa1bb2014-09-19 19:15:45 +0800[diff] [blame]2919
2920 return 0;
2921}
2922EXPORT_SYMBOL_GPL(rt5645_set_jack_detect);
2923
Oder Chioucd6e82b2014-10-07 10:25:37 +0800[diff] [blame]2924static void rt5645_jack_detect_work(struct work_struct *work)
2925{
2926 struct rt5645_priv *rt5645 =
2927 container_of(work, struct rt5645_priv, jack_detect_work.work);
Bard Liao6e747d52015-04-28 09:59:43 +0800[diff] [blame]2928 int val, btn_type, gpio_state = 0, report = 0;
2929
2930 switch (rt5645->pdata.jd_mode) {
2931 case 0: /* Not using rt5645 JD */
Oder Chiou0b0cefc2015-06-10 14:27:57 +0800[diff] [blame]2932 if (rt5645->gpiod_hp_det) {
2933 gpio_state = gpiod_get_value(rt5645->gpiod_hp_det);
2934 dev_dbg(rt5645->codec->dev, "gpio_state = %d\n",
2935 gpio_state);
2936 report = rt5645_jack_detect(rt5645->codec, gpio_state);
Bard Liao6e747d52015-04-28 09:59:43 +0800[diff] [blame]2937 }
2938 snd_soc_jack_report(rt5645->hp_jack,
2939 report, SND_JACK_HEADPHONE);
2940 snd_soc_jack_report(rt5645->mic_jack,
2941 report, SND_JACK_MICROPHONE);
Nicolas Boichatf312bc52015-07-14 14:51:26 +0800[diff] [blame]2942 return;
Bard Liao6e747d52015-04-28 09:59:43 +0800[diff] [blame]2943 case 1: /* 2 port */
2944 val = snd_soc_read(rt5645->codec, RT5645_A_JD_CTRL1) & 0x0070;
2945 break;
2946 default: /* 1 port */
2947 val = snd_soc_read(rt5645->codec, RT5645_A_JD_CTRL1) & 0x0020;
2948 break;
2949
2950 }
2951
2952 switch (val) {
2953 /* jack in */
2954 case 0x30: /* 2 port */
2955 case 0x0: /* 1 port or 2 port */
2956 if (rt5645->jack_type == 0) {
2957 report = rt5645_jack_detect(rt5645->codec, 1);
2958 /* for push button and jack out */
2959 break;
2960 }
2961 btn_type = 0;
2962 if (snd_soc_read(rt5645->codec, RT5645_INT_IRQ_ST) & 0x4) {
2963 /* button pressed */
2964 report = SND_JACK_HEADSET;
2965 btn_type = rt5645_button_detect(rt5645->codec);
2966 /* rt5650 can report three kinds of button behavior,
2967 one click, double click and hold. However,
2968 currently we will report button pressed/released
2969 event. So all the three button behaviors are
2970 treated as button pressed. */
2971 switch (btn_type) {
2972 case 0x8000:
2973 case 0x4000:
2974 case 0x2000:
2975 report |= SND_JACK_BTN_0;
2976 break;
2977 case 0x1000:
2978 case 0x0800:
2979 case 0x0400:
2980 report |= SND_JACK_BTN_1;
2981 break;
2982 case 0x0200:
2983 case 0x0100:
2984 case 0x0080:
2985 report |= SND_JACK_BTN_2;
2986 break;
2987 case 0x0040:
2988 case 0x0020:
2989 case 0x0010:
2990 report |= SND_JACK_BTN_3;
2991 break;
2992 case 0x0000: /* unpressed */
2993 break;
2994 default:
2995 dev_err(rt5645->codec->dev,
2996 "Unexpected button code 0x%04x\n",
2997 btn_type);
2998 break;
2999 }
3000 }
3001 if (btn_type == 0)/* button release */
3002 report = rt5645->jack_type;
3003
3004 break;
3005 /* jack out */
3006 case 0x70: /* 2 port */
3007 case 0x10: /* 2 port */
3008 case 0x20: /* 1 port */
3009 report = 0;
3010 snd_soc_update_bits(rt5645->codec,
3011 RT5645_INT_IRQ_ST, 0x1, 0x0);
3012 rt5645_jack_detect(rt5645->codec, 0);
3013 break;
3014 default:
3015 break;
3016 }
3017
3018 snd_soc_jack_report(rt5645->hp_jack, report, SND_JACK_HEADPHONE);
3019 snd_soc_jack_report(rt5645->mic_jack, report, SND_JACK_MICROPHONE);
3020 if (rt5645->en_button_func)
3021 snd_soc_jack_report(rt5645->btn_jack,
Bard Liaoe0b5d902015-04-30 18:18:46 +0800[diff] [blame]3022 report, SND_JACK_BTN_0 | SND_JACK_BTN_1 |
3023 SND_JACK_BTN_2 | SND_JACK_BTN_3);
Nicolas Boichatf312bc52015-07-14 14:51:26 +0800[diff] [blame]3024}
Bard Liao6e747d52015-04-28 09:59:43 +0800[diff] [blame]3025
Nicolas Boichatf312bc52015-07-14 14:51:26 +0800[diff] [blame]3026static irqreturn_t rt5645_irq(int irq, void *data)
3027{
3028 struct rt5645_priv *rt5645 = data;
3029
3030 queue_delayed_work(system_power_efficient_wq,
3031 &rt5645->jack_detect_work, msecs_to_jiffies(250));
3032
3033 return IRQ_HANDLED;
Bard Liao6e747d52015-04-28 09:59:43 +0800[diff] [blame]3034}
3035
Oder Chiou1319b2f2014-04-28 19:59:10 +0800[diff] [blame]3036static int rt5645_probe(struct snd_soc_codec *codec)
3037{
Lars-Peter Clausene2ada812015-07-06 15:38:06 +0200[diff] [blame]3038 struct snd_soc_dapm_context *dapm = snd_soc_codec_get_dapm(codec);
Oder Chiou1319b2f2014-04-28 19:59:10 +0800[diff] [blame]3039 struct rt5645_priv *rt5645 = snd_soc_codec_get_drvdata(codec);
3040
3041 rt5645->codec = codec;
3042
Bard Liao5c4ca992015-01-21 20:50:15 +0800[diff] [blame]3043 switch (rt5645->codec_type) {
3044 case CODEC_TYPE_RT5645:
Mark Brownf2a76382015-07-07 15:04:40 +0100[diff] [blame]3045 snd_soc_dapm_new_controls(dapm,
Bard Liao83c09292015-06-29 14:20:50 +0800[diff] [blame]3046 rt5645_specific_dapm_widgets,
3047 ARRAY_SIZE(rt5645_specific_dapm_widgets));
Lars-Peter Clausene2ada812015-07-06 15:38:06 +0200[diff] [blame]3048 snd_soc_dapm_add_routes(dapm,
Bard Liao5c4ca992015-01-21 20:50:15 +0800[diff] [blame]3049 rt5645_specific_dapm_routes,
3050 ARRAY_SIZE(rt5645_specific_dapm_routes));
3051 break;
3052 case CODEC_TYPE_RT5650:
Lars-Peter Clausene2ada812015-07-06 15:38:06 +0200[diff] [blame]3053 snd_soc_dapm_new_controls(dapm,
Bard Liao5c4ca992015-01-21 20:50:15 +0800[diff] [blame]3054 rt5650_specific_dapm_widgets,
3055 ARRAY_SIZE(rt5650_specific_dapm_widgets));
Lars-Peter Clausene2ada812015-07-06 15:38:06 +0200[diff] [blame]3056 snd_soc_dapm_add_routes(dapm,
Bard Liao5c4ca992015-01-21 20:50:15 +0800[diff] [blame]3057 rt5650_specific_dapm_routes,
3058 ARRAY_SIZE(rt5650_specific_dapm_routes));
3059 break;
3060 }
3061
Lars-Peter Clausenbd1204c2015-04-27 22:13:24 +0200[diff] [blame]3062 snd_soc_codec_force_bias_level(codec, SND_SOC_BIAS_OFF);
Oder Chiou1319b2f2014-04-28 19:59:10 +0800[diff] [blame]3063
Bard Liaobb656ad2014-11-05 15:02:08 +0800[diff] [blame]3064 /* for JD function */
Bard Liaoac4fc3e2015-05-05 21:42:01 +0800[diff] [blame]3065 if (rt5645->pdata.jd_mode) {
Lars-Peter Clausene2ada812015-07-06 15:38:06 +0200[diff] [blame]3066 snd_soc_dapm_force_enable_pin(dapm, "JD Power");
3067 snd_soc_dapm_force_enable_pin(dapm, "LDO2");
3068 snd_soc_dapm_sync(dapm);
Bard Liaobb656ad2014-11-05 15:02:08 +0800[diff] [blame]3069 }
3070
Oder Chiou1319b2f2014-04-28 19:59:10 +0800[diff] [blame]3071 return 0;
3072}
3073
3074static int rt5645_remove(struct snd_soc_codec *codec)
3075{
3076 rt5645_reset(codec);
3077 return 0;
3078}
3079
3080#ifdef CONFIG_PM
3081static int rt5645_suspend(struct snd_soc_codec *codec)
3082{
3083 struct rt5645_priv *rt5645 = snd_soc_codec_get_drvdata(codec);
3084
3085 regcache_cache_only(rt5645->regmap, true);
3086 regcache_mark_dirty(rt5645->regmap);
3087
3088 return 0;
3089}
3090
3091static int rt5645_resume(struct snd_soc_codec *codec)
3092{
3093 struct rt5645_priv *rt5645 = snd_soc_codec_get_drvdata(codec);
3094
3095 regcache_cache_only(rt5645->regmap, false);
Oder Chiou0f776ef2014-05-08 14:47:37 +0800[diff] [blame]3096 regcache_sync(rt5645->regmap);
Oder Chiou1319b2f2014-04-28 19:59:10 +0800[diff] [blame]3097
3098 return 0;
3099}
3100#else
3101#define rt5645_suspend NULL
3102#define rt5645_resume NULL
3103#endif
3104
3105#define RT5645_STEREO_RATES SNDRV_PCM_RATE_8000_96000
3106#define RT5645_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE | \
3107 SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S8)
3108
Oder Chiou9e22f782014-05-08 14:47:35 +0800[diff] [blame]3109static struct snd_soc_dai_ops rt5645_aif_dai_ops = {
Oder Chiou1319b2f2014-04-28 19:59:10 +0800[diff] [blame]3110 .hw_params = rt5645_hw_params,
3111 .set_fmt = rt5645_set_dai_fmt,
3112 .set_sysclk = rt5645_set_dai_sysclk,
3113 .set_tdm_slot = rt5645_set_tdm_slot,
3114 .set_pll = rt5645_set_dai_pll,
3115};
3116
Oder Chiou9e22f782014-05-08 14:47:35 +0800[diff] [blame]3117static struct snd_soc_dai_driver rt5645_dai[] = {
Oder Chiou1319b2f2014-04-28 19:59:10 +0800[diff] [blame]3118 {
3119 .name = "rt5645-aif1",
3120 .id = RT5645_AIF1,
3121 .playback = {
3122 .stream_name = "AIF1 Playback",
3123 .channels_min = 1,
3124 .channels_max = 2,
3125 .rates = RT5645_STEREO_RATES,
3126 .formats = RT5645_FORMATS,
3127 },
3128 .capture = {
3129 .stream_name = "AIF1 Capture",
3130 .channels_min = 1,
3131 .channels_max = 2,
3132 .rates = RT5645_STEREO_RATES,
3133 .formats = RT5645_FORMATS,
3134 },
3135 .ops = &rt5645_aif_dai_ops,
3136 },
3137 {
3138 .name = "rt5645-aif2",
3139 .id = RT5645_AIF2,
3140 .playback = {
3141 .stream_name = "AIF2 Playback",
3142 .channels_min = 1,
3143 .channels_max = 2,
3144 .rates = RT5645_STEREO_RATES,
3145 .formats = RT5645_FORMATS,
3146 },
3147 .capture = {
3148 .stream_name = "AIF2 Capture",
3149 .channels_min = 1,
3150 .channels_max = 2,
3151 .rates = RT5645_STEREO_RATES,
3152 .formats = RT5645_FORMATS,
3153 },
3154 .ops = &rt5645_aif_dai_ops,
3155 },
3156};
3157
3158static struct snd_soc_codec_driver soc_codec_dev_rt5645 = {
3159 .probe = rt5645_probe,
3160 .remove = rt5645_remove,
3161 .suspend = rt5645_suspend,
3162 .resume = rt5645_resume,
3163 .set_bias_level = rt5645_set_bias_level,
3164 .idle_bias_off = true,
3165 .controls = rt5645_snd_controls,
3166 .num_controls = ARRAY_SIZE(rt5645_snd_controls),
3167 .dapm_widgets = rt5645_dapm_widgets,
3168 .num_dapm_widgets = ARRAY_SIZE(rt5645_dapm_widgets),
3169 .dapm_routes = rt5645_dapm_routes,
3170 .num_dapm_routes = ARRAY_SIZE(rt5645_dapm_routes),
3171};
3172
3173static const struct regmap_config rt5645_regmap = {
3174 .reg_bits = 8,
3175 .val_bits = 16,
Bard Liaoafefc122015-03-27 20:19:07 +0800[diff] [blame]3176 .use_single_rw = true,
Oder Chiou1319b2f2014-04-28 19:59:10 +0800[diff] [blame]3177 .max_register = RT5645_VENDOR_ID2 + 1 + (ARRAY_SIZE(rt5645_ranges) *
3178 RT5645_PR_SPACING),
3179 .volatile_reg = rt5645_volatile_register,
3180 .readable_reg = rt5645_readable_register,
3181
3182 .cache_type = REGCACHE_RBTREE,
3183 .reg_defaults = rt5645_reg,
3184 .num_reg_defaults = ARRAY_SIZE(rt5645_reg),
3185 .ranges = rt5645_ranges,
3186 .num_ranges = ARRAY_SIZE(rt5645_ranges),
3187};
3188
3189static const struct i2c_device_id rt5645_i2c_id[] = {
3190 { "rt5645", 0 },
Bard Liao5c4ca992015-01-21 20:50:15 +0800[diff] [blame]3191 { "rt5650", 0 },
Oder Chiou1319b2f2014-04-28 19:59:10 +0800[diff] [blame]3192 { }
3193};
3194MODULE_DEVICE_TABLE(i2c, rt5645_i2c_id);
3195
Fang, Yang A3168c202015-04-23 16:35:17 -0700[diff] [blame]3196#ifdef CONFIG_ACPI
3197static struct acpi_device_id rt5645_acpi_match[] = {
3198 { "10EC5645", 0 },
3199 { "10EC5650", 0 },
3200 {},
3201};
3202MODULE_DEVICE_TABLE(acpi, rt5645_acpi_match);
3203#endif
3204
Fang, Yang A78c34fd2015-04-24 17:50:54 -0700[diff] [blame]3205static struct rt5645_platform_data *rt5645_pdata;
3206
3207static struct rt5645_platform_data strago_platform_data = {
Bard Liaoac4fc3e2015-05-05 21:42:01 +0800[diff] [blame]3208 .dmic1_data_pin = RT5645_DMIC1_DISABLE,
Fang, Yang A78c34fd2015-04-24 17:50:54 -0700[diff] [blame]3209 .dmic2_data_pin = RT5645_DMIC_DATA_IN2P,
Fang, Yang A78c34fd2015-04-24 17:50:54 -0700[diff] [blame]3210 .jd_mode = 3,
3211};
3212
3213static int strago_quirk_cb(const struct dmi_system_id *id)
3214{
3215 rt5645_pdata = &strago_platform_data;
3216
3217 return 1;
3218}
3219
Axel Lin0bc7d102015-06-28 11:41:19 +0800[diff] [blame]3220static const struct dmi_system_id dmi_platform_intel_braswell[] = {
Fang, Yang A78c34fd2015-04-24 17:50:54 -0700[diff] [blame]3221 {
3222 .ident = "Intel Strago",
3223 .callback = strago_quirk_cb,
3224 .matches = {
3225 DMI_MATCH(DMI_PRODUCT_NAME, "Strago"),
3226 },
3227 },
3228 { }
3229};
3230
Oder Chiou48edaa42015-06-12 14:47:36 +0800[diff] [blame]3231static int rt5645_parse_dt(struct rt5645_priv *rt5645, struct device *dev)
3232{
3233 rt5645->pdata.in2_diff = device_property_read_bool(dev,
3234 "realtek,in2-differential");
3235 device_property_read_u32(dev,
3236 "realtek,dmic1-data-pin", &rt5645->pdata.dmic1_data_pin);
3237 device_property_read_u32(dev,
3238 "realtek,dmic2-data-pin", &rt5645->pdata.dmic2_data_pin);
3239 device_property_read_u32(dev,
3240 "realtek,jd-mode", &rt5645->pdata.jd_mode);
3241
3242 return 0;
3243}
3244
Oder Chiou1319b2f2014-04-28 19:59:10 +0800[diff] [blame]3245static int rt5645_i2c_probe(struct i2c_client *i2c,
3246 const struct i2c_device_id *id)
3247{
3248 struct rt5645_platform_data *pdata = dev_get_platdata(&i2c->dev);
3249 struct rt5645_priv *rt5645;
Koro Chen9fc114c2015-07-17 11:33:12 +0800[diff] [blame^]3250 int ret, i;
Oder Chiou1319b2f2014-04-28 19:59:10 +0800[diff] [blame]3251 unsigned int val;
3252
3253 rt5645 = devm_kzalloc(&i2c->dev, sizeof(struct rt5645_priv),
3254 GFP_KERNEL);
3255 if (rt5645 == NULL)
3256 return -ENOMEM;
3257
Oder Chiouf3fa1bb2014-09-19 19:15:45 +0800[diff] [blame]3258 rt5645->i2c = i2c;
Oder Chiou1319b2f2014-04-28 19:59:10 +0800[diff] [blame]3259 i2c_set_clientdata(i2c, rt5645);
3260
Oder Chiou48edaa42015-06-12 14:47:36 +0800[diff] [blame]3261 if (pdata)
Oder Chiou1319b2f2014-04-28 19:59:10 +0800[diff] [blame]3262 rt5645->pdata = *pdata;
Oder Chiou48edaa42015-06-12 14:47:36 +0800[diff] [blame]3263 else if (dmi_check_system(dmi_platform_intel_braswell))
3264 rt5645->pdata = *rt5645_pdata;
3265 else
3266 rt5645_parse_dt(rt5645, &i2c->dev);
Oder Chiou1319b2f2014-04-28 19:59:10 +0800[diff] [blame]3267
Axel Lin25c88882015-06-12 17:19:15 +0800[diff] [blame]3268 rt5645->gpiod_hp_det = devm_gpiod_get_optional(&i2c->dev, "hp-detect",
3269 GPIOD_IN);
Oder Chiou0b0cefc2015-06-10 14:27:57 +0800[diff] [blame]3270
3271 if (IS_ERR(rt5645->gpiod_hp_det)) {
Oder Chiou0b0cefc2015-06-10 14:27:57 +0800[diff] [blame]3272 dev_err(&i2c->dev, "failed to initialize gpiod\n");
Axel Lin25c88882015-06-12 17:19:15 +0800[diff] [blame]3273 return PTR_ERR(rt5645->gpiod_hp_det);
Oder Chiou0b0cefc2015-06-10 14:27:57 +0800[diff] [blame]3274 }
3275
Oder Chiou1319b2f2014-04-28 19:59:10 +0800[diff] [blame]3276 rt5645->regmap = devm_regmap_init_i2c(i2c, &rt5645_regmap);
3277 if (IS_ERR(rt5645->regmap)) {
3278 ret = PTR_ERR(rt5645->regmap);
3279 dev_err(&i2c->dev, "Failed to allocate register map: %d\n",
3280 ret);
3281 return ret;
3282 }
3283
Koro Chen9fc114c2015-07-17 11:33:12 +0800[diff] [blame^]3284 for (i = 0; i < ARRAY_SIZE(rt5645->supplies); i++)
3285 rt5645->supplies[i].supply = rt5645_supply_names[i];
3286
3287 ret = devm_regulator_bulk_get(&i2c->dev,
3288 ARRAY_SIZE(rt5645->supplies),
3289 rt5645->supplies);
3290 if (ret) {
3291 dev_err(&i2c->dev, "Failed to request supplies: %d\n", ret);
3292 return ret;
3293 }
3294
3295 ret = regulator_bulk_enable(ARRAY_SIZE(rt5645->supplies),
3296 rt5645->supplies);
3297 if (ret) {
3298 dev_err(&i2c->dev, "Failed to enable supplies: %d\n", ret);
3299 return ret;
3300 }
3301
Oder Chiou1319b2f2014-04-28 19:59:10 +0800[diff] [blame]3302 regmap_read(rt5645->regmap, RT5645_VENDOR_ID2, &val);
Bard Liao5c4ca992015-01-21 20:50:15 +0800[diff] [blame]3303
3304 switch (val) {
3305 case RT5645_DEVICE_ID:
3306 rt5645->codec_type = CODEC_TYPE_RT5645;
3307 break;
3308 case RT5650_DEVICE_ID:
3309 rt5645->codec_type = CODEC_TYPE_RT5650;
3310 break;
3311 default:
Oder Chiou1319b2f2014-04-28 19:59:10 +0800[diff] [blame]3312 dev_err(&i2c->dev,
Jarkko Nikula8f68e802015-06-25 13:58:58 +0300[diff] [blame]3313 "Device with ID register %#x is not rt5645 or rt5650\n",
Bard Liao5c4ca992015-01-21 20:50:15 +0800[diff] [blame]3314 val);
Koro Chen9fc114c2015-07-17 11:33:12 +0800[diff] [blame^]3315 ret = -ENODEV;
3316 goto err_enable;
Oder Chiou1319b2f2014-04-28 19:59:10 +0800[diff] [blame]3317 }
3318
John Lind12d6c42015-05-12 20:43:02 +0800[diff] [blame]3319 if (rt5645->codec_type == CODEC_TYPE_RT5650) {
3320 ret = rt5650_calibration(rt5645);
3321
3322 if (ret < 0)
3323 pr_err("calibration failed!\n");
3324 }
3325
Oder Chiou1319b2f2014-04-28 19:59:10 +0800[diff] [blame]3326 regmap_write(rt5645->regmap, RT5645_RESET, 0);
3327
3328 ret = regmap_register_patch(rt5645->regmap, init_list,
3329 ARRAY_SIZE(init_list));
3330 if (ret != 0)
3331 dev_warn(&i2c->dev, "Failed to apply regmap patch: %d\n", ret);
3332
Bard Liao5c4ca992015-01-21 20:50:15 +0800[diff] [blame]3333 if (rt5645->codec_type == CODEC_TYPE_RT5650) {
3334 ret = regmap_register_patch(rt5645->regmap, rt5650_init_list,
3335 ARRAY_SIZE(rt5650_init_list));
3336 if (ret != 0)
3337 dev_warn(&i2c->dev, "Apply rt5650 patch failed: %d\n",
3338 ret);
3339 }
3340
Oder Chiou1319b2f2014-04-28 19:59:10 +0800[diff] [blame]3341 if (rt5645->pdata.in2_diff)
3342 regmap_update_bits(rt5645->regmap, RT5645_IN2_CTRL,
3343 RT5645_IN_DF2, RT5645_IN_DF2);
3344
Bard Liaoac4fc3e2015-05-05 21:42:01 +0800[diff] [blame]3345 if (rt5645->pdata.dmic1_data_pin || rt5645->pdata.dmic2_data_pin) {
Oder Chiou1319b2f2014-04-28 19:59:10 +0800[diff] [blame]3346 regmap_update_bits(rt5645->regmap, RT5645_GPIO_CTRL1,
3347 RT5645_GP2_PIN_MASK, RT5645_GP2_PIN_DMIC1_SCL);
Bard Liaoac4fc3e2015-05-05 21:42:01 +0800[diff] [blame]3348 }
3349 switch (rt5645->pdata.dmic1_data_pin) {
3350 case RT5645_DMIC_DATA_IN2N:
3351 regmap_update_bits(rt5645->regmap, RT5645_DMIC_CTRL1,
3352 RT5645_DMIC_1_DP_MASK, RT5645_DMIC_1_DP_IN2N);
3353 break;
Oder Chiou1319b2f2014-04-28 19:59:10 +0800[diff] [blame]3354
Bard Liaoac4fc3e2015-05-05 21:42:01 +0800[diff] [blame]3355 case RT5645_DMIC_DATA_GPIO5:
3356 regmap_update_bits(rt5645->regmap, RT5645_DMIC_CTRL1,
3357 RT5645_DMIC_1_DP_MASK, RT5645_DMIC_1_DP_GPIO5);
3358 regmap_update_bits(rt5645->regmap, RT5645_GPIO_CTRL1,
3359 RT5645_GP5_PIN_MASK, RT5645_GP5_PIN_DMIC1_SDA);
3360 break;
Oder Chiou1319b2f2014-04-28 19:59:10 +0800[diff] [blame]3361
Bard Liaoac4fc3e2015-05-05 21:42:01 +0800[diff] [blame]3362 case RT5645_DMIC_DATA_GPIO11:
3363 regmap_update_bits(rt5645->regmap, RT5645_DMIC_CTRL1,
3364 RT5645_DMIC_1_DP_MASK, RT5645_DMIC_1_DP_GPIO11);
3365 regmap_update_bits(rt5645->regmap, RT5645_GPIO_CTRL1,
3366 RT5645_GP11_PIN_MASK,
3367 RT5645_GP11_PIN_DMIC1_SDA);
3368 break;
Oder Chiou1319b2f2014-04-28 19:59:10 +0800[diff] [blame]3369
Bard Liaoac4fc3e2015-05-05 21:42:01 +0800[diff] [blame]3370 default:
3371 break;
Oder Chiou1319b2f2014-04-28 19:59:10 +0800[diff] [blame]3372 }
3373
Bard Liaoac4fc3e2015-05-05 21:42:01 +0800[diff] [blame]3374 switch (rt5645->pdata.dmic2_data_pin) {
3375 case RT5645_DMIC_DATA_IN2P:
3376 regmap_update_bits(rt5645->regmap, RT5645_DMIC_CTRL1,
3377 RT5645_DMIC_2_DP_MASK, RT5645_DMIC_2_DP_IN2P);
3378 break;
3379
3380 case RT5645_DMIC_DATA_GPIO6:
3381 regmap_update_bits(rt5645->regmap, RT5645_DMIC_CTRL1,
3382 RT5645_DMIC_2_DP_MASK, RT5645_DMIC_2_DP_GPIO6);
3383 regmap_update_bits(rt5645->regmap, RT5645_GPIO_CTRL1,
3384 RT5645_GP6_PIN_MASK, RT5645_GP6_PIN_DMIC2_SDA);
3385 break;
3386
3387 case RT5645_DMIC_DATA_GPIO10:
3388 regmap_update_bits(rt5645->regmap, RT5645_DMIC_CTRL1,
3389 RT5645_DMIC_2_DP_MASK, RT5645_DMIC_2_DP_GPIO10);
3390 regmap_update_bits(rt5645->regmap, RT5645_GPIO_CTRL1,
3391 RT5645_GP10_PIN_MASK,
3392 RT5645_GP10_PIN_DMIC2_SDA);
3393 break;
3394
3395 case RT5645_DMIC_DATA_GPIO12:
3396 regmap_update_bits(rt5645->regmap, RT5645_DMIC_CTRL1,
3397 RT5645_DMIC_2_DP_MASK, RT5645_DMIC_2_DP_GPIO12);
3398 regmap_update_bits(rt5645->regmap, RT5645_GPIO_CTRL1,
3399 RT5645_GP12_PIN_MASK,
3400 RT5645_GP12_PIN_DMIC2_SDA);
3401 break;
3402
3403 default:
3404 break;
Bard Liaobb656ad2014-11-05 15:02:08 +0800[diff] [blame]3405 }
3406
Bard Liao2d4e2d02014-11-18 16:50:18 +0800[diff] [blame]3407 if (rt5645->pdata.jd_mode) {
Bard Liaoac4fc3e2015-05-05 21:42:01 +0800[diff] [blame]3408 regmap_update_bits(rt5645->regmap, RT5645_GEN_CTRL3,
3409 RT5645_IRQ_CLK_GATE_CTRL,
3410 RT5645_IRQ_CLK_GATE_CTRL);
3411 regmap_update_bits(rt5645->regmap, RT5645_IN1_CTRL1,
3412 RT5645_CBJ_BST1_EN, RT5645_CBJ_BST1_EN);
Bard Liaoac4fc3e2015-05-05 21:42:01 +0800[diff] [blame]3413 regmap_update_bits(rt5645->regmap, RT5645_MICBIAS,
3414 RT5645_IRQ_CLK_INT, RT5645_IRQ_CLK_INT);
Bard Liao2d4e2d02014-11-18 16:50:18 +0800[diff] [blame]3415 regmap_update_bits(rt5645->regmap, RT5645_IRQ_CTRL2,
3416 RT5645_IRQ_JD_1_1_EN, RT5645_IRQ_JD_1_1_EN);
3417 regmap_update_bits(rt5645->regmap, RT5645_GEN_CTRL3,
3418 RT5645_JD_PSV_MODE, RT5645_JD_PSV_MODE);
3419 regmap_update_bits(rt5645->regmap, RT5645_HPO_MIXER,
3420 RT5645_IRQ_PSV_MODE, RT5645_IRQ_PSV_MODE);
3421 regmap_update_bits(rt5645->regmap, RT5645_MICBIAS,
3422 RT5645_MIC2_OVCD_EN, RT5645_MIC2_OVCD_EN);
3423 regmap_update_bits(rt5645->regmap, RT5645_GPIO_CTRL1,
3424 RT5645_GP1_PIN_IRQ, RT5645_GP1_PIN_IRQ);
3425 switch (rt5645->pdata.jd_mode) {
3426 case 1:
3427 regmap_update_bits(rt5645->regmap, RT5645_A_JD_CTRL1,
3428 RT5645_JD1_MODE_MASK,
3429 RT5645_JD1_MODE_0);
3430 break;
3431 case 2:
3432 regmap_update_bits(rt5645->regmap, RT5645_A_JD_CTRL1,
3433 RT5645_JD1_MODE_MASK,
3434 RT5645_JD1_MODE_1);
3435 break;
3436 case 3:
3437 regmap_update_bits(rt5645->regmap, RT5645_A_JD_CTRL1,
3438 RT5645_JD1_MODE_MASK,
3439 RT5645_JD1_MODE_2);
3440 break;
3441 default:
3442 break;
3443 }
3444 }
3445
Nicolas Boichat7ea34702015-06-05 18:42:12 +0800[diff] [blame]3446 INIT_DELAYED_WORK(&rt5645->jack_detect_work, rt5645_jack_detect_work);
3447
Oder Chiouf3fa1bb2014-09-19 19:15:45 +0800[diff] [blame]3448 if (rt5645->i2c->irq) {
3449 ret = request_threaded_irq(rt5645->i2c->irq, NULL, rt5645_irq,
3450 IRQF_TRIGGER_RISING | IRQF_TRIGGER_FALLING
3451 | IRQF_ONESHOT, "rt5645", rt5645);
Koro Chen5168c542015-07-17 11:33:11 +0800[diff] [blame]3452 if (ret) {
Oder Chiouf3fa1bb2014-09-19 19:15:45 +0800[diff] [blame]3453 dev_err(&i2c->dev, "Failed to reguest IRQ: %d\n", ret);
Koro Chen9fc114c2015-07-17 11:33:12 +0800[diff] [blame^]3454 goto err_enable;
Koro Chen5168c542015-07-17 11:33:11 +0800[diff] [blame]3455 }
Oder Chiouf3fa1bb2014-09-19 19:15:45 +0800[diff] [blame]3456 }
3457
Koro Chen5168c542015-07-17 11:33:11 +0800[diff] [blame]3458 ret = snd_soc_register_codec(&i2c->dev, &soc_codec_dev_rt5645,
3459 rt5645_dai, ARRAY_SIZE(rt5645_dai));
3460 if (ret)
3461 goto err_irq;
3462
3463 return 0;
3464
3465err_irq:
3466 if (rt5645->i2c->irq)
3467 free_irq(rt5645->i2c->irq, rt5645);
Koro Chen9fc114c2015-07-17 11:33:12 +0800[diff] [blame^]3468err_enable:
3469 regulator_bulk_disable(ARRAY_SIZE(rt5645->supplies), rt5645->supplies);
Koro Chen5168c542015-07-17 11:33:11 +0800[diff] [blame]3470 return ret;
Oder Chiou1319b2f2014-04-28 19:59:10 +0800[diff] [blame]3471}
3472
3473static int rt5645_i2c_remove(struct i2c_client *i2c)
3474{
Oder Chiouf3fa1bb2014-09-19 19:15:45 +0800[diff] [blame]3475 struct rt5645_priv *rt5645 = i2c_get_clientdata(i2c);
3476
3477 if (i2c->irq)
3478 free_irq(i2c->irq, rt5645);
3479
Oder Chioucd6e82b2014-10-07 10:25:37 +0800[diff] [blame]3480 cancel_delayed_work_sync(&rt5645->jack_detect_work);
3481
Oder Chiou1319b2f2014-04-28 19:59:10 +0800[diff] [blame]3482 snd_soc_unregister_codec(&i2c->dev);
Koro Chen9fc114c2015-07-17 11:33:12 +0800[diff] [blame^]3483 regulator_bulk_disable(ARRAY_SIZE(rt5645->supplies), rt5645->supplies);
Oder Chiou1319b2f2014-04-28 19:59:10 +0800[diff] [blame]3484
3485 return 0;
3486}
3487
Oder Chiou9e22f782014-05-08 14:47:35 +0800[diff] [blame]3488static struct i2c_driver rt5645_i2c_driver = {
Oder Chiou1319b2f2014-04-28 19:59:10 +0800[diff] [blame]3489 .driver = {
3490 .name = "rt5645",
3491 .owner = THIS_MODULE,
Fang, Yang A3168c202015-04-23 16:35:17 -0700[diff] [blame]3492 .acpi_match_table = ACPI_PTR(rt5645_acpi_match),
Oder Chiou1319b2f2014-04-28 19:59:10 +0800[diff] [blame]3493 },
3494 .probe = rt5645_i2c_probe,
3495 .remove = rt5645_i2c_remove,
3496 .id_table = rt5645_i2c_id,
3497};
3498module_i2c_driver(rt5645_i2c_driver);
3499
3500MODULE_DESCRIPTION("ASoC RT5645 driver");
3501MODULE_AUTHOR("Bard Liao <bardliao@realtek.com>");
3502MODULE_LICENSE("GPL v2");