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Magnus Damm97991652011-04-29 02:28:08 +09001/*
2 * sh7372 Power management support
3 *
4 * Copyright (C) 2011 Magnus Damm
5 *
6 * This file is subject to the terms and conditions of the GNU General Public
7 * License. See the file "COPYING" in the main directory of this archive
8 * for more details.
9 */
10
11#include <linux/pm.h>
12#include <linux/suspend.h>
Magnus Damm082a8ca2011-04-29 02:39:32 +090013#include <linux/cpuidle.h>
Magnus Damm97991652011-04-29 02:28:08 +090014#include <linux/module.h>
15#include <linux/list.h>
16#include <linux/err.h>
17#include <linux/slab.h>
Rafael J. Wysockib5e8d262011-08-25 15:34:19 +020018#include <linux/pm_clock.h>
Rafael J. Wysockie3e01092011-07-01 22:13:56 +020019#include <linux/platform_device.h>
20#include <linux/delay.h>
Magnus Dammcf338352011-09-25 23:20:49 +020021#include <linux/irq.h>
22#include <linux/bitrev.h>
Magnus Damm97991652011-04-29 02:28:08 +090023#include <asm/system.h>
24#include <asm/io.h>
25#include <asm/tlbflush.h>
Magnus Damm06b84162011-09-25 23:18:42 +020026#include <asm/suspend.h>
Magnus Damm97991652011-04-29 02:28:08 +090027#include <mach/common.h>
Rafael J. Wysockie3e01092011-07-01 22:13:56 +020028#include <mach/sh7372.h>
Magnus Damm97991652011-04-29 02:28:08 +090029
Magnus Dammcf338352011-09-25 23:20:49 +020030/* DBG */
31#define DBGREG1 0xe6100020
32#define DBGREG9 0xe6100040
Magnus Damm97991652011-04-29 02:28:08 +090033
Magnus Dammcf338352011-09-25 23:20:49 +020034/* CPGA */
35#define SYSTBCR 0xe6150024
36#define MSTPSR0 0xe6150030
37#define MSTPSR1 0xe6150038
38#define MSTPSR2 0xe6150040
39#define MSTPSR3 0xe6150048
40#define MSTPSR4 0xe615004c
41#define PLLC01STPCR 0xe61500c8
42
43/* SYSC */
Rafael J. Wysockie3e01092011-07-01 22:13:56 +020044#define SPDCR 0xe6180008
45#define SWUCR 0xe6180014
Magnus Dammcf338352011-09-25 23:20:49 +020046#define SBAR 0xe6180020
47#define WUPSMSK 0xe618002c
48#define WUPSMSK2 0xe6180048
Rafael J. Wysockie3e01092011-07-01 22:13:56 +020049#define PSTR 0xe6180080
Magnus Dammcf338352011-09-25 23:20:49 +020050#define WUPSFAC 0xe6180098
51#define IRQCR 0xe618022c
52#define IRQCR2 0xe6180238
53#define IRQCR3 0xe6180244
54#define IRQCR4 0xe6180248
55#define PDNSEL 0xe6180254
56
57/* INTC */
58#define ICR1A 0xe6900000
59#define ICR2A 0xe6900004
60#define ICR3A 0xe6900008
61#define ICR4A 0xe690000c
62#define INTMSK00A 0xe6900040
63#define INTMSK10A 0xe6900044
64#define INTMSK20A 0xe6900048
65#define INTMSK30A 0xe690004c
66
67/* MFIS */
68#define SMFRAM 0xe6a70000
69
70/* AP-System Core */
71#define APARMBAREA 0xe6f10020
Rafael J. Wysockie3e01092011-07-01 22:13:56 +020072
73#define PSTR_RETRIES 100
74#define PSTR_DELAY_US 10
75
76#ifdef CONFIG_PM
77
78static int pd_power_down(struct generic_pm_domain *genpd)
79{
80 struct sh7372_pm_domain *sh7372_pd = to_sh7372_pd(genpd);
81 unsigned int mask = 1 << sh7372_pd->bit_shift;
82
83 if (__raw_readl(PSTR) & mask) {
84 unsigned int retry_count;
85
86 __raw_writel(mask, SPDCR);
87
88 for (retry_count = PSTR_RETRIES; retry_count; retry_count--) {
89 if (!(__raw_readl(SPDCR) & mask))
90 break;
91 cpu_relax();
92 }
93 }
94
95 pr_debug("sh7372 power domain down 0x%08x -> PSTR = 0x%08x\n",
96 mask, __raw_readl(PSTR));
97
98 return 0;
99}
100
101static int pd_power_up(struct generic_pm_domain *genpd)
102{
103 struct sh7372_pm_domain *sh7372_pd = to_sh7372_pd(genpd);
104 unsigned int mask = 1 << sh7372_pd->bit_shift;
105 unsigned int retry_count;
106 int ret = 0;
107
108 if (__raw_readl(PSTR) & mask)
109 goto out;
110
111 __raw_writel(mask, SWUCR);
112
113 for (retry_count = 2 * PSTR_RETRIES; retry_count; retry_count--) {
114 if (!(__raw_readl(SWUCR) & mask))
115 goto out;
116 if (retry_count > PSTR_RETRIES)
117 udelay(PSTR_DELAY_US);
118 else
119 cpu_relax();
120 }
121 if (__raw_readl(SWUCR) & mask)
122 ret = -EIO;
123
124 out:
125 pr_debug("sh7372 power domain up 0x%08x -> PSTR = 0x%08x\n",
126 mask, __raw_readl(PSTR));
127
128 return ret;
129}
130
131static bool pd_active_wakeup(struct device *dev)
132{
133 return true;
134}
135
136void sh7372_init_pm_domain(struct sh7372_pm_domain *sh7372_pd)
137{
138 struct generic_pm_domain *genpd = &sh7372_pd->genpd;
139
140 pm_genpd_init(genpd, NULL, false);
141 genpd->stop_device = pm_clk_suspend;
142 genpd->start_device = pm_clk_resume;
Rafael J. Wysocki0aa2a222011-08-25 15:37:04 +0200143 genpd->dev_irq_safe = true;
Rafael J. Wysockie3e01092011-07-01 22:13:56 +0200144 genpd->active_wakeup = pd_active_wakeup;
Rafael J. Wysocki111058c2011-08-14 13:35:39 +0200145 genpd->power_off = pd_power_down;
146 genpd->power_on = pd_power_up;
Magnus Damm775b8ae2011-07-10 10:39:32 +0200147 genpd->power_on(&sh7372_pd->genpd);
Rafael J. Wysockie3e01092011-07-01 22:13:56 +0200148}
149
150void sh7372_add_device_to_domain(struct sh7372_pm_domain *sh7372_pd,
151 struct platform_device *pdev)
152{
153 struct device *dev = &pdev->dev;
154
Rafael J. Wysockie3e01092011-07-01 22:13:56 +0200155 pm_genpd_add_device(&sh7372_pd->genpd, dev);
Rafael J. Wysocki4605ab62011-08-25 15:34:12 +0200156 if (pm_clk_no_clocks(dev))
157 pm_clk_add(dev, NULL);
Rafael J. Wysockie3e01092011-07-01 22:13:56 +0200158}
159
Rafael J. Wysocki111058c2011-08-14 13:35:39 +0200160void sh7372_pm_add_subdomain(struct sh7372_pm_domain *sh7372_pd,
161 struct sh7372_pm_domain *sh7372_sd)
162{
163 pm_genpd_add_subdomain(&sh7372_pd->genpd, &sh7372_sd->genpd);
164}
165
Rafael J. Wysockie3e01092011-07-01 22:13:56 +0200166struct sh7372_pm_domain sh7372_a4lc = {
167 .bit_shift = 1,
168};
169
Kuninori Morimotoc1ba5bb2011-07-10 10:12:08 +0200170struct sh7372_pm_domain sh7372_a4mp = {
171 .bit_shift = 2,
172};
173
Magnus Dammd24771d2011-07-10 10:38:22 +0200174struct sh7372_pm_domain sh7372_d4 = {
175 .bit_shift = 3,
176};
177
Magnus Damm33afebf2011-07-01 22:14:45 +0200178struct sh7372_pm_domain sh7372_a3rv = {
179 .bit_shift = 6,
180};
181
Magnus Damm082517a2011-07-01 22:14:53 +0200182struct sh7372_pm_domain sh7372_a3ri = {
183 .bit_shift = 8,
184};
185
Magnus Dammc47586b2011-07-01 22:15:01 +0200186struct sh7372_pm_domain sh7372_a3sg = {
187 .bit_shift = 13,
188};
189
Rafael J. Wysockie3e01092011-07-01 22:13:56 +0200190#endif /* CONFIG_PM */
191
Magnus Damma0089bd2011-09-25 23:21:02 +0200192#if defined(CONFIG_SUSPEND) || defined(CONFIG_CPU_IDLE)
Magnus Damm06b84162011-09-25 23:18:42 +0200193static int sh7372_do_idle_core_standby(unsigned long unused)
194{
195 cpu_do_idle(); /* WFI when SYSTBCR == 0x10 -> Core Standby */
196 return 0;
197}
198
Paul Mundt66ad1292011-05-25 11:22:58 +0900199static void sh7372_enter_core_standby(void)
Magnus Damm97991652011-04-29 02:28:08 +0900200{
Magnus Damm06b84162011-09-25 23:18:42 +0200201 /* set reset vector, translate 4k */
Magnus Dammcf338352011-09-25 23:20:49 +0200202 __raw_writel(__pa(sh7372_resume_core_standby_a3sm), SBAR);
Magnus Damm06b84162011-09-25 23:18:42 +0200203 __raw_writel(0, APARMBAREA);
Magnus Damm97991652011-04-29 02:28:08 +0900204
Magnus Damm06b84162011-09-25 23:18:42 +0200205 /* enter sleep mode with SYSTBCR to 0x10 */
206 __raw_writel(0x10, SYSTBCR);
207 cpu_suspend(0, sh7372_do_idle_core_standby);
208 __raw_writel(0, SYSTBCR);
Magnus Damm97991652011-04-29 02:28:08 +0900209
Magnus Damm06b84162011-09-25 23:18:42 +0200210 /* disable reset vector translation */
211 __raw_writel(0, SBAR);
Magnus Damm97991652011-04-29 02:28:08 +0900212}
Magnus Damma0089bd2011-09-25 23:21:02 +0200213#endif
Magnus Damm97991652011-04-29 02:28:08 +0900214
Magnus Damma0089bd2011-09-25 23:21:02 +0200215#ifdef CONFIG_SUSPEND
Magnus Dammcf338352011-09-25 23:20:49 +0200216static void sh7372_enter_a3sm_common(int pllc0_on)
217{
218 /* set reset vector, translate 4k */
219 __raw_writel(__pa(sh7372_resume_core_standby_a3sm), SBAR);
220 __raw_writel(0, APARMBAREA);
221
222 if (pllc0_on)
223 __raw_writel(0, PLLC01STPCR);
224 else
225 __raw_writel(1 << 28, PLLC01STPCR);
226
227 __raw_writel(0, PDNSEL); /* power-down A3SM only, not A4S */
228 __raw_readl(WUPSFAC); /* read wakeup int. factor before sleep */
229 cpu_suspend(0, sh7372_do_idle_a3sm);
230 __raw_readl(WUPSFAC); /* read wakeup int. factor after wakeup */
231
232 /* disable reset vector translation */
233 __raw_writel(0, SBAR);
234}
235
236static int sh7372_a3sm_valid(unsigned long *mskp, unsigned long *msk2p)
237{
238 unsigned long mstpsr0, mstpsr1, mstpsr2, mstpsr3, mstpsr4;
239 unsigned long msk, msk2;
240
241 /* check active clocks to determine potential wakeup sources */
242
243 mstpsr0 = __raw_readl(MSTPSR0);
244 if ((mstpsr0 & 0x00000003) != 0x00000003) {
245 pr_debug("sh7372 mstpsr0 0x%08lx\n", mstpsr0);
246 return 0;
247 }
248
249 mstpsr1 = __raw_readl(MSTPSR1);
250 if ((mstpsr1 & 0xff079b7f) != 0xff079b7f) {
251 pr_debug("sh7372 mstpsr1 0x%08lx\n", mstpsr1);
252 return 0;
253 }
254
255 mstpsr2 = __raw_readl(MSTPSR2);
256 if ((mstpsr2 & 0x000741ff) != 0x000741ff) {
257 pr_debug("sh7372 mstpsr2 0x%08lx\n", mstpsr2);
258 return 0;
259 }
260
261 mstpsr3 = __raw_readl(MSTPSR3);
262 if ((mstpsr3 & 0x1a60f010) != 0x1a60f010) {
263 pr_debug("sh7372 mstpsr3 0x%08lx\n", mstpsr3);
264 return 0;
265 }
266
267 mstpsr4 = __raw_readl(MSTPSR4);
268 if ((mstpsr4 & 0x00008cf0) != 0x00008cf0) {
269 pr_debug("sh7372 mstpsr4 0x%08lx\n", mstpsr4);
270 return 0;
271 }
272
273 msk = 0;
274 msk2 = 0;
275
276 /* make bitmaps of limited number of wakeup sources */
277
278 if ((mstpsr2 & (1 << 23)) == 0) /* SPU2 */
279 msk |= 1 << 31;
280
281 if ((mstpsr2 & (1 << 12)) == 0) /* MFI_MFIM */
282 msk |= 1 << 21;
283
284 if ((mstpsr4 & (1 << 3)) == 0) /* KEYSC */
285 msk |= 1 << 2;
286
287 if ((mstpsr1 & (1 << 24)) == 0) /* CMT0 */
288 msk |= 1 << 1;
289
290 if ((mstpsr3 & (1 << 29)) == 0) /* CMT1 */
291 msk |= 1 << 1;
292
293 if ((mstpsr4 & (1 << 0)) == 0) /* CMT2 */
294 msk |= 1 << 1;
295
296 if ((mstpsr2 & (1 << 13)) == 0) /* MFI_MFIS */
297 msk2 |= 1 << 17;
298
299 *mskp = msk;
300 *msk2p = msk2;
301
302 return 1;
303}
304
305static void sh7372_icr_to_irqcr(unsigned long icr, u16 *irqcr1p, u16 *irqcr2p)
306{
307 u16 tmp, irqcr1, irqcr2;
308 int k;
309
310 irqcr1 = 0;
311 irqcr2 = 0;
312
313 /* convert INTCA ICR register layout to SYSC IRQCR+IRQCR2 */
314 for (k = 0; k <= 7; k++) {
315 tmp = (icr >> ((7 - k) * 4)) & 0xf;
316 irqcr1 |= (tmp & 0x03) << (k * 2);
317 irqcr2 |= (tmp >> 2) << (k * 2);
318 }
319
320 *irqcr1p = irqcr1;
321 *irqcr2p = irqcr2;
322}
323
324static void sh7372_setup_a3sm(unsigned long msk, unsigned long msk2)
325{
326 u16 irqcrx_low, irqcrx_high, irqcry_low, irqcry_high;
327 unsigned long tmp;
328
329 /* read IRQ0A -> IRQ15A mask */
330 tmp = bitrev8(__raw_readb(INTMSK00A));
331 tmp |= bitrev8(__raw_readb(INTMSK10A)) << 8;
332
333 /* setup WUPSMSK from clocks and external IRQ mask */
334 msk = (~msk & 0xc030000f) | (tmp << 4);
335 __raw_writel(msk, WUPSMSK);
336
337 /* propage level/edge trigger for external IRQ 0->15 */
338 sh7372_icr_to_irqcr(__raw_readl(ICR1A), &irqcrx_low, &irqcry_low);
339 sh7372_icr_to_irqcr(__raw_readl(ICR2A), &irqcrx_high, &irqcry_high);
340 __raw_writel((irqcrx_high << 16) | irqcrx_low, IRQCR);
341 __raw_writel((irqcry_high << 16) | irqcry_low, IRQCR2);
342
343 /* read IRQ16A -> IRQ31A mask */
344 tmp = bitrev8(__raw_readb(INTMSK20A));
345 tmp |= bitrev8(__raw_readb(INTMSK30A)) << 8;
346
347 /* setup WUPSMSK2 from clocks and external IRQ mask */
348 msk2 = (~msk2 & 0x00030000) | tmp;
349 __raw_writel(msk2, WUPSMSK2);
350
351 /* propage level/edge trigger for external IRQ 16->31 */
352 sh7372_icr_to_irqcr(__raw_readl(ICR3A), &irqcrx_low, &irqcry_low);
353 sh7372_icr_to_irqcr(__raw_readl(ICR4A), &irqcrx_high, &irqcry_high);
354 __raw_writel((irqcrx_high << 16) | irqcrx_low, IRQCR3);
355 __raw_writel((irqcry_high << 16) | irqcry_low, IRQCR4);
356}
Magnus Damma0089bd2011-09-25 23:21:02 +0200357#endif
Magnus Dammcf338352011-09-25 23:20:49 +0200358
Magnus Damm082a8ca2011-04-29 02:39:32 +0900359#ifdef CONFIG_CPU_IDLE
Magnus Dammcf338352011-09-25 23:20:49 +0200360
Magnus Damm082a8ca2011-04-29 02:39:32 +0900361static void sh7372_cpuidle_setup(struct cpuidle_device *dev)
362{
363 struct cpuidle_state *state;
364 int i = dev->state_count;
365
366 state = &dev->states[i];
367 snprintf(state->name, CPUIDLE_NAME_LEN, "C2");
368 strncpy(state->desc, "Core Standby Mode", CPUIDLE_DESC_LEN);
369 state->exit_latency = 10;
370 state->target_residency = 20 + 10;
371 state->power_usage = 1; /* perhaps not */
372 state->flags = 0;
373 state->flags |= CPUIDLE_FLAG_TIME_VALID;
374 shmobile_cpuidle_modes[i] = sh7372_enter_core_standby;
375
376 dev->state_count = i + 1;
377}
378
379static void sh7372_cpuidle_init(void)
380{
381 shmobile_cpuidle_setup = sh7372_cpuidle_setup;
382}
383#else
384static void sh7372_cpuidle_init(void) {}
385#endif
386
387#ifdef CONFIG_SUSPEND
Magnus Dammcf338352011-09-25 23:20:49 +0200388
Magnus Damm97991652011-04-29 02:28:08 +0900389static int sh7372_enter_suspend(suspend_state_t suspend_state)
390{
Magnus Dammcf338352011-09-25 23:20:49 +0200391 unsigned long msk, msk2;
392
393 /* check active clocks to determine potential wakeup sources */
394 if (sh7372_a3sm_valid(&msk, &msk2)) {
395
396 /* convert INTC mask and sense to SYSC mask and sense */
397 sh7372_setup_a3sm(msk, msk2);
398
399 /* enter A3SM sleep with PLLC0 off */
400 pr_debug("entering A3SM\n");
401 sh7372_enter_a3sm_common(0);
402 } else {
403 /* default to Core Standby that supports all wakeup sources */
404 pr_debug("entering Core Standby\n");
405 sh7372_enter_core_standby();
406 }
Magnus Damm97991652011-04-29 02:28:08 +0900407 return 0;
408}
409
410static void sh7372_suspend_init(void)
411{
412 shmobile_suspend_ops.enter = sh7372_enter_suspend;
413}
414#else
415static void sh7372_suspend_init(void) {}
416#endif
417
Magnus Damm97991652011-04-29 02:28:08 +0900418void __init sh7372_pm_init(void)
419{
420 /* enable DBG hardware block to kick SYSC */
421 __raw_writel(0x0000a500, DBGREG9);
422 __raw_writel(0x0000a501, DBGREG9);
423 __raw_writel(0x00000000, DBGREG1);
424
425 sh7372_suspend_init();
Magnus Damm082a8ca2011-04-29 02:39:32 +0900426 sh7372_cpuidle_init();
Magnus Damm97991652011-04-29 02:28:08 +0900427}