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Prashant Gaikwadece70092013-03-20 17:30:34 +05301/*
2 * Copyright (c) 2013 NVIDIA CORPORATION. All rights reserved.
3 *
4 * This program is free software; you can redistribute it and/or modify it
5 * under the terms and conditions of the GNU General Public License,
6 * version 2, as published by the Free Software Foundation.
7 *
8 * This program is distributed in the hope it will be useful, but WITHOUT
9 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
10 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
11 * more details.
12 *
13 * You should have received a copy of the GNU General Public License
14 * along with this program. If not, see <http://www.gnu.org/licenses/>.
15 */
16
17#include <linux/clk.h>
18#include <linux/clk-provider.h>
19#include <linux/err.h>
20#include <linux/slab.h>
21
Prashant Gaikwadece70092013-03-20 17:30:34 +053022static u8 clk_composite_get_parent(struct clk_hw *hw)
23{
24 struct clk_composite *composite = to_clk_composite(hw);
25 const struct clk_ops *mux_ops = composite->mux_ops;
26 struct clk_hw *mux_hw = composite->mux_hw;
27
Javier Martinez Canillas4e907ef2015-02-12 14:58:30 +010028 __clk_hw_set_clk(mux_hw, hw);
Prashant Gaikwadece70092013-03-20 17:30:34 +053029
30 return mux_ops->get_parent(mux_hw);
31}
32
33static int clk_composite_set_parent(struct clk_hw *hw, u8 index)
34{
35 struct clk_composite *composite = to_clk_composite(hw);
36 const struct clk_ops *mux_ops = composite->mux_ops;
37 struct clk_hw *mux_hw = composite->mux_hw;
38
Javier Martinez Canillas4e907ef2015-02-12 14:58:30 +010039 __clk_hw_set_clk(mux_hw, hw);
Prashant Gaikwadece70092013-03-20 17:30:34 +053040
41 return mux_ops->set_parent(mux_hw, index);
42}
43
44static unsigned long clk_composite_recalc_rate(struct clk_hw *hw,
45 unsigned long parent_rate)
46{
47 struct clk_composite *composite = to_clk_composite(hw);
Mike Turquetted3a1c7b2013-04-11 11:31:36 -070048 const struct clk_ops *rate_ops = composite->rate_ops;
49 struct clk_hw *rate_hw = composite->rate_hw;
Prashant Gaikwadece70092013-03-20 17:30:34 +053050
Javier Martinez Canillas4e907ef2015-02-12 14:58:30 +010051 __clk_hw_set_clk(rate_hw, hw);
Prashant Gaikwadece70092013-03-20 17:30:34 +053052
Mike Turquetted3a1c7b2013-04-11 11:31:36 -070053 return rate_ops->recalc_rate(rate_hw, parent_rate);
Prashant Gaikwadece70092013-03-20 17:30:34 +053054}
55
Boris Brezillon0817b622015-07-07 20:48:08 +020056static int clk_composite_determine_rate(struct clk_hw *hw,
57 struct clk_rate_request *req)
Emilio López107f3192013-09-14 21:37:59 -030058{
59 struct clk_composite *composite = to_clk_composite(hw);
60 const struct clk_ops *rate_ops = composite->rate_ops;
61 const struct clk_ops *mux_ops = composite->mux_ops;
62 struct clk_hw *rate_hw = composite->rate_hw;
63 struct clk_hw *mux_hw = composite->mux_hw;
Stephen Boyd2f508a92015-07-30 17:20:57 -070064 struct clk_hw *parent;
Boris BREZILLON3eb635f2014-07-03 01:56:45 +020065 unsigned long parent_rate;
66 long tmp_rate, best_rate = 0;
67 unsigned long rate_diff;
68 unsigned long best_rate_diff = ULONG_MAX;
Boris Brezillon0817b622015-07-07 20:48:08 +020069 long rate;
Boris BREZILLON3eb635f2014-07-03 01:56:45 +020070 int i;
Emilio López107f3192013-09-14 21:37:59 -030071
72 if (rate_hw && rate_ops && rate_ops->determine_rate) {
Javier Martinez Canillas4e907ef2015-02-12 14:58:30 +010073 __clk_hw_set_clk(rate_hw, hw);
Boris Brezillon0817b622015-07-07 20:48:08 +020074 return rate_ops->determine_rate(rate_hw, req);
Boris BREZILLON3eb635f2014-07-03 01:56:45 +020075 } else if (rate_hw && rate_ops && rate_ops->round_rate &&
76 mux_hw && mux_ops && mux_ops->set_parent) {
Boris Brezillon0817b622015-07-07 20:48:08 +020077 req->best_parent_hw = NULL;
Boris BREZILLON3eb635f2014-07-03 01:56:45 +020078
Stephen Boyd98d8a602015-06-29 16:56:30 -070079 if (clk_hw_get_flags(hw) & CLK_SET_RATE_NO_REPARENT) {
Stephen Boyd2f508a92015-07-30 17:20:57 -070080 parent = clk_hw_get_parent(mux_hw);
81 req->best_parent_hw = parent;
82 req->best_parent_rate = clk_hw_get_rate(parent);
Boris BREZILLON3eb635f2014-07-03 01:56:45 +020083
Boris Brezillon0817b622015-07-07 20:48:08 +020084 rate = rate_ops->round_rate(rate_hw, req->rate,
85 &req->best_parent_rate);
86 if (rate < 0)
87 return rate;
88
89 req->rate = rate;
90 return 0;
Boris BREZILLON3eb635f2014-07-03 01:56:45 +020091 }
92
Stephen Boyd497295a2015-06-25 16:53:23 -070093 for (i = 0; i < clk_hw_get_num_parents(mux_hw); i++) {
Stephen Boyd2f508a92015-07-30 17:20:57 -070094 parent = clk_hw_get_parent_by_index(mux_hw, i);
Boris BREZILLON3eb635f2014-07-03 01:56:45 +020095 if (!parent)
96 continue;
97
Stephen Boyd2f508a92015-07-30 17:20:57 -070098 parent_rate = clk_hw_get_rate(parent);
Boris BREZILLON3eb635f2014-07-03 01:56:45 +020099
Boris Brezillon0817b622015-07-07 20:48:08 +0200100 tmp_rate = rate_ops->round_rate(rate_hw, req->rate,
Boris BREZILLON3eb635f2014-07-03 01:56:45 +0200101 &parent_rate);
102 if (tmp_rate < 0)
103 continue;
104
Boris Brezillon0817b622015-07-07 20:48:08 +0200105 rate_diff = abs(req->rate - tmp_rate);
Boris BREZILLON3eb635f2014-07-03 01:56:45 +0200106
Boris Brezillon0817b622015-07-07 20:48:08 +0200107 if (!rate_diff || !req->best_parent_hw
Boris BREZILLON3eb635f2014-07-03 01:56:45 +0200108 || best_rate_diff > rate_diff) {
Stephen Boyd2f508a92015-07-30 17:20:57 -0700109 req->best_parent_hw = parent;
Boris Brezillon0817b622015-07-07 20:48:08 +0200110 req->best_parent_rate = parent_rate;
Boris BREZILLON3eb635f2014-07-03 01:56:45 +0200111 best_rate_diff = rate_diff;
112 best_rate = tmp_rate;
113 }
114
115 if (!rate_diff)
Boris Brezillon0817b622015-07-07 20:48:08 +0200116 return 0;
Boris BREZILLON3eb635f2014-07-03 01:56:45 +0200117 }
118
Boris Brezillon0817b622015-07-07 20:48:08 +0200119 req->rate = best_rate;
120 return 0;
Emilio López107f3192013-09-14 21:37:59 -0300121 } else if (mux_hw && mux_ops && mux_ops->determine_rate) {
Javier Martinez Canillas4e907ef2015-02-12 14:58:30 +0100122 __clk_hw_set_clk(mux_hw, hw);
Boris Brezillon0817b622015-07-07 20:48:08 +0200123 return mux_ops->determine_rate(mux_hw, req);
Emilio López107f3192013-09-14 21:37:59 -0300124 } else {
125 pr_err("clk: clk_composite_determine_rate function called, but no mux or rate callback set!\n");
Boris Brezillon57d866e2015-07-09 22:39:38 +0200126 return -EINVAL;
Emilio López107f3192013-09-14 21:37:59 -0300127 }
128}
129
Prashant Gaikwadece70092013-03-20 17:30:34 +0530130static long clk_composite_round_rate(struct clk_hw *hw, unsigned long rate,
131 unsigned long *prate)
132{
133 struct clk_composite *composite = to_clk_composite(hw);
Mike Turquetted3a1c7b2013-04-11 11:31:36 -0700134 const struct clk_ops *rate_ops = composite->rate_ops;
135 struct clk_hw *rate_hw = composite->rate_hw;
Prashant Gaikwadece70092013-03-20 17:30:34 +0530136
Javier Martinez Canillas4e907ef2015-02-12 14:58:30 +0100137 __clk_hw_set_clk(rate_hw, hw);
Prashant Gaikwadece70092013-03-20 17:30:34 +0530138
Mike Turquetted3a1c7b2013-04-11 11:31:36 -0700139 return rate_ops->round_rate(rate_hw, rate, prate);
Prashant Gaikwadece70092013-03-20 17:30:34 +0530140}
141
142static int clk_composite_set_rate(struct clk_hw *hw, unsigned long rate,
143 unsigned long parent_rate)
144{
145 struct clk_composite *composite = to_clk_composite(hw);
Mike Turquetted3a1c7b2013-04-11 11:31:36 -0700146 const struct clk_ops *rate_ops = composite->rate_ops;
147 struct clk_hw *rate_hw = composite->rate_hw;
Prashant Gaikwadece70092013-03-20 17:30:34 +0530148
Javier Martinez Canillas4e907ef2015-02-12 14:58:30 +0100149 __clk_hw_set_clk(rate_hw, hw);
Prashant Gaikwadece70092013-03-20 17:30:34 +0530150
Mike Turquetted3a1c7b2013-04-11 11:31:36 -0700151 return rate_ops->set_rate(rate_hw, rate, parent_rate);
Prashant Gaikwadece70092013-03-20 17:30:34 +0530152}
153
Finley Xiao9e52cec2016-04-12 16:43:39 +0800154static int clk_composite_set_rate_and_parent(struct clk_hw *hw,
155 unsigned long rate,
156 unsigned long parent_rate,
157 u8 index)
158{
159 struct clk_composite *composite = to_clk_composite(hw);
160 const struct clk_ops *rate_ops = composite->rate_ops;
161 const struct clk_ops *mux_ops = composite->mux_ops;
162 struct clk_hw *rate_hw = composite->rate_hw;
163 struct clk_hw *mux_hw = composite->mux_hw;
164 unsigned long temp_rate;
165
166 __clk_hw_set_clk(rate_hw, hw);
167 __clk_hw_set_clk(mux_hw, hw);
168
169 temp_rate = rate_ops->recalc_rate(rate_hw, parent_rate);
170 if (temp_rate > rate) {
171 rate_ops->set_rate(rate_hw, rate, parent_rate);
172 mux_ops->set_parent(mux_hw, index);
173 } else {
174 mux_ops->set_parent(mux_hw, index);
175 rate_ops->set_rate(rate_hw, rate, parent_rate);
176 }
177
178 return 0;
179}
180
Prashant Gaikwadece70092013-03-20 17:30:34 +0530181static int clk_composite_is_enabled(struct clk_hw *hw)
182{
183 struct clk_composite *composite = to_clk_composite(hw);
184 const struct clk_ops *gate_ops = composite->gate_ops;
185 struct clk_hw *gate_hw = composite->gate_hw;
186
Javier Martinez Canillas4e907ef2015-02-12 14:58:30 +0100187 __clk_hw_set_clk(gate_hw, hw);
Prashant Gaikwadece70092013-03-20 17:30:34 +0530188
189 return gate_ops->is_enabled(gate_hw);
190}
191
192static int clk_composite_enable(struct clk_hw *hw)
193{
194 struct clk_composite *composite = to_clk_composite(hw);
195 const struct clk_ops *gate_ops = composite->gate_ops;
196 struct clk_hw *gate_hw = composite->gate_hw;
197
Javier Martinez Canillas4e907ef2015-02-12 14:58:30 +0100198 __clk_hw_set_clk(gate_hw, hw);
Prashant Gaikwadece70092013-03-20 17:30:34 +0530199
200 return gate_ops->enable(gate_hw);
201}
202
203static void clk_composite_disable(struct clk_hw *hw)
204{
205 struct clk_composite *composite = to_clk_composite(hw);
206 const struct clk_ops *gate_ops = composite->gate_ops;
207 struct clk_hw *gate_hw = composite->gate_hw;
208
Javier Martinez Canillas4e907ef2015-02-12 14:58:30 +0100209 __clk_hw_set_clk(gate_hw, hw);
Prashant Gaikwadece70092013-03-20 17:30:34 +0530210
211 gate_ops->disable(gate_hw);
212}
213
Stephen Boyd49cb3922016-02-07 00:20:31 -0800214struct clk_hw *clk_hw_register_composite(struct device *dev, const char *name,
Sascha Hauer2893c372015-03-31 20:16:52 +0200215 const char * const *parent_names, int num_parents,
Prashant Gaikwadece70092013-03-20 17:30:34 +0530216 struct clk_hw *mux_hw, const struct clk_ops *mux_ops,
Mike Turquetted3a1c7b2013-04-11 11:31:36 -0700217 struct clk_hw *rate_hw, const struct clk_ops *rate_ops,
Prashant Gaikwadece70092013-03-20 17:30:34 +0530218 struct clk_hw *gate_hw, const struct clk_ops *gate_ops,
219 unsigned long flags)
220{
Stephen Boyd49cb3922016-02-07 00:20:31 -0800221 struct clk_hw *hw;
Prashant Gaikwadece70092013-03-20 17:30:34 +0530222 struct clk_init_data init;
223 struct clk_composite *composite;
224 struct clk_ops *clk_composite_ops;
Stephen Boyd49cb3922016-02-07 00:20:31 -0800225 int ret;
Prashant Gaikwadece70092013-03-20 17:30:34 +0530226
227 composite = kzalloc(sizeof(*composite), GFP_KERNEL);
Stephen Boydd122db72015-05-14 16:47:10 -0700228 if (!composite)
Prashant Gaikwadece70092013-03-20 17:30:34 +0530229 return ERR_PTR(-ENOMEM);
Prashant Gaikwadece70092013-03-20 17:30:34 +0530230
231 init.name = name;
232 init.flags = flags | CLK_IS_BASIC;
233 init.parent_names = parent_names;
234 init.num_parents = num_parents;
Stephen Boyd49cb3922016-02-07 00:20:31 -0800235 hw = &composite->hw;
Prashant Gaikwadece70092013-03-20 17:30:34 +0530236
237 clk_composite_ops = &composite->ops;
238
239 if (mux_hw && mux_ops) {
Heiko Stübner0c02cf22014-07-03 01:57:30 +0200240 if (!mux_ops->get_parent) {
Stephen Boyd49cb3922016-02-07 00:20:31 -0800241 hw = ERR_PTR(-EINVAL);
Prashant Gaikwadece70092013-03-20 17:30:34 +0530242 goto err;
243 }
244
245 composite->mux_hw = mux_hw;
246 composite->mux_ops = mux_ops;
247 clk_composite_ops->get_parent = clk_composite_get_parent;
Heiko Stübner0c02cf22014-07-03 01:57:30 +0200248 if (mux_ops->set_parent)
249 clk_composite_ops->set_parent = clk_composite_set_parent;
Emilio López107f3192013-09-14 21:37:59 -0300250 if (mux_ops->determine_rate)
251 clk_composite_ops->determine_rate = clk_composite_determine_rate;
Prashant Gaikwadece70092013-03-20 17:30:34 +0530252 }
253
Mike Turquetted3a1c7b2013-04-11 11:31:36 -0700254 if (rate_hw && rate_ops) {
Mike Turquettef363e212013-04-11 11:31:37 -0700255 if (!rate_ops->recalc_rate) {
Stephen Boyd49cb3922016-02-07 00:20:31 -0800256 hw = ERR_PTR(-EINVAL);
Prashant Gaikwadece70092013-03-20 17:30:34 +0530257 goto err;
258 }
Mike Turquette5a994e12014-07-03 01:58:14 +0200259 clk_composite_ops->recalc_rate = clk_composite_recalc_rate;
Prashant Gaikwadece70092013-03-20 17:30:34 +0530260
Mike Turquette5a994e12014-07-03 01:58:14 +0200261 if (rate_ops->determine_rate)
262 clk_composite_ops->determine_rate =
263 clk_composite_determine_rate;
264 else if (rate_ops->round_rate)
265 clk_composite_ops->round_rate =
266 clk_composite_round_rate;
267
268 /* .set_rate requires either .round_rate or .determine_rate */
269 if (rate_ops->set_rate) {
270 if (rate_ops->determine_rate || rate_ops->round_rate)
271 clk_composite_ops->set_rate =
272 clk_composite_set_rate;
273 else
274 WARN(1, "%s: missing round_rate op is required\n",
275 __func__);
Mike Turquettef363e212013-04-11 11:31:37 -0700276 }
277
Mike Turquetted3a1c7b2013-04-11 11:31:36 -0700278 composite->rate_hw = rate_hw;
279 composite->rate_ops = rate_ops;
Prashant Gaikwadece70092013-03-20 17:30:34 +0530280 }
281
Finley Xiao9e52cec2016-04-12 16:43:39 +0800282 if (mux_hw && mux_ops && rate_hw && rate_ops) {
283 if (mux_ops->set_parent && rate_ops->set_rate)
284 clk_composite_ops->set_rate_and_parent =
285 clk_composite_set_rate_and_parent;
286 }
287
Prashant Gaikwadece70092013-03-20 17:30:34 +0530288 if (gate_hw && gate_ops) {
289 if (!gate_ops->is_enabled || !gate_ops->enable ||
290 !gate_ops->disable) {
Stephen Boyd49cb3922016-02-07 00:20:31 -0800291 hw = ERR_PTR(-EINVAL);
Prashant Gaikwadece70092013-03-20 17:30:34 +0530292 goto err;
293 }
294
295 composite->gate_hw = gate_hw;
296 composite->gate_ops = gate_ops;
297 clk_composite_ops->is_enabled = clk_composite_is_enabled;
298 clk_composite_ops->enable = clk_composite_enable;
299 clk_composite_ops->disable = clk_composite_disable;
300 }
301
302 init.ops = clk_composite_ops;
303 composite->hw.init = &init;
304
Stephen Boyd49cb3922016-02-07 00:20:31 -0800305 ret = clk_hw_register(dev, hw);
306 if (ret) {
307 hw = ERR_PTR(ret);
Prashant Gaikwadece70092013-03-20 17:30:34 +0530308 goto err;
Stephen Boyd49cb3922016-02-07 00:20:31 -0800309 }
Prashant Gaikwadece70092013-03-20 17:30:34 +0530310
311 if (composite->mux_hw)
Stephen Boyd49cb3922016-02-07 00:20:31 -0800312 composite->mux_hw->clk = hw->clk;
Prashant Gaikwadece70092013-03-20 17:30:34 +0530313
Mike Turquetted3a1c7b2013-04-11 11:31:36 -0700314 if (composite->rate_hw)
Stephen Boyd49cb3922016-02-07 00:20:31 -0800315 composite->rate_hw->clk = hw->clk;
Prashant Gaikwadece70092013-03-20 17:30:34 +0530316
317 if (composite->gate_hw)
Stephen Boyd49cb3922016-02-07 00:20:31 -0800318 composite->gate_hw->clk = hw->clk;
Prashant Gaikwadece70092013-03-20 17:30:34 +0530319
Stephen Boyd49cb3922016-02-07 00:20:31 -0800320 return hw;
Prashant Gaikwadece70092013-03-20 17:30:34 +0530321
322err:
323 kfree(composite);
Stephen Boyd49cb3922016-02-07 00:20:31 -0800324 return hw;
325}
326
327struct clk *clk_register_composite(struct device *dev, const char *name,
328 const char * const *parent_names, int num_parents,
329 struct clk_hw *mux_hw, const struct clk_ops *mux_ops,
330 struct clk_hw *rate_hw, const struct clk_ops *rate_ops,
331 struct clk_hw *gate_hw, const struct clk_ops *gate_ops,
332 unsigned long flags)
333{
334 struct clk_hw *hw;
335
336 hw = clk_hw_register_composite(dev, name, parent_names, num_parents,
337 mux_hw, mux_ops, rate_hw, rate_ops, gate_hw, gate_ops,
338 flags);
339 if (IS_ERR(hw))
340 return ERR_CAST(hw);
341 return hw->clk;
Prashant Gaikwadece70092013-03-20 17:30:34 +0530342}
Maxime Ripard92a39d92016-03-23 17:38:24 +0100343
344void clk_unregister_composite(struct clk *clk)
345{
346 struct clk_composite *composite;
347 struct clk_hw *hw;
348
349 hw = __clk_get_hw(clk);
350 if (!hw)
351 return;
352
353 composite = to_clk_composite(hw);
354
355 clk_unregister(clk);
356 kfree(composite);
357}