Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 1 | /* |
| 2 | * Copyright 2008 Advanced Micro Devices, Inc. |
| 3 | * Copyright 2008 Red Hat Inc. |
| 4 | * Copyright 2009 Jerome Glisse. |
| 5 | * |
| 6 | * Permission is hereby granted, free of charge, to any person obtaining a |
| 7 | * copy of this software and associated documentation files (the "Software"), |
| 8 | * to deal in the Software without restriction, including without limitation |
| 9 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, |
| 10 | * and/or sell copies of the Software, and to permit persons to whom the |
| 11 | * Software is furnished to do so, subject to the following conditions: |
| 12 | * |
| 13 | * The above copyright notice and this permission notice shall be included in |
| 14 | * all copies or substantial portions of the Software. |
| 15 | * |
| 16 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
| 17 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
| 18 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
| 19 | * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR |
| 20 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, |
| 21 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR |
| 22 | * OTHER DEALINGS IN THE SOFTWARE. |
| 23 | * |
| 24 | * Authors: Dave Airlie |
| 25 | * Alex Deucher |
| 26 | * Jerome Glisse |
Jerome Glisse | c507f7e | 2012-05-09 15:34:58 +0200 | [diff] [blame] | 27 | * Christian König |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 28 | */ |
David Howells | 760285e | 2012-10-02 18:01:07 +0100 | [diff] [blame] | 29 | #include <drm/drmP.h> |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 30 | #include "radeon.h" |
Christian König | 7bd560e | 2012-05-02 15:11:12 +0200 | [diff] [blame] | 31 | |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 32 | /* |
Alex Deucher | 7592328 | 2012-07-17 14:02:38 -0400 | [diff] [blame] | 33 | * Rings |
| 34 | * Most engines on the GPU are fed via ring buffers. Ring |
| 35 | * buffers are areas of GPU accessible memory that the host |
| 36 | * writes commands into and the GPU reads commands out of. |
| 37 | * There is a rptr (read pointer) that determines where the |
| 38 | * GPU is currently reading, and a wptr (write pointer) |
| 39 | * which determines where the host has written. When the |
| 40 | * pointers are equal, the ring is idle. When the host |
| 41 | * writes commands to the ring buffer, it increments the |
| 42 | * wptr. The GPU then starts fetching commands and executes |
| 43 | * them until the pointers are equal again. |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 44 | */ |
Lauri Kasanen | 1109ca0 | 2012-08-31 13:43:50 -0400 | [diff] [blame] | 45 | static int radeon_debugfs_ring_init(struct radeon_device *rdev, struct radeon_ring *ring); |
Jerome Glisse | c507f7e | 2012-05-09 15:34:58 +0200 | [diff] [blame] | 46 | |
Alex Deucher | 7592328 | 2012-07-17 14:02:38 -0400 | [diff] [blame] | 47 | /** |
Alex Deucher | 7592328 | 2012-07-17 14:02:38 -0400 | [diff] [blame] | 48 | * radeon_ring_supports_scratch_reg - check if the ring supports |
| 49 | * writing to scratch registers |
| 50 | * |
| 51 | * @rdev: radeon_device pointer |
| 52 | * @ring: radeon_ring structure holding ring information |
| 53 | * |
| 54 | * Check if a specific ring supports writing to scratch registers (all asics). |
| 55 | * Returns true if the ring supports writing to scratch regs, false if not. |
| 56 | */ |
Alex Deucher | 89d3580 | 2012-07-17 14:02:31 -0400 | [diff] [blame] | 57 | bool radeon_ring_supports_scratch_reg(struct radeon_device *rdev, |
| 58 | struct radeon_ring *ring) |
| 59 | { |
| 60 | switch (ring->idx) { |
| 61 | case RADEON_RING_TYPE_GFX_INDEX: |
| 62 | case CAYMAN_RING_TYPE_CP1_INDEX: |
| 63 | case CAYMAN_RING_TYPE_CP2_INDEX: |
| 64 | return true; |
| 65 | default: |
| 66 | return false; |
| 67 | } |
| 68 | } |
| 69 | |
Alex Deucher | 7592328 | 2012-07-17 14:02:38 -0400 | [diff] [blame] | 70 | /** |
| 71 | * radeon_ring_free_size - update the free size |
| 72 | * |
| 73 | * @rdev: radeon_device pointer |
| 74 | * @ring: radeon_ring structure holding ring information |
| 75 | * |
| 76 | * Update the free dw slots in the ring buffer (all asics). |
| 77 | */ |
Christian König | e32eb50 | 2011-10-23 12:56:27 +0200 | [diff] [blame] | 78 | void radeon_ring_free_size(struct radeon_device *rdev, struct radeon_ring *ring) |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 79 | { |
Christian König | ff212f2 | 2014-02-18 14:52:33 +0100 | [diff] [blame] | 80 | uint32_t rptr = radeon_ring_get_rptr(rdev, ring); |
| 81 | |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 82 | /* This works because ring_size is a power of 2 */ |
Christian König | ff212f2 | 2014-02-18 14:52:33 +0100 | [diff] [blame] | 83 | ring->ring_free_dw = rptr + (ring->ring_size / 4); |
Christian König | e32eb50 | 2011-10-23 12:56:27 +0200 | [diff] [blame] | 84 | ring->ring_free_dw -= ring->wptr; |
| 85 | ring->ring_free_dw &= ring->ptr_mask; |
| 86 | if (!ring->ring_free_dw) { |
Christian König | 82dc62a | 2014-02-18 15:03:22 +0100 | [diff] [blame] | 87 | /* this is an empty ring */ |
Christian König | e32eb50 | 2011-10-23 12:56:27 +0200 | [diff] [blame] | 88 | ring->ring_free_dw = ring->ring_size / 4; |
Christian König | 82dc62a | 2014-02-18 15:03:22 +0100 | [diff] [blame] | 89 | /* update lockup info to avoid false positive */ |
| 90 | radeon_ring_lockup_update(rdev, ring); |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 91 | } |
| 92 | } |
| 93 | |
Alex Deucher | 7592328 | 2012-07-17 14:02:38 -0400 | [diff] [blame] | 94 | /** |
| 95 | * radeon_ring_alloc - allocate space on the ring buffer |
| 96 | * |
| 97 | * @rdev: radeon_device pointer |
| 98 | * @ring: radeon_ring structure holding ring information |
| 99 | * @ndw: number of dwords to allocate in the ring buffer |
| 100 | * |
| 101 | * Allocate @ndw dwords in the ring buffer (all asics). |
| 102 | * Returns 0 on success, error on failure. |
| 103 | */ |
Christian König | e32eb50 | 2011-10-23 12:56:27 +0200 | [diff] [blame] | 104 | int radeon_ring_alloc(struct radeon_device *rdev, struct radeon_ring *ring, unsigned ndw) |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 105 | { |
| 106 | int r; |
| 107 | |
Alex Deucher | fd5d93a | 2013-01-30 14:24:09 -0500 | [diff] [blame] | 108 | /* make sure we aren't trying to allocate more space than there is on the ring */ |
| 109 | if (ndw > (ring->ring_size / 4)) |
| 110 | return -ENOMEM; |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 111 | /* Align requested size with padding so unlock_commit can |
| 112 | * pad safely */ |
Jerome Glisse | 8444d5c | 2013-06-19 10:02:28 -0400 | [diff] [blame] | 113 | radeon_ring_free_size(rdev, ring); |
Christian König | e32eb50 | 2011-10-23 12:56:27 +0200 | [diff] [blame] | 114 | ndw = (ndw + ring->align_mask) & ~ring->align_mask; |
| 115 | while (ndw > (ring->ring_free_dw - 1)) { |
| 116 | radeon_ring_free_size(rdev, ring); |
| 117 | if (ndw < ring->ring_free_dw) { |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 118 | break; |
| 119 | } |
Christian König | 3761552 | 2014-02-18 15:58:31 +0100 | [diff] [blame] | 120 | r = radeon_fence_wait_next(rdev, ring->idx); |
Matthew Garrett | 91700f3 | 2010-04-30 15:24:17 -0400 | [diff] [blame] | 121 | if (r) |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 122 | return r; |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 123 | } |
Christian König | e32eb50 | 2011-10-23 12:56:27 +0200 | [diff] [blame] | 124 | ring->count_dw = ndw; |
| 125 | ring->wptr_old = ring->wptr; |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 126 | return 0; |
| 127 | } |
| 128 | |
Alex Deucher | 7592328 | 2012-07-17 14:02:38 -0400 | [diff] [blame] | 129 | /** |
| 130 | * radeon_ring_lock - lock the ring and allocate space on it |
| 131 | * |
| 132 | * @rdev: radeon_device pointer |
| 133 | * @ring: radeon_ring structure holding ring information |
| 134 | * @ndw: number of dwords to allocate in the ring buffer |
| 135 | * |
| 136 | * Lock the ring and allocate @ndw dwords in the ring buffer |
| 137 | * (all asics). |
| 138 | * Returns 0 on success, error on failure. |
| 139 | */ |
Christian König | e32eb50 | 2011-10-23 12:56:27 +0200 | [diff] [blame] | 140 | int radeon_ring_lock(struct radeon_device *rdev, struct radeon_ring *ring, unsigned ndw) |
Matthew Garrett | 91700f3 | 2010-04-30 15:24:17 -0400 | [diff] [blame] | 141 | { |
| 142 | int r; |
| 143 | |
Christian König | d6999bc | 2012-05-09 15:34:45 +0200 | [diff] [blame] | 144 | mutex_lock(&rdev->ring_lock); |
Christian König | e32eb50 | 2011-10-23 12:56:27 +0200 | [diff] [blame] | 145 | r = radeon_ring_alloc(rdev, ring, ndw); |
Matthew Garrett | 91700f3 | 2010-04-30 15:24:17 -0400 | [diff] [blame] | 146 | if (r) { |
Christian König | d6999bc | 2012-05-09 15:34:45 +0200 | [diff] [blame] | 147 | mutex_unlock(&rdev->ring_lock); |
Matthew Garrett | 91700f3 | 2010-04-30 15:24:17 -0400 | [diff] [blame] | 148 | return r; |
| 149 | } |
| 150 | return 0; |
| 151 | } |
| 152 | |
Alex Deucher | 7592328 | 2012-07-17 14:02:38 -0400 | [diff] [blame] | 153 | /** |
| 154 | * radeon_ring_commit - tell the GPU to execute the new |
| 155 | * commands on the ring buffer |
| 156 | * |
| 157 | * @rdev: radeon_device pointer |
| 158 | * @ring: radeon_ring structure holding ring information |
Michel Dänzer | 1538a9e | 2014-08-18 17:34:55 +0900 | [diff] [blame] | 159 | * @hdp_flush: Whether or not to perform an HDP cache flush |
Alex Deucher | 7592328 | 2012-07-17 14:02:38 -0400 | [diff] [blame] | 160 | * |
| 161 | * Update the wptr (write pointer) to tell the GPU to |
| 162 | * execute new commands on the ring buffer (all asics). |
| 163 | */ |
Michel Dänzer | 1538a9e | 2014-08-18 17:34:55 +0900 | [diff] [blame] | 164 | void radeon_ring_commit(struct radeon_device *rdev, struct radeon_ring *ring, |
| 165 | bool hdp_flush) |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 166 | { |
Michel Dänzer | 72a9987 | 2014-07-31 18:43:49 +0900 | [diff] [blame] | 167 | /* If we are emitting the HDP flush via the ring buffer, we need to |
| 168 | * do it before padding. |
| 169 | */ |
Michel Dänzer | 1538a9e | 2014-08-18 17:34:55 +0900 | [diff] [blame] | 170 | if (hdp_flush && rdev->asic->ring[ring->idx]->hdp_flush) |
Michel Dänzer | 72a9987 | 2014-07-31 18:43:49 +0900 | [diff] [blame] | 171 | rdev->asic->ring[ring->idx]->hdp_flush(rdev, ring); |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 172 | /* We pad to match fetch size */ |
Christian König | 07a7133 | 2012-07-07 12:11:32 +0200 | [diff] [blame] | 173 | while (ring->wptr & ring->align_mask) { |
Alex Deucher | 78c5560 | 2011-11-17 14:25:56 -0500 | [diff] [blame] | 174 | radeon_ring_write(ring, ring->nop); |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 175 | } |
Daniel Vetter | 85b2331 | 2013-12-11 11:34:45 +0100 | [diff] [blame] | 176 | mb(); |
Michel Dänzer | 72a9987 | 2014-07-31 18:43:49 +0900 | [diff] [blame] | 177 | /* If we are emitting the HDP flush via MMIO, we need to do it after |
| 178 | * all CPU writes to VRAM finished. |
| 179 | */ |
Michel Dänzer | 1538a9e | 2014-08-18 17:34:55 +0900 | [diff] [blame] | 180 | if (hdp_flush && rdev->asic->mmio_hdp_flush) |
Michel Dänzer | 72a9987 | 2014-07-31 18:43:49 +0900 | [diff] [blame] | 181 | rdev->asic->mmio_hdp_flush(rdev); |
Alex Deucher | f93bdef | 2013-01-29 14:10:56 -0500 | [diff] [blame] | 182 | radeon_ring_set_wptr(rdev, ring); |
Matthew Garrett | 91700f3 | 2010-04-30 15:24:17 -0400 | [diff] [blame] | 183 | } |
| 184 | |
Alex Deucher | 7592328 | 2012-07-17 14:02:38 -0400 | [diff] [blame] | 185 | /** |
| 186 | * radeon_ring_unlock_commit - tell the GPU to execute the new |
| 187 | * commands on the ring buffer and unlock it |
| 188 | * |
| 189 | * @rdev: radeon_device pointer |
| 190 | * @ring: radeon_ring structure holding ring information |
Michel Dänzer | 1538a9e | 2014-08-18 17:34:55 +0900 | [diff] [blame] | 191 | * @hdp_flush: Whether or not to perform an HDP cache flush |
Alex Deucher | 7592328 | 2012-07-17 14:02:38 -0400 | [diff] [blame] | 192 | * |
| 193 | * Call radeon_ring_commit() then unlock the ring (all asics). |
| 194 | */ |
Michel Dänzer | 1538a9e | 2014-08-18 17:34:55 +0900 | [diff] [blame] | 195 | void radeon_ring_unlock_commit(struct radeon_device *rdev, struct radeon_ring *ring, |
| 196 | bool hdp_flush) |
Matthew Garrett | 91700f3 | 2010-04-30 15:24:17 -0400 | [diff] [blame] | 197 | { |
Michel Dänzer | 1538a9e | 2014-08-18 17:34:55 +0900 | [diff] [blame] | 198 | radeon_ring_commit(rdev, ring, hdp_flush); |
Christian König | d6999bc | 2012-05-09 15:34:45 +0200 | [diff] [blame] | 199 | mutex_unlock(&rdev->ring_lock); |
| 200 | } |
| 201 | |
Alex Deucher | 7592328 | 2012-07-17 14:02:38 -0400 | [diff] [blame] | 202 | /** |
| 203 | * radeon_ring_undo - reset the wptr |
| 204 | * |
| 205 | * @ring: radeon_ring structure holding ring information |
| 206 | * |
Paul Bolle | 501f9d4c | 2012-11-20 22:31:06 +0100 | [diff] [blame] | 207 | * Reset the driver's copy of the wptr (all asics). |
Alex Deucher | 7592328 | 2012-07-17 14:02:38 -0400 | [diff] [blame] | 208 | */ |
Christian König | d6999bc | 2012-05-09 15:34:45 +0200 | [diff] [blame] | 209 | void radeon_ring_undo(struct radeon_ring *ring) |
| 210 | { |
| 211 | ring->wptr = ring->wptr_old; |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 212 | } |
| 213 | |
Alex Deucher | 7592328 | 2012-07-17 14:02:38 -0400 | [diff] [blame] | 214 | /** |
| 215 | * radeon_ring_unlock_undo - reset the wptr and unlock the ring |
| 216 | * |
| 217 | * @ring: radeon_ring structure holding ring information |
| 218 | * |
| 219 | * Call radeon_ring_undo() then unlock the ring (all asics). |
| 220 | */ |
Christian König | e32eb50 | 2011-10-23 12:56:27 +0200 | [diff] [blame] | 221 | void radeon_ring_unlock_undo(struct radeon_device *rdev, struct radeon_ring *ring) |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 222 | { |
Christian König | d6999bc | 2012-05-09 15:34:45 +0200 | [diff] [blame] | 223 | radeon_ring_undo(ring); |
| 224 | mutex_unlock(&rdev->ring_lock); |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 225 | } |
| 226 | |
Alex Deucher | 7592328 | 2012-07-17 14:02:38 -0400 | [diff] [blame] | 227 | /** |
Paul Bolle | 501f9d4c | 2012-11-20 22:31:06 +0100 | [diff] [blame] | 228 | * radeon_ring_lockup_update - update lockup variables |
Alex Deucher | 7592328 | 2012-07-17 14:02:38 -0400 | [diff] [blame] | 229 | * |
| 230 | * @ring: radeon_ring structure holding ring information |
| 231 | * |
| 232 | * Update the last rptr value and timestamp (all asics). |
| 233 | */ |
Christian König | ff212f2 | 2014-02-18 14:52:33 +0100 | [diff] [blame] | 234 | void radeon_ring_lockup_update(struct radeon_device *rdev, |
| 235 | struct radeon_ring *ring) |
Christian König | 069211e | 2012-05-02 15:11:20 +0200 | [diff] [blame] | 236 | { |
Christian König | aee4aa7 | 2014-02-18 15:24:06 +0100 | [diff] [blame] | 237 | atomic_set(&ring->last_rptr, radeon_ring_get_rptr(rdev, ring)); |
| 238 | atomic64_set(&ring->last_activity, jiffies_64); |
Christian König | 069211e | 2012-05-02 15:11:20 +0200 | [diff] [blame] | 239 | } |
| 240 | |
| 241 | /** |
| 242 | * radeon_ring_test_lockup() - check if ring is lockedup by recording information |
| 243 | * @rdev: radeon device structure |
| 244 | * @ring: radeon_ring structure holding ring information |
| 245 | * |
Christian König | 2d2fe3f | 2014-02-18 12:37:50 +0100 | [diff] [blame] | 246 | */ |
Christian König | 069211e | 2012-05-02 15:11:20 +0200 | [diff] [blame] | 247 | bool radeon_ring_test_lockup(struct radeon_device *rdev, struct radeon_ring *ring) |
| 248 | { |
Christian König | ff212f2 | 2014-02-18 14:52:33 +0100 | [diff] [blame] | 249 | uint32_t rptr = radeon_ring_get_rptr(rdev, ring); |
Christian König | aee4aa7 | 2014-02-18 15:24:06 +0100 | [diff] [blame] | 250 | uint64_t last = atomic64_read(&ring->last_activity); |
| 251 | uint64_t elapsed; |
Christian König | 069211e | 2012-05-02 15:11:20 +0200 | [diff] [blame] | 252 | |
Christian König | aee4aa7 | 2014-02-18 15:24:06 +0100 | [diff] [blame] | 253 | if (rptr != atomic_read(&ring->last_rptr)) { |
| 254 | /* ring is still working, no lockup */ |
Christian König | ff212f2 | 2014-02-18 14:52:33 +0100 | [diff] [blame] | 255 | radeon_ring_lockup_update(rdev, ring); |
Christian König | 069211e | 2012-05-02 15:11:20 +0200 | [diff] [blame] | 256 | return false; |
| 257 | } |
Christian König | aee4aa7 | 2014-02-18 15:24:06 +0100 | [diff] [blame] | 258 | |
| 259 | elapsed = jiffies_to_msecs(jiffies_64 - last); |
Christian König | 3368ff0 | 2012-05-02 15:11:21 +0200 | [diff] [blame] | 260 | if (radeon_lockup_timeout && elapsed >= radeon_lockup_timeout) { |
Christian König | aee4aa7 | 2014-02-18 15:24:06 +0100 | [diff] [blame] | 261 | dev_err(rdev->dev, "ring %d stalled for more than %llumsec\n", |
| 262 | ring->idx, elapsed); |
Christian König | 069211e | 2012-05-02 15:11:20 +0200 | [diff] [blame] | 263 | return true; |
| 264 | } |
| 265 | /* give a chance to the GPU ... */ |
| 266 | return false; |
| 267 | } |
| 268 | |
Christian König | 55d7c22 | 2012-07-09 11:52:44 +0200 | [diff] [blame] | 269 | /** |
| 270 | * radeon_ring_backup - Back up the content of a ring |
| 271 | * |
| 272 | * @rdev: radeon_device pointer |
| 273 | * @ring: the ring we want to back up |
| 274 | * |
| 275 | * Saves all unprocessed commits from a ring, returns the number of dwords saved. |
| 276 | */ |
| 277 | unsigned radeon_ring_backup(struct radeon_device *rdev, struct radeon_ring *ring, |
| 278 | uint32_t **data) |
| 279 | { |
| 280 | unsigned size, ptr, i; |
Christian König | 55d7c22 | 2012-07-09 11:52:44 +0200 | [diff] [blame] | 281 | |
| 282 | /* just in case lock the ring */ |
| 283 | mutex_lock(&rdev->ring_lock); |
| 284 | *data = NULL; |
| 285 | |
Alex Deucher | 89d3580 | 2012-07-17 14:02:31 -0400 | [diff] [blame] | 286 | if (ring->ring_obj == NULL) { |
Christian König | 55d7c22 | 2012-07-09 11:52:44 +0200 | [diff] [blame] | 287 | mutex_unlock(&rdev->ring_lock); |
| 288 | return 0; |
| 289 | } |
| 290 | |
| 291 | /* it doesn't make sense to save anything if all fences are signaled */ |
Alex Deucher | 8b25ed3 | 2012-07-17 14:02:30 -0400 | [diff] [blame] | 292 | if (!radeon_fence_count_emitted(rdev, ring->idx)) { |
Christian König | 55d7c22 | 2012-07-09 11:52:44 +0200 | [diff] [blame] | 293 | mutex_unlock(&rdev->ring_lock); |
| 294 | return 0; |
| 295 | } |
| 296 | |
| 297 | /* calculate the number of dw on the ring */ |
Alex Deucher | 89d3580 | 2012-07-17 14:02:31 -0400 | [diff] [blame] | 298 | if (ring->rptr_save_reg) |
| 299 | ptr = RREG32(ring->rptr_save_reg); |
| 300 | else if (rdev->wb.enabled) |
| 301 | ptr = le32_to_cpu(*ring->next_rptr_cpu_addr); |
| 302 | else { |
| 303 | /* no way to read back the next rptr */ |
| 304 | mutex_unlock(&rdev->ring_lock); |
| 305 | return 0; |
| 306 | } |
| 307 | |
Christian König | 55d7c22 | 2012-07-09 11:52:44 +0200 | [diff] [blame] | 308 | size = ring->wptr + (ring->ring_size / 4); |
| 309 | size -= ptr; |
| 310 | size &= ring->ptr_mask; |
| 311 | if (size == 0) { |
| 312 | mutex_unlock(&rdev->ring_lock); |
| 313 | return 0; |
| 314 | } |
| 315 | |
| 316 | /* and then save the content of the ring */ |
Michel Dänzer | e5a5fd4 | 2014-10-20 18:40:54 +0900 | [diff] [blame] | 317 | *data = drm_malloc_ab(size, sizeof(uint32_t)); |
Dan Carpenter | 1e179d4 | 2012-07-20 14:17:00 +0300 | [diff] [blame] | 318 | if (!*data) { |
| 319 | mutex_unlock(&rdev->ring_lock); |
| 320 | return 0; |
| 321 | } |
Christian König | 55d7c22 | 2012-07-09 11:52:44 +0200 | [diff] [blame] | 322 | for (i = 0; i < size; ++i) { |
| 323 | (*data)[i] = ring->ring[ptr++]; |
| 324 | ptr &= ring->ptr_mask; |
| 325 | } |
| 326 | |
| 327 | mutex_unlock(&rdev->ring_lock); |
| 328 | return size; |
| 329 | } |
| 330 | |
| 331 | /** |
| 332 | * radeon_ring_restore - append saved commands to the ring again |
| 333 | * |
| 334 | * @rdev: radeon_device pointer |
| 335 | * @ring: ring to append commands to |
| 336 | * @size: number of dwords we want to write |
| 337 | * @data: saved commands |
| 338 | * |
| 339 | * Allocates space on the ring and restore the previously saved commands. |
| 340 | */ |
| 341 | int radeon_ring_restore(struct radeon_device *rdev, struct radeon_ring *ring, |
| 342 | unsigned size, uint32_t *data) |
| 343 | { |
| 344 | int i, r; |
| 345 | |
| 346 | if (!size || !data) |
| 347 | return 0; |
| 348 | |
| 349 | /* restore the saved ring content */ |
| 350 | r = radeon_ring_lock(rdev, ring, size); |
| 351 | if (r) |
| 352 | return r; |
| 353 | |
| 354 | for (i = 0; i < size; ++i) { |
| 355 | radeon_ring_write(ring, data[i]); |
| 356 | } |
| 357 | |
Michel Dänzer | 1538a9e | 2014-08-18 17:34:55 +0900 | [diff] [blame] | 358 | radeon_ring_unlock_commit(rdev, ring, false); |
Michel Dänzer | e5a5fd4 | 2014-10-20 18:40:54 +0900 | [diff] [blame] | 359 | drm_free_large(data); |
Christian König | 55d7c22 | 2012-07-09 11:52:44 +0200 | [diff] [blame] | 360 | return 0; |
| 361 | } |
| 362 | |
Alex Deucher | 7592328 | 2012-07-17 14:02:38 -0400 | [diff] [blame] | 363 | /** |
| 364 | * radeon_ring_init - init driver ring struct. |
| 365 | * |
| 366 | * @rdev: radeon_device pointer |
| 367 | * @ring: radeon_ring structure holding ring information |
| 368 | * @ring_size: size of the ring |
| 369 | * @rptr_offs: offset of the rptr writeback location in the WB buffer |
Alex Deucher | 7592328 | 2012-07-17 14:02:38 -0400 | [diff] [blame] | 370 | * @nop: nop packet for this ring |
| 371 | * |
| 372 | * Initialize the driver information for the selected ring (all asics). |
| 373 | * Returns 0 on success, error on failure. |
| 374 | */ |
Christian König | e32eb50 | 2011-10-23 12:56:27 +0200 | [diff] [blame] | 375 | int radeon_ring_init(struct radeon_device *rdev, struct radeon_ring *ring, unsigned ring_size, |
Alex Deucher | ea31bf6 | 2013-12-09 19:44:30 -0500 | [diff] [blame] | 376 | unsigned rptr_offs, u32 nop) |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 377 | { |
| 378 | int r; |
| 379 | |
Christian König | e32eb50 | 2011-10-23 12:56:27 +0200 | [diff] [blame] | 380 | ring->ring_size = ring_size; |
| 381 | ring->rptr_offs = rptr_offs; |
Alex Deucher | 78c5560 | 2011-11-17 14:25:56 -0500 | [diff] [blame] | 382 | ring->nop = nop; |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 383 | /* Allocate ring buffer */ |
Christian König | e32eb50 | 2011-10-23 12:56:27 +0200 | [diff] [blame] | 384 | if (ring->ring_obj == NULL) { |
| 385 | r = radeon_bo_create(rdev, ring->ring_size, PAGE_SIZE, true, |
Maarten Lankhorst | 831b696 | 2014-09-18 14:11:56 +0200 | [diff] [blame] | 386 | RADEON_GEM_DOMAIN_GTT, 0, NULL, |
Alex Deucher | 40f5cf9 | 2012-05-10 18:33:13 -0400 | [diff] [blame] | 387 | NULL, &ring->ring_obj); |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 388 | if (r) { |
Jerome Glisse | 4c78867 | 2009-11-20 14:29:23 +0100 | [diff] [blame] | 389 | dev_err(rdev->dev, "(%d) ring create failed\n", r); |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 390 | return r; |
| 391 | } |
Christian König | e32eb50 | 2011-10-23 12:56:27 +0200 | [diff] [blame] | 392 | r = radeon_bo_reserve(ring->ring_obj, false); |
Jerome Glisse | 4c78867 | 2009-11-20 14:29:23 +0100 | [diff] [blame] | 393 | if (unlikely(r != 0)) |
| 394 | return r; |
Christian König | e32eb50 | 2011-10-23 12:56:27 +0200 | [diff] [blame] | 395 | r = radeon_bo_pin(ring->ring_obj, RADEON_GEM_DOMAIN_GTT, |
| 396 | &ring->gpu_addr); |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 397 | if (r) { |
Christian König | e32eb50 | 2011-10-23 12:56:27 +0200 | [diff] [blame] | 398 | radeon_bo_unreserve(ring->ring_obj); |
Jerome Glisse | 4c78867 | 2009-11-20 14:29:23 +0100 | [diff] [blame] | 399 | dev_err(rdev->dev, "(%d) ring pin failed\n", r); |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 400 | return r; |
| 401 | } |
Christian König | e32eb50 | 2011-10-23 12:56:27 +0200 | [diff] [blame] | 402 | r = radeon_bo_kmap(ring->ring_obj, |
| 403 | (void **)&ring->ring); |
| 404 | radeon_bo_unreserve(ring->ring_obj); |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 405 | if (r) { |
Jerome Glisse | 4c78867 | 2009-11-20 14:29:23 +0100 | [diff] [blame] | 406 | dev_err(rdev->dev, "(%d) ring map failed\n", r); |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 407 | return r; |
| 408 | } |
| 409 | } |
Christian König | e32eb50 | 2011-10-23 12:56:27 +0200 | [diff] [blame] | 410 | ring->ptr_mask = (ring->ring_size / 4) - 1; |
| 411 | ring->ring_free_dw = ring->ring_size / 4; |
Alex Deucher | 89d3580 | 2012-07-17 14:02:31 -0400 | [diff] [blame] | 412 | if (rdev->wb.enabled) { |
| 413 | u32 index = RADEON_WB_RING0_NEXT_RPTR + (ring->idx * 4); |
| 414 | ring->next_rptr_gpu_addr = rdev->wb.gpu_addr + index; |
| 415 | ring->next_rptr_cpu_addr = &rdev->wb.wb[index/4]; |
| 416 | } |
Christian König | ec1a6cc | 2012-05-02 15:11:11 +0200 | [diff] [blame] | 417 | if (radeon_debugfs_ring_init(rdev, ring)) { |
| 418 | DRM_ERROR("Failed to register debugfs file for rings !\n"); |
| 419 | } |
Christian König | ff212f2 | 2014-02-18 14:52:33 +0100 | [diff] [blame] | 420 | radeon_ring_lockup_update(rdev, ring); |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 421 | return 0; |
| 422 | } |
| 423 | |
Alex Deucher | 7592328 | 2012-07-17 14:02:38 -0400 | [diff] [blame] | 424 | /** |
| 425 | * radeon_ring_fini - tear down the driver ring struct. |
| 426 | * |
| 427 | * @rdev: radeon_device pointer |
| 428 | * @ring: radeon_ring structure holding ring information |
| 429 | * |
| 430 | * Tear down the driver information for the selected ring (all asics). |
| 431 | */ |
Christian König | e32eb50 | 2011-10-23 12:56:27 +0200 | [diff] [blame] | 432 | void radeon_ring_fini(struct radeon_device *rdev, struct radeon_ring *ring) |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 433 | { |
Jerome Glisse | 4c78867 | 2009-11-20 14:29:23 +0100 | [diff] [blame] | 434 | int r; |
Alex Deucher | ca2af92 | 2010-05-06 11:02:24 -0400 | [diff] [blame] | 435 | struct radeon_bo *ring_obj; |
Jerome Glisse | 4c78867 | 2009-11-20 14:29:23 +0100 | [diff] [blame] | 436 | |
Christian König | d6999bc | 2012-05-09 15:34:45 +0200 | [diff] [blame] | 437 | mutex_lock(&rdev->ring_lock); |
Christian König | e32eb50 | 2011-10-23 12:56:27 +0200 | [diff] [blame] | 438 | ring_obj = ring->ring_obj; |
Christian König | d6999bc | 2012-05-09 15:34:45 +0200 | [diff] [blame] | 439 | ring->ready = false; |
Christian König | e32eb50 | 2011-10-23 12:56:27 +0200 | [diff] [blame] | 440 | ring->ring = NULL; |
| 441 | ring->ring_obj = NULL; |
Christian König | d6999bc | 2012-05-09 15:34:45 +0200 | [diff] [blame] | 442 | mutex_unlock(&rdev->ring_lock); |
Alex Deucher | ca2af92 | 2010-05-06 11:02:24 -0400 | [diff] [blame] | 443 | |
| 444 | if (ring_obj) { |
| 445 | r = radeon_bo_reserve(ring_obj, false); |
| 446 | if (likely(r == 0)) { |
| 447 | radeon_bo_kunmap(ring_obj); |
| 448 | radeon_bo_unpin(ring_obj); |
| 449 | radeon_bo_unreserve(ring_obj); |
| 450 | } |
| 451 | radeon_bo_unref(&ring_obj); |
| 452 | } |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 453 | } |
| 454 | |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 455 | /* |
| 456 | * Debugfs info |
| 457 | */ |
| 458 | #if defined(CONFIG_DEBUG_FS) |
Christian König | af9720f | 2011-10-24 17:08:44 +0200 | [diff] [blame] | 459 | |
| 460 | static int radeon_debugfs_ring_info(struct seq_file *m, void *data) |
| 461 | { |
| 462 | struct drm_info_node *node = (struct drm_info_node *) m->private; |
| 463 | struct drm_device *dev = node->minor->dev; |
| 464 | struct radeon_device *rdev = dev->dev_private; |
| 465 | int ridx = *(int*)node->info_ent->data; |
| 466 | struct radeon_ring *ring = &rdev->ring[ridx]; |
Christian König | df893a2 | 2013-12-12 09:42:37 +0100 | [diff] [blame] | 467 | |
| 468 | uint32_t rptr, wptr, rptr_next; |
Christian König | af9720f | 2011-10-24 17:08:44 +0200 | [diff] [blame] | 469 | unsigned count, i, j; |
| 470 | |
| 471 | radeon_ring_free_size(rdev, ring); |
| 472 | count = (ring->ring_size / 4) - ring->ring_free_dw; |
Christian König | df893a2 | 2013-12-12 09:42:37 +0100 | [diff] [blame] | 473 | |
| 474 | wptr = radeon_ring_get_wptr(rdev, ring); |
Alex Deucher | ea31bf6 | 2013-12-09 19:44:30 -0500 | [diff] [blame] | 475 | seq_printf(m, "wptr: 0x%08x [%5d]\n", |
| 476 | wptr, wptr); |
Christian König | df893a2 | 2013-12-12 09:42:37 +0100 | [diff] [blame] | 477 | |
| 478 | rptr = radeon_ring_get_rptr(rdev, ring); |
Alex Deucher | ea31bf6 | 2013-12-09 19:44:30 -0500 | [diff] [blame] | 479 | seq_printf(m, "rptr: 0x%08x [%5d]\n", |
| 480 | rptr, rptr); |
Christian König | df893a2 | 2013-12-12 09:42:37 +0100 | [diff] [blame] | 481 | |
Christian König | 45df680 | 2012-07-06 16:22:55 +0200 | [diff] [blame] | 482 | if (ring->rptr_save_reg) { |
Christian König | df893a2 | 2013-12-12 09:42:37 +0100 | [diff] [blame] | 483 | rptr_next = RREG32(ring->rptr_save_reg); |
| 484 | seq_printf(m, "rptr next(0x%04x): 0x%08x [%5d]\n", |
| 485 | ring->rptr_save_reg, rptr_next, rptr_next); |
| 486 | } else |
| 487 | rptr_next = ~0; |
| 488 | |
| 489 | seq_printf(m, "driver's copy of the wptr: 0x%08x [%5d]\n", |
| 490 | ring->wptr, ring->wptr); |
Christian König | df893a2 | 2013-12-12 09:42:37 +0100 | [diff] [blame] | 491 | seq_printf(m, "last semaphore signal addr : 0x%016llx\n", |
| 492 | ring->last_semaphore_signal_addr); |
| 493 | seq_printf(m, "last semaphore wait addr : 0x%016llx\n", |
| 494 | ring->last_semaphore_wait_addr); |
Christian König | af9720f | 2011-10-24 17:08:44 +0200 | [diff] [blame] | 495 | seq_printf(m, "%u free dwords in ring\n", ring->ring_free_dw); |
| 496 | seq_printf(m, "%u dwords in ring\n", count); |
Christian König | df893a2 | 2013-12-12 09:42:37 +0100 | [diff] [blame] | 497 | |
Christian König | 1b01fc3 | 2015-03-23 11:32:59 +0100 | [diff] [blame] | 498 | if (!ring->ring) |
Christian König | df893a2 | 2013-12-12 09:42:37 +0100 | [diff] [blame] | 499 | return 0; |
| 500 | |
Jerome Glisse | 4d00919 | 2013-01-02 17:30:34 -0500 | [diff] [blame] | 501 | /* print 8 dw before current rptr as often it's the last executed |
| 502 | * packet that is the root issue |
| 503 | */ |
Christian König | df893a2 | 2013-12-12 09:42:37 +0100 | [diff] [blame] | 504 | i = (rptr + ring->ptr_mask + 1 - 32) & ring->ptr_mask; |
| 505 | for (j = 0; j <= (count + 32); j++) { |
| 506 | seq_printf(m, "r[%5d]=0x%08x", i, ring->ring[i]); |
| 507 | if (rptr == i) |
| 508 | seq_puts(m, " *"); |
| 509 | if (rptr_next == i) |
| 510 | seq_puts(m, " #"); |
| 511 | seq_puts(m, "\n"); |
| 512 | i = (i + 1) & ring->ptr_mask; |
Christian König | af9720f | 2011-10-24 17:08:44 +0200 | [diff] [blame] | 513 | } |
| 514 | return 0; |
| 515 | } |
| 516 | |
Christian König | f2ba57b | 2013-04-08 12:41:29 +0200 | [diff] [blame] | 517 | static int radeon_gfx_index = RADEON_RING_TYPE_GFX_INDEX; |
| 518 | static int cayman_cp1_index = CAYMAN_RING_TYPE_CP1_INDEX; |
| 519 | static int cayman_cp2_index = CAYMAN_RING_TYPE_CP2_INDEX; |
| 520 | static int radeon_dma1_index = R600_RING_TYPE_DMA_INDEX; |
| 521 | static int radeon_dma2_index = CAYMAN_RING_TYPE_DMA1_INDEX; |
| 522 | static int r600_uvd_index = R600_RING_TYPE_UVD_INDEX; |
Christian König | d93f793 | 2013-05-23 12:10:04 +0200 | [diff] [blame] | 523 | static int si_vce1_index = TN_RING_TYPE_VCE1_INDEX; |
| 524 | static int si_vce2_index = TN_RING_TYPE_VCE2_INDEX; |
Christian König | af9720f | 2011-10-24 17:08:44 +0200 | [diff] [blame] | 525 | |
| 526 | static struct drm_info_list radeon_debugfs_ring_info_list[] = { |
Christian König | f2ba57b | 2013-04-08 12:41:29 +0200 | [diff] [blame] | 527 | {"radeon_ring_gfx", radeon_debugfs_ring_info, 0, &radeon_gfx_index}, |
| 528 | {"radeon_ring_cp1", radeon_debugfs_ring_info, 0, &cayman_cp1_index}, |
| 529 | {"radeon_ring_cp2", radeon_debugfs_ring_info, 0, &cayman_cp2_index}, |
| 530 | {"radeon_ring_dma1", radeon_debugfs_ring_info, 0, &radeon_dma1_index}, |
| 531 | {"radeon_ring_dma2", radeon_debugfs_ring_info, 0, &radeon_dma2_index}, |
| 532 | {"radeon_ring_uvd", radeon_debugfs_ring_info, 0, &r600_uvd_index}, |
Christian König | d93f793 | 2013-05-23 12:10:04 +0200 | [diff] [blame] | 533 | {"radeon_ring_vce1", radeon_debugfs_ring_info, 0, &si_vce1_index}, |
| 534 | {"radeon_ring_vce2", radeon_debugfs_ring_info, 0, &si_vce2_index}, |
Christian König | af9720f | 2011-10-24 17:08:44 +0200 | [diff] [blame] | 535 | }; |
| 536 | |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 537 | #endif |
| 538 | |
Lauri Kasanen | 1109ca0 | 2012-08-31 13:43:50 -0400 | [diff] [blame] | 539 | static int radeon_debugfs_ring_init(struct radeon_device *rdev, struct radeon_ring *ring) |
Christian König | af9720f | 2011-10-24 17:08:44 +0200 | [diff] [blame] | 540 | { |
| 541 | #if defined(CONFIG_DEBUG_FS) |
Christian König | ec1a6cc | 2012-05-02 15:11:11 +0200 | [diff] [blame] | 542 | unsigned i; |
| 543 | for (i = 0; i < ARRAY_SIZE(radeon_debugfs_ring_info_list); ++i) { |
| 544 | struct drm_info_list *info = &radeon_debugfs_ring_info_list[i]; |
| 545 | int ridx = *(int*)radeon_debugfs_ring_info_list[i].data; |
| 546 | unsigned r; |
| 547 | |
| 548 | if (&rdev->ring[ridx] != ring) |
| 549 | continue; |
| 550 | |
| 551 | r = radeon_debugfs_add_files(rdev, info, 1); |
| 552 | if (r) |
| 553 | return r; |
| 554 | } |
Christian König | af9720f | 2011-10-24 17:08:44 +0200 | [diff] [blame] | 555 | #endif |
Christian König | ec1a6cc | 2012-05-02 15:11:11 +0200 | [diff] [blame] | 556 | return 0; |
Christian König | af9720f | 2011-10-24 17:08:44 +0200 | [diff] [blame] | 557 | } |