blob: 97e35c8fec6b2282cf8f67a116f6e10af976bf09 [file] [log] [blame]
Divy Le Ray4d22de32007-01-18 22:04:14 -05001/*
2 * This file is part of the Chelsio T3 Ethernet driver for Linux.
3 *
4 * Copyright (C) 2003-2006 Chelsio Communications. All rights reserved.
5 *
6 * This program is distributed in the hope that it will be useful, but WITHOUT
7 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
8 * FITNESS FOR A PARTICULAR PURPOSE. See the LICENSE file included in this
9 * release for licensing terms and conditions.
10 */
11
12/* This file should not be included directly. Include common.h instead. */
13
14#ifndef __T3_ADAPTER_H__
15#define __T3_ADAPTER_H__
16
17#include <linux/pci.h>
18#include <linux/spinlock.h>
19#include <linux/interrupt.h>
20#include <linux/timer.h>
21#include <linux/cache.h>
Divy Le Raya13fbee2007-01-30 19:44:29 -080022#include <linux/mutex.h>
Divy Le Ray4d22de32007-01-18 22:04:14 -050023#include "t3cdev.h"
24#include <asm/semaphore.h>
25#include <asm/bitops.h>
26#include <asm/io.h>
27
28typedef irqreturn_t(*intr_handler_t) (int, void *);
29
30struct vlan_group;
31
32struct port_info {
33 struct vlan_group *vlan_grp;
34 const struct port_type_info *port_type;
35 u8 port_id;
36 u8 rx_csum_offload;
37 u8 nqsets;
38 u8 first_qset;
39 struct cphy phy;
40 struct cmac mac;
41 struct link_config link_config;
42 struct net_device_stats netstats;
43 int activity;
44};
45
46enum { /* adapter flags */
47 FULL_INIT_DONE = (1 << 0),
48 USING_MSI = (1 << 1),
49 USING_MSIX = (1 << 2),
Divy Le Ray14ab9892007-01-30 19:43:50 -080050 QUEUES_BOUND = (1 << 3),
Divy Le Ray4d22de32007-01-18 22:04:14 -050051};
52
53struct rx_desc;
54struct rx_sw_desc;
55
56struct sge_fl { /* SGE per free-buffer list state */
57 unsigned int buf_size; /* size of each Rx buffer */
58 unsigned int credits; /* # of available Rx buffers */
59 unsigned int size; /* capacity of free list */
60 unsigned int cidx; /* consumer index */
61 unsigned int pidx; /* producer index */
62 unsigned int gen; /* free list generation */
63 struct rx_desc *desc; /* address of HW Rx descriptor ring */
64 struct rx_sw_desc *sdesc; /* address of SW Rx descriptor ring */
65 dma_addr_t phys_addr; /* physical address of HW ring start */
66 unsigned int cntxt_id; /* SGE context id for the free list */
67 unsigned long empty; /* # of times queue ran out of buffers */
68};
69
70/*
71 * Bundle size for grouping offload RX packets for delivery to the stack.
72 * Don't make this too big as we do prefetch on each packet in a bundle.
73 */
74# define RX_BUNDLE_SIZE 8
75
76struct rsp_desc;
77
78struct sge_rspq { /* state for an SGE response queue */
79 unsigned int credits; /* # of pending response credits */
80 unsigned int size; /* capacity of response queue */
81 unsigned int cidx; /* consumer index */
82 unsigned int gen; /* current generation bit */
83 unsigned int polling; /* is the queue serviced through NAPI? */
84 unsigned int holdoff_tmr; /* interrupt holdoff timer in 100ns */
85 unsigned int next_holdoff; /* holdoff time for next interrupt */
86 struct rsp_desc *desc; /* address of HW response ring */
87 dma_addr_t phys_addr; /* physical address of the ring */
88 unsigned int cntxt_id; /* SGE context id for the response q */
89 spinlock_t lock; /* guards response processing */
90 struct sk_buff *rx_head; /* offload packet receive queue head */
91 struct sk_buff *rx_tail; /* offload packet receive queue tail */
92
93 unsigned long offload_pkts;
94 unsigned long offload_bundles;
95 unsigned long eth_pkts; /* # of ethernet packets */
96 unsigned long pure_rsps; /* # of pure (non-data) responses */
97 unsigned long imm_data; /* responses with immediate data */
98 unsigned long rx_drops; /* # of packets dropped due to no mem */
99 unsigned long async_notif; /* # of asynchronous notification events */
100 unsigned long empty; /* # of times queue ran out of credits */
101 unsigned long nomem; /* # of responses deferred due to no mem */
102 unsigned long unhandled_irqs; /* # of spurious intrs */
103};
104
105struct tx_desc;
106struct tx_sw_desc;
107
108struct sge_txq { /* state for an SGE Tx queue */
109 unsigned long flags; /* HW DMA fetch status */
110 unsigned int in_use; /* # of in-use Tx descriptors */
111 unsigned int size; /* # of descriptors */
112 unsigned int processed; /* total # of descs HW has processed */
113 unsigned int cleaned; /* total # of descs SW has reclaimed */
114 unsigned int stop_thres; /* SW TX queue suspend threshold */
115 unsigned int cidx; /* consumer index */
116 unsigned int pidx; /* producer index */
117 unsigned int gen; /* current value of generation bit */
118 unsigned int unacked; /* Tx descriptors used since last COMPL */
119 struct tx_desc *desc; /* address of HW Tx descriptor ring */
120 struct tx_sw_desc *sdesc; /* address of SW Tx descriptor ring */
121 spinlock_t lock; /* guards enqueueing of new packets */
122 unsigned int token; /* WR token */
123 dma_addr_t phys_addr; /* physical address of the ring */
124 struct sk_buff_head sendq; /* List of backpressured offload packets */
125 struct tasklet_struct qresume_tsk; /* restarts the queue */
126 unsigned int cntxt_id; /* SGE context id for the Tx q */
127 unsigned long stops; /* # of times q has been stopped */
128 unsigned long restarts; /* # of queue restarts */
129};
130
131enum { /* per port SGE statistics */
132 SGE_PSTAT_TSO, /* # of TSO requests */
133 SGE_PSTAT_RX_CSUM_GOOD, /* # of successful RX csum offloads */
134 SGE_PSTAT_TX_CSUM, /* # of TX checksum offloads */
135 SGE_PSTAT_VLANEX, /* # of VLAN tag extractions */
136 SGE_PSTAT_VLANINS, /* # of VLAN tag insertions */
137
138 SGE_PSTAT_MAX /* must be last */
139};
140
141struct sge_qset { /* an SGE queue set */
142 struct sge_rspq rspq;
143 struct sge_fl fl[SGE_RXQ_PER_SET];
144 struct sge_txq txq[SGE_TXQ_PER_SET];
145 struct net_device *netdev; /* associated net device */
146 unsigned long txq_stopped; /* which Tx queues are stopped */
147 struct timer_list tx_reclaim_timer; /* reclaims TX buffers */
148 unsigned long port_stats[SGE_PSTAT_MAX];
149} ____cacheline_aligned;
150
151struct sge {
152 struct sge_qset qs[SGE_QSETS];
153 spinlock_t reg_lock; /* guards non-atomic SGE registers (eg context) */
154};
155
156struct adapter {
157 struct t3cdev tdev;
158 struct list_head adapter_list;
159 void __iomem *regs;
160 struct pci_dev *pdev;
161 unsigned long registered_device_map;
162 unsigned long open_device_map;
163 unsigned long flags;
164
165 const char *name;
166 int msg_enable;
167 unsigned int mmio_len;
168
169 struct adapter_params params;
170 unsigned int slow_intr_mask;
171 unsigned long irq_stats[IRQ_NUM_STATS];
172
173 struct {
174 unsigned short vec;
175 char desc[22];
176 } msix_info[SGE_QSETS + 1];
177
178 /* T3 modules */
179 struct sge sge;
180 struct mc7 pmrx;
181 struct mc7 pmtx;
182 struct mc7 cm;
183 struct mc5 mc5;
184
185 struct net_device *port[MAX_NPORTS];
186 unsigned int check_task_cnt;
187 struct delayed_work adap_check_task;
188 struct work_struct ext_intr_handler_task;
189
190 /*
191 * Dummy netdevices are needed when using multiple receive queues with
192 * NAPI as each netdevice can service only one queue.
193 */
194 struct net_device *dummy_netdev[SGE_QSETS - 1];
195
196 struct dentry *debugfs_root;
197
198 struct mutex mdio_lock;
199 spinlock_t stats_lock;
200 spinlock_t work_lock;
201};
202
203static inline u32 t3_read_reg(struct adapter *adapter, u32 reg_addr)
204{
205 u32 val = readl(adapter->regs + reg_addr);
206
207 CH_DBG(adapter, MMIO, "read register 0x%x value 0x%x\n", reg_addr, val);
208 return val;
209}
210
211static inline void t3_write_reg(struct adapter *adapter, u32 reg_addr, u32 val)
212{
213 CH_DBG(adapter, MMIO, "setting register 0x%x to 0x%x\n", reg_addr, val);
214 writel(val, adapter->regs + reg_addr);
215}
216
217static inline struct port_info *adap2pinfo(struct adapter *adap, int idx)
218{
219 return netdev_priv(adap->port[idx]);
220}
221
222/*
223 * We use the spare atalk_ptr to map a net device to its SGE queue set.
224 * This is a macro so it can be used as l-value.
225 */
226#define dev2qset(netdev) ((netdev)->atalk_ptr)
227
228#define OFFLOAD_DEVMAP_BIT 15
229
230#define tdev2adap(d) container_of(d, struct adapter, tdev)
231
232static inline int offload_running(struct adapter *adapter)
233{
234 return test_bit(OFFLOAD_DEVMAP_BIT, &adapter->open_device_map);
235}
236
237int t3_offload_tx(struct t3cdev *tdev, struct sk_buff *skb);
238
239void t3_os_ext_intr_handler(struct adapter *adapter);
240void t3_os_link_changed(struct adapter *adapter, int port_id, int link_status,
241 int speed, int duplex, int fc);
242
243void t3_sge_start(struct adapter *adap);
244void t3_sge_stop(struct adapter *adap);
245void t3_free_sge_resources(struct adapter *adap);
246void t3_sge_err_intr_handler(struct adapter *adapter);
247intr_handler_t t3_intr_handler(struct adapter *adap, int polling);
248int t3_eth_xmit(struct sk_buff *skb, struct net_device *dev);
Divy Le Ray14ab9892007-01-30 19:43:50 -0800249int t3_mgmt_tx(struct adapter *adap, struct sk_buff *skb);
Divy Le Ray4d22de32007-01-18 22:04:14 -0500250void t3_update_qset_coalesce(struct sge_qset *qs, const struct qset_params *p);
251int t3_sge_alloc_qset(struct adapter *adapter, unsigned int id, int nports,
252 int irq_vec_idx, const struct qset_params *p,
253 int ntxq, struct net_device *netdev);
254int t3_get_desc(const struct sge_qset *qs, unsigned int qnum, unsigned int idx,
255 unsigned char *data);
256irqreturn_t t3_sge_intr_msix(int irq, void *cookie);
257
258#endif /* __T3_ADAPTER_H__ */