Shawn Guo | 9daaf31 | 2011-10-17 08:42:17 +0800 | [diff] [blame] | 1 | /* |
| 2 | * Copyright 2011 Freescale Semiconductor, Inc. |
| 3 | * Copyright 2011 Linaro Ltd. |
| 4 | * |
| 5 | * The code contained herein is licensed under the GNU General Public |
| 6 | * License. You may obtain a copy of the GNU General Public License |
| 7 | * Version 2 or later at the following locations: |
| 8 | * |
| 9 | * http://www.opensource.org/licenses/gpl-license.html |
| 10 | * http://www.gnu.org/copyleft/gpl.html |
| 11 | */ |
| 12 | |
Shawn Guo | 36dffd8 | 2013-04-07 10:49:34 +0800 | [diff] [blame] | 13 | #include "skeleton.dtsi" |
Shawn Guo | e164153 | 2013-02-20 10:32:52 +0800 | [diff] [blame] | 14 | #include "imx51-pinfunc.h" |
Shawn Guo | 9daaf31 | 2011-10-17 08:42:17 +0800 | [diff] [blame] | 15 | |
| 16 | / { |
| 17 | aliases { |
Shawn Guo | 5230f8f | 2012-08-05 14:01:28 +0800 | [diff] [blame] | 18 | gpio0 = &gpio1; |
| 19 | gpio1 = &gpio2; |
| 20 | gpio2 = &gpio3; |
| 21 | gpio3 = &gpio4; |
Sascha Hauer | e3b73c6 | 2013-06-25 15:51:55 +0200 | [diff] [blame] | 22 | i2c0 = &i2c1; |
| 23 | i2c1 = &i2c2; |
| 24 | serial0 = &uart1; |
| 25 | serial1 = &uart2; |
| 26 | serial2 = &uart3; |
| 27 | spi0 = &ecspi1; |
| 28 | spi1 = &ecspi2; |
| 29 | spi2 = &cspi; |
Shawn Guo | 9daaf31 | 2011-10-17 08:42:17 +0800 | [diff] [blame] | 30 | }; |
| 31 | |
| 32 | tzic: tz-interrupt-controller@e0000000 { |
| 33 | compatible = "fsl,imx51-tzic", "fsl,tzic"; |
| 34 | interrupt-controller; |
| 35 | #interrupt-cells = <1>; |
| 36 | reg = <0xe0000000 0x4000>; |
| 37 | }; |
| 38 | |
| 39 | clocks { |
| 40 | #address-cells = <1>; |
| 41 | #size-cells = <0>; |
| 42 | |
| 43 | ckil { |
| 44 | compatible = "fsl,imx-ckil", "fixed-clock"; |
| 45 | clock-frequency = <32768>; |
| 46 | }; |
| 47 | |
| 48 | ckih1 { |
| 49 | compatible = "fsl,imx-ckih1", "fixed-clock"; |
Alexander Shiyan | 677e28b | 2013-07-27 11:19:45 +0400 | [diff] [blame] | 50 | clock-frequency = <0>; |
Shawn Guo | 9daaf31 | 2011-10-17 08:42:17 +0800 | [diff] [blame] | 51 | }; |
| 52 | |
| 53 | ckih2 { |
| 54 | compatible = "fsl,imx-ckih2", "fixed-clock"; |
| 55 | clock-frequency = <0>; |
| 56 | }; |
| 57 | |
| 58 | osc { |
| 59 | compatible = "fsl,imx-osc", "fixed-clock"; |
| 60 | clock-frequency = <24000000>; |
| 61 | }; |
| 62 | }; |
| 63 | |
Markus Pargmann | 6f9d62d | 2013-04-07 21:56:45 +0200 | [diff] [blame] | 64 | cpus { |
| 65 | #address-cells = <1>; |
| 66 | #size-cells = <0>; |
| 67 | cpu@0 { |
| 68 | device_type = "cpu"; |
| 69 | compatible = "arm,cortex-a8"; |
| 70 | reg = <0>; |
| 71 | clock-latency = <61036>; /* two CLK32 periods */ |
| 72 | clocks = <&clks 24>; |
| 73 | clock-names = "cpu"; |
| 74 | operating-points = < |
| 75 | /* kHz uV (No regulator support) */ |
| 76 | 160000 0 |
| 77 | 800000 0 |
| 78 | >; |
| 79 | }; |
| 80 | }; |
| 81 | |
Shawn Guo | 9daaf31 | 2011-10-17 08:42:17 +0800 | [diff] [blame] | 82 | soc { |
| 83 | #address-cells = <1>; |
| 84 | #size-cells = <1>; |
| 85 | compatible = "simple-bus"; |
| 86 | interrupt-parent = <&tzic>; |
| 87 | ranges; |
| 88 | |
Alexander Shiyan | da38ea3 | 2013-08-21 11:28:24 +0400 | [diff] [blame] | 89 | iram: iram@1ffe0000 { |
| 90 | compatible = "mmio-sram"; |
| 91 | reg = <0x1ffe0000 0x20000>; |
| 92 | }; |
| 93 | |
Sascha Hauer | b5af6b1 | 2012-11-12 12:56:00 +0100 | [diff] [blame] | 94 | ipu: ipu@40000000 { |
| 95 | #crtc-cells = <1>; |
| 96 | compatible = "fsl,imx51-ipu"; |
| 97 | reg = <0x40000000 0x20000000>; |
| 98 | interrupts = <11 10>; |
Philipp Zabel | 4438a6a | 2013-03-27 18:30:36 +0100 | [diff] [blame] | 99 | clocks = <&clks 59>, <&clks 110>, <&clks 61>; |
| 100 | clock-names = "bus", "di0", "di1"; |
Philipp Zabel | 8d84c37 | 2013-03-28 17:35:23 +0100 | [diff] [blame] | 101 | resets = <&src 2>; |
Sascha Hauer | b5af6b1 | 2012-11-12 12:56:00 +0100 | [diff] [blame] | 102 | }; |
| 103 | |
Shawn Guo | 9daaf31 | 2011-10-17 08:42:17 +0800 | [diff] [blame] | 104 | aips@70000000 { /* AIPS1 */ |
| 105 | compatible = "fsl,aips-bus", "simple-bus"; |
| 106 | #address-cells = <1>; |
| 107 | #size-cells = <1>; |
| 108 | reg = <0x70000000 0x10000000>; |
| 109 | ranges; |
| 110 | |
| 111 | spba@70000000 { |
| 112 | compatible = "fsl,spba-bus", "simple-bus"; |
| 113 | #address-cells = <1>; |
| 114 | #size-cells = <1>; |
| 115 | reg = <0x70000000 0x40000>; |
| 116 | ranges; |
| 117 | |
Sascha Hauer | 7b7d672 | 2012-11-15 09:31:52 +0100 | [diff] [blame] | 118 | esdhc1: esdhc@70004000 { |
Shawn Guo | 9daaf31 | 2011-10-17 08:42:17 +0800 | [diff] [blame] | 119 | compatible = "fsl,imx51-esdhc"; |
| 120 | reg = <0x70004000 0x4000>; |
| 121 | interrupts = <1>; |
Fabio Estevam | f40f38d | 2012-11-21 13:43:05 -0200 | [diff] [blame] | 122 | clocks = <&clks 44>, <&clks 0>, <&clks 71>; |
| 123 | clock-names = "ipg", "ahb", "per"; |
Shawn Guo | 9daaf31 | 2011-10-17 08:42:17 +0800 | [diff] [blame] | 124 | status = "disabled"; |
| 125 | }; |
| 126 | |
Sascha Hauer | 7b7d672 | 2012-11-15 09:31:52 +0100 | [diff] [blame] | 127 | esdhc2: esdhc@70008000 { |
Shawn Guo | 9daaf31 | 2011-10-17 08:42:17 +0800 | [diff] [blame] | 128 | compatible = "fsl,imx51-esdhc"; |
| 129 | reg = <0x70008000 0x4000>; |
| 130 | interrupts = <2>; |
Fabio Estevam | f40f38d | 2012-11-21 13:43:05 -0200 | [diff] [blame] | 131 | clocks = <&clks 45>, <&clks 0>, <&clks 72>; |
| 132 | clock-names = "ipg", "ahb", "per"; |
Sascha Hauer | c104b6a | 2012-09-25 11:49:33 +0200 | [diff] [blame] | 133 | bus-width = <4>; |
Shawn Guo | 9daaf31 | 2011-10-17 08:42:17 +0800 | [diff] [blame] | 134 | status = "disabled"; |
| 135 | }; |
| 136 | |
Shawn Guo | 0c456cf | 2012-04-02 14:39:26 +0800 | [diff] [blame] | 137 | uart3: serial@7000c000 { |
Shawn Guo | 9daaf31 | 2011-10-17 08:42:17 +0800 | [diff] [blame] | 138 | compatible = "fsl,imx51-uart", "fsl,imx21-uart"; |
| 139 | reg = <0x7000c000 0x4000>; |
| 140 | interrupts = <33>; |
Fabio Estevam | f40f38d | 2012-11-21 13:43:05 -0200 | [diff] [blame] | 141 | clocks = <&clks 32>, <&clks 33>; |
| 142 | clock-names = "ipg", "per"; |
Shawn Guo | 9daaf31 | 2011-10-17 08:42:17 +0800 | [diff] [blame] | 143 | status = "disabled"; |
| 144 | }; |
| 145 | |
Sascha Hauer | 7b7d672 | 2012-11-15 09:31:52 +0100 | [diff] [blame] | 146 | ecspi1: ecspi@70010000 { |
Shawn Guo | 9daaf31 | 2011-10-17 08:42:17 +0800 | [diff] [blame] | 147 | #address-cells = <1>; |
| 148 | #size-cells = <0>; |
| 149 | compatible = "fsl,imx51-ecspi"; |
| 150 | reg = <0x70010000 0x4000>; |
| 151 | interrupts = <36>; |
Fabio Estevam | f40f38d | 2012-11-21 13:43:05 -0200 | [diff] [blame] | 152 | clocks = <&clks 51>, <&clks 52>; |
| 153 | clock-names = "ipg", "per"; |
Shawn Guo | 9daaf31 | 2011-10-17 08:42:17 +0800 | [diff] [blame] | 154 | status = "disabled"; |
| 155 | }; |
| 156 | |
Shawn Guo | a15d9f8 | 2012-05-11 13:08:46 +0800 | [diff] [blame] | 157 | ssi2: ssi@70014000 { |
| 158 | compatible = "fsl,imx51-ssi", "fsl,imx21-ssi"; |
| 159 | reg = <0x70014000 0x4000>; |
| 160 | interrupts = <30>; |
Fabio Estevam | f40f38d | 2012-11-21 13:43:05 -0200 | [diff] [blame] | 161 | clocks = <&clks 49>; |
Shawn Guo | 5da826a | 2013-07-17 13:50:54 +0800 | [diff] [blame] | 162 | dmas = <&sdma 24 1 0>, |
| 163 | <&sdma 25 1 0>; |
| 164 | dma-names = "rx", "tx"; |
Shawn Guo | a15d9f8 | 2012-05-11 13:08:46 +0800 | [diff] [blame] | 165 | fsl,fifo-depth = <15>; |
| 166 | fsl,ssi-dma-events = <25 24 23 22>; /* TX0 RX0 TX1 RX1 */ |
| 167 | status = "disabled"; |
| 168 | }; |
| 169 | |
Sascha Hauer | 7b7d672 | 2012-11-15 09:31:52 +0100 | [diff] [blame] | 170 | esdhc3: esdhc@70020000 { |
Shawn Guo | 9daaf31 | 2011-10-17 08:42:17 +0800 | [diff] [blame] | 171 | compatible = "fsl,imx51-esdhc"; |
| 172 | reg = <0x70020000 0x4000>; |
| 173 | interrupts = <3>; |
Fabio Estevam | f40f38d | 2012-11-21 13:43:05 -0200 | [diff] [blame] | 174 | clocks = <&clks 46>, <&clks 0>, <&clks 73>; |
| 175 | clock-names = "ipg", "ahb", "per"; |
Sascha Hauer | c104b6a | 2012-09-25 11:49:33 +0200 | [diff] [blame] | 176 | bus-width = <4>; |
Shawn Guo | 9daaf31 | 2011-10-17 08:42:17 +0800 | [diff] [blame] | 177 | status = "disabled"; |
| 178 | }; |
| 179 | |
Sascha Hauer | 7b7d672 | 2012-11-15 09:31:52 +0100 | [diff] [blame] | 180 | esdhc4: esdhc@70024000 { |
Shawn Guo | 9daaf31 | 2011-10-17 08:42:17 +0800 | [diff] [blame] | 181 | compatible = "fsl,imx51-esdhc"; |
| 182 | reg = <0x70024000 0x4000>; |
| 183 | interrupts = <4>; |
Fabio Estevam | f40f38d | 2012-11-21 13:43:05 -0200 | [diff] [blame] | 184 | clocks = <&clks 47>, <&clks 0>, <&clks 74>; |
| 185 | clock-names = "ipg", "ahb", "per"; |
Sascha Hauer | c104b6a | 2012-09-25 11:49:33 +0200 | [diff] [blame] | 186 | bus-width = <4>; |
Shawn Guo | 9daaf31 | 2011-10-17 08:42:17 +0800 | [diff] [blame] | 187 | status = "disabled"; |
| 188 | }; |
| 189 | }; |
| 190 | |
Michael Grzeschik | a79025c | 2013-04-11 12:13:16 +0200 | [diff] [blame] | 191 | usbphy0: usbphy@0 { |
| 192 | compatible = "usb-nop-xceiv"; |
Alexander Shiyan | 036e299 | 2013-11-05 18:00:18 +0400 | [diff] [blame] | 193 | clocks = <&clks 75>; |
Michael Grzeschik | a79025c | 2013-04-11 12:13:16 +0200 | [diff] [blame] | 194 | clock-names = "main_clk"; |
| 195 | status = "okay"; |
| 196 | }; |
| 197 | |
Sascha Hauer | 7b7d672 | 2012-11-15 09:31:52 +0100 | [diff] [blame] | 198 | usbotg: usb@73f80000 { |
Michael Grzeschik | 212d0b8 | 2012-08-23 12:35:57 +0200 | [diff] [blame] | 199 | compatible = "fsl,imx51-usb", "fsl,imx27-usb"; |
| 200 | reg = <0x73f80000 0x0200>; |
| 201 | interrupts = <18>; |
Michael Grzeschik | 8e38890 | 2013-04-11 12:13:15 +0200 | [diff] [blame] | 202 | clocks = <&clks 108>; |
Michael Grzeschik | a573502 | 2013-04-11 12:13:14 +0200 | [diff] [blame] | 203 | fsl,usbmisc = <&usbmisc 0>; |
Michael Grzeschik | a79025c | 2013-04-11 12:13:16 +0200 | [diff] [blame] | 204 | fsl,usbphy = <&usbphy0>; |
Michael Grzeschik | 212d0b8 | 2012-08-23 12:35:57 +0200 | [diff] [blame] | 205 | status = "disabled"; |
| 206 | }; |
| 207 | |
Sascha Hauer | 7b7d672 | 2012-11-15 09:31:52 +0100 | [diff] [blame] | 208 | usbh1: usb@73f80200 { |
Michael Grzeschik | 212d0b8 | 2012-08-23 12:35:57 +0200 | [diff] [blame] | 209 | compatible = "fsl,imx51-usb", "fsl,imx27-usb"; |
| 210 | reg = <0x73f80200 0x0200>; |
| 211 | interrupts = <14>; |
Michael Grzeschik | 8e38890 | 2013-04-11 12:13:15 +0200 | [diff] [blame] | 212 | clocks = <&clks 108>; |
Michael Grzeschik | a573502 | 2013-04-11 12:13:14 +0200 | [diff] [blame] | 213 | fsl,usbmisc = <&usbmisc 1>; |
Michael Grzeschik | 212d0b8 | 2012-08-23 12:35:57 +0200 | [diff] [blame] | 214 | status = "disabled"; |
| 215 | }; |
| 216 | |
Sascha Hauer | 7b7d672 | 2012-11-15 09:31:52 +0100 | [diff] [blame] | 217 | usbh2: usb@73f80400 { |
Michael Grzeschik | 212d0b8 | 2012-08-23 12:35:57 +0200 | [diff] [blame] | 218 | compatible = "fsl,imx51-usb", "fsl,imx27-usb"; |
| 219 | reg = <0x73f80400 0x0200>; |
| 220 | interrupts = <16>; |
Michael Grzeschik | 8e38890 | 2013-04-11 12:13:15 +0200 | [diff] [blame] | 221 | clocks = <&clks 108>; |
Michael Grzeschik | a573502 | 2013-04-11 12:13:14 +0200 | [diff] [blame] | 222 | fsl,usbmisc = <&usbmisc 2>; |
Michael Grzeschik | 212d0b8 | 2012-08-23 12:35:57 +0200 | [diff] [blame] | 223 | status = "disabled"; |
| 224 | }; |
| 225 | |
Sascha Hauer | 7b7d672 | 2012-11-15 09:31:52 +0100 | [diff] [blame] | 226 | usbh3: usb@73f80600 { |
Michael Grzeschik | 212d0b8 | 2012-08-23 12:35:57 +0200 | [diff] [blame] | 227 | compatible = "fsl,imx51-usb", "fsl,imx27-usb"; |
| 228 | reg = <0x73f80600 0x0200>; |
| 229 | interrupts = <17>; |
Michael Grzeschik | 8e38890 | 2013-04-11 12:13:15 +0200 | [diff] [blame] | 230 | clocks = <&clks 108>; |
Michael Grzeschik | a573502 | 2013-04-11 12:13:14 +0200 | [diff] [blame] | 231 | fsl,usbmisc = <&usbmisc 3>; |
Michael Grzeschik | 212d0b8 | 2012-08-23 12:35:57 +0200 | [diff] [blame] | 232 | status = "disabled"; |
| 233 | }; |
| 234 | |
Michael Grzeschik | a573502 | 2013-04-11 12:13:14 +0200 | [diff] [blame] | 235 | usbmisc: usbmisc@73f80800 { |
| 236 | #index-cells = <1>; |
| 237 | compatible = "fsl,imx51-usbmisc"; |
| 238 | reg = <0x73f80800 0x200>; |
Michael Grzeschik | 8e38890 | 2013-04-11 12:13:15 +0200 | [diff] [blame] | 239 | clocks = <&clks 108>; |
Michael Grzeschik | a573502 | 2013-04-11 12:13:14 +0200 | [diff] [blame] | 240 | }; |
| 241 | |
Richard Zhao | 4d19186 | 2011-12-14 09:26:44 +0800 | [diff] [blame] | 242 | gpio1: gpio@73f84000 { |
Benoît Thébaudeau | aeb2774 | 2012-06-22 21:04:06 +0200 | [diff] [blame] | 243 | compatible = "fsl,imx51-gpio", "fsl,imx35-gpio"; |
Shawn Guo | 9daaf31 | 2011-10-17 08:42:17 +0800 | [diff] [blame] | 244 | reg = <0x73f84000 0x4000>; |
| 245 | interrupts = <50 51>; |
| 246 | gpio-controller; |
| 247 | #gpio-cells = <2>; |
| 248 | interrupt-controller; |
Shawn Guo | 88cde8b | 2012-07-06 20:03:37 +0800 | [diff] [blame] | 249 | #interrupt-cells = <2>; |
Shawn Guo | 9daaf31 | 2011-10-17 08:42:17 +0800 | [diff] [blame] | 250 | }; |
| 251 | |
Richard Zhao | 4d19186 | 2011-12-14 09:26:44 +0800 | [diff] [blame] | 252 | gpio2: gpio@73f88000 { |
Benoît Thébaudeau | aeb2774 | 2012-06-22 21:04:06 +0200 | [diff] [blame] | 253 | compatible = "fsl,imx51-gpio", "fsl,imx35-gpio"; |
Shawn Guo | 9daaf31 | 2011-10-17 08:42:17 +0800 | [diff] [blame] | 254 | reg = <0x73f88000 0x4000>; |
| 255 | interrupts = <52 53>; |
| 256 | gpio-controller; |
| 257 | #gpio-cells = <2>; |
| 258 | interrupt-controller; |
Shawn Guo | 88cde8b | 2012-07-06 20:03:37 +0800 | [diff] [blame] | 259 | #interrupt-cells = <2>; |
Shawn Guo | 9daaf31 | 2011-10-17 08:42:17 +0800 | [diff] [blame] | 260 | }; |
| 261 | |
Richard Zhao | 4d19186 | 2011-12-14 09:26:44 +0800 | [diff] [blame] | 262 | gpio3: gpio@73f8c000 { |
Benoît Thébaudeau | aeb2774 | 2012-06-22 21:04:06 +0200 | [diff] [blame] | 263 | compatible = "fsl,imx51-gpio", "fsl,imx35-gpio"; |
Shawn Guo | 9daaf31 | 2011-10-17 08:42:17 +0800 | [diff] [blame] | 264 | reg = <0x73f8c000 0x4000>; |
| 265 | interrupts = <54 55>; |
| 266 | gpio-controller; |
| 267 | #gpio-cells = <2>; |
| 268 | interrupt-controller; |
Shawn Guo | 88cde8b | 2012-07-06 20:03:37 +0800 | [diff] [blame] | 269 | #interrupt-cells = <2>; |
Shawn Guo | 9daaf31 | 2011-10-17 08:42:17 +0800 | [diff] [blame] | 270 | }; |
| 271 | |
Richard Zhao | 4d19186 | 2011-12-14 09:26:44 +0800 | [diff] [blame] | 272 | gpio4: gpio@73f90000 { |
Benoît Thébaudeau | aeb2774 | 2012-06-22 21:04:06 +0200 | [diff] [blame] | 273 | compatible = "fsl,imx51-gpio", "fsl,imx35-gpio"; |
Shawn Guo | 9daaf31 | 2011-10-17 08:42:17 +0800 | [diff] [blame] | 274 | reg = <0x73f90000 0x4000>; |
| 275 | interrupts = <56 57>; |
| 276 | gpio-controller; |
| 277 | #gpio-cells = <2>; |
| 278 | interrupt-controller; |
Shawn Guo | 88cde8b | 2012-07-06 20:03:37 +0800 | [diff] [blame] | 279 | #interrupt-cells = <2>; |
Shawn Guo | 9daaf31 | 2011-10-17 08:42:17 +0800 | [diff] [blame] | 280 | }; |
| 281 | |
Liu Ying | 6012555 | 2013-01-03 20:37:33 +0800 | [diff] [blame] | 282 | kpp: kpp@73f94000 { |
| 283 | compatible = "fsl,imx51-kpp", "fsl,imx21-kpp"; |
| 284 | reg = <0x73f94000 0x4000>; |
| 285 | interrupts = <60>; |
| 286 | clocks = <&clks 0>; |
| 287 | status = "disabled"; |
| 288 | }; |
| 289 | |
Sascha Hauer | 7b7d672 | 2012-11-15 09:31:52 +0100 | [diff] [blame] | 290 | wdog1: wdog@73f98000 { |
Shawn Guo | 9daaf31 | 2011-10-17 08:42:17 +0800 | [diff] [blame] | 291 | compatible = "fsl,imx51-wdt", "fsl,imx21-wdt"; |
| 292 | reg = <0x73f98000 0x4000>; |
| 293 | interrupts = <58>; |
Fabio Estevam | f40f38d | 2012-11-21 13:43:05 -0200 | [diff] [blame] | 294 | clocks = <&clks 0>; |
Shawn Guo | 9daaf31 | 2011-10-17 08:42:17 +0800 | [diff] [blame] | 295 | }; |
| 296 | |
Sascha Hauer | 7b7d672 | 2012-11-15 09:31:52 +0100 | [diff] [blame] | 297 | wdog2: wdog@73f9c000 { |
Shawn Guo | 9daaf31 | 2011-10-17 08:42:17 +0800 | [diff] [blame] | 298 | compatible = "fsl,imx51-wdt", "fsl,imx21-wdt"; |
| 299 | reg = <0x73f9c000 0x4000>; |
| 300 | interrupts = <59>; |
Fabio Estevam | f40f38d | 2012-11-21 13:43:05 -0200 | [diff] [blame] | 301 | clocks = <&clks 0>; |
Shawn Guo | 9daaf31 | 2011-10-17 08:42:17 +0800 | [diff] [blame] | 302 | status = "disabled"; |
| 303 | }; |
| 304 | |
Sascha Hauer | ed73c63 | 2013-03-14 13:08:59 +0100 | [diff] [blame] | 305 | gpt: timer@73fa0000 { |
| 306 | compatible = "fsl,imx51-gpt", "fsl,imx31-gpt"; |
| 307 | reg = <0x73fa0000 0x4000>; |
| 308 | interrupts = <39>; |
| 309 | clocks = <&clks 36>, <&clks 41>; |
| 310 | clock-names = "ipg", "per"; |
| 311 | }; |
| 312 | |
Sascha Hauer | 7b7d672 | 2012-11-15 09:31:52 +0100 | [diff] [blame] | 313 | iomuxc: iomuxc@73fa8000 { |
Shawn Guo | b72cf10 | 2012-08-13 19:45:19 +0800 | [diff] [blame] | 314 | compatible = "fsl,imx51-iomuxc"; |
| 315 | reg = <0x73fa8000 0x4000>; |
Shawn Guo | b72cf10 | 2012-08-13 19:45:19 +0800 | [diff] [blame] | 316 | }; |
| 317 | |
Sascha Hauer | 82a618d | 2012-11-19 00:57:08 +0100 | [diff] [blame] | 318 | pwm1: pwm@73fb4000 { |
| 319 | #pwm-cells = <2>; |
| 320 | compatible = "fsl,imx51-pwm", "fsl,imx27-pwm"; |
| 321 | reg = <0x73fb4000 0x4000>; |
| 322 | clocks = <&clks 37>, <&clks 38>; |
| 323 | clock-names = "ipg", "per"; |
| 324 | interrupts = <61>; |
| 325 | }; |
| 326 | |
| 327 | pwm2: pwm@73fb8000 { |
| 328 | #pwm-cells = <2>; |
| 329 | compatible = "fsl,imx51-pwm", "fsl,imx27-pwm"; |
| 330 | reg = <0x73fb8000 0x4000>; |
| 331 | clocks = <&clks 39>, <&clks 40>; |
| 332 | clock-names = "ipg", "per"; |
| 333 | interrupts = <94>; |
| 334 | }; |
| 335 | |
Shawn Guo | 0c456cf | 2012-04-02 14:39:26 +0800 | [diff] [blame] | 336 | uart1: serial@73fbc000 { |
Shawn Guo | 9daaf31 | 2011-10-17 08:42:17 +0800 | [diff] [blame] | 337 | compatible = "fsl,imx51-uart", "fsl,imx21-uart"; |
| 338 | reg = <0x73fbc000 0x4000>; |
| 339 | interrupts = <31>; |
Fabio Estevam | f40f38d | 2012-11-21 13:43:05 -0200 | [diff] [blame] | 340 | clocks = <&clks 28>, <&clks 29>; |
| 341 | clock-names = "ipg", "per"; |
Shawn Guo | 9daaf31 | 2011-10-17 08:42:17 +0800 | [diff] [blame] | 342 | status = "disabled"; |
| 343 | }; |
| 344 | |
Shawn Guo | 0c456cf | 2012-04-02 14:39:26 +0800 | [diff] [blame] | 345 | uart2: serial@73fc0000 { |
Shawn Guo | 9daaf31 | 2011-10-17 08:42:17 +0800 | [diff] [blame] | 346 | compatible = "fsl,imx51-uart", "fsl,imx21-uart"; |
| 347 | reg = <0x73fc0000 0x4000>; |
| 348 | interrupts = <32>; |
Fabio Estevam | f40f38d | 2012-11-21 13:43:05 -0200 | [diff] [blame] | 349 | clocks = <&clks 30>, <&clks 31>; |
| 350 | clock-names = "ipg", "per"; |
Shawn Guo | 9daaf31 | 2011-10-17 08:42:17 +0800 | [diff] [blame] | 351 | status = "disabled"; |
| 352 | }; |
Fabio Estevam | f40f38d | 2012-11-21 13:43:05 -0200 | [diff] [blame] | 353 | |
Philipp Zabel | 8d84c37 | 2013-03-28 17:35:23 +0100 | [diff] [blame] | 354 | src: src@73fd0000 { |
| 355 | compatible = "fsl,imx51-src"; |
| 356 | reg = <0x73fd0000 0x4000>; |
| 357 | #reset-cells = <1>; |
| 358 | }; |
| 359 | |
Fabio Estevam | f40f38d | 2012-11-21 13:43:05 -0200 | [diff] [blame] | 360 | clks: ccm@73fd4000{ |
| 361 | compatible = "fsl,imx51-ccm"; |
| 362 | reg = <0x73fd4000 0x4000>; |
| 363 | interrupts = <0 71 0x04 0 72 0x04>; |
| 364 | #clock-cells = <1>; |
| 365 | }; |
Shawn Guo | 9daaf31 | 2011-10-17 08:42:17 +0800 | [diff] [blame] | 366 | }; |
| 367 | |
| 368 | aips@80000000 { /* AIPS2 */ |
| 369 | compatible = "fsl,aips-bus", "simple-bus"; |
| 370 | #address-cells = <1>; |
| 371 | #size-cells = <1>; |
| 372 | reg = <0x80000000 0x10000000>; |
| 373 | ranges; |
| 374 | |
Sascha Hauer | 6510ea25 | 2013-06-25 15:51:51 +0200 | [diff] [blame] | 375 | iim: iim@83f98000 { |
| 376 | compatible = "fsl,imx51-iim", "fsl,imx27-iim"; |
| 377 | reg = <0x83f98000 0x4000>; |
| 378 | interrupts = <69>; |
| 379 | clocks = <&clks 107>; |
| 380 | }; |
| 381 | |
Alexander Shiyan | ad15f08 | 2013-08-21 11:28:25 +0400 | [diff] [blame] | 382 | owire: owire@83fa4000 { |
| 383 | compatible = "fsl,imx51-owire", "fsl,imx21-owire"; |
| 384 | reg = <0x83fa4000 0x4000>; |
| 385 | interrupts = <88>; |
| 386 | clocks = <&clks 159>; |
| 387 | status = "disabled"; |
| 388 | }; |
| 389 | |
Sascha Hauer | 7b7d672 | 2012-11-15 09:31:52 +0100 | [diff] [blame] | 390 | ecspi2: ecspi@83fac000 { |
Shawn Guo | 9daaf31 | 2011-10-17 08:42:17 +0800 | [diff] [blame] | 391 | #address-cells = <1>; |
| 392 | #size-cells = <0>; |
| 393 | compatible = "fsl,imx51-ecspi"; |
| 394 | reg = <0x83fac000 0x4000>; |
| 395 | interrupts = <37>; |
Fabio Estevam | f40f38d | 2012-11-21 13:43:05 -0200 | [diff] [blame] | 396 | clocks = <&clks 53>, <&clks 54>; |
| 397 | clock-names = "ipg", "per"; |
Shawn Guo | 9daaf31 | 2011-10-17 08:42:17 +0800 | [diff] [blame] | 398 | status = "disabled"; |
| 399 | }; |
| 400 | |
Sascha Hauer | 7b7d672 | 2012-11-15 09:31:52 +0100 | [diff] [blame] | 401 | sdma: sdma@83fb0000 { |
Shawn Guo | 9daaf31 | 2011-10-17 08:42:17 +0800 | [diff] [blame] | 402 | compatible = "fsl,imx51-sdma", "fsl,imx35-sdma"; |
| 403 | reg = <0x83fb0000 0x4000>; |
| 404 | interrupts = <6>; |
Fabio Estevam | f40f38d | 2012-11-21 13:43:05 -0200 | [diff] [blame] | 405 | clocks = <&clks 56>, <&clks 56>; |
| 406 | clock-names = "ipg", "ahb"; |
Huang Shijie | fb72bb2 | 2013-07-02 10:15:29 +0800 | [diff] [blame] | 407 | #dma-cells = <3>; |
Fabio Estevam | 7e4f036 | 2012-08-08 11:28:07 -0300 | [diff] [blame] | 408 | fsl,sdma-ram-script-name = "imx/sdma/sdma-imx51.bin"; |
Shawn Guo | 9daaf31 | 2011-10-17 08:42:17 +0800 | [diff] [blame] | 409 | }; |
| 410 | |
Sascha Hauer | 7b7d672 | 2012-11-15 09:31:52 +0100 | [diff] [blame] | 411 | cspi: cspi@83fc0000 { |
Shawn Guo | 9daaf31 | 2011-10-17 08:42:17 +0800 | [diff] [blame] | 412 | #address-cells = <1>; |
| 413 | #size-cells = <0>; |
| 414 | compatible = "fsl,imx51-cspi", "fsl,imx35-cspi"; |
| 415 | reg = <0x83fc0000 0x4000>; |
| 416 | interrupts = <38>; |
Jonas Andersson | 37523dc | 2013-05-23 13:38:05 +0200 | [diff] [blame] | 417 | clocks = <&clks 55>, <&clks 55>; |
Fabio Estevam | f40f38d | 2012-11-21 13:43:05 -0200 | [diff] [blame] | 418 | clock-names = "ipg", "per"; |
Shawn Guo | 9daaf31 | 2011-10-17 08:42:17 +0800 | [diff] [blame] | 419 | status = "disabled"; |
| 420 | }; |
| 421 | |
Sascha Hauer | 7b7d672 | 2012-11-15 09:31:52 +0100 | [diff] [blame] | 422 | i2c2: i2c@83fc4000 { |
Shawn Guo | 9daaf31 | 2011-10-17 08:42:17 +0800 | [diff] [blame] | 423 | #address-cells = <1>; |
| 424 | #size-cells = <0>; |
Shawn Guo | 5bdfba2 | 2012-09-14 15:19:00 +0800 | [diff] [blame] | 425 | compatible = "fsl,imx51-i2c", "fsl,imx21-i2c"; |
Shawn Guo | 9daaf31 | 2011-10-17 08:42:17 +0800 | [diff] [blame] | 426 | reg = <0x83fc4000 0x4000>; |
| 427 | interrupts = <63>; |
Fabio Estevam | f40f38d | 2012-11-21 13:43:05 -0200 | [diff] [blame] | 428 | clocks = <&clks 35>; |
Shawn Guo | 9daaf31 | 2011-10-17 08:42:17 +0800 | [diff] [blame] | 429 | status = "disabled"; |
| 430 | }; |
| 431 | |
Sascha Hauer | 7b7d672 | 2012-11-15 09:31:52 +0100 | [diff] [blame] | 432 | i2c1: i2c@83fc8000 { |
Shawn Guo | 9daaf31 | 2011-10-17 08:42:17 +0800 | [diff] [blame] | 433 | #address-cells = <1>; |
| 434 | #size-cells = <0>; |
Shawn Guo | 5bdfba2 | 2012-09-14 15:19:00 +0800 | [diff] [blame] | 435 | compatible = "fsl,imx51-i2c", "fsl,imx21-i2c"; |
Shawn Guo | 9daaf31 | 2011-10-17 08:42:17 +0800 | [diff] [blame] | 436 | reg = <0x83fc8000 0x4000>; |
| 437 | interrupts = <62>; |
Fabio Estevam | f40f38d | 2012-11-21 13:43:05 -0200 | [diff] [blame] | 438 | clocks = <&clks 34>; |
Shawn Guo | 9daaf31 | 2011-10-17 08:42:17 +0800 | [diff] [blame] | 439 | status = "disabled"; |
| 440 | }; |
| 441 | |
Shawn Guo | a15d9f8 | 2012-05-11 13:08:46 +0800 | [diff] [blame] | 442 | ssi1: ssi@83fcc000 { |
| 443 | compatible = "fsl,imx51-ssi", "fsl,imx21-ssi"; |
| 444 | reg = <0x83fcc000 0x4000>; |
| 445 | interrupts = <29>; |
Fabio Estevam | f40f38d | 2012-11-21 13:43:05 -0200 | [diff] [blame] | 446 | clocks = <&clks 48>; |
Shawn Guo | 5da826a | 2013-07-17 13:50:54 +0800 | [diff] [blame] | 447 | dmas = <&sdma 28 0 0>, |
| 448 | <&sdma 29 0 0>; |
| 449 | dma-names = "rx", "tx"; |
Shawn Guo | a15d9f8 | 2012-05-11 13:08:46 +0800 | [diff] [blame] | 450 | fsl,fifo-depth = <15>; |
| 451 | fsl,ssi-dma-events = <29 28 27 26>; /* TX0 RX0 TX1 RX1 */ |
| 452 | status = "disabled"; |
| 453 | }; |
| 454 | |
Sascha Hauer | 7b7d672 | 2012-11-15 09:31:52 +0100 | [diff] [blame] | 455 | audmux: audmux@83fd0000 { |
Shawn Guo | a15d9f8 | 2012-05-11 13:08:46 +0800 | [diff] [blame] | 456 | compatible = "fsl,imx51-audmux", "fsl,imx31-audmux"; |
| 457 | reg = <0x83fd0000 0x4000>; |
| 458 | status = "disabled"; |
| 459 | }; |
| 460 | |
Alexander Shiyan | edd0528 | 2013-07-13 08:30:57 +0400 | [diff] [blame] | 461 | weim: weim@83fda000 { |
| 462 | #address-cells = <2>; |
| 463 | #size-cells = <1>; |
| 464 | compatible = "fsl,imx51-weim"; |
| 465 | reg = <0x83fda000 0x1000>; |
| 466 | clocks = <&clks 57>; |
| 467 | ranges = < |
| 468 | 0 0 0xb0000000 0x08000000 |
| 469 | 1 0 0xb8000000 0x08000000 |
| 470 | 2 0 0xc0000000 0x08000000 |
| 471 | 3 0 0xc8000000 0x04000000 |
| 472 | 4 0 0xcc000000 0x02000000 |
| 473 | 5 0 0xce000000 0x02000000 |
| 474 | >; |
| 475 | status = "disabled"; |
| 476 | }; |
| 477 | |
Sascha Hauer | 7b7d672 | 2012-11-15 09:31:52 +0100 | [diff] [blame] | 478 | nfc: nand@83fdb000 { |
Sascha Hauer | 75453a0 | 2012-06-06 12:33:16 +0200 | [diff] [blame] | 479 | compatible = "fsl,imx51-nand"; |
| 480 | reg = <0x83fdb000 0x1000 0xcfff0000 0x10000>; |
| 481 | interrupts = <8>; |
Fabio Estevam | f40f38d | 2012-11-21 13:43:05 -0200 | [diff] [blame] | 482 | clocks = <&clks 60>; |
Sascha Hauer | 75453a0 | 2012-06-06 12:33:16 +0200 | [diff] [blame] | 483 | status = "disabled"; |
| 484 | }; |
| 485 | |
Sascha Hauer | 718a3500 | 2013-04-04 11:25:09 +0200 | [diff] [blame] | 486 | pata: pata@83fe0000 { |
| 487 | compatible = "fsl,imx51-pata", "fsl,imx27-pata"; |
| 488 | reg = <0x83fe0000 0x4000>; |
| 489 | interrupts = <70>; |
Arnaud Patard (Rtp) | 6a030ee | 2013-09-07 15:23:14 +0200 | [diff] [blame] | 490 | clocks = <&clks 172>; |
Sascha Hauer | 718a3500 | 2013-04-04 11:25:09 +0200 | [diff] [blame] | 491 | status = "disabled"; |
| 492 | }; |
| 493 | |
Shawn Guo | a15d9f8 | 2012-05-11 13:08:46 +0800 | [diff] [blame] | 494 | ssi3: ssi@83fe8000 { |
| 495 | compatible = "fsl,imx51-ssi", "fsl,imx21-ssi"; |
| 496 | reg = <0x83fe8000 0x4000>; |
| 497 | interrupts = <96>; |
Fabio Estevam | f40f38d | 2012-11-21 13:43:05 -0200 | [diff] [blame] | 498 | clocks = <&clks 50>; |
Shawn Guo | 5da826a | 2013-07-17 13:50:54 +0800 | [diff] [blame] | 499 | dmas = <&sdma 46 0 0>, |
| 500 | <&sdma 47 0 0>; |
| 501 | dma-names = "rx", "tx"; |
Shawn Guo | a15d9f8 | 2012-05-11 13:08:46 +0800 | [diff] [blame] | 502 | fsl,fifo-depth = <15>; |
| 503 | fsl,ssi-dma-events = <47 46 37 35>; /* TX0 RX0 TX1 RX1 */ |
| 504 | status = "disabled"; |
| 505 | }; |
| 506 | |
Sascha Hauer | 7b7d672 | 2012-11-15 09:31:52 +0100 | [diff] [blame] | 507 | fec: ethernet@83fec000 { |
Shawn Guo | 9daaf31 | 2011-10-17 08:42:17 +0800 | [diff] [blame] | 508 | compatible = "fsl,imx51-fec", "fsl,imx27-fec"; |
| 509 | reg = <0x83fec000 0x4000>; |
| 510 | interrupts = <87>; |
Fabio Estevam | f40f38d | 2012-11-21 13:43:05 -0200 | [diff] [blame] | 511 | clocks = <&clks 42>, <&clks 42>, <&clks 42>; |
| 512 | clock-names = "ipg", "ahb", "ptp"; |
Shawn Guo | 9daaf31 | 2011-10-17 08:42:17 +0800 | [diff] [blame] | 513 | status = "disabled"; |
| 514 | }; |
| 515 | }; |
| 516 | }; |
| 517 | }; |
Alexander Shiyan | 3587814 | 2013-08-14 13:05:51 +0400 | [diff] [blame] | 518 | |
| 519 | &iomuxc { |
| 520 | audmux { |
| 521 | pinctrl_audmux_1: audmuxgrp-1 { |
| 522 | fsl,pins = < |
| 523 | MX51_PAD_AUD3_BB_TXD__AUD3_TXD 0x80000000 |
| 524 | MX51_PAD_AUD3_BB_RXD__AUD3_RXD 0x80000000 |
| 525 | MX51_PAD_AUD3_BB_CK__AUD3_TXC 0x80000000 |
| 526 | MX51_PAD_AUD3_BB_FS__AUD3_TXFS 0x80000000 |
| 527 | >; |
| 528 | }; |
| 529 | }; |
| 530 | |
| 531 | fec { |
| 532 | pinctrl_fec_1: fecgrp-1 { |
| 533 | fsl,pins = < |
| 534 | MX51_PAD_EIM_EB2__FEC_MDIO 0x80000000 |
| 535 | MX51_PAD_EIM_EB3__FEC_RDATA1 0x80000000 |
| 536 | MX51_PAD_EIM_CS2__FEC_RDATA2 0x80000000 |
| 537 | MX51_PAD_EIM_CS3__FEC_RDATA3 0x80000000 |
| 538 | MX51_PAD_EIM_CS4__FEC_RX_ER 0x80000000 |
| 539 | MX51_PAD_EIM_CS5__FEC_CRS 0x80000000 |
| 540 | MX51_PAD_NANDF_RB2__FEC_COL 0x80000000 |
| 541 | MX51_PAD_NANDF_RB3__FEC_RX_CLK 0x80000000 |
| 542 | MX51_PAD_NANDF_D9__FEC_RDATA0 0x80000000 |
| 543 | MX51_PAD_NANDF_D8__FEC_TDATA0 0x80000000 |
| 544 | MX51_PAD_NANDF_CS2__FEC_TX_ER 0x80000000 |
| 545 | MX51_PAD_NANDF_CS3__FEC_MDC 0x80000000 |
| 546 | MX51_PAD_NANDF_CS4__FEC_TDATA1 0x80000000 |
| 547 | MX51_PAD_NANDF_CS5__FEC_TDATA2 0x80000000 |
| 548 | MX51_PAD_NANDF_CS6__FEC_TDATA3 0x80000000 |
| 549 | MX51_PAD_NANDF_CS7__FEC_TX_EN 0x80000000 |
| 550 | MX51_PAD_NANDF_RDY_INT__FEC_TX_CLK 0x80000000 |
| 551 | >; |
| 552 | }; |
| 553 | |
| 554 | pinctrl_fec_2: fecgrp-2 { |
| 555 | fsl,pins = < |
| 556 | MX51_PAD_DI_GP3__FEC_TX_ER 0x80000000 |
| 557 | MX51_PAD_DI2_PIN4__FEC_CRS 0x80000000 |
| 558 | MX51_PAD_DI2_PIN2__FEC_MDC 0x80000000 |
| 559 | MX51_PAD_DI2_PIN3__FEC_MDIO 0x80000000 |
| 560 | MX51_PAD_DI2_DISP_CLK__FEC_RDATA1 0x80000000 |
| 561 | MX51_PAD_DI_GP4__FEC_RDATA2 0x80000000 |
| 562 | MX51_PAD_DISP2_DAT0__FEC_RDATA3 0x80000000 |
| 563 | MX51_PAD_DISP2_DAT1__FEC_RX_ER 0x80000000 |
| 564 | MX51_PAD_DISP2_DAT6__FEC_TDATA1 0x80000000 |
| 565 | MX51_PAD_DISP2_DAT7__FEC_TDATA2 0x80000000 |
| 566 | MX51_PAD_DISP2_DAT8__FEC_TDATA3 0x80000000 |
| 567 | MX51_PAD_DISP2_DAT9__FEC_TX_EN 0x80000000 |
| 568 | MX51_PAD_DISP2_DAT10__FEC_COL 0x80000000 |
| 569 | MX51_PAD_DISP2_DAT11__FEC_RX_CLK 0x80000000 |
| 570 | MX51_PAD_DISP2_DAT12__FEC_RX_DV 0x80000000 |
| 571 | MX51_PAD_DISP2_DAT13__FEC_TX_CLK 0x80000000 |
| 572 | MX51_PAD_DISP2_DAT14__FEC_RDATA0 0x80000000 |
| 573 | MX51_PAD_DISP2_DAT15__FEC_TDATA0 0x80000000 |
| 574 | >; |
| 575 | }; |
| 576 | }; |
| 577 | |
| 578 | ecspi1 { |
| 579 | pinctrl_ecspi1_1: ecspi1grp-1 { |
| 580 | fsl,pins = < |
| 581 | MX51_PAD_CSPI1_MISO__ECSPI1_MISO 0x185 |
| 582 | MX51_PAD_CSPI1_MOSI__ECSPI1_MOSI 0x185 |
| 583 | MX51_PAD_CSPI1_SCLK__ECSPI1_SCLK 0x185 |
| 584 | >; |
| 585 | }; |
| 586 | }; |
| 587 | |
| 588 | ecspi2 { |
| 589 | pinctrl_ecspi2_1: ecspi2grp-1 { |
| 590 | fsl,pins = < |
| 591 | MX51_PAD_NANDF_RB3__ECSPI2_MISO 0x185 |
| 592 | MX51_PAD_NANDF_D15__ECSPI2_MOSI 0x185 |
| 593 | MX51_PAD_NANDF_RB2__ECSPI2_SCLK 0x185 |
| 594 | >; |
| 595 | }; |
| 596 | }; |
| 597 | |
| 598 | esdhc1 { |
| 599 | pinctrl_esdhc1_1: esdhc1grp-1 { |
| 600 | fsl,pins = < |
| 601 | MX51_PAD_SD1_CMD__SD1_CMD 0x400020d5 |
| 602 | MX51_PAD_SD1_CLK__SD1_CLK 0x20d5 |
| 603 | MX51_PAD_SD1_DATA0__SD1_DATA0 0x20d5 |
| 604 | MX51_PAD_SD1_DATA1__SD1_DATA1 0x20d5 |
| 605 | MX51_PAD_SD1_DATA2__SD1_DATA2 0x20d5 |
| 606 | MX51_PAD_SD1_DATA3__SD1_DATA3 0x20d5 |
| 607 | >; |
| 608 | }; |
| 609 | }; |
| 610 | |
| 611 | esdhc2 { |
| 612 | pinctrl_esdhc2_1: esdhc2grp-1 { |
| 613 | fsl,pins = < |
| 614 | MX51_PAD_SD2_CMD__SD2_CMD 0x400020d5 |
| 615 | MX51_PAD_SD2_CLK__SD2_CLK 0x20d5 |
| 616 | MX51_PAD_SD2_DATA0__SD2_DATA0 0x20d5 |
| 617 | MX51_PAD_SD2_DATA1__SD2_DATA1 0x20d5 |
| 618 | MX51_PAD_SD2_DATA2__SD2_DATA2 0x20d5 |
| 619 | MX51_PAD_SD2_DATA3__SD2_DATA3 0x20d5 |
| 620 | >; |
| 621 | }; |
| 622 | }; |
| 623 | |
| 624 | i2c2 { |
| 625 | pinctrl_i2c2_1: i2c2grp-1 { |
| 626 | fsl,pins = < |
| 627 | MX51_PAD_KEY_COL4__I2C2_SCL 0x400001ed |
| 628 | MX51_PAD_KEY_COL5__I2C2_SDA 0x400001ed |
| 629 | >; |
| 630 | }; |
| 631 | |
| 632 | pinctrl_i2c2_2: i2c2grp-2 { |
| 633 | fsl,pins = < |
| 634 | MX51_PAD_EIM_D27__I2C2_SCL 0x400001ed |
| 635 | MX51_PAD_EIM_D24__I2C2_SDA 0x400001ed |
| 636 | >; |
| 637 | }; |
Alexander Shiyan | 10ed76d | 2013-08-14 13:05:52 +0400 | [diff] [blame] | 638 | |
| 639 | pinctrl_i2c2_3: i2c2grp-3 { |
| 640 | fsl,pins = < |
| 641 | MX51_PAD_GPIO1_2__I2C2_SCL 0x400001ed |
| 642 | MX51_PAD_GPIO1_3__I2C2_SDA 0x400001ed |
| 643 | >; |
| 644 | }; |
Alexander Shiyan | 3587814 | 2013-08-14 13:05:51 +0400 | [diff] [blame] | 645 | }; |
| 646 | |
| 647 | ipu_disp1 { |
| 648 | pinctrl_ipu_disp1_1: ipudisp1grp-1 { |
| 649 | fsl,pins = < |
| 650 | MX51_PAD_DISP1_DAT0__DISP1_DAT0 0x5 |
| 651 | MX51_PAD_DISP1_DAT1__DISP1_DAT1 0x5 |
| 652 | MX51_PAD_DISP1_DAT2__DISP1_DAT2 0x5 |
| 653 | MX51_PAD_DISP1_DAT3__DISP1_DAT3 0x5 |
| 654 | MX51_PAD_DISP1_DAT4__DISP1_DAT4 0x5 |
| 655 | MX51_PAD_DISP1_DAT5__DISP1_DAT5 0x5 |
| 656 | MX51_PAD_DISP1_DAT6__DISP1_DAT6 0x5 |
| 657 | MX51_PAD_DISP1_DAT7__DISP1_DAT7 0x5 |
| 658 | MX51_PAD_DISP1_DAT8__DISP1_DAT8 0x5 |
| 659 | MX51_PAD_DISP1_DAT9__DISP1_DAT9 0x5 |
| 660 | MX51_PAD_DISP1_DAT10__DISP1_DAT10 0x5 |
| 661 | MX51_PAD_DISP1_DAT11__DISP1_DAT11 0x5 |
| 662 | MX51_PAD_DISP1_DAT12__DISP1_DAT12 0x5 |
| 663 | MX51_PAD_DISP1_DAT13__DISP1_DAT13 0x5 |
| 664 | MX51_PAD_DISP1_DAT14__DISP1_DAT14 0x5 |
| 665 | MX51_PAD_DISP1_DAT15__DISP1_DAT15 0x5 |
| 666 | MX51_PAD_DISP1_DAT16__DISP1_DAT16 0x5 |
| 667 | MX51_PAD_DISP1_DAT17__DISP1_DAT17 0x5 |
| 668 | MX51_PAD_DISP1_DAT18__DISP1_DAT18 0x5 |
| 669 | MX51_PAD_DISP1_DAT19__DISP1_DAT19 0x5 |
| 670 | MX51_PAD_DISP1_DAT20__DISP1_DAT20 0x5 |
| 671 | MX51_PAD_DISP1_DAT21__DISP1_DAT21 0x5 |
| 672 | MX51_PAD_DISP1_DAT22__DISP1_DAT22 0x5 |
| 673 | MX51_PAD_DISP1_DAT23__DISP1_DAT23 0x5 |
| 674 | MX51_PAD_DI1_PIN2__DI1_PIN2 0x5 /* hsync */ |
| 675 | MX51_PAD_DI1_PIN3__DI1_PIN3 0x5 /* vsync */ |
| 676 | >; |
| 677 | }; |
| 678 | }; |
| 679 | |
| 680 | ipu_disp2 { |
| 681 | pinctrl_ipu_disp2_1: ipudisp2grp-1 { |
| 682 | fsl,pins = < |
| 683 | MX51_PAD_DISP2_DAT0__DISP2_DAT0 0x5 |
| 684 | MX51_PAD_DISP2_DAT1__DISP2_DAT1 0x5 |
| 685 | MX51_PAD_DISP2_DAT2__DISP2_DAT2 0x5 |
| 686 | MX51_PAD_DISP2_DAT3__DISP2_DAT3 0x5 |
| 687 | MX51_PAD_DISP2_DAT4__DISP2_DAT4 0x5 |
| 688 | MX51_PAD_DISP2_DAT5__DISP2_DAT5 0x5 |
| 689 | MX51_PAD_DISP2_DAT6__DISP2_DAT6 0x5 |
| 690 | MX51_PAD_DISP2_DAT7__DISP2_DAT7 0x5 |
| 691 | MX51_PAD_DISP2_DAT8__DISP2_DAT8 0x5 |
| 692 | MX51_PAD_DISP2_DAT9__DISP2_DAT9 0x5 |
| 693 | MX51_PAD_DISP2_DAT10__DISP2_DAT10 0x5 |
| 694 | MX51_PAD_DISP2_DAT11__DISP2_DAT11 0x5 |
| 695 | MX51_PAD_DISP2_DAT12__DISP2_DAT12 0x5 |
| 696 | MX51_PAD_DISP2_DAT13__DISP2_DAT13 0x5 |
| 697 | MX51_PAD_DISP2_DAT14__DISP2_DAT14 0x5 |
| 698 | MX51_PAD_DISP2_DAT15__DISP2_DAT15 0x5 |
| 699 | MX51_PAD_DI2_PIN2__DI2_PIN2 0x5 /* hsync */ |
| 700 | MX51_PAD_DI2_PIN3__DI2_PIN3 0x5 /* vsync */ |
| 701 | MX51_PAD_DI2_DISP_CLK__DI2_DISP_CLK 0x5 /* CLK */ |
| 702 | MX51_PAD_DI_GP4__DI2_PIN15 0x5 /* DE */ |
| 703 | >; |
| 704 | }; |
| 705 | }; |
| 706 | |
| 707 | kpp { |
| 708 | pinctrl_kpp_1: kppgrp-1 { |
| 709 | fsl,pins = < |
| 710 | MX51_PAD_KEY_ROW0__KEY_ROW0 0xe0 |
| 711 | MX51_PAD_KEY_ROW1__KEY_ROW1 0xe0 |
| 712 | MX51_PAD_KEY_ROW2__KEY_ROW2 0xe0 |
| 713 | MX51_PAD_KEY_ROW3__KEY_ROW3 0xe0 |
| 714 | MX51_PAD_KEY_COL0__KEY_COL0 0xe8 |
| 715 | MX51_PAD_KEY_COL1__KEY_COL1 0xe8 |
| 716 | MX51_PAD_KEY_COL2__KEY_COL2 0xe8 |
| 717 | MX51_PAD_KEY_COL3__KEY_COL3 0xe8 |
| 718 | >; |
| 719 | }; |
| 720 | }; |
| 721 | |
| 722 | pata { |
| 723 | pinctrl_pata_1: patagrp-1 { |
| 724 | fsl,pins = < |
| 725 | MX51_PAD_NANDF_WE_B__PATA_DIOW 0x2004 |
| 726 | MX51_PAD_NANDF_RE_B__PATA_DIOR 0x2004 |
| 727 | MX51_PAD_NANDF_ALE__PATA_BUFFER_EN 0x2004 |
| 728 | MX51_PAD_NANDF_CLE__PATA_RESET_B 0x2004 |
| 729 | MX51_PAD_NANDF_WP_B__PATA_DMACK 0x2004 |
| 730 | MX51_PAD_NANDF_RB0__PATA_DMARQ 0x2004 |
| 731 | MX51_PAD_NANDF_RB1__PATA_IORDY 0x2004 |
| 732 | MX51_PAD_GPIO_NAND__PATA_INTRQ 0x2004 |
| 733 | MX51_PAD_NANDF_CS2__PATA_CS_0 0x2004 |
| 734 | MX51_PAD_NANDF_CS3__PATA_CS_1 0x2004 |
| 735 | MX51_PAD_NANDF_CS4__PATA_DA_0 0x2004 |
| 736 | MX51_PAD_NANDF_CS5__PATA_DA_1 0x2004 |
| 737 | MX51_PAD_NANDF_CS6__PATA_DA_2 0x2004 |
| 738 | MX51_PAD_NANDF_D15__PATA_DATA15 0x2004 |
| 739 | MX51_PAD_NANDF_D14__PATA_DATA14 0x2004 |
| 740 | MX51_PAD_NANDF_D13__PATA_DATA13 0x2004 |
| 741 | MX51_PAD_NANDF_D12__PATA_DATA12 0x2004 |
| 742 | MX51_PAD_NANDF_D11__PATA_DATA11 0x2004 |
| 743 | MX51_PAD_NANDF_D10__PATA_DATA10 0x2004 |
| 744 | MX51_PAD_NANDF_D9__PATA_DATA9 0x2004 |
| 745 | MX51_PAD_NANDF_D8__PATA_DATA8 0x2004 |
| 746 | MX51_PAD_NANDF_D7__PATA_DATA7 0x2004 |
| 747 | MX51_PAD_NANDF_D6__PATA_DATA6 0x2004 |
| 748 | MX51_PAD_NANDF_D5__PATA_DATA5 0x2004 |
| 749 | MX51_PAD_NANDF_D4__PATA_DATA4 0x2004 |
| 750 | MX51_PAD_NANDF_D3__PATA_DATA3 0x2004 |
| 751 | MX51_PAD_NANDF_D2__PATA_DATA2 0x2004 |
| 752 | MX51_PAD_NANDF_D1__PATA_DATA1 0x2004 |
| 753 | MX51_PAD_NANDF_D0__PATA_DATA0 0x2004 |
| 754 | >; |
| 755 | }; |
| 756 | }; |
| 757 | |
| 758 | uart1 { |
| 759 | pinctrl_uart1_1: uart1grp-1 { |
| 760 | fsl,pins = < |
| 761 | MX51_PAD_UART1_RXD__UART1_RXD 0x1c5 |
| 762 | MX51_PAD_UART1_TXD__UART1_TXD 0x1c5 |
Alexander Shiyan | 727b812 | 2013-08-21 11:28:23 +0400 | [diff] [blame] | 763 | >; |
| 764 | }; |
| 765 | |
| 766 | pinctrl_uart1_rtscts_1: uart1rtscts-1 { |
| 767 | fsl,pins = < |
Alexander Shiyan | 3587814 | 2013-08-14 13:05:51 +0400 | [diff] [blame] | 768 | MX51_PAD_UART1_RTS__UART1_RTS 0x1c5 |
| 769 | MX51_PAD_UART1_CTS__UART1_CTS 0x1c5 |
| 770 | >; |
| 771 | }; |
| 772 | }; |
| 773 | |
| 774 | uart2 { |
| 775 | pinctrl_uart2_1: uart2grp-1 { |
| 776 | fsl,pins = < |
| 777 | MX51_PAD_UART2_RXD__UART2_RXD 0x1c5 |
| 778 | MX51_PAD_UART2_TXD__UART2_TXD 0x1c5 |
| 779 | >; |
| 780 | }; |
| 781 | }; |
| 782 | |
| 783 | uart3 { |
| 784 | pinctrl_uart3_1: uart3grp-1 { |
| 785 | fsl,pins = < |
| 786 | MX51_PAD_EIM_D25__UART3_RXD 0x1c5 |
| 787 | MX51_PAD_EIM_D26__UART3_TXD 0x1c5 |
Alexander Shiyan | 727b812 | 2013-08-21 11:28:23 +0400 | [diff] [blame] | 788 | >; |
| 789 | }; |
| 790 | |
| 791 | pinctrl_uart3_rtscts_1: uart3rtscts-1 { |
| 792 | fsl,pins = < |
Alexander Shiyan | 3587814 | 2013-08-14 13:05:51 +0400 | [diff] [blame] | 793 | MX51_PAD_EIM_D27__UART3_RTS 0x1c5 |
| 794 | MX51_PAD_EIM_D24__UART3_CTS 0x1c5 |
| 795 | >; |
| 796 | }; |
| 797 | |
| 798 | pinctrl_uart3_2: uart3grp-2 { |
| 799 | fsl,pins = < |
| 800 | MX51_PAD_UART3_RXD__UART3_RXD 0x1c5 |
| 801 | MX51_PAD_UART3_TXD__UART3_TXD 0x1c5 |
| 802 | >; |
| 803 | }; |
| 804 | }; |
| 805 | |
| 806 | usbh1 { |
| 807 | pinctrl_usbh1_1: usbh1grp-1 { |
| 808 | fsl,pins = < |
| 809 | MX51_PAD_USBH1_DATA0__USBH1_DATA0 0x1e5 |
| 810 | MX51_PAD_USBH1_DATA1__USBH1_DATA1 0x1e5 |
| 811 | MX51_PAD_USBH1_DATA2__USBH1_DATA2 0x1e5 |
| 812 | MX51_PAD_USBH1_DATA3__USBH1_DATA3 0x1e5 |
| 813 | MX51_PAD_USBH1_DATA4__USBH1_DATA4 0x1e5 |
| 814 | MX51_PAD_USBH1_DATA5__USBH1_DATA5 0x1e5 |
| 815 | MX51_PAD_USBH1_DATA6__USBH1_DATA6 0x1e5 |
| 816 | MX51_PAD_USBH1_DATA7__USBH1_DATA7 0x1e5 |
| 817 | MX51_PAD_USBH1_CLK__USBH1_CLK 0x1e5 |
| 818 | MX51_PAD_USBH1_DIR__USBH1_DIR 0x1e5 |
| 819 | MX51_PAD_USBH1_NXT__USBH1_NXT 0x1e5 |
| 820 | MX51_PAD_USBH1_STP__USBH1_STP 0x1e5 |
| 821 | >; |
| 822 | }; |
| 823 | }; |
| 824 | |
| 825 | usbh2 { |
| 826 | pinctrl_usbh2_1: usbh2grp-1 { |
| 827 | fsl,pins = < |
| 828 | MX51_PAD_EIM_D16__USBH2_DATA0 0x1e5 |
| 829 | MX51_PAD_EIM_D17__USBH2_DATA1 0x1e5 |
| 830 | MX51_PAD_EIM_D18__USBH2_DATA2 0x1e5 |
| 831 | MX51_PAD_EIM_D19__USBH2_DATA3 0x1e5 |
| 832 | MX51_PAD_EIM_D20__USBH2_DATA4 0x1e5 |
| 833 | MX51_PAD_EIM_D21__USBH2_DATA5 0x1e5 |
| 834 | MX51_PAD_EIM_D22__USBH2_DATA6 0x1e5 |
| 835 | MX51_PAD_EIM_D23__USBH2_DATA7 0x1e5 |
| 836 | MX51_PAD_EIM_A24__USBH2_CLK 0x1e5 |
| 837 | MX51_PAD_EIM_A25__USBH2_DIR 0x1e5 |
| 838 | MX51_PAD_EIM_A27__USBH2_NXT 0x1e5 |
| 839 | MX51_PAD_EIM_A26__USBH2_STP 0x1e5 |
| 840 | >; |
| 841 | }; |
| 842 | }; |
| 843 | }; |