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R Sricharan6b5de092012-05-10 19:46:00 +05301/*
Sricharan Rfa63d032013-06-07 18:52:47 +05302 * Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com/
R Sricharan6b5de092012-05-10 19:46:00 +05303 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License version 2 as
6 * published by the Free Software Foundation.
7 */
8/dts-v1/;
9
Florian Vaussard98ef79572013-05-31 14:32:55 +020010#include "omap5.dtsi"
J Keerthye00c27e2013-06-13 10:00:11 +053011#include <dt-bindings/interrupt-controller/irq.h>
12#include <dt-bindings/interrupt-controller/arm-gic.h>
R Sricharan6b5de092012-05-10 19:46:00 +053013
14/ {
Sricharan Rfa63d032013-06-07 18:52:47 +053015 model = "TI OMAP5 uEVM board";
16 compatible = "ti,omap5-uevm", "ti,omap5";
R Sricharan6b5de092012-05-10 19:46:00 +053017
18 memory {
19 device_type = "memory";
Santosh Shilimkar03178c62013-01-18 11:43:16 +053020 reg = <0x80000000 0x7F000000>; /* 2032 MB */
R Sricharan6b5de092012-05-10 19:46:00 +053021 };
Balaji T K5dd18b02012-08-07 12:48:21 +053022
23 vmmcsd_fixed: fixedregulator-mmcsd {
24 compatible = "regulator-fixed";
25 regulator-name = "vmmcsd_fixed";
26 regulator-min-microvolt = <3000000>;
27 regulator-max-microvolt = <3000000>;
28 };
Sourav Poddar5449fbc2012-07-25 11:03:27 +053029
Roger Quadrosed7f8e82013-06-07 18:52:48 +053030 /* HS USB Host PHY on PORT 2 */
31 hsusb2_phy: hsusb2_phy {
32 compatible = "usb-nop-xceiv";
Roger Quadros8ae9b592013-09-24 11:53:53 +030033 reset-gpios = <&gpio3 16 GPIO_ACTIVE_LOW>; /* gpio3_80 HUB_NRESET */
Roger Quadros153030c2013-06-18 19:04:46 +030034 /**
35 * FIXME
36 * Put the right clock phandle here when available
37 * clocks = <&auxclk1>;
38 * clock-names = "main_clk";
39 */
40 clock-frequency = <19200000>;
Roger Quadrosed7f8e82013-06-07 18:52:48 +053041 };
42
Roger Quadrosed7f8e82013-06-07 18:52:48 +053043 /* HS USB Host PHY on PORT 3 */
44 hsusb3_phy: hsusb3_phy {
45 compatible = "usb-nop-xceiv";
Roger Quadros8ae9b592013-09-24 11:53:53 +030046 reset-gpios = <&gpio3 15 GPIO_ACTIVE_LOW>; /* gpio3_79 ETH_NRESET */
Roger Quadrosed7f8e82013-06-07 18:52:48 +053047 };
48
Dan Murphy66155302013-06-07 18:52:49 +053049 leds {
50 compatible = "gpio-leds";
51 led@1 {
52 label = "omap5:blue:usr1";
53 gpios = <&gpio5 25 GPIO_ACTIVE_HIGH>; /* gpio5_153 D1 LED */
54 linux,default-trigger = "heartbeat";
55 default-state = "off";
56 };
57 };
Balaji T K5dd18b02012-08-07 12:48:21 +053058};
59
Peter Ujfalusi8bbacc52012-10-04 14:57:28 +030060&omap5_pmx_core {
61 pinctrl-names = "default";
62 pinctrl-0 = <
63 &twl6040_pins
64 &mcpdm_pins
Peter Ujfalusi8bbacc52012-10-04 14:57:28 +030065 &mcbsp1_pins
66 &mcbsp2_pins
Roger Quadrosed7f8e82013-06-07 18:52:48 +053067 &usbhost_pins
Dan Murphy66155302013-06-07 18:52:49 +053068 &led_gpio_pins
Peter Ujfalusi8bbacc52012-10-04 14:57:28 +030069 >;
70
71 twl6040_pins: pinmux_twl6040_pins {
72 pinctrl-single,pins = <
Peter Ujfalusi472e623d2013-10-23 12:32:19 +030073 0x17e (PIN_OUTPUT | MUX_MODE6) /* mcspi1_somi.gpio5_141 */
Peter Ujfalusi8bbacc52012-10-04 14:57:28 +030074 >;
75 };
76
77 mcpdm_pins: pinmux_mcpdm_pins {
78 pinctrl-single,pins = <
Florian Vaussardbcd3cca2013-05-31 14:32:59 +020079 0x142 (PIN_INPUT_PULLDOWN | MUX_MODE0) /* abe_clks.abe_clks */
80 0x15c (PIN_INPUT_PULLDOWN | MUX_MODE0) /* abemcpdm_ul_data.abemcpdm_ul_data */
81 0x15e (PIN_INPUT_PULLDOWN | MUX_MODE0) /* abemcpdm_dl_data.abemcpdm_dl_data */
82 0x160 (PIN_INPUT_PULLUP | MUX_MODE0) /* abemcpdm_frame.abemcpdm_frame */
83 0x162 (PIN_INPUT_PULLDOWN | MUX_MODE0) /* abemcpdm_lb_clk.abemcpdm_lb_clk */
Peter Ujfalusi8bbacc52012-10-04 14:57:28 +030084 >;
85 };
86
Peter Ujfalusi8bbacc52012-10-04 14:57:28 +030087 mcbsp1_pins: pinmux_mcbsp1_pins {
88 pinctrl-single,pins = <
Florian Vaussardbcd3cca2013-05-31 14:32:59 +020089 0x14c (PIN_INPUT | MUX_MODE1) /* abedmic_clk2.abemcbsp1_fsx */
90 0x14e (PIN_OUTPUT_PULLDOWN | MUX_MODE1) /* abedmic_clk3.abemcbsp1_dx */
91 0x150 (PIN_INPUT | MUX_MODE1) /* abeslimbus1_clock.abemcbsp1_clkx */
92 0x152 (PIN_INPUT_PULLDOWN | MUX_MODE1) /* abeslimbus1_data.abemcbsp1_dr */
Peter Ujfalusi8bbacc52012-10-04 14:57:28 +030093 >;
94 };
95
96 mcbsp2_pins: pinmux_mcbsp2_pins {
97 pinctrl-single,pins = <
Florian Vaussardbcd3cca2013-05-31 14:32:59 +020098 0x154 (PIN_INPUT_PULLDOWN | MUX_MODE0) /* abemcbsp2_dr.abemcbsp2_dr */
99 0x156 (PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* abemcbsp2_dx.abemcbsp2_dx */
100 0x158 (PIN_INPUT | MUX_MODE0) /* abemcbsp2_fsx.abemcbsp2_fsx */
101 0x15a (PIN_INPUT | MUX_MODE0) /* abemcbsp2_clkx.abemcbsp2_clkx */
Peter Ujfalusi8bbacc52012-10-04 14:57:28 +0300102 >;
103 };
Sourav Poddar9be495c2013-02-13 14:58:22 +0530104
Florian Vaussardbcd3cca2013-05-31 14:32:59 +0200105 i2c1_pins: pinmux_i2c1_pins {
106 pinctrl-single,pins = <
107 0x1b2 (PIN_INPUT_PULLUP | MUX_MODE0) /* i2c1_scl */
108 0x1b4 (PIN_INPUT_PULLUP | MUX_MODE0) /* i2c1_sda */
109 >;
110 };
Sourav Poddar9be495c2013-02-13 14:58:22 +0530111
Sourav Poddar9be495c2013-02-13 14:58:22 +0530112 i2c5_pins: pinmux_i2c5_pins {
113 pinctrl-single,pins = <
Florian Vaussardbcd3cca2013-05-31 14:32:59 +0200114 0x184 (PIN_INPUT | MUX_MODE0) /* i2c5_scl */
115 0x186 (PIN_INPUT | MUX_MODE0) /* i2c5_sda */
Sourav Poddar9be495c2013-02-13 14:58:22 +0530116 >;
117 };
Sourav Poddar392adaf2013-02-13 14:58:44 +0530118
119 mcspi2_pins: pinmux_mcspi2_pins {
120 pinctrl-single,pins = <
Florian Vaussardbcd3cca2013-05-31 14:32:59 +0200121 0xbc (PIN_INPUT | MUX_MODE0) /* mcspi2_clk */
122 0xbe (PIN_INPUT | MUX_MODE0) /* mcspi2_simo */
123 0xc0 (PIN_INPUT_PULLUP | MUX_MODE0) /* mcspi2_somi */
Eric Witcher05bc85d2013-10-18 02:42:34 -0400124 0xc2 (PIN_OUTPUT | MUX_MODE0) /* mcspi2_cs0 */
Sourav Poddar392adaf2013-02-13 14:58:44 +0530125 >;
126 };
127
128 mcspi3_pins: pinmux_mcspi3_pins {
129 pinctrl-single,pins = <
Eric Witcher05bc85d2013-10-18 02:42:34 -0400130 0x78 (PIN_INPUT | MUX_MODE1) /* mcspi3_somi */
131 0x7a (PIN_INPUT | MUX_MODE1) /* mcspi3_cs0 */
132 0x7c (PIN_INPUT | MUX_MODE1) /* mcspi3_simo */
133 0x7e (PIN_INPUT | MUX_MODE1) /* mcspi3_clk */
Sourav Poddar392adaf2013-02-13 14:58:44 +0530134 >;
135 };
136
137 mcspi4_pins: pinmux_mcspi4_pins {
138 pinctrl-single,pins = <
Eric Witcher05bc85d2013-10-18 02:42:34 -0400139 0x164 (PIN_INPUT | MUX_MODE1) /* mcspi4_clk */
140 0x168 (PIN_INPUT | MUX_MODE1) /* mcspi4_simo */
141 0x16a (PIN_INPUT | MUX_MODE1) /* mcspi4_somi */
142 0x16c (PIN_INPUT | MUX_MODE1) /* mcspi4_cs0 */
Sourav Poddar392adaf2013-02-13 14:58:44 +0530143 >;
144 };
Roger Quadrosed7f8e82013-06-07 18:52:48 +0530145
146 usbhost_pins: pinmux_usbhost_pins {
147 pinctrl-single,pins = <
148 0x84 (PIN_INPUT | MUX_MODE0) /* usbb2_hsic_strobe */
149 0x86 (PIN_INPUT | MUX_MODE0) /* usbb2_hsic_data */
150
151 0x19e (PIN_INPUT | MUX_MODE0) /* usbb3_hsic_strobe */
152 0x1a0 (PIN_INPUT | MUX_MODE0) /* usbb3_hsic_data */
153
154 0x70 (PIN_OUTPUT | MUX_MODE6) /* gpio3_80 HUB_NRESET */
155 0x6e (PIN_OUTPUT | MUX_MODE6) /* gpio3_79 ETH_NRESET */
156 >;
157 };
Dan Murphy66155302013-06-07 18:52:49 +0530158
159 led_gpio_pins: pinmux_led_gpio_pins {
160 pinctrl-single,pins = <
161 0x196 (PIN_OUTPUT | MUX_MODE6) /* uart3_cts_rctx.gpio5_153 */
162 >;
163 };
Sourav Poddared22fee2013-06-07 18:52:50 +0530164
165 uart1_pins: pinmux_uart1_pins {
166 pinctrl-single,pins = <
167 0x60 (PIN_OUTPUT | MUX_MODE0) /* uart1_tx.uart1_cts */
168 0x62 (PIN_INPUT_PULLUP | MUX_MODE0) /* uart1_tx.uart1_cts */
169 0x64 (PIN_INPUT_PULLUP | MUX_MODE0) /* uart1_rx.uart1_rts */
170 0x66 (PIN_OUTPUT | MUX_MODE0) /* uart1_rx.uart1_rts */
171 >;
172 };
173
174 uart3_pins: pinmux_uart3_pins {
175 pinctrl-single,pins = <
176 0x19a (PIN_OUTPUT | MUX_MODE0) /* uart3_rts_irsd.uart3_tx_irtx */
177 0x19c (PIN_INPUT_PULLUP | MUX_MODE0) /* uart3_rx_irrx.uart3_usbb3_hsic */
178 >;
179 };
180
181 uart5_pins: pinmux_uart5_pins {
182 pinctrl-single,pins = <
183 0x170 (PIN_INPUT_PULLUP | MUX_MODE0) /* uart5_rx.uart5_rx */
184 0x172 (PIN_OUTPUT | MUX_MODE0) /* uart5_tx.uart5_tx */
185 0x174 (PIN_INPUT_PULLUP | MUX_MODE0) /* uart5_cts.uart5_rts */
186 0x176 (PIN_OUTPUT | MUX_MODE0) /* uart5_cts.uart5_rts */
187 >;
188 };
189
Roger Quadrosed7f8e82013-06-07 18:52:48 +0530190};
191
192&omap5_pmx_wkup {
193 pinctrl-names = "default";
194 pinctrl-0 = <
195 &usbhost_wkup_pins
196 >;
197
198 usbhost_wkup_pins: pinmux_usbhost_wkup_pins {
199 pinctrl-single,pins = <
200 0x1A (PIN_OUTPUT | MUX_MODE0) /* fref_clk1_out, USB hub clk */
201 >;
202 };
Peter Ujfalusi8bbacc52012-10-04 14:57:28 +0300203};
204
Balaji T K5dd18b02012-08-07 12:48:21 +0530205&mmc1 {
Nishanth Menone18235a2013-07-29 12:03:02 -0500206 vmmc-supply = <&ldo9_reg>;
Balaji T K5dd18b02012-08-07 12:48:21 +0530207 bus-width = <4>;
208};
209
210&mmc2 {
211 vmmc-supply = <&vmmcsd_fixed>;
212 bus-width = <8>;
213 ti,non-removable;
214};
215
216&mmc3 {
217 bus-width = <4>;
218 ti,non-removable;
219};
220
221&mmc4 {
222 status = "disabled";
223};
224
225&mmc5 {
226 status = "disabled";
R Sricharan6b5de092012-05-10 19:46:00 +0530227};
Sourav Poddar08f3e212012-07-25 11:02:43 +0530228
Sourav Poddar9be495c2013-02-13 14:58:22 +0530229&i2c1 {
230 pinctrl-names = "default";
231 pinctrl-0 = <&i2c1_pins>;
232
233 clock-frequency = <400000>;
J Keerthye00c27e2013-06-13 10:00:11 +0530234
235 palmas: palmas@48 {
236 compatible = "ti,palmas";
237 interrupts = <GIC_SPI 7 IRQ_TYPE_NONE>; /* IRQ_SYS_1N */
238 interrupt-parent = <&gic>;
239 reg = <0x48>;
240 interrupt-controller;
241 #interrupt-cells = <2>;
Nishanth Menon86583372013-09-19 14:11:36 -0500242 ti,system-power-controller;
J Keerthye00c27e2013-06-13 10:00:11 +0530243
Felipe Balbie3a412c2013-08-21 20:01:32 +0530244 extcon_usb3: palmas_usb {
245 compatible = "ti,palmas-usb-vid";
246 ti,enable-vbus-detection;
247 ti,enable-id-detection;
248 ti,wakeup;
249 };
250
J Keerthye00c27e2013-06-13 10:00:11 +0530251 palmas_pmic {
252 compatible = "ti,palmas-pmic";
253 interrupt-parent = <&palmas>;
254 interrupts = <14 IRQ_TYPE_NONE>;
255 interrupt-name = "short-irq";
256
257 ti,ldo6-vibrator;
258
259 regulators {
260 smps123_reg: smps123 {
Nishanth Menon3709d322013-07-29 12:03:01 -0500261 /* VDD_OPP_MPU */
J Keerthye00c27e2013-06-13 10:00:11 +0530262 regulator-name = "smps123";
263 regulator-min-microvolt = < 600000>;
264 regulator-max-microvolt = <1500000>;
265 regulator-always-on;
266 regulator-boot-on;
267 };
268
269 smps45_reg: smps45 {
Nishanth Menon3709d322013-07-29 12:03:01 -0500270 /* VDD_OPP_MM */
J Keerthye00c27e2013-06-13 10:00:11 +0530271 regulator-name = "smps45";
272 regulator-min-microvolt = < 600000>;
273 regulator-max-microvolt = <1310000>;
274 regulator-always-on;
275 regulator-boot-on;
276 };
277
278 smps6_reg: smps6 {
Nishanth Menon3709d322013-07-29 12:03:01 -0500279 /* VDD_DDR3 - over VDD_SMPS6 */
J Keerthye00c27e2013-06-13 10:00:11 +0530280 regulator-name = "smps6";
281 regulator-min-microvolt = <1200000>;
282 regulator-max-microvolt = <1200000>;
283 regulator-always-on;
284 regulator-boot-on;
285 };
286
287 smps7_reg: smps7 {
Nishanth Menon3709d322013-07-29 12:03:01 -0500288 /* VDDS_1v8_OMAP over VDDS_1v8_MAIN */
J Keerthye00c27e2013-06-13 10:00:11 +0530289 regulator-name = "smps7";
290 regulator-min-microvolt = <1800000>;
291 regulator-max-microvolt = <1800000>;
292 regulator-always-on;
293 regulator-boot-on;
294 };
295
296 smps8_reg: smps8 {
Nishanth Menon3709d322013-07-29 12:03:01 -0500297 /* VDD_OPP_CORE */
J Keerthye00c27e2013-06-13 10:00:11 +0530298 regulator-name = "smps8";
299 regulator-min-microvolt = < 600000>;
300 regulator-max-microvolt = <1310000>;
301 regulator-always-on;
302 regulator-boot-on;
303 };
304
305 smps9_reg: smps9 {
Nishanth Menon3709d322013-07-29 12:03:01 -0500306 /* VDDA_2v1_AUD over VDD_2v1 */
J Keerthye00c27e2013-06-13 10:00:11 +0530307 regulator-name = "smps9";
308 regulator-min-microvolt = <2100000>;
309 regulator-max-microvolt = <2100000>;
J Keerthye00c27e2013-06-13 10:00:11 +0530310 ti,smps-range = <0x80>;
311 };
312
Kishon Vijay Abraham I94489962013-08-12 15:07:01 +0530313 smps10_out2_reg: smps10_out2 {
Nishanth Menon3709d322013-07-29 12:03:01 -0500314 /* VBUS_5V_OTG */
Kishon Vijay Abraham I94489962013-08-12 15:07:01 +0530315 regulator-name = "smps10_out2";
316 regulator-min-microvolt = <5000000>;
317 regulator-max-microvolt = <5000000>;
318 regulator-always-on;
319 regulator-boot-on;
320 };
321
322 smps10_out1_reg: smps10_out1 {
323 /* VBUS_5V_OTG */
324 regulator-name = "smps10_out1";
J Keerthye00c27e2013-06-13 10:00:11 +0530325 regulator-min-microvolt = <5000000>;
326 regulator-max-microvolt = <5000000>;
J Keerthye00c27e2013-06-13 10:00:11 +0530327 };
328
329 ldo1_reg: ldo1 {
Nishanth Menon3709d322013-07-29 12:03:01 -0500330 /* VDDAPHY_CAM: vdda_csiport */
J Keerthye00c27e2013-06-13 10:00:11 +0530331 regulator-name = "ldo1";
Nishanth Menone18235a2013-07-29 12:03:02 -0500332 regulator-min-microvolt = <1500000>;
333 regulator-max-microvolt = <1800000>;
J Keerthye00c27e2013-06-13 10:00:11 +0530334 };
335
336 ldo2_reg: ldo2 {
Nishanth Menon3709d322013-07-29 12:03:01 -0500337 /* VCC_2V8_DISP: Does not go anywhere */
J Keerthye00c27e2013-06-13 10:00:11 +0530338 regulator-name = "ldo2";
Nishanth Menonbd3c5542013-07-29 12:03:03 -0500339 regulator-min-microvolt = <2800000>;
340 regulator-max-microvolt = <2800000>;
341 /* Unused */
342 status = "disabled";
J Keerthye00c27e2013-06-13 10:00:11 +0530343 };
344
345 ldo3_reg: ldo3 {
Nishanth Menon3709d322013-07-29 12:03:01 -0500346 /* VDDAPHY_MDM: vdda_lli */
J Keerthye00c27e2013-06-13 10:00:11 +0530347 regulator-name = "ldo3";
Nishanth Menone18235a2013-07-29 12:03:02 -0500348 regulator-min-microvolt = <1500000>;
349 regulator-max-microvolt = <1500000>;
J Keerthye00c27e2013-06-13 10:00:11 +0530350 regulator-boot-on;
Nishanth Menone18235a2013-07-29 12:03:02 -0500351 /* Only if Modem is used */
352 status = "disabled";
J Keerthye00c27e2013-06-13 10:00:11 +0530353 };
354
355 ldo4_reg: ldo4 {
Nishanth Menon3709d322013-07-29 12:03:01 -0500356 /* VDDAPHY_DISP: vdda_dsiport/hdmi */
J Keerthye00c27e2013-06-13 10:00:11 +0530357 regulator-name = "ldo4";
Nishanth Menone18235a2013-07-29 12:03:02 -0500358 regulator-min-microvolt = <1500000>;
359 regulator-max-microvolt = <1800000>;
J Keerthye00c27e2013-06-13 10:00:11 +0530360 };
361
362 ldo5_reg: ldo5 {
Nishanth Menon3709d322013-07-29 12:03:01 -0500363 /* VDDA_1V8_PHY: usb/sata/hdmi.. */
J Keerthye00c27e2013-06-13 10:00:11 +0530364 regulator-name = "ldo5";
365 regulator-min-microvolt = <1800000>;
366 regulator-max-microvolt = <1800000>;
367 regulator-always-on;
368 regulator-boot-on;
369 };
370
371 ldo6_reg: ldo6 {
Nishanth Menon3709d322013-07-29 12:03:01 -0500372 /* VDDS_1V2_WKUP: hsic/ldo_emu_wkup */
J Keerthye00c27e2013-06-13 10:00:11 +0530373 regulator-name = "ldo6";
Nishanth Menone18235a2013-07-29 12:03:02 -0500374 regulator-min-microvolt = <1200000>;
375 regulator-max-microvolt = <1200000>;
J Keerthye00c27e2013-06-13 10:00:11 +0530376 regulator-always-on;
377 regulator-boot-on;
378 };
379
380 ldo7_reg: ldo7 {
Nishanth Menon3709d322013-07-29 12:03:01 -0500381 /* VDD_VPP: vpp1 */
J Keerthye00c27e2013-06-13 10:00:11 +0530382 regulator-name = "ldo7";
Nishanth Menone18235a2013-07-29 12:03:02 -0500383 regulator-min-microvolt = <2000000>;
384 regulator-max-microvolt = <2000000>;
385 /* Only for efuse reprograming! */
386 status = "disabled";
J Keerthye00c27e2013-06-13 10:00:11 +0530387 };
388
389 ldo8_reg: ldo8 {
Nishanth Menon3709d322013-07-29 12:03:01 -0500390 /* VDD_3v0: Does not go anywhere */
J Keerthye00c27e2013-06-13 10:00:11 +0530391 regulator-name = "ldo8";
Nishanth Menonbd3c5542013-07-29 12:03:03 -0500392 regulator-min-microvolt = <3000000>;
393 regulator-max-microvolt = <3000000>;
J Keerthye00c27e2013-06-13 10:00:11 +0530394 regulator-boot-on;
Nishanth Menonbd3c5542013-07-29 12:03:03 -0500395 /* Unused */
396 status = "disabled";
J Keerthye00c27e2013-06-13 10:00:11 +0530397 };
398
399 ldo9_reg: ldo9 {
Nishanth Menon3709d322013-07-29 12:03:01 -0500400 /* VCC_DV_SDIO: vdds_sdcard */
J Keerthye00c27e2013-06-13 10:00:11 +0530401 regulator-name = "ldo9";
402 regulator-min-microvolt = <1800000>;
Nishanth Menone18235a2013-07-29 12:03:02 -0500403 regulator-max-microvolt = <3000000>;
J Keerthye00c27e2013-06-13 10:00:11 +0530404 regulator-boot-on;
405 };
406
407 ldoln_reg: ldoln {
Nishanth Menon3709d322013-07-29 12:03:01 -0500408 /* VDDA_1v8_REF: vdds_osc/mm_l4per.. */
J Keerthye00c27e2013-06-13 10:00:11 +0530409 regulator-name = "ldoln";
410 regulator-min-microvolt = <1800000>;
411 regulator-max-microvolt = <1800000>;
412 regulator-always-on;
413 regulator-boot-on;
414 };
415
416 ldousb_reg: ldousb {
Nishanth Menon3709d322013-07-29 12:03:01 -0500417 /* VDDA_3V_USB: VDDA_USBHS33 */
J Keerthye00c27e2013-06-13 10:00:11 +0530418 regulator-name = "ldousb";
419 regulator-min-microvolt = <3250000>;
420 regulator-max-microvolt = <3250000>;
421 regulator-always-on;
422 regulator-boot-on;
423 };
Nishanth Menone18235a2013-07-29 12:03:02 -0500424
425 regen3_reg: regen3 {
426 /* REGEN3 controls LDO9 supply to card */
427 regulator-name = "regen3";
428 regulator-always-on;
429 regulator-boot-on;
430 };
J Keerthye00c27e2013-06-13 10:00:11 +0530431 };
432 };
433 };
Sourav Poddar9be495c2013-02-13 14:58:22 +0530434};
435
Sourav Poddar9be495c2013-02-13 14:58:22 +0530436&i2c5 {
437 pinctrl-names = "default";
438 pinctrl-0 = <&i2c5_pins>;
439
440 clock-frequency = <400000>;
441};
442
Peter Ujfalusi42601d52012-10-04 14:57:24 +0300443&mcbsp3 {
444 status = "disabled";
445};
Lokesh Vutla4d2750f2012-11-05 18:22:52 +0530446
Roger Quadrosed7f8e82013-06-07 18:52:48 +0530447&usbhshost {
448 port2-mode = "ehci-hsic";
449 port3-mode = "ehci-hsic";
450};
451
452&usbhsehci {
453 phys = <0 &hsusb2_phy &hsusb3_phy>;
454};
455
Felipe Balbie3a412c2013-08-21 20:01:32 +0530456&usb3 {
457 extcon = <&extcon_usb3>;
458 vbus-supply = <&smps10_out1_reg>;
459};
460
Sourav Poddar392adaf2013-02-13 14:58:44 +0530461&mcspi1 {
462
463};
464
465&mcspi2 {
466 pinctrl-names = "default";
467 pinctrl-0 = <&mcspi2_pins>;
468};
469
470&mcspi3 {
471 pinctrl-names = "default";
472 pinctrl-0 = <&mcspi3_pins>;
473};
474
475&mcspi4 {
476 pinctrl-names = "default";
477 pinctrl-0 = <&mcspi4_pins>;
478};
Sourav Poddared22fee2013-06-07 18:52:50 +0530479
480&uart1 {
481 pinctrl-names = "default";
482 pinctrl-0 = <&uart1_pins>;
483};
484
485&uart3 {
486 pinctrl-names = "default";
487 pinctrl-0 = <&uart3_pins>;
488};
489
490&uart5 {
491 pinctrl-names = "default";
492 pinctrl-0 = <&uart5_pins>;
493};
Nishanth Menonb8981d72013-10-16 10:39:04 -0500494
495&cpu0 {
496 cpu0-supply = <&smps123_reg>;
497};