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Sricharan R96ca8482013-12-03 15:57:23 +05301/*
2 * drivers/irqchip/irq-crossbar.c
3 *
4 * Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com
5 * Author: Sricharan R <r.sricharan@ti.com>
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
10 *
11 */
12#include <linux/err.h>
13#include <linux/io.h>
Joel Porquet41a83e02015-07-07 17:11:46 -040014#include <linux/irqchip.h>
Marc Zyngier783d3182015-03-11 15:43:44 +000015#include <linux/irqdomain.h>
Sricharan R96ca8482013-12-03 15:57:23 +053016#include <linux/of_address.h>
17#include <linux/of_irq.h>
18#include <linux/slab.h>
Marc Zyngier783d3182015-03-11 15:43:44 +000019
Sricharan R96ca8482013-12-03 15:57:23 +053020#define IRQ_FREE -1
Nishanth Menon1d50d2c2014-06-26 12:40:19 +053021#define IRQ_RESERVED -2
Nishanth Menon64e0f8b2014-06-26 12:40:21 +053022#define IRQ_SKIP -3
Sricharan R96ca8482013-12-03 15:57:23 +053023#define GIC_IRQ_START 32
24
Nishanth Menone30ef8a2014-06-26 12:40:26 +053025/**
26 * struct crossbar_device - crossbar device description
Marc Zyngier783d3182015-03-11 15:43:44 +000027 * @lock: spinlock serializing access to @irq_map
Sricharan R96ca8482013-12-03 15:57:23 +053028 * @int_max: maximum number of supported interrupts
Nishanth Menona35057d2014-06-26 12:40:22 +053029 * @safe_map: safe default value to initialize the crossbar
Nishanth Menon2f7d2fb2014-06-26 12:40:31 +053030 * @max_crossbar_sources: Maximum number of crossbar sources
Sricharan R96ca8482013-12-03 15:57:23 +053031 * @irq_map: array of interrupts to crossbar number mapping
32 * @crossbar_base: crossbar base address
33 * @register_offsets: offsets for each irq number
Nishanth Menone30ef8a2014-06-26 12:40:26 +053034 * @write: register write function pointer
Sricharan R96ca8482013-12-03 15:57:23 +053035 */
36struct crossbar_device {
Marc Zyngier783d3182015-03-11 15:43:44 +000037 raw_spinlock_t lock;
Sricharan R96ca8482013-12-03 15:57:23 +053038 uint int_max;
Nishanth Menona35057d2014-06-26 12:40:22 +053039 uint safe_map;
Nishanth Menon2f7d2fb2014-06-26 12:40:31 +053040 uint max_crossbar_sources;
Sricharan R96ca8482013-12-03 15:57:23 +053041 uint *irq_map;
42 void __iomem *crossbar_base;
43 int *register_offsets;
Nishanth Menona35057d2014-06-26 12:40:22 +053044 void (*write)(int, int);
Sricharan R96ca8482013-12-03 15:57:23 +053045};
46
47static struct crossbar_device *cb;
48
Marc Zyngier783d3182015-03-11 15:43:44 +000049static void crossbar_writel(int irq_no, int cb_no)
Sricharan R96ca8482013-12-03 15:57:23 +053050{
51 writel(cb_no, cb->crossbar_base + cb->register_offsets[irq_no]);
52}
53
Marc Zyngier783d3182015-03-11 15:43:44 +000054static void crossbar_writew(int irq_no, int cb_no)
Sricharan R96ca8482013-12-03 15:57:23 +053055{
56 writew(cb_no, cb->crossbar_base + cb->register_offsets[irq_no]);
57}
58
Marc Zyngier783d3182015-03-11 15:43:44 +000059static void crossbar_writeb(int irq_no, int cb_no)
Sricharan R96ca8482013-12-03 15:57:23 +053060{
61 writeb(cb_no, cb->crossbar_base + cb->register_offsets[irq_no]);
62}
63
Marc Zyngier783d3182015-03-11 15:43:44 +000064static struct irq_chip crossbar_chip = {
65 .name = "CBAR",
66 .irq_eoi = irq_chip_eoi_parent,
67 .irq_mask = irq_chip_mask_parent,
68 .irq_unmask = irq_chip_unmask_parent,
69 .irq_retrigger = irq_chip_retrigger_hierarchy,
Grygorii Strashkoe269ec42015-08-14 15:20:27 +030070 .irq_set_type = irq_chip_set_type_parent,
Grygorii Strashko8200fe42015-08-14 15:20:30 +030071 .flags = IRQCHIP_MASK_ON_SUSPEND |
72 IRQCHIP_SKIP_SET_WAKE,
Marc Zyngier783d3182015-03-11 15:43:44 +000073#ifdef CONFIG_SMP
74 .irq_set_affinity = irq_chip_set_affinity_parent,
75#endif
76};
77
78static int allocate_gic_irq(struct irq_domain *domain, unsigned virq,
79 irq_hw_number_t hwirq)
Nishanth Menon6f16fc82014-06-26 12:40:20 +053080{
Marc Zyngierf833f572015-10-13 12:51:33 +010081 struct irq_fwspec fwspec;
Nishanth Menon6f16fc82014-06-26 12:40:20 +053082 int i;
Marc Zyngier783d3182015-03-11 15:43:44 +000083 int err;
Nishanth Menon6f16fc82014-06-26 12:40:20 +053084
Marc Zyngierf833f572015-10-13 12:51:33 +010085 if (!irq_domain_get_of_node(domain->parent))
86 return -EINVAL;
87
Marc Zyngier783d3182015-03-11 15:43:44 +000088 raw_spin_lock(&cb->lock);
Nishanth Menonddee0fb2014-06-26 12:40:23 +053089 for (i = cb->int_max - 1; i >= 0; i--) {
Sricharan R96ca8482013-12-03 15:57:23 +053090 if (cb->irq_map[i] == IRQ_FREE) {
Marc Zyngier783d3182015-03-11 15:43:44 +000091 cb->irq_map[i] = hwirq;
92 break;
Sricharan R96ca8482013-12-03 15:57:23 +053093 }
94 }
Marc Zyngier783d3182015-03-11 15:43:44 +000095 raw_spin_unlock(&cb->lock);
Sricharan R96ca8482013-12-03 15:57:23 +053096
Marc Zyngier783d3182015-03-11 15:43:44 +000097 if (i < 0)
98 return -ENODEV;
99
Marc Zyngierf833f572015-10-13 12:51:33 +0100100 fwspec.fwnode = domain->parent->fwnode;
101 fwspec.param_count = 3;
102 fwspec.param[0] = 0; /* SPI */
103 fwspec.param[1] = i;
104 fwspec.param[2] = IRQ_TYPE_LEVEL_HIGH;
Marc Zyngier783d3182015-03-11 15:43:44 +0000105
Marc Zyngierf833f572015-10-13 12:51:33 +0100106 err = irq_domain_alloc_irqs_parent(domain, virq, 1, &fwspec);
Marc Zyngier783d3182015-03-11 15:43:44 +0000107 if (err)
108 cb->irq_map[i] = IRQ_FREE;
109 else
110 cb->write(i, hwirq);
111
112 return err;
Sricharan R96ca8482013-12-03 15:57:23 +0530113}
114
Marc Zyngier783d3182015-03-11 15:43:44 +0000115static int crossbar_domain_alloc(struct irq_domain *d, unsigned int virq,
116 unsigned int nr_irqs, void *data)
Nishanth Menon29918b62014-06-26 12:40:32 +0530117{
Marc Zyngierf833f572015-10-13 12:51:33 +0100118 struct irq_fwspec *fwspec = data;
Marc Zyngier783d3182015-03-11 15:43:44 +0000119 irq_hw_number_t hwirq;
120 int i;
Nishanth Menond3608922014-06-26 12:40:34 +0530121
Marc Zyngierf833f572015-10-13 12:51:33 +0100122 if (fwspec->param_count != 3)
Marc Zyngier783d3182015-03-11 15:43:44 +0000123 return -EINVAL; /* Not GIC compliant */
Marc Zyngierf833f572015-10-13 12:51:33 +0100124 if (fwspec->param[0] != 0)
Marc Zyngier783d3182015-03-11 15:43:44 +0000125 return -EINVAL; /* No PPI should point to this domain */
126
Marc Zyngierf833f572015-10-13 12:51:33 +0100127 hwirq = fwspec->param[1];
Marc Zyngier783d3182015-03-11 15:43:44 +0000128 if ((hwirq + nr_irqs) > cb->max_crossbar_sources)
129 return -EINVAL; /* Can't deal with this */
130
131 for (i = 0; i < nr_irqs; i++) {
132 int err = allocate_gic_irq(d, virq + i, hwirq + i);
133
134 if (err)
135 return err;
136
137 irq_domain_set_hwirq_and_chip(d, virq + i, hwirq + i,
138 &crossbar_chip, NULL);
Nishanth Menond3608922014-06-26 12:40:34 +0530139 }
Nishanth Menon29918b62014-06-26 12:40:32 +0530140
Sricharan R96ca8482013-12-03 15:57:23 +0530141 return 0;
142}
143
Sricharan R8b09a452014-06-26 12:40:30 +0530144/**
Marc Zyngier783d3182015-03-11 15:43:44 +0000145 * crossbar_domain_free - unmap/free a crossbar<->irq connection
146 * @domain: domain of irq to unmap
147 * @virq: virq number
148 * @nr_irqs: number of irqs to free
Sricharan R8b09a452014-06-26 12:40:30 +0530149 *
150 * We do not maintain a use count of total number of map/unmap
151 * calls for a particular irq to find out if a irq can be really
152 * unmapped. This is because unmap is called during irq_dispose_mapping(irq),
153 * after which irq is anyways unusable. So an explicit map has to be called
154 * after that.
155 */
Marc Zyngier783d3182015-03-11 15:43:44 +0000156static void crossbar_domain_free(struct irq_domain *domain, unsigned int virq,
157 unsigned int nr_irqs)
Sricharan R96ca8482013-12-03 15:57:23 +0530158{
Marc Zyngier783d3182015-03-11 15:43:44 +0000159 int i;
Sricharan R96ca8482013-12-03 15:57:23 +0530160
Marc Zyngier783d3182015-03-11 15:43:44 +0000161 raw_spin_lock(&cb->lock);
162 for (i = 0; i < nr_irqs; i++) {
163 struct irq_data *d = irq_domain_get_irq_data(domain, virq + i);
164
165 irq_domain_reset_irq_data(d);
166 cb->irq_map[d->hwirq] = IRQ_FREE;
167 cb->write(d->hwirq, cb->safe_map);
Nishanth Menona35057d2014-06-26 12:40:22 +0530168 }
Marc Zyngier783d3182015-03-11 15:43:44 +0000169 raw_spin_unlock(&cb->lock);
Sricharan R96ca8482013-12-03 15:57:23 +0530170}
171
Marc Zyngierf833f572015-10-13 12:51:33 +0100172static int crossbar_domain_translate(struct irq_domain *d,
173 struct irq_fwspec *fwspec,
174 unsigned long *hwirq,
175 unsigned int *type)
Sricharan R96ca8482013-12-03 15:57:23 +0530176{
Marc Zyngierf833f572015-10-13 12:51:33 +0100177 if (is_of_node(fwspec->fwnode)) {
178 if (fwspec->param_count != 3)
179 return -EINVAL;
Sricharan R96ca8482013-12-03 15:57:23 +0530180
Marc Zyngierf833f572015-10-13 12:51:33 +0100181 /* No PPI should point to this domain */
182 if (fwspec->param[0] != 0)
183 return -EINVAL;
184
185 *hwirq = fwspec->param[1];
Jon Huntera2a8fa52016-05-10 16:14:37 +0100186 *type = fwspec->param[2] & IRQ_TYPE_SENSE_MASK;
Marc Zyngierf833f572015-10-13 12:51:33 +0100187 return 0;
188 }
189
190 return -EINVAL;
Sricharan R96ca8482013-12-03 15:57:23 +0530191}
192
Marc Zyngier783d3182015-03-11 15:43:44 +0000193static const struct irq_domain_ops crossbar_domain_ops = {
Marc Zyngierf833f572015-10-13 12:51:33 +0100194 .alloc = crossbar_domain_alloc,
195 .free = crossbar_domain_free,
196 .translate = crossbar_domain_translate,
Sricharan R96ca8482013-12-03 15:57:23 +0530197};
198
199static int __init crossbar_of_init(struct device_node *node)
200{
Nishanth Menonedb442d2014-06-26 12:40:27 +0530201 int i, size, max = 0, reserved = 0, entry;
Sricharan R96ca8482013-12-03 15:57:23 +0530202 const __be32 *irqsr;
Nishanth Menonedb442d2014-06-26 12:40:27 +0530203 int ret = -ENOMEM;
Sricharan R96ca8482013-12-03 15:57:23 +0530204
Dan Carpenter3894e9e2014-04-03 10:21:34 +0300205 cb = kzalloc(sizeof(*cb), GFP_KERNEL);
Sricharan R96ca8482013-12-03 15:57:23 +0530206
207 if (!cb)
Nishanth Menonedb442d2014-06-26 12:40:27 +0530208 return ret;
Sricharan R96ca8482013-12-03 15:57:23 +0530209
210 cb->crossbar_base = of_iomap(node, 0);
211 if (!cb->crossbar_base)
Nishanth Menon3c44d512014-06-26 12:40:28 +0530212 goto err_cb;
Sricharan R96ca8482013-12-03 15:57:23 +0530213
Nishanth Menon2f7d2fb2014-06-26 12:40:31 +0530214 of_property_read_u32(node, "ti,max-crossbar-sources",
215 &cb->max_crossbar_sources);
216 if (!cb->max_crossbar_sources) {
217 pr_err("missing 'ti,max-crossbar-sources' property\n");
218 ret = -EINVAL;
219 goto err_base;
220 }
221
Sricharan R96ca8482013-12-03 15:57:23 +0530222 of_property_read_u32(node, "ti,max-irqs", &max);
Nishanth Menonedb442d2014-06-26 12:40:27 +0530223 if (!max) {
224 pr_err("missing 'ti,max-irqs' property\n");
225 ret = -EINVAL;
Nishanth Menon3c44d512014-06-26 12:40:28 +0530226 goto err_base;
Nishanth Menonedb442d2014-06-26 12:40:27 +0530227 }
Nishanth Menon4dbf45e2014-06-26 12:40:25 +0530228 cb->irq_map = kcalloc(max, sizeof(int), GFP_KERNEL);
Sricharan R96ca8482013-12-03 15:57:23 +0530229 if (!cb->irq_map)
Nishanth Menon3c44d512014-06-26 12:40:28 +0530230 goto err_base;
Sricharan R96ca8482013-12-03 15:57:23 +0530231
232 cb->int_max = max;
233
234 for (i = 0; i < max; i++)
235 cb->irq_map[i] = IRQ_FREE;
236
237 /* Get and mark reserved irqs */
238 irqsr = of_get_property(node, "ti,irqs-reserved", &size);
239 if (irqsr) {
240 size /= sizeof(__be32);
241
242 for (i = 0; i < size; i++) {
243 of_property_read_u32_index(node,
244 "ti,irqs-reserved",
245 i, &entry);
Dan Carpenter702f7e32014-08-07 18:28:21 +0300246 if (entry >= max) {
Sricharan R96ca8482013-12-03 15:57:23 +0530247 pr_err("Invalid reserved entry\n");
Nishanth Menonedb442d2014-06-26 12:40:27 +0530248 ret = -EINVAL;
Nishanth Menon3c44d512014-06-26 12:40:28 +0530249 goto err_irq_map;
Sricharan R96ca8482013-12-03 15:57:23 +0530250 }
Nishanth Menon1d50d2c2014-06-26 12:40:19 +0530251 cb->irq_map[entry] = IRQ_RESERVED;
Sricharan R96ca8482013-12-03 15:57:23 +0530252 }
253 }
254
Nishanth Menon64e0f8b2014-06-26 12:40:21 +0530255 /* Skip irqs hardwired to bypass the crossbar */
256 irqsr = of_get_property(node, "ti,irqs-skip", &size);
257 if (irqsr) {
258 size /= sizeof(__be32);
259
260 for (i = 0; i < size; i++) {
261 of_property_read_u32_index(node,
262 "ti,irqs-skip",
263 i, &entry);
Dan Carpenter702f7e32014-08-07 18:28:21 +0300264 if (entry >= max) {
Nishanth Menon64e0f8b2014-06-26 12:40:21 +0530265 pr_err("Invalid skip entry\n");
266 ret = -EINVAL;
Nishanth Menon3c44d512014-06-26 12:40:28 +0530267 goto err_irq_map;
Nishanth Menon64e0f8b2014-06-26 12:40:21 +0530268 }
269 cb->irq_map[entry] = IRQ_SKIP;
270 }
271 }
272
273
Nishanth Menon4dbf45e2014-06-26 12:40:25 +0530274 cb->register_offsets = kcalloc(max, sizeof(int), GFP_KERNEL);
Sricharan R96ca8482013-12-03 15:57:23 +0530275 if (!cb->register_offsets)
Nishanth Menon3c44d512014-06-26 12:40:28 +0530276 goto err_irq_map;
Sricharan R96ca8482013-12-03 15:57:23 +0530277
278 of_property_read_u32(node, "ti,reg-size", &size);
279
280 switch (size) {
281 case 1:
282 cb->write = crossbar_writeb;
283 break;
284 case 2:
285 cb->write = crossbar_writew;
286 break;
287 case 4:
288 cb->write = crossbar_writel;
289 break;
290 default:
291 pr_err("Invalid reg-size property\n");
Nishanth Menonedb442d2014-06-26 12:40:27 +0530292 ret = -EINVAL;
Nishanth Menon3c44d512014-06-26 12:40:28 +0530293 goto err_reg_offset;
Sricharan R96ca8482013-12-03 15:57:23 +0530294 break;
295 }
296
297 /*
298 * Register offsets are not linear because of the
299 * reserved irqs. so find and store the offsets once.
300 */
301 for (i = 0; i < max; i++) {
Nishanth Menon1d50d2c2014-06-26 12:40:19 +0530302 if (cb->irq_map[i] == IRQ_RESERVED)
Sricharan R96ca8482013-12-03 15:57:23 +0530303 continue;
304
305 cb->register_offsets[i] = reserved;
306 reserved += size;
307 }
308
Nishanth Menona35057d2014-06-26 12:40:22 +0530309 of_property_read_u32(node, "ti,irqs-safe-map", &cb->safe_map);
Nishanth Menona35057d2014-06-26 12:40:22 +0530310 /* Initialize the crossbar with safe map to start with */
311 for (i = 0; i < max; i++) {
312 if (cb->irq_map[i] == IRQ_RESERVED ||
313 cb->irq_map[i] == IRQ_SKIP)
314 continue;
315
316 cb->write(i, cb->safe_map);
317 }
318
Marc Zyngier783d3182015-03-11 15:43:44 +0000319 raw_spin_lock_init(&cb->lock);
320
Sricharan R96ca8482013-12-03 15:57:23 +0530321 return 0;
322
Nishanth Menon3c44d512014-06-26 12:40:28 +0530323err_reg_offset:
Sricharan R96ca8482013-12-03 15:57:23 +0530324 kfree(cb->register_offsets);
Nishanth Menon3c44d512014-06-26 12:40:28 +0530325err_irq_map:
Sricharan R96ca8482013-12-03 15:57:23 +0530326 kfree(cb->irq_map);
Nishanth Menon3c44d512014-06-26 12:40:28 +0530327err_base:
Sricharan R96ca8482013-12-03 15:57:23 +0530328 iounmap(cb->crossbar_base);
Nishanth Menon3c44d512014-06-26 12:40:28 +0530329err_cb:
Sricharan R96ca8482013-12-03 15:57:23 +0530330 kfree(cb);
Sricharan R99e37d0e2014-06-26 12:40:29 +0530331
332 cb = NULL;
Nishanth Menonedb442d2014-06-26 12:40:27 +0530333 return ret;
Sricharan R96ca8482013-12-03 15:57:23 +0530334}
335
Marc Zyngier783d3182015-03-11 15:43:44 +0000336static int __init irqcrossbar_init(struct device_node *node,
337 struct device_node *parent)
Sricharan R96ca8482013-12-03 15:57:23 +0530338{
Marc Zyngier783d3182015-03-11 15:43:44 +0000339 struct irq_domain *parent_domain, *domain;
340 int err;
Sricharan R96ca8482013-12-03 15:57:23 +0530341
Marc Zyngier783d3182015-03-11 15:43:44 +0000342 if (!parent) {
343 pr_err("%s: no parent, giving up\n", node->full_name);
344 return -ENODEV;
345 }
346
347 parent_domain = irq_find_host(parent);
348 if (!parent_domain) {
349 pr_err("%s: unable to obtain parent domain\n", node->full_name);
350 return -ENXIO;
351 }
352
353 err = crossbar_of_init(node);
354 if (err)
355 return err;
356
357 domain = irq_domain_add_hierarchy(parent_domain, 0,
358 cb->max_crossbar_sources,
359 node, &crossbar_domain_ops,
360 NULL);
361 if (!domain) {
362 pr_err("%s: failed to allocated domain\n", node->full_name);
363 return -ENOMEM;
364 }
365
Sricharan R96ca8482013-12-03 15:57:23 +0530366 return 0;
367}
Marc Zyngier783d3182015-03-11 15:43:44 +0000368
369IRQCHIP_DECLARE(ti_irqcrossbar, "ti,irq-crossbar", irqcrossbar_init);