Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 1 | /* |
| 2 | * Copyright 2006 Dave Airlie <airlied@linux.ie> |
| 3 | * Copyright © 2006-2007 Intel Corporation |
| 4 | * Jesse Barnes <jesse.barnes@intel.com> |
| 5 | * |
| 6 | * Permission is hereby granted, free of charge, to any person obtaining a |
| 7 | * copy of this software and associated documentation files (the "Software"), |
| 8 | * to deal in the Software without restriction, including without limitation |
| 9 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, |
| 10 | * and/or sell copies of the Software, and to permit persons to whom the |
| 11 | * Software is furnished to do so, subject to the following conditions: |
| 12 | * |
| 13 | * The above copyright notice and this permission notice (including the next |
| 14 | * paragraph) shall be included in all copies or substantial portions of the |
| 15 | * Software. |
| 16 | * |
| 17 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
| 18 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
| 19 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
| 20 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER |
| 21 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING |
| 22 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER |
| 23 | * DEALINGS IN THE SOFTWARE. |
| 24 | * |
| 25 | * Authors: |
| 26 | * Eric Anholt <eric@anholt.net> |
| 27 | */ |
| 28 | #include <linux/i2c.h> |
| 29 | #include <linux/delay.h> |
| 30 | #include "drmP.h" |
| 31 | #include "drm.h" |
| 32 | #include "drm_crtc.h" |
| 33 | #include "intel_drv.h" |
ling.ma@intel.com | 2b8d33f7 | 2009-07-29 11:31:18 +0800 | [diff] [blame] | 34 | #include "drm_edid.h" |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 35 | #include "i915_drm.h" |
| 36 | #include "i915_drv.h" |
| 37 | #include "intel_sdvo_regs.h" |
| 38 | |
Zhenyu Wang | 14571b4 | 2010-03-30 14:06:33 +0800 | [diff] [blame] | 39 | #define SDVO_TMDS_MASK (SDVO_OUTPUT_TMDS0 | SDVO_OUTPUT_TMDS1) |
| 40 | #define SDVO_RGB_MASK (SDVO_OUTPUT_RGB0 | SDVO_OUTPUT_RGB1) |
| 41 | #define SDVO_LVDS_MASK (SDVO_OUTPUT_LVDS0 | SDVO_OUTPUT_LVDS1) |
| 42 | #define SDVO_TV_MASK (SDVO_OUTPUT_CVBS0 | SDVO_OUTPUT_SVID0) |
| 43 | |
| 44 | #define SDVO_OUTPUT_MASK (SDVO_TMDS_MASK | SDVO_RGB_MASK | SDVO_LVDS_MASK |\ |
| 45 | SDVO_TV_MASK) |
| 46 | |
| 47 | #define IS_TV(c) (c->output_flag & SDVO_TV_MASK) |
| 48 | #define IS_LVDS(c) (c->output_flag & SDVO_LVDS_MASK) |
| 49 | |
| 50 | |
Zhao Yakui | ce6feab | 2009-08-24 13:50:26 +0800 | [diff] [blame] | 51 | static char *tv_format_names[] = { |
| 52 | "NTSC_M" , "NTSC_J" , "NTSC_443", |
| 53 | "PAL_B" , "PAL_D" , "PAL_G" , |
| 54 | "PAL_H" , "PAL_I" , "PAL_M" , |
| 55 | "PAL_N" , "PAL_NC" , "PAL_60" , |
| 56 | "SECAM_B" , "SECAM_D" , "SECAM_G" , |
| 57 | "SECAM_K" , "SECAM_K1", "SECAM_L" , |
| 58 | "SECAM_60" |
| 59 | }; |
| 60 | |
| 61 | #define TV_FORMAT_NUM (sizeof(tv_format_names) / sizeof(*tv_format_names)) |
| 62 | |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 63 | struct intel_sdvo_priv { |
Keith Packard | f9c10a9 | 2009-05-30 12:16:25 -0700 | [diff] [blame] | 64 | u8 slave_addr; |
Jesse Barnes | e2f0ba9 | 2009-02-02 15:11:52 -0800 | [diff] [blame] | 65 | |
| 66 | /* Register for the SDVO device: SDVOB or SDVOC */ |
Eric Anholt | c751ce4 | 2010-03-25 11:48:48 -0700 | [diff] [blame] | 67 | int sdvo_reg; |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 68 | |
Jesse Barnes | e2f0ba9 | 2009-02-02 15:11:52 -0800 | [diff] [blame] | 69 | /* Active outputs controlled by this SDVO output */ |
| 70 | uint16_t controlled_output; |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 71 | |
Jesse Barnes | e2f0ba9 | 2009-02-02 15:11:52 -0800 | [diff] [blame] | 72 | /* |
| 73 | * Capabilities of the SDVO device returned by |
| 74 | * i830_sdvo_get_capabilities() |
| 75 | */ |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 76 | struct intel_sdvo_caps caps; |
Jesse Barnes | e2f0ba9 | 2009-02-02 15:11:52 -0800 | [diff] [blame] | 77 | |
| 78 | /* Pixel clock limitations reported by the SDVO device, in kHz */ |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 79 | int pixel_clock_min, pixel_clock_max; |
| 80 | |
ling.ma@intel.com | fb7a46f | 2009-07-23 17:11:34 +0800 | [diff] [blame] | 81 | /* |
| 82 | * For multiple function SDVO device, |
| 83 | * this is for current attached outputs. |
| 84 | */ |
| 85 | uint16_t attached_output; |
| 86 | |
Jesse Barnes | e2f0ba9 | 2009-02-02 15:11:52 -0800 | [diff] [blame] | 87 | /** |
| 88 | * This is set if we're going to treat the device as TV-out. |
| 89 | * |
| 90 | * While we have these nice friendly flags for output types that ought |
| 91 | * to decide this for us, the S-Video output on our HDMI+S-Video card |
| 92 | * shows up as RGB1 (VGA). |
| 93 | */ |
| 94 | bool is_tv; |
| 95 | |
Zhao Yakui | ce6feab | 2009-08-24 13:50:26 +0800 | [diff] [blame] | 96 | /* This is for current tv format name */ |
| 97 | char *tv_format_name; |
| 98 | |
Jesse Barnes | e2f0ba9 | 2009-02-02 15:11:52 -0800 | [diff] [blame] | 99 | /** |
| 100 | * This is set if we treat the device as HDMI, instead of DVI. |
| 101 | */ |
| 102 | bool is_hdmi; |
ling.ma@intel.com | 12682a9 | 2009-06-30 11:35:35 +0800 | [diff] [blame] | 103 | |
Ma Ling | 7086c87 | 2009-05-13 11:20:06 +0800 | [diff] [blame] | 104 | /** |
| 105 | * This is set if we detect output of sdvo device as LVDS. |
| 106 | */ |
| 107 | bool is_lvds; |
Jesse Barnes | e2f0ba9 | 2009-02-02 15:11:52 -0800 | [diff] [blame] | 108 | |
| 109 | /** |
ling.ma@intel.com | 12682a9 | 2009-06-30 11:35:35 +0800 | [diff] [blame] | 110 | * This is sdvo flags for input timing. |
| 111 | */ |
| 112 | uint8_t sdvo_flags; |
| 113 | |
| 114 | /** |
| 115 | * This is sdvo fixed pannel mode pointer |
| 116 | */ |
| 117 | struct drm_display_mode *sdvo_lvds_fixed_mode; |
| 118 | |
Jesse Barnes | e2f0ba9 | 2009-02-02 15:11:52 -0800 | [diff] [blame] | 119 | /* |
| 120 | * supported encoding mode, used to determine whether HDMI is |
| 121 | * supported |
| 122 | */ |
| 123 | struct intel_sdvo_encode encode; |
| 124 | |
Eric Anholt | c751ce4 | 2010-03-25 11:48:48 -0700 | [diff] [blame] | 125 | /* DDC bus used by this SDVO encoder */ |
Jesse Barnes | e2f0ba9 | 2009-02-02 15:11:52 -0800 | [diff] [blame] | 126 | uint8_t ddc_bus; |
| 127 | |
Keith Packard | 57cdaf9 | 2009-09-04 13:07:54 +0800 | [diff] [blame] | 128 | /* Mac mini hack -- use the same DDC as the analog connector */ |
| 129 | struct i2c_adapter *analog_ddc_bus; |
| 130 | |
Zhenyu Wang | 14571b4 | 2010-03-30 14:06:33 +0800 | [diff] [blame] | 131 | }; |
| 132 | |
| 133 | struct intel_sdvo_connector { |
| 134 | /* Mark the type of connector */ |
| 135 | uint16_t output_flag; |
| 136 | |
| 137 | /* This contains all current supported TV format */ |
| 138 | char *tv_format_supported[TV_FORMAT_NUM]; |
| 139 | int format_supported_num; |
| 140 | struct drm_property *tv_format_property; |
| 141 | struct drm_property *tv_format_name_property[TV_FORMAT_NUM]; |
| 142 | |
| 143 | /** |
| 144 | * Returned SDTV resolutions allowed for the current format, if the |
| 145 | * device reported it. |
| 146 | */ |
| 147 | struct intel_sdvo_sdtv_resolution_reply sdtv_resolutions; |
| 148 | |
Zhao Yakui | b9219c5 | 2009-09-10 15:45:46 +0800 | [diff] [blame] | 149 | /* add the property for the SDVO-TV */ |
| 150 | struct drm_property *left_property; |
| 151 | struct drm_property *right_property; |
| 152 | struct drm_property *top_property; |
| 153 | struct drm_property *bottom_property; |
| 154 | struct drm_property *hpos_property; |
| 155 | struct drm_property *vpos_property; |
| 156 | |
| 157 | /* add the property for the SDVO-TV/LVDS */ |
| 158 | struct drm_property *brightness_property; |
| 159 | struct drm_property *contrast_property; |
| 160 | struct drm_property *saturation_property; |
| 161 | struct drm_property *hue_property; |
| 162 | |
| 163 | /* Add variable to record current setting for the above property */ |
| 164 | u32 left_margin, right_margin, top_margin, bottom_margin; |
| 165 | /* this is to get the range of margin.*/ |
| 166 | u32 max_hscan, max_vscan; |
| 167 | u32 max_hpos, cur_hpos; |
| 168 | u32 max_vpos, cur_vpos; |
| 169 | u32 cur_brightness, max_brightness; |
| 170 | u32 cur_contrast, max_contrast; |
| 171 | u32 cur_saturation, max_saturation; |
| 172 | u32 cur_hue, max_hue; |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 173 | }; |
| 174 | |
ling.ma@intel.com | fb7a46f | 2009-07-23 17:11:34 +0800 | [diff] [blame] | 175 | static bool |
Zhenyu Wang | d2a82a6 | 2010-03-29 21:22:55 +0800 | [diff] [blame] | 176 | intel_sdvo_output_setup(struct intel_encoder *intel_encoder, |
Zhenyu Wang | d2a82a6 | 2010-03-29 21:22:55 +0800 | [diff] [blame] | 177 | uint16_t flags); |
Zhenyu Wang | 14571b4 | 2010-03-30 14:06:33 +0800 | [diff] [blame] | 178 | static void |
| 179 | intel_sdvo_tv_create_property(struct drm_connector *connector, int type); |
| 180 | static void |
| 181 | intel_sdvo_create_enhance_property(struct drm_connector *connector); |
ling.ma@intel.com | fb7a46f | 2009-07-23 17:11:34 +0800 | [diff] [blame] | 182 | |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 183 | /** |
| 184 | * Writes the SDVOB or SDVOC with the given value, but always writes both |
| 185 | * SDVOB and SDVOC to work around apparent hardware issues (according to |
| 186 | * comments in the BIOS). |
| 187 | */ |
Eric Anholt | 21d40d3 | 2010-03-25 11:11:14 -0700 | [diff] [blame] | 188 | static void intel_sdvo_write_sdvox(struct intel_encoder *intel_encoder, u32 val) |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 189 | { |
Zhenyu Wang | d2a82a6 | 2010-03-29 21:22:55 +0800 | [diff] [blame] | 190 | struct drm_device *dev = intel_encoder->enc.dev; |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 191 | struct drm_i915_private *dev_priv = dev->dev_private; |
Eric Anholt | 21d40d3 | 2010-03-25 11:11:14 -0700 | [diff] [blame] | 192 | struct intel_sdvo_priv *sdvo_priv = intel_encoder->dev_priv; |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 193 | u32 bval = val, cval = val; |
| 194 | int i; |
| 195 | |
Eric Anholt | c751ce4 | 2010-03-25 11:48:48 -0700 | [diff] [blame] | 196 | if (sdvo_priv->sdvo_reg == SDVOB) { |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 197 | cval = I915_READ(SDVOC); |
| 198 | } else { |
| 199 | bval = I915_READ(SDVOB); |
| 200 | } |
| 201 | /* |
| 202 | * Write the registers twice for luck. Sometimes, |
| 203 | * writing them only once doesn't appear to 'stick'. |
| 204 | * The BIOS does this too. Yay, magic |
| 205 | */ |
| 206 | for (i = 0; i < 2; i++) |
| 207 | { |
| 208 | I915_WRITE(SDVOB, bval); |
| 209 | I915_READ(SDVOB); |
| 210 | I915_WRITE(SDVOC, cval); |
| 211 | I915_READ(SDVOC); |
| 212 | } |
| 213 | } |
| 214 | |
Eric Anholt | 21d40d3 | 2010-03-25 11:11:14 -0700 | [diff] [blame] | 215 | static bool intel_sdvo_read_byte(struct intel_encoder *intel_encoder, u8 addr, |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 216 | u8 *ch) |
| 217 | { |
Eric Anholt | 21d40d3 | 2010-03-25 11:11:14 -0700 | [diff] [blame] | 218 | struct intel_sdvo_priv *sdvo_priv = intel_encoder->dev_priv; |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 219 | u8 out_buf[2]; |
| 220 | u8 buf[2]; |
| 221 | int ret; |
| 222 | |
| 223 | struct i2c_msg msgs[] = { |
| 224 | { |
Keith Packard | f9c10a9 | 2009-05-30 12:16:25 -0700 | [diff] [blame] | 225 | .addr = sdvo_priv->slave_addr >> 1, |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 226 | .flags = 0, |
| 227 | .len = 1, |
| 228 | .buf = out_buf, |
| 229 | }, |
| 230 | { |
Keith Packard | f9c10a9 | 2009-05-30 12:16:25 -0700 | [diff] [blame] | 231 | .addr = sdvo_priv->slave_addr >> 1, |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 232 | .flags = I2C_M_RD, |
| 233 | .len = 1, |
| 234 | .buf = buf, |
| 235 | } |
| 236 | }; |
| 237 | |
| 238 | out_buf[0] = addr; |
| 239 | out_buf[1] = 0; |
| 240 | |
Eric Anholt | 21d40d3 | 2010-03-25 11:11:14 -0700 | [diff] [blame] | 241 | if ((ret = i2c_transfer(intel_encoder->i2c_bus, msgs, 2)) == 2) |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 242 | { |
| 243 | *ch = buf[0]; |
| 244 | return true; |
| 245 | } |
| 246 | |
Zhao Yakui | 8a4c47f | 2009-07-20 13:48:04 +0800 | [diff] [blame] | 247 | DRM_DEBUG_KMS("i2c transfer returned %d\n", ret); |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 248 | return false; |
| 249 | } |
| 250 | |
Eric Anholt | 21d40d3 | 2010-03-25 11:11:14 -0700 | [diff] [blame] | 251 | static bool intel_sdvo_write_byte(struct intel_encoder *intel_encoder, int addr, |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 252 | u8 ch) |
| 253 | { |
Eric Anholt | 21d40d3 | 2010-03-25 11:11:14 -0700 | [diff] [blame] | 254 | struct intel_sdvo_priv *sdvo_priv = intel_encoder->dev_priv; |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 255 | u8 out_buf[2]; |
| 256 | struct i2c_msg msgs[] = { |
| 257 | { |
Keith Packard | f9c10a9 | 2009-05-30 12:16:25 -0700 | [diff] [blame] | 258 | .addr = sdvo_priv->slave_addr >> 1, |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 259 | .flags = 0, |
| 260 | .len = 2, |
| 261 | .buf = out_buf, |
| 262 | } |
| 263 | }; |
| 264 | |
| 265 | out_buf[0] = addr; |
| 266 | out_buf[1] = ch; |
| 267 | |
Eric Anholt | 21d40d3 | 2010-03-25 11:11:14 -0700 | [diff] [blame] | 268 | if (i2c_transfer(intel_encoder->i2c_bus, msgs, 1) == 1) |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 269 | { |
| 270 | return true; |
| 271 | } |
| 272 | return false; |
| 273 | } |
| 274 | |
| 275 | #define SDVO_CMD_NAME_ENTRY(cmd) {cmd, #cmd} |
| 276 | /** Mapping of command numbers to names, for debug output */ |
Tobias Klauser | 005568b | 2009-02-09 22:02:42 +0100 | [diff] [blame] | 277 | static const struct _sdvo_cmd_name { |
Jesse Barnes | e2f0ba9 | 2009-02-02 15:11:52 -0800 | [diff] [blame] | 278 | u8 cmd; |
| 279 | char *name; |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 280 | } sdvo_cmd_names[] = { |
| 281 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_RESET), |
| 282 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_DEVICE_CAPS), |
| 283 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_FIRMWARE_REV), |
| 284 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_TRAINED_INPUTS), |
| 285 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_ACTIVE_OUTPUTS), |
| 286 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_ACTIVE_OUTPUTS), |
| 287 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_IN_OUT_MAP), |
| 288 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_IN_OUT_MAP), |
| 289 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_ATTACHED_DISPLAYS), |
| 290 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_HOT_PLUG_SUPPORT), |
| 291 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_ACTIVE_HOT_PLUG), |
| 292 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_ACTIVE_HOT_PLUG), |
| 293 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_INTERRUPT_EVENT_SOURCE), |
| 294 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_TARGET_INPUT), |
| 295 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_TARGET_OUTPUT), |
| 296 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_INPUT_TIMINGS_PART1), |
| 297 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_INPUT_TIMINGS_PART2), |
| 298 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_INPUT_TIMINGS_PART1), |
| 299 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_INPUT_TIMINGS_PART2), |
| 300 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_INPUT_TIMINGS_PART1), |
| 301 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_OUTPUT_TIMINGS_PART1), |
| 302 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_OUTPUT_TIMINGS_PART2), |
| 303 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_OUTPUT_TIMINGS_PART1), |
| 304 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_OUTPUT_TIMINGS_PART2), |
| 305 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_CREATE_PREFERRED_INPUT_TIMING), |
| 306 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_PREFERRED_INPUT_TIMING_PART1), |
| 307 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_PREFERRED_INPUT_TIMING_PART2), |
| 308 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_INPUT_PIXEL_CLOCK_RANGE), |
| 309 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_OUTPUT_PIXEL_CLOCK_RANGE), |
| 310 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_SUPPORTED_CLOCK_RATE_MULTS), |
| 311 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_CLOCK_RATE_MULT), |
| 312 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_CLOCK_RATE_MULT), |
| 313 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_SUPPORTED_TV_FORMATS), |
| 314 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_TV_FORMAT), |
| 315 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_TV_FORMAT), |
Jesse Barnes | e2f0ba9 | 2009-02-02 15:11:52 -0800 | [diff] [blame] | 316 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_SUPPORTED_POWER_STATES), |
| 317 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_POWER_STATE), |
| 318 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_ENCODER_POWER_STATE), |
| 319 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_DISPLAY_POWER_STATE), |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 320 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_CONTROL_BUS_SWITCH), |
Jesse Barnes | e2f0ba9 | 2009-02-02 15:11:52 -0800 | [diff] [blame] | 321 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_SDTV_RESOLUTION_SUPPORT), |
| 322 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_SCALED_HDTV_RESOLUTION_SUPPORT), |
| 323 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_SUPPORTED_ENHANCEMENTS), |
Zhao Yakui | b9219c5 | 2009-09-10 15:45:46 +0800 | [diff] [blame] | 324 | /* Add the op code for SDVO enhancements */ |
| 325 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_POSITION_H), |
| 326 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_POSITION_H), |
| 327 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_POSITION_H), |
| 328 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_POSITION_V), |
| 329 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_POSITION_V), |
| 330 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_POSITION_V), |
| 331 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_SATURATION), |
| 332 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_SATURATION), |
| 333 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_SATURATION), |
| 334 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_HUE), |
| 335 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_HUE), |
| 336 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_HUE), |
| 337 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_CONTRAST), |
| 338 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_CONTRAST), |
| 339 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_CONTRAST), |
| 340 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_BRIGHTNESS), |
| 341 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_BRIGHTNESS), |
| 342 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_BRIGHTNESS), |
| 343 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_OVERSCAN_H), |
| 344 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_OVERSCAN_H), |
| 345 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_OVERSCAN_H), |
| 346 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_OVERSCAN_V), |
| 347 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_OVERSCAN_V), |
| 348 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_OVERSCAN_V), |
Jesse Barnes | e2f0ba9 | 2009-02-02 15:11:52 -0800 | [diff] [blame] | 349 | /* HDMI op code */ |
| 350 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_SUPP_ENCODE), |
| 351 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_ENCODE), |
| 352 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_ENCODE), |
| 353 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_PIXEL_REPLI), |
| 354 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_PIXEL_REPLI), |
| 355 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_COLORIMETRY_CAP), |
| 356 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_COLORIMETRY), |
| 357 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_COLORIMETRY), |
| 358 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_AUDIO_ENCRYPT_PREFER), |
| 359 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_AUDIO_STAT), |
| 360 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_AUDIO_STAT), |
| 361 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_HBUF_INDEX), |
| 362 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_HBUF_INDEX), |
| 363 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_HBUF_INFO), |
| 364 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_HBUF_AV_SPLIT), |
| 365 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_HBUF_AV_SPLIT), |
| 366 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_HBUF_TXRATE), |
| 367 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_HBUF_TXRATE), |
| 368 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_HBUF_DATA), |
| 369 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_HBUF_DATA), |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 370 | }; |
| 371 | |
Eric Anholt | c751ce4 | 2010-03-25 11:48:48 -0700 | [diff] [blame] | 372 | #define SDVO_NAME(dev_priv) ((dev_priv)->sdvo_reg == SDVOB ? "SDVOB" : "SDVOC") |
| 373 | #define SDVO_PRIV(encoder) ((struct intel_sdvo_priv *) (encoder)->dev_priv) |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 374 | |
Eric Anholt | 21d40d3 | 2010-03-25 11:11:14 -0700 | [diff] [blame] | 375 | static void intel_sdvo_debug_write(struct intel_encoder *intel_encoder, u8 cmd, |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 376 | void *args, int args_len) |
| 377 | { |
Eric Anholt | 21d40d3 | 2010-03-25 11:11:14 -0700 | [diff] [blame] | 378 | struct intel_sdvo_priv *sdvo_priv = intel_encoder->dev_priv; |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 379 | int i; |
| 380 | |
Zhao Yakui | 8a4c47f | 2009-07-20 13:48:04 +0800 | [diff] [blame] | 381 | DRM_DEBUG_KMS("%s: W: %02X ", |
yakui_zhao | 342dc38 | 2009-06-02 14:12:00 +0800 | [diff] [blame] | 382 | SDVO_NAME(sdvo_priv), cmd); |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 383 | for (i = 0; i < args_len; i++) |
yakui_zhao | 342dc38 | 2009-06-02 14:12:00 +0800 | [diff] [blame] | 384 | DRM_LOG_KMS("%02X ", ((u8 *)args)[i]); |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 385 | for (; i < 8; i++) |
yakui_zhao | 342dc38 | 2009-06-02 14:12:00 +0800 | [diff] [blame] | 386 | DRM_LOG_KMS(" "); |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 387 | for (i = 0; i < sizeof(sdvo_cmd_names) / sizeof(sdvo_cmd_names[0]); i++) { |
| 388 | if (cmd == sdvo_cmd_names[i].cmd) { |
yakui_zhao | 342dc38 | 2009-06-02 14:12:00 +0800 | [diff] [blame] | 389 | DRM_LOG_KMS("(%s)", sdvo_cmd_names[i].name); |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 390 | break; |
| 391 | } |
| 392 | } |
| 393 | if (i == sizeof(sdvo_cmd_names)/ sizeof(sdvo_cmd_names[0])) |
yakui_zhao | 342dc38 | 2009-06-02 14:12:00 +0800 | [diff] [blame] | 394 | DRM_LOG_KMS("(%02X)", cmd); |
| 395 | DRM_LOG_KMS("\n"); |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 396 | } |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 397 | |
Eric Anholt | 21d40d3 | 2010-03-25 11:11:14 -0700 | [diff] [blame] | 398 | static void intel_sdvo_write_cmd(struct intel_encoder *intel_encoder, u8 cmd, |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 399 | void *args, int args_len) |
| 400 | { |
| 401 | int i; |
| 402 | |
Eric Anholt | 21d40d3 | 2010-03-25 11:11:14 -0700 | [diff] [blame] | 403 | intel_sdvo_debug_write(intel_encoder, cmd, args, args_len); |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 404 | |
| 405 | for (i = 0; i < args_len; i++) { |
Eric Anholt | 21d40d3 | 2010-03-25 11:11:14 -0700 | [diff] [blame] | 406 | intel_sdvo_write_byte(intel_encoder, SDVO_I2C_ARG_0 - i, |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 407 | ((u8*)args)[i]); |
| 408 | } |
| 409 | |
Eric Anholt | 21d40d3 | 2010-03-25 11:11:14 -0700 | [diff] [blame] | 410 | intel_sdvo_write_byte(intel_encoder, SDVO_I2C_OPCODE, cmd); |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 411 | } |
| 412 | |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 413 | static const char *cmd_status_names[] = { |
| 414 | "Power on", |
| 415 | "Success", |
| 416 | "Not supported", |
| 417 | "Invalid arg", |
| 418 | "Pending", |
| 419 | "Target not specified", |
| 420 | "Scaling not supported" |
| 421 | }; |
| 422 | |
Eric Anholt | 21d40d3 | 2010-03-25 11:11:14 -0700 | [diff] [blame] | 423 | static void intel_sdvo_debug_response(struct intel_encoder *intel_encoder, |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 424 | void *response, int response_len, |
| 425 | u8 status) |
| 426 | { |
Eric Anholt | 21d40d3 | 2010-03-25 11:11:14 -0700 | [diff] [blame] | 427 | struct intel_sdvo_priv *sdvo_priv = intel_encoder->dev_priv; |
Zhenyu Wang | 33b5296 | 2009-03-24 14:02:40 +0800 | [diff] [blame] | 428 | int i; |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 429 | |
Zhao Yakui | 8a4c47f | 2009-07-20 13:48:04 +0800 | [diff] [blame] | 430 | DRM_DEBUG_KMS("%s: R: ", SDVO_NAME(sdvo_priv)); |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 431 | for (i = 0; i < response_len; i++) |
yakui_zhao | 342dc38 | 2009-06-02 14:12:00 +0800 | [diff] [blame] | 432 | DRM_LOG_KMS("%02X ", ((u8 *)response)[i]); |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 433 | for (; i < 8; i++) |
yakui_zhao | 342dc38 | 2009-06-02 14:12:00 +0800 | [diff] [blame] | 434 | DRM_LOG_KMS(" "); |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 435 | if (status <= SDVO_CMD_STATUS_SCALING_NOT_SUPP) |
yakui_zhao | 342dc38 | 2009-06-02 14:12:00 +0800 | [diff] [blame] | 436 | DRM_LOG_KMS("(%s)", cmd_status_names[status]); |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 437 | else |
yakui_zhao | 342dc38 | 2009-06-02 14:12:00 +0800 | [diff] [blame] | 438 | DRM_LOG_KMS("(??? %d)", status); |
| 439 | DRM_LOG_KMS("\n"); |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 440 | } |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 441 | |
Eric Anholt | 21d40d3 | 2010-03-25 11:11:14 -0700 | [diff] [blame] | 442 | static u8 intel_sdvo_read_response(struct intel_encoder *intel_encoder, |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 443 | void *response, int response_len) |
| 444 | { |
| 445 | int i; |
| 446 | u8 status; |
| 447 | u8 retry = 50; |
| 448 | |
| 449 | while (retry--) { |
| 450 | /* Read the command response */ |
| 451 | for (i = 0; i < response_len; i++) { |
Eric Anholt | 21d40d3 | 2010-03-25 11:11:14 -0700 | [diff] [blame] | 452 | intel_sdvo_read_byte(intel_encoder, |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 453 | SDVO_I2C_RETURN_0 + i, |
| 454 | &((u8 *)response)[i]); |
| 455 | } |
| 456 | |
| 457 | /* read the return status */ |
Eric Anholt | 21d40d3 | 2010-03-25 11:11:14 -0700 | [diff] [blame] | 458 | intel_sdvo_read_byte(intel_encoder, SDVO_I2C_CMD_STATUS, |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 459 | &status); |
| 460 | |
Eric Anholt | 21d40d3 | 2010-03-25 11:11:14 -0700 | [diff] [blame] | 461 | intel_sdvo_debug_response(intel_encoder, response, response_len, |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 462 | status); |
| 463 | if (status != SDVO_CMD_STATUS_PENDING) |
| 464 | return status; |
| 465 | |
| 466 | mdelay(50); |
| 467 | } |
| 468 | |
| 469 | return status; |
| 470 | } |
| 471 | |
Hannes Eder | b358d0a | 2008-12-18 21:18:47 +0100 | [diff] [blame] | 472 | static int intel_sdvo_get_pixel_multiplier(struct drm_display_mode *mode) |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 473 | { |
| 474 | if (mode->clock >= 100000) |
| 475 | return 1; |
| 476 | else if (mode->clock >= 50000) |
| 477 | return 2; |
| 478 | else |
| 479 | return 4; |
| 480 | } |
| 481 | |
| 482 | /** |
Zhao Yakui | 6a304ca | 2010-01-08 10:58:19 +0800 | [diff] [blame] | 483 | * Try to read the response after issuie the DDC switch command. But it |
| 484 | * is noted that we must do the action of reading response and issuing DDC |
| 485 | * switch command in one I2C transaction. Otherwise when we try to start |
| 486 | * another I2C transaction after issuing the DDC bus switch, it will be |
| 487 | * switched to the internal SDVO register. |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 488 | */ |
Eric Anholt | 21d40d3 | 2010-03-25 11:11:14 -0700 | [diff] [blame] | 489 | static void intel_sdvo_set_control_bus_switch(struct intel_encoder *intel_encoder, |
Hannes Eder | b358d0a | 2008-12-18 21:18:47 +0100 | [diff] [blame] | 490 | u8 target) |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 491 | { |
Eric Anholt | 21d40d3 | 2010-03-25 11:11:14 -0700 | [diff] [blame] | 492 | struct intel_sdvo_priv *sdvo_priv = intel_encoder->dev_priv; |
Zhao Yakui | 6a304ca | 2010-01-08 10:58:19 +0800 | [diff] [blame] | 493 | u8 out_buf[2], cmd_buf[2], ret_value[2], ret; |
| 494 | struct i2c_msg msgs[] = { |
| 495 | { |
| 496 | .addr = sdvo_priv->slave_addr >> 1, |
| 497 | .flags = 0, |
| 498 | .len = 2, |
| 499 | .buf = out_buf, |
| 500 | }, |
| 501 | /* the following two are to read the response */ |
| 502 | { |
| 503 | .addr = sdvo_priv->slave_addr >> 1, |
| 504 | .flags = 0, |
| 505 | .len = 1, |
| 506 | .buf = cmd_buf, |
| 507 | }, |
| 508 | { |
| 509 | .addr = sdvo_priv->slave_addr >> 1, |
| 510 | .flags = I2C_M_RD, |
| 511 | .len = 1, |
| 512 | .buf = ret_value, |
| 513 | }, |
| 514 | }; |
| 515 | |
Eric Anholt | 21d40d3 | 2010-03-25 11:11:14 -0700 | [diff] [blame] | 516 | intel_sdvo_debug_write(intel_encoder, SDVO_CMD_SET_CONTROL_BUS_SWITCH, |
Zhao Yakui | 6a304ca | 2010-01-08 10:58:19 +0800 | [diff] [blame] | 517 | &target, 1); |
| 518 | /* write the DDC switch command argument */ |
Eric Anholt | 21d40d3 | 2010-03-25 11:11:14 -0700 | [diff] [blame] | 519 | intel_sdvo_write_byte(intel_encoder, SDVO_I2C_ARG_0, target); |
Zhao Yakui | 6a304ca | 2010-01-08 10:58:19 +0800 | [diff] [blame] | 520 | |
| 521 | out_buf[0] = SDVO_I2C_OPCODE; |
| 522 | out_buf[1] = SDVO_CMD_SET_CONTROL_BUS_SWITCH; |
| 523 | cmd_buf[0] = SDVO_I2C_CMD_STATUS; |
| 524 | cmd_buf[1] = 0; |
| 525 | ret_value[0] = 0; |
| 526 | ret_value[1] = 0; |
| 527 | |
Eric Anholt | 21d40d3 | 2010-03-25 11:11:14 -0700 | [diff] [blame] | 528 | ret = i2c_transfer(intel_encoder->i2c_bus, msgs, 3); |
Zhao Yakui | 6a304ca | 2010-01-08 10:58:19 +0800 | [diff] [blame] | 529 | if (ret != 3) { |
| 530 | /* failure in I2C transfer */ |
| 531 | DRM_DEBUG_KMS("I2c transfer returned %d\n", ret); |
| 532 | return; |
| 533 | } |
| 534 | if (ret_value[0] != SDVO_CMD_STATUS_SUCCESS) { |
| 535 | DRM_DEBUG_KMS("DDC switch command returns response %d\n", |
| 536 | ret_value[0]); |
| 537 | return; |
| 538 | } |
| 539 | return; |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 540 | } |
| 541 | |
Eric Anholt | 21d40d3 | 2010-03-25 11:11:14 -0700 | [diff] [blame] | 542 | static bool intel_sdvo_set_target_input(struct intel_encoder *intel_encoder, bool target_0, bool target_1) |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 543 | { |
| 544 | struct intel_sdvo_set_target_input_args targets = {0}; |
| 545 | u8 status; |
| 546 | |
| 547 | if (target_0 && target_1) |
| 548 | return SDVO_CMD_STATUS_NOTSUPP; |
| 549 | |
| 550 | if (target_1) |
| 551 | targets.target_1 = 1; |
| 552 | |
Eric Anholt | 21d40d3 | 2010-03-25 11:11:14 -0700 | [diff] [blame] | 553 | intel_sdvo_write_cmd(intel_encoder, SDVO_CMD_SET_TARGET_INPUT, &targets, |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 554 | sizeof(targets)); |
| 555 | |
Eric Anholt | 21d40d3 | 2010-03-25 11:11:14 -0700 | [diff] [blame] | 556 | status = intel_sdvo_read_response(intel_encoder, NULL, 0); |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 557 | |
| 558 | return (status == SDVO_CMD_STATUS_SUCCESS); |
| 559 | } |
| 560 | |
| 561 | /** |
| 562 | * Return whether each input is trained. |
| 563 | * |
| 564 | * This function is making an assumption about the layout of the response, |
| 565 | * which should be checked against the docs. |
| 566 | */ |
Eric Anholt | 21d40d3 | 2010-03-25 11:11:14 -0700 | [diff] [blame] | 567 | static bool intel_sdvo_get_trained_inputs(struct intel_encoder *intel_encoder, bool *input_1, bool *input_2) |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 568 | { |
| 569 | struct intel_sdvo_get_trained_inputs_response response; |
| 570 | u8 status; |
| 571 | |
Eric Anholt | 21d40d3 | 2010-03-25 11:11:14 -0700 | [diff] [blame] | 572 | intel_sdvo_write_cmd(intel_encoder, SDVO_CMD_GET_TRAINED_INPUTS, NULL, 0); |
| 573 | status = intel_sdvo_read_response(intel_encoder, &response, sizeof(response)); |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 574 | if (status != SDVO_CMD_STATUS_SUCCESS) |
| 575 | return false; |
| 576 | |
| 577 | *input_1 = response.input0_trained; |
| 578 | *input_2 = response.input1_trained; |
| 579 | return true; |
| 580 | } |
| 581 | |
Eric Anholt | 21d40d3 | 2010-03-25 11:11:14 -0700 | [diff] [blame] | 582 | static bool intel_sdvo_set_active_outputs(struct intel_encoder *intel_encoder, |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 583 | u16 outputs) |
| 584 | { |
| 585 | u8 status; |
| 586 | |
Eric Anholt | 21d40d3 | 2010-03-25 11:11:14 -0700 | [diff] [blame] | 587 | intel_sdvo_write_cmd(intel_encoder, SDVO_CMD_SET_ACTIVE_OUTPUTS, &outputs, |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 588 | sizeof(outputs)); |
Eric Anholt | 21d40d3 | 2010-03-25 11:11:14 -0700 | [diff] [blame] | 589 | status = intel_sdvo_read_response(intel_encoder, NULL, 0); |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 590 | return (status == SDVO_CMD_STATUS_SUCCESS); |
| 591 | } |
| 592 | |
Eric Anholt | 21d40d3 | 2010-03-25 11:11:14 -0700 | [diff] [blame] | 593 | static bool intel_sdvo_set_encoder_power_state(struct intel_encoder *intel_encoder, |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 594 | int mode) |
| 595 | { |
| 596 | u8 status, state = SDVO_ENCODER_STATE_ON; |
| 597 | |
| 598 | switch (mode) { |
| 599 | case DRM_MODE_DPMS_ON: |
| 600 | state = SDVO_ENCODER_STATE_ON; |
| 601 | break; |
| 602 | case DRM_MODE_DPMS_STANDBY: |
| 603 | state = SDVO_ENCODER_STATE_STANDBY; |
| 604 | break; |
| 605 | case DRM_MODE_DPMS_SUSPEND: |
| 606 | state = SDVO_ENCODER_STATE_SUSPEND; |
| 607 | break; |
| 608 | case DRM_MODE_DPMS_OFF: |
| 609 | state = SDVO_ENCODER_STATE_OFF; |
| 610 | break; |
| 611 | } |
| 612 | |
Eric Anholt | 21d40d3 | 2010-03-25 11:11:14 -0700 | [diff] [blame] | 613 | intel_sdvo_write_cmd(intel_encoder, SDVO_CMD_SET_ENCODER_POWER_STATE, &state, |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 614 | sizeof(state)); |
Eric Anholt | 21d40d3 | 2010-03-25 11:11:14 -0700 | [diff] [blame] | 615 | status = intel_sdvo_read_response(intel_encoder, NULL, 0); |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 616 | |
| 617 | return (status == SDVO_CMD_STATUS_SUCCESS); |
| 618 | } |
| 619 | |
Eric Anholt | 21d40d3 | 2010-03-25 11:11:14 -0700 | [diff] [blame] | 620 | static bool intel_sdvo_get_input_pixel_clock_range(struct intel_encoder *intel_encoder, |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 621 | int *clock_min, |
| 622 | int *clock_max) |
| 623 | { |
| 624 | struct intel_sdvo_pixel_clock_range clocks; |
| 625 | u8 status; |
| 626 | |
Eric Anholt | 21d40d3 | 2010-03-25 11:11:14 -0700 | [diff] [blame] | 627 | intel_sdvo_write_cmd(intel_encoder, SDVO_CMD_GET_INPUT_PIXEL_CLOCK_RANGE, |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 628 | NULL, 0); |
| 629 | |
Eric Anholt | 21d40d3 | 2010-03-25 11:11:14 -0700 | [diff] [blame] | 630 | status = intel_sdvo_read_response(intel_encoder, &clocks, sizeof(clocks)); |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 631 | |
| 632 | if (status != SDVO_CMD_STATUS_SUCCESS) |
| 633 | return false; |
| 634 | |
| 635 | /* Convert the values from units of 10 kHz to kHz. */ |
| 636 | *clock_min = clocks.min * 10; |
| 637 | *clock_max = clocks.max * 10; |
| 638 | |
| 639 | return true; |
| 640 | } |
| 641 | |
Eric Anholt | 21d40d3 | 2010-03-25 11:11:14 -0700 | [diff] [blame] | 642 | static bool intel_sdvo_set_target_output(struct intel_encoder *intel_encoder, |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 643 | u16 outputs) |
| 644 | { |
| 645 | u8 status; |
| 646 | |
Eric Anholt | 21d40d3 | 2010-03-25 11:11:14 -0700 | [diff] [blame] | 647 | intel_sdvo_write_cmd(intel_encoder, SDVO_CMD_SET_TARGET_OUTPUT, &outputs, |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 648 | sizeof(outputs)); |
| 649 | |
Eric Anholt | 21d40d3 | 2010-03-25 11:11:14 -0700 | [diff] [blame] | 650 | status = intel_sdvo_read_response(intel_encoder, NULL, 0); |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 651 | return (status == SDVO_CMD_STATUS_SUCCESS); |
| 652 | } |
| 653 | |
Eric Anholt | 21d40d3 | 2010-03-25 11:11:14 -0700 | [diff] [blame] | 654 | static bool intel_sdvo_set_timing(struct intel_encoder *intel_encoder, u8 cmd, |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 655 | struct intel_sdvo_dtd *dtd) |
| 656 | { |
| 657 | u8 status; |
| 658 | |
Eric Anholt | 21d40d3 | 2010-03-25 11:11:14 -0700 | [diff] [blame] | 659 | intel_sdvo_write_cmd(intel_encoder, cmd, &dtd->part1, sizeof(dtd->part1)); |
| 660 | status = intel_sdvo_read_response(intel_encoder, NULL, 0); |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 661 | if (status != SDVO_CMD_STATUS_SUCCESS) |
| 662 | return false; |
| 663 | |
Eric Anholt | 21d40d3 | 2010-03-25 11:11:14 -0700 | [diff] [blame] | 664 | intel_sdvo_write_cmd(intel_encoder, cmd + 1, &dtd->part2, sizeof(dtd->part2)); |
| 665 | status = intel_sdvo_read_response(intel_encoder, NULL, 0); |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 666 | if (status != SDVO_CMD_STATUS_SUCCESS) |
| 667 | return false; |
| 668 | |
| 669 | return true; |
| 670 | } |
| 671 | |
Eric Anholt | 21d40d3 | 2010-03-25 11:11:14 -0700 | [diff] [blame] | 672 | static bool intel_sdvo_set_input_timing(struct intel_encoder *intel_encoder, |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 673 | struct intel_sdvo_dtd *dtd) |
| 674 | { |
Eric Anholt | 21d40d3 | 2010-03-25 11:11:14 -0700 | [diff] [blame] | 675 | return intel_sdvo_set_timing(intel_encoder, |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 676 | SDVO_CMD_SET_INPUT_TIMINGS_PART1, dtd); |
| 677 | } |
| 678 | |
Eric Anholt | 21d40d3 | 2010-03-25 11:11:14 -0700 | [diff] [blame] | 679 | static bool intel_sdvo_set_output_timing(struct intel_encoder *intel_encoder, |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 680 | struct intel_sdvo_dtd *dtd) |
| 681 | { |
Eric Anholt | 21d40d3 | 2010-03-25 11:11:14 -0700 | [diff] [blame] | 682 | return intel_sdvo_set_timing(intel_encoder, |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 683 | SDVO_CMD_SET_OUTPUT_TIMINGS_PART1, dtd); |
| 684 | } |
| 685 | |
Jesse Barnes | e2f0ba9 | 2009-02-02 15:11:52 -0800 | [diff] [blame] | 686 | static bool |
Eric Anholt | c751ce4 | 2010-03-25 11:48:48 -0700 | [diff] [blame] | 687 | intel_sdvo_create_preferred_input_timing(struct intel_encoder *intel_encoder, |
Jesse Barnes | e2f0ba9 | 2009-02-02 15:11:52 -0800 | [diff] [blame] | 688 | uint16_t clock, |
| 689 | uint16_t width, |
| 690 | uint16_t height) |
| 691 | { |
| 692 | struct intel_sdvo_preferred_input_timing_args args; |
Eric Anholt | c751ce4 | 2010-03-25 11:48:48 -0700 | [diff] [blame] | 693 | struct intel_sdvo_priv *sdvo_priv = intel_encoder->dev_priv; |
Jesse Barnes | e2f0ba9 | 2009-02-02 15:11:52 -0800 | [diff] [blame] | 694 | uint8_t status; |
| 695 | |
Zhenyu Wang | e642c6f | 2009-03-24 14:02:42 +0800 | [diff] [blame] | 696 | memset(&args, 0, sizeof(args)); |
Jesse Barnes | e2f0ba9 | 2009-02-02 15:11:52 -0800 | [diff] [blame] | 697 | args.clock = clock; |
| 698 | args.width = width; |
| 699 | args.height = height; |
Zhenyu Wang | e642c6f | 2009-03-24 14:02:42 +0800 | [diff] [blame] | 700 | args.interlace = 0; |
ling.ma@intel.com | 12682a9 | 2009-06-30 11:35:35 +0800 | [diff] [blame] | 701 | |
| 702 | if (sdvo_priv->is_lvds && |
| 703 | (sdvo_priv->sdvo_lvds_fixed_mode->hdisplay != width || |
| 704 | sdvo_priv->sdvo_lvds_fixed_mode->vdisplay != height)) |
| 705 | args.scaled = 1; |
| 706 | |
Eric Anholt | c751ce4 | 2010-03-25 11:48:48 -0700 | [diff] [blame] | 707 | intel_sdvo_write_cmd(intel_encoder, |
| 708 | SDVO_CMD_CREATE_PREFERRED_INPUT_TIMING, |
Jesse Barnes | e2f0ba9 | 2009-02-02 15:11:52 -0800 | [diff] [blame] | 709 | &args, sizeof(args)); |
Eric Anholt | c751ce4 | 2010-03-25 11:48:48 -0700 | [diff] [blame] | 710 | status = intel_sdvo_read_response(intel_encoder, NULL, 0); |
Jesse Barnes | e2f0ba9 | 2009-02-02 15:11:52 -0800 | [diff] [blame] | 711 | if (status != SDVO_CMD_STATUS_SUCCESS) |
| 712 | return false; |
| 713 | |
| 714 | return true; |
| 715 | } |
| 716 | |
Eric Anholt | c751ce4 | 2010-03-25 11:48:48 -0700 | [diff] [blame] | 717 | static bool intel_sdvo_get_preferred_input_timing(struct intel_encoder *intel_encoder, |
Jesse Barnes | e2f0ba9 | 2009-02-02 15:11:52 -0800 | [diff] [blame] | 718 | struct intel_sdvo_dtd *dtd) |
| 719 | { |
| 720 | bool status; |
| 721 | |
Eric Anholt | c751ce4 | 2010-03-25 11:48:48 -0700 | [diff] [blame] | 722 | intel_sdvo_write_cmd(intel_encoder, SDVO_CMD_GET_PREFERRED_INPUT_TIMING_PART1, |
Jesse Barnes | e2f0ba9 | 2009-02-02 15:11:52 -0800 | [diff] [blame] | 723 | NULL, 0); |
| 724 | |
Eric Anholt | c751ce4 | 2010-03-25 11:48:48 -0700 | [diff] [blame] | 725 | status = intel_sdvo_read_response(intel_encoder, &dtd->part1, |
Jesse Barnes | e2f0ba9 | 2009-02-02 15:11:52 -0800 | [diff] [blame] | 726 | sizeof(dtd->part1)); |
| 727 | if (status != SDVO_CMD_STATUS_SUCCESS) |
| 728 | return false; |
| 729 | |
Eric Anholt | c751ce4 | 2010-03-25 11:48:48 -0700 | [diff] [blame] | 730 | intel_sdvo_write_cmd(intel_encoder, SDVO_CMD_GET_PREFERRED_INPUT_TIMING_PART2, |
Jesse Barnes | e2f0ba9 | 2009-02-02 15:11:52 -0800 | [diff] [blame] | 731 | NULL, 0); |
| 732 | |
Eric Anholt | c751ce4 | 2010-03-25 11:48:48 -0700 | [diff] [blame] | 733 | status = intel_sdvo_read_response(intel_encoder, &dtd->part2, |
Jesse Barnes | e2f0ba9 | 2009-02-02 15:11:52 -0800 | [diff] [blame] | 734 | sizeof(dtd->part2)); |
| 735 | if (status != SDVO_CMD_STATUS_SUCCESS) |
| 736 | return false; |
| 737 | |
| 738 | return false; |
| 739 | } |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 740 | |
Eric Anholt | 21d40d3 | 2010-03-25 11:11:14 -0700 | [diff] [blame] | 741 | static bool intel_sdvo_set_clock_rate_mult(struct intel_encoder *intel_encoder, u8 val) |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 742 | { |
| 743 | u8 status; |
| 744 | |
Eric Anholt | 21d40d3 | 2010-03-25 11:11:14 -0700 | [diff] [blame] | 745 | intel_sdvo_write_cmd(intel_encoder, SDVO_CMD_SET_CLOCK_RATE_MULT, &val, 1); |
| 746 | status = intel_sdvo_read_response(intel_encoder, NULL, 0); |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 747 | if (status != SDVO_CMD_STATUS_SUCCESS) |
| 748 | return false; |
| 749 | |
| 750 | return true; |
| 751 | } |
| 752 | |
Jesse Barnes | e2f0ba9 | 2009-02-02 15:11:52 -0800 | [diff] [blame] | 753 | static void intel_sdvo_get_dtd_from_mode(struct intel_sdvo_dtd *dtd, |
| 754 | struct drm_display_mode *mode) |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 755 | { |
Jesse Barnes | e2f0ba9 | 2009-02-02 15:11:52 -0800 | [diff] [blame] | 756 | uint16_t width, height; |
| 757 | uint16_t h_blank_len, h_sync_len, v_blank_len, v_sync_len; |
| 758 | uint16_t h_sync_offset, v_sync_offset; |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 759 | |
| 760 | width = mode->crtc_hdisplay; |
| 761 | height = mode->crtc_vdisplay; |
| 762 | |
| 763 | /* do some mode translations */ |
| 764 | h_blank_len = mode->crtc_hblank_end - mode->crtc_hblank_start; |
| 765 | h_sync_len = mode->crtc_hsync_end - mode->crtc_hsync_start; |
| 766 | |
| 767 | v_blank_len = mode->crtc_vblank_end - mode->crtc_vblank_start; |
| 768 | v_sync_len = mode->crtc_vsync_end - mode->crtc_vsync_start; |
| 769 | |
| 770 | h_sync_offset = mode->crtc_hsync_start - mode->crtc_hblank_start; |
| 771 | v_sync_offset = mode->crtc_vsync_start - mode->crtc_vblank_start; |
| 772 | |
Jesse Barnes | e2f0ba9 | 2009-02-02 15:11:52 -0800 | [diff] [blame] | 773 | dtd->part1.clock = mode->clock / 10; |
| 774 | dtd->part1.h_active = width & 0xff; |
| 775 | dtd->part1.h_blank = h_blank_len & 0xff; |
| 776 | dtd->part1.h_high = (((width >> 8) & 0xf) << 4) | |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 777 | ((h_blank_len >> 8) & 0xf); |
Jesse Barnes | e2f0ba9 | 2009-02-02 15:11:52 -0800 | [diff] [blame] | 778 | dtd->part1.v_active = height & 0xff; |
| 779 | dtd->part1.v_blank = v_blank_len & 0xff; |
| 780 | dtd->part1.v_high = (((height >> 8) & 0xf) << 4) | |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 781 | ((v_blank_len >> 8) & 0xf); |
| 782 | |
Zhenyu Wang | 171a9e9 | 2009-03-24 14:02:41 +0800 | [diff] [blame] | 783 | dtd->part2.h_sync_off = h_sync_offset & 0xff; |
Jesse Barnes | e2f0ba9 | 2009-02-02 15:11:52 -0800 | [diff] [blame] | 784 | dtd->part2.h_sync_width = h_sync_len & 0xff; |
| 785 | dtd->part2.v_sync_off_width = (v_sync_offset & 0xf) << 4 | |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 786 | (v_sync_len & 0xf); |
Jesse Barnes | e2f0ba9 | 2009-02-02 15:11:52 -0800 | [diff] [blame] | 787 | dtd->part2.sync_off_width_high = ((h_sync_offset & 0x300) >> 2) | |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 788 | ((h_sync_len & 0x300) >> 4) | ((v_sync_offset & 0x30) >> 2) | |
| 789 | ((v_sync_len & 0x30) >> 4); |
| 790 | |
Jesse Barnes | e2f0ba9 | 2009-02-02 15:11:52 -0800 | [diff] [blame] | 791 | dtd->part2.dtd_flags = 0x18; |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 792 | if (mode->flags & DRM_MODE_FLAG_PHSYNC) |
Jesse Barnes | e2f0ba9 | 2009-02-02 15:11:52 -0800 | [diff] [blame] | 793 | dtd->part2.dtd_flags |= 0x2; |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 794 | if (mode->flags & DRM_MODE_FLAG_PVSYNC) |
Jesse Barnes | e2f0ba9 | 2009-02-02 15:11:52 -0800 | [diff] [blame] | 795 | dtd->part2.dtd_flags |= 0x4; |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 796 | |
Jesse Barnes | e2f0ba9 | 2009-02-02 15:11:52 -0800 | [diff] [blame] | 797 | dtd->part2.sdvo_flags = 0; |
| 798 | dtd->part2.v_sync_off_high = v_sync_offset & 0xc0; |
| 799 | dtd->part2.reserved = 0; |
| 800 | } |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 801 | |
Jesse Barnes | e2f0ba9 | 2009-02-02 15:11:52 -0800 | [diff] [blame] | 802 | static void intel_sdvo_get_mode_from_dtd(struct drm_display_mode * mode, |
| 803 | struct intel_sdvo_dtd *dtd) |
| 804 | { |
Jesse Barnes | e2f0ba9 | 2009-02-02 15:11:52 -0800 | [diff] [blame] | 805 | mode->hdisplay = dtd->part1.h_active; |
| 806 | mode->hdisplay += ((dtd->part1.h_high >> 4) & 0x0f) << 8; |
| 807 | mode->hsync_start = mode->hdisplay + dtd->part2.h_sync_off; |
Zhenyu Wang | 171a9e9 | 2009-03-24 14:02:41 +0800 | [diff] [blame] | 808 | mode->hsync_start += (dtd->part2.sync_off_width_high & 0xc0) << 2; |
Jesse Barnes | e2f0ba9 | 2009-02-02 15:11:52 -0800 | [diff] [blame] | 809 | mode->hsync_end = mode->hsync_start + dtd->part2.h_sync_width; |
| 810 | mode->hsync_end += (dtd->part2.sync_off_width_high & 0x30) << 4; |
| 811 | mode->htotal = mode->hdisplay + dtd->part1.h_blank; |
| 812 | mode->htotal += (dtd->part1.h_high & 0xf) << 8; |
| 813 | |
| 814 | mode->vdisplay = dtd->part1.v_active; |
| 815 | mode->vdisplay += ((dtd->part1.v_high >> 4) & 0x0f) << 8; |
| 816 | mode->vsync_start = mode->vdisplay; |
| 817 | mode->vsync_start += (dtd->part2.v_sync_off_width >> 4) & 0xf; |
Zhenyu Wang | 171a9e9 | 2009-03-24 14:02:41 +0800 | [diff] [blame] | 818 | mode->vsync_start += (dtd->part2.sync_off_width_high & 0x0c) << 2; |
Jesse Barnes | e2f0ba9 | 2009-02-02 15:11:52 -0800 | [diff] [blame] | 819 | mode->vsync_start += dtd->part2.v_sync_off_high & 0xc0; |
| 820 | mode->vsync_end = mode->vsync_start + |
| 821 | (dtd->part2.v_sync_off_width & 0xf); |
| 822 | mode->vsync_end += (dtd->part2.sync_off_width_high & 0x3) << 4; |
| 823 | mode->vtotal = mode->vdisplay + dtd->part1.v_blank; |
| 824 | mode->vtotal += (dtd->part1.v_high & 0xf) << 8; |
| 825 | |
| 826 | mode->clock = dtd->part1.clock * 10; |
| 827 | |
Zhenyu Wang | 171a9e9 | 2009-03-24 14:02:41 +0800 | [diff] [blame] | 828 | mode->flags &= ~(DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC); |
Jesse Barnes | e2f0ba9 | 2009-02-02 15:11:52 -0800 | [diff] [blame] | 829 | if (dtd->part2.dtd_flags & 0x2) |
| 830 | mode->flags |= DRM_MODE_FLAG_PHSYNC; |
| 831 | if (dtd->part2.dtd_flags & 0x4) |
| 832 | mode->flags |= DRM_MODE_FLAG_PVSYNC; |
| 833 | } |
| 834 | |
Eric Anholt | c751ce4 | 2010-03-25 11:48:48 -0700 | [diff] [blame] | 835 | static bool intel_sdvo_get_supp_encode(struct intel_encoder *intel_encoder, |
Jesse Barnes | e2f0ba9 | 2009-02-02 15:11:52 -0800 | [diff] [blame] | 836 | struct intel_sdvo_encode *encode) |
| 837 | { |
| 838 | uint8_t status; |
| 839 | |
Eric Anholt | c751ce4 | 2010-03-25 11:48:48 -0700 | [diff] [blame] | 840 | intel_sdvo_write_cmd(intel_encoder, SDVO_CMD_GET_SUPP_ENCODE, NULL, 0); |
| 841 | status = intel_sdvo_read_response(intel_encoder, encode, sizeof(*encode)); |
Jesse Barnes | e2f0ba9 | 2009-02-02 15:11:52 -0800 | [diff] [blame] | 842 | if (status != SDVO_CMD_STATUS_SUCCESS) { /* non-support means DVI */ |
| 843 | memset(encode, 0, sizeof(*encode)); |
| 844 | return false; |
| 845 | } |
| 846 | |
| 847 | return true; |
| 848 | } |
| 849 | |
Eric Anholt | c751ce4 | 2010-03-25 11:48:48 -0700 | [diff] [blame] | 850 | static bool intel_sdvo_set_encode(struct intel_encoder *intel_encoder, |
| 851 | uint8_t mode) |
Jesse Barnes | e2f0ba9 | 2009-02-02 15:11:52 -0800 | [diff] [blame] | 852 | { |
| 853 | uint8_t status; |
| 854 | |
Eric Anholt | c751ce4 | 2010-03-25 11:48:48 -0700 | [diff] [blame] | 855 | intel_sdvo_write_cmd(intel_encoder, SDVO_CMD_SET_ENCODE, &mode, 1); |
| 856 | status = intel_sdvo_read_response(intel_encoder, NULL, 0); |
Jesse Barnes | e2f0ba9 | 2009-02-02 15:11:52 -0800 | [diff] [blame] | 857 | |
| 858 | return (status == SDVO_CMD_STATUS_SUCCESS); |
| 859 | } |
| 860 | |
Eric Anholt | c751ce4 | 2010-03-25 11:48:48 -0700 | [diff] [blame] | 861 | static bool intel_sdvo_set_colorimetry(struct intel_encoder *intel_encoder, |
Jesse Barnes | e2f0ba9 | 2009-02-02 15:11:52 -0800 | [diff] [blame] | 862 | uint8_t mode) |
| 863 | { |
| 864 | uint8_t status; |
| 865 | |
Eric Anholt | c751ce4 | 2010-03-25 11:48:48 -0700 | [diff] [blame] | 866 | intel_sdvo_write_cmd(intel_encoder, SDVO_CMD_SET_COLORIMETRY, &mode, 1); |
| 867 | status = intel_sdvo_read_response(intel_encoder, NULL, 0); |
Jesse Barnes | e2f0ba9 | 2009-02-02 15:11:52 -0800 | [diff] [blame] | 868 | |
| 869 | return (status == SDVO_CMD_STATUS_SUCCESS); |
| 870 | } |
| 871 | |
| 872 | #if 0 |
Eric Anholt | c751ce4 | 2010-03-25 11:48:48 -0700 | [diff] [blame] | 873 | static void intel_sdvo_dump_hdmi_buf(struct intel_encoder *intel_encoder) |
Jesse Barnes | e2f0ba9 | 2009-02-02 15:11:52 -0800 | [diff] [blame] | 874 | { |
| 875 | int i, j; |
| 876 | uint8_t set_buf_index[2]; |
| 877 | uint8_t av_split; |
| 878 | uint8_t buf_size; |
| 879 | uint8_t buf[48]; |
| 880 | uint8_t *pos; |
| 881 | |
Eric Anholt | c751ce4 | 2010-03-25 11:48:48 -0700 | [diff] [blame] | 882 | intel_sdvo_write_cmd(encoder, SDVO_CMD_GET_HBUF_AV_SPLIT, NULL, 0); |
| 883 | intel_sdvo_read_response(encoder, &av_split, 1); |
Jesse Barnes | e2f0ba9 | 2009-02-02 15:11:52 -0800 | [diff] [blame] | 884 | |
| 885 | for (i = 0; i <= av_split; i++) { |
| 886 | set_buf_index[0] = i; set_buf_index[1] = 0; |
Eric Anholt | c751ce4 | 2010-03-25 11:48:48 -0700 | [diff] [blame] | 887 | intel_sdvo_write_cmd(encoder, SDVO_CMD_SET_HBUF_INDEX, |
Jesse Barnes | e2f0ba9 | 2009-02-02 15:11:52 -0800 | [diff] [blame] | 888 | set_buf_index, 2); |
Eric Anholt | c751ce4 | 2010-03-25 11:48:48 -0700 | [diff] [blame] | 889 | intel_sdvo_write_cmd(encoder, SDVO_CMD_GET_HBUF_INFO, NULL, 0); |
| 890 | intel_sdvo_read_response(encoder, &buf_size, 1); |
Jesse Barnes | e2f0ba9 | 2009-02-02 15:11:52 -0800 | [diff] [blame] | 891 | |
| 892 | pos = buf; |
| 893 | for (j = 0; j <= buf_size; j += 8) { |
Eric Anholt | c751ce4 | 2010-03-25 11:48:48 -0700 | [diff] [blame] | 894 | intel_sdvo_write_cmd(encoder, SDVO_CMD_GET_HBUF_DATA, |
Jesse Barnes | e2f0ba9 | 2009-02-02 15:11:52 -0800 | [diff] [blame] | 895 | NULL, 0); |
Eric Anholt | c751ce4 | 2010-03-25 11:48:48 -0700 | [diff] [blame] | 896 | intel_sdvo_read_response(encoder, pos, 8); |
Jesse Barnes | e2f0ba9 | 2009-02-02 15:11:52 -0800 | [diff] [blame] | 897 | pos += 8; |
| 898 | } |
| 899 | } |
| 900 | } |
| 901 | #endif |
| 902 | |
Eric Anholt | c751ce4 | 2010-03-25 11:48:48 -0700 | [diff] [blame] | 903 | static void intel_sdvo_set_hdmi_buf(struct intel_encoder *intel_encoder, |
| 904 | int index, |
| 905 | uint8_t *data, int8_t size, uint8_t tx_rate) |
Jesse Barnes | e2f0ba9 | 2009-02-02 15:11:52 -0800 | [diff] [blame] | 906 | { |
| 907 | uint8_t set_buf_index[2]; |
| 908 | |
| 909 | set_buf_index[0] = index; |
| 910 | set_buf_index[1] = 0; |
| 911 | |
Eric Anholt | c751ce4 | 2010-03-25 11:48:48 -0700 | [diff] [blame] | 912 | intel_sdvo_write_cmd(intel_encoder, SDVO_CMD_SET_HBUF_INDEX, |
| 913 | set_buf_index, 2); |
Jesse Barnes | e2f0ba9 | 2009-02-02 15:11:52 -0800 | [diff] [blame] | 914 | |
| 915 | for (; size > 0; size -= 8) { |
Eric Anholt | c751ce4 | 2010-03-25 11:48:48 -0700 | [diff] [blame] | 916 | intel_sdvo_write_cmd(intel_encoder, SDVO_CMD_SET_HBUF_DATA, data, 8); |
Jesse Barnes | e2f0ba9 | 2009-02-02 15:11:52 -0800 | [diff] [blame] | 917 | data += 8; |
| 918 | } |
| 919 | |
Eric Anholt | c751ce4 | 2010-03-25 11:48:48 -0700 | [diff] [blame] | 920 | intel_sdvo_write_cmd(intel_encoder, SDVO_CMD_SET_HBUF_TXRATE, &tx_rate, 1); |
Jesse Barnes | e2f0ba9 | 2009-02-02 15:11:52 -0800 | [diff] [blame] | 921 | } |
| 922 | |
| 923 | static uint8_t intel_sdvo_calc_hbuf_csum(uint8_t *data, uint8_t size) |
| 924 | { |
| 925 | uint8_t csum = 0; |
| 926 | int i; |
| 927 | |
| 928 | for (i = 0; i < size; i++) |
| 929 | csum += data[i]; |
| 930 | |
| 931 | return 0x100 - csum; |
| 932 | } |
| 933 | |
| 934 | #define DIP_TYPE_AVI 0x82 |
| 935 | #define DIP_VERSION_AVI 0x2 |
| 936 | #define DIP_LEN_AVI 13 |
| 937 | |
| 938 | struct dip_infoframe { |
| 939 | uint8_t type; |
| 940 | uint8_t version; |
| 941 | uint8_t len; |
| 942 | uint8_t checksum; |
| 943 | union { |
| 944 | struct { |
| 945 | /* Packet Byte #1 */ |
| 946 | uint8_t S:2; |
| 947 | uint8_t B:2; |
| 948 | uint8_t A:1; |
| 949 | uint8_t Y:2; |
| 950 | uint8_t rsvd1:1; |
| 951 | /* Packet Byte #2 */ |
| 952 | uint8_t R:4; |
| 953 | uint8_t M:2; |
| 954 | uint8_t C:2; |
| 955 | /* Packet Byte #3 */ |
| 956 | uint8_t SC:2; |
| 957 | uint8_t Q:2; |
| 958 | uint8_t EC:3; |
| 959 | uint8_t ITC:1; |
| 960 | /* Packet Byte #4 */ |
| 961 | uint8_t VIC:7; |
| 962 | uint8_t rsvd2:1; |
| 963 | /* Packet Byte #5 */ |
| 964 | uint8_t PR:4; |
| 965 | uint8_t rsvd3:4; |
| 966 | /* Packet Byte #6~13 */ |
| 967 | uint16_t top_bar_end; |
| 968 | uint16_t bottom_bar_start; |
| 969 | uint16_t left_bar_end; |
| 970 | uint16_t right_bar_start; |
| 971 | } avi; |
| 972 | struct { |
| 973 | /* Packet Byte #1 */ |
| 974 | uint8_t channel_count:3; |
| 975 | uint8_t rsvd1:1; |
| 976 | uint8_t coding_type:4; |
| 977 | /* Packet Byte #2 */ |
| 978 | uint8_t sample_size:2; /* SS0, SS1 */ |
| 979 | uint8_t sample_frequency:3; |
| 980 | uint8_t rsvd2:3; |
| 981 | /* Packet Byte #3 */ |
| 982 | uint8_t coding_type_private:5; |
| 983 | uint8_t rsvd3:3; |
| 984 | /* Packet Byte #4 */ |
| 985 | uint8_t channel_allocation; |
| 986 | /* Packet Byte #5 */ |
| 987 | uint8_t rsvd4:3; |
| 988 | uint8_t level_shift:4; |
| 989 | uint8_t downmix_inhibit:1; |
| 990 | } audio; |
| 991 | uint8_t payload[28]; |
| 992 | } __attribute__ ((packed)) u; |
| 993 | } __attribute__((packed)); |
| 994 | |
Eric Anholt | c751ce4 | 2010-03-25 11:48:48 -0700 | [diff] [blame] | 995 | static void intel_sdvo_set_avi_infoframe(struct intel_encoder *intel_encoder, |
Jesse Barnes | e2f0ba9 | 2009-02-02 15:11:52 -0800 | [diff] [blame] | 996 | struct drm_display_mode * mode) |
| 997 | { |
| 998 | struct dip_infoframe avi_if = { |
| 999 | .type = DIP_TYPE_AVI, |
| 1000 | .version = DIP_VERSION_AVI, |
| 1001 | .len = DIP_LEN_AVI, |
| 1002 | }; |
| 1003 | |
| 1004 | avi_if.checksum = intel_sdvo_calc_hbuf_csum((uint8_t *)&avi_if, |
| 1005 | 4 + avi_if.len); |
Eric Anholt | c751ce4 | 2010-03-25 11:48:48 -0700 | [diff] [blame] | 1006 | intel_sdvo_set_hdmi_buf(intel_encoder, 1, (uint8_t *)&avi_if, |
| 1007 | 4 + avi_if.len, |
Jesse Barnes | e2f0ba9 | 2009-02-02 15:11:52 -0800 | [diff] [blame] | 1008 | SDVO_HBUF_TX_VSYNC); |
| 1009 | } |
| 1010 | |
Eric Anholt | c751ce4 | 2010-03-25 11:48:48 -0700 | [diff] [blame] | 1011 | static void intel_sdvo_set_tv_format(struct intel_encoder *intel_encoder) |
Zhenyu Wang | 7026d4a | 2009-03-24 14:02:43 +0800 | [diff] [blame] | 1012 | { |
Zhenyu Wang | 7026d4a | 2009-03-24 14:02:43 +0800 | [diff] [blame] | 1013 | |
Zhao Yakui | ce6feab | 2009-08-24 13:50:26 +0800 | [diff] [blame] | 1014 | struct intel_sdvo_tv_format format; |
Eric Anholt | c751ce4 | 2010-03-25 11:48:48 -0700 | [diff] [blame] | 1015 | struct intel_sdvo_priv *sdvo_priv = intel_encoder->dev_priv; |
Zhao Yakui | ce6feab | 2009-08-24 13:50:26 +0800 | [diff] [blame] | 1016 | uint32_t format_map, i; |
| 1017 | uint8_t status; |
| 1018 | |
| 1019 | for (i = 0; i < TV_FORMAT_NUM; i++) |
| 1020 | if (tv_format_names[i] == sdvo_priv->tv_format_name) |
| 1021 | break; |
| 1022 | |
| 1023 | format_map = 1 << i; |
| 1024 | memset(&format, 0, sizeof(format)); |
| 1025 | memcpy(&format, &format_map, sizeof(format_map) > sizeof(format) ? |
| 1026 | sizeof(format) : sizeof(format_map)); |
| 1027 | |
Eric Anholt | c751ce4 | 2010-03-25 11:48:48 -0700 | [diff] [blame] | 1028 | intel_sdvo_write_cmd(intel_encoder, SDVO_CMD_SET_TV_FORMAT, &format_map, |
Zhao Yakui | ce6feab | 2009-08-24 13:50:26 +0800 | [diff] [blame] | 1029 | sizeof(format)); |
| 1030 | |
Eric Anholt | c751ce4 | 2010-03-25 11:48:48 -0700 | [diff] [blame] | 1031 | status = intel_sdvo_read_response(intel_encoder, NULL, 0); |
Zhao Yakui | ce6feab | 2009-08-24 13:50:26 +0800 | [diff] [blame] | 1032 | if (status != SDVO_CMD_STATUS_SUCCESS) |
Zhao Yakui | b9219c5 | 2009-09-10 15:45:46 +0800 | [diff] [blame] | 1033 | DRM_DEBUG_KMS("%s: Failed to set TV format\n", |
Zhao Yakui | ce6feab | 2009-08-24 13:50:26 +0800 | [diff] [blame] | 1034 | SDVO_NAME(sdvo_priv)); |
Zhenyu Wang | 7026d4a | 2009-03-24 14:02:43 +0800 | [diff] [blame] | 1035 | } |
| 1036 | |
Jesse Barnes | e2f0ba9 | 2009-02-02 15:11:52 -0800 | [diff] [blame] | 1037 | static bool intel_sdvo_mode_fixup(struct drm_encoder *encoder, |
| 1038 | struct drm_display_mode *mode, |
| 1039 | struct drm_display_mode *adjusted_mode) |
| 1040 | { |
Eric Anholt | c751ce4 | 2010-03-25 11:48:48 -0700 | [diff] [blame] | 1041 | struct intel_encoder *intel_encoder = enc_to_intel_encoder(encoder); |
| 1042 | struct intel_sdvo_priv *dev_priv = intel_encoder->dev_priv; |
Jesse Barnes | e2f0ba9 | 2009-02-02 15:11:52 -0800 | [diff] [blame] | 1043 | |
ling.ma@intel.com | 12682a9 | 2009-06-30 11:35:35 +0800 | [diff] [blame] | 1044 | if (dev_priv->is_tv) { |
Jesse Barnes | e2f0ba9 | 2009-02-02 15:11:52 -0800 | [diff] [blame] | 1045 | struct intel_sdvo_dtd output_dtd; |
| 1046 | bool success; |
| 1047 | |
| 1048 | /* We need to construct preferred input timings based on our |
| 1049 | * output timings. To do that, we have to set the output |
| 1050 | * timings, even though this isn't really the right place in |
| 1051 | * the sequence to do it. Oh well. |
| 1052 | */ |
| 1053 | |
| 1054 | |
| 1055 | /* Set output timings */ |
| 1056 | intel_sdvo_get_dtd_from_mode(&output_dtd, mode); |
Eric Anholt | c751ce4 | 2010-03-25 11:48:48 -0700 | [diff] [blame] | 1057 | intel_sdvo_set_target_output(intel_encoder, |
Zhenyu Wang | 14571b4 | 2010-03-30 14:06:33 +0800 | [diff] [blame] | 1058 | dev_priv->attached_output); |
Eric Anholt | c751ce4 | 2010-03-25 11:48:48 -0700 | [diff] [blame] | 1059 | intel_sdvo_set_output_timing(intel_encoder, &output_dtd); |
Jesse Barnes | e2f0ba9 | 2009-02-02 15:11:52 -0800 | [diff] [blame] | 1060 | |
| 1061 | /* Set the input timing to the screen. Assume always input 0. */ |
Eric Anholt | c751ce4 | 2010-03-25 11:48:48 -0700 | [diff] [blame] | 1062 | intel_sdvo_set_target_input(intel_encoder, true, false); |
Jesse Barnes | e2f0ba9 | 2009-02-02 15:11:52 -0800 | [diff] [blame] | 1063 | |
| 1064 | |
Eric Anholt | c751ce4 | 2010-03-25 11:48:48 -0700 | [diff] [blame] | 1065 | success = intel_sdvo_create_preferred_input_timing(intel_encoder, |
Jesse Barnes | e2f0ba9 | 2009-02-02 15:11:52 -0800 | [diff] [blame] | 1066 | mode->clock / 10, |
| 1067 | mode->hdisplay, |
| 1068 | mode->vdisplay); |
| 1069 | if (success) { |
| 1070 | struct intel_sdvo_dtd input_dtd; |
| 1071 | |
Eric Anholt | c751ce4 | 2010-03-25 11:48:48 -0700 | [diff] [blame] | 1072 | intel_sdvo_get_preferred_input_timing(intel_encoder, |
Jesse Barnes | e2f0ba9 | 2009-02-02 15:11:52 -0800 | [diff] [blame] | 1073 | &input_dtd); |
| 1074 | intel_sdvo_get_mode_from_dtd(adjusted_mode, &input_dtd); |
ling.ma@intel.com | 12682a9 | 2009-06-30 11:35:35 +0800 | [diff] [blame] | 1075 | dev_priv->sdvo_flags = input_dtd.part2.sdvo_flags; |
Jesse Barnes | e2f0ba9 | 2009-02-02 15:11:52 -0800 | [diff] [blame] | 1076 | |
Zhenyu Wang | 7026d4a | 2009-03-24 14:02:43 +0800 | [diff] [blame] | 1077 | drm_mode_set_crtcinfo(adjusted_mode, 0); |
| 1078 | |
| 1079 | mode->clock = adjusted_mode->clock; |
| 1080 | |
| 1081 | adjusted_mode->clock *= |
| 1082 | intel_sdvo_get_pixel_multiplier(mode); |
Jesse Barnes | e2f0ba9 | 2009-02-02 15:11:52 -0800 | [diff] [blame] | 1083 | } else { |
| 1084 | return false; |
| 1085 | } |
ling.ma@intel.com | 12682a9 | 2009-06-30 11:35:35 +0800 | [diff] [blame] | 1086 | } else if (dev_priv->is_lvds) { |
| 1087 | struct intel_sdvo_dtd output_dtd; |
| 1088 | bool success; |
| 1089 | |
| 1090 | drm_mode_set_crtcinfo(dev_priv->sdvo_lvds_fixed_mode, 0); |
| 1091 | /* Set output timings */ |
| 1092 | intel_sdvo_get_dtd_from_mode(&output_dtd, |
| 1093 | dev_priv->sdvo_lvds_fixed_mode); |
| 1094 | |
Eric Anholt | c751ce4 | 2010-03-25 11:48:48 -0700 | [diff] [blame] | 1095 | intel_sdvo_set_target_output(intel_encoder, |
Zhenyu Wang | 14571b4 | 2010-03-30 14:06:33 +0800 | [diff] [blame] | 1096 | dev_priv->attached_output); |
Eric Anholt | c751ce4 | 2010-03-25 11:48:48 -0700 | [diff] [blame] | 1097 | intel_sdvo_set_output_timing(intel_encoder, &output_dtd); |
ling.ma@intel.com | 12682a9 | 2009-06-30 11:35:35 +0800 | [diff] [blame] | 1098 | |
| 1099 | /* Set the input timing to the screen. Assume always input 0. */ |
Eric Anholt | c751ce4 | 2010-03-25 11:48:48 -0700 | [diff] [blame] | 1100 | intel_sdvo_set_target_input(intel_encoder, true, false); |
ling.ma@intel.com | 12682a9 | 2009-06-30 11:35:35 +0800 | [diff] [blame] | 1101 | |
| 1102 | |
| 1103 | success = intel_sdvo_create_preferred_input_timing( |
Eric Anholt | c751ce4 | 2010-03-25 11:48:48 -0700 | [diff] [blame] | 1104 | intel_encoder, |
ling.ma@intel.com | 12682a9 | 2009-06-30 11:35:35 +0800 | [diff] [blame] | 1105 | mode->clock / 10, |
| 1106 | mode->hdisplay, |
| 1107 | mode->vdisplay); |
| 1108 | |
| 1109 | if (success) { |
| 1110 | struct intel_sdvo_dtd input_dtd; |
| 1111 | |
Eric Anholt | c751ce4 | 2010-03-25 11:48:48 -0700 | [diff] [blame] | 1112 | intel_sdvo_get_preferred_input_timing(intel_encoder, |
ling.ma@intel.com | 12682a9 | 2009-06-30 11:35:35 +0800 | [diff] [blame] | 1113 | &input_dtd); |
| 1114 | intel_sdvo_get_mode_from_dtd(adjusted_mode, &input_dtd); |
| 1115 | dev_priv->sdvo_flags = input_dtd.part2.sdvo_flags; |
| 1116 | |
| 1117 | drm_mode_set_crtcinfo(adjusted_mode, 0); |
| 1118 | |
| 1119 | mode->clock = adjusted_mode->clock; |
| 1120 | |
| 1121 | adjusted_mode->clock *= |
| 1122 | intel_sdvo_get_pixel_multiplier(mode); |
| 1123 | } else { |
| 1124 | return false; |
| 1125 | } |
| 1126 | |
| 1127 | } else { |
| 1128 | /* Make the CRTC code factor in the SDVO pixel multiplier. The |
| 1129 | * SDVO device will be told of the multiplier during mode_set. |
| 1130 | */ |
| 1131 | adjusted_mode->clock *= intel_sdvo_get_pixel_multiplier(mode); |
Jesse Barnes | e2f0ba9 | 2009-02-02 15:11:52 -0800 | [diff] [blame] | 1132 | } |
| 1133 | return true; |
| 1134 | } |
| 1135 | |
| 1136 | static void intel_sdvo_mode_set(struct drm_encoder *encoder, |
| 1137 | struct drm_display_mode *mode, |
| 1138 | struct drm_display_mode *adjusted_mode) |
| 1139 | { |
| 1140 | struct drm_device *dev = encoder->dev; |
| 1141 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 1142 | struct drm_crtc *crtc = encoder->crtc; |
| 1143 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
Eric Anholt | c751ce4 | 2010-03-25 11:48:48 -0700 | [diff] [blame] | 1144 | struct intel_encoder *intel_encoder = enc_to_intel_encoder(encoder); |
| 1145 | struct intel_sdvo_priv *sdvo_priv = intel_encoder->dev_priv; |
Jesse Barnes | e2f0ba9 | 2009-02-02 15:11:52 -0800 | [diff] [blame] | 1146 | u32 sdvox = 0; |
| 1147 | int sdvo_pixel_multiply; |
| 1148 | struct intel_sdvo_in_out_map in_out; |
| 1149 | struct intel_sdvo_dtd input_dtd; |
| 1150 | u8 status; |
| 1151 | |
| 1152 | if (!mode) |
| 1153 | return; |
| 1154 | |
| 1155 | /* First, set the input mapping for the first input to our controlled |
| 1156 | * output. This is only correct if we're a single-input device, in |
| 1157 | * which case the first input is the output from the appropriate SDVO |
| 1158 | * channel on the motherboard. In a two-input device, the first input |
| 1159 | * will be SDVOB and the second SDVOC. |
| 1160 | */ |
Zhenyu Wang | 14571b4 | 2010-03-30 14:06:33 +0800 | [diff] [blame] | 1161 | in_out.in0 = sdvo_priv->attached_output; |
Jesse Barnes | e2f0ba9 | 2009-02-02 15:11:52 -0800 | [diff] [blame] | 1162 | in_out.in1 = 0; |
| 1163 | |
Eric Anholt | c751ce4 | 2010-03-25 11:48:48 -0700 | [diff] [blame] | 1164 | intel_sdvo_write_cmd(intel_encoder, SDVO_CMD_SET_IN_OUT_MAP, |
Jesse Barnes | e2f0ba9 | 2009-02-02 15:11:52 -0800 | [diff] [blame] | 1165 | &in_out, sizeof(in_out)); |
Eric Anholt | c751ce4 | 2010-03-25 11:48:48 -0700 | [diff] [blame] | 1166 | status = intel_sdvo_read_response(intel_encoder, NULL, 0); |
Jesse Barnes | e2f0ba9 | 2009-02-02 15:11:52 -0800 | [diff] [blame] | 1167 | |
| 1168 | if (sdvo_priv->is_hdmi) { |
Eric Anholt | c751ce4 | 2010-03-25 11:48:48 -0700 | [diff] [blame] | 1169 | intel_sdvo_set_avi_infoframe(intel_encoder, mode); |
Jesse Barnes | e2f0ba9 | 2009-02-02 15:11:52 -0800 | [diff] [blame] | 1170 | sdvox |= SDVO_AUDIO_ENABLE; |
| 1171 | } |
| 1172 | |
Zhenyu Wang | 7026d4a | 2009-03-24 14:02:43 +0800 | [diff] [blame] | 1173 | /* We have tried to get input timing in mode_fixup, and filled into |
| 1174 | adjusted_mode */ |
ling.ma@intel.com | 12682a9 | 2009-06-30 11:35:35 +0800 | [diff] [blame] | 1175 | if (sdvo_priv->is_tv || sdvo_priv->is_lvds) { |
Zhenyu Wang | 7026d4a | 2009-03-24 14:02:43 +0800 | [diff] [blame] | 1176 | intel_sdvo_get_dtd_from_mode(&input_dtd, adjusted_mode); |
ling.ma@intel.com | 12682a9 | 2009-06-30 11:35:35 +0800 | [diff] [blame] | 1177 | input_dtd.part2.sdvo_flags = sdvo_priv->sdvo_flags; |
| 1178 | } else |
Zhenyu Wang | 7026d4a | 2009-03-24 14:02:43 +0800 | [diff] [blame] | 1179 | intel_sdvo_get_dtd_from_mode(&input_dtd, mode); |
Jesse Barnes | e2f0ba9 | 2009-02-02 15:11:52 -0800 | [diff] [blame] | 1180 | |
| 1181 | /* If it's a TV, we already set the output timing in mode_fixup. |
| 1182 | * Otherwise, the output timing is equal to the input timing. |
| 1183 | */ |
ling.ma@intel.com | 12682a9 | 2009-06-30 11:35:35 +0800 | [diff] [blame] | 1184 | if (!sdvo_priv->is_tv && !sdvo_priv->is_lvds) { |
Jesse Barnes | e2f0ba9 | 2009-02-02 15:11:52 -0800 | [diff] [blame] | 1185 | /* Set the output timing to the screen */ |
Eric Anholt | c751ce4 | 2010-03-25 11:48:48 -0700 | [diff] [blame] | 1186 | intel_sdvo_set_target_output(intel_encoder, |
Zhenyu Wang | 14571b4 | 2010-03-30 14:06:33 +0800 | [diff] [blame] | 1187 | sdvo_priv->attached_output); |
Eric Anholt | c751ce4 | 2010-03-25 11:48:48 -0700 | [diff] [blame] | 1188 | intel_sdvo_set_output_timing(intel_encoder, &input_dtd); |
Jesse Barnes | e2f0ba9 | 2009-02-02 15:11:52 -0800 | [diff] [blame] | 1189 | } |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 1190 | |
| 1191 | /* Set the input timing to the screen. Assume always input 0. */ |
Eric Anholt | c751ce4 | 2010-03-25 11:48:48 -0700 | [diff] [blame] | 1192 | intel_sdvo_set_target_input(intel_encoder, true, false); |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 1193 | |
Zhenyu Wang | 7026d4a | 2009-03-24 14:02:43 +0800 | [diff] [blame] | 1194 | if (sdvo_priv->is_tv) |
Eric Anholt | c751ce4 | 2010-03-25 11:48:48 -0700 | [diff] [blame] | 1195 | intel_sdvo_set_tv_format(intel_encoder); |
Zhenyu Wang | 7026d4a | 2009-03-24 14:02:43 +0800 | [diff] [blame] | 1196 | |
Jesse Barnes | e2f0ba9 | 2009-02-02 15:11:52 -0800 | [diff] [blame] | 1197 | /* We would like to use intel_sdvo_create_preferred_input_timing() to |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 1198 | * provide the device with a timing it can support, if it supports that |
| 1199 | * feature. However, presumably we would need to adjust the CRTC to |
| 1200 | * output the preferred timing, and we don't support that currently. |
| 1201 | */ |
Jesse Barnes | e2f0ba9 | 2009-02-02 15:11:52 -0800 | [diff] [blame] | 1202 | #if 0 |
Eric Anholt | c751ce4 | 2010-03-25 11:48:48 -0700 | [diff] [blame] | 1203 | success = intel_sdvo_create_preferred_input_timing(encoder, clock, |
Jesse Barnes | e2f0ba9 | 2009-02-02 15:11:52 -0800 | [diff] [blame] | 1204 | width, height); |
| 1205 | if (success) { |
| 1206 | struct intel_sdvo_dtd *input_dtd; |
| 1207 | |
Eric Anholt | c751ce4 | 2010-03-25 11:48:48 -0700 | [diff] [blame] | 1208 | intel_sdvo_get_preferred_input_timing(encoder, &input_dtd); |
| 1209 | intel_sdvo_set_input_timing(encoder, &input_dtd); |
Jesse Barnes | e2f0ba9 | 2009-02-02 15:11:52 -0800 | [diff] [blame] | 1210 | } |
| 1211 | #else |
Eric Anholt | c751ce4 | 2010-03-25 11:48:48 -0700 | [diff] [blame] | 1212 | intel_sdvo_set_input_timing(intel_encoder, &input_dtd); |
Jesse Barnes | e2f0ba9 | 2009-02-02 15:11:52 -0800 | [diff] [blame] | 1213 | #endif |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 1214 | |
| 1215 | switch (intel_sdvo_get_pixel_multiplier(mode)) { |
| 1216 | case 1: |
Eric Anholt | c751ce4 | 2010-03-25 11:48:48 -0700 | [diff] [blame] | 1217 | intel_sdvo_set_clock_rate_mult(intel_encoder, |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 1218 | SDVO_CLOCK_RATE_MULT_1X); |
| 1219 | break; |
| 1220 | case 2: |
Eric Anholt | c751ce4 | 2010-03-25 11:48:48 -0700 | [diff] [blame] | 1221 | intel_sdvo_set_clock_rate_mult(intel_encoder, |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 1222 | SDVO_CLOCK_RATE_MULT_2X); |
| 1223 | break; |
| 1224 | case 4: |
Eric Anholt | c751ce4 | 2010-03-25 11:48:48 -0700 | [diff] [blame] | 1225 | intel_sdvo_set_clock_rate_mult(intel_encoder, |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 1226 | SDVO_CLOCK_RATE_MULT_4X); |
| 1227 | break; |
| 1228 | } |
| 1229 | |
| 1230 | /* Set the SDVO control regs. */ |
Jesse Barnes | e2f0ba9 | 2009-02-02 15:11:52 -0800 | [diff] [blame] | 1231 | if (IS_I965G(dev)) { |
| 1232 | sdvox |= SDVO_BORDER_ENABLE | |
| 1233 | SDVO_VSYNC_ACTIVE_HIGH | |
| 1234 | SDVO_HSYNC_ACTIVE_HIGH; |
| 1235 | } else { |
Eric Anholt | c751ce4 | 2010-03-25 11:48:48 -0700 | [diff] [blame] | 1236 | sdvox |= I915_READ(sdvo_priv->sdvo_reg); |
| 1237 | switch (sdvo_priv->sdvo_reg) { |
Jesse Barnes | e2f0ba9 | 2009-02-02 15:11:52 -0800 | [diff] [blame] | 1238 | case SDVOB: |
| 1239 | sdvox &= SDVOB_PRESERVE_MASK; |
| 1240 | break; |
| 1241 | case SDVOC: |
| 1242 | sdvox &= SDVOC_PRESERVE_MASK; |
| 1243 | break; |
| 1244 | } |
| 1245 | sdvox |= (9 << 19) | SDVO_BORDER_ENABLE; |
| 1246 | } |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 1247 | if (intel_crtc->pipe == 1) |
| 1248 | sdvox |= SDVO_PIPE_B_SELECT; |
| 1249 | |
| 1250 | sdvo_pixel_multiply = intel_sdvo_get_pixel_multiplier(mode); |
| 1251 | if (IS_I965G(dev)) { |
Jesse Barnes | e2f0ba9 | 2009-02-02 15:11:52 -0800 | [diff] [blame] | 1252 | /* done in crtc_mode_set as the dpll_md reg must be written early */ |
| 1253 | } else if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) { |
| 1254 | /* done in crtc_mode_set as it lives inside the dpll register */ |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 1255 | } else { |
| 1256 | sdvox |= (sdvo_pixel_multiply - 1) << SDVO_PORT_MULTIPLY_SHIFT; |
| 1257 | } |
| 1258 | |
ling.ma@intel.com | 12682a9 | 2009-06-30 11:35:35 +0800 | [diff] [blame] | 1259 | if (sdvo_priv->sdvo_flags & SDVO_NEED_TO_STALL) |
| 1260 | sdvox |= SDVO_STALL_SELECT; |
Eric Anholt | c751ce4 | 2010-03-25 11:48:48 -0700 | [diff] [blame] | 1261 | intel_sdvo_write_sdvox(intel_encoder, sdvox); |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 1262 | } |
| 1263 | |
| 1264 | static void intel_sdvo_dpms(struct drm_encoder *encoder, int mode) |
| 1265 | { |
| 1266 | struct drm_device *dev = encoder->dev; |
| 1267 | struct drm_i915_private *dev_priv = dev->dev_private; |
Eric Anholt | 21d40d3 | 2010-03-25 11:11:14 -0700 | [diff] [blame] | 1268 | struct intel_encoder *intel_encoder = enc_to_intel_encoder(encoder); |
| 1269 | struct intel_sdvo_priv *sdvo_priv = intel_encoder->dev_priv; |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 1270 | u32 temp; |
| 1271 | |
| 1272 | if (mode != DRM_MODE_DPMS_ON) { |
Eric Anholt | 21d40d3 | 2010-03-25 11:11:14 -0700 | [diff] [blame] | 1273 | intel_sdvo_set_active_outputs(intel_encoder, 0); |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 1274 | if (0) |
Eric Anholt | 21d40d3 | 2010-03-25 11:11:14 -0700 | [diff] [blame] | 1275 | intel_sdvo_set_encoder_power_state(intel_encoder, mode); |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 1276 | |
| 1277 | if (mode == DRM_MODE_DPMS_OFF) { |
Eric Anholt | c751ce4 | 2010-03-25 11:48:48 -0700 | [diff] [blame] | 1278 | temp = I915_READ(sdvo_priv->sdvo_reg); |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 1279 | if ((temp & SDVO_ENABLE) != 0) { |
Eric Anholt | 21d40d3 | 2010-03-25 11:11:14 -0700 | [diff] [blame] | 1280 | intel_sdvo_write_sdvox(intel_encoder, temp & ~SDVO_ENABLE); |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 1281 | } |
| 1282 | } |
| 1283 | } else { |
| 1284 | bool input1, input2; |
| 1285 | int i; |
| 1286 | u8 status; |
| 1287 | |
Eric Anholt | c751ce4 | 2010-03-25 11:48:48 -0700 | [diff] [blame] | 1288 | temp = I915_READ(sdvo_priv->sdvo_reg); |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 1289 | if ((temp & SDVO_ENABLE) == 0) |
Eric Anholt | 21d40d3 | 2010-03-25 11:11:14 -0700 | [diff] [blame] | 1290 | intel_sdvo_write_sdvox(intel_encoder, temp | SDVO_ENABLE); |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 1291 | for (i = 0; i < 2; i++) |
| 1292 | intel_wait_for_vblank(dev); |
| 1293 | |
Eric Anholt | 21d40d3 | 2010-03-25 11:11:14 -0700 | [diff] [blame] | 1294 | status = intel_sdvo_get_trained_inputs(intel_encoder, &input1, |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 1295 | &input2); |
| 1296 | |
| 1297 | |
| 1298 | /* Warn if the device reported failure to sync. |
| 1299 | * A lot of SDVO devices fail to notify of sync, but it's |
| 1300 | * a given it the status is a success, we succeeded. |
| 1301 | */ |
| 1302 | if (status == SDVO_CMD_STATUS_SUCCESS && !input1) { |
Zhao Yakui | 8a4c47f | 2009-07-20 13:48:04 +0800 | [diff] [blame] | 1303 | DRM_DEBUG_KMS("First %s output reported failure to " |
| 1304 | "sync\n", SDVO_NAME(sdvo_priv)); |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 1305 | } |
| 1306 | |
| 1307 | if (0) |
Eric Anholt | 21d40d3 | 2010-03-25 11:11:14 -0700 | [diff] [blame] | 1308 | intel_sdvo_set_encoder_power_state(intel_encoder, mode); |
Zhenyu Wang | 14571b4 | 2010-03-30 14:06:33 +0800 | [diff] [blame] | 1309 | intel_sdvo_set_active_outputs(intel_encoder, sdvo_priv->attached_output); |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 1310 | } |
| 1311 | return; |
| 1312 | } |
| 1313 | |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 1314 | static int intel_sdvo_mode_valid(struct drm_connector *connector, |
| 1315 | struct drm_display_mode *mode) |
| 1316 | { |
Zhenyu Wang | d2a82a6 | 2010-03-29 21:22:55 +0800 | [diff] [blame] | 1317 | struct drm_encoder *encoder = intel_attached_encoder(connector); |
| 1318 | struct intel_encoder *intel_encoder = enc_to_intel_encoder(encoder); |
Eric Anholt | 21d40d3 | 2010-03-25 11:11:14 -0700 | [diff] [blame] | 1319 | struct intel_sdvo_priv *sdvo_priv = intel_encoder->dev_priv; |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 1320 | |
| 1321 | if (mode->flags & DRM_MODE_FLAG_DBLSCAN) |
| 1322 | return MODE_NO_DBLESCAN; |
| 1323 | |
| 1324 | if (sdvo_priv->pixel_clock_min > mode->clock) |
| 1325 | return MODE_CLOCK_LOW; |
| 1326 | |
| 1327 | if (sdvo_priv->pixel_clock_max < mode->clock) |
| 1328 | return MODE_CLOCK_HIGH; |
| 1329 | |
ling.ma@intel.com | 12682a9 | 2009-06-30 11:35:35 +0800 | [diff] [blame] | 1330 | if (sdvo_priv->is_lvds == true) { |
| 1331 | if (sdvo_priv->sdvo_lvds_fixed_mode == NULL) |
| 1332 | return MODE_PANEL; |
| 1333 | |
| 1334 | if (mode->hdisplay > sdvo_priv->sdvo_lvds_fixed_mode->hdisplay) |
| 1335 | return MODE_PANEL; |
| 1336 | |
| 1337 | if (mode->vdisplay > sdvo_priv->sdvo_lvds_fixed_mode->vdisplay) |
| 1338 | return MODE_PANEL; |
| 1339 | } |
| 1340 | |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 1341 | return MODE_OK; |
| 1342 | } |
| 1343 | |
Eric Anholt | 21d40d3 | 2010-03-25 11:11:14 -0700 | [diff] [blame] | 1344 | static bool intel_sdvo_get_capabilities(struct intel_encoder *intel_encoder, struct intel_sdvo_caps *caps) |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 1345 | { |
| 1346 | u8 status; |
| 1347 | |
Eric Anholt | 21d40d3 | 2010-03-25 11:11:14 -0700 | [diff] [blame] | 1348 | intel_sdvo_write_cmd(intel_encoder, SDVO_CMD_GET_DEVICE_CAPS, NULL, 0); |
| 1349 | status = intel_sdvo_read_response(intel_encoder, caps, sizeof(*caps)); |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 1350 | if (status != SDVO_CMD_STATUS_SUCCESS) |
| 1351 | return false; |
| 1352 | |
| 1353 | return true; |
| 1354 | } |
| 1355 | |
Zhenyu Wang | d2a82a6 | 2010-03-29 21:22:55 +0800 | [diff] [blame] | 1356 | /* No use! */ |
| 1357 | #if 0 |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 1358 | struct drm_connector* intel_sdvo_find(struct drm_device *dev, int sdvoB) |
| 1359 | { |
| 1360 | struct drm_connector *connector = NULL; |
Eric Anholt | 21d40d3 | 2010-03-25 11:11:14 -0700 | [diff] [blame] | 1361 | struct intel_encoder *iout = NULL; |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 1362 | struct intel_sdvo_priv *sdvo; |
| 1363 | |
| 1364 | /* find the sdvo connector */ |
| 1365 | list_for_each_entry(connector, &dev->mode_config.connector_list, head) { |
Eric Anholt | 21d40d3 | 2010-03-25 11:11:14 -0700 | [diff] [blame] | 1366 | iout = to_intel_encoder(connector); |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 1367 | |
| 1368 | if (iout->type != INTEL_OUTPUT_SDVO) |
| 1369 | continue; |
| 1370 | |
| 1371 | sdvo = iout->dev_priv; |
| 1372 | |
Eric Anholt | c751ce4 | 2010-03-25 11:48:48 -0700 | [diff] [blame] | 1373 | if (sdvo->sdvo_reg == SDVOB && sdvoB) |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 1374 | return connector; |
| 1375 | |
Eric Anholt | c751ce4 | 2010-03-25 11:48:48 -0700 | [diff] [blame] | 1376 | if (sdvo->sdvo_reg == SDVOC && !sdvoB) |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 1377 | return connector; |
| 1378 | |
| 1379 | } |
| 1380 | |
| 1381 | return NULL; |
| 1382 | } |
| 1383 | |
| 1384 | int intel_sdvo_supports_hotplug(struct drm_connector *connector) |
| 1385 | { |
| 1386 | u8 response[2]; |
| 1387 | u8 status; |
Eric Anholt | 21d40d3 | 2010-03-25 11:11:14 -0700 | [diff] [blame] | 1388 | struct intel_encoder *intel_encoder; |
Zhao Yakui | 8a4c47f | 2009-07-20 13:48:04 +0800 | [diff] [blame] | 1389 | DRM_DEBUG_KMS("\n"); |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 1390 | |
| 1391 | if (!connector) |
| 1392 | return 0; |
| 1393 | |
Eric Anholt | 21d40d3 | 2010-03-25 11:11:14 -0700 | [diff] [blame] | 1394 | intel_encoder = to_intel_encoder(connector); |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 1395 | |
Eric Anholt | 21d40d3 | 2010-03-25 11:11:14 -0700 | [diff] [blame] | 1396 | intel_sdvo_write_cmd(intel_encoder, SDVO_CMD_GET_HOT_PLUG_SUPPORT, NULL, 0); |
| 1397 | status = intel_sdvo_read_response(intel_encoder, &response, 2); |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 1398 | |
| 1399 | if (response[0] !=0) |
| 1400 | return 1; |
| 1401 | |
| 1402 | return 0; |
| 1403 | } |
| 1404 | |
| 1405 | void intel_sdvo_set_hotplug(struct drm_connector *connector, int on) |
| 1406 | { |
| 1407 | u8 response[2]; |
| 1408 | u8 status; |
Eric Anholt | 21d40d3 | 2010-03-25 11:11:14 -0700 | [diff] [blame] | 1409 | struct intel_encoder *intel_encoder = to_intel_encoder(connector); |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 1410 | |
Eric Anholt | 21d40d3 | 2010-03-25 11:11:14 -0700 | [diff] [blame] | 1411 | intel_sdvo_write_cmd(intel_encoder, SDVO_CMD_GET_ACTIVE_HOT_PLUG, NULL, 0); |
| 1412 | intel_sdvo_read_response(intel_encoder, &response, 2); |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 1413 | |
| 1414 | if (on) { |
Eric Anholt | 21d40d3 | 2010-03-25 11:11:14 -0700 | [diff] [blame] | 1415 | intel_sdvo_write_cmd(intel_encoder, SDVO_CMD_GET_HOT_PLUG_SUPPORT, NULL, 0); |
| 1416 | status = intel_sdvo_read_response(intel_encoder, &response, 2); |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 1417 | |
Eric Anholt | 21d40d3 | 2010-03-25 11:11:14 -0700 | [diff] [blame] | 1418 | intel_sdvo_write_cmd(intel_encoder, SDVO_CMD_SET_ACTIVE_HOT_PLUG, &response, 2); |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 1419 | } else { |
| 1420 | response[0] = 0; |
| 1421 | response[1] = 0; |
Eric Anholt | 21d40d3 | 2010-03-25 11:11:14 -0700 | [diff] [blame] | 1422 | intel_sdvo_write_cmd(intel_encoder, SDVO_CMD_SET_ACTIVE_HOT_PLUG, &response, 2); |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 1423 | } |
| 1424 | |
Eric Anholt | 21d40d3 | 2010-03-25 11:11:14 -0700 | [diff] [blame] | 1425 | intel_sdvo_write_cmd(intel_encoder, SDVO_CMD_GET_ACTIVE_HOT_PLUG, NULL, 0); |
| 1426 | intel_sdvo_read_response(intel_encoder, &response, 2); |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 1427 | } |
Zhenyu Wang | d2a82a6 | 2010-03-29 21:22:55 +0800 | [diff] [blame] | 1428 | #endif |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 1429 | |
ling.ma@intel.com | fb7a46f | 2009-07-23 17:11:34 +0800 | [diff] [blame] | 1430 | static bool |
Eric Anholt | 21d40d3 | 2010-03-25 11:11:14 -0700 | [diff] [blame] | 1431 | intel_sdvo_multifunc_encoder(struct intel_encoder *intel_encoder) |
ling.ma@intel.com | fb7a46f | 2009-07-23 17:11:34 +0800 | [diff] [blame] | 1432 | { |
Eric Anholt | 21d40d3 | 2010-03-25 11:11:14 -0700 | [diff] [blame] | 1433 | struct intel_sdvo_priv *sdvo_priv = intel_encoder->dev_priv; |
ling.ma@intel.com | fb7a46f | 2009-07-23 17:11:34 +0800 | [diff] [blame] | 1434 | int caps = 0; |
| 1435 | |
| 1436 | if (sdvo_priv->caps.output_flags & |
| 1437 | (SDVO_OUTPUT_TMDS0 | SDVO_OUTPUT_TMDS1)) |
| 1438 | caps++; |
| 1439 | if (sdvo_priv->caps.output_flags & |
| 1440 | (SDVO_OUTPUT_RGB0 | SDVO_OUTPUT_RGB1)) |
| 1441 | caps++; |
| 1442 | if (sdvo_priv->caps.output_flags & |
Roel Kluin | 19e1f88 | 2009-08-09 13:50:53 +0200 | [diff] [blame] | 1443 | (SDVO_OUTPUT_SVID0 | SDVO_OUTPUT_SVID1)) |
ling.ma@intel.com | fb7a46f | 2009-07-23 17:11:34 +0800 | [diff] [blame] | 1444 | caps++; |
| 1445 | if (sdvo_priv->caps.output_flags & |
| 1446 | (SDVO_OUTPUT_CVBS0 | SDVO_OUTPUT_CVBS1)) |
| 1447 | caps++; |
| 1448 | if (sdvo_priv->caps.output_flags & |
| 1449 | (SDVO_OUTPUT_YPRPB0 | SDVO_OUTPUT_YPRPB1)) |
| 1450 | caps++; |
| 1451 | |
| 1452 | if (sdvo_priv->caps.output_flags & |
| 1453 | (SDVO_OUTPUT_SCART0 | SDVO_OUTPUT_SCART1)) |
| 1454 | caps++; |
| 1455 | |
| 1456 | if (sdvo_priv->caps.output_flags & |
| 1457 | (SDVO_OUTPUT_LVDS0 | SDVO_OUTPUT_LVDS1)) |
| 1458 | caps++; |
| 1459 | |
| 1460 | return (caps > 1); |
| 1461 | } |
| 1462 | |
Keith Packard | 57cdaf9 | 2009-09-04 13:07:54 +0800 | [diff] [blame] | 1463 | static struct drm_connector * |
| 1464 | intel_find_analog_connector(struct drm_device *dev) |
| 1465 | { |
| 1466 | struct drm_connector *connector; |
Zhenyu Wang | d2a82a6 | 2010-03-29 21:22:55 +0800 | [diff] [blame] | 1467 | struct drm_encoder *encoder; |
Eric Anholt | 21d40d3 | 2010-03-25 11:11:14 -0700 | [diff] [blame] | 1468 | struct intel_encoder *intel_encoder; |
Keith Packard | 57cdaf9 | 2009-09-04 13:07:54 +0800 | [diff] [blame] | 1469 | |
Zhenyu Wang | d2a82a6 | 2010-03-29 21:22:55 +0800 | [diff] [blame] | 1470 | list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) { |
| 1471 | intel_encoder = enc_to_intel_encoder(encoder); |
| 1472 | if (intel_encoder->type == INTEL_OUTPUT_ANALOG) { |
| 1473 | list_for_each_entry(connector, &dev->mode_config.connector_list, head) { |
| 1474 | if (connector && encoder == intel_attached_encoder(connector)) |
| 1475 | return connector; |
| 1476 | } |
| 1477 | } |
Keith Packard | 57cdaf9 | 2009-09-04 13:07:54 +0800 | [diff] [blame] | 1478 | } |
| 1479 | return NULL; |
| 1480 | } |
| 1481 | |
| 1482 | static int |
| 1483 | intel_analog_is_connected(struct drm_device *dev) |
| 1484 | { |
| 1485 | struct drm_connector *analog_connector; |
| 1486 | analog_connector = intel_find_analog_connector(dev); |
| 1487 | |
| 1488 | if (!analog_connector) |
| 1489 | return false; |
| 1490 | |
| 1491 | if (analog_connector->funcs->detect(analog_connector) == |
| 1492 | connector_status_disconnected) |
| 1493 | return false; |
| 1494 | |
| 1495 | return true; |
| 1496 | } |
| 1497 | |
ling.ma@intel.com | 2b8d33f7 | 2009-07-29 11:31:18 +0800 | [diff] [blame] | 1498 | enum drm_connector_status |
| 1499 | intel_sdvo_hdmi_sink_detect(struct drm_connector *connector, u16 response) |
Ma Ling | 9dff6af | 2009-04-02 13:13:26 +0800 | [diff] [blame] | 1500 | { |
Zhenyu Wang | d2a82a6 | 2010-03-29 21:22:55 +0800 | [diff] [blame] | 1501 | struct drm_encoder *encoder = intel_attached_encoder(connector); |
| 1502 | struct intel_encoder *intel_encoder = enc_to_intel_encoder(encoder); |
Eric Anholt | 21d40d3 | 2010-03-25 11:11:14 -0700 | [diff] [blame] | 1503 | struct intel_sdvo_priv *sdvo_priv = intel_encoder->dev_priv; |
ling.ma@intel.com | 2b8d33f7 | 2009-07-29 11:31:18 +0800 | [diff] [blame] | 1504 | enum drm_connector_status status = connector_status_connected; |
Ma Ling | 9dff6af | 2009-04-02 13:13:26 +0800 | [diff] [blame] | 1505 | struct edid *edid = NULL; |
| 1506 | |
Zhenyu Wang | d2a82a6 | 2010-03-29 21:22:55 +0800 | [diff] [blame] | 1507 | edid = drm_get_edid(connector, |
Eric Anholt | 21d40d3 | 2010-03-25 11:11:14 -0700 | [diff] [blame] | 1508 | intel_encoder->ddc_bus); |
Keith Packard | 57cdaf9 | 2009-09-04 13:07:54 +0800 | [diff] [blame] | 1509 | |
Zhao Yakui | 7c3f0a2 | 2010-01-08 10:58:20 +0800 | [diff] [blame] | 1510 | /* This is only applied to SDVO cards with multiple outputs */ |
Eric Anholt | 21d40d3 | 2010-03-25 11:11:14 -0700 | [diff] [blame] | 1511 | if (edid == NULL && intel_sdvo_multifunc_encoder(intel_encoder)) { |
Zhao Yakui | 7c3f0a2 | 2010-01-08 10:58:20 +0800 | [diff] [blame] | 1512 | uint8_t saved_ddc, temp_ddc; |
| 1513 | saved_ddc = sdvo_priv->ddc_bus; |
| 1514 | temp_ddc = sdvo_priv->ddc_bus >> 1; |
| 1515 | /* |
| 1516 | * Don't use the 1 as the argument of DDC bus switch to get |
| 1517 | * the EDID. It is used for SDVO SPD ROM. |
| 1518 | */ |
| 1519 | while(temp_ddc > 1) { |
| 1520 | sdvo_priv->ddc_bus = temp_ddc; |
Zhenyu Wang | d2a82a6 | 2010-03-29 21:22:55 +0800 | [diff] [blame] | 1521 | edid = drm_get_edid(connector, |
Eric Anholt | 21d40d3 | 2010-03-25 11:11:14 -0700 | [diff] [blame] | 1522 | intel_encoder->ddc_bus); |
Zhao Yakui | 7c3f0a2 | 2010-01-08 10:58:20 +0800 | [diff] [blame] | 1523 | if (edid) { |
| 1524 | /* |
| 1525 | * When we can get the EDID, maybe it is the |
| 1526 | * correct DDC bus. Update it. |
| 1527 | */ |
| 1528 | sdvo_priv->ddc_bus = temp_ddc; |
| 1529 | break; |
| 1530 | } |
| 1531 | temp_ddc >>= 1; |
| 1532 | } |
| 1533 | if (edid == NULL) |
| 1534 | sdvo_priv->ddc_bus = saved_ddc; |
| 1535 | } |
Keith Packard | 57cdaf9 | 2009-09-04 13:07:54 +0800 | [diff] [blame] | 1536 | /* when there is no edid and no monitor is connected with VGA |
| 1537 | * port, try to use the CRT ddc to read the EDID for DVI-connector |
| 1538 | */ |
| 1539 | if (edid == NULL && |
| 1540 | sdvo_priv->analog_ddc_bus && |
Zhenyu Wang | d2a82a6 | 2010-03-29 21:22:55 +0800 | [diff] [blame] | 1541 | !intel_analog_is_connected(connector->dev)) |
| 1542 | edid = drm_get_edid(connector, |
Keith Packard | 57cdaf9 | 2009-09-04 13:07:54 +0800 | [diff] [blame] | 1543 | sdvo_priv->analog_ddc_bus); |
Ma Ling | 9dff6af | 2009-04-02 13:13:26 +0800 | [diff] [blame] | 1544 | if (edid != NULL) { |
ling.ma@intel.com | 2b8d33f7 | 2009-07-29 11:31:18 +0800 | [diff] [blame] | 1545 | /* Don't report the output as connected if it's a DVI-I |
| 1546 | * connector with a non-digital EDID coming out. |
| 1547 | */ |
| 1548 | if (response & (SDVO_OUTPUT_TMDS0 | SDVO_OUTPUT_TMDS1)) { |
| 1549 | if (edid->input & DRM_EDID_INPUT_DIGITAL) |
| 1550 | sdvo_priv->is_hdmi = |
| 1551 | drm_detect_hdmi_monitor(edid); |
| 1552 | else |
| 1553 | status = connector_status_disconnected; |
| 1554 | } |
| 1555 | |
Ma Ling | 9dff6af | 2009-04-02 13:13:26 +0800 | [diff] [blame] | 1556 | kfree(edid); |
Zhenyu Wang | d2a82a6 | 2010-03-29 21:22:55 +0800 | [diff] [blame] | 1557 | connector->display_info.raw_edid = NULL; |
ling.ma@intel.com | 2b8d33f7 | 2009-07-29 11:31:18 +0800 | [diff] [blame] | 1558 | |
| 1559 | } else if (response & (SDVO_OUTPUT_TMDS0 | SDVO_OUTPUT_TMDS1)) |
| 1560 | status = connector_status_disconnected; |
| 1561 | |
| 1562 | return status; |
Ma Ling | 9dff6af | 2009-04-02 13:13:26 +0800 | [diff] [blame] | 1563 | } |
| 1564 | |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 1565 | static enum drm_connector_status intel_sdvo_detect(struct drm_connector *connector) |
| 1566 | { |
ling.ma@intel.com | fb7a46f | 2009-07-23 17:11:34 +0800 | [diff] [blame] | 1567 | uint16_t response; |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 1568 | u8 status; |
Zhenyu Wang | d2a82a6 | 2010-03-29 21:22:55 +0800 | [diff] [blame] | 1569 | struct drm_encoder *encoder = intel_attached_encoder(connector); |
| 1570 | struct intel_encoder *intel_encoder = enc_to_intel_encoder(encoder); |
| 1571 | struct intel_connector *intel_connector = to_intel_connector(connector); |
Eric Anholt | 21d40d3 | 2010-03-25 11:11:14 -0700 | [diff] [blame] | 1572 | struct intel_sdvo_priv *sdvo_priv = intel_encoder->dev_priv; |
Zhenyu Wang | 14571b4 | 2010-03-30 14:06:33 +0800 | [diff] [blame] | 1573 | struct intel_sdvo_connector *sdvo_connector = intel_connector->dev_priv; |
| 1574 | enum drm_connector_status ret; |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 1575 | |
Eric Anholt | 21d40d3 | 2010-03-25 11:11:14 -0700 | [diff] [blame] | 1576 | intel_sdvo_write_cmd(intel_encoder, |
Zhao Yakui | ce6feab | 2009-08-24 13:50:26 +0800 | [diff] [blame] | 1577 | SDVO_CMD_GET_ATTACHED_DISPLAYS, NULL, 0); |
Zhao Yakui | d09c23d | 2009-11-06 15:39:56 +0800 | [diff] [blame] | 1578 | if (sdvo_priv->is_tv) { |
| 1579 | /* add 30ms delay when the output type is SDVO-TV */ |
| 1580 | mdelay(30); |
| 1581 | } |
Eric Anholt | 21d40d3 | 2010-03-25 11:11:14 -0700 | [diff] [blame] | 1582 | status = intel_sdvo_read_response(intel_encoder, &response, 2); |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 1583 | |
Dave Airlie | 51c8b40 | 2009-08-20 13:38:04 +1000 | [diff] [blame] | 1584 | DRM_DEBUG_KMS("SDVO response %d %d\n", response & 0xff, response >> 8); |
Jesse Barnes | e2f0ba9 | 2009-02-02 15:11:52 -0800 | [diff] [blame] | 1585 | |
| 1586 | if (status != SDVO_CMD_STATUS_SUCCESS) |
| 1587 | return connector_status_unknown; |
| 1588 | |
ling.ma@intel.com | fb7a46f | 2009-07-23 17:11:34 +0800 | [diff] [blame] | 1589 | if (response == 0) |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 1590 | return connector_status_disconnected; |
ling.ma@intel.com | fb7a46f | 2009-07-23 17:11:34 +0800 | [diff] [blame] | 1591 | |
Zhenyu Wang | 14571b4 | 2010-03-30 14:06:33 +0800 | [diff] [blame] | 1592 | sdvo_priv->attached_output = response; |
| 1593 | |
| 1594 | if ((sdvo_connector->output_flag & response) == 0) |
| 1595 | ret = connector_status_disconnected; |
| 1596 | else if (response & (SDVO_OUTPUT_TMDS0 | SDVO_OUTPUT_TMDS1)) |
| 1597 | ret = intel_sdvo_hdmi_sink_detect(connector, response); |
| 1598 | else |
| 1599 | ret = connector_status_connected; |
| 1600 | |
| 1601 | /* May update encoder flag for like clock for SDVO TV, etc.*/ |
| 1602 | if (ret == connector_status_connected) { |
| 1603 | sdvo_priv->is_tv = false; |
| 1604 | sdvo_priv->is_lvds = false; |
| 1605 | intel_encoder->needs_tv_clock = false; |
| 1606 | |
| 1607 | if (response & SDVO_TV_MASK) { |
| 1608 | sdvo_priv->is_tv = true; |
| 1609 | intel_encoder->needs_tv_clock = true; |
| 1610 | } |
| 1611 | if (response & SDVO_LVDS_MASK) |
| 1612 | sdvo_priv->is_lvds = true; |
ling.ma@intel.com | fb7a46f | 2009-07-23 17:11:34 +0800 | [diff] [blame] | 1613 | } |
Zhenyu Wang | 14571b4 | 2010-03-30 14:06:33 +0800 | [diff] [blame] | 1614 | |
| 1615 | return ret; |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 1616 | } |
| 1617 | |
Jesse Barnes | e2f0ba9 | 2009-02-02 15:11:52 -0800 | [diff] [blame] | 1618 | static void intel_sdvo_get_ddc_modes(struct drm_connector *connector) |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 1619 | { |
Zhenyu Wang | d2a82a6 | 2010-03-29 21:22:55 +0800 | [diff] [blame] | 1620 | struct drm_encoder *encoder = intel_attached_encoder(connector); |
| 1621 | struct intel_encoder *intel_encoder = enc_to_intel_encoder(encoder); |
Eric Anholt | 21d40d3 | 2010-03-25 11:11:14 -0700 | [diff] [blame] | 1622 | struct intel_sdvo_priv *sdvo_priv = intel_encoder->dev_priv; |
Keith Packard | 57cdaf9 | 2009-09-04 13:07:54 +0800 | [diff] [blame] | 1623 | int num_modes; |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 1624 | |
| 1625 | /* set the bus switch and get the modes */ |
Zhenyu Wang | 335af9a | 2010-03-30 14:39:31 +0800 | [diff] [blame] | 1626 | num_modes = intel_ddc_get_modes(connector, intel_encoder->ddc_bus); |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 1627 | |
Keith Packard | 57cdaf9 | 2009-09-04 13:07:54 +0800 | [diff] [blame] | 1628 | /* |
| 1629 | * Mac mini hack. On this device, the DVI-I connector shares one DDC |
| 1630 | * link between analog and digital outputs. So, if the regular SDVO |
| 1631 | * DDC fails, check to see if the analog output is disconnected, in |
| 1632 | * which case we'll look there for the digital DDC data. |
Jesse Barnes | e2f0ba9 | 2009-02-02 15:11:52 -0800 | [diff] [blame] | 1633 | */ |
Keith Packard | 57cdaf9 | 2009-09-04 13:07:54 +0800 | [diff] [blame] | 1634 | if (num_modes == 0 && |
| 1635 | sdvo_priv->analog_ddc_bus && |
Zhenyu Wang | d2a82a6 | 2010-03-29 21:22:55 +0800 | [diff] [blame] | 1636 | !intel_analog_is_connected(connector->dev)) { |
Keith Packard | 57cdaf9 | 2009-09-04 13:07:54 +0800 | [diff] [blame] | 1637 | /* Switch to the analog ddc bus and try that |
| 1638 | */ |
Zhenyu Wang | 335af9a | 2010-03-30 14:39:31 +0800 | [diff] [blame] | 1639 | (void) intel_ddc_get_modes(connector, sdvo_priv->analog_ddc_bus); |
Jesse Barnes | e2f0ba9 | 2009-02-02 15:11:52 -0800 | [diff] [blame] | 1640 | } |
Jesse Barnes | e2f0ba9 | 2009-02-02 15:11:52 -0800 | [diff] [blame] | 1641 | } |
| 1642 | |
| 1643 | /* |
| 1644 | * Set of SDVO TV modes. |
| 1645 | * Note! This is in reply order (see loop in get_tv_modes). |
| 1646 | * XXX: all 60Hz refresh? |
| 1647 | */ |
| 1648 | struct drm_display_mode sdvo_tv_modes[] = { |
Zhenyu Wang | 7026d4a | 2009-03-24 14:02:43 +0800 | [diff] [blame] | 1649 | { DRM_MODE("320x200", DRM_MODE_TYPE_DRIVER, 5815, 320, 321, 384, |
| 1650 | 416, 0, 200, 201, 232, 233, 0, |
Jesse Barnes | e2f0ba9 | 2009-02-02 15:11:52 -0800 | [diff] [blame] | 1651 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, |
Zhenyu Wang | 7026d4a | 2009-03-24 14:02:43 +0800 | [diff] [blame] | 1652 | { DRM_MODE("320x240", DRM_MODE_TYPE_DRIVER, 6814, 320, 321, 384, |
| 1653 | 416, 0, 240, 241, 272, 273, 0, |
Jesse Barnes | e2f0ba9 | 2009-02-02 15:11:52 -0800 | [diff] [blame] | 1654 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, |
Zhenyu Wang | 7026d4a | 2009-03-24 14:02:43 +0800 | [diff] [blame] | 1655 | { DRM_MODE("400x300", DRM_MODE_TYPE_DRIVER, 9910, 400, 401, 464, |
| 1656 | 496, 0, 300, 301, 332, 333, 0, |
Jesse Barnes | e2f0ba9 | 2009-02-02 15:11:52 -0800 | [diff] [blame] | 1657 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, |
Zhenyu Wang | 7026d4a | 2009-03-24 14:02:43 +0800 | [diff] [blame] | 1658 | { DRM_MODE("640x350", DRM_MODE_TYPE_DRIVER, 16913, 640, 641, 704, |
| 1659 | 736, 0, 350, 351, 382, 383, 0, |
Jesse Barnes | e2f0ba9 | 2009-02-02 15:11:52 -0800 | [diff] [blame] | 1660 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, |
Zhenyu Wang | 7026d4a | 2009-03-24 14:02:43 +0800 | [diff] [blame] | 1661 | { DRM_MODE("640x400", DRM_MODE_TYPE_DRIVER, 19121, 640, 641, 704, |
| 1662 | 736, 0, 400, 401, 432, 433, 0, |
Jesse Barnes | e2f0ba9 | 2009-02-02 15:11:52 -0800 | [diff] [blame] | 1663 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, |
Zhenyu Wang | 7026d4a | 2009-03-24 14:02:43 +0800 | [diff] [blame] | 1664 | { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 22654, 640, 641, 704, |
| 1665 | 736, 0, 480, 481, 512, 513, 0, |
Jesse Barnes | e2f0ba9 | 2009-02-02 15:11:52 -0800 | [diff] [blame] | 1666 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, |
Zhenyu Wang | 7026d4a | 2009-03-24 14:02:43 +0800 | [diff] [blame] | 1667 | { DRM_MODE("704x480", DRM_MODE_TYPE_DRIVER, 24624, 704, 705, 768, |
| 1668 | 800, 0, 480, 481, 512, 513, 0, |
Jesse Barnes | e2f0ba9 | 2009-02-02 15:11:52 -0800 | [diff] [blame] | 1669 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, |
Zhenyu Wang | 7026d4a | 2009-03-24 14:02:43 +0800 | [diff] [blame] | 1670 | { DRM_MODE("704x576", DRM_MODE_TYPE_DRIVER, 29232, 704, 705, 768, |
| 1671 | 800, 0, 576, 577, 608, 609, 0, |
Jesse Barnes | e2f0ba9 | 2009-02-02 15:11:52 -0800 | [diff] [blame] | 1672 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, |
Zhenyu Wang | 7026d4a | 2009-03-24 14:02:43 +0800 | [diff] [blame] | 1673 | { DRM_MODE("720x350", DRM_MODE_TYPE_DRIVER, 18751, 720, 721, 784, |
| 1674 | 816, 0, 350, 351, 382, 383, 0, |
Jesse Barnes | e2f0ba9 | 2009-02-02 15:11:52 -0800 | [diff] [blame] | 1675 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, |
Zhenyu Wang | 7026d4a | 2009-03-24 14:02:43 +0800 | [diff] [blame] | 1676 | { DRM_MODE("720x400", DRM_MODE_TYPE_DRIVER, 21199, 720, 721, 784, |
| 1677 | 816, 0, 400, 401, 432, 433, 0, |
Jesse Barnes | e2f0ba9 | 2009-02-02 15:11:52 -0800 | [diff] [blame] | 1678 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, |
Zhenyu Wang | 7026d4a | 2009-03-24 14:02:43 +0800 | [diff] [blame] | 1679 | { DRM_MODE("720x480", DRM_MODE_TYPE_DRIVER, 25116, 720, 721, 784, |
| 1680 | 816, 0, 480, 481, 512, 513, 0, |
Jesse Barnes | e2f0ba9 | 2009-02-02 15:11:52 -0800 | [diff] [blame] | 1681 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, |
Zhenyu Wang | 7026d4a | 2009-03-24 14:02:43 +0800 | [diff] [blame] | 1682 | { DRM_MODE("720x540", DRM_MODE_TYPE_DRIVER, 28054, 720, 721, 784, |
| 1683 | 816, 0, 540, 541, 572, 573, 0, |
Jesse Barnes | e2f0ba9 | 2009-02-02 15:11:52 -0800 | [diff] [blame] | 1684 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, |
Zhenyu Wang | 7026d4a | 2009-03-24 14:02:43 +0800 | [diff] [blame] | 1685 | { DRM_MODE("720x576", DRM_MODE_TYPE_DRIVER, 29816, 720, 721, 784, |
| 1686 | 816, 0, 576, 577, 608, 609, 0, |
Jesse Barnes | e2f0ba9 | 2009-02-02 15:11:52 -0800 | [diff] [blame] | 1687 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, |
Zhenyu Wang | 7026d4a | 2009-03-24 14:02:43 +0800 | [diff] [blame] | 1688 | { DRM_MODE("768x576", DRM_MODE_TYPE_DRIVER, 31570, 768, 769, 832, |
| 1689 | 864, 0, 576, 577, 608, 609, 0, |
Jesse Barnes | e2f0ba9 | 2009-02-02 15:11:52 -0800 | [diff] [blame] | 1690 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, |
Zhenyu Wang | 7026d4a | 2009-03-24 14:02:43 +0800 | [diff] [blame] | 1691 | { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 34030, 800, 801, 864, |
| 1692 | 896, 0, 600, 601, 632, 633, 0, |
Jesse Barnes | e2f0ba9 | 2009-02-02 15:11:52 -0800 | [diff] [blame] | 1693 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, |
Zhenyu Wang | 7026d4a | 2009-03-24 14:02:43 +0800 | [diff] [blame] | 1694 | { DRM_MODE("832x624", DRM_MODE_TYPE_DRIVER, 36581, 832, 833, 896, |
| 1695 | 928, 0, 624, 625, 656, 657, 0, |
Jesse Barnes | e2f0ba9 | 2009-02-02 15:11:52 -0800 | [diff] [blame] | 1696 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, |
Zhenyu Wang | 7026d4a | 2009-03-24 14:02:43 +0800 | [diff] [blame] | 1697 | { DRM_MODE("920x766", DRM_MODE_TYPE_DRIVER, 48707, 920, 921, 984, |
| 1698 | 1016, 0, 766, 767, 798, 799, 0, |
Jesse Barnes | e2f0ba9 | 2009-02-02 15:11:52 -0800 | [diff] [blame] | 1699 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, |
Zhenyu Wang | 7026d4a | 2009-03-24 14:02:43 +0800 | [diff] [blame] | 1700 | { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 53827, 1024, 1025, 1088, |
| 1701 | 1120, 0, 768, 769, 800, 801, 0, |
Jesse Barnes | e2f0ba9 | 2009-02-02 15:11:52 -0800 | [diff] [blame] | 1702 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, |
Zhenyu Wang | 7026d4a | 2009-03-24 14:02:43 +0800 | [diff] [blame] | 1703 | { DRM_MODE("1280x1024", DRM_MODE_TYPE_DRIVER, 87265, 1280, 1281, 1344, |
| 1704 | 1376, 0, 1024, 1025, 1056, 1057, 0, |
Jesse Barnes | e2f0ba9 | 2009-02-02 15:11:52 -0800 | [diff] [blame] | 1705 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, |
| 1706 | }; |
| 1707 | |
| 1708 | static void intel_sdvo_get_tv_modes(struct drm_connector *connector) |
| 1709 | { |
Zhenyu Wang | d2a82a6 | 2010-03-29 21:22:55 +0800 | [diff] [blame] | 1710 | struct drm_encoder *encoder = intel_attached_encoder(connector); |
| 1711 | struct intel_encoder *intel_encoder = enc_to_intel_encoder(encoder); |
| 1712 | struct intel_sdvo_priv *sdvo_priv = intel_encoder->dev_priv; |
Zhenyu Wang | 7026d4a | 2009-03-24 14:02:43 +0800 | [diff] [blame] | 1713 | struct intel_sdvo_sdtv_resolution_request tv_res; |
Zhao Yakui | ce6feab | 2009-08-24 13:50:26 +0800 | [diff] [blame] | 1714 | uint32_t reply = 0, format_map = 0; |
| 1715 | int i; |
Jesse Barnes | e2f0ba9 | 2009-02-02 15:11:52 -0800 | [diff] [blame] | 1716 | uint8_t status; |
Jesse Barnes | e2f0ba9 | 2009-02-02 15:11:52 -0800 | [diff] [blame] | 1717 | |
Jesse Barnes | e2f0ba9 | 2009-02-02 15:11:52 -0800 | [diff] [blame] | 1718 | |
| 1719 | /* Read the list of supported input resolutions for the selected TV |
| 1720 | * format. |
| 1721 | */ |
Zhao Yakui | ce6feab | 2009-08-24 13:50:26 +0800 | [diff] [blame] | 1722 | for (i = 0; i < TV_FORMAT_NUM; i++) |
| 1723 | if (tv_format_names[i] == sdvo_priv->tv_format_name) |
| 1724 | break; |
| 1725 | |
| 1726 | format_map = (1 << i); |
| 1727 | memcpy(&tv_res, &format_map, |
| 1728 | sizeof(struct intel_sdvo_sdtv_resolution_request) > |
| 1729 | sizeof(format_map) ? sizeof(format_map) : |
| 1730 | sizeof(struct intel_sdvo_sdtv_resolution_request)); |
| 1731 | |
Zhenyu Wang | 14571b4 | 2010-03-30 14:06:33 +0800 | [diff] [blame] | 1732 | intel_sdvo_set_target_output(intel_encoder, sdvo_priv->attached_output); |
Zhao Yakui | ce6feab | 2009-08-24 13:50:26 +0800 | [diff] [blame] | 1733 | |
Zhenyu Wang | d2a82a6 | 2010-03-29 21:22:55 +0800 | [diff] [blame] | 1734 | intel_sdvo_write_cmd(intel_encoder, SDVO_CMD_GET_SDTV_RESOLUTION_SUPPORT, |
Zhenyu Wang | 7026d4a | 2009-03-24 14:02:43 +0800 | [diff] [blame] | 1735 | &tv_res, sizeof(tv_res)); |
Zhenyu Wang | d2a82a6 | 2010-03-29 21:22:55 +0800 | [diff] [blame] | 1736 | status = intel_sdvo_read_response(intel_encoder, &reply, 3); |
Jesse Barnes | e2f0ba9 | 2009-02-02 15:11:52 -0800 | [diff] [blame] | 1737 | if (status != SDVO_CMD_STATUS_SUCCESS) |
| 1738 | return; |
| 1739 | |
| 1740 | for (i = 0; i < ARRAY_SIZE(sdvo_tv_modes); i++) |
Zhenyu Wang | 7026d4a | 2009-03-24 14:02:43 +0800 | [diff] [blame] | 1741 | if (reply & (1 << i)) { |
| 1742 | struct drm_display_mode *nmode; |
| 1743 | nmode = drm_mode_duplicate(connector->dev, |
| 1744 | &sdvo_tv_modes[i]); |
| 1745 | if (nmode) |
| 1746 | drm_mode_probed_add(connector, nmode); |
| 1747 | } |
Zhao Yakui | ce6feab | 2009-08-24 13:50:26 +0800 | [diff] [blame] | 1748 | |
Jesse Barnes | e2f0ba9 | 2009-02-02 15:11:52 -0800 | [diff] [blame] | 1749 | } |
| 1750 | |
Ma Ling | 7086c87 | 2009-05-13 11:20:06 +0800 | [diff] [blame] | 1751 | static void intel_sdvo_get_lvds_modes(struct drm_connector *connector) |
| 1752 | { |
Zhenyu Wang | d2a82a6 | 2010-03-29 21:22:55 +0800 | [diff] [blame] | 1753 | struct drm_encoder *encoder = intel_attached_encoder(connector); |
| 1754 | struct intel_encoder *intel_encoder = enc_to_intel_encoder(encoder); |
Ma Ling | 7086c87 | 2009-05-13 11:20:06 +0800 | [diff] [blame] | 1755 | struct drm_i915_private *dev_priv = connector->dev->dev_private; |
Eric Anholt | 21d40d3 | 2010-03-25 11:11:14 -0700 | [diff] [blame] | 1756 | struct intel_sdvo_priv *sdvo_priv = intel_encoder->dev_priv; |
ling.ma@intel.com | 12682a9 | 2009-06-30 11:35:35 +0800 | [diff] [blame] | 1757 | struct drm_display_mode *newmode; |
Ma Ling | 7086c87 | 2009-05-13 11:20:06 +0800 | [diff] [blame] | 1758 | |
| 1759 | /* |
| 1760 | * Attempt to get the mode list from DDC. |
| 1761 | * Assume that the preferred modes are |
| 1762 | * arranged in priority order. |
| 1763 | */ |
Zhenyu Wang | 335af9a | 2010-03-30 14:39:31 +0800 | [diff] [blame] | 1764 | intel_ddc_get_modes(connector, intel_encoder->ddc_bus); |
Ma Ling | 7086c87 | 2009-05-13 11:20:06 +0800 | [diff] [blame] | 1765 | if (list_empty(&connector->probed_modes) == false) |
ling.ma@intel.com | 12682a9 | 2009-06-30 11:35:35 +0800 | [diff] [blame] | 1766 | goto end; |
Ma Ling | 7086c87 | 2009-05-13 11:20:06 +0800 | [diff] [blame] | 1767 | |
| 1768 | /* Fetch modes from VBT */ |
| 1769 | if (dev_priv->sdvo_lvds_vbt_mode != NULL) { |
Ma Ling | 7086c87 | 2009-05-13 11:20:06 +0800 | [diff] [blame] | 1770 | newmode = drm_mode_duplicate(connector->dev, |
| 1771 | dev_priv->sdvo_lvds_vbt_mode); |
| 1772 | if (newmode != NULL) { |
| 1773 | /* Guarantee the mode is preferred */ |
| 1774 | newmode->type = (DRM_MODE_TYPE_PREFERRED | |
| 1775 | DRM_MODE_TYPE_DRIVER); |
| 1776 | drm_mode_probed_add(connector, newmode); |
| 1777 | } |
| 1778 | } |
ling.ma@intel.com | 12682a9 | 2009-06-30 11:35:35 +0800 | [diff] [blame] | 1779 | |
| 1780 | end: |
| 1781 | list_for_each_entry(newmode, &connector->probed_modes, head) { |
| 1782 | if (newmode->type & DRM_MODE_TYPE_PREFERRED) { |
| 1783 | sdvo_priv->sdvo_lvds_fixed_mode = |
| 1784 | drm_mode_duplicate(connector->dev, newmode); |
| 1785 | break; |
| 1786 | } |
| 1787 | } |
| 1788 | |
Ma Ling | 7086c87 | 2009-05-13 11:20:06 +0800 | [diff] [blame] | 1789 | } |
| 1790 | |
Jesse Barnes | e2f0ba9 | 2009-02-02 15:11:52 -0800 | [diff] [blame] | 1791 | static int intel_sdvo_get_modes(struct drm_connector *connector) |
| 1792 | { |
Zhenyu Wang | 14571b4 | 2010-03-30 14:06:33 +0800 | [diff] [blame] | 1793 | struct intel_connector *intel_connector = to_intel_connector(connector); |
| 1794 | struct intel_sdvo_connector *sdvo_connector = intel_connector->dev_priv; |
Jesse Barnes | e2f0ba9 | 2009-02-02 15:11:52 -0800 | [diff] [blame] | 1795 | |
Zhenyu Wang | 14571b4 | 2010-03-30 14:06:33 +0800 | [diff] [blame] | 1796 | if (IS_TV(sdvo_connector)) |
Jesse Barnes | e2f0ba9 | 2009-02-02 15:11:52 -0800 | [diff] [blame] | 1797 | intel_sdvo_get_tv_modes(connector); |
Zhenyu Wang | 14571b4 | 2010-03-30 14:06:33 +0800 | [diff] [blame] | 1798 | else if (IS_LVDS(sdvo_connector)) |
Ma Ling | 7086c87 | 2009-05-13 11:20:06 +0800 | [diff] [blame] | 1799 | intel_sdvo_get_lvds_modes(connector); |
Jesse Barnes | e2f0ba9 | 2009-02-02 15:11:52 -0800 | [diff] [blame] | 1800 | else |
| 1801 | intel_sdvo_get_ddc_modes(connector); |
| 1802 | |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 1803 | if (list_empty(&connector->probed_modes)) |
| 1804 | return 0; |
| 1805 | return 1; |
| 1806 | } |
| 1807 | |
Zhao Yakui | b9219c5 | 2009-09-10 15:45:46 +0800 | [diff] [blame] | 1808 | static |
| 1809 | void intel_sdvo_destroy_enhance_property(struct drm_connector *connector) |
| 1810 | { |
Zhenyu Wang | 14571b4 | 2010-03-30 14:06:33 +0800 | [diff] [blame] | 1811 | struct intel_connector *intel_connector = to_intel_connector(connector); |
| 1812 | struct intel_sdvo_connector *sdvo_priv = intel_connector->dev_priv; |
| 1813 | struct drm_device *dev = connector->dev; |
Zhao Yakui | b9219c5 | 2009-09-10 15:45:46 +0800 | [diff] [blame] | 1814 | |
Zhenyu Wang | 14571b4 | 2010-03-30 14:06:33 +0800 | [diff] [blame] | 1815 | if (IS_TV(sdvo_priv)) { |
Zhao Yakui | b9219c5 | 2009-09-10 15:45:46 +0800 | [diff] [blame] | 1816 | if (sdvo_priv->left_property) |
| 1817 | drm_property_destroy(dev, sdvo_priv->left_property); |
| 1818 | if (sdvo_priv->right_property) |
| 1819 | drm_property_destroy(dev, sdvo_priv->right_property); |
| 1820 | if (sdvo_priv->top_property) |
| 1821 | drm_property_destroy(dev, sdvo_priv->top_property); |
| 1822 | if (sdvo_priv->bottom_property) |
| 1823 | drm_property_destroy(dev, sdvo_priv->bottom_property); |
| 1824 | if (sdvo_priv->hpos_property) |
| 1825 | drm_property_destroy(dev, sdvo_priv->hpos_property); |
| 1826 | if (sdvo_priv->vpos_property) |
| 1827 | drm_property_destroy(dev, sdvo_priv->vpos_property); |
Zhao Yakui | b9219c5 | 2009-09-10 15:45:46 +0800 | [diff] [blame] | 1828 | if (sdvo_priv->saturation_property) |
| 1829 | drm_property_destroy(dev, |
| 1830 | sdvo_priv->saturation_property); |
| 1831 | if (sdvo_priv->contrast_property) |
| 1832 | drm_property_destroy(dev, |
| 1833 | sdvo_priv->contrast_property); |
| 1834 | if (sdvo_priv->hue_property) |
| 1835 | drm_property_destroy(dev, sdvo_priv->hue_property); |
| 1836 | } |
Zhenyu Wang | 14571b4 | 2010-03-30 14:06:33 +0800 | [diff] [blame] | 1837 | if (IS_TV(sdvo_priv) || IS_LVDS(sdvo_priv)) { |
Zhao Yakui | b9219c5 | 2009-09-10 15:45:46 +0800 | [diff] [blame] | 1838 | if (sdvo_priv->brightness_property) |
| 1839 | drm_property_destroy(dev, |
| 1840 | sdvo_priv->brightness_property); |
| 1841 | } |
| 1842 | return; |
| 1843 | } |
| 1844 | |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 1845 | static void intel_sdvo_destroy(struct drm_connector *connector) |
| 1846 | { |
Zhenyu Wang | 14571b4 | 2010-03-30 14:06:33 +0800 | [diff] [blame] | 1847 | struct intel_connector *intel_connector = to_intel_connector(connector); |
| 1848 | struct intel_sdvo_connector *sdvo_connector = intel_connector->dev_priv; |
| 1849 | |
| 1850 | if (sdvo_connector->tv_format_property) |
| 1851 | drm_property_destroy(connector->dev, |
| 1852 | sdvo_connector->tv_format_property); |
| 1853 | |
Zhenyu Wang | d2a82a6 | 2010-03-29 21:22:55 +0800 | [diff] [blame] | 1854 | intel_sdvo_destroy_enhance_property(connector); |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 1855 | drm_sysfs_connector_remove(connector); |
| 1856 | drm_connector_cleanup(connector); |
Zhenyu Wang | d2a82a6 | 2010-03-29 21:22:55 +0800 | [diff] [blame] | 1857 | kfree(connector); |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 1858 | } |
| 1859 | |
Zhao Yakui | ce6feab | 2009-08-24 13:50:26 +0800 | [diff] [blame] | 1860 | static int |
| 1861 | intel_sdvo_set_property(struct drm_connector *connector, |
| 1862 | struct drm_property *property, |
| 1863 | uint64_t val) |
| 1864 | { |
Zhenyu Wang | d2a82a6 | 2010-03-29 21:22:55 +0800 | [diff] [blame] | 1865 | struct drm_encoder *encoder = intel_attached_encoder(connector); |
| 1866 | struct intel_encoder *intel_encoder = enc_to_intel_encoder(encoder); |
Eric Anholt | 21d40d3 | 2010-03-25 11:11:14 -0700 | [diff] [blame] | 1867 | struct intel_sdvo_priv *sdvo_priv = intel_encoder->dev_priv; |
Zhenyu Wang | 14571b4 | 2010-03-30 14:06:33 +0800 | [diff] [blame] | 1868 | struct intel_connector *intel_connector = to_intel_connector(connector); |
| 1869 | struct intel_sdvo_connector *sdvo_connector = intel_connector->dev_priv; |
Zhao Yakui | ce6feab | 2009-08-24 13:50:26 +0800 | [diff] [blame] | 1870 | struct drm_crtc *crtc = encoder->crtc; |
| 1871 | int ret = 0; |
| 1872 | bool changed = false; |
Zhao Yakui | b9219c5 | 2009-09-10 15:45:46 +0800 | [diff] [blame] | 1873 | uint8_t cmd, status; |
| 1874 | uint16_t temp_value; |
Zhao Yakui | ce6feab | 2009-08-24 13:50:26 +0800 | [diff] [blame] | 1875 | |
| 1876 | ret = drm_connector_property_set_value(connector, property, val); |
| 1877 | if (ret < 0) |
| 1878 | goto out; |
| 1879 | |
Zhenyu Wang | 14571b4 | 2010-03-30 14:06:33 +0800 | [diff] [blame] | 1880 | if (property == sdvo_connector->tv_format_property) { |
Zhao Yakui | ce6feab | 2009-08-24 13:50:26 +0800 | [diff] [blame] | 1881 | if (val >= TV_FORMAT_NUM) { |
| 1882 | ret = -EINVAL; |
| 1883 | goto out; |
| 1884 | } |
| 1885 | if (sdvo_priv->tv_format_name == |
Zhenyu Wang | 14571b4 | 2010-03-30 14:06:33 +0800 | [diff] [blame] | 1886 | sdvo_connector->tv_format_supported[val]) |
Zhao Yakui | ce6feab | 2009-08-24 13:50:26 +0800 | [diff] [blame] | 1887 | goto out; |
| 1888 | |
Zhenyu Wang | 14571b4 | 2010-03-30 14:06:33 +0800 | [diff] [blame] | 1889 | sdvo_priv->tv_format_name = sdvo_connector->tv_format_supported[val]; |
Zhao Yakui | ce6feab | 2009-08-24 13:50:26 +0800 | [diff] [blame] | 1890 | changed = true; |
Zhao Yakui | ce6feab | 2009-08-24 13:50:26 +0800 | [diff] [blame] | 1891 | } |
| 1892 | |
Zhenyu Wang | 14571b4 | 2010-03-30 14:06:33 +0800 | [diff] [blame] | 1893 | if (IS_TV(sdvo_connector) || IS_LVDS(sdvo_connector)) { |
Zhao Yakui | b9219c5 | 2009-09-10 15:45:46 +0800 | [diff] [blame] | 1894 | cmd = 0; |
| 1895 | temp_value = val; |
Zhenyu Wang | 14571b4 | 2010-03-30 14:06:33 +0800 | [diff] [blame] | 1896 | if (sdvo_connector->left_property == property) { |
Zhao Yakui | b9219c5 | 2009-09-10 15:45:46 +0800 | [diff] [blame] | 1897 | drm_connector_property_set_value(connector, |
Zhenyu Wang | 14571b4 | 2010-03-30 14:06:33 +0800 | [diff] [blame] | 1898 | sdvo_connector->right_property, val); |
| 1899 | if (sdvo_connector->left_margin == temp_value) |
Zhao Yakui | b9219c5 | 2009-09-10 15:45:46 +0800 | [diff] [blame] | 1900 | goto out; |
| 1901 | |
Zhenyu Wang | 14571b4 | 2010-03-30 14:06:33 +0800 | [diff] [blame] | 1902 | sdvo_connector->left_margin = temp_value; |
| 1903 | sdvo_connector->right_margin = temp_value; |
| 1904 | temp_value = sdvo_connector->max_hscan - |
| 1905 | sdvo_connector->left_margin; |
Zhao Yakui | b9219c5 | 2009-09-10 15:45:46 +0800 | [diff] [blame] | 1906 | cmd = SDVO_CMD_SET_OVERSCAN_H; |
Zhenyu Wang | 14571b4 | 2010-03-30 14:06:33 +0800 | [diff] [blame] | 1907 | } else if (sdvo_connector->right_property == property) { |
Zhao Yakui | b9219c5 | 2009-09-10 15:45:46 +0800 | [diff] [blame] | 1908 | drm_connector_property_set_value(connector, |
Zhenyu Wang | 14571b4 | 2010-03-30 14:06:33 +0800 | [diff] [blame] | 1909 | sdvo_connector->left_property, val); |
| 1910 | if (sdvo_connector->right_margin == temp_value) |
Zhao Yakui | b9219c5 | 2009-09-10 15:45:46 +0800 | [diff] [blame] | 1911 | goto out; |
| 1912 | |
Zhenyu Wang | 14571b4 | 2010-03-30 14:06:33 +0800 | [diff] [blame] | 1913 | sdvo_connector->left_margin = temp_value; |
| 1914 | sdvo_connector->right_margin = temp_value; |
| 1915 | temp_value = sdvo_connector->max_hscan - |
| 1916 | sdvo_connector->left_margin; |
Zhao Yakui | b9219c5 | 2009-09-10 15:45:46 +0800 | [diff] [blame] | 1917 | cmd = SDVO_CMD_SET_OVERSCAN_H; |
Zhenyu Wang | 14571b4 | 2010-03-30 14:06:33 +0800 | [diff] [blame] | 1918 | } else if (sdvo_connector->top_property == property) { |
Zhao Yakui | b9219c5 | 2009-09-10 15:45:46 +0800 | [diff] [blame] | 1919 | drm_connector_property_set_value(connector, |
Zhenyu Wang | 14571b4 | 2010-03-30 14:06:33 +0800 | [diff] [blame] | 1920 | sdvo_connector->bottom_property, val); |
| 1921 | if (sdvo_connector->top_margin == temp_value) |
Zhao Yakui | b9219c5 | 2009-09-10 15:45:46 +0800 | [diff] [blame] | 1922 | goto out; |
| 1923 | |
Zhenyu Wang | 14571b4 | 2010-03-30 14:06:33 +0800 | [diff] [blame] | 1924 | sdvo_connector->top_margin = temp_value; |
| 1925 | sdvo_connector->bottom_margin = temp_value; |
| 1926 | temp_value = sdvo_connector->max_vscan - |
| 1927 | sdvo_connector->top_margin; |
Zhao Yakui | b9219c5 | 2009-09-10 15:45:46 +0800 | [diff] [blame] | 1928 | cmd = SDVO_CMD_SET_OVERSCAN_V; |
Zhenyu Wang | 14571b4 | 2010-03-30 14:06:33 +0800 | [diff] [blame] | 1929 | } else if (sdvo_connector->bottom_property == property) { |
Zhao Yakui | b9219c5 | 2009-09-10 15:45:46 +0800 | [diff] [blame] | 1930 | drm_connector_property_set_value(connector, |
Zhenyu Wang | 14571b4 | 2010-03-30 14:06:33 +0800 | [diff] [blame] | 1931 | sdvo_connector->top_property, val); |
| 1932 | if (sdvo_connector->bottom_margin == temp_value) |
Zhao Yakui | b9219c5 | 2009-09-10 15:45:46 +0800 | [diff] [blame] | 1933 | goto out; |
Zhenyu Wang | 14571b4 | 2010-03-30 14:06:33 +0800 | [diff] [blame] | 1934 | sdvo_connector->top_margin = temp_value; |
| 1935 | sdvo_connector->bottom_margin = temp_value; |
| 1936 | temp_value = sdvo_connector->max_vscan - |
| 1937 | sdvo_connector->top_margin; |
Zhao Yakui | b9219c5 | 2009-09-10 15:45:46 +0800 | [diff] [blame] | 1938 | cmd = SDVO_CMD_SET_OVERSCAN_V; |
Zhenyu Wang | 14571b4 | 2010-03-30 14:06:33 +0800 | [diff] [blame] | 1939 | } else if (sdvo_connector->hpos_property == property) { |
| 1940 | if (sdvo_connector->cur_hpos == temp_value) |
Zhao Yakui | b9219c5 | 2009-09-10 15:45:46 +0800 | [diff] [blame] | 1941 | goto out; |
| 1942 | |
| 1943 | cmd = SDVO_CMD_SET_POSITION_H; |
Zhenyu Wang | 14571b4 | 2010-03-30 14:06:33 +0800 | [diff] [blame] | 1944 | sdvo_connector->cur_hpos = temp_value; |
| 1945 | } else if (sdvo_connector->vpos_property == property) { |
| 1946 | if (sdvo_connector->cur_vpos == temp_value) |
Zhao Yakui | b9219c5 | 2009-09-10 15:45:46 +0800 | [diff] [blame] | 1947 | goto out; |
| 1948 | |
| 1949 | cmd = SDVO_CMD_SET_POSITION_V; |
Zhenyu Wang | 14571b4 | 2010-03-30 14:06:33 +0800 | [diff] [blame] | 1950 | sdvo_connector->cur_vpos = temp_value; |
| 1951 | } else if (sdvo_connector->saturation_property == property) { |
| 1952 | if (sdvo_connector->cur_saturation == temp_value) |
Zhao Yakui | b9219c5 | 2009-09-10 15:45:46 +0800 | [diff] [blame] | 1953 | goto out; |
| 1954 | |
| 1955 | cmd = SDVO_CMD_SET_SATURATION; |
Zhenyu Wang | 14571b4 | 2010-03-30 14:06:33 +0800 | [diff] [blame] | 1956 | sdvo_connector->cur_saturation = temp_value; |
| 1957 | } else if (sdvo_connector->contrast_property == property) { |
| 1958 | if (sdvo_connector->cur_contrast == temp_value) |
Zhao Yakui | b9219c5 | 2009-09-10 15:45:46 +0800 | [diff] [blame] | 1959 | goto out; |
| 1960 | |
| 1961 | cmd = SDVO_CMD_SET_CONTRAST; |
Zhenyu Wang | 14571b4 | 2010-03-30 14:06:33 +0800 | [diff] [blame] | 1962 | sdvo_connector->cur_contrast = temp_value; |
| 1963 | } else if (sdvo_connector->hue_property == property) { |
| 1964 | if (sdvo_connector->cur_hue == temp_value) |
Zhao Yakui | b9219c5 | 2009-09-10 15:45:46 +0800 | [diff] [blame] | 1965 | goto out; |
| 1966 | |
| 1967 | cmd = SDVO_CMD_SET_HUE; |
Zhenyu Wang | 14571b4 | 2010-03-30 14:06:33 +0800 | [diff] [blame] | 1968 | sdvo_connector->cur_hue = temp_value; |
| 1969 | } else if (sdvo_connector->brightness_property == property) { |
| 1970 | if (sdvo_connector->cur_brightness == temp_value) |
Zhao Yakui | b9219c5 | 2009-09-10 15:45:46 +0800 | [diff] [blame] | 1971 | goto out; |
| 1972 | |
| 1973 | cmd = SDVO_CMD_SET_BRIGHTNESS; |
Zhenyu Wang | 14571b4 | 2010-03-30 14:06:33 +0800 | [diff] [blame] | 1974 | sdvo_connector->cur_brightness = temp_value; |
Zhao Yakui | b9219c5 | 2009-09-10 15:45:46 +0800 | [diff] [blame] | 1975 | } |
| 1976 | if (cmd) { |
Eric Anholt | 21d40d3 | 2010-03-25 11:11:14 -0700 | [diff] [blame] | 1977 | intel_sdvo_write_cmd(intel_encoder, cmd, &temp_value, 2); |
| 1978 | status = intel_sdvo_read_response(intel_encoder, |
Zhao Yakui | b9219c5 | 2009-09-10 15:45:46 +0800 | [diff] [blame] | 1979 | NULL, 0); |
| 1980 | if (status != SDVO_CMD_STATUS_SUCCESS) { |
| 1981 | DRM_DEBUG_KMS("Incorrect SDVO command \n"); |
| 1982 | return -EINVAL; |
| 1983 | } |
| 1984 | changed = true; |
| 1985 | } |
| 1986 | } |
Zhao Yakui | ce6feab | 2009-08-24 13:50:26 +0800 | [diff] [blame] | 1987 | if (changed && crtc) |
| 1988 | drm_crtc_helper_set_mode(crtc, &crtc->mode, crtc->x, |
| 1989 | crtc->y, crtc->fb); |
| 1990 | out: |
| 1991 | return ret; |
| 1992 | } |
| 1993 | |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 1994 | static const struct drm_encoder_helper_funcs intel_sdvo_helper_funcs = { |
| 1995 | .dpms = intel_sdvo_dpms, |
| 1996 | .mode_fixup = intel_sdvo_mode_fixup, |
| 1997 | .prepare = intel_encoder_prepare, |
| 1998 | .mode_set = intel_sdvo_mode_set, |
| 1999 | .commit = intel_encoder_commit, |
| 2000 | }; |
| 2001 | |
| 2002 | static const struct drm_connector_funcs intel_sdvo_connector_funcs = { |
Keith Packard | c9fb15f | 2009-05-30 20:42:28 -0700 | [diff] [blame] | 2003 | .dpms = drm_helper_connector_dpms, |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 2004 | .detect = intel_sdvo_detect, |
| 2005 | .fill_modes = drm_helper_probe_single_connector_modes, |
Zhao Yakui | ce6feab | 2009-08-24 13:50:26 +0800 | [diff] [blame] | 2006 | .set_property = intel_sdvo_set_property, |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 2007 | .destroy = intel_sdvo_destroy, |
| 2008 | }; |
| 2009 | |
| 2010 | static const struct drm_connector_helper_funcs intel_sdvo_connector_helper_funcs = { |
| 2011 | .get_modes = intel_sdvo_get_modes, |
| 2012 | .mode_valid = intel_sdvo_mode_valid, |
Zhenyu Wang | d2a82a6 | 2010-03-29 21:22:55 +0800 | [diff] [blame] | 2013 | .best_encoder = intel_attached_encoder, |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 2014 | }; |
| 2015 | |
Hannes Eder | b358d0a | 2008-12-18 21:18:47 +0100 | [diff] [blame] | 2016 | static void intel_sdvo_enc_destroy(struct drm_encoder *encoder) |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 2017 | { |
Zhenyu Wang | d2a82a6 | 2010-03-29 21:22:55 +0800 | [diff] [blame] | 2018 | struct intel_encoder *intel_encoder = enc_to_intel_encoder(encoder); |
| 2019 | struct intel_sdvo_priv *sdvo_priv = intel_encoder->dev_priv; |
| 2020 | |
| 2021 | if (intel_encoder->i2c_bus) |
| 2022 | intel_i2c_destroy(intel_encoder->i2c_bus); |
| 2023 | if (intel_encoder->ddc_bus) |
| 2024 | intel_i2c_destroy(intel_encoder->ddc_bus); |
| 2025 | if (sdvo_priv->analog_ddc_bus) |
| 2026 | intel_i2c_destroy(sdvo_priv->analog_ddc_bus); |
| 2027 | |
| 2028 | if (sdvo_priv->sdvo_lvds_fixed_mode != NULL) |
| 2029 | drm_mode_destroy(encoder->dev, |
| 2030 | sdvo_priv->sdvo_lvds_fixed_mode); |
| 2031 | |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 2032 | drm_encoder_cleanup(encoder); |
Zhenyu Wang | d2a82a6 | 2010-03-29 21:22:55 +0800 | [diff] [blame] | 2033 | kfree(intel_encoder); |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 2034 | } |
| 2035 | |
| 2036 | static const struct drm_encoder_funcs intel_sdvo_enc_funcs = { |
| 2037 | .destroy = intel_sdvo_enc_destroy, |
| 2038 | }; |
| 2039 | |
| 2040 | |
Jesse Barnes | e2f0ba9 | 2009-02-02 15:11:52 -0800 | [diff] [blame] | 2041 | /** |
| 2042 | * Choose the appropriate DDC bus for control bus switch command for this |
| 2043 | * SDVO output based on the controlled output. |
| 2044 | * |
| 2045 | * DDC bus number assignment is in a priority order of RGB outputs, then TMDS |
| 2046 | * outputs, then LVDS outputs. |
| 2047 | */ |
| 2048 | static void |
| 2049 | intel_sdvo_select_ddc_bus(struct intel_sdvo_priv *dev_priv) |
| 2050 | { |
| 2051 | uint16_t mask = 0; |
| 2052 | unsigned int num_bits; |
| 2053 | |
| 2054 | /* Make a mask of outputs less than or equal to our own priority in the |
| 2055 | * list. |
| 2056 | */ |
| 2057 | switch (dev_priv->controlled_output) { |
| 2058 | case SDVO_OUTPUT_LVDS1: |
| 2059 | mask |= SDVO_OUTPUT_LVDS1; |
| 2060 | case SDVO_OUTPUT_LVDS0: |
| 2061 | mask |= SDVO_OUTPUT_LVDS0; |
| 2062 | case SDVO_OUTPUT_TMDS1: |
| 2063 | mask |= SDVO_OUTPUT_TMDS1; |
| 2064 | case SDVO_OUTPUT_TMDS0: |
| 2065 | mask |= SDVO_OUTPUT_TMDS0; |
| 2066 | case SDVO_OUTPUT_RGB1: |
| 2067 | mask |= SDVO_OUTPUT_RGB1; |
| 2068 | case SDVO_OUTPUT_RGB0: |
| 2069 | mask |= SDVO_OUTPUT_RGB0; |
| 2070 | break; |
| 2071 | } |
| 2072 | |
| 2073 | /* Count bits to find what number we are in the priority list. */ |
| 2074 | mask &= dev_priv->caps.output_flags; |
| 2075 | num_bits = hweight16(mask); |
| 2076 | if (num_bits > 3) { |
| 2077 | /* if more than 3 outputs, default to DDC bus 3 for now */ |
| 2078 | num_bits = 3; |
| 2079 | } |
| 2080 | |
| 2081 | /* Corresponds to SDVO_CONTROL_BUS_DDCx */ |
| 2082 | dev_priv->ddc_bus = 1 << num_bits; |
| 2083 | } |
| 2084 | |
| 2085 | static bool |
Zhenyu Wang | 14571b4 | 2010-03-30 14:06:33 +0800 | [diff] [blame] | 2086 | intel_sdvo_get_digital_encoding_mode(struct intel_encoder *output, int device) |
Jesse Barnes | e2f0ba9 | 2009-02-02 15:11:52 -0800 | [diff] [blame] | 2087 | { |
| 2088 | struct intel_sdvo_priv *sdvo_priv = output->dev_priv; |
| 2089 | uint8_t status; |
| 2090 | |
Zhenyu Wang | 14571b4 | 2010-03-30 14:06:33 +0800 | [diff] [blame] | 2091 | if (device == 0) |
| 2092 | intel_sdvo_set_target_output(output, SDVO_OUTPUT_TMDS0); |
| 2093 | else |
| 2094 | intel_sdvo_set_target_output(output, SDVO_OUTPUT_TMDS1); |
Jesse Barnes | e2f0ba9 | 2009-02-02 15:11:52 -0800 | [diff] [blame] | 2095 | |
| 2096 | intel_sdvo_write_cmd(output, SDVO_CMD_GET_ENCODE, NULL, 0); |
| 2097 | status = intel_sdvo_read_response(output, &sdvo_priv->is_hdmi, 1); |
| 2098 | if (status != SDVO_CMD_STATUS_SUCCESS) |
| 2099 | return false; |
| 2100 | return true; |
| 2101 | } |
| 2102 | |
Eric Anholt | 21d40d3 | 2010-03-25 11:11:14 -0700 | [diff] [blame] | 2103 | static struct intel_encoder * |
| 2104 | intel_sdvo_chan_to_intel_encoder(struct intel_i2c_chan *chan) |
Ma Ling | 619ac3b | 2009-05-18 16:12:46 +0800 | [diff] [blame] | 2105 | { |
| 2106 | struct drm_device *dev = chan->drm_dev; |
Zhenyu Wang | d2a82a6 | 2010-03-29 21:22:55 +0800 | [diff] [blame] | 2107 | struct drm_encoder *encoder; |
Eric Anholt | 21d40d3 | 2010-03-25 11:11:14 -0700 | [diff] [blame] | 2108 | struct intel_encoder *intel_encoder = NULL; |
Ma Ling | 619ac3b | 2009-05-18 16:12:46 +0800 | [diff] [blame] | 2109 | |
Zhenyu Wang | d2a82a6 | 2010-03-29 21:22:55 +0800 | [diff] [blame] | 2110 | list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) { |
| 2111 | intel_encoder = enc_to_intel_encoder(encoder); |
| 2112 | if (intel_encoder->ddc_bus == &chan->adapter) |
Ma Ling | 619ac3b | 2009-05-18 16:12:46 +0800 | [diff] [blame] | 2113 | break; |
Ma Ling | 619ac3b | 2009-05-18 16:12:46 +0800 | [diff] [blame] | 2114 | } |
Eric Anholt | 21d40d3 | 2010-03-25 11:11:14 -0700 | [diff] [blame] | 2115 | return intel_encoder; |
Ma Ling | 619ac3b | 2009-05-18 16:12:46 +0800 | [diff] [blame] | 2116 | } |
| 2117 | |
| 2118 | static int intel_sdvo_master_xfer(struct i2c_adapter *i2c_adap, |
| 2119 | struct i2c_msg msgs[], int num) |
| 2120 | { |
Eric Anholt | 21d40d3 | 2010-03-25 11:11:14 -0700 | [diff] [blame] | 2121 | struct intel_encoder *intel_encoder; |
Ma Ling | 619ac3b | 2009-05-18 16:12:46 +0800 | [diff] [blame] | 2122 | struct intel_sdvo_priv *sdvo_priv; |
| 2123 | struct i2c_algo_bit_data *algo_data; |
Keith Packard | f9c10a9 | 2009-05-30 12:16:25 -0700 | [diff] [blame] | 2124 | const struct i2c_algorithm *algo; |
Ma Ling | 619ac3b | 2009-05-18 16:12:46 +0800 | [diff] [blame] | 2125 | |
| 2126 | algo_data = (struct i2c_algo_bit_data *)i2c_adap->algo_data; |
Eric Anholt | 21d40d3 | 2010-03-25 11:11:14 -0700 | [diff] [blame] | 2127 | intel_encoder = |
| 2128 | intel_sdvo_chan_to_intel_encoder( |
Ma Ling | 619ac3b | 2009-05-18 16:12:46 +0800 | [diff] [blame] | 2129 | (struct intel_i2c_chan *)(algo_data->data)); |
Eric Anholt | 21d40d3 | 2010-03-25 11:11:14 -0700 | [diff] [blame] | 2130 | if (intel_encoder == NULL) |
Ma Ling | 619ac3b | 2009-05-18 16:12:46 +0800 | [diff] [blame] | 2131 | return -EINVAL; |
| 2132 | |
Eric Anholt | 21d40d3 | 2010-03-25 11:11:14 -0700 | [diff] [blame] | 2133 | sdvo_priv = intel_encoder->dev_priv; |
| 2134 | algo = intel_encoder->i2c_bus->algo; |
Ma Ling | 619ac3b | 2009-05-18 16:12:46 +0800 | [diff] [blame] | 2135 | |
Eric Anholt | 21d40d3 | 2010-03-25 11:11:14 -0700 | [diff] [blame] | 2136 | intel_sdvo_set_control_bus_switch(intel_encoder, sdvo_priv->ddc_bus); |
Ma Ling | 619ac3b | 2009-05-18 16:12:46 +0800 | [diff] [blame] | 2137 | return algo->master_xfer(i2c_adap, msgs, num); |
| 2138 | } |
| 2139 | |
| 2140 | static struct i2c_algorithm intel_sdvo_i2c_bit_algo = { |
| 2141 | .master_xfer = intel_sdvo_master_xfer, |
| 2142 | }; |
| 2143 | |
yakui_zhao | 714605e | 2009-05-31 17:18:07 +0800 | [diff] [blame] | 2144 | static u8 |
Eric Anholt | c751ce4 | 2010-03-25 11:48:48 -0700 | [diff] [blame] | 2145 | intel_sdvo_get_slave_addr(struct drm_device *dev, int sdvo_reg) |
yakui_zhao | 714605e | 2009-05-31 17:18:07 +0800 | [diff] [blame] | 2146 | { |
| 2147 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 2148 | struct sdvo_device_mapping *my_mapping, *other_mapping; |
| 2149 | |
Eric Anholt | c751ce4 | 2010-03-25 11:48:48 -0700 | [diff] [blame] | 2150 | if (sdvo_reg == SDVOB) { |
yakui_zhao | 714605e | 2009-05-31 17:18:07 +0800 | [diff] [blame] | 2151 | my_mapping = &dev_priv->sdvo_mappings[0]; |
| 2152 | other_mapping = &dev_priv->sdvo_mappings[1]; |
| 2153 | } else { |
| 2154 | my_mapping = &dev_priv->sdvo_mappings[1]; |
| 2155 | other_mapping = &dev_priv->sdvo_mappings[0]; |
| 2156 | } |
| 2157 | |
| 2158 | /* If the BIOS described our SDVO device, take advantage of it. */ |
| 2159 | if (my_mapping->slave_addr) |
| 2160 | return my_mapping->slave_addr; |
| 2161 | |
| 2162 | /* If the BIOS only described a different SDVO device, use the |
| 2163 | * address that it isn't using. |
| 2164 | */ |
| 2165 | if (other_mapping->slave_addr) { |
| 2166 | if (other_mapping->slave_addr == 0x70) |
| 2167 | return 0x72; |
| 2168 | else |
| 2169 | return 0x70; |
| 2170 | } |
| 2171 | |
| 2172 | /* No SDVO device info is found for another DVO port, |
| 2173 | * so use mapping assumption we had before BIOS parsing. |
| 2174 | */ |
Eric Anholt | c751ce4 | 2010-03-25 11:48:48 -0700 | [diff] [blame] | 2175 | if (sdvo_reg == SDVOB) |
yakui_zhao | 714605e | 2009-05-31 17:18:07 +0800 | [diff] [blame] | 2176 | return 0x70; |
| 2177 | else |
| 2178 | return 0x72; |
| 2179 | } |
| 2180 | |
ling.ma@intel.com | fb7a46f | 2009-07-23 17:11:34 +0800 | [diff] [blame] | 2181 | static bool |
Zhenyu Wang | 14571b4 | 2010-03-30 14:06:33 +0800 | [diff] [blame] | 2182 | intel_sdvo_connector_alloc (struct intel_connector **ret) |
ling.ma@intel.com | fb7a46f | 2009-07-23 17:11:34 +0800 | [diff] [blame] | 2183 | { |
Zhenyu Wang | 14571b4 | 2010-03-30 14:06:33 +0800 | [diff] [blame] | 2184 | struct intel_connector *intel_connector; |
| 2185 | struct intel_sdvo_connector *sdvo_connector; |
| 2186 | |
| 2187 | *ret = kzalloc(sizeof(*intel_connector) + |
| 2188 | sizeof(*sdvo_connector), GFP_KERNEL); |
| 2189 | if (!*ret) |
| 2190 | return false; |
| 2191 | |
| 2192 | intel_connector = *ret; |
| 2193 | sdvo_connector = (struct intel_sdvo_connector *)(intel_connector + 1); |
| 2194 | intel_connector->dev_priv = sdvo_connector; |
| 2195 | |
| 2196 | return true; |
| 2197 | } |
| 2198 | |
| 2199 | static void |
| 2200 | intel_sdvo_connector_create (struct drm_encoder *encoder, |
| 2201 | struct drm_connector *connector) |
| 2202 | { |
| 2203 | drm_connector_init(encoder->dev, connector, &intel_sdvo_connector_funcs, |
| 2204 | connector->connector_type); |
| 2205 | |
| 2206 | drm_connector_helper_add(connector, &intel_sdvo_connector_helper_funcs); |
| 2207 | |
| 2208 | connector->interlace_allowed = 0; |
| 2209 | connector->doublescan_allowed = 0; |
| 2210 | connector->display_info.subpixel_order = SubPixelHorizontalRGB; |
| 2211 | |
| 2212 | drm_mode_connector_attach_encoder(connector, encoder); |
| 2213 | drm_sysfs_connector_add(connector); |
| 2214 | } |
| 2215 | |
| 2216 | static bool |
| 2217 | intel_sdvo_dvi_init(struct intel_encoder *intel_encoder, int device) |
| 2218 | { |
Eric Anholt | 21d40d3 | 2010-03-25 11:11:14 -0700 | [diff] [blame] | 2219 | struct drm_encoder *encoder = &intel_encoder->enc; |
| 2220 | struct intel_sdvo_priv *sdvo_priv = intel_encoder->dev_priv; |
Zhenyu Wang | 14571b4 | 2010-03-30 14:06:33 +0800 | [diff] [blame] | 2221 | struct drm_connector *connector; |
| 2222 | struct intel_connector *intel_connector; |
| 2223 | struct intel_sdvo_connector *sdvo_connector; |
| 2224 | |
| 2225 | if (!intel_sdvo_connector_alloc(&intel_connector)) |
| 2226 | return false; |
| 2227 | |
| 2228 | sdvo_connector = intel_connector->dev_priv; |
| 2229 | |
| 2230 | if (device == 0) { |
| 2231 | sdvo_priv->controlled_output |= SDVO_OUTPUT_TMDS0; |
| 2232 | sdvo_connector->output_flag = SDVO_OUTPUT_TMDS0; |
| 2233 | } else if (device == 1) { |
| 2234 | sdvo_priv->controlled_output |= SDVO_OUTPUT_TMDS1; |
| 2235 | sdvo_connector->output_flag = SDVO_OUTPUT_TMDS1; |
| 2236 | } |
| 2237 | |
| 2238 | connector = &intel_connector->base; |
| 2239 | encoder->encoder_type = DRM_MODE_ENCODER_TMDS; |
| 2240 | connector->connector_type = DRM_MODE_CONNECTOR_DVID; |
| 2241 | |
| 2242 | if (intel_sdvo_get_supp_encode(intel_encoder, &sdvo_priv->encode) |
| 2243 | && intel_sdvo_get_digital_encoding_mode(intel_encoder, device) |
| 2244 | && sdvo_priv->is_hdmi) { |
| 2245 | /* enable hdmi encoding mode if supported */ |
| 2246 | intel_sdvo_set_encode(intel_encoder, SDVO_ENCODE_HDMI); |
| 2247 | intel_sdvo_set_colorimetry(intel_encoder, |
| 2248 | SDVO_COLORIMETRY_RGB256); |
| 2249 | connector->connector_type = DRM_MODE_CONNECTOR_HDMIA; |
| 2250 | } |
| 2251 | intel_encoder->clone_mask = (1 << INTEL_SDVO_NON_TV_CLONE_BIT) | |
| 2252 | (1 << INTEL_ANALOG_CLONE_BIT); |
| 2253 | |
| 2254 | intel_sdvo_connector_create(encoder, connector); |
| 2255 | |
| 2256 | return true; |
| 2257 | } |
| 2258 | |
| 2259 | static bool |
| 2260 | intel_sdvo_tv_init(struct intel_encoder *intel_encoder, int type) |
| 2261 | { |
| 2262 | struct drm_encoder *encoder = &intel_encoder->enc; |
| 2263 | struct intel_sdvo_priv *sdvo_priv = intel_encoder->dev_priv; |
| 2264 | struct drm_connector *connector; |
| 2265 | struct intel_connector *intel_connector; |
| 2266 | struct intel_sdvo_connector *sdvo_connector; |
| 2267 | |
| 2268 | if (!intel_sdvo_connector_alloc(&intel_connector)) |
| 2269 | return false; |
| 2270 | |
| 2271 | connector = &intel_connector->base; |
| 2272 | encoder->encoder_type = DRM_MODE_ENCODER_TVDAC; |
| 2273 | connector->connector_type = DRM_MODE_CONNECTOR_SVIDEO; |
| 2274 | sdvo_connector = intel_connector->dev_priv; |
| 2275 | |
| 2276 | sdvo_priv->controlled_output |= type; |
| 2277 | sdvo_connector->output_flag = type; |
| 2278 | |
| 2279 | sdvo_priv->is_tv = true; |
| 2280 | intel_encoder->needs_tv_clock = true; |
| 2281 | intel_encoder->clone_mask = 1 << INTEL_SDVO_TV_CLONE_BIT; |
| 2282 | |
| 2283 | intel_sdvo_connector_create(encoder, connector); |
| 2284 | |
| 2285 | intel_sdvo_tv_create_property(connector, type); |
| 2286 | |
| 2287 | intel_sdvo_create_enhance_property(connector); |
| 2288 | |
| 2289 | return true; |
| 2290 | } |
| 2291 | |
| 2292 | static bool |
| 2293 | intel_sdvo_analog_init(struct intel_encoder *intel_encoder, int device) |
| 2294 | { |
| 2295 | struct drm_encoder *encoder = &intel_encoder->enc; |
| 2296 | struct intel_sdvo_priv *sdvo_priv = intel_encoder->dev_priv; |
| 2297 | struct drm_connector *connector; |
| 2298 | struct intel_connector *intel_connector; |
| 2299 | struct intel_sdvo_connector *sdvo_connector; |
| 2300 | |
| 2301 | if (!intel_sdvo_connector_alloc(&intel_connector)) |
| 2302 | return false; |
| 2303 | |
| 2304 | connector = &intel_connector->base; |
| 2305 | encoder->encoder_type = DRM_MODE_ENCODER_DAC; |
| 2306 | connector->connector_type = DRM_MODE_CONNECTOR_VGA; |
| 2307 | sdvo_connector = intel_connector->dev_priv; |
| 2308 | |
| 2309 | if (device == 0) { |
| 2310 | sdvo_priv->controlled_output |= SDVO_OUTPUT_RGB0; |
| 2311 | sdvo_connector->output_flag = SDVO_OUTPUT_RGB0; |
| 2312 | } else if (device == 1) { |
| 2313 | sdvo_priv->controlled_output |= SDVO_OUTPUT_RGB1; |
| 2314 | sdvo_connector->output_flag = SDVO_OUTPUT_RGB1; |
| 2315 | } |
| 2316 | |
| 2317 | intel_encoder->clone_mask = (1 << INTEL_SDVO_NON_TV_CLONE_BIT) | |
| 2318 | (1 << INTEL_ANALOG_CLONE_BIT); |
| 2319 | |
| 2320 | intel_sdvo_connector_create(encoder, connector); |
| 2321 | return true; |
| 2322 | } |
| 2323 | |
| 2324 | static bool |
| 2325 | intel_sdvo_lvds_init(struct intel_encoder *intel_encoder, int device) |
| 2326 | { |
| 2327 | struct drm_encoder *encoder = &intel_encoder->enc; |
| 2328 | struct intel_sdvo_priv *sdvo_priv = intel_encoder->dev_priv; |
| 2329 | struct drm_connector *connector; |
| 2330 | struct intel_connector *intel_connector; |
| 2331 | struct intel_sdvo_connector *sdvo_connector; |
| 2332 | |
| 2333 | if (!intel_sdvo_connector_alloc(&intel_connector)) |
| 2334 | return false; |
| 2335 | |
| 2336 | connector = &intel_connector->base; |
| 2337 | encoder->encoder_type = DRM_MODE_ENCODER_LVDS; |
| 2338 | connector->connector_type = DRM_MODE_CONNECTOR_LVDS; |
| 2339 | sdvo_connector = intel_connector->dev_priv; |
| 2340 | |
| 2341 | sdvo_priv->is_lvds = true; |
| 2342 | |
| 2343 | if (device == 0) { |
| 2344 | sdvo_priv->controlled_output |= SDVO_OUTPUT_LVDS0; |
| 2345 | sdvo_connector->output_flag = SDVO_OUTPUT_LVDS0; |
| 2346 | } else if (device == 1) { |
| 2347 | sdvo_priv->controlled_output |= SDVO_OUTPUT_LVDS1; |
| 2348 | sdvo_connector->output_flag = SDVO_OUTPUT_LVDS1; |
| 2349 | } |
| 2350 | |
| 2351 | intel_encoder->clone_mask = (1 << INTEL_ANALOG_CLONE_BIT) | |
| 2352 | (1 << INTEL_SDVO_LVDS_CLONE_BIT); |
| 2353 | |
| 2354 | intel_sdvo_connector_create(encoder, connector); |
| 2355 | intel_sdvo_create_enhance_property(connector); |
| 2356 | return true; |
| 2357 | } |
| 2358 | |
| 2359 | static bool |
| 2360 | intel_sdvo_output_setup(struct intel_encoder *intel_encoder, uint16_t flags) |
| 2361 | { |
| 2362 | struct intel_sdvo_priv *sdvo_priv = intel_encoder->dev_priv; |
ling.ma@intel.com | fb7a46f | 2009-07-23 17:11:34 +0800 | [diff] [blame] | 2363 | |
| 2364 | sdvo_priv->is_tv = false; |
Eric Anholt | 21d40d3 | 2010-03-25 11:11:14 -0700 | [diff] [blame] | 2365 | intel_encoder->needs_tv_clock = false; |
ling.ma@intel.com | fb7a46f | 2009-07-23 17:11:34 +0800 | [diff] [blame] | 2366 | sdvo_priv->is_lvds = false; |
| 2367 | |
Zhenyu Wang | 14571b4 | 2010-03-30 14:06:33 +0800 | [diff] [blame] | 2368 | /* SDVO requires XXX1 function may not exist unless it has XXX0 function.*/ |
ling.ma@intel.com | fb7a46f | 2009-07-23 17:11:34 +0800 | [diff] [blame] | 2369 | |
Zhenyu Wang | 14571b4 | 2010-03-30 14:06:33 +0800 | [diff] [blame] | 2370 | if (flags & SDVO_OUTPUT_TMDS0) |
| 2371 | if (!intel_sdvo_dvi_init(intel_encoder, 0)) |
| 2372 | return false; |
ling.ma@intel.com | fb7a46f | 2009-07-23 17:11:34 +0800 | [diff] [blame] | 2373 | |
Zhenyu Wang | 14571b4 | 2010-03-30 14:06:33 +0800 | [diff] [blame] | 2374 | if ((flags & SDVO_TMDS_MASK) == SDVO_TMDS_MASK) |
| 2375 | if (!intel_sdvo_dvi_init(intel_encoder, 1)) |
| 2376 | return false; |
ling.ma@intel.com | fb7a46f | 2009-07-23 17:11:34 +0800 | [diff] [blame] | 2377 | |
Zhenyu Wang | 14571b4 | 2010-03-30 14:06:33 +0800 | [diff] [blame] | 2378 | /* TV has no XXX1 function block */ |
Zhenyu Wang | a1f4b7ff | 2010-03-29 23:16:13 +0800 | [diff] [blame^] | 2379 | if (flags & SDVO_OUTPUT_SVID0) |
Zhenyu Wang | 14571b4 | 2010-03-30 14:06:33 +0800 | [diff] [blame] | 2380 | if (!intel_sdvo_tv_init(intel_encoder, SDVO_OUTPUT_SVID0)) |
| 2381 | return false; |
ling.ma@intel.com | fb7a46f | 2009-07-23 17:11:34 +0800 | [diff] [blame] | 2382 | |
Zhenyu Wang | 14571b4 | 2010-03-30 14:06:33 +0800 | [diff] [blame] | 2383 | if (flags & SDVO_OUTPUT_CVBS0) |
| 2384 | if (!intel_sdvo_tv_init(intel_encoder, SDVO_OUTPUT_CVBS0)) |
| 2385 | return false; |
ling.ma@intel.com | fb7a46f | 2009-07-23 17:11:34 +0800 | [diff] [blame] | 2386 | |
Zhenyu Wang | 14571b4 | 2010-03-30 14:06:33 +0800 | [diff] [blame] | 2387 | if (flags & SDVO_OUTPUT_RGB0) |
| 2388 | if (!intel_sdvo_analog_init(intel_encoder, 0)) |
| 2389 | return false; |
ling.ma@intel.com | fb7a46f | 2009-07-23 17:11:34 +0800 | [diff] [blame] | 2390 | |
Zhenyu Wang | 14571b4 | 2010-03-30 14:06:33 +0800 | [diff] [blame] | 2391 | if ((flags & SDVO_RGB_MASK) == SDVO_RGB_MASK) |
| 2392 | if (!intel_sdvo_analog_init(intel_encoder, 1)) |
| 2393 | return false; |
Zhao Yakui | 2dd8738 | 2010-01-27 16:32:46 +0800 | [diff] [blame] | 2394 | |
Zhenyu Wang | 14571b4 | 2010-03-30 14:06:33 +0800 | [diff] [blame] | 2395 | if (flags & SDVO_OUTPUT_LVDS0) |
| 2396 | if (!intel_sdvo_lvds_init(intel_encoder, 0)) |
| 2397 | return false; |
ling.ma@intel.com | fb7a46f | 2009-07-23 17:11:34 +0800 | [diff] [blame] | 2398 | |
Zhenyu Wang | 14571b4 | 2010-03-30 14:06:33 +0800 | [diff] [blame] | 2399 | if ((flags & SDVO_LVDS_MASK) == SDVO_LVDS_MASK) |
| 2400 | if (!intel_sdvo_lvds_init(intel_encoder, 1)) |
| 2401 | return false; |
ling.ma@intel.com | fb7a46f | 2009-07-23 17:11:34 +0800 | [diff] [blame] | 2402 | |
Zhenyu Wang | 14571b4 | 2010-03-30 14:06:33 +0800 | [diff] [blame] | 2403 | if ((flags & SDVO_OUTPUT_MASK) == 0) { |
ling.ma@intel.com | fb7a46f | 2009-07-23 17:11:34 +0800 | [diff] [blame] | 2404 | unsigned char bytes[2]; |
| 2405 | |
| 2406 | sdvo_priv->controlled_output = 0; |
| 2407 | memcpy(bytes, &sdvo_priv->caps.output_flags, 2); |
Dave Airlie | 51c8b40 | 2009-08-20 13:38:04 +1000 | [diff] [blame] | 2408 | DRM_DEBUG_KMS("%s: Unknown SDVO output type (0x%02x%02x)\n", |
| 2409 | SDVO_NAME(sdvo_priv), |
| 2410 | bytes[0], bytes[1]); |
Zhenyu Wang | 14571b4 | 2010-03-30 14:06:33 +0800 | [diff] [blame] | 2411 | return false; |
ling.ma@intel.com | fb7a46f | 2009-07-23 17:11:34 +0800 | [diff] [blame] | 2412 | } |
Eric Anholt | 21d40d3 | 2010-03-25 11:11:14 -0700 | [diff] [blame] | 2413 | intel_encoder->crtc_mask = (1 << 0) | (1 << 1); |
ling.ma@intel.com | fb7a46f | 2009-07-23 17:11:34 +0800 | [diff] [blame] | 2414 | |
Zhenyu Wang | 14571b4 | 2010-03-30 14:06:33 +0800 | [diff] [blame] | 2415 | return true; |
ling.ma@intel.com | fb7a46f | 2009-07-23 17:11:34 +0800 | [diff] [blame] | 2416 | } |
| 2417 | |
Zhenyu Wang | 14571b4 | 2010-03-30 14:06:33 +0800 | [diff] [blame] | 2418 | static void intel_sdvo_tv_create_property(struct drm_connector *connector, int type) |
Zhao Yakui | ce6feab | 2009-08-24 13:50:26 +0800 | [diff] [blame] | 2419 | { |
Zhenyu Wang | d2a82a6 | 2010-03-29 21:22:55 +0800 | [diff] [blame] | 2420 | struct drm_encoder *encoder = intel_attached_encoder(connector); |
| 2421 | struct intel_encoder *intel_encoder = enc_to_intel_encoder(encoder); |
Eric Anholt | 21d40d3 | 2010-03-25 11:11:14 -0700 | [diff] [blame] | 2422 | struct intel_sdvo_priv *sdvo_priv = intel_encoder->dev_priv; |
Zhenyu Wang | 14571b4 | 2010-03-30 14:06:33 +0800 | [diff] [blame] | 2423 | struct intel_connector *intel_connector = to_intel_connector(connector); |
| 2424 | struct intel_sdvo_connector *sdvo_connector = intel_connector->dev_priv; |
Zhao Yakui | ce6feab | 2009-08-24 13:50:26 +0800 | [diff] [blame] | 2425 | struct intel_sdvo_tv_format format; |
| 2426 | uint32_t format_map, i; |
| 2427 | uint8_t status; |
| 2428 | |
Zhenyu Wang | 14571b4 | 2010-03-30 14:06:33 +0800 | [diff] [blame] | 2429 | intel_sdvo_set_target_output(intel_encoder, type); |
Zhao Yakui | ce6feab | 2009-08-24 13:50:26 +0800 | [diff] [blame] | 2430 | |
Eric Anholt | 21d40d3 | 2010-03-25 11:11:14 -0700 | [diff] [blame] | 2431 | intel_sdvo_write_cmd(intel_encoder, |
Zhao Yakui | ce6feab | 2009-08-24 13:50:26 +0800 | [diff] [blame] | 2432 | SDVO_CMD_GET_SUPPORTED_TV_FORMATS, NULL, 0); |
Eric Anholt | 21d40d3 | 2010-03-25 11:11:14 -0700 | [diff] [blame] | 2433 | status = intel_sdvo_read_response(intel_encoder, |
Zhao Yakui | ce6feab | 2009-08-24 13:50:26 +0800 | [diff] [blame] | 2434 | &format, sizeof(format)); |
| 2435 | if (status != SDVO_CMD_STATUS_SUCCESS) |
| 2436 | return; |
| 2437 | |
| 2438 | memcpy(&format_map, &format, sizeof(format) > sizeof(format_map) ? |
| 2439 | sizeof(format_map) : sizeof(format)); |
| 2440 | |
| 2441 | if (format_map == 0) |
| 2442 | return; |
| 2443 | |
Zhenyu Wang | 14571b4 | 2010-03-30 14:06:33 +0800 | [diff] [blame] | 2444 | sdvo_connector->format_supported_num = 0; |
Zhao Yakui | ce6feab | 2009-08-24 13:50:26 +0800 | [diff] [blame] | 2445 | for (i = 0 ; i < TV_FORMAT_NUM; i++) |
| 2446 | if (format_map & (1 << i)) { |
Zhenyu Wang | 14571b4 | 2010-03-30 14:06:33 +0800 | [diff] [blame] | 2447 | sdvo_connector->tv_format_supported |
| 2448 | [sdvo_connector->format_supported_num++] = |
Zhao Yakui | ce6feab | 2009-08-24 13:50:26 +0800 | [diff] [blame] | 2449 | tv_format_names[i]; |
| 2450 | } |
| 2451 | |
| 2452 | |
Zhenyu Wang | 14571b4 | 2010-03-30 14:06:33 +0800 | [diff] [blame] | 2453 | sdvo_connector->tv_format_property = |
Zhao Yakui | ce6feab | 2009-08-24 13:50:26 +0800 | [diff] [blame] | 2454 | drm_property_create( |
| 2455 | connector->dev, DRM_MODE_PROP_ENUM, |
Zhenyu Wang | 14571b4 | 2010-03-30 14:06:33 +0800 | [diff] [blame] | 2456 | "mode", sdvo_connector->format_supported_num); |
Zhao Yakui | ce6feab | 2009-08-24 13:50:26 +0800 | [diff] [blame] | 2457 | |
Zhenyu Wang | 14571b4 | 2010-03-30 14:06:33 +0800 | [diff] [blame] | 2458 | for (i = 0; i < sdvo_connector->format_supported_num; i++) |
Zhao Yakui | ce6feab | 2009-08-24 13:50:26 +0800 | [diff] [blame] | 2459 | drm_property_add_enum( |
Zhenyu Wang | 14571b4 | 2010-03-30 14:06:33 +0800 | [diff] [blame] | 2460 | sdvo_connector->tv_format_property, i, |
| 2461 | i, sdvo_connector->tv_format_supported[i]); |
Zhao Yakui | ce6feab | 2009-08-24 13:50:26 +0800 | [diff] [blame] | 2462 | |
Zhenyu Wang | 14571b4 | 2010-03-30 14:06:33 +0800 | [diff] [blame] | 2463 | sdvo_priv->tv_format_name = sdvo_connector->tv_format_supported[0]; |
Zhao Yakui | ce6feab | 2009-08-24 13:50:26 +0800 | [diff] [blame] | 2464 | drm_connector_attach_property( |
Zhenyu Wang | 14571b4 | 2010-03-30 14:06:33 +0800 | [diff] [blame] | 2465 | connector, sdvo_connector->tv_format_property, 0); |
Zhao Yakui | ce6feab | 2009-08-24 13:50:26 +0800 | [diff] [blame] | 2466 | |
| 2467 | } |
| 2468 | |
Zhao Yakui | b9219c5 | 2009-09-10 15:45:46 +0800 | [diff] [blame] | 2469 | static void intel_sdvo_create_enhance_property(struct drm_connector *connector) |
| 2470 | { |
Zhenyu Wang | d2a82a6 | 2010-03-29 21:22:55 +0800 | [diff] [blame] | 2471 | struct drm_encoder *encoder = intel_attached_encoder(connector); |
| 2472 | struct intel_encoder *intel_encoder = enc_to_intel_encoder(encoder); |
Zhenyu Wang | 14571b4 | 2010-03-30 14:06:33 +0800 | [diff] [blame] | 2473 | struct intel_connector *intel_connector = to_intel_connector(connector); |
| 2474 | struct intel_sdvo_connector *sdvo_priv = intel_connector->dev_priv; |
Zhao Yakui | b9219c5 | 2009-09-10 15:45:46 +0800 | [diff] [blame] | 2475 | struct intel_sdvo_enhancements_reply sdvo_data; |
| 2476 | struct drm_device *dev = connector->dev; |
| 2477 | uint8_t status; |
| 2478 | uint16_t response, data_value[2]; |
| 2479 | |
Eric Anholt | 21d40d3 | 2010-03-25 11:11:14 -0700 | [diff] [blame] | 2480 | intel_sdvo_write_cmd(intel_encoder, SDVO_CMD_GET_SUPPORTED_ENHANCEMENTS, |
Zhao Yakui | b9219c5 | 2009-09-10 15:45:46 +0800 | [diff] [blame] | 2481 | NULL, 0); |
Eric Anholt | 21d40d3 | 2010-03-25 11:11:14 -0700 | [diff] [blame] | 2482 | status = intel_sdvo_read_response(intel_encoder, &sdvo_data, |
Zhao Yakui | b9219c5 | 2009-09-10 15:45:46 +0800 | [diff] [blame] | 2483 | sizeof(sdvo_data)); |
| 2484 | if (status != SDVO_CMD_STATUS_SUCCESS) { |
| 2485 | DRM_DEBUG_KMS(" incorrect response is returned\n"); |
| 2486 | return; |
| 2487 | } |
| 2488 | response = *((uint16_t *)&sdvo_data); |
| 2489 | if (!response) { |
| 2490 | DRM_DEBUG_KMS("No enhancement is supported\n"); |
| 2491 | return; |
| 2492 | } |
Zhenyu Wang | 14571b4 | 2010-03-30 14:06:33 +0800 | [diff] [blame] | 2493 | if (IS_TV(sdvo_priv)) { |
Zhao Yakui | b9219c5 | 2009-09-10 15:45:46 +0800 | [diff] [blame] | 2494 | /* when horizontal overscan is supported, Add the left/right |
| 2495 | * property |
| 2496 | */ |
| 2497 | if (sdvo_data.overscan_h) { |
Eric Anholt | 21d40d3 | 2010-03-25 11:11:14 -0700 | [diff] [blame] | 2498 | intel_sdvo_write_cmd(intel_encoder, |
Zhao Yakui | b9219c5 | 2009-09-10 15:45:46 +0800 | [diff] [blame] | 2499 | SDVO_CMD_GET_MAX_OVERSCAN_H, NULL, 0); |
Eric Anholt | 21d40d3 | 2010-03-25 11:11:14 -0700 | [diff] [blame] | 2500 | status = intel_sdvo_read_response(intel_encoder, |
Zhao Yakui | b9219c5 | 2009-09-10 15:45:46 +0800 | [diff] [blame] | 2501 | &data_value, 4); |
| 2502 | if (status != SDVO_CMD_STATUS_SUCCESS) { |
| 2503 | DRM_DEBUG_KMS("Incorrect SDVO max " |
| 2504 | "h_overscan\n"); |
| 2505 | return; |
| 2506 | } |
Eric Anholt | 21d40d3 | 2010-03-25 11:11:14 -0700 | [diff] [blame] | 2507 | intel_sdvo_write_cmd(intel_encoder, |
Zhao Yakui | b9219c5 | 2009-09-10 15:45:46 +0800 | [diff] [blame] | 2508 | SDVO_CMD_GET_OVERSCAN_H, NULL, 0); |
Eric Anholt | 21d40d3 | 2010-03-25 11:11:14 -0700 | [diff] [blame] | 2509 | status = intel_sdvo_read_response(intel_encoder, |
Zhao Yakui | b9219c5 | 2009-09-10 15:45:46 +0800 | [diff] [blame] | 2510 | &response, 2); |
| 2511 | if (status != SDVO_CMD_STATUS_SUCCESS) { |
| 2512 | DRM_DEBUG_KMS("Incorrect SDVO h_overscan\n"); |
| 2513 | return; |
| 2514 | } |
| 2515 | sdvo_priv->max_hscan = data_value[0]; |
| 2516 | sdvo_priv->left_margin = data_value[0] - response; |
| 2517 | sdvo_priv->right_margin = sdvo_priv->left_margin; |
| 2518 | sdvo_priv->left_property = |
| 2519 | drm_property_create(dev, DRM_MODE_PROP_RANGE, |
| 2520 | "left_margin", 2); |
| 2521 | sdvo_priv->left_property->values[0] = 0; |
| 2522 | sdvo_priv->left_property->values[1] = data_value[0]; |
| 2523 | drm_connector_attach_property(connector, |
| 2524 | sdvo_priv->left_property, |
| 2525 | sdvo_priv->left_margin); |
| 2526 | sdvo_priv->right_property = |
| 2527 | drm_property_create(dev, DRM_MODE_PROP_RANGE, |
| 2528 | "right_margin", 2); |
| 2529 | sdvo_priv->right_property->values[0] = 0; |
| 2530 | sdvo_priv->right_property->values[1] = data_value[0]; |
| 2531 | drm_connector_attach_property(connector, |
| 2532 | sdvo_priv->right_property, |
| 2533 | sdvo_priv->right_margin); |
| 2534 | DRM_DEBUG_KMS("h_overscan: max %d, " |
| 2535 | "default %d, current %d\n", |
| 2536 | data_value[0], data_value[1], response); |
| 2537 | } |
| 2538 | if (sdvo_data.overscan_v) { |
Eric Anholt | 21d40d3 | 2010-03-25 11:11:14 -0700 | [diff] [blame] | 2539 | intel_sdvo_write_cmd(intel_encoder, |
Zhao Yakui | b9219c5 | 2009-09-10 15:45:46 +0800 | [diff] [blame] | 2540 | SDVO_CMD_GET_MAX_OVERSCAN_V, NULL, 0); |
Eric Anholt | 21d40d3 | 2010-03-25 11:11:14 -0700 | [diff] [blame] | 2541 | status = intel_sdvo_read_response(intel_encoder, |
Zhao Yakui | b9219c5 | 2009-09-10 15:45:46 +0800 | [diff] [blame] | 2542 | &data_value, 4); |
| 2543 | if (status != SDVO_CMD_STATUS_SUCCESS) { |
| 2544 | DRM_DEBUG_KMS("Incorrect SDVO max " |
| 2545 | "v_overscan\n"); |
| 2546 | return; |
| 2547 | } |
Eric Anholt | 21d40d3 | 2010-03-25 11:11:14 -0700 | [diff] [blame] | 2548 | intel_sdvo_write_cmd(intel_encoder, |
Zhao Yakui | b9219c5 | 2009-09-10 15:45:46 +0800 | [diff] [blame] | 2549 | SDVO_CMD_GET_OVERSCAN_V, NULL, 0); |
Eric Anholt | 21d40d3 | 2010-03-25 11:11:14 -0700 | [diff] [blame] | 2550 | status = intel_sdvo_read_response(intel_encoder, |
Zhao Yakui | b9219c5 | 2009-09-10 15:45:46 +0800 | [diff] [blame] | 2551 | &response, 2); |
| 2552 | if (status != SDVO_CMD_STATUS_SUCCESS) { |
| 2553 | DRM_DEBUG_KMS("Incorrect SDVO v_overscan\n"); |
| 2554 | return; |
| 2555 | } |
| 2556 | sdvo_priv->max_vscan = data_value[0]; |
| 2557 | sdvo_priv->top_margin = data_value[0] - response; |
| 2558 | sdvo_priv->bottom_margin = sdvo_priv->top_margin; |
| 2559 | sdvo_priv->top_property = |
| 2560 | drm_property_create(dev, DRM_MODE_PROP_RANGE, |
| 2561 | "top_margin", 2); |
| 2562 | sdvo_priv->top_property->values[0] = 0; |
| 2563 | sdvo_priv->top_property->values[1] = data_value[0]; |
| 2564 | drm_connector_attach_property(connector, |
| 2565 | sdvo_priv->top_property, |
| 2566 | sdvo_priv->top_margin); |
| 2567 | sdvo_priv->bottom_property = |
| 2568 | drm_property_create(dev, DRM_MODE_PROP_RANGE, |
| 2569 | "bottom_margin", 2); |
| 2570 | sdvo_priv->bottom_property->values[0] = 0; |
| 2571 | sdvo_priv->bottom_property->values[1] = data_value[0]; |
| 2572 | drm_connector_attach_property(connector, |
| 2573 | sdvo_priv->bottom_property, |
| 2574 | sdvo_priv->bottom_margin); |
| 2575 | DRM_DEBUG_KMS("v_overscan: max %d, " |
| 2576 | "default %d, current %d\n", |
| 2577 | data_value[0], data_value[1], response); |
| 2578 | } |
| 2579 | if (sdvo_data.position_h) { |
Eric Anholt | 21d40d3 | 2010-03-25 11:11:14 -0700 | [diff] [blame] | 2580 | intel_sdvo_write_cmd(intel_encoder, |
Zhao Yakui | b9219c5 | 2009-09-10 15:45:46 +0800 | [diff] [blame] | 2581 | SDVO_CMD_GET_MAX_POSITION_H, NULL, 0); |
Eric Anholt | 21d40d3 | 2010-03-25 11:11:14 -0700 | [diff] [blame] | 2582 | status = intel_sdvo_read_response(intel_encoder, |
Zhao Yakui | b9219c5 | 2009-09-10 15:45:46 +0800 | [diff] [blame] | 2583 | &data_value, 4); |
| 2584 | if (status != SDVO_CMD_STATUS_SUCCESS) { |
| 2585 | DRM_DEBUG_KMS("Incorrect SDVO Max h_pos\n"); |
| 2586 | return; |
| 2587 | } |
Eric Anholt | 21d40d3 | 2010-03-25 11:11:14 -0700 | [diff] [blame] | 2588 | intel_sdvo_write_cmd(intel_encoder, |
Zhao Yakui | b9219c5 | 2009-09-10 15:45:46 +0800 | [diff] [blame] | 2589 | SDVO_CMD_GET_POSITION_H, NULL, 0); |
Eric Anholt | 21d40d3 | 2010-03-25 11:11:14 -0700 | [diff] [blame] | 2590 | status = intel_sdvo_read_response(intel_encoder, |
Zhao Yakui | b9219c5 | 2009-09-10 15:45:46 +0800 | [diff] [blame] | 2591 | &response, 2); |
| 2592 | if (status != SDVO_CMD_STATUS_SUCCESS) { |
| 2593 | DRM_DEBUG_KMS("Incorrect SDVO get h_postion\n"); |
| 2594 | return; |
| 2595 | } |
| 2596 | sdvo_priv->max_hpos = data_value[0]; |
| 2597 | sdvo_priv->cur_hpos = response; |
| 2598 | sdvo_priv->hpos_property = |
| 2599 | drm_property_create(dev, DRM_MODE_PROP_RANGE, |
| 2600 | "hpos", 2); |
| 2601 | sdvo_priv->hpos_property->values[0] = 0; |
| 2602 | sdvo_priv->hpos_property->values[1] = data_value[0]; |
| 2603 | drm_connector_attach_property(connector, |
| 2604 | sdvo_priv->hpos_property, |
| 2605 | sdvo_priv->cur_hpos); |
| 2606 | DRM_DEBUG_KMS("h_position: max %d, " |
| 2607 | "default %d, current %d\n", |
| 2608 | data_value[0], data_value[1], response); |
| 2609 | } |
| 2610 | if (sdvo_data.position_v) { |
Eric Anholt | 21d40d3 | 2010-03-25 11:11:14 -0700 | [diff] [blame] | 2611 | intel_sdvo_write_cmd(intel_encoder, |
Zhao Yakui | b9219c5 | 2009-09-10 15:45:46 +0800 | [diff] [blame] | 2612 | SDVO_CMD_GET_MAX_POSITION_V, NULL, 0); |
Eric Anholt | 21d40d3 | 2010-03-25 11:11:14 -0700 | [diff] [blame] | 2613 | status = intel_sdvo_read_response(intel_encoder, |
Zhao Yakui | b9219c5 | 2009-09-10 15:45:46 +0800 | [diff] [blame] | 2614 | &data_value, 4); |
| 2615 | if (status != SDVO_CMD_STATUS_SUCCESS) { |
| 2616 | DRM_DEBUG_KMS("Incorrect SDVO Max v_pos\n"); |
| 2617 | return; |
| 2618 | } |
Eric Anholt | 21d40d3 | 2010-03-25 11:11:14 -0700 | [diff] [blame] | 2619 | intel_sdvo_write_cmd(intel_encoder, |
Zhao Yakui | b9219c5 | 2009-09-10 15:45:46 +0800 | [diff] [blame] | 2620 | SDVO_CMD_GET_POSITION_V, NULL, 0); |
Eric Anholt | 21d40d3 | 2010-03-25 11:11:14 -0700 | [diff] [blame] | 2621 | status = intel_sdvo_read_response(intel_encoder, |
Zhao Yakui | b9219c5 | 2009-09-10 15:45:46 +0800 | [diff] [blame] | 2622 | &response, 2); |
| 2623 | if (status != SDVO_CMD_STATUS_SUCCESS) { |
| 2624 | DRM_DEBUG_KMS("Incorrect SDVO get v_postion\n"); |
| 2625 | return; |
| 2626 | } |
| 2627 | sdvo_priv->max_vpos = data_value[0]; |
| 2628 | sdvo_priv->cur_vpos = response; |
| 2629 | sdvo_priv->vpos_property = |
| 2630 | drm_property_create(dev, DRM_MODE_PROP_RANGE, |
| 2631 | "vpos", 2); |
| 2632 | sdvo_priv->vpos_property->values[0] = 0; |
| 2633 | sdvo_priv->vpos_property->values[1] = data_value[0]; |
| 2634 | drm_connector_attach_property(connector, |
| 2635 | sdvo_priv->vpos_property, |
| 2636 | sdvo_priv->cur_vpos); |
| 2637 | DRM_DEBUG_KMS("v_position: max %d, " |
| 2638 | "default %d, current %d\n", |
| 2639 | data_value[0], data_value[1], response); |
| 2640 | } |
Zhao Yakui | b9219c5 | 2009-09-10 15:45:46 +0800 | [diff] [blame] | 2641 | if (sdvo_data.saturation) { |
Eric Anholt | 21d40d3 | 2010-03-25 11:11:14 -0700 | [diff] [blame] | 2642 | intel_sdvo_write_cmd(intel_encoder, |
Zhao Yakui | b9219c5 | 2009-09-10 15:45:46 +0800 | [diff] [blame] | 2643 | SDVO_CMD_GET_MAX_SATURATION, NULL, 0); |
Eric Anholt | 21d40d3 | 2010-03-25 11:11:14 -0700 | [diff] [blame] | 2644 | status = intel_sdvo_read_response(intel_encoder, |
Zhao Yakui | b9219c5 | 2009-09-10 15:45:46 +0800 | [diff] [blame] | 2645 | &data_value, 4); |
| 2646 | if (status != SDVO_CMD_STATUS_SUCCESS) { |
| 2647 | DRM_DEBUG_KMS("Incorrect SDVO Max sat\n"); |
| 2648 | return; |
| 2649 | } |
Eric Anholt | 21d40d3 | 2010-03-25 11:11:14 -0700 | [diff] [blame] | 2650 | intel_sdvo_write_cmd(intel_encoder, |
Zhao Yakui | b9219c5 | 2009-09-10 15:45:46 +0800 | [diff] [blame] | 2651 | SDVO_CMD_GET_SATURATION, NULL, 0); |
Eric Anholt | 21d40d3 | 2010-03-25 11:11:14 -0700 | [diff] [blame] | 2652 | status = intel_sdvo_read_response(intel_encoder, |
Zhao Yakui | b9219c5 | 2009-09-10 15:45:46 +0800 | [diff] [blame] | 2653 | &response, 2); |
| 2654 | if (status != SDVO_CMD_STATUS_SUCCESS) { |
| 2655 | DRM_DEBUG_KMS("Incorrect SDVO get sat\n"); |
| 2656 | return; |
| 2657 | } |
| 2658 | sdvo_priv->max_saturation = data_value[0]; |
| 2659 | sdvo_priv->cur_saturation = response; |
| 2660 | sdvo_priv->saturation_property = |
| 2661 | drm_property_create(dev, DRM_MODE_PROP_RANGE, |
| 2662 | "saturation", 2); |
| 2663 | sdvo_priv->saturation_property->values[0] = 0; |
| 2664 | sdvo_priv->saturation_property->values[1] = |
| 2665 | data_value[0]; |
| 2666 | drm_connector_attach_property(connector, |
| 2667 | sdvo_priv->saturation_property, |
| 2668 | sdvo_priv->cur_saturation); |
| 2669 | DRM_DEBUG_KMS("saturation: max %d, " |
| 2670 | "default %d, current %d\n", |
| 2671 | data_value[0], data_value[1], response); |
| 2672 | } |
| 2673 | if (sdvo_data.contrast) { |
Eric Anholt | 21d40d3 | 2010-03-25 11:11:14 -0700 | [diff] [blame] | 2674 | intel_sdvo_write_cmd(intel_encoder, |
Zhao Yakui | b9219c5 | 2009-09-10 15:45:46 +0800 | [diff] [blame] | 2675 | SDVO_CMD_GET_MAX_CONTRAST, NULL, 0); |
Eric Anholt | 21d40d3 | 2010-03-25 11:11:14 -0700 | [diff] [blame] | 2676 | status = intel_sdvo_read_response(intel_encoder, |
Zhao Yakui | b9219c5 | 2009-09-10 15:45:46 +0800 | [diff] [blame] | 2677 | &data_value, 4); |
| 2678 | if (status != SDVO_CMD_STATUS_SUCCESS) { |
| 2679 | DRM_DEBUG_KMS("Incorrect SDVO Max contrast\n"); |
| 2680 | return; |
| 2681 | } |
Eric Anholt | 21d40d3 | 2010-03-25 11:11:14 -0700 | [diff] [blame] | 2682 | intel_sdvo_write_cmd(intel_encoder, |
Zhao Yakui | b9219c5 | 2009-09-10 15:45:46 +0800 | [diff] [blame] | 2683 | SDVO_CMD_GET_CONTRAST, NULL, 0); |
Eric Anholt | 21d40d3 | 2010-03-25 11:11:14 -0700 | [diff] [blame] | 2684 | status = intel_sdvo_read_response(intel_encoder, |
Zhao Yakui | b9219c5 | 2009-09-10 15:45:46 +0800 | [diff] [blame] | 2685 | &response, 2); |
| 2686 | if (status != SDVO_CMD_STATUS_SUCCESS) { |
| 2687 | DRM_DEBUG_KMS("Incorrect SDVO get contrast\n"); |
| 2688 | return; |
| 2689 | } |
| 2690 | sdvo_priv->max_contrast = data_value[0]; |
| 2691 | sdvo_priv->cur_contrast = response; |
| 2692 | sdvo_priv->contrast_property = |
| 2693 | drm_property_create(dev, DRM_MODE_PROP_RANGE, |
| 2694 | "contrast", 2); |
| 2695 | sdvo_priv->contrast_property->values[0] = 0; |
| 2696 | sdvo_priv->contrast_property->values[1] = data_value[0]; |
| 2697 | drm_connector_attach_property(connector, |
| 2698 | sdvo_priv->contrast_property, |
| 2699 | sdvo_priv->cur_contrast); |
| 2700 | DRM_DEBUG_KMS("contrast: max %d, " |
| 2701 | "default %d, current %d\n", |
| 2702 | data_value[0], data_value[1], response); |
| 2703 | } |
| 2704 | if (sdvo_data.hue) { |
Eric Anholt | 21d40d3 | 2010-03-25 11:11:14 -0700 | [diff] [blame] | 2705 | intel_sdvo_write_cmd(intel_encoder, |
Zhao Yakui | b9219c5 | 2009-09-10 15:45:46 +0800 | [diff] [blame] | 2706 | SDVO_CMD_GET_MAX_HUE, NULL, 0); |
Eric Anholt | 21d40d3 | 2010-03-25 11:11:14 -0700 | [diff] [blame] | 2707 | status = intel_sdvo_read_response(intel_encoder, |
Zhao Yakui | b9219c5 | 2009-09-10 15:45:46 +0800 | [diff] [blame] | 2708 | &data_value, 4); |
| 2709 | if (status != SDVO_CMD_STATUS_SUCCESS) { |
| 2710 | DRM_DEBUG_KMS("Incorrect SDVO Max hue\n"); |
| 2711 | return; |
| 2712 | } |
Eric Anholt | 21d40d3 | 2010-03-25 11:11:14 -0700 | [diff] [blame] | 2713 | intel_sdvo_write_cmd(intel_encoder, |
Zhao Yakui | b9219c5 | 2009-09-10 15:45:46 +0800 | [diff] [blame] | 2714 | SDVO_CMD_GET_HUE, NULL, 0); |
Eric Anholt | 21d40d3 | 2010-03-25 11:11:14 -0700 | [diff] [blame] | 2715 | status = intel_sdvo_read_response(intel_encoder, |
Zhao Yakui | b9219c5 | 2009-09-10 15:45:46 +0800 | [diff] [blame] | 2716 | &response, 2); |
| 2717 | if (status != SDVO_CMD_STATUS_SUCCESS) { |
| 2718 | DRM_DEBUG_KMS("Incorrect SDVO get hue\n"); |
| 2719 | return; |
| 2720 | } |
| 2721 | sdvo_priv->max_hue = data_value[0]; |
| 2722 | sdvo_priv->cur_hue = response; |
| 2723 | sdvo_priv->hue_property = |
| 2724 | drm_property_create(dev, DRM_MODE_PROP_RANGE, |
| 2725 | "hue", 2); |
| 2726 | sdvo_priv->hue_property->values[0] = 0; |
| 2727 | sdvo_priv->hue_property->values[1] = |
| 2728 | data_value[0]; |
| 2729 | drm_connector_attach_property(connector, |
| 2730 | sdvo_priv->hue_property, |
| 2731 | sdvo_priv->cur_hue); |
| 2732 | DRM_DEBUG_KMS("hue: max %d, default %d, current %d\n", |
| 2733 | data_value[0], data_value[1], response); |
| 2734 | } |
| 2735 | } |
Zhenyu Wang | 14571b4 | 2010-03-30 14:06:33 +0800 | [diff] [blame] | 2736 | if (IS_TV(sdvo_priv) || IS_LVDS(sdvo_priv)) { |
Zhao Yakui | b9219c5 | 2009-09-10 15:45:46 +0800 | [diff] [blame] | 2737 | if (sdvo_data.brightness) { |
Eric Anholt | 21d40d3 | 2010-03-25 11:11:14 -0700 | [diff] [blame] | 2738 | intel_sdvo_write_cmd(intel_encoder, |
Zhao Yakui | b9219c5 | 2009-09-10 15:45:46 +0800 | [diff] [blame] | 2739 | SDVO_CMD_GET_MAX_BRIGHTNESS, NULL, 0); |
Eric Anholt | 21d40d3 | 2010-03-25 11:11:14 -0700 | [diff] [blame] | 2740 | status = intel_sdvo_read_response(intel_encoder, |
Zhao Yakui | b9219c5 | 2009-09-10 15:45:46 +0800 | [diff] [blame] | 2741 | &data_value, 4); |
| 2742 | if (status != SDVO_CMD_STATUS_SUCCESS) { |
| 2743 | DRM_DEBUG_KMS("Incorrect SDVO Max bright\n"); |
| 2744 | return; |
| 2745 | } |
Eric Anholt | 21d40d3 | 2010-03-25 11:11:14 -0700 | [diff] [blame] | 2746 | intel_sdvo_write_cmd(intel_encoder, |
Zhao Yakui | b9219c5 | 2009-09-10 15:45:46 +0800 | [diff] [blame] | 2747 | SDVO_CMD_GET_BRIGHTNESS, NULL, 0); |
Eric Anholt | 21d40d3 | 2010-03-25 11:11:14 -0700 | [diff] [blame] | 2748 | status = intel_sdvo_read_response(intel_encoder, |
Zhao Yakui | b9219c5 | 2009-09-10 15:45:46 +0800 | [diff] [blame] | 2749 | &response, 2); |
| 2750 | if (status != SDVO_CMD_STATUS_SUCCESS) { |
| 2751 | DRM_DEBUG_KMS("Incorrect SDVO get brigh\n"); |
| 2752 | return; |
| 2753 | } |
| 2754 | sdvo_priv->max_brightness = data_value[0]; |
| 2755 | sdvo_priv->cur_brightness = response; |
| 2756 | sdvo_priv->brightness_property = |
| 2757 | drm_property_create(dev, DRM_MODE_PROP_RANGE, |
| 2758 | "brightness", 2); |
| 2759 | sdvo_priv->brightness_property->values[0] = 0; |
| 2760 | sdvo_priv->brightness_property->values[1] = |
| 2761 | data_value[0]; |
| 2762 | drm_connector_attach_property(connector, |
| 2763 | sdvo_priv->brightness_property, |
| 2764 | sdvo_priv->cur_brightness); |
| 2765 | DRM_DEBUG_KMS("brightness: max %d, " |
| 2766 | "default %d, current %d\n", |
| 2767 | data_value[0], data_value[1], response); |
| 2768 | } |
| 2769 | } |
| 2770 | return; |
| 2771 | } |
| 2772 | |
Eric Anholt | c751ce4 | 2010-03-25 11:48:48 -0700 | [diff] [blame] | 2773 | bool intel_sdvo_init(struct drm_device *dev, int sdvo_reg) |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 2774 | { |
Jesse Barnes | b01f2c3 | 2009-12-11 11:07:17 -0800 | [diff] [blame] | 2775 | struct drm_i915_private *dev_priv = dev->dev_private; |
Eric Anholt | 21d40d3 | 2010-03-25 11:11:14 -0700 | [diff] [blame] | 2776 | struct intel_encoder *intel_encoder; |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 2777 | struct intel_sdvo_priv *sdvo_priv; |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 2778 | u8 ch[0x40]; |
| 2779 | int i; |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 2780 | |
Eric Anholt | 21d40d3 | 2010-03-25 11:11:14 -0700 | [diff] [blame] | 2781 | intel_encoder = kcalloc(sizeof(struct intel_encoder)+sizeof(struct intel_sdvo_priv), 1, GFP_KERNEL); |
| 2782 | if (!intel_encoder) { |
Eric Anholt | 7d57382 | 2009-01-02 13:33:00 -0800 | [diff] [blame] | 2783 | return false; |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 2784 | } |
| 2785 | |
Eric Anholt | 21d40d3 | 2010-03-25 11:11:14 -0700 | [diff] [blame] | 2786 | sdvo_priv = (struct intel_sdvo_priv *)(intel_encoder + 1); |
Eric Anholt | c751ce4 | 2010-03-25 11:48:48 -0700 | [diff] [blame] | 2787 | sdvo_priv->sdvo_reg = sdvo_reg; |
Keith Packard | 308cd3a | 2009-06-14 11:56:18 -0700 | [diff] [blame] | 2788 | |
Eric Anholt | 21d40d3 | 2010-03-25 11:11:14 -0700 | [diff] [blame] | 2789 | intel_encoder->dev_priv = sdvo_priv; |
| 2790 | intel_encoder->type = INTEL_OUTPUT_SDVO; |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 2791 | |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 2792 | /* setup the DDC bus. */ |
Eric Anholt | c751ce4 | 2010-03-25 11:48:48 -0700 | [diff] [blame] | 2793 | if (sdvo_reg == SDVOB) |
Eric Anholt | 21d40d3 | 2010-03-25 11:11:14 -0700 | [diff] [blame] | 2794 | intel_encoder->i2c_bus = intel_i2c_create(dev, GPIOE, "SDVOCTRL_E for SDVOB"); |
Keith Packard | 308cd3a | 2009-06-14 11:56:18 -0700 | [diff] [blame] | 2795 | else |
Eric Anholt | 21d40d3 | 2010-03-25 11:11:14 -0700 | [diff] [blame] | 2796 | intel_encoder->i2c_bus = intel_i2c_create(dev, GPIOE, "SDVOCTRL_E for SDVOC"); |
Keith Packard | 308cd3a | 2009-06-14 11:56:18 -0700 | [diff] [blame] | 2797 | |
Eric Anholt | 21d40d3 | 2010-03-25 11:11:14 -0700 | [diff] [blame] | 2798 | if (!intel_encoder->i2c_bus) |
Jonas Bonn | ad5b2a6 | 2009-05-15 09:10:41 +0200 | [diff] [blame] | 2799 | goto err_inteloutput; |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 2800 | |
Eric Anholt | c751ce4 | 2010-03-25 11:48:48 -0700 | [diff] [blame] | 2801 | sdvo_priv->slave_addr = intel_sdvo_get_slave_addr(dev, sdvo_reg); |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 2802 | |
Keith Packard | 308cd3a | 2009-06-14 11:56:18 -0700 | [diff] [blame] | 2803 | /* Save the bit-banging i2c functionality for use by the DDC wrapper */ |
Eric Anholt | 21d40d3 | 2010-03-25 11:11:14 -0700 | [diff] [blame] | 2804 | intel_sdvo_i2c_bit_algo.functionality = intel_encoder->i2c_bus->algo->functionality; |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 2805 | |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 2806 | /* Read the regs to test if we can talk to the device */ |
| 2807 | for (i = 0; i < 0x40; i++) { |
Eric Anholt | 21d40d3 | 2010-03-25 11:11:14 -0700 | [diff] [blame] | 2808 | if (!intel_sdvo_read_byte(intel_encoder, i, &ch[i])) { |
Zhao Yakui | 8a4c47f | 2009-07-20 13:48:04 +0800 | [diff] [blame] | 2809 | DRM_DEBUG_KMS("No SDVO device found on SDVO%c\n", |
Eric Anholt | c751ce4 | 2010-03-25 11:48:48 -0700 | [diff] [blame] | 2810 | sdvo_reg == SDVOB ? 'B' : 'C'); |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 2811 | goto err_i2c; |
| 2812 | } |
| 2813 | } |
| 2814 | |
Ma Ling | 619ac3b | 2009-05-18 16:12:46 +0800 | [diff] [blame] | 2815 | /* setup the DDC bus. */ |
Eric Anholt | c751ce4 | 2010-03-25 11:48:48 -0700 | [diff] [blame] | 2816 | if (sdvo_reg == SDVOB) { |
Eric Anholt | 21d40d3 | 2010-03-25 11:11:14 -0700 | [diff] [blame] | 2817 | intel_encoder->ddc_bus = intel_i2c_create(dev, GPIOE, "SDVOB DDC BUS"); |
Keith Packard | 57cdaf9 | 2009-09-04 13:07:54 +0800 | [diff] [blame] | 2818 | sdvo_priv->analog_ddc_bus = intel_i2c_create(dev, GPIOA, |
| 2819 | "SDVOB/VGA DDC BUS"); |
Jesse Barnes | b01f2c3 | 2009-12-11 11:07:17 -0800 | [diff] [blame] | 2820 | dev_priv->hotplug_supported_mask |= SDVOB_HOTPLUG_INT_STATUS; |
Keith Packard | 57cdaf9 | 2009-09-04 13:07:54 +0800 | [diff] [blame] | 2821 | } else { |
Eric Anholt | 21d40d3 | 2010-03-25 11:11:14 -0700 | [diff] [blame] | 2822 | intel_encoder->ddc_bus = intel_i2c_create(dev, GPIOE, "SDVOC DDC BUS"); |
Keith Packard | 57cdaf9 | 2009-09-04 13:07:54 +0800 | [diff] [blame] | 2823 | sdvo_priv->analog_ddc_bus = intel_i2c_create(dev, GPIOA, |
| 2824 | "SDVOC/VGA DDC BUS"); |
Jesse Barnes | b01f2c3 | 2009-12-11 11:07:17 -0800 | [diff] [blame] | 2825 | dev_priv->hotplug_supported_mask |= SDVOC_HOTPLUG_INT_STATUS; |
Keith Packard | 57cdaf9 | 2009-09-04 13:07:54 +0800 | [diff] [blame] | 2826 | } |
Ma Ling | 619ac3b | 2009-05-18 16:12:46 +0800 | [diff] [blame] | 2827 | |
Eric Anholt | 21d40d3 | 2010-03-25 11:11:14 -0700 | [diff] [blame] | 2828 | if (intel_encoder->ddc_bus == NULL) |
Ma Ling | 619ac3b | 2009-05-18 16:12:46 +0800 | [diff] [blame] | 2829 | goto err_i2c; |
| 2830 | |
Keith Packard | 308cd3a | 2009-06-14 11:56:18 -0700 | [diff] [blame] | 2831 | /* Wrap with our custom algo which switches to DDC mode */ |
Eric Anholt | 21d40d3 | 2010-03-25 11:11:14 -0700 | [diff] [blame] | 2832 | intel_encoder->ddc_bus->algo = &intel_sdvo_i2c_bit_algo; |
Ma Ling | 619ac3b | 2009-05-18 16:12:46 +0800 | [diff] [blame] | 2833 | |
Zhenyu Wang | 14571b4 | 2010-03-30 14:06:33 +0800 | [diff] [blame] | 2834 | /* encoder type will be decided later */ |
| 2835 | drm_encoder_init(dev, &intel_encoder->enc, &intel_sdvo_enc_funcs, 0); |
| 2836 | drm_encoder_helper_add(&intel_encoder->enc, &intel_sdvo_helper_funcs); |
| 2837 | |
André Goddard Rosa | af901ca | 2009-11-14 13:09:05 -0200 | [diff] [blame] | 2838 | /* In default case sdvo lvds is false */ |
Eric Anholt | 21d40d3 | 2010-03-25 11:11:14 -0700 | [diff] [blame] | 2839 | intel_sdvo_get_capabilities(intel_encoder, &sdvo_priv->caps); |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 2840 | |
Zhenyu Wang | 14571b4 | 2010-03-30 14:06:33 +0800 | [diff] [blame] | 2841 | if (intel_sdvo_output_setup(intel_encoder, |
ling.ma@intel.com | fb7a46f | 2009-07-23 17:11:34 +0800 | [diff] [blame] | 2842 | sdvo_priv->caps.output_flags) != true) { |
Dave Airlie | 51c8b40 | 2009-08-20 13:38:04 +1000 | [diff] [blame] | 2843 | DRM_DEBUG_KMS("SDVO output failed to setup on SDVO%c\n", |
Eric Anholt | c751ce4 | 2010-03-25 11:48:48 -0700 | [diff] [blame] | 2844 | sdvo_reg == SDVOB ? 'B' : 'C'); |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 2845 | goto err_i2c; |
| 2846 | } |
| 2847 | |
Jesse Barnes | e2f0ba9 | 2009-02-02 15:11:52 -0800 | [diff] [blame] | 2848 | intel_sdvo_select_ddc_bus(sdvo_priv); |
| 2849 | |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 2850 | /* Set the input timing to the screen. Assume always input 0. */ |
Eric Anholt | 21d40d3 | 2010-03-25 11:11:14 -0700 | [diff] [blame] | 2851 | intel_sdvo_set_target_input(intel_encoder, true, false); |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 2852 | |
Eric Anholt | 21d40d3 | 2010-03-25 11:11:14 -0700 | [diff] [blame] | 2853 | intel_sdvo_get_input_pixel_clock_range(intel_encoder, |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 2854 | &sdvo_priv->pixel_clock_min, |
| 2855 | &sdvo_priv->pixel_clock_max); |
| 2856 | |
| 2857 | |
Zhao Yakui | 8a4c47f | 2009-07-20 13:48:04 +0800 | [diff] [blame] | 2858 | DRM_DEBUG_KMS("%s device VID/DID: %02X:%02X.%02X, " |
yakui_zhao | 342dc38 | 2009-06-02 14:12:00 +0800 | [diff] [blame] | 2859 | "clock range %dMHz - %dMHz, " |
| 2860 | "input 1: %c, input 2: %c, " |
| 2861 | "output 1: %c, output 2: %c\n", |
| 2862 | SDVO_NAME(sdvo_priv), |
| 2863 | sdvo_priv->caps.vendor_id, sdvo_priv->caps.device_id, |
| 2864 | sdvo_priv->caps.device_rev_id, |
| 2865 | sdvo_priv->pixel_clock_min / 1000, |
| 2866 | sdvo_priv->pixel_clock_max / 1000, |
| 2867 | (sdvo_priv->caps.sdvo_inputs_mask & 0x1) ? 'Y' : 'N', |
| 2868 | (sdvo_priv->caps.sdvo_inputs_mask & 0x2) ? 'Y' : 'N', |
| 2869 | /* check currently supported outputs */ |
| 2870 | sdvo_priv->caps.output_flags & |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 2871 | (SDVO_OUTPUT_TMDS0 | SDVO_OUTPUT_RGB0) ? 'Y' : 'N', |
yakui_zhao | 342dc38 | 2009-06-02 14:12:00 +0800 | [diff] [blame] | 2872 | sdvo_priv->caps.output_flags & |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 2873 | (SDVO_OUTPUT_TMDS1 | SDVO_OUTPUT_RGB1) ? 'Y' : 'N'); |
| 2874 | |
Eric Anholt | 7d57382 | 2009-01-02 13:33:00 -0800 | [diff] [blame] | 2875 | return true; |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 2876 | |
| 2877 | err_i2c: |
Keith Packard | 57cdaf9 | 2009-09-04 13:07:54 +0800 | [diff] [blame] | 2878 | if (sdvo_priv->analog_ddc_bus != NULL) |
| 2879 | intel_i2c_destroy(sdvo_priv->analog_ddc_bus); |
Eric Anholt | 21d40d3 | 2010-03-25 11:11:14 -0700 | [diff] [blame] | 2880 | if (intel_encoder->ddc_bus != NULL) |
| 2881 | intel_i2c_destroy(intel_encoder->ddc_bus); |
| 2882 | if (intel_encoder->i2c_bus != NULL) |
| 2883 | intel_i2c_destroy(intel_encoder->i2c_bus); |
Jonas Bonn | ad5b2a6 | 2009-05-15 09:10:41 +0200 | [diff] [blame] | 2884 | err_inteloutput: |
Eric Anholt | 21d40d3 | 2010-03-25 11:11:14 -0700 | [diff] [blame] | 2885 | kfree(intel_encoder); |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 2886 | |
Eric Anholt | 7d57382 | 2009-01-02 13:33:00 -0800 | [diff] [blame] | 2887 | return false; |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 2888 | } |