Ben Skeggs | 4b223ee | 2010-08-03 10:00:56 +1000 | [diff] [blame] | 1 | /* |
| 2 | * Copyright 2010 Red Hat Inc. |
| 3 | * |
| 4 | * Permission is hereby granted, free of charge, to any person obtaining a |
| 5 | * copy of this software and associated documentation files (the "Software"), |
| 6 | * to deal in the Software without restriction, including without limitation |
| 7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, |
| 8 | * and/or sell copies of the Software, and to permit persons to whom the |
| 9 | * Software is furnished to do so, subject to the following conditions: |
| 10 | * |
| 11 | * The above copyright notice and this permission notice shall be included in |
| 12 | * all copies or substantial portions of the Software. |
| 13 | * |
| 14 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
| 15 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
| 16 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
| 17 | * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR |
| 18 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, |
| 19 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR |
| 20 | * OTHER DEALINGS IN THE SOFTWARE. |
| 21 | * |
| 22 | * Authors: Ben Skeggs |
| 23 | */ |
| 24 | |
Ben Skeggs | 966a5b7 | 2010-11-24 10:49:02 +1000 | [diff] [blame] | 25 | #include <linux/firmware.h> |
| 26 | |
Ben Skeggs | 4b223ee | 2010-08-03 10:00:56 +1000 | [diff] [blame] | 27 | #include "drmP.h" |
| 28 | |
| 29 | #include "nouveau_drv.h" |
Ben Skeggs | 966a5b7 | 2010-11-24 10:49:02 +1000 | [diff] [blame] | 30 | #include "nouveau_mm.h" |
Ben Skeggs | 0411de8 | 2011-05-25 18:32:44 +1000 | [diff] [blame] | 31 | |
Ben Skeggs | 966a5b7 | 2010-11-24 10:49:02 +1000 | [diff] [blame] | 32 | #include "nvc0_graph.h" |
Ben Skeggs | 0411de8 | 2011-05-25 18:32:44 +1000 | [diff] [blame] | 33 | #include "nvc0_grhub.fuc.h" |
| 34 | #include "nvc0_grgpc.fuc.h" |
| 35 | |
| 36 | static void |
| 37 | nvc0_graph_ctxctl_debug_unit(struct drm_device *dev, u32 base) |
| 38 | { |
| 39 | NV_INFO(dev, "PGRAPH: %06x - done 0x%08x\n", base, |
| 40 | nv_rd32(dev, base + 0x400)); |
| 41 | NV_INFO(dev, "PGRAPH: %06x - stat 0x%08x 0x%08x 0x%08x 0x%08x\n", base, |
| 42 | nv_rd32(dev, base + 0x800), nv_rd32(dev, base + 0x804), |
| 43 | nv_rd32(dev, base + 0x808), nv_rd32(dev, base + 0x80c)); |
| 44 | NV_INFO(dev, "PGRAPH: %06x - stat 0x%08x 0x%08x 0x%08x 0x%08x\n", base, |
| 45 | nv_rd32(dev, base + 0x810), nv_rd32(dev, base + 0x814), |
| 46 | nv_rd32(dev, base + 0x818), nv_rd32(dev, base + 0x81c)); |
| 47 | } |
| 48 | |
| 49 | static void |
| 50 | nvc0_graph_ctxctl_debug(struct drm_device *dev) |
| 51 | { |
| 52 | u32 gpcnr = nv_rd32(dev, 0x409604) & 0xffff; |
| 53 | u32 gpc; |
| 54 | |
| 55 | nvc0_graph_ctxctl_debug_unit(dev, 0x409000); |
| 56 | for (gpc = 0; gpc < gpcnr; gpc++) |
| 57 | nvc0_graph_ctxctl_debug_unit(dev, 0x502000 + (gpc * 0x8000)); |
| 58 | } |
Ben Skeggs | 966a5b7 | 2010-11-24 10:49:02 +1000 | [diff] [blame] | 59 | |
Ben Skeggs | 966a5b7 | 2010-11-24 10:49:02 +1000 | [diff] [blame] | 60 | static int |
Ben Skeggs | 7a45cd1 | 2011-04-01 10:59:53 +1000 | [diff] [blame] | 61 | nvc0_graph_load_context(struct nouveau_channel *chan) |
| 62 | { |
| 63 | struct drm_device *dev = chan->dev; |
| 64 | |
| 65 | nv_wr32(dev, 0x409840, 0x00000030); |
| 66 | nv_wr32(dev, 0x409500, 0x80000000 | chan->ramin->vinst >> 12); |
| 67 | nv_wr32(dev, 0x409504, 0x00000003); |
| 68 | if (!nv_wait(dev, 0x409800, 0x00000010, 0x00000010)) |
| 69 | NV_ERROR(dev, "PGRAPH: load_ctx timeout\n"); |
| 70 | |
| 71 | return 0; |
| 72 | } |
| 73 | |
| 74 | static int |
| 75 | nvc0_graph_unload_context_to(struct drm_device *dev, u64 chan) |
| 76 | { |
| 77 | nv_wr32(dev, 0x409840, 0x00000003); |
| 78 | nv_wr32(dev, 0x409500, 0x80000000 | chan >> 12); |
| 79 | nv_wr32(dev, 0x409504, 0x00000009); |
| 80 | if (!nv_wait(dev, 0x409800, 0x00000001, 0x00000000)) { |
| 81 | NV_ERROR(dev, "PGRAPH: unload_ctx timeout\n"); |
| 82 | return -EBUSY; |
| 83 | } |
| 84 | |
| 85 | return 0; |
| 86 | } |
| 87 | |
| 88 | static int |
Ben Skeggs | 966a5b7 | 2010-11-24 10:49:02 +1000 | [diff] [blame] | 89 | nvc0_graph_construct_context(struct nouveau_channel *chan) |
| 90 | { |
| 91 | struct drm_nouveau_private *dev_priv = chan->dev->dev_private; |
Ben Skeggs | 7a45cd1 | 2011-04-01 10:59:53 +1000 | [diff] [blame] | 92 | struct nvc0_graph_priv *priv = nv_engine(chan->dev, NVOBJ_ENGINE_GR); |
| 93 | struct nvc0_graph_chan *grch = chan->engctx[NVOBJ_ENGINE_GR]; |
Ben Skeggs | 966a5b7 | 2010-11-24 10:49:02 +1000 | [diff] [blame] | 94 | struct drm_device *dev = chan->dev; |
| 95 | int ret, i; |
| 96 | u32 *ctx; |
| 97 | |
| 98 | ctx = kmalloc(priv->grctx_size, GFP_KERNEL); |
| 99 | if (!ctx) |
| 100 | return -ENOMEM; |
| 101 | |
Ben Skeggs | 0411de8 | 2011-05-25 18:32:44 +1000 | [diff] [blame] | 102 | if (!nouveau_ctxfw) { |
| 103 | nv_wr32(dev, 0x409840, 0x80000000); |
| 104 | nv_wr32(dev, 0x409500, 0x80000000 | chan->ramin->vinst >> 12); |
| 105 | nv_wr32(dev, 0x409504, 0x00000001); |
| 106 | if (!nv_wait(dev, 0x409800, 0x80000000, 0x80000000)) { |
| 107 | NV_ERROR(dev, "PGRAPH: HUB_SET_CHAN timeout\n"); |
| 108 | nvc0_graph_ctxctl_debug(dev); |
| 109 | return -EBUSY; |
| 110 | } |
| 111 | } else { |
| 112 | nvc0_graph_load_context(chan); |
Ben Skeggs | 966a5b7 | 2010-11-24 10:49:02 +1000 | [diff] [blame] | 113 | |
Ben Skeggs | 0411de8 | 2011-05-25 18:32:44 +1000 | [diff] [blame] | 114 | nv_wo32(grch->grctx, 0x1c, 1); |
| 115 | nv_wo32(grch->grctx, 0x20, 0); |
| 116 | nv_wo32(grch->grctx, 0x28, 0); |
| 117 | nv_wo32(grch->grctx, 0x2c, 0); |
| 118 | dev_priv->engine.instmem.flush(dev); |
| 119 | } |
Ben Skeggs | 966a5b7 | 2010-11-24 10:49:02 +1000 | [diff] [blame] | 120 | |
| 121 | ret = nvc0_grctx_generate(chan); |
| 122 | if (ret) { |
| 123 | kfree(ctx); |
| 124 | return ret; |
| 125 | } |
| 126 | |
Ben Skeggs | 0411de8 | 2011-05-25 18:32:44 +1000 | [diff] [blame] | 127 | if (!nouveau_ctxfw) { |
| 128 | nv_wr32(dev, 0x409840, 0x80000000); |
| 129 | nv_wr32(dev, 0x409500, 0x80000000 | chan->ramin->vinst >> 12); |
| 130 | nv_wr32(dev, 0x409504, 0x00000002); |
| 131 | if (!nv_wait(dev, 0x409800, 0x80000000, 0x80000000)) { |
| 132 | NV_ERROR(dev, "PGRAPH: HUB_CTX_SAVE timeout\n"); |
| 133 | nvc0_graph_ctxctl_debug(dev); |
| 134 | return -EBUSY; |
| 135 | } |
| 136 | } else { |
| 137 | ret = nvc0_graph_unload_context_to(dev, chan->ramin->vinst); |
| 138 | if (ret) { |
| 139 | kfree(ctx); |
| 140 | return ret; |
| 141 | } |
Ben Skeggs | 966a5b7 | 2010-11-24 10:49:02 +1000 | [diff] [blame] | 142 | } |
| 143 | |
| 144 | for (i = 0; i < priv->grctx_size; i += 4) |
| 145 | ctx[i / 4] = nv_ro32(grch->grctx, i); |
| 146 | |
| 147 | priv->grctx_vals = ctx; |
| 148 | return 0; |
| 149 | } |
| 150 | |
| 151 | static int |
| 152 | nvc0_graph_create_context_mmio_list(struct nouveau_channel *chan) |
| 153 | { |
Ben Skeggs | 7a45cd1 | 2011-04-01 10:59:53 +1000 | [diff] [blame] | 154 | struct nvc0_graph_priv *priv = nv_engine(chan->dev, NVOBJ_ENGINE_GR); |
| 155 | struct nvc0_graph_chan *grch = chan->engctx[NVOBJ_ENGINE_GR]; |
Ben Skeggs | 966a5b7 | 2010-11-24 10:49:02 +1000 | [diff] [blame] | 156 | struct drm_device *dev = chan->dev; |
| 157 | int i = 0, gpc, tp, ret; |
| 158 | u32 magic; |
| 159 | |
| 160 | ret = nouveau_gpuobj_new(dev, NULL, 0x2000, 256, NVOBJ_FLAG_VM, |
| 161 | &grch->unk408004); |
| 162 | if (ret) |
| 163 | return ret; |
| 164 | |
| 165 | ret = nouveau_gpuobj_new(dev, NULL, 0x8000, 256, NVOBJ_FLAG_VM, |
| 166 | &grch->unk40800c); |
| 167 | if (ret) |
| 168 | return ret; |
| 169 | |
Ben Skeggs | c906ca0 | 2011-01-14 10:27:02 +1000 | [diff] [blame] | 170 | ret = nouveau_gpuobj_new(dev, NULL, 384 * 1024, 4096, |
| 171 | NVOBJ_FLAG_VM | NVOBJ_FLAG_VM_USER, |
Ben Skeggs | 966a5b7 | 2010-11-24 10:49:02 +1000 | [diff] [blame] | 172 | &grch->unk418810); |
| 173 | if (ret) |
| 174 | return ret; |
| 175 | |
| 176 | ret = nouveau_gpuobj_new(dev, NULL, 0x1000, 0, NVOBJ_FLAG_VM, |
| 177 | &grch->mmio); |
| 178 | if (ret) |
| 179 | return ret; |
| 180 | |
| 181 | |
| 182 | nv_wo32(grch->mmio, i++ * 4, 0x00408004); |
Ben Skeggs | f8522fc | 2011-05-25 17:22:43 +1000 | [diff] [blame] | 183 | nv_wo32(grch->mmio, i++ * 4, grch->unk408004->linst >> 8); |
Ben Skeggs | 966a5b7 | 2010-11-24 10:49:02 +1000 | [diff] [blame] | 184 | nv_wo32(grch->mmio, i++ * 4, 0x00408008); |
| 185 | nv_wo32(grch->mmio, i++ * 4, 0x80000018); |
| 186 | |
| 187 | nv_wo32(grch->mmio, i++ * 4, 0x0040800c); |
Ben Skeggs | f8522fc | 2011-05-25 17:22:43 +1000 | [diff] [blame] | 188 | nv_wo32(grch->mmio, i++ * 4, grch->unk40800c->linst >> 8); |
Ben Skeggs | 966a5b7 | 2010-11-24 10:49:02 +1000 | [diff] [blame] | 189 | nv_wo32(grch->mmio, i++ * 4, 0x00408010); |
| 190 | nv_wo32(grch->mmio, i++ * 4, 0x80000000); |
| 191 | |
| 192 | nv_wo32(grch->mmio, i++ * 4, 0x00418810); |
Ben Skeggs | f8522fc | 2011-05-25 17:22:43 +1000 | [diff] [blame] | 193 | nv_wo32(grch->mmio, i++ * 4, 0x80000000 | grch->unk418810->linst >> 12); |
Ben Skeggs | 966a5b7 | 2010-11-24 10:49:02 +1000 | [diff] [blame] | 194 | nv_wo32(grch->mmio, i++ * 4, 0x00419848); |
Ben Skeggs | f8522fc | 2011-05-25 17:22:43 +1000 | [diff] [blame] | 195 | nv_wo32(grch->mmio, i++ * 4, 0x10000000 | grch->unk418810->linst >> 12); |
Ben Skeggs | 966a5b7 | 2010-11-24 10:49:02 +1000 | [diff] [blame] | 196 | |
| 197 | nv_wo32(grch->mmio, i++ * 4, 0x00419004); |
Ben Skeggs | f8522fc | 2011-05-25 17:22:43 +1000 | [diff] [blame] | 198 | nv_wo32(grch->mmio, i++ * 4, grch->unk40800c->linst >> 8); |
Ben Skeggs | 966a5b7 | 2010-11-24 10:49:02 +1000 | [diff] [blame] | 199 | nv_wo32(grch->mmio, i++ * 4, 0x00419008); |
| 200 | nv_wo32(grch->mmio, i++ * 4, 0x00000000); |
| 201 | |
| 202 | nv_wo32(grch->mmio, i++ * 4, 0x00418808); |
Ben Skeggs | f8522fc | 2011-05-25 17:22:43 +1000 | [diff] [blame] | 203 | nv_wo32(grch->mmio, i++ * 4, grch->unk408004->linst >> 8); |
Ben Skeggs | 966a5b7 | 2010-11-24 10:49:02 +1000 | [diff] [blame] | 204 | nv_wo32(grch->mmio, i++ * 4, 0x0041880c); |
| 205 | nv_wo32(grch->mmio, i++ * 4, 0x80000018); |
| 206 | |
| 207 | magic = 0x02180000; |
| 208 | nv_wo32(grch->mmio, i++ * 4, 0x00405830); |
| 209 | nv_wo32(grch->mmio, i++ * 4, magic); |
| 210 | for (gpc = 0; gpc < priv->gpc_nr; gpc++) { |
Ben Skeggs | e1b89b1 | 2011-05-24 14:57:53 +1000 | [diff] [blame] | 211 | for (tp = 0; tp < priv->tp_nr[gpc]; tp++, magic += 0x0324) { |
Ben Skeggs | 966a5b7 | 2010-11-24 10:49:02 +1000 | [diff] [blame] | 212 | u32 reg = 0x504520 + (gpc * 0x8000) + (tp * 0x0800); |
| 213 | nv_wo32(grch->mmio, i++ * 4, reg); |
| 214 | nv_wo32(grch->mmio, i++ * 4, magic); |
| 215 | } |
| 216 | } |
| 217 | |
| 218 | grch->mmio_nr = i / 2; |
| 219 | return 0; |
| 220 | } |
| 221 | |
Ben Skeggs | 7a45cd1 | 2011-04-01 10:59:53 +1000 | [diff] [blame] | 222 | static int |
| 223 | nvc0_graph_context_new(struct nouveau_channel *chan, int engine) |
Ben Skeggs | 4b223ee | 2010-08-03 10:00:56 +1000 | [diff] [blame] | 224 | { |
Ben Skeggs | 966a5b7 | 2010-11-24 10:49:02 +1000 | [diff] [blame] | 225 | struct drm_device *dev = chan->dev; |
Ben Skeggs | 7a45cd1 | 2011-04-01 10:59:53 +1000 | [diff] [blame] | 226 | struct drm_nouveau_private *dev_priv = dev->dev_private; |
| 227 | struct nouveau_instmem_engine *pinstmem = &dev_priv->engine.instmem; |
| 228 | struct nvc0_graph_priv *priv = nv_engine(dev, engine); |
| 229 | struct nvc0_graph_chan *grch; |
Ben Skeggs | 966a5b7 | 2010-11-24 10:49:02 +1000 | [diff] [blame] | 230 | struct nouveau_gpuobj *grctx; |
| 231 | int ret, i; |
| 232 | |
Ben Skeggs | 7a45cd1 | 2011-04-01 10:59:53 +1000 | [diff] [blame] | 233 | grch = kzalloc(sizeof(*grch), GFP_KERNEL); |
| 234 | if (!grch) |
Ben Skeggs | 966a5b7 | 2010-11-24 10:49:02 +1000 | [diff] [blame] | 235 | return -ENOMEM; |
Ben Skeggs | 7a45cd1 | 2011-04-01 10:59:53 +1000 | [diff] [blame] | 236 | chan->engctx[NVOBJ_ENGINE_GR] = grch; |
Ben Skeggs | 966a5b7 | 2010-11-24 10:49:02 +1000 | [diff] [blame] | 237 | |
| 238 | ret = nouveau_gpuobj_new(dev, NULL, priv->grctx_size, 256, |
| 239 | NVOBJ_FLAG_VM | NVOBJ_FLAG_ZERO_ALLOC, |
| 240 | &grch->grctx); |
| 241 | if (ret) |
| 242 | goto error; |
Ben Skeggs | 966a5b7 | 2010-11-24 10:49:02 +1000 | [diff] [blame] | 243 | grctx = grch->grctx; |
| 244 | |
| 245 | ret = nvc0_graph_create_context_mmio_list(chan); |
| 246 | if (ret) |
| 247 | goto error; |
| 248 | |
Ben Skeggs | f8522fc | 2011-05-25 17:22:43 +1000 | [diff] [blame] | 249 | nv_wo32(chan->ramin, 0x0210, lower_32_bits(grctx->linst) | 4); |
| 250 | nv_wo32(chan->ramin, 0x0214, upper_32_bits(grctx->linst)); |
Ben Skeggs | 966a5b7 | 2010-11-24 10:49:02 +1000 | [diff] [blame] | 251 | pinstmem->flush(dev); |
| 252 | |
| 253 | if (!priv->grctx_vals) { |
| 254 | ret = nvc0_graph_construct_context(chan); |
| 255 | if (ret) |
| 256 | goto error; |
| 257 | } |
| 258 | |
| 259 | for (i = 0; i < priv->grctx_size; i += 4) |
| 260 | nv_wo32(grctx, i, priv->grctx_vals[i / 4]); |
| 261 | |
Ben Skeggs | 0411de8 | 2011-05-25 18:32:44 +1000 | [diff] [blame] | 262 | if (!nouveau_ctxfw) { |
| 263 | nv_wo32(grctx, 0x00, grch->mmio_nr); |
| 264 | nv_wo32(grctx, 0x04, grch->mmio->linst >> 8); |
| 265 | } else { |
| 266 | nv_wo32(grctx, 0xf4, 0); |
| 267 | nv_wo32(grctx, 0xf8, 0); |
| 268 | nv_wo32(grctx, 0x10, grch->mmio_nr); |
| 269 | nv_wo32(grctx, 0x14, lower_32_bits(grch->mmio->linst)); |
| 270 | nv_wo32(grctx, 0x18, upper_32_bits(grch->mmio->linst)); |
| 271 | nv_wo32(grctx, 0x1c, 1); |
| 272 | nv_wo32(grctx, 0x20, 0); |
| 273 | nv_wo32(grctx, 0x28, 0); |
| 274 | nv_wo32(grctx, 0x2c, 0); |
| 275 | } |
Ben Skeggs | 966a5b7 | 2010-11-24 10:49:02 +1000 | [diff] [blame] | 276 | pinstmem->flush(dev); |
Ben Skeggs | 4b223ee | 2010-08-03 10:00:56 +1000 | [diff] [blame] | 277 | return 0; |
Ben Skeggs | 966a5b7 | 2010-11-24 10:49:02 +1000 | [diff] [blame] | 278 | |
| 279 | error: |
Ben Skeggs | 7a45cd1 | 2011-04-01 10:59:53 +1000 | [diff] [blame] | 280 | priv->base.context_del(chan, engine); |
Ben Skeggs | 966a5b7 | 2010-11-24 10:49:02 +1000 | [diff] [blame] | 281 | return ret; |
Ben Skeggs | 4b223ee | 2010-08-03 10:00:56 +1000 | [diff] [blame] | 282 | } |
| 283 | |
Ben Skeggs | 7a45cd1 | 2011-04-01 10:59:53 +1000 | [diff] [blame] | 284 | static void |
| 285 | nvc0_graph_context_del(struct nouveau_channel *chan, int engine) |
Ben Skeggs | 4b223ee | 2010-08-03 10:00:56 +1000 | [diff] [blame] | 286 | { |
Ben Skeggs | 7a45cd1 | 2011-04-01 10:59:53 +1000 | [diff] [blame] | 287 | struct nvc0_graph_chan *grch = chan->engctx[engine]; |
Ben Skeggs | 966a5b7 | 2010-11-24 10:49:02 +1000 | [diff] [blame] | 288 | |
| 289 | nouveau_gpuobj_ref(NULL, &grch->mmio); |
| 290 | nouveau_gpuobj_ref(NULL, &grch->unk418810); |
| 291 | nouveau_gpuobj_ref(NULL, &grch->unk40800c); |
| 292 | nouveau_gpuobj_ref(NULL, &grch->unk408004); |
| 293 | nouveau_gpuobj_ref(NULL, &grch->grctx); |
Ben Skeggs | 7a45cd1 | 2011-04-01 10:59:53 +1000 | [diff] [blame] | 294 | chan->engctx[engine] = NULL; |
Ben Skeggs | 4b223ee | 2010-08-03 10:00:56 +1000 | [diff] [blame] | 295 | } |
| 296 | |
Ben Skeggs | 7a45cd1 | 2011-04-01 10:59:53 +1000 | [diff] [blame] | 297 | static int |
| 298 | nvc0_graph_object_new(struct nouveau_channel *chan, int engine, |
| 299 | u32 handle, u16 class) |
Ben Skeggs | 4b223ee | 2010-08-03 10:00:56 +1000 | [diff] [blame] | 300 | { |
Ben Skeggs | 966a5b7 | 2010-11-24 10:49:02 +1000 | [diff] [blame] | 301 | return 0; |
| 302 | } |
| 303 | |
| 304 | static int |
Ben Skeggs | 7a45cd1 | 2011-04-01 10:59:53 +1000 | [diff] [blame] | 305 | nvc0_graph_fini(struct drm_device *dev, int engine) |
Ben Skeggs | 966a5b7 | 2010-11-24 10:49:02 +1000 | [diff] [blame] | 306 | { |
Ben Skeggs | 4b223ee | 2010-08-03 10:00:56 +1000 | [diff] [blame] | 307 | return 0; |
| 308 | } |
| 309 | |
Ben Skeggs | 966a5b7 | 2010-11-24 10:49:02 +1000 | [diff] [blame] | 310 | static int |
Ben Skeggs | bd2f203 | 2011-02-08 15:16:23 +1000 | [diff] [blame] | 311 | nvc0_graph_mthd_page_flip(struct nouveau_channel *chan, |
| 312 | u32 class, u32 mthd, u32 data) |
| 313 | { |
| 314 | nouveau_finish_page_flip(chan, NULL); |
| 315 | return 0; |
| 316 | } |
| 317 | |
Ben Skeggs | 966a5b7 | 2010-11-24 10:49:02 +1000 | [diff] [blame] | 318 | static void |
| 319 | nvc0_graph_init_obj418880(struct drm_device *dev) |
| 320 | { |
Ben Skeggs | 7a45cd1 | 2011-04-01 10:59:53 +1000 | [diff] [blame] | 321 | struct nvc0_graph_priv *priv = nv_engine(dev, NVOBJ_ENGINE_GR); |
Ben Skeggs | 966a5b7 | 2010-11-24 10:49:02 +1000 | [diff] [blame] | 322 | int i; |
| 323 | |
| 324 | nv_wr32(dev, GPC_BCAST(0x0880), 0x00000000); |
| 325 | nv_wr32(dev, GPC_BCAST(0x08a4), 0x00000000); |
| 326 | for (i = 0; i < 4; i++) |
| 327 | nv_wr32(dev, GPC_BCAST(0x0888) + (i * 4), 0x00000000); |
| 328 | nv_wr32(dev, GPC_BCAST(0x08b4), priv->unk4188b4->vinst >> 8); |
| 329 | nv_wr32(dev, GPC_BCAST(0x08b8), priv->unk4188b8->vinst >> 8); |
| 330 | } |
| 331 | |
| 332 | static void |
| 333 | nvc0_graph_init_regs(struct drm_device *dev) |
| 334 | { |
| 335 | nv_wr32(dev, 0x400080, 0x003083c2); |
| 336 | nv_wr32(dev, 0x400088, 0x00006fe7); |
| 337 | nv_wr32(dev, 0x40008c, 0x00000000); |
| 338 | nv_wr32(dev, 0x400090, 0x00000030); |
| 339 | nv_wr32(dev, 0x40013c, 0x013901f7); |
| 340 | nv_wr32(dev, 0x400140, 0x00000100); |
| 341 | nv_wr32(dev, 0x400144, 0x00000000); |
| 342 | nv_wr32(dev, 0x400148, 0x00000110); |
| 343 | nv_wr32(dev, 0x400138, 0x00000000); |
| 344 | nv_wr32(dev, 0x400130, 0x00000000); |
| 345 | nv_wr32(dev, 0x400134, 0x00000000); |
| 346 | nv_wr32(dev, 0x400124, 0x00000002); |
| 347 | } |
| 348 | |
| 349 | static void |
| 350 | nvc0_graph_init_gpc_0(struct drm_device *dev) |
| 351 | { |
Ben Skeggs | 7a45cd1 | 2011-04-01 10:59:53 +1000 | [diff] [blame] | 352 | struct nvc0_graph_priv *priv = nv_engine(dev, NVOBJ_ENGINE_GR); |
Ben Skeggs | aa58c40 | 2011-04-18 12:52:47 +1000 | [diff] [blame] | 353 | u32 data[TP_MAX / 8]; |
| 354 | u8 tpnr[GPC_MAX]; |
| 355 | int i, gpc, tpc; |
Ben Skeggs | 966a5b7 | 2010-11-24 10:49:02 +1000 | [diff] [blame] | 356 | |
Emil Velikov | f212949 | 2011-03-19 23:31:52 +0000 | [diff] [blame] | 357 | /* |
| 358 | * TP ROP UNKVAL(magic_not_rop_nr) |
| 359 | * 450: 4/0/0/0 2 3 |
| 360 | * 460: 3/4/0/0 4 1 |
| 361 | * 465: 3/4/4/0 4 7 |
| 362 | * 470: 3/3/4/4 5 5 |
| 363 | * 480: 3/4/4/4 6 6 |
Ben Skeggs | aa58c40 | 2011-04-18 12:52:47 +1000 | [diff] [blame] | 364 | * |
Emil Velikov | f212949 | 2011-03-19 23:31:52 +0000 | [diff] [blame] | 365 | * magicgpc918 |
| 366 | * 450: 00200000 00000000001000000000000000000000 |
| 367 | * 460: 00124925 00000000000100100100100100100101 |
| 368 | * 465: 000ba2e9 00000000000010111010001011101001 |
| 369 | * 470: 00092493 00000000000010010010010010010011 |
| 370 | * 480: 00088889 00000000000010001000100010001001 |
Emil Velikov | f212949 | 2011-03-19 23:31:52 +0000 | [diff] [blame] | 371 | */ |
| 372 | |
Ben Skeggs | aa58c40 | 2011-04-18 12:52:47 +1000 | [diff] [blame] | 373 | memset(data, 0x00, sizeof(data)); |
| 374 | memcpy(tpnr, priv->tp_nr, sizeof(priv->tp_nr)); |
| 375 | for (i = 0, gpc = -1; i < priv->tp_total; i++) { |
| 376 | do { |
| 377 | gpc = (gpc + 1) % priv->gpc_nr; |
| 378 | } while (!tpnr[gpc]); |
| 379 | tpc = priv->tp_nr[gpc] - tpnr[gpc]--; |
| 380 | |
| 381 | data[i / 8] |= tpc << ((i % 8) * 4); |
| 382 | } |
| 383 | |
| 384 | nv_wr32(dev, GPC_BCAST(0x0980), data[0]); |
| 385 | nv_wr32(dev, GPC_BCAST(0x0984), data[1]); |
| 386 | nv_wr32(dev, GPC_BCAST(0x0988), data[2]); |
| 387 | nv_wr32(dev, GPC_BCAST(0x098c), data[3]); |
Ben Skeggs | 966a5b7 | 2010-11-24 10:49:02 +1000 | [diff] [blame] | 388 | |
| 389 | for (gpc = 0; gpc < priv->gpc_nr; gpc++) { |
| 390 | nv_wr32(dev, GPC_UNIT(gpc, 0x0914), priv->magic_not_rop_nr << 8 | |
| 391 | priv->tp_nr[gpc]); |
| 392 | nv_wr32(dev, GPC_UNIT(gpc, 0x0910), 0x00040000 | priv->tp_total); |
| 393 | nv_wr32(dev, GPC_UNIT(gpc, 0x0918), priv->magicgpc918); |
| 394 | } |
| 395 | |
| 396 | nv_wr32(dev, GPC_BCAST(0x1bd4), priv->magicgpc918); |
| 397 | nv_wr32(dev, GPC_BCAST(0x08ac), priv->rop_nr); |
| 398 | } |
| 399 | |
| 400 | static void |
| 401 | nvc0_graph_init_units(struct drm_device *dev) |
| 402 | { |
| 403 | nv_wr32(dev, 0x409c24, 0x000f0000); |
| 404 | nv_wr32(dev, 0x404000, 0xc0000000); /* DISPATCH */ |
| 405 | nv_wr32(dev, 0x404600, 0xc0000000); /* M2MF */ |
| 406 | nv_wr32(dev, 0x408030, 0xc0000000); |
| 407 | nv_wr32(dev, 0x40601c, 0xc0000000); |
| 408 | nv_wr32(dev, 0x404490, 0xc0000000); /* MACRO */ |
| 409 | nv_wr32(dev, 0x406018, 0xc0000000); |
| 410 | nv_wr32(dev, 0x405840, 0xc0000000); |
| 411 | nv_wr32(dev, 0x405844, 0x00ffffff); |
| 412 | nv_mask(dev, 0x419cc0, 0x00000008, 0x00000008); |
| 413 | nv_mask(dev, 0x419eb4, 0x00001000, 0x00001000); |
| 414 | } |
| 415 | |
| 416 | static void |
| 417 | nvc0_graph_init_gpc_1(struct drm_device *dev) |
| 418 | { |
Ben Skeggs | 7a45cd1 | 2011-04-01 10:59:53 +1000 | [diff] [blame] | 419 | struct nvc0_graph_priv *priv = nv_engine(dev, NVOBJ_ENGINE_GR); |
Ben Skeggs | 966a5b7 | 2010-11-24 10:49:02 +1000 | [diff] [blame] | 420 | int gpc, tp; |
| 421 | |
| 422 | for (gpc = 0; gpc < priv->gpc_nr; gpc++) { |
| 423 | nv_wr32(dev, GPC_UNIT(gpc, 0x0420), 0xc0000000); |
| 424 | nv_wr32(dev, GPC_UNIT(gpc, 0x0900), 0xc0000000); |
| 425 | nv_wr32(dev, GPC_UNIT(gpc, 0x1028), 0xc0000000); |
| 426 | nv_wr32(dev, GPC_UNIT(gpc, 0x0824), 0xc0000000); |
| 427 | for (tp = 0; tp < priv->tp_nr[gpc]; tp++) { |
| 428 | nv_wr32(dev, TP_UNIT(gpc, tp, 0x508), 0xffffffff); |
| 429 | nv_wr32(dev, TP_UNIT(gpc, tp, 0x50c), 0xffffffff); |
| 430 | nv_wr32(dev, TP_UNIT(gpc, tp, 0x224), 0xc0000000); |
| 431 | nv_wr32(dev, TP_UNIT(gpc, tp, 0x48c), 0xc0000000); |
| 432 | nv_wr32(dev, TP_UNIT(gpc, tp, 0x084), 0xc0000000); |
Ben Skeggs | 0f1cb20 | 2011-01-21 11:15:16 +1000 | [diff] [blame] | 433 | nv_wr32(dev, TP_UNIT(gpc, tp, 0x644), 0x001ffffe); |
| 434 | nv_wr32(dev, TP_UNIT(gpc, tp, 0x64c), 0x0000000f); |
Ben Skeggs | 966a5b7 | 2010-11-24 10:49:02 +1000 | [diff] [blame] | 435 | } |
| 436 | nv_wr32(dev, GPC_UNIT(gpc, 0x2c90), 0xffffffff); |
| 437 | nv_wr32(dev, GPC_UNIT(gpc, 0x2c94), 0xffffffff); |
| 438 | } |
| 439 | } |
| 440 | |
| 441 | static void |
| 442 | nvc0_graph_init_rop(struct drm_device *dev) |
| 443 | { |
Ben Skeggs | 7a45cd1 | 2011-04-01 10:59:53 +1000 | [diff] [blame] | 444 | struct nvc0_graph_priv *priv = nv_engine(dev, NVOBJ_ENGINE_GR); |
Ben Skeggs | 966a5b7 | 2010-11-24 10:49:02 +1000 | [diff] [blame] | 445 | int rop; |
| 446 | |
| 447 | for (rop = 0; rop < priv->rop_nr; rop++) { |
| 448 | nv_wr32(dev, ROP_UNIT(rop, 0x144), 0xc0000000); |
| 449 | nv_wr32(dev, ROP_UNIT(rop, 0x070), 0xc0000000); |
| 450 | nv_wr32(dev, ROP_UNIT(rop, 0x204), 0xffffffff); |
| 451 | nv_wr32(dev, ROP_UNIT(rop, 0x208), 0xffffffff); |
| 452 | } |
| 453 | } |
| 454 | |
Ben Skeggs | fe79911 | 2011-04-12 18:50:36 +1000 | [diff] [blame] | 455 | static void |
| 456 | nvc0_graph_init_fuc(struct drm_device *dev, u32 fuc_base, |
| 457 | struct nvc0_graph_fuc *code, struct nvc0_graph_fuc *data) |
Ben Skeggs | 966a5b7 | 2010-11-24 10:49:02 +1000 | [diff] [blame] | 458 | { |
Ben Skeggs | fe79911 | 2011-04-12 18:50:36 +1000 | [diff] [blame] | 459 | int i; |
Ben Skeggs | 966a5b7 | 2010-11-24 10:49:02 +1000 | [diff] [blame] | 460 | |
| 461 | nv_wr32(dev, fuc_base + 0x01c0, 0x01000000); |
Ben Skeggs | fe79911 | 2011-04-12 18:50:36 +1000 | [diff] [blame] | 462 | for (i = 0; i < data->size / 4; i++) |
| 463 | nv_wr32(dev, fuc_base + 0x01c4, data->data[i]); |
Ben Skeggs | 966a5b7 | 2010-11-24 10:49:02 +1000 | [diff] [blame] | 464 | |
| 465 | nv_wr32(dev, fuc_base + 0x0180, 0x01000000); |
Ben Skeggs | fe79911 | 2011-04-12 18:50:36 +1000 | [diff] [blame] | 466 | for (i = 0; i < code->size / 4; i++) { |
Ben Skeggs | 966a5b7 | 2010-11-24 10:49:02 +1000 | [diff] [blame] | 467 | if ((i & 0x3f) == 0) |
| 468 | nv_wr32(dev, fuc_base + 0x0188, i >> 6); |
Ben Skeggs | fe79911 | 2011-04-12 18:50:36 +1000 | [diff] [blame] | 469 | nv_wr32(dev, fuc_base + 0x0184, code->data[i]); |
Ben Skeggs | 966a5b7 | 2010-11-24 10:49:02 +1000 | [diff] [blame] | 470 | } |
Ben Skeggs | 966a5b7 | 2010-11-24 10:49:02 +1000 | [diff] [blame] | 471 | } |
| 472 | |
| 473 | static int |
| 474 | nvc0_graph_init_ctxctl(struct drm_device *dev) |
| 475 | { |
Ben Skeggs | 0411de8 | 2011-05-25 18:32:44 +1000 | [diff] [blame] | 476 | struct drm_nouveau_private *dev_priv = dev->dev_private; |
Ben Skeggs | 7a45cd1 | 2011-04-01 10:59:53 +1000 | [diff] [blame] | 477 | struct nvc0_graph_priv *priv = nv_engine(dev, NVOBJ_ENGINE_GR); |
Ben Skeggs | 966a5b7 | 2010-11-24 10:49:02 +1000 | [diff] [blame] | 478 | u32 r000260; |
Ben Skeggs | 0411de8 | 2011-05-25 18:32:44 +1000 | [diff] [blame] | 479 | int i; |
| 480 | |
| 481 | if (!nouveau_ctxfw) { |
| 482 | /* load HUB microcode */ |
| 483 | r000260 = nv_mask(dev, 0x000260, 0x00000001, 0x00000000); |
| 484 | nv_wr32(dev, 0x4091c0, 0x01000000); |
| 485 | for (i = 0; i < sizeof(nvc0_grhub_data) / 4; i++) |
| 486 | nv_wr32(dev, 0x4091c4, nvc0_grhub_data[i]); |
| 487 | |
| 488 | nv_wr32(dev, 0x409180, 0x01000000); |
| 489 | for (i = 0; i < sizeof(nvc0_grhub_code) / 4; i++) { |
| 490 | if ((i & 0x3f) == 0) |
| 491 | nv_wr32(dev, 0x409188, i >> 6); |
| 492 | nv_wr32(dev, 0x409184, nvc0_grhub_code[i]); |
| 493 | } |
| 494 | |
| 495 | /* load GPC microcode */ |
| 496 | nv_wr32(dev, 0x41a1c0, 0x01000000); |
| 497 | for (i = 0; i < sizeof(nvc0_grgpc_data) / 4; i++) |
| 498 | nv_wr32(dev, 0x41a1c4, nvc0_grgpc_data[i]); |
| 499 | |
| 500 | nv_wr32(dev, 0x41a180, 0x01000000); |
| 501 | for (i = 0; i < sizeof(nvc0_grgpc_code) / 4; i++) { |
| 502 | if ((i & 0x3f) == 0) |
| 503 | nv_wr32(dev, 0x41a188, i >> 6); |
| 504 | nv_wr32(dev, 0x41a184, nvc0_grgpc_code[i]); |
| 505 | } |
| 506 | nv_wr32(dev, 0x000260, r000260); |
| 507 | |
| 508 | /* start HUB ucode running, it'll init the GPCs */ |
| 509 | nv_wr32(dev, 0x409800, dev_priv->chipset); |
| 510 | nv_wr32(dev, 0x40910c, 0x00000000); |
| 511 | nv_wr32(dev, 0x409100, 0x00000002); |
| 512 | if (!nv_wait(dev, 0x409800, 0x80000000, 0x80000000)) { |
| 513 | NV_ERROR(dev, "PGRAPH: HUB_INIT timed out\n"); |
| 514 | nvc0_graph_ctxctl_debug(dev); |
| 515 | return -EBUSY; |
| 516 | } |
| 517 | |
| 518 | priv->grctx_size = nv_rd32(dev, 0x409804); |
| 519 | return 0; |
| 520 | } |
Ben Skeggs | 966a5b7 | 2010-11-24 10:49:02 +1000 | [diff] [blame] | 521 | |
| 522 | /* load fuc microcode */ |
| 523 | r000260 = nv_mask(dev, 0x000260, 0x00000001, 0x00000000); |
Ben Skeggs | fe79911 | 2011-04-12 18:50:36 +1000 | [diff] [blame] | 524 | nvc0_graph_init_fuc(dev, 0x409000, &priv->fuc409c, &priv->fuc409d); |
| 525 | nvc0_graph_init_fuc(dev, 0x41a000, &priv->fuc41ac, &priv->fuc41ad); |
Ben Skeggs | 966a5b7 | 2010-11-24 10:49:02 +1000 | [diff] [blame] | 526 | nv_wr32(dev, 0x000260, r000260); |
| 527 | |
Ben Skeggs | 966a5b7 | 2010-11-24 10:49:02 +1000 | [diff] [blame] | 528 | /* start both of them running */ |
| 529 | nv_wr32(dev, 0x409840, 0xffffffff); |
| 530 | nv_wr32(dev, 0x41a10c, 0x00000000); |
| 531 | nv_wr32(dev, 0x40910c, 0x00000000); |
| 532 | nv_wr32(dev, 0x41a100, 0x00000002); |
| 533 | nv_wr32(dev, 0x409100, 0x00000002); |
| 534 | if (!nv_wait(dev, 0x409800, 0x00000001, 0x00000001)) |
| 535 | NV_INFO(dev, "0x409800 wait failed\n"); |
| 536 | |
| 537 | nv_wr32(dev, 0x409840, 0xffffffff); |
| 538 | nv_wr32(dev, 0x409500, 0x7fffffff); |
| 539 | nv_wr32(dev, 0x409504, 0x00000021); |
| 540 | |
| 541 | nv_wr32(dev, 0x409840, 0xffffffff); |
| 542 | nv_wr32(dev, 0x409500, 0x00000000); |
| 543 | nv_wr32(dev, 0x409504, 0x00000010); |
| 544 | if (!nv_wait_ne(dev, 0x409800, 0xffffffff, 0x00000000)) { |
| 545 | NV_ERROR(dev, "fuc09 req 0x10 timeout\n"); |
| 546 | return -EBUSY; |
| 547 | } |
| 548 | priv->grctx_size = nv_rd32(dev, 0x409800); |
| 549 | |
| 550 | nv_wr32(dev, 0x409840, 0xffffffff); |
| 551 | nv_wr32(dev, 0x409500, 0x00000000); |
| 552 | nv_wr32(dev, 0x409504, 0x00000016); |
| 553 | if (!nv_wait_ne(dev, 0x409800, 0xffffffff, 0x00000000)) { |
| 554 | NV_ERROR(dev, "fuc09 req 0x16 timeout\n"); |
| 555 | return -EBUSY; |
| 556 | } |
| 557 | |
| 558 | nv_wr32(dev, 0x409840, 0xffffffff); |
| 559 | nv_wr32(dev, 0x409500, 0x00000000); |
| 560 | nv_wr32(dev, 0x409504, 0x00000025); |
| 561 | if (!nv_wait_ne(dev, 0x409800, 0xffffffff, 0x00000000)) { |
| 562 | NV_ERROR(dev, "fuc09 req 0x25 timeout\n"); |
| 563 | return -EBUSY; |
| 564 | } |
| 565 | |
| 566 | return 0; |
Ben Skeggs | 4b223ee | 2010-08-03 10:00:56 +1000 | [diff] [blame] | 567 | } |
| 568 | |
Ben Skeggs | 7a45cd1 | 2011-04-01 10:59:53 +1000 | [diff] [blame] | 569 | static int |
| 570 | nvc0_graph_init(struct drm_device *dev, int engine) |
Ben Skeggs | 4b223ee | 2010-08-03 10:00:56 +1000 | [diff] [blame] | 571 | { |
Ben Skeggs | 966a5b7 | 2010-11-24 10:49:02 +1000 | [diff] [blame] | 572 | int ret; |
| 573 | |
Ben Skeggs | 966a5b7 | 2010-11-24 10:49:02 +1000 | [diff] [blame] | 574 | nv_mask(dev, 0x000200, 0x18001000, 0x00000000); |
| 575 | nv_mask(dev, 0x000200, 0x18001000, 0x18001000); |
| 576 | |
Ben Skeggs | 966a5b7 | 2010-11-24 10:49:02 +1000 | [diff] [blame] | 577 | nvc0_graph_init_obj418880(dev); |
| 578 | nvc0_graph_init_regs(dev); |
Emil Velikov | f212949 | 2011-03-19 23:31:52 +0000 | [diff] [blame] | 579 | /*nvc0_graph_init_unitplemented_magics(dev);*/ |
Ben Skeggs | 966a5b7 | 2010-11-24 10:49:02 +1000 | [diff] [blame] | 580 | nvc0_graph_init_gpc_0(dev); |
Emil Velikov | f212949 | 2011-03-19 23:31:52 +0000 | [diff] [blame] | 581 | /*nvc0_graph_init_unitplemented_c242(dev);*/ |
Ben Skeggs | 966a5b7 | 2010-11-24 10:49:02 +1000 | [diff] [blame] | 582 | |
| 583 | nv_wr32(dev, 0x400500, 0x00010001); |
| 584 | nv_wr32(dev, 0x400100, 0xffffffff); |
| 585 | nv_wr32(dev, 0x40013c, 0xffffffff); |
| 586 | |
| 587 | nvc0_graph_init_units(dev); |
| 588 | nvc0_graph_init_gpc_1(dev); |
| 589 | nvc0_graph_init_rop(dev); |
| 590 | |
| 591 | nv_wr32(dev, 0x400108, 0xffffffff); |
| 592 | nv_wr32(dev, 0x400138, 0xffffffff); |
| 593 | nv_wr32(dev, 0x400118, 0xffffffff); |
| 594 | nv_wr32(dev, 0x400130, 0xffffffff); |
| 595 | nv_wr32(dev, 0x40011c, 0xffffffff); |
| 596 | nv_wr32(dev, 0x400134, 0xffffffff); |
| 597 | nv_wr32(dev, 0x400054, 0x34ce3464); |
| 598 | |
| 599 | ret = nvc0_graph_init_ctxctl(dev); |
Ben Skeggs | a82dd49 | 2011-04-01 13:56:05 +1000 | [diff] [blame] | 600 | if (ret) |
| 601 | return ret; |
| 602 | |
Ben Skeggs | 4b223ee | 2010-08-03 10:00:56 +1000 | [diff] [blame] | 603 | return 0; |
| 604 | } |
| 605 | |
Ben Skeggs | d5a2737 | 2011-04-01 16:10:08 +1000 | [diff] [blame] | 606 | int |
Ben Skeggs | 966a5b7 | 2010-11-24 10:49:02 +1000 | [diff] [blame] | 607 | nvc0_graph_isr_chid(struct drm_device *dev, u64 inst) |
| 608 | { |
| 609 | struct drm_nouveau_private *dev_priv = dev->dev_private; |
| 610 | struct nouveau_channel *chan; |
| 611 | unsigned long flags; |
| 612 | int i; |
| 613 | |
| 614 | spin_lock_irqsave(&dev_priv->channels.lock, flags); |
| 615 | for (i = 0; i < dev_priv->engine.fifo.channels; i++) { |
| 616 | chan = dev_priv->channels.ptr[i]; |
| 617 | if (!chan || !chan->ramin) |
| 618 | continue; |
| 619 | |
| 620 | if (inst == chan->ramin->vinst) |
| 621 | break; |
| 622 | } |
| 623 | spin_unlock_irqrestore(&dev_priv->channels.lock, flags); |
| 624 | return i; |
| 625 | } |
| 626 | |
| 627 | static void |
Ben Skeggs | 0411de8 | 2011-05-25 18:32:44 +1000 | [diff] [blame] | 628 | nvc0_graph_ctxctl_isr(struct drm_device *dev) |
| 629 | { |
| 630 | u32 ustat = nv_rd32(dev, 0x409c18); |
| 631 | |
| 632 | if (ustat & 0x00000001) |
| 633 | NV_INFO(dev, "PGRAPH: CTXCTRL ucode error\n"); |
| 634 | if (ustat & 0x00080000) |
| 635 | NV_INFO(dev, "PGRAPH: CTXCTRL watchdog timeout\n"); |
| 636 | if (ustat & ~0x00080001) |
| 637 | NV_INFO(dev, "PGRAPH: CTXCTRL 0x%08x\n", ustat); |
| 638 | |
| 639 | nvc0_graph_ctxctl_debug(dev); |
| 640 | nv_wr32(dev, 0x409c20, ustat); |
| 641 | } |
| 642 | |
| 643 | static void |
Ben Skeggs | 966a5b7 | 2010-11-24 10:49:02 +1000 | [diff] [blame] | 644 | nvc0_graph_isr(struct drm_device *dev) |
| 645 | { |
| 646 | u64 inst = (u64)(nv_rd32(dev, 0x409b00) & 0x0fffffff) << 12; |
| 647 | u32 chid = nvc0_graph_isr_chid(dev, inst); |
| 648 | u32 stat = nv_rd32(dev, 0x400100); |
| 649 | u32 addr = nv_rd32(dev, 0x400704); |
| 650 | u32 mthd = (addr & 0x00003ffc); |
| 651 | u32 subc = (addr & 0x00070000) >> 16; |
| 652 | u32 data = nv_rd32(dev, 0x400708); |
| 653 | u32 code = nv_rd32(dev, 0x400110); |
| 654 | u32 class = nv_rd32(dev, 0x404200 + (subc * 4)); |
| 655 | |
| 656 | if (stat & 0x00000010) { |
Ben Skeggs | bd2f203 | 2011-02-08 15:16:23 +1000 | [diff] [blame] | 657 | if (nouveau_gpuobj_mthd_call2(dev, chid, class, mthd, data)) { |
| 658 | NV_INFO(dev, "PGRAPH: ILLEGAL_MTHD ch %d [0x%010llx] " |
| 659 | "subc %d class 0x%04x mthd 0x%04x " |
| 660 | "data 0x%08x\n", |
| 661 | chid, inst, subc, class, mthd, data); |
| 662 | } |
Ben Skeggs | 966a5b7 | 2010-11-24 10:49:02 +1000 | [diff] [blame] | 663 | nv_wr32(dev, 0x400100, 0x00000010); |
| 664 | stat &= ~0x00000010; |
| 665 | } |
| 666 | |
Ben Skeggs | eae5e7f | 2010-12-30 11:40:07 +1000 | [diff] [blame] | 667 | if (stat & 0x00000020) { |
| 668 | NV_INFO(dev, "PGRAPH: ILLEGAL_CLASS ch %d [0x%010llx] subc %d " |
| 669 | "class 0x%04x mthd 0x%04x data 0x%08x\n", |
| 670 | chid, inst, subc, class, mthd, data); |
| 671 | nv_wr32(dev, 0x400100, 0x00000020); |
| 672 | stat &= ~0x00000020; |
| 673 | } |
| 674 | |
Ben Skeggs | 966a5b7 | 2010-11-24 10:49:02 +1000 | [diff] [blame] | 675 | if (stat & 0x00100000) { |
| 676 | NV_INFO(dev, "PGRAPH: DATA_ERROR ["); |
Ben Skeggs | 6effe39 | 2010-12-30 11:48:03 +1000 | [diff] [blame] | 677 | nouveau_enum_print(nv50_data_error_names, code); |
Ben Skeggs | 966a5b7 | 2010-11-24 10:49:02 +1000 | [diff] [blame] | 678 | printk("] ch %d [0x%010llx] subc %d class 0x%04x " |
| 679 | "mthd 0x%04x data 0x%08x\n", |
| 680 | chid, inst, subc, class, mthd, data); |
| 681 | nv_wr32(dev, 0x400100, 0x00100000); |
| 682 | stat &= ~0x00100000; |
| 683 | } |
| 684 | |
Ben Skeggs | eae5e7f | 2010-12-30 11:40:07 +1000 | [diff] [blame] | 685 | if (stat & 0x00200000) { |
| 686 | u32 trap = nv_rd32(dev, 0x400108); |
| 687 | NV_INFO(dev, "PGRAPH: TRAP ch %d status 0x%08x\n", chid, trap); |
| 688 | nv_wr32(dev, 0x400108, trap); |
| 689 | nv_wr32(dev, 0x400100, 0x00200000); |
| 690 | stat &= ~0x00200000; |
| 691 | } |
| 692 | |
Ben Skeggs | 966a5b7 | 2010-11-24 10:49:02 +1000 | [diff] [blame] | 693 | if (stat & 0x00080000) { |
Ben Skeggs | 0411de8 | 2011-05-25 18:32:44 +1000 | [diff] [blame] | 694 | nvc0_graph_ctxctl_isr(dev); |
Ben Skeggs | 966a5b7 | 2010-11-24 10:49:02 +1000 | [diff] [blame] | 695 | nv_wr32(dev, 0x400100, 0x00080000); |
| 696 | stat &= ~0x00080000; |
| 697 | } |
| 698 | |
| 699 | if (stat) { |
| 700 | NV_INFO(dev, "PGRAPH: unknown stat 0x%08x\n", stat); |
| 701 | nv_wr32(dev, 0x400100, stat); |
| 702 | } |
| 703 | |
| 704 | nv_wr32(dev, 0x400500, 0x00010001); |
| 705 | } |
Ben Skeggs | 51f73d6 | 2011-01-21 13:53:21 +1000 | [diff] [blame] | 706 | |
| 707 | static void |
| 708 | nvc0_runk140_isr(struct drm_device *dev) |
| 709 | { |
| 710 | u32 units = nv_rd32(dev, 0x00017c) & 0x1f; |
| 711 | |
| 712 | while (units) { |
| 713 | u32 unit = ffs(units) - 1; |
| 714 | u32 reg = 0x140000 + unit * 0x2000; |
| 715 | u32 st0 = nv_mask(dev, reg + 0x1020, 0, 0); |
| 716 | u32 st1 = nv_mask(dev, reg + 0x1420, 0, 0); |
| 717 | |
| 718 | NV_INFO(dev, "PRUNK140: %d 0x%08x 0x%08x\n", unit, st0, st1); |
| 719 | units &= ~(1 << unit); |
| 720 | } |
| 721 | } |
Ben Skeggs | 7a45cd1 | 2011-04-01 10:59:53 +1000 | [diff] [blame] | 722 | |
Ben Skeggs | fe79911 | 2011-04-12 18:50:36 +1000 | [diff] [blame] | 723 | static int |
| 724 | nvc0_graph_create_fw(struct drm_device *dev, const char *fwname, |
| 725 | struct nvc0_graph_fuc *fuc) |
| 726 | { |
| 727 | struct drm_nouveau_private *dev_priv = dev->dev_private; |
| 728 | const struct firmware *fw; |
| 729 | char f[32]; |
| 730 | int ret; |
| 731 | |
| 732 | snprintf(f, sizeof(f), "nouveau/nv%02x_%s", dev_priv->chipset, fwname); |
| 733 | ret = request_firmware(&fw, f, &dev->pdev->dev); |
| 734 | if (ret) { |
| 735 | snprintf(f, sizeof(f), "nouveau/%s", fwname); |
| 736 | ret = request_firmware(&fw, f, &dev->pdev->dev); |
| 737 | if (ret) { |
| 738 | NV_ERROR(dev, "failed to load %s\n", fwname); |
| 739 | return ret; |
| 740 | } |
| 741 | } |
| 742 | |
| 743 | fuc->size = fw->size; |
| 744 | fuc->data = kmemdup(fw->data, fuc->size, GFP_KERNEL); |
| 745 | release_firmware(fw); |
| 746 | return (fuc->data != NULL) ? 0 : -ENOMEM; |
| 747 | } |
| 748 | |
| 749 | static void |
| 750 | nvc0_graph_destroy_fw(struct nvc0_graph_fuc *fuc) |
| 751 | { |
| 752 | if (fuc->data) { |
| 753 | kfree(fuc->data); |
| 754 | fuc->data = NULL; |
| 755 | } |
| 756 | } |
| 757 | |
Ben Skeggs | 7a45cd1 | 2011-04-01 10:59:53 +1000 | [diff] [blame] | 758 | static void |
| 759 | nvc0_graph_destroy(struct drm_device *dev, int engine) |
| 760 | { |
| 761 | struct nvc0_graph_priv *priv = nv_engine(dev, engine); |
| 762 | |
Ben Skeggs | 0411de8 | 2011-05-25 18:32:44 +1000 | [diff] [blame] | 763 | if (nouveau_ctxfw) { |
| 764 | nvc0_graph_destroy_fw(&priv->fuc409c); |
| 765 | nvc0_graph_destroy_fw(&priv->fuc409d); |
| 766 | nvc0_graph_destroy_fw(&priv->fuc41ac); |
| 767 | nvc0_graph_destroy_fw(&priv->fuc41ad); |
| 768 | } |
Ben Skeggs | fe79911 | 2011-04-12 18:50:36 +1000 | [diff] [blame] | 769 | |
Ben Skeggs | 7a45cd1 | 2011-04-01 10:59:53 +1000 | [diff] [blame] | 770 | nouveau_irq_unregister(dev, 12); |
| 771 | nouveau_irq_unregister(dev, 25); |
| 772 | |
| 773 | nouveau_gpuobj_ref(NULL, &priv->unk4188b8); |
| 774 | nouveau_gpuobj_ref(NULL, &priv->unk4188b4); |
| 775 | |
| 776 | if (priv->grctx_vals) |
| 777 | kfree(priv->grctx_vals); |
| 778 | |
| 779 | NVOBJ_ENGINE_DEL(dev, GR); |
| 780 | kfree(priv); |
| 781 | } |
| 782 | |
| 783 | int |
| 784 | nvc0_graph_create(struct drm_device *dev) |
| 785 | { |
| 786 | struct drm_nouveau_private *dev_priv = dev->dev_private; |
| 787 | struct nvc0_graph_priv *priv; |
| 788 | int ret, gpc, i; |
Ben Skeggs | 847adea | 2011-05-24 14:37:41 +1000 | [diff] [blame] | 789 | u32 fermi; |
Ben Skeggs | 7a45cd1 | 2011-04-01 10:59:53 +1000 | [diff] [blame] | 790 | |
Ben Skeggs | 847adea | 2011-05-24 14:37:41 +1000 | [diff] [blame] | 791 | fermi = nvc0_graph_class(dev); |
| 792 | if (!fermi) { |
Ben Skeggs | a82dd49 | 2011-04-01 13:56:05 +1000 | [diff] [blame] | 793 | NV_ERROR(dev, "PGRAPH: unsupported chipset, please report!\n"); |
| 794 | return 0; |
| 795 | } |
| 796 | |
Ben Skeggs | 7a45cd1 | 2011-04-01 10:59:53 +1000 | [diff] [blame] | 797 | priv = kzalloc(sizeof(*priv), GFP_KERNEL); |
| 798 | if (!priv) |
| 799 | return -ENOMEM; |
| 800 | |
| 801 | priv->base.destroy = nvc0_graph_destroy; |
| 802 | priv->base.init = nvc0_graph_init; |
| 803 | priv->base.fini = nvc0_graph_fini; |
| 804 | priv->base.context_new = nvc0_graph_context_new; |
| 805 | priv->base.context_del = nvc0_graph_context_del; |
| 806 | priv->base.object_new = nvc0_graph_object_new; |
| 807 | |
| 808 | NVOBJ_ENGINE_ADD(dev, GR, &priv->base); |
| 809 | nouveau_irq_register(dev, 12, nvc0_graph_isr); |
| 810 | nouveau_irq_register(dev, 25, nvc0_runk140_isr); |
| 811 | |
Ben Skeggs | 0411de8 | 2011-05-25 18:32:44 +1000 | [diff] [blame] | 812 | if (nouveau_ctxfw) { |
| 813 | NV_INFO(dev, "PGRAPH: using external firmware\n"); |
| 814 | if (nvc0_graph_create_fw(dev, "fuc409c", &priv->fuc409c) || |
| 815 | nvc0_graph_create_fw(dev, "fuc409d", &priv->fuc409d) || |
| 816 | nvc0_graph_create_fw(dev, "fuc41ac", &priv->fuc41ac) || |
| 817 | nvc0_graph_create_fw(dev, "fuc41ad", &priv->fuc41ad)) { |
| 818 | ret = 0; |
| 819 | goto error; |
| 820 | } |
Ben Skeggs | fe79911 | 2011-04-12 18:50:36 +1000 | [diff] [blame] | 821 | } |
| 822 | |
Ben Skeggs | 7a45cd1 | 2011-04-01 10:59:53 +1000 | [diff] [blame] | 823 | ret = nouveau_gpuobj_new(dev, NULL, 0x1000, 256, 0, &priv->unk4188b4); |
| 824 | if (ret) |
| 825 | goto error; |
| 826 | |
| 827 | ret = nouveau_gpuobj_new(dev, NULL, 0x1000, 256, 0, &priv->unk4188b8); |
| 828 | if (ret) |
| 829 | goto error; |
| 830 | |
| 831 | for (i = 0; i < 0x1000; i += 4) { |
| 832 | nv_wo32(priv->unk4188b4, i, 0x00000010); |
| 833 | nv_wo32(priv->unk4188b8, i, 0x00000010); |
| 834 | } |
| 835 | |
| 836 | priv->gpc_nr = nv_rd32(dev, 0x409604) & 0x0000001f; |
| 837 | priv->rop_nr = (nv_rd32(dev, 0x409604) & 0x001f0000) >> 16; |
| 838 | for (gpc = 0; gpc < priv->gpc_nr; gpc++) { |
| 839 | priv->tp_nr[gpc] = nv_rd32(dev, GPC_UNIT(gpc, 0x2608)); |
| 840 | priv->tp_total += priv->tp_nr[gpc]; |
| 841 | } |
| 842 | |
| 843 | /*XXX: these need figuring out... */ |
| 844 | switch (dev_priv->chipset) { |
| 845 | case 0xc0: |
| 846 | if (priv->tp_total == 11) { /* 465, 3/4/4/0, 4 */ |
| 847 | priv->magic_not_rop_nr = 0x07; |
| 848 | /* filled values up to tp_total, the rest 0 */ |
Ben Skeggs | 7a45cd1 | 2011-04-01 10:59:53 +1000 | [diff] [blame] | 849 | priv->magicgpc918 = 0x000ba2e9; |
| 850 | } else |
| 851 | if (priv->tp_total == 14) { /* 470, 3/3/4/4, 5 */ |
| 852 | priv->magic_not_rop_nr = 0x05; |
Ben Skeggs | 7a45cd1 | 2011-04-01 10:59:53 +1000 | [diff] [blame] | 853 | priv->magicgpc918 = 0x00092493; |
| 854 | } else |
| 855 | if (priv->tp_total == 15) { /* 480, 3/4/4/4, 6 */ |
| 856 | priv->magic_not_rop_nr = 0x06; |
Ben Skeggs | 7a45cd1 | 2011-04-01 10:59:53 +1000 | [diff] [blame] | 857 | priv->magicgpc918 = 0x00088889; |
| 858 | } |
| 859 | break; |
| 860 | case 0xc3: /* 450, 4/0/0/0, 2 */ |
| 861 | priv->magic_not_rop_nr = 0x03; |
Ben Skeggs | 7a45cd1 | 2011-04-01 10:59:53 +1000 | [diff] [blame] | 862 | priv->magicgpc918 = 0x00200000; |
| 863 | break; |
| 864 | case 0xc4: /* 460, 3/4/0/0, 4 */ |
| 865 | priv->magic_not_rop_nr = 0x01; |
Ben Skeggs | 7a45cd1 | 2011-04-01 10:59:53 +1000 | [diff] [blame] | 866 | priv->magicgpc918 = 0x00124925; |
| 867 | break; |
Ben Skeggs | a219997 | 2011-05-26 10:54:05 +1000 | [diff] [blame^] | 868 | case 0xc1: /* 2/0/0/0, 1 */ |
| 869 | priv->magic_not_rop_nr = 0x01; |
| 870 | priv->magicgpc918 = 0x00400000; |
| 871 | break; |
| 872 | case 0xc8: /* 4/4/3/4, 5 */ |
| 873 | priv->magic_not_rop_nr = 0x06; |
| 874 | priv->magicgpc918 = 0x00088889; |
| 875 | break; |
| 876 | case 0xce: /* 4/4/0/0, 4 */ |
| 877 | priv->magic_not_rop_nr = 0x03; |
| 878 | priv->magicgpc918 = 0x00100000; |
| 879 | break; |
Ben Skeggs | 7a45cd1 | 2011-04-01 10:59:53 +1000 | [diff] [blame] | 880 | } |
| 881 | |
| 882 | if (!priv->magic_not_rop_nr) { |
| 883 | NV_ERROR(dev, "PGRAPH: unknown config: %d/%d/%d/%d, %d\n", |
| 884 | priv->tp_nr[0], priv->tp_nr[1], priv->tp_nr[2], |
| 885 | priv->tp_nr[3], priv->rop_nr); |
| 886 | /* use 0xc3's values... */ |
| 887 | priv->magic_not_rop_nr = 0x03; |
Ben Skeggs | 7a45cd1 | 2011-04-01 10:59:53 +1000 | [diff] [blame] | 888 | priv->magicgpc918 = 0x00200000; |
| 889 | } |
| 890 | |
| 891 | NVOBJ_CLASS(dev, 0x902d, GR); /* 2D */ |
| 892 | NVOBJ_CLASS(dev, 0x9039, GR); /* M2MF */ |
| 893 | NVOBJ_MTHD (dev, 0x9039, 0x0500, nvc0_graph_mthd_page_flip); |
| 894 | NVOBJ_CLASS(dev, 0x9097, GR); /* 3D */ |
Ben Skeggs | 847adea | 2011-05-24 14:37:41 +1000 | [diff] [blame] | 895 | if (fermi >= 0x9197) |
| 896 | NVOBJ_CLASS(dev, 0x9197, GR); /* 3D (NVC1-) */ |
| 897 | if (fermi >= 0x9297) |
| 898 | NVOBJ_CLASS(dev, 0x9297, GR); /* 3D (NVC8-) */ |
Ben Skeggs | 7a45cd1 | 2011-04-01 10:59:53 +1000 | [diff] [blame] | 899 | NVOBJ_CLASS(dev, 0x90c0, GR); /* COMPUTE */ |
| 900 | return 0; |
| 901 | |
| 902 | error: |
| 903 | nvc0_graph_destroy(dev, NVOBJ_ENGINE_GR); |
| 904 | return ret; |
| 905 | } |
Ben Skeggs | fe79911 | 2011-04-12 18:50:36 +1000 | [diff] [blame] | 906 | |
| 907 | MODULE_FIRMWARE("nouveau/nvc0_fuc409c"); |
| 908 | MODULE_FIRMWARE("nouveau/nvc0_fuc409d"); |
| 909 | MODULE_FIRMWARE("nouveau/nvc0_fuc41ac"); |
| 910 | MODULE_FIRMWARE("nouveau/nvc0_fuc41ad"); |
| 911 | MODULE_FIRMWARE("nouveau/nvc3_fuc409c"); |
| 912 | MODULE_FIRMWARE("nouveau/nvc3_fuc409d"); |
| 913 | MODULE_FIRMWARE("nouveau/nvc3_fuc41ac"); |
| 914 | MODULE_FIRMWARE("nouveau/nvc3_fuc41ad"); |
| 915 | MODULE_FIRMWARE("nouveau/nvc4_fuc409c"); |
| 916 | MODULE_FIRMWARE("nouveau/nvc4_fuc409d"); |
| 917 | MODULE_FIRMWARE("nouveau/nvc4_fuc41ac"); |
| 918 | MODULE_FIRMWARE("nouveau/nvc4_fuc41ad"); |
| 919 | MODULE_FIRMWARE("nouveau/fuc409c"); |
| 920 | MODULE_FIRMWARE("nouveau/fuc409d"); |
| 921 | MODULE_FIRMWARE("nouveau/fuc41ac"); |
| 922 | MODULE_FIRMWARE("nouveau/fuc41ad"); |