Shrenuj Bansal | a419c79 | 2016-10-20 14:05:11 -0700 | [diff] [blame] | 1 | /* Copyright (c) 2011-2017, The Linux Foundation. All rights reserved. |
| 2 | * |
| 3 | * This program is free software; you can redistribute it and/or modify |
| 4 | * it under the terms of the GNU General Public License version 2 and |
| 5 | * only version 2 as published by the Free Software Foundation. |
| 6 | * |
| 7 | * This program is distributed in the hope that it will be useful, |
| 8 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 9 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 10 | * GNU General Public License for more details. |
| 11 | * |
| 12 | */ |
| 13 | #include <linux/types.h> |
| 14 | #include <linux/delay.h> |
| 15 | #include <linux/device.h> |
| 16 | #include <linux/spinlock.h> |
| 17 | #include <linux/genalloc.h> |
| 18 | #include <linux/slab.h> |
| 19 | #include <linux/iommu.h> |
| 20 | #include <linux/msm_kgsl.h> |
| 21 | #include <linux/ratelimit.h> |
| 22 | #include <linux/of_platform.h> |
| 23 | #include <soc/qcom/scm.h> |
| 24 | #include <soc/qcom/secure_buffer.h> |
| 25 | #include <stddef.h> |
| 26 | #include <linux/compat.h> |
| 27 | |
| 28 | #include "kgsl.h" |
| 29 | #include "kgsl_device.h" |
| 30 | #include "kgsl_mmu.h" |
| 31 | #include "kgsl_sharedmem.h" |
| 32 | #include "kgsl_iommu.h" |
| 33 | #include "adreno_pm4types.h" |
| 34 | #include "adreno.h" |
| 35 | #include "kgsl_trace.h" |
| 36 | #include "kgsl_pwrctrl.h" |
| 37 | |
| 38 | #define _IOMMU_PRIV(_mmu) (&((_mmu)->priv.iommu)) |
| 39 | |
| 40 | #define ADDR_IN_GLOBAL(_a) \ |
| 41 | (((_a) >= KGSL_IOMMU_GLOBAL_MEM_BASE) && \ |
| 42 | ((_a) < (KGSL_IOMMU_GLOBAL_MEM_BASE + KGSL_IOMMU_GLOBAL_MEM_SIZE))) |
| 43 | |
Sushmita Susheelendra | 7f66cf7 | 2016-09-12 11:04:43 -0600 | [diff] [blame] | 44 | /* |
| 45 | * Flag to set SMMU memory attributes required to |
| 46 | * enable system cache for GPU transactions. |
| 47 | */ |
| 48 | #ifndef IOMMU_USE_UPSTREAM_HINT |
| 49 | #define IOMMU_USE_UPSTREAM_HINT 0 |
| 50 | #endif |
| 51 | |
Shrenuj Bansal | a419c79 | 2016-10-20 14:05:11 -0700 | [diff] [blame] | 52 | static struct kgsl_mmu_pt_ops iommu_pt_ops; |
| 53 | static bool need_iommu_sync; |
| 54 | |
| 55 | const unsigned int kgsl_iommu_reg_list[KGSL_IOMMU_REG_MAX] = { |
| 56 | 0x0,/* SCTLR */ |
| 57 | 0x20,/* TTBR0 */ |
| 58 | 0x34,/* CONTEXTIDR */ |
| 59 | 0x58,/* FSR */ |
| 60 | 0x60,/* FAR_0 */ |
| 61 | 0x618,/* TLBIALL */ |
| 62 | 0x008,/* RESUME */ |
| 63 | 0x68,/* FSYNR0 */ |
| 64 | 0x6C,/* FSYNR1 */ |
| 65 | 0x7F0,/* TLBSYNC */ |
| 66 | 0x7F4,/* TLBSTATUS */ |
| 67 | }; |
| 68 | |
| 69 | /* |
| 70 | * struct kgsl_iommu_addr_entry - entry in the kgsl_iommu_pt rbtree. |
| 71 | * @base: starting virtual address of the entry |
| 72 | * @size: size of the entry |
| 73 | * @node: the rbtree node |
| 74 | * |
| 75 | */ |
| 76 | struct kgsl_iommu_addr_entry { |
| 77 | uint64_t base; |
| 78 | uint64_t size; |
| 79 | struct rb_node node; |
| 80 | }; |
| 81 | |
| 82 | static struct kmem_cache *addr_entry_cache; |
| 83 | |
| 84 | /* |
| 85 | * There are certain memory allocations (ringbuffer, memstore, etc) that need to |
| 86 | * be present at the same address in every pagetable. We call these "global" |
| 87 | * pagetable entries. There are relatively few of these and they are mostly |
| 88 | * stable (defined at init time) but the actual number of globals can differ |
| 89 | * slight depending on the target and implementation. |
| 90 | * |
| 91 | * Here we define an array and a simple allocator to keep track of the currently |
| 92 | * active global entries. Each entry is assigned a unique address inside of a |
| 93 | * MMU implementation specific "global" region. The addresses are assigned |
| 94 | * sequentially and never re-used to avoid having to go back and reprogram |
| 95 | * existing pagetables. The entire list of active entries are mapped and |
| 96 | * unmapped into every new pagetable as it is created and destroyed. |
| 97 | * |
| 98 | * Because there are relatively few entries and they are defined at boot time we |
| 99 | * don't need to go over the top to define a dynamic allocation scheme. It will |
| 100 | * be less wasteful to pick a static number with a little bit of growth |
| 101 | * potential. |
| 102 | */ |
| 103 | |
| 104 | #define GLOBAL_PT_ENTRIES 32 |
| 105 | |
| 106 | struct global_pt_entry { |
| 107 | struct kgsl_memdesc *memdesc; |
| 108 | char name[32]; |
| 109 | }; |
| 110 | |
| 111 | static struct global_pt_entry global_pt_entries[GLOBAL_PT_ENTRIES]; |
| 112 | static struct kgsl_memdesc *kgsl_global_secure_pt_entry; |
| 113 | static int global_pt_count; |
| 114 | uint64_t global_pt_alloc; |
| 115 | static struct kgsl_memdesc gpu_qdss_desc; |
Jonathan Wicks | 4892d8d | 2017-02-24 16:21:26 -0700 | [diff] [blame] | 116 | static struct kgsl_memdesc gpu_qtimer_desc; |
Shrenuj Bansal | a419c79 | 2016-10-20 14:05:11 -0700 | [diff] [blame] | 117 | |
| 118 | void kgsl_print_global_pt_entries(struct seq_file *s) |
| 119 | { |
| 120 | int i; |
| 121 | |
| 122 | for (i = 0; i < global_pt_count; i++) { |
| 123 | struct kgsl_memdesc *memdesc = global_pt_entries[i].memdesc; |
| 124 | |
| 125 | if (memdesc == NULL) |
| 126 | continue; |
| 127 | |
| 128 | seq_printf(s, "0x%16.16llX-0x%16.16llX %16llu %s\n", |
| 129 | memdesc->gpuaddr, memdesc->gpuaddr + memdesc->size - 1, |
| 130 | memdesc->size, global_pt_entries[i].name); |
| 131 | } |
| 132 | } |
| 133 | |
| 134 | static void kgsl_iommu_unmap_globals(struct kgsl_pagetable *pagetable) |
| 135 | { |
| 136 | unsigned int i; |
| 137 | |
| 138 | for (i = 0; i < global_pt_count; i++) { |
| 139 | if (global_pt_entries[i].memdesc != NULL) |
| 140 | kgsl_mmu_unmap(pagetable, |
| 141 | global_pt_entries[i].memdesc); |
| 142 | } |
| 143 | } |
| 144 | |
| 145 | static int kgsl_iommu_map_globals(struct kgsl_pagetable *pagetable) |
| 146 | { |
| 147 | unsigned int i; |
| 148 | |
| 149 | for (i = 0; i < global_pt_count; i++) { |
| 150 | if (global_pt_entries[i].memdesc != NULL) { |
| 151 | int ret = kgsl_mmu_map(pagetable, |
| 152 | global_pt_entries[i].memdesc); |
| 153 | |
| 154 | if (ret) |
| 155 | return ret; |
| 156 | } |
| 157 | } |
| 158 | |
| 159 | return 0; |
| 160 | } |
| 161 | |
| 162 | static void kgsl_iommu_unmap_global_secure_pt_entry(struct kgsl_pagetable |
| 163 | *pagetable) |
| 164 | { |
| 165 | struct kgsl_memdesc *entry = kgsl_global_secure_pt_entry; |
| 166 | |
| 167 | if (entry != NULL) |
| 168 | kgsl_mmu_unmap(pagetable, entry); |
| 169 | |
| 170 | } |
| 171 | |
| 172 | static int kgsl_map_global_secure_pt_entry(struct kgsl_pagetable *pagetable) |
| 173 | { |
| 174 | int ret = 0; |
| 175 | struct kgsl_memdesc *entry = kgsl_global_secure_pt_entry; |
| 176 | |
| 177 | if (entry != NULL) { |
| 178 | entry->pagetable = pagetable; |
| 179 | ret = kgsl_mmu_map(pagetable, entry); |
| 180 | } |
| 181 | return ret; |
| 182 | } |
| 183 | |
| 184 | static void kgsl_iommu_remove_global(struct kgsl_mmu *mmu, |
| 185 | struct kgsl_memdesc *memdesc) |
| 186 | { |
| 187 | int i; |
| 188 | |
| 189 | if (memdesc->gpuaddr == 0 || !(memdesc->priv & KGSL_MEMDESC_GLOBAL)) |
| 190 | return; |
| 191 | |
| 192 | for (i = 0; i < global_pt_count; i++) { |
| 193 | if (global_pt_entries[i].memdesc == memdesc) { |
| 194 | memdesc->gpuaddr = 0; |
| 195 | memdesc->priv &= ~KGSL_MEMDESC_GLOBAL; |
| 196 | global_pt_entries[i].memdesc = NULL; |
| 197 | return; |
| 198 | } |
| 199 | } |
| 200 | } |
| 201 | |
| 202 | static void kgsl_iommu_add_global(struct kgsl_mmu *mmu, |
| 203 | struct kgsl_memdesc *memdesc, const char *name) |
| 204 | { |
| 205 | if (memdesc->gpuaddr != 0) |
| 206 | return; |
| 207 | |
| 208 | /*Check that we can fit the global allocations */ |
| 209 | if (WARN_ON(global_pt_count >= GLOBAL_PT_ENTRIES) || |
| 210 | WARN_ON((global_pt_alloc + memdesc->size) >= |
| 211 | KGSL_IOMMU_GLOBAL_MEM_SIZE)) |
| 212 | return; |
| 213 | |
| 214 | memdesc->gpuaddr = KGSL_IOMMU_GLOBAL_MEM_BASE + global_pt_alloc; |
| 215 | memdesc->priv |= KGSL_MEMDESC_GLOBAL; |
| 216 | global_pt_alloc += memdesc->size; |
| 217 | |
| 218 | global_pt_entries[global_pt_count].memdesc = memdesc; |
| 219 | strlcpy(global_pt_entries[global_pt_count].name, name, |
| 220 | sizeof(global_pt_entries[global_pt_count].name)); |
| 221 | global_pt_count++; |
| 222 | } |
| 223 | |
| 224 | void kgsl_add_global_secure_entry(struct kgsl_device *device, |
| 225 | struct kgsl_memdesc *memdesc) |
| 226 | { |
| 227 | memdesc->gpuaddr = KGSL_IOMMU_SECURE_BASE; |
| 228 | kgsl_global_secure_pt_entry = memdesc; |
| 229 | } |
| 230 | |
| 231 | struct kgsl_memdesc *kgsl_iommu_get_qdss_global_entry(void) |
| 232 | { |
| 233 | return &gpu_qdss_desc; |
| 234 | } |
| 235 | |
| 236 | static void kgsl_setup_qdss_desc(struct kgsl_device *device) |
| 237 | { |
| 238 | int result = 0; |
| 239 | uint32_t gpu_qdss_entry[2]; |
| 240 | |
| 241 | if (!of_find_property(device->pdev->dev.of_node, |
| 242 | "qcom,gpu-qdss-stm", NULL)) |
| 243 | return; |
| 244 | |
| 245 | if (of_property_read_u32_array(device->pdev->dev.of_node, |
| 246 | "qcom,gpu-qdss-stm", gpu_qdss_entry, 2)) { |
| 247 | KGSL_CORE_ERR("Failed to read gpu qdss dts entry\n"); |
| 248 | return; |
| 249 | } |
| 250 | |
| 251 | gpu_qdss_desc.flags = 0; |
| 252 | gpu_qdss_desc.priv = 0; |
| 253 | gpu_qdss_desc.physaddr = gpu_qdss_entry[0]; |
| 254 | gpu_qdss_desc.size = gpu_qdss_entry[1]; |
| 255 | gpu_qdss_desc.pagetable = NULL; |
| 256 | gpu_qdss_desc.ops = NULL; |
| 257 | gpu_qdss_desc.dev = device->dev->parent; |
| 258 | gpu_qdss_desc.hostptr = NULL; |
| 259 | |
| 260 | result = memdesc_sg_dma(&gpu_qdss_desc, gpu_qdss_desc.physaddr, |
| 261 | gpu_qdss_desc.size); |
| 262 | if (result) { |
| 263 | KGSL_CORE_ERR("memdesc_sg_dma failed: %d\n", result); |
| 264 | return; |
| 265 | } |
| 266 | |
| 267 | kgsl_mmu_add_global(device, &gpu_qdss_desc, "gpu-qdss"); |
| 268 | } |
| 269 | |
| 270 | static inline void kgsl_cleanup_qdss_desc(struct kgsl_mmu *mmu) |
| 271 | { |
| 272 | kgsl_iommu_remove_global(mmu, &gpu_qdss_desc); |
| 273 | kgsl_sharedmem_free(&gpu_qdss_desc); |
| 274 | } |
| 275 | |
Jonathan Wicks | 4892d8d | 2017-02-24 16:21:26 -0700 | [diff] [blame] | 276 | struct kgsl_memdesc *kgsl_iommu_get_qtimer_global_entry(void) |
| 277 | { |
| 278 | return &gpu_qtimer_desc; |
| 279 | } |
| 280 | |
| 281 | static void kgsl_setup_qtimer_desc(struct kgsl_device *device) |
| 282 | { |
| 283 | int result = 0; |
| 284 | uint32_t gpu_qtimer_entry[2]; |
| 285 | |
| 286 | if (!of_find_property(device->pdev->dev.of_node, |
| 287 | "qcom,gpu-qtimer", NULL)) |
| 288 | return; |
| 289 | |
| 290 | if (of_property_read_u32_array(device->pdev->dev.of_node, |
| 291 | "qcom,gpu-qtimer", gpu_qtimer_entry, 2)) { |
| 292 | KGSL_CORE_ERR("Failed to read gpu qtimer dts entry\n"); |
| 293 | return; |
| 294 | } |
| 295 | |
| 296 | gpu_qtimer_desc.flags = 0; |
| 297 | gpu_qtimer_desc.priv = 0; |
| 298 | gpu_qtimer_desc.physaddr = gpu_qtimer_entry[0]; |
| 299 | gpu_qtimer_desc.size = gpu_qtimer_entry[1]; |
| 300 | gpu_qtimer_desc.pagetable = NULL; |
| 301 | gpu_qtimer_desc.ops = NULL; |
| 302 | gpu_qtimer_desc.dev = device->dev->parent; |
| 303 | gpu_qtimer_desc.hostptr = NULL; |
| 304 | |
| 305 | result = memdesc_sg_dma(&gpu_qtimer_desc, gpu_qtimer_desc.physaddr, |
| 306 | gpu_qtimer_desc.size); |
| 307 | if (result) { |
| 308 | KGSL_CORE_ERR("memdesc_sg_dma failed: %d\n", result); |
| 309 | return; |
| 310 | } |
| 311 | |
| 312 | kgsl_mmu_add_global(device, &gpu_qtimer_desc, "gpu-qtimer"); |
| 313 | } |
| 314 | |
| 315 | static inline void kgsl_cleanup_qtimer_desc(struct kgsl_mmu *mmu) |
| 316 | { |
| 317 | kgsl_iommu_remove_global(mmu, &gpu_qtimer_desc); |
| 318 | kgsl_sharedmem_free(&gpu_qtimer_desc); |
| 319 | } |
Shrenuj Bansal | a419c79 | 2016-10-20 14:05:11 -0700 | [diff] [blame] | 320 | |
| 321 | static inline void _iommu_sync_mmu_pc(bool lock) |
| 322 | { |
| 323 | if (need_iommu_sync == false) |
| 324 | return; |
| 325 | |
| 326 | if (lock) |
| 327 | mutex_lock(&kgsl_mmu_sync); |
| 328 | else |
| 329 | mutex_unlock(&kgsl_mmu_sync); |
| 330 | } |
| 331 | |
| 332 | static void _detach_pt(struct kgsl_iommu_pt *iommu_pt, |
| 333 | struct kgsl_iommu_context *ctx) |
| 334 | { |
| 335 | if (iommu_pt->attached) { |
| 336 | _iommu_sync_mmu_pc(true); |
| 337 | iommu_detach_device(iommu_pt->domain, ctx->dev); |
| 338 | _iommu_sync_mmu_pc(false); |
| 339 | iommu_pt->attached = false; |
| 340 | } |
| 341 | } |
| 342 | |
| 343 | static int _attach_pt(struct kgsl_iommu_pt *iommu_pt, |
| 344 | struct kgsl_iommu_context *ctx) |
| 345 | { |
| 346 | int ret; |
| 347 | |
| 348 | if (iommu_pt->attached) |
| 349 | return 0; |
| 350 | |
| 351 | _iommu_sync_mmu_pc(true); |
| 352 | ret = iommu_attach_device(iommu_pt->domain, ctx->dev); |
| 353 | _iommu_sync_mmu_pc(false); |
| 354 | |
| 355 | if (ret == 0) |
| 356 | iommu_pt->attached = true; |
| 357 | |
| 358 | return ret; |
| 359 | } |
| 360 | |
| 361 | static int _lock_if_secure_mmu(struct kgsl_memdesc *memdesc, |
| 362 | struct kgsl_mmu *mmu) |
| 363 | { |
| 364 | struct kgsl_device *device = KGSL_MMU_DEVICE(mmu); |
| 365 | |
| 366 | if (!kgsl_memdesc_is_secured(memdesc)) |
| 367 | return 0; |
| 368 | |
| 369 | if (!kgsl_mmu_is_secured(mmu)) |
| 370 | return -EINVAL; |
| 371 | |
| 372 | mutex_lock(&device->mutex); |
| 373 | if (kgsl_active_count_get(device)) { |
| 374 | mutex_unlock(&device->mutex); |
| 375 | return -EINVAL; |
| 376 | } |
| 377 | |
| 378 | return 0; |
| 379 | } |
| 380 | |
| 381 | static void _unlock_if_secure_mmu(struct kgsl_memdesc *memdesc, |
| 382 | struct kgsl_mmu *mmu) |
| 383 | { |
| 384 | struct kgsl_device *device = KGSL_MMU_DEVICE(mmu); |
| 385 | |
| 386 | if (!kgsl_memdesc_is_secured(memdesc) || !kgsl_mmu_is_secured(mmu)) |
| 387 | return; |
| 388 | |
| 389 | kgsl_active_count_put(device); |
| 390 | mutex_unlock(&device->mutex); |
| 391 | } |
| 392 | |
| 393 | static int _iommu_map_sync_pc(struct kgsl_pagetable *pt, |
| 394 | struct kgsl_memdesc *memdesc, |
| 395 | uint64_t gpuaddr, phys_addr_t physaddr, |
| 396 | uint64_t size, unsigned int flags) |
| 397 | { |
| 398 | struct kgsl_iommu_pt *iommu_pt = pt->priv; |
| 399 | int ret; |
| 400 | |
| 401 | ret = _lock_if_secure_mmu(memdesc, pt->mmu); |
| 402 | if (ret) |
| 403 | return ret; |
| 404 | |
| 405 | _iommu_sync_mmu_pc(true); |
| 406 | |
| 407 | ret = iommu_map(iommu_pt->domain, gpuaddr, physaddr, size, flags); |
| 408 | |
| 409 | _iommu_sync_mmu_pc(false); |
| 410 | |
| 411 | _unlock_if_secure_mmu(memdesc, pt->mmu); |
| 412 | |
| 413 | if (ret) { |
| 414 | KGSL_CORE_ERR("map err: 0x%016llX, 0x%llx, 0x%x, %d\n", |
| 415 | gpuaddr, size, flags, ret); |
| 416 | return -ENODEV; |
| 417 | } |
| 418 | |
| 419 | return 0; |
| 420 | } |
| 421 | |
| 422 | static int _iommu_unmap_sync_pc(struct kgsl_pagetable *pt, |
| 423 | struct kgsl_memdesc *memdesc, uint64_t addr, uint64_t size) |
| 424 | { |
| 425 | struct kgsl_iommu_pt *iommu_pt = pt->priv; |
| 426 | size_t unmapped = 0; |
| 427 | int ret; |
| 428 | |
| 429 | ret = _lock_if_secure_mmu(memdesc, pt->mmu); |
| 430 | if (ret) |
| 431 | return ret; |
| 432 | |
| 433 | _iommu_sync_mmu_pc(true); |
| 434 | |
| 435 | unmapped = iommu_unmap(iommu_pt->domain, addr, size); |
| 436 | |
| 437 | _iommu_sync_mmu_pc(false); |
| 438 | |
| 439 | _unlock_if_secure_mmu(memdesc, pt->mmu); |
| 440 | |
| 441 | if (unmapped != size) { |
| 442 | KGSL_CORE_ERR("unmap err: 0x%016llx, 0x%llx, %zd\n", |
| 443 | addr, size, unmapped); |
| 444 | return -ENODEV; |
| 445 | } |
| 446 | |
| 447 | return 0; |
| 448 | } |
| 449 | |
| 450 | static int _iommu_map_sg_offset_sync_pc(struct kgsl_pagetable *pt, |
| 451 | uint64_t addr, struct kgsl_memdesc *memdesc, |
| 452 | struct scatterlist *sg, int nents, |
| 453 | uint64_t offset, uint64_t size, unsigned int flags) |
| 454 | { |
| 455 | struct kgsl_iommu_pt *iommu_pt = pt->priv; |
| 456 | uint64_t offset_tmp = offset; |
| 457 | uint64_t size_tmp = size; |
| 458 | size_t mapped = 0; |
| 459 | unsigned int i; |
| 460 | struct scatterlist *s; |
| 461 | phys_addr_t physaddr; |
| 462 | int ret; |
| 463 | |
| 464 | ret = _lock_if_secure_mmu(memdesc, pt->mmu); |
| 465 | if (ret) |
| 466 | return ret; |
| 467 | |
| 468 | _iommu_sync_mmu_pc(true); |
| 469 | |
| 470 | for_each_sg(sg, s, nents, i) { |
| 471 | /* Iterate until we find the offset */ |
| 472 | if (offset_tmp >= s->length) { |
| 473 | offset_tmp -= s->length; |
| 474 | continue; |
| 475 | } |
| 476 | |
| 477 | /* How much mapping is needed in this sg? */ |
| 478 | if (size < s->length - offset_tmp) |
| 479 | size_tmp = size; |
| 480 | else |
| 481 | size_tmp = s->length - offset_tmp; |
| 482 | |
| 483 | /* Get the phys addr for the offset page */ |
| 484 | if (offset_tmp != 0) { |
| 485 | physaddr = page_to_phys(nth_page(sg_page(s), |
| 486 | offset_tmp >> PAGE_SHIFT)); |
| 487 | /* Reset offset_tmp */ |
| 488 | offset_tmp = 0; |
| 489 | } else |
| 490 | physaddr = page_to_phys(sg_page(s)); |
| 491 | |
| 492 | /* Do the map for this sg */ |
| 493 | ret = iommu_map(iommu_pt->domain, addr + mapped, |
| 494 | physaddr, size_tmp, flags); |
| 495 | if (ret) |
| 496 | break; |
| 497 | |
| 498 | mapped += size_tmp; |
| 499 | size -= size_tmp; |
| 500 | |
| 501 | if (size == 0) |
| 502 | break; |
| 503 | } |
| 504 | |
| 505 | _iommu_sync_mmu_pc(false); |
| 506 | |
| 507 | _unlock_if_secure_mmu(memdesc, pt->mmu); |
| 508 | |
| 509 | if (size != 0) { |
| 510 | /* Cleanup on error */ |
| 511 | _iommu_unmap_sync_pc(pt, memdesc, addr, mapped); |
| 512 | KGSL_CORE_ERR( |
| 513 | "map sg offset err: 0x%016llX, %d, %x, %zd\n", |
| 514 | addr, nents, flags, mapped); |
| 515 | return -ENODEV; |
| 516 | } |
| 517 | |
| 518 | return 0; |
| 519 | } |
| 520 | |
| 521 | static int _iommu_map_sg_sync_pc(struct kgsl_pagetable *pt, |
| 522 | uint64_t addr, struct kgsl_memdesc *memdesc, |
| 523 | struct scatterlist *sg, int nents, |
| 524 | unsigned int flags) |
| 525 | { |
| 526 | struct kgsl_iommu_pt *iommu_pt = pt->priv; |
| 527 | size_t mapped; |
| 528 | int ret; |
| 529 | |
| 530 | ret = _lock_if_secure_mmu(memdesc, pt->mmu); |
| 531 | if (ret) |
| 532 | return ret; |
| 533 | |
| 534 | _iommu_sync_mmu_pc(true); |
| 535 | |
| 536 | mapped = iommu_map_sg(iommu_pt->domain, addr, sg, nents, flags); |
| 537 | |
| 538 | _iommu_sync_mmu_pc(false); |
| 539 | |
| 540 | _unlock_if_secure_mmu(memdesc, pt->mmu); |
| 541 | |
| 542 | if (mapped == 0) { |
| 543 | KGSL_CORE_ERR("map sg err: 0x%016llX, %d, %x, %zd\n", |
| 544 | addr, nents, flags, mapped); |
| 545 | return -ENODEV; |
| 546 | } |
| 547 | |
| 548 | return 0; |
| 549 | } |
| 550 | |
| 551 | /* |
| 552 | * One page allocation for a guard region to protect against over-zealous |
| 553 | * GPU pre-fetch |
| 554 | */ |
| 555 | |
| 556 | static struct page *kgsl_guard_page; |
| 557 | static struct kgsl_memdesc kgsl_secure_guard_page_memdesc; |
| 558 | |
| 559 | /* |
| 560 | * The dummy page is a placeholder/extra page to be used for sparse mappings. |
| 561 | * This page will be mapped to all virtual sparse bindings that are not |
| 562 | * physically backed. |
| 563 | */ |
| 564 | static struct page *kgsl_dummy_page; |
| 565 | |
| 566 | /* These functions help find the nearest allocated memory entries on either side |
| 567 | * of a faulting address. If we know the nearby allocations memory we can |
| 568 | * get a better determination of what we think should have been located in the |
| 569 | * faulting region |
| 570 | */ |
| 571 | |
| 572 | /* |
| 573 | * A local structure to make it easy to store the interesting bits for the |
| 574 | * memory entries on either side of the faulting address |
| 575 | */ |
| 576 | |
| 577 | struct _mem_entry { |
| 578 | uint64_t gpuaddr; |
| 579 | uint64_t size; |
| 580 | uint64_t flags; |
| 581 | unsigned int priv; |
| 582 | int pending_free; |
| 583 | pid_t pid; |
| 584 | char name[32]; |
| 585 | }; |
| 586 | |
| 587 | static void _get_global_entries(uint64_t faultaddr, |
| 588 | struct _mem_entry *prev, |
| 589 | struct _mem_entry *next) |
| 590 | { |
| 591 | int i; |
| 592 | uint64_t prevaddr = 0; |
| 593 | struct global_pt_entry *p = NULL; |
| 594 | |
| 595 | uint64_t nextaddr = (uint64_t) -1; |
| 596 | struct global_pt_entry *n = NULL; |
| 597 | |
| 598 | for (i = 0; i < global_pt_count; i++) { |
| 599 | uint64_t addr; |
| 600 | |
| 601 | if (global_pt_entries[i].memdesc == NULL) |
| 602 | continue; |
| 603 | |
| 604 | addr = global_pt_entries[i].memdesc->gpuaddr; |
| 605 | if ((addr < faultaddr) && (addr > prevaddr)) { |
| 606 | prevaddr = addr; |
| 607 | p = &global_pt_entries[i]; |
| 608 | } |
| 609 | |
| 610 | if ((addr > faultaddr) && (addr < nextaddr)) { |
| 611 | nextaddr = addr; |
| 612 | n = &global_pt_entries[i]; |
| 613 | } |
| 614 | } |
| 615 | |
| 616 | if (p != NULL) { |
| 617 | prev->gpuaddr = p->memdesc->gpuaddr; |
| 618 | prev->size = p->memdesc->size; |
| 619 | prev->flags = p->memdesc->flags; |
| 620 | prev->priv = p->memdesc->priv; |
| 621 | prev->pid = 0; |
| 622 | strlcpy(prev->name, p->name, sizeof(prev->name)); |
| 623 | } |
| 624 | |
| 625 | if (n != NULL) { |
| 626 | next->gpuaddr = n->memdesc->gpuaddr; |
| 627 | next->size = n->memdesc->size; |
| 628 | next->flags = n->memdesc->flags; |
| 629 | next->priv = n->memdesc->priv; |
| 630 | next->pid = 0; |
| 631 | strlcpy(next->name, n->name, sizeof(next->name)); |
| 632 | } |
| 633 | } |
| 634 | |
| 635 | void __kgsl_get_memory_usage(struct _mem_entry *entry) |
| 636 | { |
| 637 | kgsl_get_memory_usage(entry->name, sizeof(entry->name), entry->flags); |
| 638 | } |
| 639 | |
| 640 | static void _get_entries(struct kgsl_process_private *private, |
| 641 | uint64_t faultaddr, struct _mem_entry *prev, |
| 642 | struct _mem_entry *next) |
| 643 | { |
| 644 | int id; |
| 645 | struct kgsl_mem_entry *entry; |
| 646 | |
| 647 | uint64_t prevaddr = 0; |
| 648 | struct kgsl_mem_entry *p = NULL; |
| 649 | |
| 650 | uint64_t nextaddr = (uint64_t) -1; |
| 651 | struct kgsl_mem_entry *n = NULL; |
| 652 | |
| 653 | idr_for_each_entry(&private->mem_idr, entry, id) { |
| 654 | uint64_t addr = entry->memdesc.gpuaddr; |
| 655 | |
| 656 | if ((addr < faultaddr) && (addr > prevaddr)) { |
| 657 | prevaddr = addr; |
| 658 | p = entry; |
| 659 | } |
| 660 | |
| 661 | if ((addr > faultaddr) && (addr < nextaddr)) { |
| 662 | nextaddr = addr; |
| 663 | n = entry; |
| 664 | } |
| 665 | } |
| 666 | |
| 667 | if (p != NULL) { |
| 668 | prev->gpuaddr = p->memdesc.gpuaddr; |
| 669 | prev->size = p->memdesc.size; |
| 670 | prev->flags = p->memdesc.flags; |
| 671 | prev->priv = p->memdesc.priv; |
| 672 | prev->pending_free = p->pending_free; |
| 673 | prev->pid = private->pid; |
| 674 | __kgsl_get_memory_usage(prev); |
| 675 | } |
| 676 | |
| 677 | if (n != NULL) { |
| 678 | next->gpuaddr = n->memdesc.gpuaddr; |
| 679 | next->size = n->memdesc.size; |
| 680 | next->flags = n->memdesc.flags; |
| 681 | next->priv = n->memdesc.priv; |
| 682 | next->pending_free = n->pending_free; |
| 683 | next->pid = private->pid; |
| 684 | __kgsl_get_memory_usage(next); |
| 685 | } |
| 686 | } |
| 687 | |
| 688 | static void _find_mem_entries(struct kgsl_mmu *mmu, uint64_t faultaddr, |
| 689 | struct _mem_entry *preventry, struct _mem_entry *nextentry, |
| 690 | struct kgsl_context *context) |
| 691 | { |
| 692 | struct kgsl_process_private *private; |
| 693 | |
| 694 | memset(preventry, 0, sizeof(*preventry)); |
| 695 | memset(nextentry, 0, sizeof(*nextentry)); |
| 696 | |
| 697 | /* Set the maximum possible size as an initial value */ |
| 698 | nextentry->gpuaddr = (uint64_t) -1; |
| 699 | |
| 700 | if (ADDR_IN_GLOBAL(faultaddr)) { |
| 701 | _get_global_entries(faultaddr, preventry, nextentry); |
| 702 | } else if (context) { |
| 703 | private = context->proc_priv; |
| 704 | spin_lock(&private->mem_lock); |
| 705 | _get_entries(private, faultaddr, preventry, nextentry); |
| 706 | spin_unlock(&private->mem_lock); |
| 707 | } |
| 708 | } |
| 709 | |
| 710 | static void _print_entry(struct kgsl_device *device, struct _mem_entry *entry) |
| 711 | { |
| 712 | KGSL_LOG_DUMP(device, |
| 713 | "[%016llX - %016llX] %s %s (pid = %d) (%s)\n", |
| 714 | entry->gpuaddr, |
| 715 | entry->gpuaddr + entry->size, |
| 716 | entry->priv & KGSL_MEMDESC_GUARD_PAGE ? "(+guard)" : "", |
| 717 | entry->pending_free ? "(pending free)" : "", |
| 718 | entry->pid, entry->name); |
| 719 | } |
| 720 | |
| 721 | static void _check_if_freed(struct kgsl_iommu_context *ctx, |
| 722 | uint64_t addr, pid_t ptname) |
| 723 | { |
| 724 | uint64_t gpuaddr = addr; |
| 725 | uint64_t size = 0; |
| 726 | uint64_t flags = 0; |
| 727 | pid_t pid; |
| 728 | |
| 729 | char name[32]; |
| 730 | |
| 731 | memset(name, 0, sizeof(name)); |
| 732 | |
| 733 | if (kgsl_memfree_find_entry(ptname, &gpuaddr, &size, &flags, &pid)) { |
| 734 | kgsl_get_memory_usage(name, sizeof(name) - 1, flags); |
| 735 | KGSL_LOG_DUMP(ctx->kgsldev, "---- premature free ----\n"); |
| 736 | KGSL_LOG_DUMP(ctx->kgsldev, |
| 737 | "[%8.8llX-%8.8llX] (%s) was already freed by pid %d\n", |
| 738 | gpuaddr, gpuaddr + size, name, pid); |
| 739 | } |
| 740 | } |
| 741 | |
| 742 | static bool |
| 743 | kgsl_iommu_uche_overfetch(struct kgsl_process_private *private, |
| 744 | uint64_t faultaddr) |
| 745 | { |
| 746 | int id; |
| 747 | struct kgsl_mem_entry *entry = NULL; |
| 748 | |
| 749 | spin_lock(&private->mem_lock); |
| 750 | idr_for_each_entry(&private->mem_idr, entry, id) { |
| 751 | struct kgsl_memdesc *m = &entry->memdesc; |
| 752 | |
| 753 | if ((faultaddr >= (m->gpuaddr + m->size)) |
| 754 | && (faultaddr < (m->gpuaddr + m->size + 64))) { |
| 755 | spin_unlock(&private->mem_lock); |
| 756 | return true; |
| 757 | } |
| 758 | } |
| 759 | spin_unlock(&private->mem_lock); |
| 760 | return false; |
| 761 | } |
| 762 | |
| 763 | /* |
| 764 | * Read pagefaults where the faulting address lies within the first 64 bytes |
| 765 | * of a page (UCHE line size is 64 bytes) and the fault page is preceded by a |
| 766 | * valid allocation are considered likely due to UCHE overfetch and suppressed. |
| 767 | */ |
| 768 | |
| 769 | static bool kgsl_iommu_suppress_pagefault(uint64_t faultaddr, int write, |
| 770 | struct kgsl_context *context) |
| 771 | { |
| 772 | /* |
| 773 | * If there is no context associated with the pagefault then this |
| 774 | * could be a fault on a global buffer. We do not suppress faults |
| 775 | * on global buffers as they are mainly accessed by the CP bypassing |
| 776 | * the UCHE. Also, write pagefaults are never suppressed. |
| 777 | */ |
| 778 | if (!context || write) |
| 779 | return false; |
| 780 | |
| 781 | return kgsl_iommu_uche_overfetch(context->proc_priv, faultaddr); |
| 782 | } |
| 783 | |
| 784 | static int kgsl_iommu_fault_handler(struct iommu_domain *domain, |
| 785 | struct device *dev, unsigned long addr, int flags, void *token) |
| 786 | { |
| 787 | int ret = 0; |
| 788 | struct kgsl_pagetable *pt = token; |
| 789 | struct kgsl_mmu *mmu = pt->mmu; |
| 790 | struct kgsl_iommu *iommu; |
| 791 | struct kgsl_iommu_context *ctx; |
| 792 | u64 ptbase; |
| 793 | u32 contextidr; |
| 794 | pid_t tid = 0; |
| 795 | pid_t ptname; |
| 796 | struct _mem_entry prev, next; |
| 797 | int write; |
| 798 | struct kgsl_device *device; |
| 799 | struct adreno_device *adreno_dev; |
Lynus Vaz | 1fde74d | 2017-03-20 18:02:47 +0530 | [diff] [blame] | 800 | struct adreno_gpudev *gpudev; |
Shrenuj Bansal | a419c79 | 2016-10-20 14:05:11 -0700 | [diff] [blame] | 801 | unsigned int no_page_fault_log = 0; |
| 802 | unsigned int curr_context_id = 0; |
| 803 | struct kgsl_context *context; |
| 804 | char *fault_type = "unknown"; |
| 805 | |
| 806 | static DEFINE_RATELIMIT_STATE(_rs, |
| 807 | DEFAULT_RATELIMIT_INTERVAL, |
| 808 | DEFAULT_RATELIMIT_BURST); |
| 809 | |
| 810 | if (mmu == NULL) |
| 811 | return ret; |
| 812 | |
| 813 | iommu = _IOMMU_PRIV(mmu); |
| 814 | ctx = &iommu->ctx[KGSL_IOMMU_CONTEXT_USER]; |
| 815 | device = KGSL_MMU_DEVICE(mmu); |
| 816 | adreno_dev = ADRENO_DEVICE(device); |
Lynus Vaz | 1fde74d | 2017-03-20 18:02:47 +0530 | [diff] [blame] | 817 | gpudev = ADRENO_GPU_DEVICE(adreno_dev); |
Shrenuj Bansal | a419c79 | 2016-10-20 14:05:11 -0700 | [diff] [blame] | 818 | |
| 819 | if (pt->name == KGSL_MMU_SECURE_PT) |
| 820 | ctx = &iommu->ctx[KGSL_IOMMU_CONTEXT_SECURE]; |
| 821 | |
| 822 | /* |
| 823 | * set the fault bits and stuff before any printks so that if fault |
| 824 | * handler runs then it will know it's dealing with a pagefault. |
| 825 | * Read the global current timestamp because we could be in middle of |
| 826 | * RB switch and hence the cur RB may not be reliable but global |
| 827 | * one will always be reliable |
| 828 | */ |
| 829 | kgsl_sharedmem_readl(&device->memstore, &curr_context_id, |
| 830 | KGSL_MEMSTORE_OFFSET(KGSL_MEMSTORE_GLOBAL, current_context)); |
| 831 | |
| 832 | context = kgsl_context_get(device, curr_context_id); |
| 833 | |
| 834 | write = (flags & IOMMU_FAULT_WRITE) ? 1 : 0; |
| 835 | if (flags & IOMMU_FAULT_TRANSLATION) |
| 836 | fault_type = "translation"; |
| 837 | else if (flags & IOMMU_FAULT_PERMISSION) |
| 838 | fault_type = "permission"; |
| 839 | |
| 840 | if (kgsl_iommu_suppress_pagefault(addr, write, context)) { |
| 841 | iommu->pagefault_suppression_count++; |
| 842 | kgsl_context_put(context); |
| 843 | return ret; |
| 844 | } |
| 845 | |
| 846 | if (context != NULL) { |
| 847 | /* save pagefault timestamp for GFT */ |
| 848 | set_bit(KGSL_CONTEXT_PRIV_PAGEFAULT, &context->priv); |
| 849 | tid = context->tid; |
| 850 | } |
| 851 | |
| 852 | ctx->fault = 1; |
| 853 | |
| 854 | if (test_bit(KGSL_FT_PAGEFAULT_GPUHALT_ENABLE, |
| 855 | &adreno_dev->ft_pf_policy) && |
| 856 | (flags & IOMMU_FAULT_TRANSACTION_STALLED)) { |
| 857 | /* |
| 858 | * Turn off GPU IRQ so we don't get faults from it too. |
| 859 | * The device mutex must be held to change power state |
| 860 | */ |
| 861 | mutex_lock(&device->mutex); |
| 862 | kgsl_pwrctrl_change_state(device, KGSL_STATE_AWARE); |
| 863 | mutex_unlock(&device->mutex); |
| 864 | } |
| 865 | |
| 866 | ptbase = KGSL_IOMMU_GET_CTX_REG_Q(ctx, TTBR0); |
| 867 | contextidr = KGSL_IOMMU_GET_CTX_REG(ctx, CONTEXTIDR); |
| 868 | |
| 869 | ptname = MMU_FEATURE(mmu, KGSL_MMU_GLOBAL_PAGETABLE) ? |
| 870 | KGSL_MMU_GLOBAL_PT : tid; |
Sunil Khatri | 86e9568 | 2017-01-23 17:10:32 +0530 | [diff] [blame] | 871 | /* |
| 872 | * Trace needs to be logged before searching the faulting |
| 873 | * address in free list as it takes quite long time in |
| 874 | * search and delays the trace unnecessarily. |
| 875 | */ |
| 876 | trace_kgsl_mmu_pagefault(ctx->kgsldev, addr, |
| 877 | ptname, write ? "write" : "read"); |
Shrenuj Bansal | a419c79 | 2016-10-20 14:05:11 -0700 | [diff] [blame] | 878 | |
| 879 | if (test_bit(KGSL_FT_PAGEFAULT_LOG_ONE_PER_PAGE, |
| 880 | &adreno_dev->ft_pf_policy)) |
| 881 | no_page_fault_log = kgsl_mmu_log_fault_addr(mmu, ptbase, addr); |
| 882 | |
| 883 | if (!no_page_fault_log && __ratelimit(&_rs)) { |
| 884 | KGSL_MEM_CRIT(ctx->kgsldev, |
| 885 | "GPU PAGE FAULT: addr = %lX pid= %d\n", addr, ptname); |
| 886 | KGSL_MEM_CRIT(ctx->kgsldev, |
| 887 | "context=%s TTBR0=0x%llx CIDR=0x%x (%s %s fault)\n", |
| 888 | ctx->name, ptbase, contextidr, |
| 889 | write ? "write" : "read", fault_type); |
| 890 | |
Lynus Vaz | 1fde74d | 2017-03-20 18:02:47 +0530 | [diff] [blame] | 891 | if (gpudev->iommu_fault_block) { |
| 892 | unsigned int fsynr1; |
| 893 | |
| 894 | fsynr1 = KGSL_IOMMU_GET_CTX_REG(ctx, FSYNR1); |
| 895 | KGSL_MEM_CRIT(ctx->kgsldev, |
| 896 | "FAULTING BLOCK: %s\n", |
| 897 | gpudev->iommu_fault_block(adreno_dev, |
| 898 | fsynr1)); |
| 899 | } |
| 900 | |
Shrenuj Bansal | a419c79 | 2016-10-20 14:05:11 -0700 | [diff] [blame] | 901 | /* Don't print the debug if this is a permissions fault */ |
| 902 | if (!(flags & IOMMU_FAULT_PERMISSION)) { |
| 903 | _check_if_freed(ctx, addr, ptname); |
| 904 | |
| 905 | KGSL_LOG_DUMP(ctx->kgsldev, |
| 906 | "---- nearby memory ----\n"); |
| 907 | |
| 908 | _find_mem_entries(mmu, addr, &prev, &next, context); |
| 909 | if (prev.gpuaddr) |
| 910 | _print_entry(ctx->kgsldev, &prev); |
| 911 | else |
| 912 | KGSL_LOG_DUMP(ctx->kgsldev, "*EMPTY*\n"); |
| 913 | |
| 914 | KGSL_LOG_DUMP(ctx->kgsldev, " <- fault @ %8.8lX\n", |
| 915 | addr); |
| 916 | |
| 917 | if (next.gpuaddr != (uint64_t) -1) |
| 918 | _print_entry(ctx->kgsldev, &next); |
| 919 | else |
| 920 | KGSL_LOG_DUMP(ctx->kgsldev, "*EMPTY*\n"); |
| 921 | } |
| 922 | } |
| 923 | |
Shrenuj Bansal | a419c79 | 2016-10-20 14:05:11 -0700 | [diff] [blame] | 924 | |
| 925 | /* |
| 926 | * We do not want the h/w to resume fetching data from an iommu |
| 927 | * that has faulted, this is better for debugging as it will stall |
| 928 | * the GPU and trigger a snapshot. Return EBUSY error. |
| 929 | */ |
| 930 | if (test_bit(KGSL_FT_PAGEFAULT_GPUHALT_ENABLE, |
| 931 | &adreno_dev->ft_pf_policy) && |
| 932 | (flags & IOMMU_FAULT_TRANSACTION_STALLED)) { |
| 933 | uint32_t sctlr_val; |
| 934 | |
| 935 | ret = -EBUSY; |
| 936 | /* |
| 937 | * Disable context fault interrupts |
| 938 | * as we do not clear FSR in the ISR. |
| 939 | * Will be re-enabled after FSR is cleared. |
| 940 | */ |
| 941 | sctlr_val = KGSL_IOMMU_GET_CTX_REG(ctx, SCTLR); |
| 942 | sctlr_val &= ~(0x1 << KGSL_IOMMU_SCTLR_CFIE_SHIFT); |
| 943 | KGSL_IOMMU_SET_CTX_REG(ctx, SCTLR, sctlr_val); |
| 944 | |
| 945 | adreno_set_gpu_fault(adreno_dev, ADRENO_IOMMU_PAGE_FAULT); |
| 946 | /* Go ahead with recovery*/ |
| 947 | adreno_dispatcher_schedule(device); |
| 948 | } |
| 949 | |
| 950 | kgsl_context_put(context); |
| 951 | return ret; |
| 952 | } |
| 953 | |
| 954 | /* |
| 955 | * kgsl_iommu_disable_clk() - Disable iommu clocks |
| 956 | * Disable IOMMU clocks |
| 957 | */ |
| 958 | static void kgsl_iommu_disable_clk(struct kgsl_mmu *mmu) |
| 959 | { |
| 960 | struct kgsl_iommu *iommu = _IOMMU_PRIV(mmu); |
| 961 | int j; |
| 962 | |
| 963 | atomic_dec(&iommu->clk_enable_count); |
| 964 | |
| 965 | /* |
| 966 | * Make sure the clk refcounts are good. An unbalance may |
| 967 | * cause the clocks to be off when we need them on. |
| 968 | */ |
| 969 | WARN_ON(atomic_read(&iommu->clk_enable_count) < 0); |
| 970 | |
| 971 | for (j = (KGSL_IOMMU_MAX_CLKS - 1); j >= 0; j--) |
| 972 | if (iommu->clks[j]) |
| 973 | clk_disable_unprepare(iommu->clks[j]); |
| 974 | } |
| 975 | |
| 976 | /* |
| 977 | * kgsl_iommu_enable_clk_prepare_enable - Enable the specified IOMMU clock |
| 978 | * Try 4 times to enable it and then BUG() for debug |
| 979 | */ |
| 980 | static void kgsl_iommu_clk_prepare_enable(struct clk *clk) |
| 981 | { |
| 982 | int num_retries = 4; |
| 983 | |
| 984 | while (num_retries--) { |
| 985 | if (!clk_prepare_enable(clk)) |
| 986 | return; |
| 987 | } |
| 988 | |
| 989 | /* Failure is fatal so BUG() to facilitate debug */ |
| 990 | KGSL_CORE_ERR("IOMMU clock enable failed\n"); |
| 991 | BUG(); |
| 992 | } |
| 993 | |
| 994 | /* |
| 995 | * kgsl_iommu_enable_clk - Enable iommu clocks |
| 996 | * Enable all the IOMMU clocks |
| 997 | */ |
| 998 | static void kgsl_iommu_enable_clk(struct kgsl_mmu *mmu) |
| 999 | { |
| 1000 | int j; |
| 1001 | struct kgsl_iommu *iommu = _IOMMU_PRIV(mmu); |
| 1002 | |
| 1003 | for (j = 0; j < KGSL_IOMMU_MAX_CLKS; j++) { |
| 1004 | if (iommu->clks[j]) |
| 1005 | kgsl_iommu_clk_prepare_enable(iommu->clks[j]); |
| 1006 | } |
| 1007 | atomic_inc(&iommu->clk_enable_count); |
| 1008 | } |
| 1009 | |
| 1010 | /* kgsl_iommu_get_ttbr0 - Get TTBR0 setting for a pagetable */ |
| 1011 | static u64 kgsl_iommu_get_ttbr0(struct kgsl_pagetable *pt) |
| 1012 | { |
| 1013 | struct kgsl_iommu_pt *iommu_pt = pt ? pt->priv : NULL; |
| 1014 | |
| 1015 | BUG_ON(iommu_pt == NULL); |
| 1016 | |
| 1017 | return iommu_pt->ttbr0; |
| 1018 | } |
| 1019 | |
| 1020 | static bool kgsl_iommu_pt_equal(struct kgsl_mmu *mmu, |
| 1021 | struct kgsl_pagetable *pt, |
| 1022 | u64 ttbr0) |
| 1023 | { |
| 1024 | struct kgsl_iommu_pt *iommu_pt = pt ? pt->priv : NULL; |
| 1025 | u64 domain_ttbr0; |
| 1026 | |
| 1027 | if (iommu_pt == NULL) |
| 1028 | return 0; |
| 1029 | |
| 1030 | domain_ttbr0 = kgsl_iommu_get_ttbr0(pt); |
| 1031 | |
| 1032 | return (domain_ttbr0 == ttbr0); |
| 1033 | } |
| 1034 | |
| 1035 | /* kgsl_iommu_get_contextidr - query CONTEXTIDR setting for a pagetable */ |
| 1036 | static u32 kgsl_iommu_get_contextidr(struct kgsl_pagetable *pt) |
| 1037 | { |
| 1038 | struct kgsl_iommu_pt *iommu_pt = pt ? pt->priv : NULL; |
| 1039 | |
| 1040 | BUG_ON(iommu_pt == NULL); |
| 1041 | |
| 1042 | return iommu_pt->contextidr; |
| 1043 | } |
| 1044 | |
| 1045 | /* |
| 1046 | * kgsl_iommu_destroy_pagetable - Free up reaources help by a pagetable |
| 1047 | * @mmu_specific_pt - Pointer to pagetable which is to be freed |
| 1048 | * |
| 1049 | * Return - void |
| 1050 | */ |
| 1051 | static void kgsl_iommu_destroy_pagetable(struct kgsl_pagetable *pt) |
| 1052 | { |
| 1053 | struct kgsl_iommu_pt *iommu_pt = pt->priv; |
| 1054 | struct kgsl_mmu *mmu = pt->mmu; |
| 1055 | struct kgsl_iommu *iommu; |
| 1056 | struct kgsl_iommu_context *ctx; |
| 1057 | |
| 1058 | /* |
| 1059 | * Make sure all allocations are unmapped before destroying |
| 1060 | * the pagetable |
| 1061 | */ |
| 1062 | WARN_ON(!list_empty(&pt->list)); |
| 1063 | |
| 1064 | iommu = _IOMMU_PRIV(mmu); |
| 1065 | |
| 1066 | if (pt->name == KGSL_MMU_SECURE_PT) { |
| 1067 | ctx = &iommu->ctx[KGSL_IOMMU_CONTEXT_SECURE]; |
| 1068 | kgsl_iommu_unmap_global_secure_pt_entry(pt); |
| 1069 | } else { |
| 1070 | ctx = &iommu->ctx[KGSL_IOMMU_CONTEXT_USER]; |
| 1071 | kgsl_iommu_unmap_globals(pt); |
| 1072 | } |
| 1073 | |
| 1074 | if (iommu_pt->domain) { |
| 1075 | trace_kgsl_pagetable_destroy(iommu_pt->ttbr0, pt->name); |
| 1076 | |
| 1077 | _detach_pt(iommu_pt, ctx); |
| 1078 | |
| 1079 | iommu_domain_free(iommu_pt->domain); |
| 1080 | } |
| 1081 | |
| 1082 | kfree(iommu_pt); |
| 1083 | } |
| 1084 | |
| 1085 | static void setup_64bit_pagetable(struct kgsl_mmu *mmu, |
| 1086 | struct kgsl_pagetable *pagetable, |
| 1087 | struct kgsl_iommu_pt *pt) |
| 1088 | { |
| 1089 | unsigned int secure_global_size = kgsl_global_secure_pt_entry != NULL ? |
| 1090 | kgsl_global_secure_pt_entry->size : 0; |
| 1091 | if (mmu->secured && pagetable->name == KGSL_MMU_SECURE_PT) { |
| 1092 | pt->compat_va_start = KGSL_IOMMU_SECURE_BASE + |
| 1093 | secure_global_size; |
| 1094 | pt->compat_va_end = KGSL_IOMMU_SECURE_END; |
| 1095 | pt->va_start = KGSL_IOMMU_SECURE_BASE + secure_global_size; |
| 1096 | pt->va_end = KGSL_IOMMU_SECURE_END; |
| 1097 | } else { |
| 1098 | pt->compat_va_start = KGSL_IOMMU_SVM_BASE32; |
| 1099 | pt->compat_va_end = KGSL_IOMMU_SVM_END32; |
| 1100 | pt->va_start = KGSL_IOMMU_VA_BASE64; |
| 1101 | pt->va_end = KGSL_IOMMU_VA_END64; |
| 1102 | } |
| 1103 | |
| 1104 | if (pagetable->name != KGSL_MMU_GLOBAL_PT && |
| 1105 | pagetable->name != KGSL_MMU_SECURE_PT) { |
| 1106 | if ((BITS_PER_LONG == 32) || is_compat_task()) { |
| 1107 | pt->svm_start = KGSL_IOMMU_SVM_BASE32; |
| 1108 | pt->svm_end = KGSL_IOMMU_SVM_END32; |
| 1109 | } else { |
| 1110 | pt->svm_start = KGSL_IOMMU_SVM_BASE64; |
| 1111 | pt->svm_end = KGSL_IOMMU_SVM_END64; |
| 1112 | } |
| 1113 | } |
| 1114 | } |
| 1115 | |
| 1116 | static void setup_32bit_pagetable(struct kgsl_mmu *mmu, |
| 1117 | struct kgsl_pagetable *pagetable, |
| 1118 | struct kgsl_iommu_pt *pt) |
| 1119 | { |
| 1120 | unsigned int secure_global_size = kgsl_global_secure_pt_entry != NULL ? |
| 1121 | kgsl_global_secure_pt_entry->size : 0; |
| 1122 | if (mmu->secured) { |
| 1123 | if (pagetable->name == KGSL_MMU_SECURE_PT) { |
| 1124 | pt->compat_va_start = KGSL_IOMMU_SECURE_BASE + |
| 1125 | secure_global_size; |
| 1126 | pt->compat_va_end = KGSL_IOMMU_SECURE_END; |
| 1127 | pt->va_start = KGSL_IOMMU_SECURE_BASE + |
| 1128 | secure_global_size; |
| 1129 | pt->va_end = KGSL_IOMMU_SECURE_END; |
| 1130 | } else { |
| 1131 | pt->va_start = KGSL_IOMMU_SVM_BASE32; |
| 1132 | pt->va_end = KGSL_IOMMU_SECURE_BASE + |
| 1133 | secure_global_size; |
| 1134 | pt->compat_va_start = pt->va_start; |
| 1135 | pt->compat_va_end = pt->va_end; |
| 1136 | } |
| 1137 | } else { |
| 1138 | pt->va_start = KGSL_IOMMU_SVM_BASE32; |
| 1139 | pt->va_end = KGSL_IOMMU_GLOBAL_MEM_BASE; |
| 1140 | pt->compat_va_start = pt->va_start; |
| 1141 | pt->compat_va_end = pt->va_end; |
| 1142 | } |
| 1143 | |
| 1144 | if (pagetable->name != KGSL_MMU_GLOBAL_PT && |
| 1145 | pagetable->name != KGSL_MMU_SECURE_PT) { |
| 1146 | pt->svm_start = KGSL_IOMMU_SVM_BASE32; |
| 1147 | pt->svm_end = KGSL_IOMMU_SVM_END32; |
| 1148 | } |
| 1149 | } |
| 1150 | |
| 1151 | |
| 1152 | static struct kgsl_iommu_pt * |
| 1153 | _alloc_pt(struct device *dev, struct kgsl_mmu *mmu, struct kgsl_pagetable *pt) |
| 1154 | { |
| 1155 | struct kgsl_iommu_pt *iommu_pt; |
| 1156 | struct bus_type *bus = kgsl_mmu_get_bus(dev); |
| 1157 | |
| 1158 | if (bus == NULL) |
| 1159 | return ERR_PTR(-ENODEV); |
| 1160 | |
| 1161 | iommu_pt = kzalloc(sizeof(struct kgsl_iommu_pt), GFP_KERNEL); |
| 1162 | if (iommu_pt == NULL) |
| 1163 | return ERR_PTR(-ENOMEM); |
| 1164 | |
| 1165 | iommu_pt->domain = iommu_domain_alloc(bus); |
| 1166 | if (iommu_pt->domain == NULL) { |
| 1167 | kfree(iommu_pt); |
| 1168 | return ERR_PTR(-ENODEV); |
| 1169 | } |
| 1170 | |
| 1171 | pt->pt_ops = &iommu_pt_ops; |
| 1172 | pt->priv = iommu_pt; |
| 1173 | pt->fault_addr = ~0ULL; |
| 1174 | iommu_pt->rbtree = RB_ROOT; |
| 1175 | |
| 1176 | if (MMU_FEATURE(mmu, KGSL_MMU_64BIT)) |
| 1177 | setup_64bit_pagetable(mmu, pt, iommu_pt); |
| 1178 | else |
| 1179 | setup_32bit_pagetable(mmu, pt, iommu_pt); |
| 1180 | |
| 1181 | |
| 1182 | return iommu_pt; |
| 1183 | } |
| 1184 | |
| 1185 | static void _free_pt(struct kgsl_iommu_context *ctx, struct kgsl_pagetable *pt) |
| 1186 | { |
| 1187 | struct kgsl_iommu_pt *iommu_pt = pt->priv; |
| 1188 | |
| 1189 | pt->pt_ops = NULL; |
| 1190 | pt->priv = NULL; |
| 1191 | |
| 1192 | if (iommu_pt == NULL) |
| 1193 | return; |
| 1194 | |
| 1195 | _detach_pt(iommu_pt, ctx); |
| 1196 | |
| 1197 | if (iommu_pt->domain != NULL) |
| 1198 | iommu_domain_free(iommu_pt->domain); |
| 1199 | kfree(iommu_pt); |
| 1200 | } |
| 1201 | |
Sushmita Susheelendra | 906564d | 2017-01-10 15:53:55 -0700 | [diff] [blame] | 1202 | void _enable_gpuhtw_llc(struct kgsl_mmu *mmu, struct kgsl_iommu_pt *iommu_pt) |
| 1203 | { |
| 1204 | struct kgsl_device *device = KGSL_MMU_DEVICE(mmu); |
| 1205 | struct adreno_device *adreno_dev = ADRENO_DEVICE(device); |
| 1206 | int gpuhtw_llc_enable = 1; |
| 1207 | int ret; |
| 1208 | |
| 1209 | /* GPU pagetable walk LLC slice not enabled */ |
| 1210 | if (!adreno_dev->gpuhtw_llc_slice) |
| 1211 | return; |
| 1212 | |
| 1213 | /* Domain attribute to enable system cache for GPU pagetable walks */ |
| 1214 | ret = iommu_domain_set_attr(iommu_pt->domain, |
| 1215 | DOMAIN_ATTR_USE_UPSTREAM_HINT, &gpuhtw_llc_enable); |
| 1216 | /* |
| 1217 | * Warn that the system cache will not be used for GPU |
| 1218 | * pagetable walks. This is not a fatal error. |
| 1219 | */ |
| 1220 | WARN_ONCE(ret, |
| 1221 | "System cache not enabled for GPU pagetable walks: %d\n", ret); |
| 1222 | } |
| 1223 | |
Shrenuj Bansal | a419c79 | 2016-10-20 14:05:11 -0700 | [diff] [blame] | 1224 | static int _init_global_pt(struct kgsl_mmu *mmu, struct kgsl_pagetable *pt) |
| 1225 | { |
| 1226 | int ret = 0; |
| 1227 | struct kgsl_iommu_pt *iommu_pt = NULL; |
| 1228 | unsigned int cb_num; |
| 1229 | struct kgsl_iommu *iommu = _IOMMU_PRIV(mmu); |
| 1230 | struct kgsl_iommu_context *ctx = &iommu->ctx[KGSL_IOMMU_CONTEXT_USER]; |
| 1231 | |
| 1232 | iommu_pt = _alloc_pt(ctx->dev, mmu, pt); |
| 1233 | |
| 1234 | if (IS_ERR(iommu_pt)) |
| 1235 | return PTR_ERR(iommu_pt); |
| 1236 | |
| 1237 | if (kgsl_mmu_is_perprocess(mmu)) { |
| 1238 | ret = iommu_domain_set_attr(iommu_pt->domain, |
| 1239 | DOMAIN_ATTR_PROCID, &pt->name); |
| 1240 | if (ret) { |
| 1241 | KGSL_CORE_ERR("set DOMAIN_ATTR_PROCID failed: %d\n", |
| 1242 | ret); |
| 1243 | goto done; |
| 1244 | } |
| 1245 | } |
| 1246 | |
Sushmita Susheelendra | 906564d | 2017-01-10 15:53:55 -0700 | [diff] [blame] | 1247 | _enable_gpuhtw_llc(mmu, iommu_pt); |
| 1248 | |
Shrenuj Bansal | a419c79 | 2016-10-20 14:05:11 -0700 | [diff] [blame] | 1249 | ret = _attach_pt(iommu_pt, ctx); |
| 1250 | if (ret) |
| 1251 | goto done; |
| 1252 | |
| 1253 | iommu_set_fault_handler(iommu_pt->domain, |
| 1254 | kgsl_iommu_fault_handler, pt); |
| 1255 | |
| 1256 | ret = iommu_domain_get_attr(iommu_pt->domain, |
| 1257 | DOMAIN_ATTR_CONTEXT_BANK, &cb_num); |
| 1258 | if (ret) { |
| 1259 | KGSL_CORE_ERR("get DOMAIN_ATTR_PROCID failed: %d\n", |
| 1260 | ret); |
| 1261 | goto done; |
| 1262 | } |
| 1263 | |
| 1264 | ctx->cb_num = cb_num; |
| 1265 | ctx->regbase = iommu->regbase + KGSL_IOMMU_CB0_OFFSET |
| 1266 | + (cb_num << KGSL_IOMMU_CB_SHIFT); |
| 1267 | |
| 1268 | ret = iommu_domain_get_attr(iommu_pt->domain, |
| 1269 | DOMAIN_ATTR_TTBR0, &iommu_pt->ttbr0); |
| 1270 | if (ret) { |
| 1271 | KGSL_CORE_ERR("get DOMAIN_ATTR_TTBR0 failed: %d\n", |
| 1272 | ret); |
| 1273 | goto done; |
| 1274 | } |
| 1275 | ret = iommu_domain_get_attr(iommu_pt->domain, |
| 1276 | DOMAIN_ATTR_CONTEXTIDR, &iommu_pt->contextidr); |
| 1277 | if (ret) { |
| 1278 | KGSL_CORE_ERR("get DOMAIN_ATTR_CONTEXTIDR failed: %d\n", |
| 1279 | ret); |
| 1280 | goto done; |
| 1281 | } |
| 1282 | |
| 1283 | ret = kgsl_iommu_map_globals(pt); |
| 1284 | |
| 1285 | done: |
| 1286 | if (ret) |
| 1287 | _free_pt(ctx, pt); |
| 1288 | |
| 1289 | return ret; |
| 1290 | } |
| 1291 | |
| 1292 | static int _init_secure_pt(struct kgsl_mmu *mmu, struct kgsl_pagetable *pt) |
| 1293 | { |
| 1294 | int ret = 0; |
| 1295 | struct kgsl_iommu_pt *iommu_pt = NULL; |
| 1296 | struct kgsl_iommu *iommu = _IOMMU_PRIV(mmu); |
| 1297 | struct kgsl_iommu_context *ctx = &iommu->ctx[KGSL_IOMMU_CONTEXT_SECURE]; |
| 1298 | int secure_vmid = VMID_CP_PIXEL; |
| 1299 | unsigned int cb_num; |
| 1300 | |
| 1301 | if (!mmu->secured) |
| 1302 | return -EPERM; |
| 1303 | |
| 1304 | if (!MMU_FEATURE(mmu, KGSL_MMU_HYP_SECURE_ALLOC)) { |
| 1305 | if (!kgsl_mmu_bus_secured(ctx->dev)) |
| 1306 | return -EPERM; |
| 1307 | } |
| 1308 | |
| 1309 | iommu_pt = _alloc_pt(ctx->dev, mmu, pt); |
| 1310 | |
| 1311 | if (IS_ERR(iommu_pt)) |
| 1312 | return PTR_ERR(iommu_pt); |
| 1313 | |
| 1314 | ret = iommu_domain_set_attr(iommu_pt->domain, |
| 1315 | DOMAIN_ATTR_SECURE_VMID, &secure_vmid); |
| 1316 | if (ret) { |
| 1317 | KGSL_CORE_ERR("set DOMAIN_ATTR_SECURE_VMID failed: %d\n", ret); |
| 1318 | goto done; |
| 1319 | } |
| 1320 | |
Sushmita Susheelendra | 906564d | 2017-01-10 15:53:55 -0700 | [diff] [blame] | 1321 | _enable_gpuhtw_llc(mmu, iommu_pt); |
| 1322 | |
Shrenuj Bansal | a419c79 | 2016-10-20 14:05:11 -0700 | [diff] [blame] | 1323 | ret = _attach_pt(iommu_pt, ctx); |
| 1324 | |
| 1325 | if (MMU_FEATURE(mmu, KGSL_MMU_HYP_SECURE_ALLOC)) |
| 1326 | iommu_set_fault_handler(iommu_pt->domain, |
| 1327 | kgsl_iommu_fault_handler, pt); |
| 1328 | |
| 1329 | ret = iommu_domain_get_attr(iommu_pt->domain, |
| 1330 | DOMAIN_ATTR_CONTEXT_BANK, &cb_num); |
| 1331 | if (ret) { |
| 1332 | KGSL_CORE_ERR("get DOMAIN_ATTR_PROCID failed: %d\n", |
| 1333 | ret); |
| 1334 | goto done; |
| 1335 | } |
| 1336 | |
| 1337 | ctx->cb_num = cb_num; |
| 1338 | ctx->regbase = iommu->regbase + KGSL_IOMMU_CB0_OFFSET |
| 1339 | + (cb_num << KGSL_IOMMU_CB_SHIFT); |
| 1340 | |
| 1341 | ret = kgsl_map_global_secure_pt_entry(pt); |
| 1342 | |
| 1343 | done: |
| 1344 | if (ret) |
| 1345 | _free_pt(ctx, pt); |
| 1346 | return ret; |
| 1347 | } |
| 1348 | |
| 1349 | static int _init_per_process_pt(struct kgsl_mmu *mmu, struct kgsl_pagetable *pt) |
| 1350 | { |
| 1351 | int ret = 0; |
| 1352 | struct kgsl_iommu_pt *iommu_pt = NULL; |
| 1353 | struct kgsl_iommu *iommu = _IOMMU_PRIV(mmu); |
| 1354 | struct kgsl_iommu_context *ctx = &iommu->ctx[KGSL_IOMMU_CONTEXT_USER]; |
| 1355 | int dynamic = 1; |
| 1356 | unsigned int cb_num = ctx->cb_num; |
| 1357 | |
| 1358 | iommu_pt = _alloc_pt(ctx->dev, mmu, pt); |
| 1359 | |
| 1360 | if (IS_ERR(iommu_pt)) |
| 1361 | return PTR_ERR(iommu_pt); |
| 1362 | |
| 1363 | ret = iommu_domain_set_attr(iommu_pt->domain, |
| 1364 | DOMAIN_ATTR_DYNAMIC, &dynamic); |
| 1365 | if (ret) { |
| 1366 | KGSL_CORE_ERR("set DOMAIN_ATTR_DYNAMIC failed: %d\n", ret); |
| 1367 | goto done; |
| 1368 | } |
| 1369 | ret = iommu_domain_set_attr(iommu_pt->domain, |
| 1370 | DOMAIN_ATTR_CONTEXT_BANK, &cb_num); |
| 1371 | if (ret) { |
| 1372 | KGSL_CORE_ERR("set DOMAIN_ATTR_CONTEXT_BANK failed: %d\n", ret); |
| 1373 | goto done; |
| 1374 | } |
| 1375 | |
| 1376 | ret = iommu_domain_set_attr(iommu_pt->domain, |
| 1377 | DOMAIN_ATTR_PROCID, &pt->name); |
| 1378 | if (ret) { |
| 1379 | KGSL_CORE_ERR("set DOMAIN_ATTR_PROCID failed: %d\n", ret); |
| 1380 | goto done; |
| 1381 | } |
| 1382 | |
Sushmita Susheelendra | 906564d | 2017-01-10 15:53:55 -0700 | [diff] [blame] | 1383 | _enable_gpuhtw_llc(mmu, iommu_pt); |
| 1384 | |
Shrenuj Bansal | a419c79 | 2016-10-20 14:05:11 -0700 | [diff] [blame] | 1385 | ret = _attach_pt(iommu_pt, ctx); |
| 1386 | if (ret) |
| 1387 | goto done; |
| 1388 | |
| 1389 | /* now read back the attributes needed for self programming */ |
| 1390 | ret = iommu_domain_get_attr(iommu_pt->domain, |
| 1391 | DOMAIN_ATTR_TTBR0, &iommu_pt->ttbr0); |
| 1392 | if (ret) { |
| 1393 | KGSL_CORE_ERR("get DOMAIN_ATTR_TTBR0 failed: %d\n", ret); |
| 1394 | goto done; |
| 1395 | } |
| 1396 | |
| 1397 | ret = iommu_domain_get_attr(iommu_pt->domain, |
| 1398 | DOMAIN_ATTR_CONTEXTIDR, &iommu_pt->contextidr); |
| 1399 | if (ret) { |
| 1400 | KGSL_CORE_ERR("get DOMAIN_ATTR_CONTEXTIDR failed: %d\n", ret); |
| 1401 | goto done; |
| 1402 | } |
| 1403 | |
| 1404 | ret = kgsl_iommu_map_globals(pt); |
| 1405 | |
| 1406 | done: |
| 1407 | if (ret) |
| 1408 | _free_pt(ctx, pt); |
| 1409 | |
| 1410 | return ret; |
| 1411 | } |
| 1412 | |
| 1413 | /* kgsl_iommu_init_pt - Set up an IOMMU pagetable */ |
| 1414 | static int kgsl_iommu_init_pt(struct kgsl_mmu *mmu, struct kgsl_pagetable *pt) |
| 1415 | { |
| 1416 | if (pt == NULL) |
| 1417 | return -EINVAL; |
| 1418 | |
| 1419 | switch (pt->name) { |
| 1420 | case KGSL_MMU_GLOBAL_PT: |
| 1421 | return _init_global_pt(mmu, pt); |
| 1422 | |
| 1423 | case KGSL_MMU_SECURE_PT: |
| 1424 | return _init_secure_pt(mmu, pt); |
| 1425 | |
| 1426 | default: |
| 1427 | return _init_per_process_pt(mmu, pt); |
| 1428 | } |
| 1429 | } |
| 1430 | |
| 1431 | static struct kgsl_pagetable *kgsl_iommu_getpagetable(struct kgsl_mmu *mmu, |
| 1432 | unsigned long name) |
| 1433 | { |
| 1434 | struct kgsl_pagetable *pt; |
| 1435 | |
| 1436 | if (!kgsl_mmu_is_perprocess(mmu) && (name != KGSL_MMU_SECURE_PT)) { |
| 1437 | name = KGSL_MMU_GLOBAL_PT; |
| 1438 | if (mmu->defaultpagetable != NULL) |
| 1439 | return mmu->defaultpagetable; |
| 1440 | } |
| 1441 | |
| 1442 | pt = kgsl_get_pagetable(name); |
| 1443 | if (pt == NULL) |
| 1444 | pt = kgsl_mmu_createpagetableobject(mmu, name); |
| 1445 | |
| 1446 | return pt; |
| 1447 | } |
| 1448 | |
| 1449 | /* |
| 1450 | * kgsl_iommu_get_reg_ahbaddr - Returns the ahb address of the register |
| 1451 | * @mmu - Pointer to mmu structure |
| 1452 | * @id - The context ID of the IOMMU ctx |
| 1453 | * @reg - The register for which address is required |
| 1454 | * |
| 1455 | * Return - The address of register which can be used in type0 packet |
| 1456 | */ |
| 1457 | static unsigned int kgsl_iommu_get_reg_ahbaddr(struct kgsl_mmu *mmu, |
| 1458 | int id, unsigned int reg) |
| 1459 | { |
| 1460 | struct kgsl_iommu *iommu = _IOMMU_PRIV(mmu); |
| 1461 | struct kgsl_iommu_context *ctx = &iommu->ctx[id]; |
| 1462 | |
| 1463 | return ctx->gpu_offset + kgsl_iommu_reg_list[reg]; |
| 1464 | } |
| 1465 | |
| 1466 | static void _detach_context(struct kgsl_iommu_context *ctx) |
| 1467 | { |
| 1468 | struct kgsl_iommu_pt *iommu_pt; |
| 1469 | |
| 1470 | if (ctx->default_pt == NULL) |
| 1471 | return; |
| 1472 | |
| 1473 | iommu_pt = ctx->default_pt->priv; |
| 1474 | |
| 1475 | _detach_pt(iommu_pt, ctx); |
| 1476 | |
| 1477 | ctx->default_pt = NULL; |
| 1478 | } |
| 1479 | |
| 1480 | static void kgsl_iommu_close(struct kgsl_mmu *mmu) |
| 1481 | { |
| 1482 | struct kgsl_iommu *iommu = _IOMMU_PRIV(mmu); |
| 1483 | int i; |
| 1484 | |
| 1485 | for (i = 0; i < KGSL_IOMMU_CONTEXT_MAX; i++) |
| 1486 | _detach_context(&iommu->ctx[i]); |
| 1487 | |
| 1488 | kgsl_mmu_putpagetable(mmu->defaultpagetable); |
| 1489 | mmu->defaultpagetable = NULL; |
| 1490 | |
| 1491 | kgsl_mmu_putpagetable(mmu->securepagetable); |
| 1492 | mmu->securepagetable = NULL; |
| 1493 | |
| 1494 | if (iommu->regbase != NULL) |
| 1495 | iounmap(iommu->regbase); |
| 1496 | |
| 1497 | kgsl_sharedmem_free(&kgsl_secure_guard_page_memdesc); |
| 1498 | |
| 1499 | if (kgsl_guard_page != NULL) { |
| 1500 | __free_page(kgsl_guard_page); |
| 1501 | kgsl_guard_page = NULL; |
| 1502 | } |
| 1503 | |
| 1504 | if (kgsl_dummy_page != NULL) { |
| 1505 | __free_page(kgsl_dummy_page); |
| 1506 | kgsl_dummy_page = NULL; |
| 1507 | } |
| 1508 | |
| 1509 | kgsl_iommu_remove_global(mmu, &iommu->setstate); |
| 1510 | kgsl_sharedmem_free(&iommu->setstate); |
| 1511 | kgsl_cleanup_qdss_desc(mmu); |
Jonathan Wicks | 4892d8d | 2017-02-24 16:21:26 -0700 | [diff] [blame] | 1512 | kgsl_cleanup_qtimer_desc(mmu); |
Shrenuj Bansal | a419c79 | 2016-10-20 14:05:11 -0700 | [diff] [blame] | 1513 | } |
| 1514 | |
| 1515 | static int _setstate_alloc(struct kgsl_device *device, |
| 1516 | struct kgsl_iommu *iommu) |
| 1517 | { |
| 1518 | int ret; |
| 1519 | |
| 1520 | ret = kgsl_sharedmem_alloc_contig(device, &iommu->setstate, PAGE_SIZE); |
| 1521 | |
| 1522 | if (!ret) { |
| 1523 | /* Mark the setstate memory as read only */ |
| 1524 | iommu->setstate.flags |= KGSL_MEMFLAGS_GPUREADONLY; |
| 1525 | |
| 1526 | kgsl_sharedmem_set(device, &iommu->setstate, 0, 0, PAGE_SIZE); |
| 1527 | } |
| 1528 | |
| 1529 | return ret; |
| 1530 | } |
| 1531 | |
| 1532 | static int kgsl_iommu_init(struct kgsl_mmu *mmu) |
| 1533 | { |
| 1534 | struct kgsl_device *device = KGSL_MMU_DEVICE(mmu); |
| 1535 | struct kgsl_iommu *iommu = _IOMMU_PRIV(mmu); |
| 1536 | struct kgsl_iommu_context *ctx = &iommu->ctx[KGSL_IOMMU_CONTEXT_USER]; |
| 1537 | int status; |
| 1538 | |
| 1539 | mmu->features |= KGSL_MMU_PAGED; |
| 1540 | |
| 1541 | if (ctx->name == NULL) { |
| 1542 | KGSL_CORE_ERR("dt: gfx3d0_user context bank not found\n"); |
| 1543 | return -EINVAL; |
| 1544 | } |
| 1545 | |
| 1546 | status = _setstate_alloc(device, iommu); |
| 1547 | if (status) |
| 1548 | return status; |
| 1549 | |
| 1550 | /* check requirements for per process pagetables */ |
| 1551 | if (ctx->gpu_offset == UINT_MAX) { |
| 1552 | KGSL_CORE_ERR("missing qcom,gpu-offset forces global pt\n"); |
| 1553 | mmu->features |= KGSL_MMU_GLOBAL_PAGETABLE; |
| 1554 | } |
| 1555 | |
| 1556 | if (iommu->version == 1 && iommu->micro_mmu_ctrl == UINT_MAX) { |
| 1557 | KGSL_CORE_ERR( |
| 1558 | "missing qcom,micro-mmu-control forces global pt\n"); |
| 1559 | mmu->features |= KGSL_MMU_GLOBAL_PAGETABLE; |
| 1560 | } |
| 1561 | |
| 1562 | /* Check to see if we need to do the IOMMU sync dance */ |
| 1563 | need_iommu_sync = of_property_read_bool(device->pdev->dev.of_node, |
| 1564 | "qcom,gpu-quirk-iommu-sync"); |
| 1565 | |
| 1566 | iommu->regbase = ioremap(iommu->regstart, iommu->regsize); |
| 1567 | if (iommu->regbase == NULL) { |
| 1568 | KGSL_CORE_ERR("Could not map IOMMU registers 0x%lx:0x%x\n", |
| 1569 | iommu->regstart, iommu->regsize); |
| 1570 | status = -ENOMEM; |
| 1571 | goto done; |
| 1572 | } |
| 1573 | |
| 1574 | if (addr_entry_cache == NULL) { |
| 1575 | addr_entry_cache = KMEM_CACHE(kgsl_iommu_addr_entry, 0); |
| 1576 | if (addr_entry_cache == NULL) { |
| 1577 | status = -ENOMEM; |
| 1578 | goto done; |
| 1579 | } |
| 1580 | } |
| 1581 | |
| 1582 | kgsl_iommu_add_global(mmu, &iommu->setstate, "setstate"); |
| 1583 | kgsl_setup_qdss_desc(device); |
Jonathan Wicks | 4892d8d | 2017-02-24 16:21:26 -0700 | [diff] [blame] | 1584 | kgsl_setup_qtimer_desc(device); |
Shrenuj Bansal | a419c79 | 2016-10-20 14:05:11 -0700 | [diff] [blame] | 1585 | |
| 1586 | done: |
| 1587 | if (status) |
| 1588 | kgsl_iommu_close(mmu); |
| 1589 | |
| 1590 | return status; |
| 1591 | } |
| 1592 | |
| 1593 | static int _setup_user_context(struct kgsl_mmu *mmu) |
| 1594 | { |
| 1595 | int ret = 0; |
| 1596 | struct kgsl_iommu *iommu = _IOMMU_PRIV(mmu); |
| 1597 | struct kgsl_iommu_context *ctx = &iommu->ctx[KGSL_IOMMU_CONTEXT_USER]; |
| 1598 | struct kgsl_device *device = KGSL_MMU_DEVICE(mmu); |
| 1599 | struct adreno_device *adreno_dev = ADRENO_DEVICE(device); |
| 1600 | struct kgsl_iommu_pt *iommu_pt = NULL; |
| 1601 | unsigned int sctlr_val; |
| 1602 | |
| 1603 | if (mmu->defaultpagetable == NULL) { |
| 1604 | mmu->defaultpagetable = kgsl_mmu_getpagetable(mmu, |
| 1605 | KGSL_MMU_GLOBAL_PT); |
| 1606 | /* if we don't have a default pagetable, nothing will work */ |
| 1607 | if (IS_ERR(mmu->defaultpagetable)) { |
| 1608 | ret = PTR_ERR(mmu->defaultpagetable); |
| 1609 | mmu->defaultpagetable = NULL; |
| 1610 | return ret; |
Lynus Vaz | a2e3111 | 2017-04-17 18:29:58 +0530 | [diff] [blame^] | 1611 | } else if (mmu->defaultpagetable == NULL) { |
| 1612 | return -ENOMEM; |
Shrenuj Bansal | a419c79 | 2016-10-20 14:05:11 -0700 | [diff] [blame] | 1613 | } |
| 1614 | } |
| 1615 | |
| 1616 | iommu_pt = mmu->defaultpagetable->priv; |
| 1617 | if (iommu_pt == NULL) |
| 1618 | return -ENODEV; |
| 1619 | |
| 1620 | ret = _attach_pt(iommu_pt, ctx); |
| 1621 | if (ret) |
| 1622 | return ret; |
| 1623 | |
| 1624 | ctx->default_pt = mmu->defaultpagetable; |
| 1625 | |
| 1626 | kgsl_iommu_enable_clk(mmu); |
| 1627 | |
| 1628 | sctlr_val = KGSL_IOMMU_GET_CTX_REG(ctx, SCTLR); |
| 1629 | |
| 1630 | /* |
| 1631 | * If pagefault policy is GPUHALT_ENABLE, |
| 1632 | * 1) Program CFCFG to 1 to enable STALL mode |
| 1633 | * 2) Program HUPCF to 0 (Stall or terminate subsequent |
| 1634 | * transactions in the presence of an outstanding fault) |
| 1635 | * else |
| 1636 | * 1) Program CFCFG to 0 to disable STALL mode (0=Terminate) |
| 1637 | * 2) Program HUPCF to 1 (Process subsequent transactions |
| 1638 | * independently of any outstanding fault) |
| 1639 | */ |
| 1640 | |
| 1641 | if (test_bit(KGSL_FT_PAGEFAULT_GPUHALT_ENABLE, |
| 1642 | &adreno_dev->ft_pf_policy)) { |
| 1643 | sctlr_val |= (0x1 << KGSL_IOMMU_SCTLR_CFCFG_SHIFT); |
| 1644 | sctlr_val &= ~(0x1 << KGSL_IOMMU_SCTLR_HUPCF_SHIFT); |
| 1645 | } else { |
| 1646 | sctlr_val &= ~(0x1 << KGSL_IOMMU_SCTLR_CFCFG_SHIFT); |
| 1647 | sctlr_val |= (0x1 << KGSL_IOMMU_SCTLR_HUPCF_SHIFT); |
| 1648 | } |
| 1649 | KGSL_IOMMU_SET_CTX_REG(ctx, SCTLR, sctlr_val); |
| 1650 | kgsl_iommu_disable_clk(mmu); |
| 1651 | |
| 1652 | return 0; |
| 1653 | } |
| 1654 | |
| 1655 | static int _setup_secure_context(struct kgsl_mmu *mmu) |
| 1656 | { |
| 1657 | int ret; |
| 1658 | struct kgsl_iommu *iommu = _IOMMU_PRIV(mmu); |
| 1659 | struct kgsl_iommu_context *ctx = &iommu->ctx[KGSL_IOMMU_CONTEXT_SECURE]; |
| 1660 | unsigned int cb_num; |
| 1661 | |
| 1662 | struct kgsl_iommu_pt *iommu_pt; |
| 1663 | |
| 1664 | if (ctx->dev == NULL || !mmu->secured) |
| 1665 | return 0; |
| 1666 | |
| 1667 | if (mmu->securepagetable == NULL) { |
| 1668 | mmu->securepagetable = kgsl_mmu_getpagetable(mmu, |
| 1669 | KGSL_MMU_SECURE_PT); |
| 1670 | if (IS_ERR(mmu->securepagetable)) { |
| 1671 | ret = PTR_ERR(mmu->securepagetable); |
| 1672 | mmu->securepagetable = NULL; |
| 1673 | return ret; |
| 1674 | } else if (mmu->securepagetable == NULL) { |
| 1675 | return -ENOMEM; |
| 1676 | } |
| 1677 | } |
| 1678 | iommu_pt = mmu->securepagetable->priv; |
| 1679 | |
| 1680 | ret = _attach_pt(iommu_pt, ctx); |
| 1681 | if (ret) |
| 1682 | goto done; |
| 1683 | |
| 1684 | ctx->default_pt = mmu->securepagetable; |
| 1685 | |
| 1686 | ret = iommu_domain_get_attr(iommu_pt->domain, DOMAIN_ATTR_CONTEXT_BANK, |
| 1687 | &cb_num); |
| 1688 | if (ret) { |
| 1689 | KGSL_CORE_ERR("get CONTEXT_BANK attr, err %d\n", ret); |
| 1690 | goto done; |
| 1691 | } |
| 1692 | ctx->cb_num = cb_num; |
| 1693 | done: |
| 1694 | if (ret) |
| 1695 | _detach_context(ctx); |
| 1696 | return ret; |
| 1697 | } |
| 1698 | |
| 1699 | static int kgsl_iommu_set_pt(struct kgsl_mmu *mmu, struct kgsl_pagetable *pt); |
| 1700 | |
| 1701 | static int kgsl_iommu_start(struct kgsl_mmu *mmu) |
| 1702 | { |
| 1703 | int status; |
| 1704 | struct kgsl_iommu *iommu = _IOMMU_PRIV(mmu); |
| 1705 | |
| 1706 | status = _setup_user_context(mmu); |
| 1707 | if (status) |
| 1708 | return status; |
| 1709 | |
| 1710 | status = _setup_secure_context(mmu); |
| 1711 | if (status) { |
| 1712 | _detach_context(&iommu->ctx[KGSL_IOMMU_CONTEXT_USER]); |
| 1713 | return status; |
| 1714 | } |
| 1715 | |
| 1716 | /* Make sure the hardware is programmed to the default pagetable */ |
| 1717 | return kgsl_iommu_set_pt(mmu, mmu->defaultpagetable); |
| 1718 | } |
| 1719 | |
| 1720 | static int |
| 1721 | kgsl_iommu_unmap_offset(struct kgsl_pagetable *pt, |
| 1722 | struct kgsl_memdesc *memdesc, uint64_t addr, |
| 1723 | uint64_t offset, uint64_t size) |
| 1724 | { |
| 1725 | if (size == 0 || (size + offset) > kgsl_memdesc_footprint(memdesc)) |
| 1726 | return -EINVAL; |
| 1727 | /* |
| 1728 | * All GPU addresses as assigned are page aligned, but some |
| 1729 | * functions perturb the gpuaddr with an offset, so apply the |
| 1730 | * mask here to make sure we have the right address. |
| 1731 | */ |
| 1732 | |
| 1733 | addr = PAGE_ALIGN(addr); |
| 1734 | if (addr == 0) |
| 1735 | return -EINVAL; |
| 1736 | |
| 1737 | return _iommu_unmap_sync_pc(pt, memdesc, addr + offset, size); |
| 1738 | } |
| 1739 | |
| 1740 | static int |
| 1741 | kgsl_iommu_unmap(struct kgsl_pagetable *pt, struct kgsl_memdesc *memdesc) |
| 1742 | { |
| 1743 | if (memdesc->size == 0 || memdesc->gpuaddr == 0) |
| 1744 | return -EINVAL; |
| 1745 | |
| 1746 | return kgsl_iommu_unmap_offset(pt, memdesc, memdesc->gpuaddr, 0, |
| 1747 | kgsl_memdesc_footprint(memdesc)); |
| 1748 | } |
| 1749 | |
| 1750 | /** |
| 1751 | * _iommu_map_guard_page - Map iommu guard page |
| 1752 | * @pt - Pointer to kgsl pagetable structure |
| 1753 | * @memdesc - memdesc to add guard page |
| 1754 | * @gpuaddr - GPU addr of guard page |
| 1755 | * @protflags - flags for mapping |
| 1756 | * |
| 1757 | * Return 0 on success, error on map fail |
| 1758 | */ |
| 1759 | static int _iommu_map_guard_page(struct kgsl_pagetable *pt, |
| 1760 | struct kgsl_memdesc *memdesc, |
| 1761 | uint64_t gpuaddr, |
| 1762 | unsigned int protflags) |
| 1763 | { |
| 1764 | phys_addr_t physaddr; |
| 1765 | |
| 1766 | if (!kgsl_memdesc_has_guard_page(memdesc)) |
| 1767 | return 0; |
| 1768 | |
| 1769 | /* |
| 1770 | * Allocate guard page for secure buffers. |
| 1771 | * This has to be done after we attach a smmu pagetable. |
| 1772 | * Allocate the guard page when first secure buffer is. |
| 1773 | * mapped to save 1MB of memory if CPZ is not used. |
| 1774 | */ |
| 1775 | if (kgsl_memdesc_is_secured(memdesc)) { |
| 1776 | struct scatterlist *sg; |
| 1777 | unsigned int sgp_size = pt->mmu->secure_align_mask + 1; |
| 1778 | |
| 1779 | if (!kgsl_secure_guard_page_memdesc.sgt) { |
| 1780 | if (kgsl_allocate_user(KGSL_MMU_DEVICE(pt->mmu), |
| 1781 | &kgsl_secure_guard_page_memdesc, |
| 1782 | sgp_size, KGSL_MEMFLAGS_SECURE)) { |
| 1783 | KGSL_CORE_ERR( |
| 1784 | "Secure guard page alloc failed\n"); |
| 1785 | return -ENOMEM; |
| 1786 | } |
| 1787 | } |
| 1788 | |
| 1789 | sg = kgsl_secure_guard_page_memdesc.sgt->sgl; |
| 1790 | physaddr = page_to_phys(sg_page(sg)); |
| 1791 | } else { |
| 1792 | if (kgsl_guard_page == NULL) { |
| 1793 | kgsl_guard_page = alloc_page(GFP_KERNEL | __GFP_ZERO | |
| 1794 | __GFP_NORETRY | __GFP_HIGHMEM); |
| 1795 | if (kgsl_guard_page == NULL) |
| 1796 | return -ENOMEM; |
| 1797 | } |
| 1798 | |
| 1799 | physaddr = page_to_phys(kgsl_guard_page); |
| 1800 | } |
| 1801 | |
| 1802 | return _iommu_map_sync_pc(pt, memdesc, gpuaddr, physaddr, |
| 1803 | kgsl_memdesc_guard_page_size(memdesc), |
| 1804 | protflags & ~IOMMU_WRITE); |
| 1805 | } |
| 1806 | |
| 1807 | static unsigned int _get_protection_flags(struct kgsl_memdesc *memdesc) |
| 1808 | { |
Sushmita Susheelendra | 7f66cf7 | 2016-09-12 11:04:43 -0600 | [diff] [blame] | 1809 | unsigned int flags = IOMMU_READ | IOMMU_WRITE | |
| 1810 | IOMMU_NOEXEC | IOMMU_USE_UPSTREAM_HINT; |
Shrenuj Bansal | a419c79 | 2016-10-20 14:05:11 -0700 | [diff] [blame] | 1811 | |
| 1812 | if (memdesc->flags & KGSL_MEMFLAGS_GPUREADONLY) |
| 1813 | flags &= ~IOMMU_WRITE; |
| 1814 | |
| 1815 | if (memdesc->priv & KGSL_MEMDESC_PRIVILEGED) |
| 1816 | flags |= IOMMU_PRIV; |
| 1817 | |
| 1818 | return flags; |
| 1819 | } |
| 1820 | |
| 1821 | static int |
| 1822 | kgsl_iommu_map(struct kgsl_pagetable *pt, |
| 1823 | struct kgsl_memdesc *memdesc) |
| 1824 | { |
| 1825 | int ret; |
| 1826 | uint64_t addr = memdesc->gpuaddr; |
| 1827 | uint64_t size = memdesc->size; |
| 1828 | unsigned int flags = _get_protection_flags(memdesc); |
| 1829 | struct sg_table *sgt = NULL; |
| 1830 | |
| 1831 | /* |
| 1832 | * For paged memory allocated through kgsl, memdesc->pages is not NULL. |
| 1833 | * Allocate sgt here just for its map operation. Contiguous memory |
| 1834 | * already has its sgt, so no need to allocate it here. |
| 1835 | */ |
| 1836 | if (memdesc->pages != NULL) |
| 1837 | sgt = kgsl_alloc_sgt_from_pages(memdesc); |
| 1838 | else |
| 1839 | sgt = memdesc->sgt; |
| 1840 | |
| 1841 | if (IS_ERR(sgt)) |
| 1842 | return PTR_ERR(sgt); |
| 1843 | |
| 1844 | ret = _iommu_map_sg_sync_pc(pt, addr, memdesc, sgt->sgl, |
| 1845 | sgt->nents, flags); |
| 1846 | if (ret) |
| 1847 | goto done; |
| 1848 | |
| 1849 | ret = _iommu_map_guard_page(pt, memdesc, addr + size, flags); |
| 1850 | if (ret) |
| 1851 | _iommu_unmap_sync_pc(pt, memdesc, addr, size); |
| 1852 | |
| 1853 | done: |
| 1854 | if (memdesc->pages != NULL) |
| 1855 | kgsl_free_sgt(sgt); |
| 1856 | |
| 1857 | return ret; |
| 1858 | } |
| 1859 | |
| 1860 | static int kgsl_iommu_sparse_dummy_map(struct kgsl_pagetable *pt, |
| 1861 | struct kgsl_memdesc *memdesc, uint64_t offset, uint64_t size) |
| 1862 | { |
| 1863 | int ret = 0, i; |
| 1864 | struct page **pages = NULL; |
| 1865 | struct sg_table sgt; |
| 1866 | int count = size >> PAGE_SHIFT; |
| 1867 | |
| 1868 | /* verify the offset is within our range */ |
| 1869 | if (size + offset > memdesc->size) |
| 1870 | return -EINVAL; |
| 1871 | |
| 1872 | if (kgsl_dummy_page == NULL) { |
| 1873 | kgsl_dummy_page = alloc_page(GFP_KERNEL | __GFP_ZERO | |
| 1874 | __GFP_HIGHMEM); |
| 1875 | if (kgsl_dummy_page == NULL) |
| 1876 | return -ENOMEM; |
| 1877 | } |
| 1878 | |
| 1879 | pages = kcalloc(count, sizeof(struct page *), GFP_KERNEL); |
| 1880 | if (pages == NULL) |
| 1881 | return -ENOMEM; |
| 1882 | |
| 1883 | for (i = 0; i < count; i++) |
| 1884 | pages[i] = kgsl_dummy_page; |
| 1885 | |
| 1886 | ret = sg_alloc_table_from_pages(&sgt, pages, count, |
| 1887 | 0, size, GFP_KERNEL); |
| 1888 | if (ret == 0) { |
| 1889 | ret = _iommu_map_sg_sync_pc(pt, memdesc->gpuaddr + offset, |
| 1890 | memdesc, sgt.sgl, sgt.nents, |
| 1891 | IOMMU_READ | IOMMU_NOEXEC); |
| 1892 | sg_free_table(&sgt); |
| 1893 | } |
| 1894 | |
| 1895 | kfree(pages); |
| 1896 | |
| 1897 | return ret; |
| 1898 | } |
| 1899 | |
| 1900 | static int _map_to_one_page(struct kgsl_pagetable *pt, uint64_t addr, |
| 1901 | struct kgsl_memdesc *memdesc, uint64_t physoffset, |
| 1902 | uint64_t size, unsigned int map_flags) |
| 1903 | { |
| 1904 | int ret = 0, i; |
| 1905 | int pg_sz = kgsl_memdesc_get_pagesize(memdesc); |
| 1906 | int count = size >> PAGE_SHIFT; |
| 1907 | struct page *page = NULL; |
| 1908 | struct page **pages = NULL; |
| 1909 | struct sg_page_iter sg_iter; |
| 1910 | struct sg_table sgt; |
| 1911 | |
| 1912 | /* Find our physaddr offset addr */ |
| 1913 | if (memdesc->pages != NULL) |
| 1914 | page = memdesc->pages[physoffset >> PAGE_SHIFT]; |
| 1915 | else { |
| 1916 | for_each_sg_page(memdesc->sgt->sgl, &sg_iter, |
| 1917 | memdesc->sgt->nents, physoffset >> PAGE_SHIFT) { |
| 1918 | page = sg_page_iter_page(&sg_iter); |
| 1919 | break; |
| 1920 | } |
| 1921 | } |
| 1922 | |
| 1923 | if (page == NULL) |
| 1924 | return -EINVAL; |
| 1925 | |
| 1926 | pages = kcalloc(count, sizeof(struct page *), GFP_KERNEL); |
| 1927 | if (pages == NULL) |
| 1928 | return -ENOMEM; |
| 1929 | |
| 1930 | for (i = 0; i < count; i++) { |
| 1931 | if (pg_sz != PAGE_SIZE) { |
| 1932 | struct page *tmp_page = page; |
| 1933 | int j; |
| 1934 | |
| 1935 | for (j = 0; j < 16; j++, tmp_page += PAGE_SIZE) |
| 1936 | pages[i++] = tmp_page; |
| 1937 | } else |
| 1938 | pages[i] = page; |
| 1939 | } |
| 1940 | |
| 1941 | ret = sg_alloc_table_from_pages(&sgt, pages, count, |
| 1942 | 0, size, GFP_KERNEL); |
| 1943 | if (ret == 0) { |
| 1944 | ret = _iommu_map_sg_sync_pc(pt, addr, memdesc, sgt.sgl, |
| 1945 | sgt.nents, map_flags); |
| 1946 | sg_free_table(&sgt); |
| 1947 | } |
| 1948 | |
| 1949 | kfree(pages); |
| 1950 | |
| 1951 | return ret; |
| 1952 | } |
| 1953 | |
| 1954 | static int kgsl_iommu_map_offset(struct kgsl_pagetable *pt, |
| 1955 | uint64_t virtaddr, uint64_t virtoffset, |
| 1956 | struct kgsl_memdesc *memdesc, uint64_t physoffset, |
| 1957 | uint64_t size, uint64_t feature_flag) |
| 1958 | { |
| 1959 | int pg_sz; |
| 1960 | unsigned int protflags = _get_protection_flags(memdesc); |
| 1961 | int ret; |
| 1962 | struct sg_table *sgt = NULL; |
| 1963 | |
| 1964 | pg_sz = kgsl_memdesc_get_pagesize(memdesc); |
| 1965 | if (!IS_ALIGNED(virtaddr | virtoffset | physoffset | size, pg_sz)) |
| 1966 | return -EINVAL; |
| 1967 | |
| 1968 | if (size == 0) |
| 1969 | return -EINVAL; |
| 1970 | |
| 1971 | if (!(feature_flag & KGSL_SPARSE_BIND_MULTIPLE_TO_PHYS) && |
| 1972 | size + physoffset > kgsl_memdesc_footprint(memdesc)) |
| 1973 | return -EINVAL; |
| 1974 | |
| 1975 | /* |
| 1976 | * For paged memory allocated through kgsl, memdesc->pages is not NULL. |
| 1977 | * Allocate sgt here just for its map operation. Contiguous memory |
| 1978 | * already has its sgt, so no need to allocate it here. |
| 1979 | */ |
| 1980 | if (memdesc->pages != NULL) |
| 1981 | sgt = kgsl_alloc_sgt_from_pages(memdesc); |
| 1982 | else |
| 1983 | sgt = memdesc->sgt; |
| 1984 | |
| 1985 | if (IS_ERR(sgt)) |
| 1986 | return PTR_ERR(sgt); |
| 1987 | |
| 1988 | if (feature_flag & KGSL_SPARSE_BIND_MULTIPLE_TO_PHYS) |
| 1989 | ret = _map_to_one_page(pt, virtaddr + virtoffset, |
| 1990 | memdesc, physoffset, size, protflags); |
| 1991 | else |
| 1992 | ret = _iommu_map_sg_offset_sync_pc(pt, virtaddr + virtoffset, |
| 1993 | memdesc, sgt->sgl, sgt->nents, |
| 1994 | physoffset, size, protflags); |
| 1995 | |
| 1996 | if (memdesc->pages != NULL) |
| 1997 | kgsl_free_sgt(sgt); |
| 1998 | |
| 1999 | return ret; |
| 2000 | } |
| 2001 | |
| 2002 | /* This function must be called with context bank attached */ |
| 2003 | static void kgsl_iommu_clear_fsr(struct kgsl_mmu *mmu) |
| 2004 | { |
| 2005 | struct kgsl_iommu *iommu = _IOMMU_PRIV(mmu); |
| 2006 | struct kgsl_iommu_context *ctx = &iommu->ctx[KGSL_IOMMU_CONTEXT_USER]; |
| 2007 | unsigned int sctlr_val; |
| 2008 | |
| 2009 | if (ctx->default_pt != NULL) { |
| 2010 | kgsl_iommu_enable_clk(mmu); |
| 2011 | KGSL_IOMMU_SET_CTX_REG(ctx, FSR, 0xffffffff); |
| 2012 | /* |
| 2013 | * Re-enable context fault interrupts after clearing |
| 2014 | * FSR to prevent the interrupt from firing repeatedly |
| 2015 | */ |
| 2016 | sctlr_val = KGSL_IOMMU_GET_CTX_REG(ctx, SCTLR); |
| 2017 | sctlr_val |= (0x1 << KGSL_IOMMU_SCTLR_CFIE_SHIFT); |
| 2018 | KGSL_IOMMU_SET_CTX_REG(ctx, SCTLR, sctlr_val); |
| 2019 | /* |
| 2020 | * Make sure the above register writes |
| 2021 | * are not reordered across the barrier |
| 2022 | * as we use writel_relaxed to write them |
| 2023 | */ |
| 2024 | wmb(); |
| 2025 | kgsl_iommu_disable_clk(mmu); |
| 2026 | } |
| 2027 | } |
| 2028 | |
| 2029 | static void kgsl_iommu_pagefault_resume(struct kgsl_mmu *mmu) |
| 2030 | { |
| 2031 | struct kgsl_iommu *iommu = _IOMMU_PRIV(mmu); |
| 2032 | struct kgsl_iommu_context *ctx = &iommu->ctx[KGSL_IOMMU_CONTEXT_USER]; |
| 2033 | |
| 2034 | if (ctx->default_pt != NULL && ctx->fault) { |
| 2035 | /* |
| 2036 | * Write 1 to RESUME.TnR to terminate the |
| 2037 | * stalled transaction. |
| 2038 | */ |
| 2039 | KGSL_IOMMU_SET_CTX_REG(ctx, RESUME, 1); |
| 2040 | /* |
| 2041 | * Make sure the above register writes |
| 2042 | * are not reordered across the barrier |
| 2043 | * as we use writel_relaxed to write them |
| 2044 | */ |
| 2045 | wmb(); |
| 2046 | ctx->fault = 0; |
| 2047 | } |
| 2048 | } |
| 2049 | |
| 2050 | static void kgsl_iommu_stop(struct kgsl_mmu *mmu) |
| 2051 | { |
| 2052 | struct kgsl_iommu *iommu = _IOMMU_PRIV(mmu); |
| 2053 | int i; |
| 2054 | |
| 2055 | /* |
| 2056 | * If the iommu supports retention, we don't need |
| 2057 | * to detach when stopping. |
| 2058 | */ |
| 2059 | if (!MMU_FEATURE(mmu, KGSL_MMU_RETENTION)) { |
| 2060 | for (i = 0; i < KGSL_IOMMU_CONTEXT_MAX; i++) |
| 2061 | _detach_context(&iommu->ctx[i]); |
| 2062 | } |
| 2063 | } |
| 2064 | |
| 2065 | static u64 |
| 2066 | kgsl_iommu_get_current_ttbr0(struct kgsl_mmu *mmu) |
| 2067 | { |
| 2068 | u64 val; |
| 2069 | struct kgsl_iommu *iommu = _IOMMU_PRIV(mmu); |
| 2070 | /* |
| 2071 | * We cannot enable or disable the clocks in interrupt context, this |
| 2072 | * function is called from interrupt context if there is an axi error |
| 2073 | */ |
| 2074 | if (in_interrupt()) |
| 2075 | return 0; |
| 2076 | |
| 2077 | kgsl_iommu_enable_clk(mmu); |
| 2078 | val = KGSL_IOMMU_GET_CTX_REG_Q(&iommu->ctx[KGSL_IOMMU_CONTEXT_USER], |
| 2079 | TTBR0); |
| 2080 | kgsl_iommu_disable_clk(mmu); |
| 2081 | return val; |
| 2082 | } |
| 2083 | |
| 2084 | /* |
| 2085 | * kgsl_iommu_set_pt - Change the IOMMU pagetable of the primary context bank |
| 2086 | * @mmu - Pointer to mmu structure |
| 2087 | * @pt - Pagetable to switch to |
| 2088 | * |
| 2089 | * Set the new pagetable for the IOMMU by doing direct register writes |
| 2090 | * to the IOMMU registers through the cpu |
| 2091 | * |
| 2092 | * Return - void |
| 2093 | */ |
| 2094 | static int kgsl_iommu_set_pt(struct kgsl_mmu *mmu, struct kgsl_pagetable *pt) |
| 2095 | { |
| 2096 | struct kgsl_iommu *iommu = _IOMMU_PRIV(mmu); |
| 2097 | struct kgsl_iommu_context *ctx = &iommu->ctx[KGSL_IOMMU_CONTEXT_USER]; |
| 2098 | uint64_t ttbr0, temp; |
| 2099 | unsigned int contextidr; |
| 2100 | unsigned long wait_for_flush; |
| 2101 | |
| 2102 | if ((pt != mmu->defaultpagetable) && !kgsl_mmu_is_perprocess(mmu)) |
| 2103 | return 0; |
| 2104 | |
| 2105 | kgsl_iommu_enable_clk(mmu); |
| 2106 | |
| 2107 | ttbr0 = kgsl_mmu_pagetable_get_ttbr0(pt); |
| 2108 | contextidr = kgsl_mmu_pagetable_get_contextidr(pt); |
| 2109 | |
| 2110 | KGSL_IOMMU_SET_CTX_REG_Q(ctx, TTBR0, ttbr0); |
| 2111 | KGSL_IOMMU_SET_CTX_REG(ctx, CONTEXTIDR, contextidr); |
| 2112 | |
| 2113 | /* memory barrier before reading TTBR0 register */ |
| 2114 | mb(); |
| 2115 | temp = KGSL_IOMMU_GET_CTX_REG_Q(ctx, TTBR0); |
| 2116 | |
| 2117 | KGSL_IOMMU_SET_CTX_REG(ctx, TLBIALL, 1); |
| 2118 | /* make sure the TBLI write completes before we wait */ |
| 2119 | mb(); |
| 2120 | /* |
| 2121 | * Wait for flush to complete by polling the flush |
| 2122 | * status bit of TLBSTATUS register for not more than |
| 2123 | * 2 s. After 2s just exit, at that point the SMMU h/w |
| 2124 | * may be stuck and will eventually cause GPU to hang |
| 2125 | * or bring the system down. |
| 2126 | */ |
| 2127 | wait_for_flush = jiffies + msecs_to_jiffies(2000); |
| 2128 | KGSL_IOMMU_SET_CTX_REG(ctx, TLBSYNC, 0); |
| 2129 | while (KGSL_IOMMU_GET_CTX_REG(ctx, TLBSTATUS) & |
| 2130 | (KGSL_IOMMU_CTX_TLBSTATUS_SACTIVE)) { |
| 2131 | if (time_after(jiffies, wait_for_flush)) { |
| 2132 | KGSL_DRV_WARN(KGSL_MMU_DEVICE(mmu), |
| 2133 | "Wait limit reached for IOMMU tlb flush\n"); |
| 2134 | break; |
| 2135 | } |
| 2136 | cpu_relax(); |
| 2137 | } |
| 2138 | |
| 2139 | kgsl_iommu_disable_clk(mmu); |
| 2140 | return 0; |
| 2141 | } |
| 2142 | |
| 2143 | /* |
| 2144 | * kgsl_iommu_set_pf_policy() - Set the pagefault policy for IOMMU |
| 2145 | * @mmu: Pointer to mmu structure |
| 2146 | * @pf_policy: The pagefault polict to set |
| 2147 | * |
| 2148 | * Check if the new policy indicated by pf_policy is same as current |
| 2149 | * policy, if same then return else set the policy |
| 2150 | */ |
| 2151 | static int kgsl_iommu_set_pf_policy(struct kgsl_mmu *mmu, |
| 2152 | unsigned long pf_policy) |
| 2153 | { |
| 2154 | struct kgsl_iommu *iommu = _IOMMU_PRIV(mmu); |
| 2155 | struct kgsl_iommu_context *ctx = &iommu->ctx[KGSL_IOMMU_CONTEXT_USER]; |
| 2156 | struct kgsl_device *device = KGSL_MMU_DEVICE(mmu); |
| 2157 | struct adreno_device *adreno_dev = ADRENO_DEVICE(device); |
| 2158 | |
| 2159 | if ((adreno_dev->ft_pf_policy & |
| 2160 | BIT(KGSL_FT_PAGEFAULT_GPUHALT_ENABLE)) == |
| 2161 | (pf_policy & BIT(KGSL_FT_PAGEFAULT_GPUHALT_ENABLE))) |
| 2162 | return 0; |
| 2163 | |
| 2164 | /* If not attached, policy will be updated during the next attach */ |
| 2165 | if (ctx->default_pt != NULL) { |
| 2166 | unsigned int sctlr_val; |
| 2167 | |
| 2168 | kgsl_iommu_enable_clk(mmu); |
| 2169 | |
| 2170 | sctlr_val = KGSL_IOMMU_GET_CTX_REG(ctx, SCTLR); |
| 2171 | |
| 2172 | if (test_bit(KGSL_FT_PAGEFAULT_GPUHALT_ENABLE, &pf_policy)) { |
| 2173 | sctlr_val |= (0x1 << KGSL_IOMMU_SCTLR_CFCFG_SHIFT); |
| 2174 | sctlr_val &= ~(0x1 << KGSL_IOMMU_SCTLR_HUPCF_SHIFT); |
| 2175 | } else { |
| 2176 | sctlr_val &= ~(0x1 << KGSL_IOMMU_SCTLR_CFCFG_SHIFT); |
| 2177 | sctlr_val |= (0x1 << KGSL_IOMMU_SCTLR_HUPCF_SHIFT); |
| 2178 | } |
| 2179 | |
| 2180 | KGSL_IOMMU_SET_CTX_REG(ctx, SCTLR, sctlr_val); |
| 2181 | |
| 2182 | kgsl_iommu_disable_clk(mmu); |
| 2183 | } |
| 2184 | |
| 2185 | return 0; |
| 2186 | } |
| 2187 | |
| 2188 | static struct kgsl_protected_registers * |
| 2189 | kgsl_iommu_get_prot_regs(struct kgsl_mmu *mmu) |
| 2190 | { |
| 2191 | struct kgsl_iommu *iommu = _IOMMU_PRIV(mmu); |
| 2192 | |
| 2193 | return &iommu->protect; |
| 2194 | } |
| 2195 | |
| 2196 | static struct kgsl_iommu_addr_entry *_find_gpuaddr( |
| 2197 | struct kgsl_pagetable *pagetable, uint64_t gpuaddr) |
| 2198 | { |
| 2199 | struct kgsl_iommu_pt *pt = pagetable->priv; |
| 2200 | struct rb_node *node = pt->rbtree.rb_node; |
| 2201 | |
| 2202 | while (node != NULL) { |
| 2203 | struct kgsl_iommu_addr_entry *entry = rb_entry(node, |
| 2204 | struct kgsl_iommu_addr_entry, node); |
| 2205 | |
| 2206 | if (gpuaddr < entry->base) |
| 2207 | node = node->rb_left; |
| 2208 | else if (gpuaddr > entry->base) |
| 2209 | node = node->rb_right; |
| 2210 | else |
| 2211 | return entry; |
| 2212 | } |
| 2213 | |
| 2214 | return NULL; |
| 2215 | } |
| 2216 | |
| 2217 | static int _remove_gpuaddr(struct kgsl_pagetable *pagetable, |
| 2218 | uint64_t gpuaddr) |
| 2219 | { |
| 2220 | struct kgsl_iommu_pt *pt = pagetable->priv; |
| 2221 | struct kgsl_iommu_addr_entry *entry; |
| 2222 | |
| 2223 | entry = _find_gpuaddr(pagetable, gpuaddr); |
| 2224 | |
| 2225 | if (entry != NULL) { |
| 2226 | rb_erase(&entry->node, &pt->rbtree); |
| 2227 | kmem_cache_free(addr_entry_cache, entry); |
| 2228 | return 0; |
| 2229 | } |
| 2230 | |
| 2231 | WARN(1, "Couldn't remove gpuaddr: 0x%llx\n", gpuaddr); |
| 2232 | return -ENOMEM; |
| 2233 | } |
| 2234 | |
| 2235 | static int _insert_gpuaddr(struct kgsl_pagetable *pagetable, |
| 2236 | uint64_t gpuaddr, uint64_t size) |
| 2237 | { |
| 2238 | struct kgsl_iommu_pt *pt = pagetable->priv; |
| 2239 | struct rb_node **node, *parent = NULL; |
| 2240 | struct kgsl_iommu_addr_entry *new = |
| 2241 | kmem_cache_alloc(addr_entry_cache, GFP_ATOMIC); |
| 2242 | |
| 2243 | if (new == NULL) |
| 2244 | return -ENOMEM; |
| 2245 | |
| 2246 | new->base = gpuaddr; |
| 2247 | new->size = size; |
| 2248 | |
| 2249 | node = &pt->rbtree.rb_node; |
| 2250 | |
| 2251 | while (*node != NULL) { |
| 2252 | struct kgsl_iommu_addr_entry *this; |
| 2253 | |
| 2254 | parent = *node; |
| 2255 | this = rb_entry(parent, struct kgsl_iommu_addr_entry, node); |
| 2256 | |
| 2257 | if (new->base < this->base) |
| 2258 | node = &parent->rb_left; |
| 2259 | else if (new->base > this->base) |
| 2260 | node = &parent->rb_right; |
| 2261 | else { |
| 2262 | /* Duplicate entry */ |
| 2263 | WARN(1, "duplicate gpuaddr: 0x%llx\n", gpuaddr); |
| 2264 | return -EEXIST; |
| 2265 | } |
| 2266 | } |
| 2267 | |
| 2268 | rb_link_node(&new->node, parent, node); |
| 2269 | rb_insert_color(&new->node, &pt->rbtree); |
| 2270 | |
| 2271 | return 0; |
| 2272 | } |
| 2273 | |
| 2274 | static uint64_t _get_unmapped_area(struct kgsl_pagetable *pagetable, |
| 2275 | uint64_t bottom, uint64_t top, uint64_t size, |
| 2276 | uint64_t align) |
| 2277 | { |
| 2278 | struct kgsl_iommu_pt *pt = pagetable->priv; |
| 2279 | struct rb_node *node = rb_first(&pt->rbtree); |
| 2280 | uint64_t start; |
| 2281 | |
| 2282 | bottom = ALIGN(bottom, align); |
| 2283 | start = bottom; |
| 2284 | |
| 2285 | while (node != NULL) { |
| 2286 | uint64_t gap; |
| 2287 | struct kgsl_iommu_addr_entry *entry = rb_entry(node, |
| 2288 | struct kgsl_iommu_addr_entry, node); |
| 2289 | |
| 2290 | /* |
| 2291 | * Skip any entries that are outside of the range, but make sure |
| 2292 | * to account for some that might straddle the lower bound |
| 2293 | */ |
| 2294 | if (entry->base < bottom) { |
| 2295 | if (entry->base + entry->size > bottom) |
| 2296 | start = ALIGN(entry->base + entry->size, align); |
| 2297 | node = rb_next(node); |
| 2298 | continue; |
| 2299 | } |
| 2300 | |
| 2301 | /* Stop if we went over the top */ |
| 2302 | if (entry->base >= top) |
| 2303 | break; |
| 2304 | |
| 2305 | /* Make sure there is a gap to consider */ |
| 2306 | if (start < entry->base) { |
| 2307 | gap = entry->base - start; |
| 2308 | |
| 2309 | if (gap >= size) |
| 2310 | return start; |
| 2311 | } |
| 2312 | |
| 2313 | /* Stop if there is no more room in the region */ |
| 2314 | if (entry->base + entry->size >= top) |
| 2315 | return (uint64_t) -ENOMEM; |
| 2316 | |
| 2317 | /* Start the next cycle at the end of the current entry */ |
| 2318 | start = ALIGN(entry->base + entry->size, align); |
| 2319 | node = rb_next(node); |
| 2320 | } |
| 2321 | |
| 2322 | if (start + size <= top) |
| 2323 | return start; |
| 2324 | |
| 2325 | return (uint64_t) -ENOMEM; |
| 2326 | } |
| 2327 | |
| 2328 | static uint64_t _get_unmapped_area_topdown(struct kgsl_pagetable *pagetable, |
| 2329 | uint64_t bottom, uint64_t top, uint64_t size, |
| 2330 | uint64_t align) |
| 2331 | { |
| 2332 | struct kgsl_iommu_pt *pt = pagetable->priv; |
| 2333 | struct rb_node *node = rb_last(&pt->rbtree); |
| 2334 | uint64_t end = top; |
| 2335 | uint64_t mask = ~(align - 1); |
| 2336 | struct kgsl_iommu_addr_entry *entry; |
| 2337 | |
| 2338 | /* Make sure that the bottom is correctly aligned */ |
| 2339 | bottom = ALIGN(bottom, align); |
| 2340 | |
| 2341 | /* Make sure the requested size will fit in the range */ |
| 2342 | if (size > (top - bottom)) |
| 2343 | return -ENOMEM; |
| 2344 | |
| 2345 | /* Walk back through the list to find the highest entry in the range */ |
| 2346 | for (node = rb_last(&pt->rbtree); node != NULL; node = rb_prev(node)) { |
| 2347 | entry = rb_entry(node, struct kgsl_iommu_addr_entry, node); |
| 2348 | if (entry->base < top) |
| 2349 | break; |
| 2350 | } |
| 2351 | |
| 2352 | while (node != NULL) { |
| 2353 | uint64_t offset; |
| 2354 | |
| 2355 | entry = rb_entry(node, struct kgsl_iommu_addr_entry, node); |
| 2356 | |
| 2357 | /* If the entire entry is below the range the search is over */ |
| 2358 | if ((entry->base + entry->size) < bottom) |
| 2359 | break; |
| 2360 | |
| 2361 | /* Get the top of the entry properly aligned */ |
| 2362 | offset = ALIGN(entry->base + entry->size, align); |
| 2363 | |
| 2364 | /* |
| 2365 | * Try to allocate the memory from the top of the gap, |
| 2366 | * making sure that it fits between the top of this entry and |
| 2367 | * the bottom of the previous one |
| 2368 | */ |
| 2369 | |
| 2370 | if ((end > size) && (offset < end)) { |
| 2371 | uint64_t chunk = (end - size) & mask; |
| 2372 | |
| 2373 | if (chunk >= offset) |
| 2374 | return chunk; |
| 2375 | } |
| 2376 | |
| 2377 | /* |
| 2378 | * If we get here and the current entry is outside of the range |
| 2379 | * then we are officially out of room |
| 2380 | */ |
| 2381 | |
| 2382 | if (entry->base < bottom) |
| 2383 | return (uint64_t) -ENOMEM; |
| 2384 | |
| 2385 | /* Set the top of the gap to the current entry->base */ |
| 2386 | end = entry->base; |
| 2387 | |
| 2388 | /* And move on to the next lower entry */ |
| 2389 | node = rb_prev(node); |
| 2390 | } |
| 2391 | |
| 2392 | /* If we get here then there are no more entries in the region */ |
| 2393 | if ((end > size) && (((end - size) & mask) >= bottom)) |
| 2394 | return (end - size) & mask; |
| 2395 | |
| 2396 | return (uint64_t) -ENOMEM; |
| 2397 | } |
| 2398 | |
| 2399 | static uint64_t kgsl_iommu_find_svm_region(struct kgsl_pagetable *pagetable, |
| 2400 | uint64_t start, uint64_t end, uint64_t size, |
| 2401 | uint64_t alignment) |
| 2402 | { |
| 2403 | uint64_t addr; |
| 2404 | |
| 2405 | /* Avoid black holes */ |
| 2406 | if (WARN(end <= start, "Bad search range: 0x%llx-0x%llx", start, end)) |
| 2407 | return (uint64_t) -EINVAL; |
| 2408 | |
| 2409 | spin_lock(&pagetable->lock); |
| 2410 | addr = _get_unmapped_area_topdown(pagetable, |
| 2411 | start, end, size, alignment); |
| 2412 | spin_unlock(&pagetable->lock); |
| 2413 | return addr; |
| 2414 | } |
| 2415 | |
| 2416 | static int kgsl_iommu_set_svm_region(struct kgsl_pagetable *pagetable, |
| 2417 | uint64_t gpuaddr, uint64_t size) |
| 2418 | { |
| 2419 | int ret = -ENOMEM; |
| 2420 | struct kgsl_iommu_pt *pt = pagetable->priv; |
| 2421 | struct rb_node *node; |
| 2422 | |
| 2423 | /* Make sure the requested address doesn't fall in the global range */ |
| 2424 | if (ADDR_IN_GLOBAL(gpuaddr) || ADDR_IN_GLOBAL(gpuaddr + size)) |
| 2425 | return -ENOMEM; |
| 2426 | |
| 2427 | spin_lock(&pagetable->lock); |
| 2428 | node = pt->rbtree.rb_node; |
| 2429 | |
| 2430 | while (node != NULL) { |
| 2431 | uint64_t start, end; |
| 2432 | struct kgsl_iommu_addr_entry *entry = rb_entry(node, |
| 2433 | struct kgsl_iommu_addr_entry, node); |
| 2434 | |
| 2435 | start = entry->base; |
| 2436 | end = entry->base + entry->size; |
| 2437 | |
| 2438 | if (gpuaddr + size <= start) |
| 2439 | node = node->rb_left; |
| 2440 | else if (end <= gpuaddr) |
| 2441 | node = node->rb_right; |
| 2442 | else |
| 2443 | goto out; |
| 2444 | } |
| 2445 | |
| 2446 | ret = _insert_gpuaddr(pagetable, gpuaddr, size); |
| 2447 | out: |
| 2448 | spin_unlock(&pagetable->lock); |
| 2449 | return ret; |
| 2450 | } |
| 2451 | |
| 2452 | |
| 2453 | static int kgsl_iommu_get_gpuaddr(struct kgsl_pagetable *pagetable, |
| 2454 | struct kgsl_memdesc *memdesc) |
| 2455 | { |
| 2456 | struct kgsl_iommu_pt *pt = pagetable->priv; |
| 2457 | int ret = 0; |
| 2458 | uint64_t addr, start, end, size; |
| 2459 | unsigned int align; |
| 2460 | |
| 2461 | if (WARN_ON(kgsl_memdesc_use_cpu_map(memdesc))) |
| 2462 | return -EINVAL; |
| 2463 | |
| 2464 | if (memdesc->flags & KGSL_MEMFLAGS_SECURE && |
| 2465 | pagetable->name != KGSL_MMU_SECURE_PT) |
| 2466 | return -EINVAL; |
| 2467 | |
| 2468 | size = kgsl_memdesc_footprint(memdesc); |
| 2469 | |
| 2470 | align = 1 << kgsl_memdesc_get_align(memdesc); |
| 2471 | |
| 2472 | if (memdesc->flags & KGSL_MEMFLAGS_FORCE_32BIT) { |
| 2473 | start = pt->compat_va_start; |
| 2474 | end = pt->compat_va_end; |
| 2475 | } else { |
| 2476 | start = pt->va_start; |
| 2477 | end = pt->va_end; |
| 2478 | } |
| 2479 | |
| 2480 | spin_lock(&pagetable->lock); |
| 2481 | |
| 2482 | addr = _get_unmapped_area(pagetable, start, end, size, align); |
| 2483 | |
| 2484 | if (addr == (uint64_t) -ENOMEM) { |
| 2485 | ret = -ENOMEM; |
| 2486 | goto out; |
| 2487 | } |
| 2488 | |
| 2489 | ret = _insert_gpuaddr(pagetable, addr, size); |
| 2490 | if (ret == 0) { |
| 2491 | memdesc->gpuaddr = addr; |
| 2492 | memdesc->pagetable = pagetable; |
| 2493 | } |
| 2494 | |
| 2495 | out: |
| 2496 | spin_unlock(&pagetable->lock); |
| 2497 | return ret; |
| 2498 | } |
| 2499 | |
| 2500 | static void kgsl_iommu_put_gpuaddr(struct kgsl_memdesc *memdesc) |
| 2501 | { |
| 2502 | if (memdesc->pagetable == NULL) |
| 2503 | return; |
| 2504 | |
| 2505 | spin_lock(&memdesc->pagetable->lock); |
| 2506 | |
| 2507 | _remove_gpuaddr(memdesc->pagetable, memdesc->gpuaddr); |
| 2508 | |
| 2509 | spin_unlock(&memdesc->pagetable->lock); |
| 2510 | } |
| 2511 | |
| 2512 | static int kgsl_iommu_svm_range(struct kgsl_pagetable *pagetable, |
| 2513 | uint64_t *lo, uint64_t *hi, uint64_t memflags) |
| 2514 | { |
| 2515 | struct kgsl_iommu_pt *pt = pagetable->priv; |
| 2516 | bool gpu_compat = (memflags & KGSL_MEMFLAGS_FORCE_32BIT) != 0; |
| 2517 | |
| 2518 | if (lo != NULL) |
| 2519 | *lo = gpu_compat ? pt->compat_va_start : pt->svm_start; |
| 2520 | if (hi != NULL) |
| 2521 | *hi = gpu_compat ? pt->compat_va_end : pt->svm_end; |
| 2522 | |
| 2523 | return 0; |
| 2524 | } |
| 2525 | |
| 2526 | static bool kgsl_iommu_addr_in_range(struct kgsl_pagetable *pagetable, |
| 2527 | uint64_t gpuaddr) |
| 2528 | { |
| 2529 | struct kgsl_iommu_pt *pt = pagetable->priv; |
| 2530 | |
| 2531 | if (gpuaddr == 0) |
| 2532 | return false; |
| 2533 | |
| 2534 | if (gpuaddr >= pt->va_start && gpuaddr < pt->va_end) |
| 2535 | return true; |
| 2536 | |
| 2537 | if (gpuaddr >= pt->compat_va_start && gpuaddr < pt->compat_va_end) |
| 2538 | return true; |
| 2539 | |
| 2540 | if (gpuaddr >= pt->svm_start && gpuaddr < pt->svm_end) |
| 2541 | return true; |
| 2542 | |
| 2543 | return false; |
| 2544 | } |
| 2545 | |
| 2546 | static const struct { |
| 2547 | int id; |
| 2548 | char *name; |
| 2549 | } kgsl_iommu_cbs[] = { |
| 2550 | { KGSL_IOMMU_CONTEXT_USER, "gfx3d_user", }, |
| 2551 | { KGSL_IOMMU_CONTEXT_SECURE, "gfx3d_secure" }, |
| 2552 | }; |
| 2553 | |
| 2554 | static int _kgsl_iommu_cb_probe(struct kgsl_device *device, |
| 2555 | struct kgsl_iommu *iommu, struct device_node *node) |
| 2556 | { |
| 2557 | struct platform_device *pdev = of_find_device_by_node(node); |
| 2558 | struct kgsl_iommu_context *ctx = NULL; |
| 2559 | int i; |
| 2560 | |
| 2561 | for (i = 0; i < ARRAY_SIZE(kgsl_iommu_cbs); i++) { |
| 2562 | if (!strcmp(node->name, kgsl_iommu_cbs[i].name)) { |
| 2563 | int id = kgsl_iommu_cbs[i].id; |
| 2564 | |
| 2565 | ctx = &iommu->ctx[id]; |
| 2566 | ctx->id = id; |
| 2567 | ctx->cb_num = -1; |
| 2568 | ctx->name = kgsl_iommu_cbs[i].name; |
| 2569 | |
| 2570 | break; |
| 2571 | } |
| 2572 | } |
| 2573 | |
| 2574 | if (ctx == NULL) { |
| 2575 | KGSL_CORE_ERR("dt: Unknown context label %s\n", node->name); |
| 2576 | return -EINVAL; |
| 2577 | } |
| 2578 | |
| 2579 | if (ctx->id == KGSL_IOMMU_CONTEXT_SECURE) |
| 2580 | device->mmu.secured = true; |
| 2581 | |
| 2582 | /* this property won't be found for all context banks */ |
| 2583 | if (of_property_read_u32(node, "qcom,gpu-offset", &ctx->gpu_offset)) |
| 2584 | ctx->gpu_offset = UINT_MAX; |
| 2585 | |
| 2586 | ctx->kgsldev = device; |
| 2587 | |
| 2588 | /* arm-smmu driver we'll have the right device pointer here. */ |
| 2589 | if (of_find_property(node, "iommus", NULL)) { |
| 2590 | ctx->dev = &pdev->dev; |
| 2591 | } else { |
| 2592 | ctx->dev = kgsl_mmu_get_ctx(ctx->name); |
| 2593 | |
| 2594 | if (IS_ERR(ctx->dev)) |
| 2595 | return PTR_ERR(ctx->dev); |
| 2596 | } |
| 2597 | |
| 2598 | return 0; |
| 2599 | } |
| 2600 | |
| 2601 | static const struct { |
| 2602 | char *feature; |
| 2603 | int bit; |
| 2604 | } kgsl_iommu_features[] = { |
| 2605 | { "qcom,retention", KGSL_MMU_RETENTION }, |
| 2606 | { "qcom,global_pt", KGSL_MMU_GLOBAL_PAGETABLE }, |
| 2607 | { "qcom,hyp_secure_alloc", KGSL_MMU_HYP_SECURE_ALLOC }, |
| 2608 | { "qcom,force-32bit", KGSL_MMU_FORCE_32BIT }, |
| 2609 | }; |
| 2610 | |
| 2611 | static int _kgsl_iommu_probe(struct kgsl_device *device, |
| 2612 | struct device_node *node) |
| 2613 | { |
| 2614 | const char *cname; |
| 2615 | struct property *prop; |
| 2616 | u32 reg_val[2]; |
| 2617 | int i = 0; |
| 2618 | struct kgsl_iommu *iommu = KGSL_IOMMU_PRIV(device); |
| 2619 | struct device_node *child; |
| 2620 | struct platform_device *pdev = of_find_device_by_node(node); |
| 2621 | |
| 2622 | memset(iommu, 0, sizeof(*iommu)); |
| 2623 | |
| 2624 | if (of_device_is_compatible(node, "qcom,kgsl-smmu-v1")) |
| 2625 | iommu->version = 1; |
| 2626 | else |
| 2627 | iommu->version = 2; |
| 2628 | |
| 2629 | if (of_property_read_u32_array(node, "reg", reg_val, 2)) { |
| 2630 | KGSL_CORE_ERR("dt: Unable to read KGSL IOMMU register range\n"); |
| 2631 | return -EINVAL; |
| 2632 | } |
| 2633 | iommu->regstart = reg_val[0]; |
| 2634 | iommu->regsize = reg_val[1]; |
| 2635 | |
| 2636 | /* Protecting the SMMU registers is mandatory */ |
| 2637 | if (of_property_read_u32_array(node, "qcom,protect", reg_val, 2)) { |
| 2638 | KGSL_CORE_ERR("dt: no iommu protection range specified\n"); |
| 2639 | return -EINVAL; |
| 2640 | } |
| 2641 | iommu->protect.base = reg_val[0] / sizeof(u32); |
| 2642 | iommu->protect.range = ilog2(reg_val[1] / sizeof(u32)); |
| 2643 | |
| 2644 | of_property_for_each_string(node, "clock-names", prop, cname) { |
| 2645 | struct clk *c = devm_clk_get(&pdev->dev, cname); |
| 2646 | |
| 2647 | if (IS_ERR(c)) { |
| 2648 | KGSL_CORE_ERR("dt: Couldn't get clock: %s\n", cname); |
| 2649 | return -ENODEV; |
| 2650 | } |
| 2651 | if (i >= KGSL_IOMMU_MAX_CLKS) { |
| 2652 | KGSL_CORE_ERR("dt: too many clocks defined.\n"); |
| 2653 | return -EINVAL; |
| 2654 | } |
| 2655 | |
| 2656 | iommu->clks[i] = c; |
| 2657 | ++i; |
| 2658 | } |
| 2659 | |
| 2660 | for (i = 0; i < ARRAY_SIZE(kgsl_iommu_features); i++) { |
| 2661 | if (of_property_read_bool(node, kgsl_iommu_features[i].feature)) |
| 2662 | device->mmu.features |= kgsl_iommu_features[i].bit; |
| 2663 | } |
| 2664 | |
| 2665 | if (of_property_read_u32(node, "qcom,micro-mmu-control", |
| 2666 | &iommu->micro_mmu_ctrl)) |
| 2667 | iommu->micro_mmu_ctrl = UINT_MAX; |
| 2668 | |
| 2669 | if (of_property_read_u32(node, "qcom,secure_align_mask", |
| 2670 | &device->mmu.secure_align_mask)) |
| 2671 | device->mmu.secure_align_mask = 0xfff; |
| 2672 | |
| 2673 | /* Fill out the rest of the devices in the node */ |
| 2674 | of_platform_populate(node, NULL, NULL, &pdev->dev); |
| 2675 | |
| 2676 | for_each_child_of_node(node, child) { |
| 2677 | int ret; |
| 2678 | |
| 2679 | if (!of_device_is_compatible(child, "qcom,smmu-kgsl-cb")) |
| 2680 | continue; |
| 2681 | |
| 2682 | ret = _kgsl_iommu_cb_probe(device, iommu, child); |
| 2683 | if (ret) |
| 2684 | return ret; |
| 2685 | } |
| 2686 | |
| 2687 | return 0; |
| 2688 | } |
| 2689 | |
| 2690 | static const struct { |
| 2691 | char *compat; |
| 2692 | int (*probe)(struct kgsl_device *device, struct device_node *node); |
| 2693 | } kgsl_dt_devices[] = { |
| 2694 | { "qcom,kgsl-smmu-v1", _kgsl_iommu_probe }, |
| 2695 | { "qcom,kgsl-smmu-v2", _kgsl_iommu_probe }, |
| 2696 | }; |
| 2697 | |
| 2698 | static int kgsl_iommu_probe(struct kgsl_device *device) |
| 2699 | { |
| 2700 | int i; |
| 2701 | |
| 2702 | for (i = 0; i < ARRAY_SIZE(kgsl_dt_devices); i++) { |
| 2703 | struct device_node *node; |
| 2704 | |
| 2705 | node = of_find_compatible_node(device->pdev->dev.of_node, |
| 2706 | NULL, kgsl_dt_devices[i].compat); |
| 2707 | |
| 2708 | if (node != NULL) |
| 2709 | return kgsl_dt_devices[i].probe(device, node); |
| 2710 | } |
| 2711 | |
| 2712 | return -ENODEV; |
| 2713 | } |
| 2714 | |
| 2715 | struct kgsl_mmu_ops kgsl_iommu_ops = { |
| 2716 | .mmu_init = kgsl_iommu_init, |
| 2717 | .mmu_close = kgsl_iommu_close, |
| 2718 | .mmu_start = kgsl_iommu_start, |
| 2719 | .mmu_stop = kgsl_iommu_stop, |
| 2720 | .mmu_set_pt = kgsl_iommu_set_pt, |
| 2721 | .mmu_clear_fsr = kgsl_iommu_clear_fsr, |
| 2722 | .mmu_get_current_ttbr0 = kgsl_iommu_get_current_ttbr0, |
| 2723 | .mmu_enable_clk = kgsl_iommu_enable_clk, |
| 2724 | .mmu_disable_clk = kgsl_iommu_disable_clk, |
| 2725 | .mmu_get_reg_ahbaddr = kgsl_iommu_get_reg_ahbaddr, |
| 2726 | .mmu_pt_equal = kgsl_iommu_pt_equal, |
| 2727 | .mmu_set_pf_policy = kgsl_iommu_set_pf_policy, |
| 2728 | .mmu_pagefault_resume = kgsl_iommu_pagefault_resume, |
| 2729 | .mmu_get_prot_regs = kgsl_iommu_get_prot_regs, |
| 2730 | .mmu_init_pt = kgsl_iommu_init_pt, |
| 2731 | .mmu_add_global = kgsl_iommu_add_global, |
| 2732 | .mmu_remove_global = kgsl_iommu_remove_global, |
| 2733 | .mmu_getpagetable = kgsl_iommu_getpagetable, |
| 2734 | .mmu_get_qdss_global_entry = kgsl_iommu_get_qdss_global_entry, |
Jonathan Wicks | 4892d8d | 2017-02-24 16:21:26 -0700 | [diff] [blame] | 2735 | .mmu_get_qtimer_global_entry = kgsl_iommu_get_qtimer_global_entry, |
Shrenuj Bansal | a419c79 | 2016-10-20 14:05:11 -0700 | [diff] [blame] | 2736 | .probe = kgsl_iommu_probe, |
| 2737 | }; |
| 2738 | |
| 2739 | static struct kgsl_mmu_pt_ops iommu_pt_ops = { |
| 2740 | .mmu_map = kgsl_iommu_map, |
| 2741 | .mmu_unmap = kgsl_iommu_unmap, |
| 2742 | .mmu_destroy_pagetable = kgsl_iommu_destroy_pagetable, |
| 2743 | .get_ttbr0 = kgsl_iommu_get_ttbr0, |
| 2744 | .get_contextidr = kgsl_iommu_get_contextidr, |
| 2745 | .get_gpuaddr = kgsl_iommu_get_gpuaddr, |
| 2746 | .put_gpuaddr = kgsl_iommu_put_gpuaddr, |
| 2747 | .set_svm_region = kgsl_iommu_set_svm_region, |
| 2748 | .find_svm_region = kgsl_iommu_find_svm_region, |
| 2749 | .svm_range = kgsl_iommu_svm_range, |
| 2750 | .addr_in_range = kgsl_iommu_addr_in_range, |
| 2751 | .mmu_map_offset = kgsl_iommu_map_offset, |
| 2752 | .mmu_unmap_offset = kgsl_iommu_unmap_offset, |
| 2753 | .mmu_sparse_dummy_map = kgsl_iommu_sparse_dummy_map, |
| 2754 | }; |