Ingo Molnar | 241771e | 2008-12-03 10:39:53 +0100 | [diff] [blame] | 1 | /* |
| 2 | * Performance counter x86 architecture code |
| 3 | * |
Ingo Molnar | 9814451 | 2009-04-29 14:52:50 +0200 | [diff] [blame] | 4 | * Copyright (C) 2008 Thomas Gleixner <tglx@linutronix.de> |
| 5 | * Copyright (C) 2008-2009 Red Hat, Inc., Ingo Molnar |
| 6 | * Copyright (C) 2009 Jaswinder Singh Rajput |
| 7 | * Copyright (C) 2009 Advanced Micro Devices, Inc., Robert Richter |
| 8 | * Copyright (C) 2008-2009 Red Hat, Inc., Peter Zijlstra <pzijlstr@redhat.com> |
Ingo Molnar | 241771e | 2008-12-03 10:39:53 +0100 | [diff] [blame] | 9 | * |
| 10 | * For licencing details see kernel-base/COPYING |
| 11 | */ |
| 12 | |
| 13 | #include <linux/perf_counter.h> |
| 14 | #include <linux/capability.h> |
| 15 | #include <linux/notifier.h> |
| 16 | #include <linux/hardirq.h> |
| 17 | #include <linux/kprobes.h> |
Thomas Gleixner | 4ac1329 | 2008-12-09 21:43:39 +0100 | [diff] [blame] | 18 | #include <linux/module.h> |
Ingo Molnar | 241771e | 2008-12-03 10:39:53 +0100 | [diff] [blame] | 19 | #include <linux/kdebug.h> |
| 20 | #include <linux/sched.h> |
Peter Zijlstra | d7d59fb | 2009-03-30 19:07:15 +0200 | [diff] [blame] | 21 | #include <linux/uaccess.h> |
Ingo Molnar | 241771e | 2008-12-03 10:39:53 +0100 | [diff] [blame] | 22 | |
Ingo Molnar | 241771e | 2008-12-03 10:39:53 +0100 | [diff] [blame] | 23 | #include <asm/apic.h> |
Peter Zijlstra | d7d59fb | 2009-03-30 19:07:15 +0200 | [diff] [blame] | 24 | #include <asm/stacktrace.h> |
Peter Zijlstra | 4e935e4 | 2009-03-30 19:07:16 +0200 | [diff] [blame] | 25 | #include <asm/nmi.h> |
Ingo Molnar | 241771e | 2008-12-03 10:39:53 +0100 | [diff] [blame] | 26 | |
Ingo Molnar | 862a1a5 | 2008-12-17 13:09:20 +0100 | [diff] [blame] | 27 | static u64 perf_counter_mask __read_mostly; |
Ingo Molnar | 703e937 | 2008-12-17 10:51:15 +0100 | [diff] [blame] | 28 | |
Ingo Molnar | 241771e | 2008-12-03 10:39:53 +0100 | [diff] [blame] | 29 | struct cpu_hw_counters { |
Ingo Molnar | 862a1a5 | 2008-12-17 13:09:20 +0100 | [diff] [blame] | 30 | struct perf_counter *counters[X86_PMC_IDX_MAX]; |
Robert Richter | 43f6201 | 2009-04-29 16:55:56 +0200 | [diff] [blame] | 31 | unsigned long used_mask[BITS_TO_LONGS(X86_PMC_IDX_MAX)]; |
| 32 | unsigned long active_mask[BITS_TO_LONGS(X86_PMC_IDX_MAX)]; |
Mike Galbraith | 4b39fd9 | 2009-01-23 14:36:16 +0100 | [diff] [blame] | 33 | unsigned long interrupts; |
Peter Zijlstra | b0f3f28 | 2009-03-05 18:08:27 +0100 | [diff] [blame] | 34 | int enabled; |
Ingo Molnar | 241771e | 2008-12-03 10:39:53 +0100 | [diff] [blame] | 35 | }; |
| 36 | |
| 37 | /* |
Robert Richter | 5f4ec28 | 2009-04-29 12:47:04 +0200 | [diff] [blame] | 38 | * struct x86_pmu - generic x86 pmu |
Ingo Molnar | 241771e | 2008-12-03 10:39:53 +0100 | [diff] [blame] | 39 | */ |
Robert Richter | 5f4ec28 | 2009-04-29 12:47:04 +0200 | [diff] [blame] | 40 | struct x86_pmu { |
Robert Richter | faa28ae | 2009-04-29 12:47:13 +0200 | [diff] [blame] | 41 | const char *name; |
| 42 | int version; |
Robert Richter | 39d81ea | 2009-04-29 12:47:05 +0200 | [diff] [blame] | 43 | int (*handle_irq)(struct pt_regs *, int); |
Peter Zijlstra | 9e35ad3 | 2009-05-13 16:21:38 +0200 | [diff] [blame] | 44 | void (*disable_all)(void); |
| 45 | void (*enable_all)(void); |
Robert Richter | 7c90cc4 | 2009-04-29 12:47:18 +0200 | [diff] [blame] | 46 | void (*enable)(struct hw_perf_counter *, int); |
Robert Richter | d436989 | 2009-04-29 12:47:19 +0200 | [diff] [blame] | 47 | void (*disable)(struct hw_perf_counter *, int); |
Jaswinder Singh Rajput | 169e41e | 2009-02-28 18:37:49 +0530 | [diff] [blame] | 48 | unsigned eventsel; |
| 49 | unsigned perfctr; |
Peter Zijlstra | b0f3f28 | 2009-03-05 18:08:27 +0100 | [diff] [blame] | 50 | u64 (*event_map)(int); |
| 51 | u64 (*raw_event)(u64); |
Jaswinder Singh Rajput | 169e41e | 2009-02-28 18:37:49 +0530 | [diff] [blame] | 52 | int max_events; |
Robert Richter | 0933e5c | 2009-04-29 12:47:12 +0200 | [diff] [blame] | 53 | int num_counters; |
| 54 | int num_counters_fixed; |
| 55 | int counter_bits; |
| 56 | u64 counter_mask; |
Robert Richter | c619b8f | 2009-04-29 12:47:23 +0200 | [diff] [blame] | 57 | u64 max_period; |
Peter Zijlstra | 9e35ad3 | 2009-05-13 16:21:38 +0200 | [diff] [blame] | 58 | u64 intel_ctrl; |
Jaswinder Singh Rajput | b56a380 | 2009-02-27 18:09:09 +0530 | [diff] [blame] | 59 | }; |
| 60 | |
Robert Richter | 4a06bd8 | 2009-04-29 12:47:11 +0200 | [diff] [blame] | 61 | static struct x86_pmu x86_pmu __read_mostly; |
Jaswinder Singh Rajput | b56a380 | 2009-02-27 18:09:09 +0530 | [diff] [blame] | 62 | |
Peter Zijlstra | b0f3f28 | 2009-03-05 18:08:27 +0100 | [diff] [blame] | 63 | static DEFINE_PER_CPU(struct cpu_hw_counters, cpu_hw_counters) = { |
| 64 | .enabled = 1, |
| 65 | }; |
Ingo Molnar | 241771e | 2008-12-03 10:39:53 +0100 | [diff] [blame] | 66 | |
Jaswinder Singh Rajput | b56a380 | 2009-02-27 18:09:09 +0530 | [diff] [blame] | 67 | /* |
| 68 | * Intel PerfMon v3. Used on Core2 and later. |
| 69 | */ |
Peter Zijlstra | b0f3f28 | 2009-03-05 18:08:27 +0100 | [diff] [blame] | 70 | static const u64 intel_perfmon_event_map[] = |
Ingo Molnar | 241771e | 2008-12-03 10:39:53 +0100 | [diff] [blame] | 71 | { |
Ingo Molnar | f650a67 | 2008-12-23 12:17:29 +0100 | [diff] [blame] | 72 | [PERF_COUNT_CPU_CYCLES] = 0x003c, |
Ingo Molnar | 241771e | 2008-12-03 10:39:53 +0100 | [diff] [blame] | 73 | [PERF_COUNT_INSTRUCTIONS] = 0x00c0, |
| 74 | [PERF_COUNT_CACHE_REFERENCES] = 0x4f2e, |
| 75 | [PERF_COUNT_CACHE_MISSES] = 0x412e, |
| 76 | [PERF_COUNT_BRANCH_INSTRUCTIONS] = 0x00c4, |
| 77 | [PERF_COUNT_BRANCH_MISSES] = 0x00c5, |
Ingo Molnar | f650a67 | 2008-12-23 12:17:29 +0100 | [diff] [blame] | 78 | [PERF_COUNT_BUS_CYCLES] = 0x013c, |
Ingo Molnar | 241771e | 2008-12-03 10:39:53 +0100 | [diff] [blame] | 79 | }; |
| 80 | |
Robert Richter | 5f4ec28 | 2009-04-29 12:47:04 +0200 | [diff] [blame] | 81 | static u64 intel_pmu_event_map(int event) |
Jaswinder Singh Rajput | b56a380 | 2009-02-27 18:09:09 +0530 | [diff] [blame] | 82 | { |
| 83 | return intel_perfmon_event_map[event]; |
| 84 | } |
Ingo Molnar | 241771e | 2008-12-03 10:39:53 +0100 | [diff] [blame] | 85 | |
Robert Richter | 5f4ec28 | 2009-04-29 12:47:04 +0200 | [diff] [blame] | 86 | static u64 intel_pmu_raw_event(u64 event) |
Peter Zijlstra | b0f3f28 | 2009-03-05 18:08:27 +0100 | [diff] [blame] | 87 | { |
Peter Zijlstra | 82bae4f8 | 2009-03-13 12:21:31 +0100 | [diff] [blame] | 88 | #define CORE_EVNTSEL_EVENT_MASK 0x000000FFULL |
| 89 | #define CORE_EVNTSEL_UNIT_MASK 0x0000FF00ULL |
| 90 | #define CORE_EVNTSEL_COUNTER_MASK 0xFF000000ULL |
Peter Zijlstra | b0f3f28 | 2009-03-05 18:08:27 +0100 | [diff] [blame] | 91 | |
| 92 | #define CORE_EVNTSEL_MASK \ |
| 93 | (CORE_EVNTSEL_EVENT_MASK | \ |
| 94 | CORE_EVNTSEL_UNIT_MASK | \ |
| 95 | CORE_EVNTSEL_COUNTER_MASK) |
| 96 | |
| 97 | return event & CORE_EVNTSEL_MASK; |
| 98 | } |
| 99 | |
Ingo Molnar | 241771e | 2008-12-03 10:39:53 +0100 | [diff] [blame] | 100 | /* |
Jaswinder Singh Rajput | f87ad35 | 2009-02-27 20:15:14 +0530 | [diff] [blame] | 101 | * AMD Performance Monitor K7 and later. |
| 102 | */ |
Peter Zijlstra | b0f3f28 | 2009-03-05 18:08:27 +0100 | [diff] [blame] | 103 | static const u64 amd_perfmon_event_map[] = |
Jaswinder Singh Rajput | f87ad35 | 2009-02-27 20:15:14 +0530 | [diff] [blame] | 104 | { |
| 105 | [PERF_COUNT_CPU_CYCLES] = 0x0076, |
| 106 | [PERF_COUNT_INSTRUCTIONS] = 0x00c0, |
| 107 | [PERF_COUNT_CACHE_REFERENCES] = 0x0080, |
| 108 | [PERF_COUNT_CACHE_MISSES] = 0x0081, |
| 109 | [PERF_COUNT_BRANCH_INSTRUCTIONS] = 0x00c4, |
| 110 | [PERF_COUNT_BRANCH_MISSES] = 0x00c5, |
| 111 | }; |
| 112 | |
Robert Richter | 5f4ec28 | 2009-04-29 12:47:04 +0200 | [diff] [blame] | 113 | static u64 amd_pmu_event_map(int event) |
Jaswinder Singh Rajput | f87ad35 | 2009-02-27 20:15:14 +0530 | [diff] [blame] | 114 | { |
| 115 | return amd_perfmon_event_map[event]; |
| 116 | } |
| 117 | |
Robert Richter | 5f4ec28 | 2009-04-29 12:47:04 +0200 | [diff] [blame] | 118 | static u64 amd_pmu_raw_event(u64 event) |
Peter Zijlstra | b0f3f28 | 2009-03-05 18:08:27 +0100 | [diff] [blame] | 119 | { |
Peter Zijlstra | 82bae4f8 | 2009-03-13 12:21:31 +0100 | [diff] [blame] | 120 | #define K7_EVNTSEL_EVENT_MASK 0x7000000FFULL |
| 121 | #define K7_EVNTSEL_UNIT_MASK 0x00000FF00ULL |
| 122 | #define K7_EVNTSEL_COUNTER_MASK 0x0FF000000ULL |
Peter Zijlstra | b0f3f28 | 2009-03-05 18:08:27 +0100 | [diff] [blame] | 123 | |
| 124 | #define K7_EVNTSEL_MASK \ |
| 125 | (K7_EVNTSEL_EVENT_MASK | \ |
| 126 | K7_EVNTSEL_UNIT_MASK | \ |
| 127 | K7_EVNTSEL_COUNTER_MASK) |
| 128 | |
| 129 | return event & K7_EVNTSEL_MASK; |
| 130 | } |
| 131 | |
Jaswinder Singh Rajput | f87ad35 | 2009-02-27 20:15:14 +0530 | [diff] [blame] | 132 | /* |
Ingo Molnar | ee06094 | 2008-12-13 09:00:03 +0100 | [diff] [blame] | 133 | * Propagate counter elapsed time into the generic counter. |
| 134 | * Can only be executed on the CPU where the counter is active. |
| 135 | * Returns the delta events processed. |
| 136 | */ |
Robert Richter | 4b7bfd0 | 2009-04-29 12:47:22 +0200 | [diff] [blame] | 137 | static u64 |
Ingo Molnar | ee06094 | 2008-12-13 09:00:03 +0100 | [diff] [blame] | 138 | x86_perf_counter_update(struct perf_counter *counter, |
| 139 | struct hw_perf_counter *hwc, int idx) |
| 140 | { |
Peter Zijlstra | ec3232b | 2009-05-13 09:45:19 +0200 | [diff] [blame] | 141 | int shift = 64 - x86_pmu.counter_bits; |
| 142 | u64 prev_raw_count, new_raw_count; |
| 143 | s64 delta; |
Ingo Molnar | ee06094 | 2008-12-13 09:00:03 +0100 | [diff] [blame] | 144 | |
Ingo Molnar | ee06094 | 2008-12-13 09:00:03 +0100 | [diff] [blame] | 145 | /* |
| 146 | * Careful: an NMI might modify the previous counter value. |
| 147 | * |
| 148 | * Our tactic to handle this is to first atomically read and |
| 149 | * exchange a new raw count - then add that new-prev delta |
| 150 | * count to the generic counter atomically: |
| 151 | */ |
| 152 | again: |
| 153 | prev_raw_count = atomic64_read(&hwc->prev_count); |
| 154 | rdmsrl(hwc->counter_base + idx, new_raw_count); |
| 155 | |
| 156 | if (atomic64_cmpxchg(&hwc->prev_count, prev_raw_count, |
| 157 | new_raw_count) != prev_raw_count) |
| 158 | goto again; |
| 159 | |
| 160 | /* |
| 161 | * Now we have the new raw value and have updated the prev |
| 162 | * timestamp already. We can now calculate the elapsed delta |
| 163 | * (counter-)time and add that to the generic counter. |
| 164 | * |
| 165 | * Careful, not all hw sign-extends above the physical width |
Peter Zijlstra | ec3232b | 2009-05-13 09:45:19 +0200 | [diff] [blame] | 166 | * of the count. |
Ingo Molnar | ee06094 | 2008-12-13 09:00:03 +0100 | [diff] [blame] | 167 | */ |
Peter Zijlstra | ec3232b | 2009-05-13 09:45:19 +0200 | [diff] [blame] | 168 | delta = (new_raw_count << shift) - (prev_raw_count << shift); |
| 169 | delta >>= shift; |
Ingo Molnar | ee06094 | 2008-12-13 09:00:03 +0100 | [diff] [blame] | 170 | |
| 171 | atomic64_add(delta, &counter->count); |
| 172 | atomic64_sub(delta, &hwc->period_left); |
Robert Richter | 4b7bfd0 | 2009-04-29 12:47:22 +0200 | [diff] [blame] | 173 | |
| 174 | return new_raw_count; |
Ingo Molnar | ee06094 | 2008-12-13 09:00:03 +0100 | [diff] [blame] | 175 | } |
| 176 | |
Peter Zijlstra | ba77813 | 2009-05-04 18:47:44 +0200 | [diff] [blame] | 177 | static atomic_t active_counters; |
Peter Zijlstra | 4e935e4 | 2009-03-30 19:07:16 +0200 | [diff] [blame] | 178 | static DEFINE_MUTEX(pmc_reserve_mutex); |
| 179 | |
| 180 | static bool reserve_pmc_hardware(void) |
| 181 | { |
| 182 | int i; |
| 183 | |
| 184 | if (nmi_watchdog == NMI_LOCAL_APIC) |
| 185 | disable_lapic_nmi_watchdog(); |
| 186 | |
Robert Richter | 0933e5c | 2009-04-29 12:47:12 +0200 | [diff] [blame] | 187 | for (i = 0; i < x86_pmu.num_counters; i++) { |
Robert Richter | 4a06bd8 | 2009-04-29 12:47:11 +0200 | [diff] [blame] | 188 | if (!reserve_perfctr_nmi(x86_pmu.perfctr + i)) |
Peter Zijlstra | 4e935e4 | 2009-03-30 19:07:16 +0200 | [diff] [blame] | 189 | goto perfctr_fail; |
| 190 | } |
| 191 | |
Robert Richter | 0933e5c | 2009-04-29 12:47:12 +0200 | [diff] [blame] | 192 | for (i = 0; i < x86_pmu.num_counters; i++) { |
Robert Richter | 4a06bd8 | 2009-04-29 12:47:11 +0200 | [diff] [blame] | 193 | if (!reserve_evntsel_nmi(x86_pmu.eventsel + i)) |
Peter Zijlstra | 4e935e4 | 2009-03-30 19:07:16 +0200 | [diff] [blame] | 194 | goto eventsel_fail; |
| 195 | } |
| 196 | |
| 197 | return true; |
| 198 | |
| 199 | eventsel_fail: |
| 200 | for (i--; i >= 0; i--) |
Robert Richter | 4a06bd8 | 2009-04-29 12:47:11 +0200 | [diff] [blame] | 201 | release_evntsel_nmi(x86_pmu.eventsel + i); |
Peter Zijlstra | 4e935e4 | 2009-03-30 19:07:16 +0200 | [diff] [blame] | 202 | |
Robert Richter | 0933e5c | 2009-04-29 12:47:12 +0200 | [diff] [blame] | 203 | i = x86_pmu.num_counters; |
Peter Zijlstra | 4e935e4 | 2009-03-30 19:07:16 +0200 | [diff] [blame] | 204 | |
| 205 | perfctr_fail: |
| 206 | for (i--; i >= 0; i--) |
Robert Richter | 4a06bd8 | 2009-04-29 12:47:11 +0200 | [diff] [blame] | 207 | release_perfctr_nmi(x86_pmu.perfctr + i); |
Peter Zijlstra | 4e935e4 | 2009-03-30 19:07:16 +0200 | [diff] [blame] | 208 | |
| 209 | if (nmi_watchdog == NMI_LOCAL_APIC) |
| 210 | enable_lapic_nmi_watchdog(); |
| 211 | |
| 212 | return false; |
| 213 | } |
| 214 | |
| 215 | static void release_pmc_hardware(void) |
| 216 | { |
| 217 | int i; |
| 218 | |
Robert Richter | 0933e5c | 2009-04-29 12:47:12 +0200 | [diff] [blame] | 219 | for (i = 0; i < x86_pmu.num_counters; i++) { |
Robert Richter | 4a06bd8 | 2009-04-29 12:47:11 +0200 | [diff] [blame] | 220 | release_perfctr_nmi(x86_pmu.perfctr + i); |
| 221 | release_evntsel_nmi(x86_pmu.eventsel + i); |
Peter Zijlstra | 4e935e4 | 2009-03-30 19:07:16 +0200 | [diff] [blame] | 222 | } |
| 223 | |
| 224 | if (nmi_watchdog == NMI_LOCAL_APIC) |
| 225 | enable_lapic_nmi_watchdog(); |
| 226 | } |
| 227 | |
| 228 | static void hw_perf_counter_destroy(struct perf_counter *counter) |
| 229 | { |
Peter Zijlstra | ba77813 | 2009-05-04 18:47:44 +0200 | [diff] [blame] | 230 | if (atomic_dec_and_mutex_lock(&active_counters, &pmc_reserve_mutex)) { |
Peter Zijlstra | 4e935e4 | 2009-03-30 19:07:16 +0200 | [diff] [blame] | 231 | release_pmc_hardware(); |
| 232 | mutex_unlock(&pmc_reserve_mutex); |
| 233 | } |
| 234 | } |
| 235 | |
Robert Richter | 85cf9db | 2009-04-29 12:47:20 +0200 | [diff] [blame] | 236 | static inline int x86_pmu_initialized(void) |
| 237 | { |
| 238 | return x86_pmu.handle_irq != NULL; |
| 239 | } |
| 240 | |
Ingo Molnar | ee06094 | 2008-12-13 09:00:03 +0100 | [diff] [blame] | 241 | /* |
Ingo Molnar | 241771e | 2008-12-03 10:39:53 +0100 | [diff] [blame] | 242 | * Setup the hardware configuration for a given hw_event_type |
| 243 | */ |
Ingo Molnar | 621a01e | 2008-12-11 12:46:46 +0100 | [diff] [blame] | 244 | static int __hw_perf_counter_init(struct perf_counter *counter) |
Ingo Molnar | 241771e | 2008-12-03 10:39:53 +0100 | [diff] [blame] | 245 | { |
Ingo Molnar | 9f66a38 | 2008-12-10 12:33:23 +0100 | [diff] [blame] | 246 | struct perf_counter_hw_event *hw_event = &counter->hw_event; |
Ingo Molnar | 241771e | 2008-12-03 10:39:53 +0100 | [diff] [blame] | 247 | struct hw_perf_counter *hwc = &counter->hw; |
Peter Zijlstra | 4e935e4 | 2009-03-30 19:07:16 +0200 | [diff] [blame] | 248 | int err; |
Ingo Molnar | 241771e | 2008-12-03 10:39:53 +0100 | [diff] [blame] | 249 | |
Robert Richter | 85cf9db | 2009-04-29 12:47:20 +0200 | [diff] [blame] | 250 | if (!x86_pmu_initialized()) |
| 251 | return -ENODEV; |
Ingo Molnar | 241771e | 2008-12-03 10:39:53 +0100 | [diff] [blame] | 252 | |
Peter Zijlstra | 4e935e4 | 2009-03-30 19:07:16 +0200 | [diff] [blame] | 253 | err = 0; |
Peter Zijlstra | ba77813 | 2009-05-04 18:47:44 +0200 | [diff] [blame] | 254 | if (!atomic_inc_not_zero(&active_counters)) { |
Peter Zijlstra | 4e935e4 | 2009-03-30 19:07:16 +0200 | [diff] [blame] | 255 | mutex_lock(&pmc_reserve_mutex); |
Peter Zijlstra | ba77813 | 2009-05-04 18:47:44 +0200 | [diff] [blame] | 256 | if (atomic_read(&active_counters) == 0 && !reserve_pmc_hardware()) |
Peter Zijlstra | 4e935e4 | 2009-03-30 19:07:16 +0200 | [diff] [blame] | 257 | err = -EBUSY; |
| 258 | else |
Peter Zijlstra | ba77813 | 2009-05-04 18:47:44 +0200 | [diff] [blame] | 259 | atomic_inc(&active_counters); |
Peter Zijlstra | 4e935e4 | 2009-03-30 19:07:16 +0200 | [diff] [blame] | 260 | mutex_unlock(&pmc_reserve_mutex); |
| 261 | } |
| 262 | if (err) |
| 263 | return err; |
| 264 | |
Ingo Molnar | 241771e | 2008-12-03 10:39:53 +0100 | [diff] [blame] | 265 | /* |
Paul Mackerras | 0475f9e | 2009-02-11 14:35:35 +1100 | [diff] [blame] | 266 | * Generate PMC IRQs: |
Ingo Molnar | 241771e | 2008-12-03 10:39:53 +0100 | [diff] [blame] | 267 | * (keep 'enabled' bit clear for now) |
| 268 | */ |
Paul Mackerras | 0475f9e | 2009-02-11 14:35:35 +1100 | [diff] [blame] | 269 | hwc->config = ARCH_PERFMON_EVENTSEL_INT; |
Ingo Molnar | 241771e | 2008-12-03 10:39:53 +0100 | [diff] [blame] | 270 | |
| 271 | /* |
Paul Mackerras | 0475f9e | 2009-02-11 14:35:35 +1100 | [diff] [blame] | 272 | * Count user and OS events unless requested not to. |
| 273 | */ |
| 274 | if (!hw_event->exclude_user) |
| 275 | hwc->config |= ARCH_PERFMON_EVENTSEL_USR; |
| 276 | if (!hw_event->exclude_kernel) |
| 277 | hwc->config |= ARCH_PERFMON_EVENTSEL_OS; |
| 278 | |
| 279 | /* |
| 280 | * If privileged enough, allow NMI events: |
Ingo Molnar | 241771e | 2008-12-03 10:39:53 +0100 | [diff] [blame] | 281 | */ |
| 282 | hwc->nmi = 0; |
Peter Zijlstra | a026dfe | 2009-05-13 10:02:57 +0200 | [diff] [blame] | 283 | if (hw_event->nmi) { |
| 284 | if (sysctl_perf_counter_priv && !capable(CAP_SYS_ADMIN)) |
| 285 | return -EACCES; |
Paul Mackerras | 0475f9e | 2009-02-11 14:35:35 +1100 | [diff] [blame] | 286 | hwc->nmi = 1; |
Peter Zijlstra | a026dfe | 2009-05-13 10:02:57 +0200 | [diff] [blame] | 287 | } |
Ingo Molnar | 241771e | 2008-12-03 10:39:53 +0100 | [diff] [blame] | 288 | |
Peter Zijlstra | ba77813 | 2009-05-04 18:47:44 +0200 | [diff] [blame] | 289 | hwc->irq_period = hw_event->irq_period; |
Robert Richter | c619b8f | 2009-04-29 12:47:23 +0200 | [diff] [blame] | 290 | if ((s64)hwc->irq_period <= 0 || hwc->irq_period > x86_pmu.max_period) |
| 291 | hwc->irq_period = x86_pmu.max_period; |
Ingo Molnar | 241771e | 2008-12-03 10:39:53 +0100 | [diff] [blame] | 292 | |
Ingo Molnar | ee06094 | 2008-12-13 09:00:03 +0100 | [diff] [blame] | 293 | atomic64_set(&hwc->period_left, hwc->irq_period); |
Ingo Molnar | 241771e | 2008-12-03 10:39:53 +0100 | [diff] [blame] | 294 | |
| 295 | /* |
Thomas Gleixner | dfa7c89 | 2008-12-08 19:35:37 +0100 | [diff] [blame] | 296 | * Raw event type provide the config in the event structure |
Ingo Molnar | 241771e | 2008-12-03 10:39:53 +0100 | [diff] [blame] | 297 | */ |
Peter Zijlstra | f4a2deb4 | 2009-03-23 18:22:06 +0100 | [diff] [blame] | 298 | if (perf_event_raw(hw_event)) { |
Robert Richter | 4a06bd8 | 2009-04-29 12:47:11 +0200 | [diff] [blame] | 299 | hwc->config |= x86_pmu.raw_event(perf_event_config(hw_event)); |
Ingo Molnar | 241771e | 2008-12-03 10:39:53 +0100 | [diff] [blame] | 300 | } else { |
Robert Richter | 4a06bd8 | 2009-04-29 12:47:11 +0200 | [diff] [blame] | 301 | if (perf_event_id(hw_event) >= x86_pmu.max_events) |
Ingo Molnar | 241771e | 2008-12-03 10:39:53 +0100 | [diff] [blame] | 302 | return -EINVAL; |
| 303 | /* |
| 304 | * The generic map: |
| 305 | */ |
Robert Richter | 4a06bd8 | 2009-04-29 12:47:11 +0200 | [diff] [blame] | 306 | hwc->config |= x86_pmu.event_map(perf_event_id(hw_event)); |
Ingo Molnar | 241771e | 2008-12-03 10:39:53 +0100 | [diff] [blame] | 307 | } |
Ingo Molnar | 241771e | 2008-12-03 10:39:53 +0100 | [diff] [blame] | 308 | |
Peter Zijlstra | 4e935e4 | 2009-03-30 19:07:16 +0200 | [diff] [blame] | 309 | counter->destroy = hw_perf_counter_destroy; |
| 310 | |
Ingo Molnar | 241771e | 2008-12-03 10:39:53 +0100 | [diff] [blame] | 311 | return 0; |
| 312 | } |
| 313 | |
Peter Zijlstra | 9e35ad3 | 2009-05-13 16:21:38 +0200 | [diff] [blame] | 314 | static void intel_pmu_disable_all(void) |
Thomas Gleixner | 4ac1329 | 2008-12-09 21:43:39 +0100 | [diff] [blame] | 315 | { |
Ingo Molnar | 862a1a5 | 2008-12-17 13:09:20 +0100 | [diff] [blame] | 316 | wrmsrl(MSR_CORE_PERF_GLOBAL_CTRL, 0); |
Thomas Gleixner | 4ac1329 | 2008-12-09 21:43:39 +0100 | [diff] [blame] | 317 | } |
Jaswinder Singh Rajput | b56a380 | 2009-02-27 18:09:09 +0530 | [diff] [blame] | 318 | |
Peter Zijlstra | 9e35ad3 | 2009-05-13 16:21:38 +0200 | [diff] [blame] | 319 | static void amd_pmu_disable_all(void) |
Jaswinder Singh Rajput | f87ad35 | 2009-02-27 20:15:14 +0530 | [diff] [blame] | 320 | { |
Peter Zijlstra | b0f3f28 | 2009-03-05 18:08:27 +0100 | [diff] [blame] | 321 | struct cpu_hw_counters *cpuc = &__get_cpu_var(cpu_hw_counters); |
Peter Zijlstra | 9e35ad3 | 2009-05-13 16:21:38 +0200 | [diff] [blame] | 322 | int idx; |
Peter Zijlstra | b0f3f28 | 2009-03-05 18:08:27 +0100 | [diff] [blame] | 323 | |
Peter Zijlstra | 9e35ad3 | 2009-05-13 16:21:38 +0200 | [diff] [blame] | 324 | if (!cpuc->enabled) |
| 325 | return; |
| 326 | |
Peter Zijlstra | b0f3f28 | 2009-03-05 18:08:27 +0100 | [diff] [blame] | 327 | cpuc->enabled = 0; |
Peter Zijlstra | 60b3df9 | 2009-03-13 12:21:30 +0100 | [diff] [blame] | 328 | /* |
| 329 | * ensure we write the disable before we start disabling the |
Robert Richter | 5f4ec28 | 2009-04-29 12:47:04 +0200 | [diff] [blame] | 330 | * counters proper, so that amd_pmu_enable_counter() does the |
| 331 | * right thing. |
Peter Zijlstra | 60b3df9 | 2009-03-13 12:21:30 +0100 | [diff] [blame] | 332 | */ |
Peter Zijlstra | b0f3f28 | 2009-03-05 18:08:27 +0100 | [diff] [blame] | 333 | barrier(); |
Jaswinder Singh Rajput | f87ad35 | 2009-02-27 20:15:14 +0530 | [diff] [blame] | 334 | |
Robert Richter | 0933e5c | 2009-04-29 12:47:12 +0200 | [diff] [blame] | 335 | for (idx = 0; idx < x86_pmu.num_counters; idx++) { |
Peter Zijlstra | b0f3f28 | 2009-03-05 18:08:27 +0100 | [diff] [blame] | 336 | u64 val; |
| 337 | |
Robert Richter | 43f6201 | 2009-04-29 16:55:56 +0200 | [diff] [blame] | 338 | if (!test_bit(idx, cpuc->active_mask)) |
Robert Richter | 4295ee6 | 2009-04-29 12:47:01 +0200 | [diff] [blame] | 339 | continue; |
Jaswinder Singh Rajput | f87ad35 | 2009-02-27 20:15:14 +0530 | [diff] [blame] | 340 | rdmsrl(MSR_K7_EVNTSEL0 + idx, val); |
Robert Richter | 4295ee6 | 2009-04-29 12:47:01 +0200 | [diff] [blame] | 341 | if (!(val & ARCH_PERFMON_EVENTSEL0_ENABLE)) |
| 342 | continue; |
| 343 | val &= ~ARCH_PERFMON_EVENTSEL0_ENABLE; |
| 344 | wrmsrl(MSR_K7_EVNTSEL0 + idx, val); |
Jaswinder Singh Rajput | f87ad35 | 2009-02-27 20:15:14 +0530 | [diff] [blame] | 345 | } |
Jaswinder Singh Rajput | f87ad35 | 2009-02-27 20:15:14 +0530 | [diff] [blame] | 346 | } |
| 347 | |
Peter Zijlstra | 9e35ad3 | 2009-05-13 16:21:38 +0200 | [diff] [blame] | 348 | void hw_perf_disable(void) |
Jaswinder Singh Rajput | b56a380 | 2009-02-27 18:09:09 +0530 | [diff] [blame] | 349 | { |
Robert Richter | 85cf9db | 2009-04-29 12:47:20 +0200 | [diff] [blame] | 350 | if (!x86_pmu_initialized()) |
Peter Zijlstra | 9e35ad3 | 2009-05-13 16:21:38 +0200 | [diff] [blame] | 351 | return; |
| 352 | return x86_pmu.disable_all(); |
Jaswinder Singh Rajput | b56a380 | 2009-02-27 18:09:09 +0530 | [diff] [blame] | 353 | } |
Ingo Molnar | 241771e | 2008-12-03 10:39:53 +0100 | [diff] [blame] | 354 | |
Peter Zijlstra | 9e35ad3 | 2009-05-13 16:21:38 +0200 | [diff] [blame] | 355 | static void intel_pmu_enable_all(void) |
Jaswinder Singh Rajput | b56a380 | 2009-02-27 18:09:09 +0530 | [diff] [blame] | 356 | { |
Peter Zijlstra | 9e35ad3 | 2009-05-13 16:21:38 +0200 | [diff] [blame] | 357 | wrmsrl(MSR_CORE_PERF_GLOBAL_CTRL, x86_pmu.intel_ctrl); |
Jaswinder Singh Rajput | b56a380 | 2009-02-27 18:09:09 +0530 | [diff] [blame] | 358 | } |
| 359 | |
Peter Zijlstra | 9e35ad3 | 2009-05-13 16:21:38 +0200 | [diff] [blame] | 360 | static void amd_pmu_enable_all(void) |
Jaswinder Singh Rajput | f87ad35 | 2009-02-27 20:15:14 +0530 | [diff] [blame] | 361 | { |
Peter Zijlstra | b0f3f28 | 2009-03-05 18:08:27 +0100 | [diff] [blame] | 362 | struct cpu_hw_counters *cpuc = &__get_cpu_var(cpu_hw_counters); |
Jaswinder Singh Rajput | f87ad35 | 2009-02-27 20:15:14 +0530 | [diff] [blame] | 363 | int idx; |
| 364 | |
Peter Zijlstra | 9e35ad3 | 2009-05-13 16:21:38 +0200 | [diff] [blame] | 365 | if (cpuc->enabled) |
Peter Zijlstra | b0f3f28 | 2009-03-05 18:08:27 +0100 | [diff] [blame] | 366 | return; |
| 367 | |
Peter Zijlstra | 9e35ad3 | 2009-05-13 16:21:38 +0200 | [diff] [blame] | 368 | cpuc->enabled = 1; |
| 369 | barrier(); |
| 370 | |
Robert Richter | 0933e5c | 2009-04-29 12:47:12 +0200 | [diff] [blame] | 371 | for (idx = 0; idx < x86_pmu.num_counters; idx++) { |
Robert Richter | 4295ee6 | 2009-04-29 12:47:01 +0200 | [diff] [blame] | 372 | u64 val; |
Peter Zijlstra | b0f3f28 | 2009-03-05 18:08:27 +0100 | [diff] [blame] | 373 | |
Robert Richter | 43f6201 | 2009-04-29 16:55:56 +0200 | [diff] [blame] | 374 | if (!test_bit(idx, cpuc->active_mask)) |
Robert Richter | 4295ee6 | 2009-04-29 12:47:01 +0200 | [diff] [blame] | 375 | continue; |
| 376 | rdmsrl(MSR_K7_EVNTSEL0 + idx, val); |
| 377 | if (val & ARCH_PERFMON_EVENTSEL0_ENABLE) |
| 378 | continue; |
| 379 | val |= ARCH_PERFMON_EVENTSEL0_ENABLE; |
| 380 | wrmsrl(MSR_K7_EVNTSEL0 + idx, val); |
Jaswinder Singh Rajput | f87ad35 | 2009-02-27 20:15:14 +0530 | [diff] [blame] | 381 | } |
| 382 | } |
| 383 | |
Peter Zijlstra | 9e35ad3 | 2009-05-13 16:21:38 +0200 | [diff] [blame] | 384 | void hw_perf_enable(void) |
Ingo Molnar | ee06094 | 2008-12-13 09:00:03 +0100 | [diff] [blame] | 385 | { |
Robert Richter | 85cf9db | 2009-04-29 12:47:20 +0200 | [diff] [blame] | 386 | if (!x86_pmu_initialized()) |
Ingo Molnar | 2b9ff0d | 2008-12-14 18:36:30 +0100 | [diff] [blame] | 387 | return; |
Peter Zijlstra | 9e35ad3 | 2009-05-13 16:21:38 +0200 | [diff] [blame] | 388 | x86_pmu.enable_all(); |
Ingo Molnar | ee06094 | 2008-12-13 09:00:03 +0100 | [diff] [blame] | 389 | } |
Ingo Molnar | ee06094 | 2008-12-13 09:00:03 +0100 | [diff] [blame] | 390 | |
Robert Richter | 19d84da | 2009-04-29 12:47:25 +0200 | [diff] [blame] | 391 | static inline u64 intel_pmu_get_status(void) |
Peter Zijlstra | b0f3f28 | 2009-03-05 18:08:27 +0100 | [diff] [blame] | 392 | { |
| 393 | u64 status; |
| 394 | |
| 395 | rdmsrl(MSR_CORE_PERF_GLOBAL_STATUS, status); |
| 396 | |
| 397 | return status; |
| 398 | } |
| 399 | |
Robert Richter | dee5d90 | 2009-04-29 12:47:07 +0200 | [diff] [blame] | 400 | static inline void intel_pmu_ack_status(u64 ack) |
Peter Zijlstra | b0f3f28 | 2009-03-05 18:08:27 +0100 | [diff] [blame] | 401 | { |
| 402 | wrmsrl(MSR_CORE_PERF_GLOBAL_OVF_CTRL, ack); |
| 403 | } |
| 404 | |
Robert Richter | 7c90cc4 | 2009-04-29 12:47:18 +0200 | [diff] [blame] | 405 | static inline void x86_pmu_enable_counter(struct hw_perf_counter *hwc, int idx) |
Peter Zijlstra | b0f3f28 | 2009-03-05 18:08:27 +0100 | [diff] [blame] | 406 | { |
Robert Richter | 7c90cc4 | 2009-04-29 12:47:18 +0200 | [diff] [blame] | 407 | int err; |
Robert Richter | 7c90cc4 | 2009-04-29 12:47:18 +0200 | [diff] [blame] | 408 | err = checking_wrmsrl(hwc->config_base + idx, |
| 409 | hwc->config | ARCH_PERFMON_EVENTSEL0_ENABLE); |
Peter Zijlstra | b0f3f28 | 2009-03-05 18:08:27 +0100 | [diff] [blame] | 410 | } |
| 411 | |
Robert Richter | d436989 | 2009-04-29 12:47:19 +0200 | [diff] [blame] | 412 | static inline void x86_pmu_disable_counter(struct hw_perf_counter *hwc, int idx) |
Peter Zijlstra | b0f3f28 | 2009-03-05 18:08:27 +0100 | [diff] [blame] | 413 | { |
Robert Richter | d436989 | 2009-04-29 12:47:19 +0200 | [diff] [blame] | 414 | int err; |
Robert Richter | d436989 | 2009-04-29 12:47:19 +0200 | [diff] [blame] | 415 | err = checking_wrmsrl(hwc->config_base + idx, |
| 416 | hwc->config); |
Peter Zijlstra | b0f3f28 | 2009-03-05 18:08:27 +0100 | [diff] [blame] | 417 | } |
| 418 | |
Ingo Molnar | 7e2ae34 | 2008-12-09 11:40:46 +0100 | [diff] [blame] | 419 | static inline void |
Robert Richter | d436989 | 2009-04-29 12:47:19 +0200 | [diff] [blame] | 420 | intel_pmu_disable_fixed(struct hw_perf_counter *hwc, int __idx) |
Ingo Molnar | 2f18d1e | 2008-12-22 11:10:42 +0100 | [diff] [blame] | 421 | { |
| 422 | int idx = __idx - X86_PMC_IDX_FIXED; |
| 423 | u64 ctrl_val, mask; |
| 424 | int err; |
| 425 | |
| 426 | mask = 0xfULL << (idx * 4); |
| 427 | |
| 428 | rdmsrl(hwc->config_base, ctrl_val); |
| 429 | ctrl_val &= ~mask; |
| 430 | err = checking_wrmsrl(hwc->config_base, ctrl_val); |
| 431 | } |
| 432 | |
| 433 | static inline void |
Robert Richter | d436989 | 2009-04-29 12:47:19 +0200 | [diff] [blame] | 434 | intel_pmu_disable_counter(struct hw_perf_counter *hwc, int idx) |
Ingo Molnar | 7e2ae34 | 2008-12-09 11:40:46 +0100 | [diff] [blame] | 435 | { |
Robert Richter | d436989 | 2009-04-29 12:47:19 +0200 | [diff] [blame] | 436 | if (unlikely(hwc->config_base == MSR_ARCH_PERFMON_FIXED_CTR_CTRL)) { |
| 437 | intel_pmu_disable_fixed(hwc, idx); |
| 438 | return; |
| 439 | } |
| 440 | |
| 441 | x86_pmu_disable_counter(hwc, idx); |
| 442 | } |
| 443 | |
| 444 | static inline void |
| 445 | amd_pmu_disable_counter(struct hw_perf_counter *hwc, int idx) |
| 446 | { |
| 447 | x86_pmu_disable_counter(hwc, idx); |
Ingo Molnar | 7e2ae34 | 2008-12-09 11:40:46 +0100 | [diff] [blame] | 448 | } |
| 449 | |
Ingo Molnar | 2f18d1e | 2008-12-22 11:10:42 +0100 | [diff] [blame] | 450 | static DEFINE_PER_CPU(u64, prev_left[X86_PMC_IDX_MAX]); |
Ingo Molnar | 241771e | 2008-12-03 10:39:53 +0100 | [diff] [blame] | 451 | |
Ingo Molnar | ee06094 | 2008-12-13 09:00:03 +0100 | [diff] [blame] | 452 | /* |
| 453 | * Set the next IRQ period, based on the hwc->period_left value. |
| 454 | * To be called with the counter disabled in hw: |
| 455 | */ |
| 456 | static void |
Robert Richter | 26816c2 | 2009-04-29 12:47:08 +0200 | [diff] [blame] | 457 | x86_perf_counter_set_period(struct perf_counter *counter, |
Ingo Molnar | ee06094 | 2008-12-13 09:00:03 +0100 | [diff] [blame] | 458 | struct hw_perf_counter *hwc, int idx) |
Ingo Molnar | 241771e | 2008-12-03 10:39:53 +0100 | [diff] [blame] | 459 | { |
Ingo Molnar | 2f18d1e | 2008-12-22 11:10:42 +0100 | [diff] [blame] | 460 | s64 left = atomic64_read(&hwc->period_left); |
Peter Zijlstra | 595258a | 2009-03-13 12:21:28 +0100 | [diff] [blame] | 461 | s64 period = hwc->irq_period; |
Ingo Molnar | 2f18d1e | 2008-12-22 11:10:42 +0100 | [diff] [blame] | 462 | int err; |
Ingo Molnar | 241771e | 2008-12-03 10:39:53 +0100 | [diff] [blame] | 463 | |
Ingo Molnar | ee06094 | 2008-12-13 09:00:03 +0100 | [diff] [blame] | 464 | /* |
| 465 | * If we are way outside a reasoable range then just skip forward: |
| 466 | */ |
| 467 | if (unlikely(left <= -period)) { |
| 468 | left = period; |
| 469 | atomic64_set(&hwc->period_left, left); |
| 470 | } |
| 471 | |
| 472 | if (unlikely(left <= 0)) { |
| 473 | left += period; |
| 474 | atomic64_set(&hwc->period_left, left); |
| 475 | } |
| 476 | |
Ingo Molnar | ee06094 | 2008-12-13 09:00:03 +0100 | [diff] [blame] | 477 | per_cpu(prev_left[idx], smp_processor_id()) = left; |
| 478 | |
| 479 | /* |
| 480 | * The hw counter starts counting from this counter offset, |
| 481 | * mark it to be able to extra future deltas: |
| 482 | */ |
Ingo Molnar | 2f18d1e | 2008-12-22 11:10:42 +0100 | [diff] [blame] | 483 | atomic64_set(&hwc->prev_count, (u64)-left); |
Ingo Molnar | ee06094 | 2008-12-13 09:00:03 +0100 | [diff] [blame] | 484 | |
Ingo Molnar | 2f18d1e | 2008-12-22 11:10:42 +0100 | [diff] [blame] | 485 | err = checking_wrmsrl(hwc->counter_base + idx, |
Robert Richter | 0933e5c | 2009-04-29 12:47:12 +0200 | [diff] [blame] | 486 | (u64)(-left) & x86_pmu.counter_mask); |
Ingo Molnar | 2f18d1e | 2008-12-22 11:10:42 +0100 | [diff] [blame] | 487 | } |
| 488 | |
| 489 | static inline void |
Robert Richter | 7c90cc4 | 2009-04-29 12:47:18 +0200 | [diff] [blame] | 490 | intel_pmu_enable_fixed(struct hw_perf_counter *hwc, int __idx) |
Ingo Molnar | 2f18d1e | 2008-12-22 11:10:42 +0100 | [diff] [blame] | 491 | { |
| 492 | int idx = __idx - X86_PMC_IDX_FIXED; |
| 493 | u64 ctrl_val, bits, mask; |
| 494 | int err; |
| 495 | |
| 496 | /* |
Paul Mackerras | 0475f9e | 2009-02-11 14:35:35 +1100 | [diff] [blame] | 497 | * Enable IRQ generation (0x8), |
| 498 | * and enable ring-3 counting (0x2) and ring-0 counting (0x1) |
| 499 | * if requested: |
Ingo Molnar | 2f18d1e | 2008-12-22 11:10:42 +0100 | [diff] [blame] | 500 | */ |
Paul Mackerras | 0475f9e | 2009-02-11 14:35:35 +1100 | [diff] [blame] | 501 | bits = 0x8ULL; |
| 502 | if (hwc->config & ARCH_PERFMON_EVENTSEL_USR) |
| 503 | bits |= 0x2; |
Ingo Molnar | 2f18d1e | 2008-12-22 11:10:42 +0100 | [diff] [blame] | 504 | if (hwc->config & ARCH_PERFMON_EVENTSEL_OS) |
| 505 | bits |= 0x1; |
| 506 | bits <<= (idx * 4); |
| 507 | mask = 0xfULL << (idx * 4); |
| 508 | |
| 509 | rdmsrl(hwc->config_base, ctrl_val); |
| 510 | ctrl_val &= ~mask; |
| 511 | ctrl_val |= bits; |
| 512 | err = checking_wrmsrl(hwc->config_base, ctrl_val); |
Ingo Molnar | 7e2ae34 | 2008-12-09 11:40:46 +0100 | [diff] [blame] | 513 | } |
| 514 | |
Robert Richter | 7c90cc4 | 2009-04-29 12:47:18 +0200 | [diff] [blame] | 515 | static void intel_pmu_enable_counter(struct hw_perf_counter *hwc, int idx) |
Ingo Molnar | 7e2ae34 | 2008-12-09 11:40:46 +0100 | [diff] [blame] | 516 | { |
Robert Richter | 7c90cc4 | 2009-04-29 12:47:18 +0200 | [diff] [blame] | 517 | if (unlikely(hwc->config_base == MSR_ARCH_PERFMON_FIXED_CTR_CTRL)) { |
| 518 | intel_pmu_enable_fixed(hwc, idx); |
| 519 | return; |
| 520 | } |
| 521 | |
| 522 | x86_pmu_enable_counter(hwc, idx); |
| 523 | } |
| 524 | |
| 525 | static void amd_pmu_enable_counter(struct hw_perf_counter *hwc, int idx) |
| 526 | { |
| 527 | struct cpu_hw_counters *cpuc = &__get_cpu_var(cpu_hw_counters); |
| 528 | |
| 529 | if (cpuc->enabled) |
| 530 | x86_pmu_enable_counter(hwc, idx); |
Jaswinder Singh Rajput | 2b583d8 | 2008-12-27 19:15:43 +0530 | [diff] [blame] | 531 | else |
Robert Richter | d436989 | 2009-04-29 12:47:19 +0200 | [diff] [blame] | 532 | x86_pmu_disable_counter(hwc, idx); |
Ingo Molnar | 241771e | 2008-12-03 10:39:53 +0100 | [diff] [blame] | 533 | } |
| 534 | |
Ingo Molnar | 2f18d1e | 2008-12-22 11:10:42 +0100 | [diff] [blame] | 535 | static int |
| 536 | fixed_mode_idx(struct perf_counter *counter, struct hw_perf_counter *hwc) |
Ingo Molnar | 862a1a5 | 2008-12-17 13:09:20 +0100 | [diff] [blame] | 537 | { |
Ingo Molnar | 2f18d1e | 2008-12-22 11:10:42 +0100 | [diff] [blame] | 538 | unsigned int event; |
| 539 | |
Robert Richter | ef7b3e0 | 2009-04-29 12:47:24 +0200 | [diff] [blame] | 540 | if (!x86_pmu.num_counters_fixed) |
Jaswinder Singh Rajput | f87ad35 | 2009-02-27 20:15:14 +0530 | [diff] [blame] | 541 | return -1; |
| 542 | |
Ingo Molnar | 2f18d1e | 2008-12-22 11:10:42 +0100 | [diff] [blame] | 543 | if (unlikely(hwc->nmi)) |
| 544 | return -1; |
| 545 | |
| 546 | event = hwc->config & ARCH_PERFMON_EVENT_MASK; |
| 547 | |
Robert Richter | 4a06bd8 | 2009-04-29 12:47:11 +0200 | [diff] [blame] | 548 | if (unlikely(event == x86_pmu.event_map(PERF_COUNT_INSTRUCTIONS))) |
Ingo Molnar | 2f18d1e | 2008-12-22 11:10:42 +0100 | [diff] [blame] | 549 | return X86_PMC_IDX_FIXED_INSTRUCTIONS; |
Robert Richter | 4a06bd8 | 2009-04-29 12:47:11 +0200 | [diff] [blame] | 550 | if (unlikely(event == x86_pmu.event_map(PERF_COUNT_CPU_CYCLES))) |
Ingo Molnar | 2f18d1e | 2008-12-22 11:10:42 +0100 | [diff] [blame] | 551 | return X86_PMC_IDX_FIXED_CPU_CYCLES; |
Robert Richter | 4a06bd8 | 2009-04-29 12:47:11 +0200 | [diff] [blame] | 552 | if (unlikely(event == x86_pmu.event_map(PERF_COUNT_BUS_CYCLES))) |
Ingo Molnar | 2f18d1e | 2008-12-22 11:10:42 +0100 | [diff] [blame] | 553 | return X86_PMC_IDX_FIXED_BUS_CYCLES; |
| 554 | |
Ingo Molnar | 862a1a5 | 2008-12-17 13:09:20 +0100 | [diff] [blame] | 555 | return -1; |
| 556 | } |
| 557 | |
Ingo Molnar | ee06094 | 2008-12-13 09:00:03 +0100 | [diff] [blame] | 558 | /* |
| 559 | * Find a PMC slot for the freshly enabled / scheduled in counter: |
| 560 | */ |
Robert Richter | 4aeb0b4 | 2009-04-29 12:47:03 +0200 | [diff] [blame] | 561 | static int x86_pmu_enable(struct perf_counter *counter) |
Ingo Molnar | 241771e | 2008-12-03 10:39:53 +0100 | [diff] [blame] | 562 | { |
| 563 | struct cpu_hw_counters *cpuc = &__get_cpu_var(cpu_hw_counters); |
| 564 | struct hw_perf_counter *hwc = &counter->hw; |
Ingo Molnar | 2f18d1e | 2008-12-22 11:10:42 +0100 | [diff] [blame] | 565 | int idx; |
Ingo Molnar | 241771e | 2008-12-03 10:39:53 +0100 | [diff] [blame] | 566 | |
Ingo Molnar | 2f18d1e | 2008-12-22 11:10:42 +0100 | [diff] [blame] | 567 | idx = fixed_mode_idx(counter, hwc); |
| 568 | if (idx >= 0) { |
| 569 | /* |
| 570 | * Try to get the fixed counter, if that is already taken |
| 571 | * then try to get a generic counter: |
| 572 | */ |
Robert Richter | 43f6201 | 2009-04-29 16:55:56 +0200 | [diff] [blame] | 573 | if (test_and_set_bit(idx, cpuc->used_mask)) |
Ingo Molnar | 2f18d1e | 2008-12-22 11:10:42 +0100 | [diff] [blame] | 574 | goto try_generic; |
Ingo Molnar | 0dff86a | 2008-12-23 12:28:12 +0100 | [diff] [blame] | 575 | |
Ingo Molnar | 2f18d1e | 2008-12-22 11:10:42 +0100 | [diff] [blame] | 576 | hwc->config_base = MSR_ARCH_PERFMON_FIXED_CTR_CTRL; |
| 577 | /* |
| 578 | * We set it so that counter_base + idx in wrmsr/rdmsr maps to |
| 579 | * MSR_ARCH_PERFMON_FIXED_CTR0 ... CTR2: |
| 580 | */ |
| 581 | hwc->counter_base = |
| 582 | MSR_ARCH_PERFMON_FIXED_CTR0 - X86_PMC_IDX_FIXED; |
Ingo Molnar | 241771e | 2008-12-03 10:39:53 +0100 | [diff] [blame] | 583 | hwc->idx = idx; |
Ingo Molnar | 2f18d1e | 2008-12-22 11:10:42 +0100 | [diff] [blame] | 584 | } else { |
| 585 | idx = hwc->idx; |
| 586 | /* Try to get the previous generic counter again */ |
Robert Richter | 43f6201 | 2009-04-29 16:55:56 +0200 | [diff] [blame] | 587 | if (test_and_set_bit(idx, cpuc->used_mask)) { |
Ingo Molnar | 2f18d1e | 2008-12-22 11:10:42 +0100 | [diff] [blame] | 588 | try_generic: |
Robert Richter | 43f6201 | 2009-04-29 16:55:56 +0200 | [diff] [blame] | 589 | idx = find_first_zero_bit(cpuc->used_mask, |
Robert Richter | 0933e5c | 2009-04-29 12:47:12 +0200 | [diff] [blame] | 590 | x86_pmu.num_counters); |
| 591 | if (idx == x86_pmu.num_counters) |
Ingo Molnar | 2f18d1e | 2008-12-22 11:10:42 +0100 | [diff] [blame] | 592 | return -EAGAIN; |
| 593 | |
Robert Richter | 43f6201 | 2009-04-29 16:55:56 +0200 | [diff] [blame] | 594 | set_bit(idx, cpuc->used_mask); |
Ingo Molnar | 2f18d1e | 2008-12-22 11:10:42 +0100 | [diff] [blame] | 595 | hwc->idx = idx; |
| 596 | } |
Robert Richter | 4a06bd8 | 2009-04-29 12:47:11 +0200 | [diff] [blame] | 597 | hwc->config_base = x86_pmu.eventsel; |
| 598 | hwc->counter_base = x86_pmu.perfctr; |
Ingo Molnar | 241771e | 2008-12-03 10:39:53 +0100 | [diff] [blame] | 599 | } |
| 600 | |
| 601 | perf_counters_lapic_init(hwc->nmi); |
| 602 | |
Robert Richter | d436989 | 2009-04-29 12:47:19 +0200 | [diff] [blame] | 603 | x86_pmu.disable(hwc, idx); |
Ingo Molnar | 241771e | 2008-12-03 10:39:53 +0100 | [diff] [blame] | 604 | |
Ingo Molnar | 862a1a5 | 2008-12-17 13:09:20 +0100 | [diff] [blame] | 605 | cpuc->counters[idx] = counter; |
Robert Richter | 43f6201 | 2009-04-29 16:55:56 +0200 | [diff] [blame] | 606 | set_bit(idx, cpuc->active_mask); |
Ingo Molnar | 7e2ae34 | 2008-12-09 11:40:46 +0100 | [diff] [blame] | 607 | |
Robert Richter | 26816c2 | 2009-04-29 12:47:08 +0200 | [diff] [blame] | 608 | x86_perf_counter_set_period(counter, hwc, idx); |
Robert Richter | 7c90cc4 | 2009-04-29 12:47:18 +0200 | [diff] [blame] | 609 | x86_pmu.enable(hwc, idx); |
Ingo Molnar | 95cdd2e | 2008-12-21 13:50:42 +0100 | [diff] [blame] | 610 | |
| 611 | return 0; |
Ingo Molnar | 241771e | 2008-12-03 10:39:53 +0100 | [diff] [blame] | 612 | } |
| 613 | |
| 614 | void perf_counter_print_debug(void) |
| 615 | { |
Ingo Molnar | 2f18d1e | 2008-12-22 11:10:42 +0100 | [diff] [blame] | 616 | u64 ctrl, status, overflow, pmc_ctrl, pmc_count, prev_left, fixed; |
Ingo Molnar | 0dff86a | 2008-12-23 12:28:12 +0100 | [diff] [blame] | 617 | struct cpu_hw_counters *cpuc; |
Peter Zijlstra | 5bb9efe | 2009-05-13 08:12:51 +0200 | [diff] [blame] | 618 | unsigned long flags; |
Ingo Molnar | 1e12567 | 2008-12-09 12:18:18 +0100 | [diff] [blame] | 619 | int cpu, idx; |
| 620 | |
Robert Richter | 0933e5c | 2009-04-29 12:47:12 +0200 | [diff] [blame] | 621 | if (!x86_pmu.num_counters) |
Ingo Molnar | 1e12567 | 2008-12-09 12:18:18 +0100 | [diff] [blame] | 622 | return; |
Ingo Molnar | 241771e | 2008-12-03 10:39:53 +0100 | [diff] [blame] | 623 | |
Peter Zijlstra | 5bb9efe | 2009-05-13 08:12:51 +0200 | [diff] [blame] | 624 | local_irq_save(flags); |
Ingo Molnar | 241771e | 2008-12-03 10:39:53 +0100 | [diff] [blame] | 625 | |
| 626 | cpu = smp_processor_id(); |
Ingo Molnar | 0dff86a | 2008-12-23 12:28:12 +0100 | [diff] [blame] | 627 | cpuc = &per_cpu(cpu_hw_counters, cpu); |
Ingo Molnar | 241771e | 2008-12-03 10:39:53 +0100 | [diff] [blame] | 628 | |
Robert Richter | faa28ae | 2009-04-29 12:47:13 +0200 | [diff] [blame] | 629 | if (x86_pmu.version >= 2) { |
Jaswinder Singh Rajput | a1ef58f | 2009-02-28 18:45:39 +0530 | [diff] [blame] | 630 | rdmsrl(MSR_CORE_PERF_GLOBAL_CTRL, ctrl); |
| 631 | rdmsrl(MSR_CORE_PERF_GLOBAL_STATUS, status); |
| 632 | rdmsrl(MSR_CORE_PERF_GLOBAL_OVF_CTRL, overflow); |
| 633 | rdmsrl(MSR_ARCH_PERFMON_FIXED_CTR_CTRL, fixed); |
Ingo Molnar | 241771e | 2008-12-03 10:39:53 +0100 | [diff] [blame] | 634 | |
Jaswinder Singh Rajput | a1ef58f | 2009-02-28 18:45:39 +0530 | [diff] [blame] | 635 | pr_info("\n"); |
| 636 | pr_info("CPU#%d: ctrl: %016llx\n", cpu, ctrl); |
| 637 | pr_info("CPU#%d: status: %016llx\n", cpu, status); |
| 638 | pr_info("CPU#%d: overflow: %016llx\n", cpu, overflow); |
| 639 | pr_info("CPU#%d: fixed: %016llx\n", cpu, fixed); |
Jaswinder Singh Rajput | f87ad35 | 2009-02-27 20:15:14 +0530 | [diff] [blame] | 640 | } |
Robert Richter | 43f6201 | 2009-04-29 16:55:56 +0200 | [diff] [blame] | 641 | pr_info("CPU#%d: used: %016llx\n", cpu, *(u64 *)cpuc->used_mask); |
Ingo Molnar | 241771e | 2008-12-03 10:39:53 +0100 | [diff] [blame] | 642 | |
Robert Richter | 0933e5c | 2009-04-29 12:47:12 +0200 | [diff] [blame] | 643 | for (idx = 0; idx < x86_pmu.num_counters; idx++) { |
Robert Richter | 4a06bd8 | 2009-04-29 12:47:11 +0200 | [diff] [blame] | 644 | rdmsrl(x86_pmu.eventsel + idx, pmc_ctrl); |
| 645 | rdmsrl(x86_pmu.perfctr + idx, pmc_count); |
Ingo Molnar | 241771e | 2008-12-03 10:39:53 +0100 | [diff] [blame] | 646 | |
Ingo Molnar | ee06094 | 2008-12-13 09:00:03 +0100 | [diff] [blame] | 647 | prev_left = per_cpu(prev_left[idx], cpu); |
Ingo Molnar | 241771e | 2008-12-03 10:39:53 +0100 | [diff] [blame] | 648 | |
Jaswinder Singh Rajput | a1ef58f | 2009-02-28 18:45:39 +0530 | [diff] [blame] | 649 | pr_info("CPU#%d: gen-PMC%d ctrl: %016llx\n", |
Ingo Molnar | 241771e | 2008-12-03 10:39:53 +0100 | [diff] [blame] | 650 | cpu, idx, pmc_ctrl); |
Jaswinder Singh Rajput | a1ef58f | 2009-02-28 18:45:39 +0530 | [diff] [blame] | 651 | pr_info("CPU#%d: gen-PMC%d count: %016llx\n", |
Ingo Molnar | 241771e | 2008-12-03 10:39:53 +0100 | [diff] [blame] | 652 | cpu, idx, pmc_count); |
Jaswinder Singh Rajput | a1ef58f | 2009-02-28 18:45:39 +0530 | [diff] [blame] | 653 | pr_info("CPU#%d: gen-PMC%d left: %016llx\n", |
Ingo Molnar | ee06094 | 2008-12-13 09:00:03 +0100 | [diff] [blame] | 654 | cpu, idx, prev_left); |
Ingo Molnar | 241771e | 2008-12-03 10:39:53 +0100 | [diff] [blame] | 655 | } |
Robert Richter | 0933e5c | 2009-04-29 12:47:12 +0200 | [diff] [blame] | 656 | for (idx = 0; idx < x86_pmu.num_counters_fixed; idx++) { |
Ingo Molnar | 2f18d1e | 2008-12-22 11:10:42 +0100 | [diff] [blame] | 657 | rdmsrl(MSR_ARCH_PERFMON_FIXED_CTR0 + idx, pmc_count); |
| 658 | |
Jaswinder Singh Rajput | a1ef58f | 2009-02-28 18:45:39 +0530 | [diff] [blame] | 659 | pr_info("CPU#%d: fixed-PMC%d count: %016llx\n", |
Ingo Molnar | 2f18d1e | 2008-12-22 11:10:42 +0100 | [diff] [blame] | 660 | cpu, idx, pmc_count); |
| 661 | } |
Peter Zijlstra | 5bb9efe | 2009-05-13 08:12:51 +0200 | [diff] [blame] | 662 | local_irq_restore(flags); |
Ingo Molnar | 241771e | 2008-12-03 10:39:53 +0100 | [diff] [blame] | 663 | } |
| 664 | |
Robert Richter | 4aeb0b4 | 2009-04-29 12:47:03 +0200 | [diff] [blame] | 665 | static void x86_pmu_disable(struct perf_counter *counter) |
Ingo Molnar | 241771e | 2008-12-03 10:39:53 +0100 | [diff] [blame] | 666 | { |
| 667 | struct cpu_hw_counters *cpuc = &__get_cpu_var(cpu_hw_counters); |
| 668 | struct hw_perf_counter *hwc = &counter->hw; |
Robert Richter | 6f00cad | 2009-04-29 12:47:17 +0200 | [diff] [blame] | 669 | int idx = hwc->idx; |
Ingo Molnar | 241771e | 2008-12-03 10:39:53 +0100 | [diff] [blame] | 670 | |
Robert Richter | 0953423 | 2009-04-29 12:47:16 +0200 | [diff] [blame] | 671 | /* |
| 672 | * Must be done before we disable, otherwise the nmi handler |
| 673 | * could reenable again: |
| 674 | */ |
Robert Richter | 43f6201 | 2009-04-29 16:55:56 +0200 | [diff] [blame] | 675 | clear_bit(idx, cpuc->active_mask); |
Robert Richter | d436989 | 2009-04-29 12:47:19 +0200 | [diff] [blame] | 676 | x86_pmu.disable(hwc, idx); |
Ingo Molnar | 241771e | 2008-12-03 10:39:53 +0100 | [diff] [blame] | 677 | |
Ingo Molnar | 2f18d1e | 2008-12-22 11:10:42 +0100 | [diff] [blame] | 678 | /* |
| 679 | * Make sure the cleared pointer becomes visible before we |
| 680 | * (potentially) free the counter: |
| 681 | */ |
Robert Richter | 527e26a | 2009-04-29 12:47:02 +0200 | [diff] [blame] | 682 | barrier(); |
Ingo Molnar | 241771e | 2008-12-03 10:39:53 +0100 | [diff] [blame] | 683 | |
Ingo Molnar | ee06094 | 2008-12-13 09:00:03 +0100 | [diff] [blame] | 684 | /* |
| 685 | * Drain the remaining delta count out of a counter |
| 686 | * that we are disabling: |
| 687 | */ |
| 688 | x86_perf_counter_update(counter, hwc, idx); |
Robert Richter | 0953423 | 2009-04-29 12:47:16 +0200 | [diff] [blame] | 689 | cpuc->counters[idx] = NULL; |
Robert Richter | 43f6201 | 2009-04-29 16:55:56 +0200 | [diff] [blame] | 690 | clear_bit(idx, cpuc->used_mask); |
Ingo Molnar | 241771e | 2008-12-03 10:39:53 +0100 | [diff] [blame] | 691 | } |
| 692 | |
Ingo Molnar | 7e2ae34 | 2008-12-09 11:40:46 +0100 | [diff] [blame] | 693 | /* |
Ingo Molnar | ee06094 | 2008-12-13 09:00:03 +0100 | [diff] [blame] | 694 | * Save and restart an expired counter. Called by NMI contexts, |
| 695 | * so it has to be careful about preempting normal counter ops: |
Ingo Molnar | 7e2ae34 | 2008-12-09 11:40:46 +0100 | [diff] [blame] | 696 | */ |
Robert Richter | 55de0f2 | 2009-04-29 12:47:09 +0200 | [diff] [blame] | 697 | static void intel_pmu_save_and_restart(struct perf_counter *counter) |
Ingo Molnar | 241771e | 2008-12-03 10:39:53 +0100 | [diff] [blame] | 698 | { |
| 699 | struct hw_perf_counter *hwc = &counter->hw; |
| 700 | int idx = hwc->idx; |
Ingo Molnar | 241771e | 2008-12-03 10:39:53 +0100 | [diff] [blame] | 701 | |
Ingo Molnar | ee06094 | 2008-12-13 09:00:03 +0100 | [diff] [blame] | 702 | x86_perf_counter_update(counter, hwc, idx); |
Robert Richter | 26816c2 | 2009-04-29 12:47:08 +0200 | [diff] [blame] | 703 | x86_perf_counter_set_period(counter, hwc, idx); |
Ingo Molnar | 7e2ae34 | 2008-12-09 11:40:46 +0100 | [diff] [blame] | 704 | |
Ingo Molnar | 2f18d1e | 2008-12-22 11:10:42 +0100 | [diff] [blame] | 705 | if (counter->state == PERF_COUNTER_STATE_ACTIVE) |
Robert Richter | 7c90cc4 | 2009-04-29 12:47:18 +0200 | [diff] [blame] | 706 | intel_pmu_enable_counter(hwc, idx); |
Ingo Molnar | 241771e | 2008-12-03 10:39:53 +0100 | [diff] [blame] | 707 | } |
| 708 | |
Ingo Molnar | 241771e | 2008-12-03 10:39:53 +0100 | [diff] [blame] | 709 | /* |
Mike Galbraith | 4b39fd9 | 2009-01-23 14:36:16 +0100 | [diff] [blame] | 710 | * Maximum interrupt frequency of 100KHz per CPU |
| 711 | */ |
Jaswinder Singh Rajput | 169e41e | 2009-02-28 18:37:49 +0530 | [diff] [blame] | 712 | #define PERFMON_MAX_INTERRUPTS (100000/HZ) |
Mike Galbraith | 4b39fd9 | 2009-01-23 14:36:16 +0100 | [diff] [blame] | 713 | |
| 714 | /* |
Ingo Molnar | 241771e | 2008-12-03 10:39:53 +0100 | [diff] [blame] | 715 | * This handler is triggered by the local APIC, so the APIC IRQ handling |
| 716 | * rules apply: |
| 717 | */ |
Robert Richter | 39d81ea | 2009-04-29 12:47:05 +0200 | [diff] [blame] | 718 | static int intel_pmu_handle_irq(struct pt_regs *regs, int nmi) |
Ingo Molnar | 241771e | 2008-12-03 10:39:53 +0100 | [diff] [blame] | 719 | { |
| 720 | int bit, cpu = smp_processor_id(); |
Mike Galbraith | 4b39fd9 | 2009-01-23 14:36:16 +0100 | [diff] [blame] | 721 | u64 ack, status; |
Mike Galbraith | 1b023a9 | 2009-01-23 10:13:01 +0100 | [diff] [blame] | 722 | struct cpu_hw_counters *cpuc = &per_cpu(cpu_hw_counters, cpu); |
Ingo Molnar | 43874d2 | 2008-12-09 12:23:59 +0100 | [diff] [blame] | 723 | |
Peter Zijlstra | 9e35ad3 | 2009-05-13 16:21:38 +0200 | [diff] [blame] | 724 | perf_disable(); |
Robert Richter | 19d84da | 2009-04-29 12:47:25 +0200 | [diff] [blame] | 725 | status = intel_pmu_get_status(); |
Peter Zijlstra | 9e35ad3 | 2009-05-13 16:21:38 +0200 | [diff] [blame] | 726 | if (!status) { |
| 727 | perf_enable(); |
| 728 | return 0; |
| 729 | } |
Ingo Molnar | 87b9cf4 | 2008-12-08 14:20:16 +0100 | [diff] [blame] | 730 | |
Ingo Molnar | 241771e | 2008-12-03 10:39:53 +0100 | [diff] [blame] | 731 | again: |
Mike Galbraith | d278c48 | 2009-02-09 07:38:50 +0100 | [diff] [blame] | 732 | inc_irq_stat(apic_perf_irqs); |
Ingo Molnar | 241771e | 2008-12-03 10:39:53 +0100 | [diff] [blame] | 733 | ack = status; |
Ingo Molnar | 2f18d1e | 2008-12-22 11:10:42 +0100 | [diff] [blame] | 734 | for_each_bit(bit, (unsigned long *)&status, X86_PMC_IDX_MAX) { |
Ingo Molnar | 862a1a5 | 2008-12-17 13:09:20 +0100 | [diff] [blame] | 735 | struct perf_counter *counter = cpuc->counters[bit]; |
Ingo Molnar | 241771e | 2008-12-03 10:39:53 +0100 | [diff] [blame] | 736 | |
| 737 | clear_bit(bit, (unsigned long *) &status); |
Robert Richter | 43f6201 | 2009-04-29 16:55:56 +0200 | [diff] [blame] | 738 | if (!test_bit(bit, cpuc->active_mask)) |
Ingo Molnar | 241771e | 2008-12-03 10:39:53 +0100 | [diff] [blame] | 739 | continue; |
| 740 | |
Robert Richter | 55de0f2 | 2009-04-29 12:47:09 +0200 | [diff] [blame] | 741 | intel_pmu_save_and_restart(counter); |
Peter Zijlstra | 78f13e9 | 2009-04-08 15:01:33 +0200 | [diff] [blame] | 742 | if (perf_counter_overflow(counter, nmi, regs, 0)) |
Robert Richter | d436989 | 2009-04-29 12:47:19 +0200 | [diff] [blame] | 743 | intel_pmu_disable_counter(&counter->hw, bit); |
Ingo Molnar | 241771e | 2008-12-03 10:39:53 +0100 | [diff] [blame] | 744 | } |
| 745 | |
Robert Richter | dee5d90 | 2009-04-29 12:47:07 +0200 | [diff] [blame] | 746 | intel_pmu_ack_status(ack); |
Ingo Molnar | 241771e | 2008-12-03 10:39:53 +0100 | [diff] [blame] | 747 | |
| 748 | /* |
| 749 | * Repeat if there is more work to be done: |
| 750 | */ |
Robert Richter | 19d84da | 2009-04-29 12:47:25 +0200 | [diff] [blame] | 751 | status = intel_pmu_get_status(); |
Ingo Molnar | 241771e | 2008-12-03 10:39:53 +0100 | [diff] [blame] | 752 | if (status) |
| 753 | goto again; |
Peter Zijlstra | b0f3f28 | 2009-03-05 18:08:27 +0100 | [diff] [blame] | 754 | |
Peter Zijlstra | 9e35ad3 | 2009-05-13 16:21:38 +0200 | [diff] [blame] | 755 | if (++cpuc->interrupts != PERFMON_MAX_INTERRUPTS) |
| 756 | perf_enable(); |
| 757 | |
| 758 | return 1; |
Mike Galbraith | 1b023a9 | 2009-01-23 10:13:01 +0100 | [diff] [blame] | 759 | } |
| 760 | |
Robert Richter | a29aa8a | 2009-04-29 12:47:21 +0200 | [diff] [blame] | 761 | static int amd_pmu_handle_irq(struct pt_regs *regs, int nmi) |
| 762 | { |
| 763 | int cpu = smp_processor_id(); |
| 764 | struct cpu_hw_counters *cpuc = &per_cpu(cpu_hw_counters, cpu); |
| 765 | u64 val; |
| 766 | int handled = 0; |
| 767 | struct perf_counter *counter; |
| 768 | struct hw_perf_counter *hwc; |
Peter Zijlstra | 962bf7a | 2009-05-13 13:21:36 +0200 | [diff] [blame] | 769 | int idx, throttle = 0; |
Robert Richter | a29aa8a | 2009-04-29 12:47:21 +0200 | [diff] [blame] | 770 | |
Peter Zijlstra | 9e35ad3 | 2009-05-13 16:21:38 +0200 | [diff] [blame] | 771 | if (++cpuc->interrupts == PERFMON_MAX_INTERRUPTS) { |
| 772 | throttle = 1; |
| 773 | __perf_disable(); |
| 774 | cpuc->enabled = 0; |
| 775 | barrier(); |
Peter Zijlstra | 962bf7a | 2009-05-13 13:21:36 +0200 | [diff] [blame] | 776 | } |
| 777 | |
Robert Richter | a29aa8a | 2009-04-29 12:47:21 +0200 | [diff] [blame] | 778 | for (idx = 0; idx < x86_pmu.num_counters; idx++) { |
Peter Zijlstra | 962bf7a | 2009-05-13 13:21:36 +0200 | [diff] [blame] | 779 | int disable = 0; |
| 780 | |
Robert Richter | 43f6201 | 2009-04-29 16:55:56 +0200 | [diff] [blame] | 781 | if (!test_bit(idx, cpuc->active_mask)) |
Robert Richter | a29aa8a | 2009-04-29 12:47:21 +0200 | [diff] [blame] | 782 | continue; |
Peter Zijlstra | 962bf7a | 2009-05-13 13:21:36 +0200 | [diff] [blame] | 783 | |
Robert Richter | a29aa8a | 2009-04-29 12:47:21 +0200 | [diff] [blame] | 784 | counter = cpuc->counters[idx]; |
| 785 | hwc = &counter->hw; |
Peter Zijlstra | a4016a7 | 2009-05-14 14:52:17 +0200 | [diff] [blame^] | 786 | |
| 787 | if (counter->hw_event.nmi != nmi) |
| 788 | goto next; |
| 789 | |
Robert Richter | 4b7bfd0 | 2009-04-29 12:47:22 +0200 | [diff] [blame] | 790 | val = x86_perf_counter_update(counter, hwc, idx); |
Robert Richter | a29aa8a | 2009-04-29 12:47:21 +0200 | [diff] [blame] | 791 | if (val & (1ULL << (x86_pmu.counter_bits - 1))) |
Peter Zijlstra | 962bf7a | 2009-05-13 13:21:36 +0200 | [diff] [blame] | 792 | goto next; |
| 793 | |
Robert Richter | a29aa8a | 2009-04-29 12:47:21 +0200 | [diff] [blame] | 794 | /* counter overflow */ |
| 795 | x86_perf_counter_set_period(counter, hwc, idx); |
| 796 | handled = 1; |
| 797 | inc_irq_stat(apic_perf_irqs); |
Peter Zijlstra | 962bf7a | 2009-05-13 13:21:36 +0200 | [diff] [blame] | 798 | disable = perf_counter_overflow(counter, nmi, regs, 0); |
| 799 | |
| 800 | next: |
| 801 | if (disable || throttle) |
Robert Richter | a29aa8a | 2009-04-29 12:47:21 +0200 | [diff] [blame] | 802 | amd_pmu_disable_counter(hwc, idx); |
Robert Richter | a29aa8a | 2009-04-29 12:47:21 +0200 | [diff] [blame] | 803 | } |
Peter Zijlstra | 962bf7a | 2009-05-13 13:21:36 +0200 | [diff] [blame] | 804 | |
Robert Richter | a29aa8a | 2009-04-29 12:47:21 +0200 | [diff] [blame] | 805 | return handled; |
| 806 | } |
Robert Richter | 39d81ea | 2009-04-29 12:47:05 +0200 | [diff] [blame] | 807 | |
Mike Galbraith | 1b023a9 | 2009-01-23 10:13:01 +0100 | [diff] [blame] | 808 | void perf_counter_unthrottle(void) |
| 809 | { |
| 810 | struct cpu_hw_counters *cpuc; |
| 811 | |
Robert Richter | 85cf9db | 2009-04-29 12:47:20 +0200 | [diff] [blame] | 812 | if (!x86_pmu_initialized()) |
Mike Galbraith | 1b023a9 | 2009-01-23 10:13:01 +0100 | [diff] [blame] | 813 | return; |
| 814 | |
Peter Zijlstra | b0f3f28 | 2009-03-05 18:08:27 +0100 | [diff] [blame] | 815 | cpuc = &__get_cpu_var(cpu_hw_counters); |
Mike Galbraith | 4b39fd9 | 2009-01-23 14:36:16 +0100 | [diff] [blame] | 816 | if (cpuc->interrupts >= PERFMON_MAX_INTERRUPTS) { |
Ingo Molnar | f5a5a2f | 2009-05-13 12:54:01 +0200 | [diff] [blame] | 817 | /* |
| 818 | * Clear them before re-enabling irqs/NMIs again: |
| 819 | */ |
| 820 | cpuc->interrupts = 0; |
Peter Zijlstra | 9e35ad3 | 2009-05-13 16:21:38 +0200 | [diff] [blame] | 821 | perf_enable(); |
Ingo Molnar | f5a5a2f | 2009-05-13 12:54:01 +0200 | [diff] [blame] | 822 | } else { |
| 823 | cpuc->interrupts = 0; |
Mike Galbraith | 1b023a9 | 2009-01-23 10:13:01 +0100 | [diff] [blame] | 824 | } |
Ingo Molnar | 241771e | 2008-12-03 10:39:53 +0100 | [diff] [blame] | 825 | } |
| 826 | |
| 827 | void smp_perf_counter_interrupt(struct pt_regs *regs) |
| 828 | { |
| 829 | irq_enter(); |
Ingo Molnar | 241771e | 2008-12-03 10:39:53 +0100 | [diff] [blame] | 830 | apic_write(APIC_LVTPC, LOCAL_PERF_VECTOR); |
Peter Zijlstra | b0f3f28 | 2009-03-05 18:08:27 +0100 | [diff] [blame] | 831 | ack_APIC_irq(); |
Robert Richter | 4a06bd8 | 2009-04-29 12:47:11 +0200 | [diff] [blame] | 832 | x86_pmu.handle_irq(regs, 0); |
Ingo Molnar | 241771e | 2008-12-03 10:39:53 +0100 | [diff] [blame] | 833 | irq_exit(); |
| 834 | } |
| 835 | |
Peter Zijlstra | b6276f3 | 2009-04-06 11:45:03 +0200 | [diff] [blame] | 836 | void smp_perf_pending_interrupt(struct pt_regs *regs) |
| 837 | { |
| 838 | irq_enter(); |
| 839 | ack_APIC_irq(); |
| 840 | inc_irq_stat(apic_pending_irqs); |
| 841 | perf_counter_do_pending(); |
| 842 | irq_exit(); |
| 843 | } |
| 844 | |
| 845 | void set_perf_counter_pending(void) |
| 846 | { |
| 847 | apic->send_IPI_self(LOCAL_PENDING_VECTOR); |
| 848 | } |
| 849 | |
Mike Galbraith | 3415dd9 | 2009-01-23 14:16:53 +0100 | [diff] [blame] | 850 | void perf_counters_lapic_init(int nmi) |
Ingo Molnar | 241771e | 2008-12-03 10:39:53 +0100 | [diff] [blame] | 851 | { |
| 852 | u32 apic_val; |
| 853 | |
Robert Richter | 85cf9db | 2009-04-29 12:47:20 +0200 | [diff] [blame] | 854 | if (!x86_pmu_initialized()) |
Ingo Molnar | 241771e | 2008-12-03 10:39:53 +0100 | [diff] [blame] | 855 | return; |
Robert Richter | 85cf9db | 2009-04-29 12:47:20 +0200 | [diff] [blame] | 856 | |
Ingo Molnar | 241771e | 2008-12-03 10:39:53 +0100 | [diff] [blame] | 857 | /* |
| 858 | * Enable the performance counter vector in the APIC LVT: |
| 859 | */ |
| 860 | apic_val = apic_read(APIC_LVTERR); |
| 861 | |
| 862 | apic_write(APIC_LVTERR, apic_val | APIC_LVT_MASKED); |
| 863 | if (nmi) |
| 864 | apic_write(APIC_LVTPC, APIC_DM_NMI); |
| 865 | else |
| 866 | apic_write(APIC_LVTPC, LOCAL_PERF_VECTOR); |
| 867 | apic_write(APIC_LVTERR, apic_val); |
| 868 | } |
| 869 | |
| 870 | static int __kprobes |
| 871 | perf_counter_nmi_handler(struct notifier_block *self, |
| 872 | unsigned long cmd, void *__args) |
| 873 | { |
| 874 | struct die_args *args = __args; |
| 875 | struct pt_regs *regs; |
| 876 | |
Peter Zijlstra | ba77813 | 2009-05-04 18:47:44 +0200 | [diff] [blame] | 877 | if (!atomic_read(&active_counters)) |
Peter Zijlstra | 63a809a | 2009-05-01 12:23:17 +0200 | [diff] [blame] | 878 | return NOTIFY_DONE; |
| 879 | |
Peter Zijlstra | b0f3f28 | 2009-03-05 18:08:27 +0100 | [diff] [blame] | 880 | switch (cmd) { |
| 881 | case DIE_NMI: |
| 882 | case DIE_NMI_IPI: |
| 883 | break; |
| 884 | |
| 885 | default: |
Ingo Molnar | 241771e | 2008-12-03 10:39:53 +0100 | [diff] [blame] | 886 | return NOTIFY_DONE; |
Peter Zijlstra | b0f3f28 | 2009-03-05 18:08:27 +0100 | [diff] [blame] | 887 | } |
Ingo Molnar | 241771e | 2008-12-03 10:39:53 +0100 | [diff] [blame] | 888 | |
| 889 | regs = args->regs; |
| 890 | |
| 891 | apic_write(APIC_LVTPC, APIC_DM_NMI); |
Peter Zijlstra | a4016a7 | 2009-05-14 14:52:17 +0200 | [diff] [blame^] | 892 | /* |
| 893 | * Can't rely on the handled return value to say it was our NMI, two |
| 894 | * counters could trigger 'simultaneously' raising two back-to-back NMIs. |
| 895 | * |
| 896 | * If the first NMI handles both, the latter will be empty and daze |
| 897 | * the CPU. |
| 898 | */ |
| 899 | x86_pmu.handle_irq(regs, 1); |
Ingo Molnar | 241771e | 2008-12-03 10:39:53 +0100 | [diff] [blame] | 900 | |
Peter Zijlstra | a4016a7 | 2009-05-14 14:52:17 +0200 | [diff] [blame^] | 901 | return NOTIFY_STOP; |
Ingo Molnar | 241771e | 2008-12-03 10:39:53 +0100 | [diff] [blame] | 902 | } |
| 903 | |
| 904 | static __read_mostly struct notifier_block perf_counter_nmi_notifier = { |
Mike Galbraith | 5b75af0 | 2009-02-04 17:11:34 +0100 | [diff] [blame] | 905 | .notifier_call = perf_counter_nmi_handler, |
| 906 | .next = NULL, |
| 907 | .priority = 1 |
Ingo Molnar | 241771e | 2008-12-03 10:39:53 +0100 | [diff] [blame] | 908 | }; |
| 909 | |
Robert Richter | 5f4ec28 | 2009-04-29 12:47:04 +0200 | [diff] [blame] | 910 | static struct x86_pmu intel_pmu = { |
Robert Richter | faa28ae | 2009-04-29 12:47:13 +0200 | [diff] [blame] | 911 | .name = "Intel", |
Robert Richter | 39d81ea | 2009-04-29 12:47:05 +0200 | [diff] [blame] | 912 | .handle_irq = intel_pmu_handle_irq, |
Peter Zijlstra | 9e35ad3 | 2009-05-13 16:21:38 +0200 | [diff] [blame] | 913 | .disable_all = intel_pmu_disable_all, |
| 914 | .enable_all = intel_pmu_enable_all, |
Robert Richter | 5f4ec28 | 2009-04-29 12:47:04 +0200 | [diff] [blame] | 915 | .enable = intel_pmu_enable_counter, |
| 916 | .disable = intel_pmu_disable_counter, |
Jaswinder Singh Rajput | b56a380 | 2009-02-27 18:09:09 +0530 | [diff] [blame] | 917 | .eventsel = MSR_ARCH_PERFMON_EVENTSEL0, |
| 918 | .perfctr = MSR_ARCH_PERFMON_PERFCTR0, |
Robert Richter | 5f4ec28 | 2009-04-29 12:47:04 +0200 | [diff] [blame] | 919 | .event_map = intel_pmu_event_map, |
| 920 | .raw_event = intel_pmu_raw_event, |
Jaswinder Singh Rajput | b56a380 | 2009-02-27 18:09:09 +0530 | [diff] [blame] | 921 | .max_events = ARRAY_SIZE(intel_perfmon_event_map), |
Robert Richter | c619b8f | 2009-04-29 12:47:23 +0200 | [diff] [blame] | 922 | /* |
| 923 | * Intel PMCs cannot be accessed sanely above 32 bit width, |
| 924 | * so we install an artificial 1<<31 period regardless of |
| 925 | * the generic counter period: |
| 926 | */ |
| 927 | .max_period = (1ULL << 31) - 1, |
Jaswinder Singh Rajput | b56a380 | 2009-02-27 18:09:09 +0530 | [diff] [blame] | 928 | }; |
| 929 | |
Robert Richter | 5f4ec28 | 2009-04-29 12:47:04 +0200 | [diff] [blame] | 930 | static struct x86_pmu amd_pmu = { |
Robert Richter | faa28ae | 2009-04-29 12:47:13 +0200 | [diff] [blame] | 931 | .name = "AMD", |
Robert Richter | 39d81ea | 2009-04-29 12:47:05 +0200 | [diff] [blame] | 932 | .handle_irq = amd_pmu_handle_irq, |
Peter Zijlstra | 9e35ad3 | 2009-05-13 16:21:38 +0200 | [diff] [blame] | 933 | .disable_all = amd_pmu_disable_all, |
| 934 | .enable_all = amd_pmu_enable_all, |
Robert Richter | 5f4ec28 | 2009-04-29 12:47:04 +0200 | [diff] [blame] | 935 | .enable = amd_pmu_enable_counter, |
| 936 | .disable = amd_pmu_disable_counter, |
Jaswinder Singh Rajput | f87ad35 | 2009-02-27 20:15:14 +0530 | [diff] [blame] | 937 | .eventsel = MSR_K7_EVNTSEL0, |
| 938 | .perfctr = MSR_K7_PERFCTR0, |
Robert Richter | 5f4ec28 | 2009-04-29 12:47:04 +0200 | [diff] [blame] | 939 | .event_map = amd_pmu_event_map, |
| 940 | .raw_event = amd_pmu_raw_event, |
Jaswinder Singh Rajput | f87ad35 | 2009-02-27 20:15:14 +0530 | [diff] [blame] | 941 | .max_events = ARRAY_SIZE(amd_perfmon_event_map), |
Robert Richter | 0933e5c | 2009-04-29 12:47:12 +0200 | [diff] [blame] | 942 | .num_counters = 4, |
| 943 | .counter_bits = 48, |
| 944 | .counter_mask = (1ULL << 48) - 1, |
Robert Richter | c619b8f | 2009-04-29 12:47:23 +0200 | [diff] [blame] | 945 | /* use highest bit to detect overflow */ |
| 946 | .max_period = (1ULL << 47) - 1, |
Jaswinder Singh Rajput | f87ad35 | 2009-02-27 20:15:14 +0530 | [diff] [blame] | 947 | }; |
| 948 | |
Robert Richter | 72eae04 | 2009-04-29 12:47:10 +0200 | [diff] [blame] | 949 | static int intel_pmu_init(void) |
Ingo Molnar | 241771e | 2008-12-03 10:39:53 +0100 | [diff] [blame] | 950 | { |
Ingo Molnar | 703e937 | 2008-12-17 10:51:15 +0100 | [diff] [blame] | 951 | union cpuid10_edx edx; |
Ingo Molnar | 7bb497b | 2009-03-18 08:59:21 +0100 | [diff] [blame] | 952 | union cpuid10_eax eax; |
| 953 | unsigned int unused; |
| 954 | unsigned int ebx; |
Robert Richter | faa28ae | 2009-04-29 12:47:13 +0200 | [diff] [blame] | 955 | int version; |
Ingo Molnar | 241771e | 2008-12-03 10:39:53 +0100 | [diff] [blame] | 956 | |
Robert Richter | da1a776 | 2009-04-29 12:46:58 +0200 | [diff] [blame] | 957 | if (!cpu_has(&boot_cpu_data, X86_FEATURE_ARCH_PERFMON)) |
Robert Richter | 72eae04 | 2009-04-29 12:47:10 +0200 | [diff] [blame] | 958 | return -ENODEV; |
Robert Richter | da1a776 | 2009-04-29 12:46:58 +0200 | [diff] [blame] | 959 | |
Ingo Molnar | 241771e | 2008-12-03 10:39:53 +0100 | [diff] [blame] | 960 | /* |
| 961 | * Check whether the Architectural PerfMon supports |
| 962 | * Branch Misses Retired Event or not. |
| 963 | */ |
Ingo Molnar | 703e937 | 2008-12-17 10:51:15 +0100 | [diff] [blame] | 964 | cpuid(10, &eax.full, &ebx, &unused, &edx.full); |
Ingo Molnar | 241771e | 2008-12-03 10:39:53 +0100 | [diff] [blame] | 965 | if (eax.split.mask_length <= ARCH_PERFMON_BRANCH_MISSES_RETIRED) |
Robert Richter | 72eae04 | 2009-04-29 12:47:10 +0200 | [diff] [blame] | 966 | return -ENODEV; |
Ingo Molnar | 241771e | 2008-12-03 10:39:53 +0100 | [diff] [blame] | 967 | |
Robert Richter | faa28ae | 2009-04-29 12:47:13 +0200 | [diff] [blame] | 968 | version = eax.split.version_id; |
| 969 | if (version < 2) |
Robert Richter | 72eae04 | 2009-04-29 12:47:10 +0200 | [diff] [blame] | 970 | return -ENODEV; |
Ingo Molnar | 7bb497b | 2009-03-18 08:59:21 +0100 | [diff] [blame] | 971 | |
Robert Richter | 4a06bd8 | 2009-04-29 12:47:11 +0200 | [diff] [blame] | 972 | x86_pmu = intel_pmu; |
Robert Richter | faa28ae | 2009-04-29 12:47:13 +0200 | [diff] [blame] | 973 | x86_pmu.version = version; |
Robert Richter | 0933e5c | 2009-04-29 12:47:12 +0200 | [diff] [blame] | 974 | x86_pmu.num_counters = eax.split.num_counters; |
Ingo Molnar | 066d7de | 2009-05-04 19:04:09 +0200 | [diff] [blame] | 975 | |
| 976 | /* |
| 977 | * Quirk: v2 perfmon does not report fixed-purpose counters, so |
| 978 | * assume at least 3 counters: |
| 979 | */ |
| 980 | x86_pmu.num_counters_fixed = max((int)edx.split.num_counters_fixed, 3); |
| 981 | |
Robert Richter | 0933e5c | 2009-04-29 12:47:12 +0200 | [diff] [blame] | 982 | x86_pmu.counter_bits = eax.split.bit_width; |
| 983 | x86_pmu.counter_mask = (1ULL << eax.split.bit_width) - 1; |
Jaswinder Singh Rajput | b56a380 | 2009-02-27 18:09:09 +0530 | [diff] [blame] | 984 | |
Peter Zijlstra | 9e35ad3 | 2009-05-13 16:21:38 +0200 | [diff] [blame] | 985 | rdmsrl(MSR_CORE_PERF_GLOBAL_CTRL, x86_pmu.intel_ctrl); |
| 986 | |
Robert Richter | 72eae04 | 2009-04-29 12:47:10 +0200 | [diff] [blame] | 987 | return 0; |
Jaswinder Singh Rajput | b56a380 | 2009-02-27 18:09:09 +0530 | [diff] [blame] | 988 | } |
| 989 | |
Robert Richter | 72eae04 | 2009-04-29 12:47:10 +0200 | [diff] [blame] | 990 | static int amd_pmu_init(void) |
Jaswinder Singh Rajput | f87ad35 | 2009-02-27 20:15:14 +0530 | [diff] [blame] | 991 | { |
Robert Richter | 4a06bd8 | 2009-04-29 12:47:11 +0200 | [diff] [blame] | 992 | x86_pmu = amd_pmu; |
Robert Richter | 72eae04 | 2009-04-29 12:47:10 +0200 | [diff] [blame] | 993 | return 0; |
Jaswinder Singh Rajput | f87ad35 | 2009-02-27 20:15:14 +0530 | [diff] [blame] | 994 | } |
| 995 | |
Jaswinder Singh Rajput | b56a380 | 2009-02-27 18:09:09 +0530 | [diff] [blame] | 996 | void __init init_hw_perf_counters(void) |
| 997 | { |
Robert Richter | 72eae04 | 2009-04-29 12:47:10 +0200 | [diff] [blame] | 998 | int err; |
| 999 | |
Jaswinder Singh Rajput | b56a380 | 2009-02-27 18:09:09 +0530 | [diff] [blame] | 1000 | switch (boot_cpu_data.x86_vendor) { |
| 1001 | case X86_VENDOR_INTEL: |
Robert Richter | 72eae04 | 2009-04-29 12:47:10 +0200 | [diff] [blame] | 1002 | err = intel_pmu_init(); |
Jaswinder Singh Rajput | b56a380 | 2009-02-27 18:09:09 +0530 | [diff] [blame] | 1003 | break; |
Jaswinder Singh Rajput | f87ad35 | 2009-02-27 20:15:14 +0530 | [diff] [blame] | 1004 | case X86_VENDOR_AMD: |
Robert Richter | 72eae04 | 2009-04-29 12:47:10 +0200 | [diff] [blame] | 1005 | err = amd_pmu_init(); |
Jaswinder Singh Rajput | f87ad35 | 2009-02-27 20:15:14 +0530 | [diff] [blame] | 1006 | break; |
Robert Richter | 4138960 | 2009-04-29 12:47:00 +0200 | [diff] [blame] | 1007 | default: |
| 1008 | return; |
Jaswinder Singh Rajput | b56a380 | 2009-02-27 18:09:09 +0530 | [diff] [blame] | 1009 | } |
Robert Richter | 72eae04 | 2009-04-29 12:47:10 +0200 | [diff] [blame] | 1010 | if (err != 0) |
Jaswinder Singh Rajput | b56a380 | 2009-02-27 18:09:09 +0530 | [diff] [blame] | 1011 | return; |
| 1012 | |
Robert Richter | faa28ae | 2009-04-29 12:47:13 +0200 | [diff] [blame] | 1013 | pr_info("%s Performance Monitoring support detected.\n", x86_pmu.name); |
| 1014 | pr_info("... version: %d\n", x86_pmu.version); |
| 1015 | pr_info("... bit width: %d\n", x86_pmu.counter_bits); |
| 1016 | |
Robert Richter | 0933e5c | 2009-04-29 12:47:12 +0200 | [diff] [blame] | 1017 | pr_info("... num counters: %d\n", x86_pmu.num_counters); |
| 1018 | if (x86_pmu.num_counters > X86_PMC_MAX_GENERIC) { |
| 1019 | x86_pmu.num_counters = X86_PMC_MAX_GENERIC; |
Ingo Molnar | 241771e | 2008-12-03 10:39:53 +0100 | [diff] [blame] | 1020 | WARN(1, KERN_ERR "hw perf counters %d > max(%d), clipping!", |
Robert Richter | 0933e5c | 2009-04-29 12:47:12 +0200 | [diff] [blame] | 1021 | x86_pmu.num_counters, X86_PMC_MAX_GENERIC); |
Ingo Molnar | 241771e | 2008-12-03 10:39:53 +0100 | [diff] [blame] | 1022 | } |
Robert Richter | 0933e5c | 2009-04-29 12:47:12 +0200 | [diff] [blame] | 1023 | perf_counter_mask = (1 << x86_pmu.num_counters) - 1; |
| 1024 | perf_max_counters = x86_pmu.num_counters; |
Ingo Molnar | 241771e | 2008-12-03 10:39:53 +0100 | [diff] [blame] | 1025 | |
Robert Richter | 0933e5c | 2009-04-29 12:47:12 +0200 | [diff] [blame] | 1026 | pr_info("... value mask: %016Lx\n", x86_pmu.counter_mask); |
Robert Richter | c619b8f | 2009-04-29 12:47:23 +0200 | [diff] [blame] | 1027 | pr_info("... max period: %016Lx\n", x86_pmu.max_period); |
Ingo Molnar | 2f18d1e | 2008-12-22 11:10:42 +0100 | [diff] [blame] | 1028 | |
Robert Richter | 0933e5c | 2009-04-29 12:47:12 +0200 | [diff] [blame] | 1029 | if (x86_pmu.num_counters_fixed > X86_PMC_MAX_FIXED) { |
| 1030 | x86_pmu.num_counters_fixed = X86_PMC_MAX_FIXED; |
Ingo Molnar | 703e937 | 2008-12-17 10:51:15 +0100 | [diff] [blame] | 1031 | WARN(1, KERN_ERR "hw perf counters fixed %d > max(%d), clipping!", |
Robert Richter | 0933e5c | 2009-04-29 12:47:12 +0200 | [diff] [blame] | 1032 | x86_pmu.num_counters_fixed, X86_PMC_MAX_FIXED); |
Ingo Molnar | 703e937 | 2008-12-17 10:51:15 +0100 | [diff] [blame] | 1033 | } |
Robert Richter | 0933e5c | 2009-04-29 12:47:12 +0200 | [diff] [blame] | 1034 | pr_info("... fixed counters: %d\n", x86_pmu.num_counters_fixed); |
Ingo Molnar | 241771e | 2008-12-03 10:39:53 +0100 | [diff] [blame] | 1035 | |
Robert Richter | 0933e5c | 2009-04-29 12:47:12 +0200 | [diff] [blame] | 1036 | perf_counter_mask |= |
| 1037 | ((1LL << x86_pmu.num_counters_fixed)-1) << X86_PMC_IDX_FIXED; |
Ingo Molnar | 862a1a5 | 2008-12-17 13:09:20 +0100 | [diff] [blame] | 1038 | |
Jaswinder Singh Rajput | a1ef58f | 2009-02-28 18:45:39 +0530 | [diff] [blame] | 1039 | pr_info("... counter mask: %016Lx\n", perf_counter_mask); |
Ingo Molnar | 75f224cf | 2008-12-14 21:58:46 +0100 | [diff] [blame] | 1040 | |
Ingo Molnar | 241771e | 2008-12-03 10:39:53 +0100 | [diff] [blame] | 1041 | perf_counters_lapic_init(0); |
| 1042 | register_die_notifier(&perf_counter_nmi_notifier); |
Ingo Molnar | 241771e | 2008-12-03 10:39:53 +0100 | [diff] [blame] | 1043 | } |
Ingo Molnar | 621a01e | 2008-12-11 12:46:46 +0100 | [diff] [blame] | 1044 | |
Robert Richter | bb775fc | 2009-04-29 12:47:14 +0200 | [diff] [blame] | 1045 | static inline void x86_pmu_read(struct perf_counter *counter) |
Ingo Molnar | ee06094 | 2008-12-13 09:00:03 +0100 | [diff] [blame] | 1046 | { |
| 1047 | x86_perf_counter_update(counter, &counter->hw, counter->hw.idx); |
| 1048 | } |
| 1049 | |
Robert Richter | 4aeb0b4 | 2009-04-29 12:47:03 +0200 | [diff] [blame] | 1050 | static const struct pmu pmu = { |
| 1051 | .enable = x86_pmu_enable, |
| 1052 | .disable = x86_pmu_disable, |
| 1053 | .read = x86_pmu_read, |
Ingo Molnar | 621a01e | 2008-12-11 12:46:46 +0100 | [diff] [blame] | 1054 | }; |
| 1055 | |
Robert Richter | 4aeb0b4 | 2009-04-29 12:47:03 +0200 | [diff] [blame] | 1056 | const struct pmu *hw_perf_counter_init(struct perf_counter *counter) |
Ingo Molnar | 621a01e | 2008-12-11 12:46:46 +0100 | [diff] [blame] | 1057 | { |
| 1058 | int err; |
| 1059 | |
| 1060 | err = __hw_perf_counter_init(counter); |
| 1061 | if (err) |
Peter Zijlstra | 9ea98e1 | 2009-03-30 19:07:09 +0200 | [diff] [blame] | 1062 | return ERR_PTR(err); |
Ingo Molnar | 621a01e | 2008-12-11 12:46:46 +0100 | [diff] [blame] | 1063 | |
Robert Richter | 4aeb0b4 | 2009-04-29 12:47:03 +0200 | [diff] [blame] | 1064 | return &pmu; |
Ingo Molnar | 621a01e | 2008-12-11 12:46:46 +0100 | [diff] [blame] | 1065 | } |
Peter Zijlstra | d7d59fb | 2009-03-30 19:07:15 +0200 | [diff] [blame] | 1066 | |
| 1067 | /* |
| 1068 | * callchain support |
| 1069 | */ |
| 1070 | |
| 1071 | static inline |
| 1072 | void callchain_store(struct perf_callchain_entry *entry, unsigned long ip) |
| 1073 | { |
| 1074 | if (entry->nr < MAX_STACK_DEPTH) |
| 1075 | entry->ip[entry->nr++] = ip; |
| 1076 | } |
| 1077 | |
| 1078 | static DEFINE_PER_CPU(struct perf_callchain_entry, irq_entry); |
| 1079 | static DEFINE_PER_CPU(struct perf_callchain_entry, nmi_entry); |
| 1080 | |
| 1081 | |
| 1082 | static void |
| 1083 | backtrace_warning_symbol(void *data, char *msg, unsigned long symbol) |
| 1084 | { |
| 1085 | /* Ignore warnings */ |
| 1086 | } |
| 1087 | |
| 1088 | static void backtrace_warning(void *data, char *msg) |
| 1089 | { |
| 1090 | /* Ignore warnings */ |
| 1091 | } |
| 1092 | |
| 1093 | static int backtrace_stack(void *data, char *name) |
| 1094 | { |
| 1095 | /* Don't bother with IRQ stacks for now */ |
| 1096 | return -1; |
| 1097 | } |
| 1098 | |
| 1099 | static void backtrace_address(void *data, unsigned long addr, int reliable) |
| 1100 | { |
| 1101 | struct perf_callchain_entry *entry = data; |
| 1102 | |
| 1103 | if (reliable) |
| 1104 | callchain_store(entry, addr); |
| 1105 | } |
| 1106 | |
| 1107 | static const struct stacktrace_ops backtrace_ops = { |
| 1108 | .warning = backtrace_warning, |
| 1109 | .warning_symbol = backtrace_warning_symbol, |
| 1110 | .stack = backtrace_stack, |
| 1111 | .address = backtrace_address, |
| 1112 | }; |
| 1113 | |
| 1114 | static void |
| 1115 | perf_callchain_kernel(struct pt_regs *regs, struct perf_callchain_entry *entry) |
| 1116 | { |
| 1117 | unsigned long bp; |
| 1118 | char *stack; |
Peter Zijlstra | 5872bdb8 | 2009-04-02 11:12:03 +0200 | [diff] [blame] | 1119 | int nr = entry->nr; |
Peter Zijlstra | d7d59fb | 2009-03-30 19:07:15 +0200 | [diff] [blame] | 1120 | |
| 1121 | callchain_store(entry, instruction_pointer(regs)); |
| 1122 | |
| 1123 | stack = ((char *)regs + sizeof(struct pt_regs)); |
| 1124 | #ifdef CONFIG_FRAME_POINTER |
| 1125 | bp = frame_pointer(regs); |
| 1126 | #else |
| 1127 | bp = 0; |
| 1128 | #endif |
| 1129 | |
| 1130 | dump_trace(NULL, regs, (void *)stack, bp, &backtrace_ops, entry); |
Peter Zijlstra | 5872bdb8 | 2009-04-02 11:12:03 +0200 | [diff] [blame] | 1131 | |
| 1132 | entry->kernel = entry->nr - nr; |
Peter Zijlstra | d7d59fb | 2009-03-30 19:07:15 +0200 | [diff] [blame] | 1133 | } |
| 1134 | |
| 1135 | |
| 1136 | struct stack_frame { |
| 1137 | const void __user *next_fp; |
| 1138 | unsigned long return_address; |
| 1139 | }; |
| 1140 | |
| 1141 | static int copy_stack_frame(const void __user *fp, struct stack_frame *frame) |
| 1142 | { |
| 1143 | int ret; |
| 1144 | |
| 1145 | if (!access_ok(VERIFY_READ, fp, sizeof(*frame))) |
| 1146 | return 0; |
| 1147 | |
| 1148 | ret = 1; |
| 1149 | pagefault_disable(); |
| 1150 | if (__copy_from_user_inatomic(frame, fp, sizeof(*frame))) |
| 1151 | ret = 0; |
| 1152 | pagefault_enable(); |
| 1153 | |
| 1154 | return ret; |
| 1155 | } |
| 1156 | |
| 1157 | static void |
| 1158 | perf_callchain_user(struct pt_regs *regs, struct perf_callchain_entry *entry) |
| 1159 | { |
| 1160 | struct stack_frame frame; |
| 1161 | const void __user *fp; |
Peter Zijlstra | 5872bdb8 | 2009-04-02 11:12:03 +0200 | [diff] [blame] | 1162 | int nr = entry->nr; |
Peter Zijlstra | d7d59fb | 2009-03-30 19:07:15 +0200 | [diff] [blame] | 1163 | |
| 1164 | regs = (struct pt_regs *)current->thread.sp0 - 1; |
| 1165 | fp = (void __user *)regs->bp; |
| 1166 | |
| 1167 | callchain_store(entry, regs->ip); |
| 1168 | |
| 1169 | while (entry->nr < MAX_STACK_DEPTH) { |
| 1170 | frame.next_fp = NULL; |
| 1171 | frame.return_address = 0; |
| 1172 | |
| 1173 | if (!copy_stack_frame(fp, &frame)) |
| 1174 | break; |
| 1175 | |
| 1176 | if ((unsigned long)fp < user_stack_pointer(regs)) |
| 1177 | break; |
| 1178 | |
| 1179 | callchain_store(entry, frame.return_address); |
| 1180 | fp = frame.next_fp; |
| 1181 | } |
Peter Zijlstra | 5872bdb8 | 2009-04-02 11:12:03 +0200 | [diff] [blame] | 1182 | |
| 1183 | entry->user = entry->nr - nr; |
Peter Zijlstra | d7d59fb | 2009-03-30 19:07:15 +0200 | [diff] [blame] | 1184 | } |
| 1185 | |
| 1186 | static void |
| 1187 | perf_do_callchain(struct pt_regs *regs, struct perf_callchain_entry *entry) |
| 1188 | { |
| 1189 | int is_user; |
| 1190 | |
| 1191 | if (!regs) |
| 1192 | return; |
| 1193 | |
| 1194 | is_user = user_mode(regs); |
| 1195 | |
| 1196 | if (!current || current->pid == 0) |
| 1197 | return; |
| 1198 | |
| 1199 | if (is_user && current->state != TASK_RUNNING) |
| 1200 | return; |
| 1201 | |
| 1202 | if (!is_user) |
| 1203 | perf_callchain_kernel(regs, entry); |
| 1204 | |
| 1205 | if (current->mm) |
| 1206 | perf_callchain_user(regs, entry); |
| 1207 | } |
| 1208 | |
| 1209 | struct perf_callchain_entry *perf_callchain(struct pt_regs *regs) |
| 1210 | { |
| 1211 | struct perf_callchain_entry *entry; |
| 1212 | |
| 1213 | if (in_nmi()) |
| 1214 | entry = &__get_cpu_var(nmi_entry); |
| 1215 | else |
| 1216 | entry = &__get_cpu_var(irq_entry); |
| 1217 | |
| 1218 | entry->nr = 0; |
Peter Zijlstra | 5872bdb8 | 2009-04-02 11:12:03 +0200 | [diff] [blame] | 1219 | entry->hv = 0; |
| 1220 | entry->kernel = 0; |
| 1221 | entry->user = 0; |
Peter Zijlstra | d7d59fb | 2009-03-30 19:07:15 +0200 | [diff] [blame] | 1222 | |
| 1223 | perf_do_callchain(regs, entry); |
| 1224 | |
| 1225 | return entry; |
| 1226 | } |