Catalin Marinas | 4f04d8f | 2012-03-05 11:49:27 +0000 | [diff] [blame] | 1 | /* |
| 2 | * Copyright (C) 2012 ARM Ltd. |
| 3 | * |
| 4 | * This program is free software; you can redistribute it and/or modify |
| 5 | * it under the terms of the GNU General Public License version 2 as |
| 6 | * published by the Free Software Foundation. |
| 7 | * |
| 8 | * This program is distributed in the hope that it will be useful, |
| 9 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 10 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 11 | * GNU General Public License for more details. |
| 12 | * |
| 13 | * You should have received a copy of the GNU General Public License |
| 14 | * along with this program. If not, see <http://www.gnu.org/licenses/>. |
| 15 | */ |
| 16 | #ifndef __ASM_PGTABLE_H |
| 17 | #define __ASM_PGTABLE_H |
| 18 | |
Catalin Marinas | 2f4b829 | 2015-07-10 17:24:28 +0100 | [diff] [blame] | 19 | #include <asm/bug.h> |
Catalin Marinas | 4f04d8f | 2012-03-05 11:49:27 +0000 | [diff] [blame] | 20 | #include <asm/proc-fns.h> |
| 21 | |
| 22 | #include <asm/memory.h> |
| 23 | #include <asm/pgtable-hwdef.h> |
Mark Rutland | 3eca86e | 2016-02-26 14:31:32 +0000 | [diff] [blame] | 24 | #include <asm/pgtable-prot.h> |
Catalin Marinas | 4f04d8f | 2012-03-05 11:49:27 +0000 | [diff] [blame] | 25 | |
| 26 | /* |
| 27 | * VMALLOC and SPARSEMEM_VMEMMAP ranges. |
Catalin Marinas | 0837519 | 2014-07-16 17:42:43 +0100 | [diff] [blame] | 28 | * |
Ard Biesheuvel | dfd55ad | 2016-02-26 17:57:13 +0100 | [diff] [blame] | 29 | * VMEMAP_SIZE: allows the whole linear region to be covered by a struct page array |
Catalin Marinas | 0837519 | 2014-07-16 17:42:43 +0100 | [diff] [blame] | 30 | * (rounded up to PUD_SIZE). |
Ard Biesheuvel | f904077 | 2016-02-16 13:52:40 +0100 | [diff] [blame] | 31 | * VMALLOC_START: beginning of the kernel vmalloc space |
Catalin Marinas | 0837519 | 2014-07-16 17:42:43 +0100 | [diff] [blame] | 32 | * VMALLOC_END: extends to the available space below vmmemmap, PCI I/O space, |
| 33 | * fixed mappings and modules |
Catalin Marinas | 4f04d8f | 2012-03-05 11:49:27 +0000 | [diff] [blame] | 34 | */ |
Ard Biesheuvel | 36e5cd6 | 2016-03-08 21:09:29 +0700 | [diff] [blame] | 35 | #define VMEMMAP_SIZE ALIGN((1UL << (VA_BITS - PAGE_SHIFT)) * sizeof(struct page), PUD_SIZE) |
Andrey Ryabinin | 39d114d | 2015-10-12 18:52:58 +0300 | [diff] [blame] | 36 | |
Ard Biesheuvel | f904077 | 2016-02-16 13:52:40 +0100 | [diff] [blame] | 37 | #define VMALLOC_START (MODULES_END) |
Catalin Marinas | 0837519 | 2014-07-16 17:42:43 +0100 | [diff] [blame] | 38 | #define VMALLOC_END (PAGE_OFFSET - PUD_SIZE - VMEMMAP_SIZE - SZ_64K) |
Catalin Marinas | 4f04d8f | 2012-03-05 11:49:27 +0000 | [diff] [blame] | 39 | |
Ard Biesheuvel | dfd55ad | 2016-02-26 17:57:13 +0100 | [diff] [blame] | 40 | #define VMEMMAP_START (VMALLOC_END + SZ_64K) |
Ard Biesheuvel | 36e5cd6 | 2016-03-08 21:09:29 +0700 | [diff] [blame] | 41 | #define vmemmap ((struct page *)VMEMMAP_START - \ |
| 42 | SECTION_ALIGN_DOWN(memstart_addr >> PAGE_SHIFT)) |
Catalin Marinas | 4f04d8f | 2012-03-05 11:49:27 +0000 | [diff] [blame] | 43 | |
Kirill A. Shutemov | d016bf7 | 2015-02-11 15:26:41 -0800 | [diff] [blame] | 44 | #define FIRST_USER_ADDRESS 0UL |
Catalin Marinas | 4f04d8f | 2012-03-05 11:49:27 +0000 | [diff] [blame] | 45 | |
| 46 | #ifndef __ASSEMBLY__ |
Catalin Marinas | 2f4b829 | 2015-07-10 17:24:28 +0100 | [diff] [blame] | 47 | |
Mark Rutland | 961faac | 2016-01-25 11:45:07 +0000 | [diff] [blame] | 48 | #include <asm/fixmap.h> |
Catalin Marinas | 2f4b829 | 2015-07-10 17:24:28 +0100 | [diff] [blame] | 49 | #include <linux/mmdebug.h> |
| 50 | |
Catalin Marinas | 4f04d8f | 2012-03-05 11:49:27 +0000 | [diff] [blame] | 51 | extern void __pte_error(const char *file, int line, unsigned long val); |
| 52 | extern void __pmd_error(const char *file, int line, unsigned long val); |
Jungseok Lee | c79b954 | 2014-05-12 18:40:51 +0900 | [diff] [blame] | 53 | extern void __pud_error(const char *file, int line, unsigned long val); |
Catalin Marinas | 4f04d8f | 2012-03-05 11:49:27 +0000 | [diff] [blame] | 54 | extern void __pgd_error(const char *file, int line, unsigned long val); |
| 55 | |
Catalin Marinas | 4f04d8f | 2012-03-05 11:49:27 +0000 | [diff] [blame] | 56 | /* |
| 57 | * ZERO_PAGE is a global shared page that is always zero: used |
| 58 | * for zero-mapped memory areas etc.. |
| 59 | */ |
Mark Rutland | 5227cfa | 2016-01-25 11:44:57 +0000 | [diff] [blame] | 60 | extern unsigned long empty_zero_page[PAGE_SIZE / sizeof(unsigned long)]; |
| 61 | #define ZERO_PAGE(vaddr) virt_to_page(empty_zero_page) |
Catalin Marinas | 4f04d8f | 2012-03-05 11:49:27 +0000 | [diff] [blame] | 62 | |
Catalin Marinas | 7078db4 | 2014-07-21 14:52:49 +0100 | [diff] [blame] | 63 | #define pte_ERROR(pte) __pte_error(__FILE__, __LINE__, pte_val(pte)) |
| 64 | |
Catalin Marinas | 4f04d8f | 2012-03-05 11:49:27 +0000 | [diff] [blame] | 65 | #define pte_pfn(pte) ((pte_val(pte) & PHYS_MASK) >> PAGE_SHIFT) |
| 66 | |
| 67 | #define pfn_pte(pfn,prot) (__pte(((phys_addr_t)(pfn) << PAGE_SHIFT) | pgprot_val(prot))) |
| 68 | |
| 69 | #define pte_none(pte) (!pte_val(pte)) |
| 70 | #define pte_clear(mm,addr,ptep) set_pte(ptep, __pte(0)) |
| 71 | #define pte_page(pte) (pfn_to_page(pte_pfn(pte))) |
Catalin Marinas | 7078db4 | 2014-07-21 14:52:49 +0100 | [diff] [blame] | 72 | |
Catalin Marinas | 4f04d8f | 2012-03-05 11:49:27 +0000 | [diff] [blame] | 73 | /* |
| 74 | * The following only work if pte_present(). Undefined behaviour otherwise. |
| 75 | */ |
Steve Capper | 84fe682 | 2014-02-25 11:38:53 +0000 | [diff] [blame] | 76 | #define pte_present(pte) (!!(pte_val(pte) & (PTE_VALID | PTE_PROT_NONE))) |
Steve Capper | 84fe682 | 2014-02-25 11:38:53 +0000 | [diff] [blame] | 77 | #define pte_young(pte) (!!(pte_val(pte) & PTE_AF)) |
| 78 | #define pte_special(pte) (!!(pte_val(pte) & PTE_SPECIAL)) |
| 79 | #define pte_write(pte) (!!(pte_val(pte) & PTE_WRITE)) |
Catalin Marinas | 8e620b0 | 2012-11-15 17:21:16 +0000 | [diff] [blame] | 80 | #define pte_exec(pte) (!(pte_val(pte) & PTE_UXN)) |
Jeremy Linton | 93ef666 | 2015-10-07 12:00:21 -0500 | [diff] [blame] | 81 | #define pte_cont(pte) (!!(pte_val(pte) & PTE_CONT)) |
Catalin Marinas | ac15bd6 | 2016-01-07 16:07:20 +0000 | [diff] [blame] | 82 | #define pte_user(pte) (!!(pte_val(pte) & PTE_USER)) |
Catalin Marinas | 4f04d8f | 2012-03-05 11:49:27 +0000 | [diff] [blame] | 83 | |
Catalin Marinas | 2f4b829 | 2015-07-10 17:24:28 +0100 | [diff] [blame] | 84 | #ifdef CONFIG_ARM64_HW_AFDBM |
Catalin Marinas | b847415 | 2015-09-11 18:22:00 +0100 | [diff] [blame] | 85 | #define pte_hw_dirty(pte) (pte_write(pte) && !(pte_val(pte) & PTE_RDONLY)) |
Catalin Marinas | 2f4b829 | 2015-07-10 17:24:28 +0100 | [diff] [blame] | 86 | #else |
| 87 | #define pte_hw_dirty(pte) (0) |
| 88 | #endif |
| 89 | #define pte_sw_dirty(pte) (!!(pte_val(pte) & PTE_DIRTY)) |
| 90 | #define pte_dirty(pte) (pte_sw_dirty(pte) || pte_hw_dirty(pte)) |
| 91 | |
Will Deacon | 766ffb6 | 2015-07-28 16:14:03 +0100 | [diff] [blame] | 92 | #define pte_valid(pte) (!!(pte_val(pte) & PTE_VALID)) |
Catalin Marinas | 7f0b1bf | 2014-06-09 11:55:03 +0100 | [diff] [blame] | 93 | #define pte_valid_not_user(pte) \ |
| 94 | ((pte_val(pte) & (PTE_VALID | PTE_USER)) == PTE_VALID) |
Will Deacon | 76c714b | 2015-10-30 18:56:19 +0000 | [diff] [blame] | 95 | #define pte_valid_young(pte) \ |
| 96 | ((pte_val(pte) & (PTE_VALID | PTE_AF)) == (PTE_VALID | PTE_AF)) |
| 97 | |
| 98 | /* |
| 99 | * Could the pte be present in the TLB? We must check mm_tlb_flush_pending |
| 100 | * so that we don't erroneously return false for pages that have been |
| 101 | * remapped as PROT_NONE but are yet to be flushed from the TLB. |
| 102 | */ |
| 103 | #define pte_accessible(mm, pte) \ |
| 104 | (mm_tlb_flush_pending(mm) ? pte_present(pte) : pte_valid_young(pte)) |
Catalin Marinas | 4f04d8f | 2012-03-05 11:49:27 +0000 | [diff] [blame] | 105 | |
Laura Abbott | b6d4f28 | 2014-08-19 20:41:42 +0100 | [diff] [blame] | 106 | static inline pte_t clear_pte_bit(pte_t pte, pgprot_t prot) |
| 107 | { |
| 108 | pte_val(pte) &= ~pgprot_val(prot); |
| 109 | return pte; |
| 110 | } |
| 111 | |
| 112 | static inline pte_t set_pte_bit(pte_t pte, pgprot_t prot) |
| 113 | { |
| 114 | pte_val(pte) |= pgprot_val(prot); |
| 115 | return pte; |
| 116 | } |
| 117 | |
Steve Capper | 44b6dfc | 2014-01-15 14:07:12 +0000 | [diff] [blame] | 118 | static inline pte_t pte_wrprotect(pte_t pte) |
| 119 | { |
Laura Abbott | b6d4f28 | 2014-08-19 20:41:42 +0100 | [diff] [blame] | 120 | return clear_pte_bit(pte, __pgprot(PTE_WRITE)); |
Steve Capper | 44b6dfc | 2014-01-15 14:07:12 +0000 | [diff] [blame] | 121 | } |
Catalin Marinas | 4f04d8f | 2012-03-05 11:49:27 +0000 | [diff] [blame] | 122 | |
Steve Capper | 44b6dfc | 2014-01-15 14:07:12 +0000 | [diff] [blame] | 123 | static inline pte_t pte_mkwrite(pte_t pte) |
| 124 | { |
Laura Abbott | b6d4f28 | 2014-08-19 20:41:42 +0100 | [diff] [blame] | 125 | return set_pte_bit(pte, __pgprot(PTE_WRITE)); |
Steve Capper | 44b6dfc | 2014-01-15 14:07:12 +0000 | [diff] [blame] | 126 | } |
| 127 | |
| 128 | static inline pte_t pte_mkclean(pte_t pte) |
| 129 | { |
Laura Abbott | b6d4f28 | 2014-08-19 20:41:42 +0100 | [diff] [blame] | 130 | return clear_pte_bit(pte, __pgprot(PTE_DIRTY)); |
Steve Capper | 44b6dfc | 2014-01-15 14:07:12 +0000 | [diff] [blame] | 131 | } |
| 132 | |
| 133 | static inline pte_t pte_mkdirty(pte_t pte) |
| 134 | { |
Laura Abbott | b6d4f28 | 2014-08-19 20:41:42 +0100 | [diff] [blame] | 135 | return set_pte_bit(pte, __pgprot(PTE_DIRTY)); |
Steve Capper | 44b6dfc | 2014-01-15 14:07:12 +0000 | [diff] [blame] | 136 | } |
| 137 | |
| 138 | static inline pte_t pte_mkold(pte_t pte) |
| 139 | { |
Laura Abbott | b6d4f28 | 2014-08-19 20:41:42 +0100 | [diff] [blame] | 140 | return clear_pte_bit(pte, __pgprot(PTE_AF)); |
Steve Capper | 44b6dfc | 2014-01-15 14:07:12 +0000 | [diff] [blame] | 141 | } |
| 142 | |
| 143 | static inline pte_t pte_mkyoung(pte_t pte) |
| 144 | { |
Laura Abbott | b6d4f28 | 2014-08-19 20:41:42 +0100 | [diff] [blame] | 145 | return set_pte_bit(pte, __pgprot(PTE_AF)); |
Steve Capper | 44b6dfc | 2014-01-15 14:07:12 +0000 | [diff] [blame] | 146 | } |
| 147 | |
| 148 | static inline pte_t pte_mkspecial(pte_t pte) |
| 149 | { |
Laura Abbott | b6d4f28 | 2014-08-19 20:41:42 +0100 | [diff] [blame] | 150 | return set_pte_bit(pte, __pgprot(PTE_SPECIAL)); |
Steve Capper | 44b6dfc | 2014-01-15 14:07:12 +0000 | [diff] [blame] | 151 | } |
Catalin Marinas | 4f04d8f | 2012-03-05 11:49:27 +0000 | [diff] [blame] | 152 | |
Jeremy Linton | 93ef666 | 2015-10-07 12:00:21 -0500 | [diff] [blame] | 153 | static inline pte_t pte_mkcont(pte_t pte) |
| 154 | { |
David Woods | 66b3923 | 2015-12-17 14:31:26 -0500 | [diff] [blame] | 155 | pte = set_pte_bit(pte, __pgprot(PTE_CONT)); |
| 156 | return set_pte_bit(pte, __pgprot(PTE_TYPE_PAGE)); |
Jeremy Linton | 93ef666 | 2015-10-07 12:00:21 -0500 | [diff] [blame] | 157 | } |
| 158 | |
| 159 | static inline pte_t pte_mknoncont(pte_t pte) |
| 160 | { |
| 161 | return clear_pte_bit(pte, __pgprot(PTE_CONT)); |
| 162 | } |
| 163 | |
David Woods | 66b3923 | 2015-12-17 14:31:26 -0500 | [diff] [blame] | 164 | static inline pmd_t pmd_mkcont(pmd_t pmd) |
| 165 | { |
| 166 | return __pmd(pmd_val(pmd) | PMD_SECT_CONT); |
| 167 | } |
| 168 | |
Catalin Marinas | 4f04d8f | 2012-03-05 11:49:27 +0000 | [diff] [blame] | 169 | static inline void set_pte(pte_t *ptep, pte_t pte) |
| 170 | { |
| 171 | *ptep = pte; |
Catalin Marinas | 7f0b1bf | 2014-06-09 11:55:03 +0100 | [diff] [blame] | 172 | |
| 173 | /* |
| 174 | * Only if the new pte is valid and kernel, otherwise TLB maintenance |
| 175 | * or update_mmu_cache() have the necessary barriers. |
| 176 | */ |
| 177 | if (pte_valid_not_user(pte)) { |
| 178 | dsb(ishst); |
| 179 | isb(); |
| 180 | } |
Catalin Marinas | 4f04d8f | 2012-03-05 11:49:27 +0000 | [diff] [blame] | 181 | } |
| 182 | |
Catalin Marinas | 2f4b829 | 2015-07-10 17:24:28 +0100 | [diff] [blame] | 183 | struct mm_struct; |
| 184 | struct vm_area_struct; |
| 185 | |
Catalin Marinas | 4f04d8f | 2012-03-05 11:49:27 +0000 | [diff] [blame] | 186 | extern void __sync_icache_dcache(pte_t pteval, unsigned long addr); |
| 187 | |
Catalin Marinas | 2f4b829 | 2015-07-10 17:24:28 +0100 | [diff] [blame] | 188 | /* |
| 189 | * PTE bits configuration in the presence of hardware Dirty Bit Management |
| 190 | * (PTE_WRITE == PTE_DBM): |
| 191 | * |
| 192 | * Dirty Writable | PTE_RDONLY PTE_WRITE PTE_DIRTY (sw) |
| 193 | * 0 0 | 1 0 0 |
| 194 | * 0 1 | 1 1 0 |
| 195 | * 1 0 | 1 0 1 |
| 196 | * 1 1 | 0 1 x |
| 197 | * |
| 198 | * When hardware DBM is not present, the sofware PTE_DIRTY bit is updated via |
| 199 | * the page fault mechanism. Checking the dirty status of a pte becomes: |
| 200 | * |
Catalin Marinas | b847415 | 2015-09-11 18:22:00 +0100 | [diff] [blame] | 201 | * PTE_DIRTY || (PTE_WRITE && !PTE_RDONLY) |
Catalin Marinas | 2f4b829 | 2015-07-10 17:24:28 +0100 | [diff] [blame] | 202 | */ |
Catalin Marinas | 4f04d8f | 2012-03-05 11:49:27 +0000 | [diff] [blame] | 203 | static inline void set_pte_at(struct mm_struct *mm, unsigned long addr, |
| 204 | pte_t *ptep, pte_t pte) |
| 205 | { |
Catalin Marinas | fdc69e7 | 2016-03-09 16:31:29 +0000 | [diff] [blame] | 206 | if (pte_present(pte)) { |
Catalin Marinas | 2f4b829 | 2015-07-10 17:24:28 +0100 | [diff] [blame] | 207 | if (pte_sw_dirty(pte) && pte_write(pte)) |
Steve Capper | c2c93e5 | 2014-01-15 14:07:13 +0000 | [diff] [blame] | 208 | pte_val(pte) &= ~PTE_RDONLY; |
| 209 | else |
| 210 | pte_val(pte) |= PTE_RDONLY; |
Catalin Marinas | ac15bd6 | 2016-01-07 16:07:20 +0000 | [diff] [blame] | 211 | if (pte_user(pte) && pte_exec(pte) && !pte_special(pte)) |
| 212 | __sync_icache_dcache(pte, addr); |
Will Deacon | 0252246 | 2013-01-09 11:08:10 +0000 | [diff] [blame] | 213 | } |
| 214 | |
Catalin Marinas | 2f4b829 | 2015-07-10 17:24:28 +0100 | [diff] [blame] | 215 | /* |
| 216 | * If the existing pte is valid, check for potential race with |
| 217 | * hardware updates of the pte (ptep_set_access_flags safely changes |
| 218 | * valid ptes without going through an invalid entry). |
| 219 | */ |
Catalin Marinas | 82d3400 | 2015-12-08 17:39:15 +0000 | [diff] [blame] | 220 | if (IS_ENABLED(CONFIG_ARM64_HW_AFDBM) && |
| 221 | pte_valid(*ptep) && pte_valid(pte)) { |
| 222 | VM_WARN_ONCE(!pte_young(pte), |
| 223 | "%s: racy access flag clearing: 0x%016llx -> 0x%016llx", |
| 224 | __func__, pte_val(*ptep), pte_val(pte)); |
| 225 | VM_WARN_ONCE(pte_write(*ptep) && !pte_dirty(pte), |
| 226 | "%s: racy dirty state clearing: 0x%016llx -> 0x%016llx", |
| 227 | __func__, pte_val(*ptep), pte_val(pte)); |
Catalin Marinas | 2f4b829 | 2015-07-10 17:24:28 +0100 | [diff] [blame] | 228 | } |
| 229 | |
Catalin Marinas | 4f04d8f | 2012-03-05 11:49:27 +0000 | [diff] [blame] | 230 | set_pte(ptep, pte); |
| 231 | } |
| 232 | |
| 233 | /* |
| 234 | * Huge pte definitions. |
| 235 | */ |
Steve Capper | 084bd29 | 2013-04-10 13:48:00 +0100 | [diff] [blame] | 236 | #define pte_huge(pte) (!(pte_val(pte) & PTE_TABLE_BIT)) |
| 237 | #define pte_mkhuge(pte) (__pte(pte_val(pte) & ~PTE_TABLE_BIT)) |
| 238 | |
| 239 | /* |
| 240 | * Hugetlb definitions. |
| 241 | */ |
David Woods | 66b3923 | 2015-12-17 14:31:26 -0500 | [diff] [blame] | 242 | #define HUGE_MAX_HSTATE 4 |
Steve Capper | 084bd29 | 2013-04-10 13:48:00 +0100 | [diff] [blame] | 243 | #define HPAGE_SHIFT PMD_SHIFT |
| 244 | #define HPAGE_SIZE (_AC(1, UL) << HPAGE_SHIFT) |
| 245 | #define HPAGE_MASK (~(HPAGE_SIZE - 1)) |
| 246 | #define HUGETLB_PAGE_ORDER (HPAGE_SHIFT - PAGE_SHIFT) |
Catalin Marinas | 4f04d8f | 2012-03-05 11:49:27 +0000 | [diff] [blame] | 247 | |
Catalin Marinas | 4f04d8f | 2012-03-05 11:49:27 +0000 | [diff] [blame] | 248 | #define __HAVE_ARCH_PTE_SPECIAL |
| 249 | |
Steve Capper | 29e5694 | 2014-10-09 15:29:25 -0700 | [diff] [blame] | 250 | static inline pte_t pud_pte(pud_t pud) |
| 251 | { |
| 252 | return __pte(pud_val(pud)); |
| 253 | } |
| 254 | |
| 255 | static inline pmd_t pud_pmd(pud_t pud) |
| 256 | { |
| 257 | return __pmd(pud_val(pud)); |
| 258 | } |
| 259 | |
Steve Capper | 9c7e535 | 2014-02-25 10:02:13 +0000 | [diff] [blame] | 260 | static inline pte_t pmd_pte(pmd_t pmd) |
| 261 | { |
| 262 | return __pte(pmd_val(pmd)); |
| 263 | } |
Steve Capper | af07484 | 2013-04-19 16:23:57 +0100 | [diff] [blame] | 264 | |
Steve Capper | 9c7e535 | 2014-02-25 10:02:13 +0000 | [diff] [blame] | 265 | static inline pmd_t pte_pmd(pte_t pte) |
| 266 | { |
| 267 | return __pmd(pte_val(pte)); |
| 268 | } |
Steve Capper | af07484 | 2013-04-19 16:23:57 +0100 | [diff] [blame] | 269 | |
Ard Biesheuvel | 8ce837c | 2014-10-20 15:42:07 +0200 | [diff] [blame] | 270 | static inline pgprot_t mk_sect_prot(pgprot_t prot) |
| 271 | { |
| 272 | return __pgprot(pgprot_val(prot) & ~PTE_TABLE_BIT); |
| 273 | } |
| 274 | |
Steve Capper | af07484 | 2013-04-19 16:23:57 +0100 | [diff] [blame] | 275 | /* |
| 276 | * THP definitions. |
| 277 | */ |
Steve Capper | af07484 | 2013-04-19 16:23:57 +0100 | [diff] [blame] | 278 | |
| 279 | #ifdef CONFIG_TRANSPARENT_HUGEPAGE |
| 280 | #define pmd_trans_huge(pmd) (pmd_val(pmd) && !(pmd_val(pmd) & PMD_TABLE_BIT)) |
Steve Capper | 29e5694 | 2014-10-09 15:29:25 -0700 | [diff] [blame] | 281 | #endif /* CONFIG_TRANSPARENT_HUGEPAGE */ |
Steve Capper | af07484 | 2013-04-19 16:23:57 +0100 | [diff] [blame] | 282 | |
Kirill A. Shutemov | c164e03 | 2014-12-10 15:44:36 -0800 | [diff] [blame] | 283 | #define pmd_dirty(pmd) pte_dirty(pmd_pte(pmd)) |
Steve Capper | 9c7e535 | 2014-02-25 10:02:13 +0000 | [diff] [blame] | 284 | #define pmd_young(pmd) pte_young(pmd_pte(pmd)) |
| 285 | #define pmd_wrprotect(pmd) pte_pmd(pte_wrprotect(pmd_pte(pmd))) |
Steve Capper | 9c7e535 | 2014-02-25 10:02:13 +0000 | [diff] [blame] | 286 | #define pmd_mkold(pmd) pte_pmd(pte_mkold(pmd_pte(pmd))) |
| 287 | #define pmd_mkwrite(pmd) pte_pmd(pte_mkwrite(pmd_pte(pmd))) |
Minchan Kim | 05ee26d | 2016-01-15 16:55:37 -0800 | [diff] [blame] | 288 | #define pmd_mkclean(pmd) pte_pmd(pte_mkclean(pmd_pte(pmd))) |
Steve Capper | 9c7e535 | 2014-02-25 10:02:13 +0000 | [diff] [blame] | 289 | #define pmd_mkdirty(pmd) pte_pmd(pte_mkdirty(pmd_pte(pmd))) |
| 290 | #define pmd_mkyoung(pmd) pte_pmd(pte_mkyoung(pmd_pte(pmd))) |
Will Deacon | e3a920a | 2014-06-18 14:06:27 +0100 | [diff] [blame] | 291 | #define pmd_mknotpresent(pmd) (__pmd(pmd_val(pmd) & ~PMD_TYPE_MASK)) |
Steve Capper | af07484 | 2013-04-19 16:23:57 +0100 | [diff] [blame] | 292 | |
Suzuki K Poulose | 0dbd3b1 | 2016-03-15 10:46:34 +0000 | [diff] [blame] | 293 | #define pmd_thp_or_huge(pmd) (pmd_huge(pmd) || pmd_trans_huge(pmd)) |
| 294 | |
Steve Capper | 9c7e535 | 2014-02-25 10:02:13 +0000 | [diff] [blame] | 295 | #define __HAVE_ARCH_PMD_WRITE |
| 296 | #define pmd_write(pmd) pte_write(pmd_pte(pmd)) |
Steve Capper | af07484 | 2013-04-19 16:23:57 +0100 | [diff] [blame] | 297 | |
| 298 | #define pmd_mkhuge(pmd) (__pmd(pmd_val(pmd) & ~PMD_TABLE_BIT)) |
| 299 | |
| 300 | #define pmd_pfn(pmd) (((pmd_val(pmd) & PMD_MASK) & PHYS_MASK) >> PAGE_SHIFT) |
| 301 | #define pfn_pmd(pfn,prot) (__pmd(((phys_addr_t)(pfn) << PAGE_SHIFT) | pgprot_val(prot))) |
| 302 | #define mk_pmd(page,prot) pfn_pmd(page_to_pfn(page),prot) |
| 303 | |
Steve Capper | 29e5694 | 2014-10-09 15:29:25 -0700 | [diff] [blame] | 304 | #define pud_write(pud) pte_write(pud_pte(pud)) |
Steve Capper | 206a2a7 | 2014-05-06 14:02:27 +0100 | [diff] [blame] | 305 | #define pud_pfn(pud) (((pud_val(pud) & PUD_MASK) & PHYS_MASK) >> PAGE_SHIFT) |
Steve Capper | af07484 | 2013-04-19 16:23:57 +0100 | [diff] [blame] | 306 | |
Will Deacon | ceb2183 | 2014-05-27 19:11:58 +0100 | [diff] [blame] | 307 | #define set_pmd_at(mm, addr, pmdp, pmd) set_pte_at(mm, addr, (pte_t *)pmdp, pmd_pte(pmd)) |
Steve Capper | af07484 | 2013-04-19 16:23:57 +0100 | [diff] [blame] | 308 | |
| 309 | static inline int has_transparent_hugepage(void) |
| 310 | { |
| 311 | return 1; |
| 312 | } |
| 313 | |
Catalin Marinas | a501e32 | 2014-04-03 15:57:15 +0100 | [diff] [blame] | 314 | #define __pgprot_modify(prot,mask,bits) \ |
| 315 | __pgprot((pgprot_val(prot) & ~(mask)) | (bits)) |
| 316 | |
Steve Capper | af07484 | 2013-04-19 16:23:57 +0100 | [diff] [blame] | 317 | /* |
Catalin Marinas | 4f04d8f | 2012-03-05 11:49:27 +0000 | [diff] [blame] | 318 | * Mark the prot value as uncacheable and unbufferable. |
| 319 | */ |
| 320 | #define pgprot_noncached(prot) \ |
Catalin Marinas | de2db74 | 2014-03-12 16:07:06 +0000 | [diff] [blame] | 321 | __pgprot_modify(prot, PTE_ATTRINDX_MASK, PTE_ATTRINDX(MT_DEVICE_nGnRnE) | PTE_PXN | PTE_UXN) |
Catalin Marinas | 4f04d8f | 2012-03-05 11:49:27 +0000 | [diff] [blame] | 322 | #define pgprot_writecombine(prot) \ |
Catalin Marinas | de2db74 | 2014-03-12 16:07:06 +0000 | [diff] [blame] | 323 | __pgprot_modify(prot, PTE_ATTRINDX_MASK, PTE_ATTRINDX(MT_NORMAL_NC) | PTE_PXN | PTE_UXN) |
Liviu Dudau | d1e6dc9 | 2014-09-29 15:29:31 +0100 | [diff] [blame] | 324 | #define pgprot_device(prot) \ |
| 325 | __pgprot_modify(prot, PTE_ATTRINDX_MASK, PTE_ATTRINDX(MT_DEVICE_nGnRE) | PTE_PXN | PTE_UXN) |
Catalin Marinas | 4f04d8f | 2012-03-05 11:49:27 +0000 | [diff] [blame] | 326 | #define __HAVE_PHYS_MEM_ACCESS_PROT |
| 327 | struct file; |
| 328 | extern pgprot_t phys_mem_access_prot(struct file *file, unsigned long pfn, |
| 329 | unsigned long size, pgprot_t vma_prot); |
| 330 | |
| 331 | #define pmd_none(pmd) (!pmd_val(pmd)) |
| 332 | #define pmd_present(pmd) (pmd_val(pmd)) |
| 333 | |
| 334 | #define pmd_bad(pmd) (!(pmd_val(pmd) & 2)) |
| 335 | |
Marc Zyngier | 3631160 | 2012-12-07 18:35:41 +0000 | [diff] [blame] | 336 | #define pmd_table(pmd) ((pmd_val(pmd) & PMD_TYPE_MASK) == \ |
| 337 | PMD_TYPE_TABLE) |
| 338 | #define pmd_sect(pmd) ((pmd_val(pmd) & PMD_TYPE_MASK) == \ |
| 339 | PMD_TYPE_SECT) |
| 340 | |
Catalin Marinas | cac4b8c | 2016-02-25 15:53:44 +0000 | [diff] [blame] | 341 | #if defined(CONFIG_ARM64_64K_PAGES) || CONFIG_PGTABLE_LEVELS < 3 |
Steve Capper | 206a2a7 | 2014-05-06 14:02:27 +0100 | [diff] [blame] | 342 | #define pud_sect(pud) (0) |
zhichang.yuan | 523d6e9 | 2014-12-09 07:26:47 +0000 | [diff] [blame] | 343 | #define pud_table(pud) (1) |
Steve Capper | 206a2a7 | 2014-05-06 14:02:27 +0100 | [diff] [blame] | 344 | #else |
| 345 | #define pud_sect(pud) ((pud_val(pud) & PUD_TYPE_MASK) == \ |
| 346 | PUD_TYPE_SECT) |
zhichang.yuan | 523d6e9 | 2014-12-09 07:26:47 +0000 | [diff] [blame] | 347 | #define pud_table(pud) ((pud_val(pud) & PUD_TYPE_MASK) == \ |
| 348 | PUD_TYPE_TABLE) |
Steve Capper | 206a2a7 | 2014-05-06 14:02:27 +0100 | [diff] [blame] | 349 | #endif |
Marc Zyngier | 3631160 | 2012-12-07 18:35:41 +0000 | [diff] [blame] | 350 | |
Catalin Marinas | 4f04d8f | 2012-03-05 11:49:27 +0000 | [diff] [blame] | 351 | static inline void set_pmd(pmd_t *pmdp, pmd_t pmd) |
| 352 | { |
| 353 | *pmdp = pmd; |
Will Deacon | 98f7685 | 2014-05-02 16:24:10 +0100 | [diff] [blame] | 354 | dsb(ishst); |
Catalin Marinas | 7f0b1bf | 2014-06-09 11:55:03 +0100 | [diff] [blame] | 355 | isb(); |
Catalin Marinas | 4f04d8f | 2012-03-05 11:49:27 +0000 | [diff] [blame] | 356 | } |
| 357 | |
| 358 | static inline void pmd_clear(pmd_t *pmdp) |
| 359 | { |
| 360 | set_pmd(pmdp, __pmd(0)); |
| 361 | } |
| 362 | |
Mark Rutland | dca56dc | 2016-01-25 11:45:04 +0000 | [diff] [blame] | 363 | static inline phys_addr_t pmd_page_paddr(pmd_t pmd) |
Catalin Marinas | 4f04d8f | 2012-03-05 11:49:27 +0000 | [diff] [blame] | 364 | { |
Mark Rutland | dca56dc | 2016-01-25 11:45:04 +0000 | [diff] [blame] | 365 | return pmd_val(pmd) & PHYS_MASK & (s32)PAGE_MASK; |
Catalin Marinas | 4f04d8f | 2012-03-05 11:49:27 +0000 | [diff] [blame] | 366 | } |
| 367 | |
Mark Rutland | 053520f | 2016-01-25 11:45:03 +0000 | [diff] [blame] | 368 | /* Find an entry in the third-level page table. */ |
| 369 | #define pte_index(addr) (((addr) >> PAGE_SHIFT) & (PTRS_PER_PTE - 1)) |
| 370 | |
Mark Rutland | dca56dc | 2016-01-25 11:45:04 +0000 | [diff] [blame] | 371 | #define pte_offset_phys(dir,addr) (pmd_page_paddr(*(dir)) + pte_index(addr) * sizeof(pte_t)) |
| 372 | #define pte_offset_kernel(dir,addr) ((pte_t *)__va(pte_offset_phys((dir), (addr)))) |
Mark Rutland | 053520f | 2016-01-25 11:45:03 +0000 | [diff] [blame] | 373 | |
| 374 | #define pte_offset_map(dir,addr) pte_offset_kernel((dir), (addr)) |
| 375 | #define pte_offset_map_nested(dir,addr) pte_offset_kernel((dir), (addr)) |
| 376 | #define pte_unmap(pte) do { } while (0) |
| 377 | #define pte_unmap_nested(pte) do { } while (0) |
| 378 | |
Mark Rutland | 961faac | 2016-01-25 11:45:07 +0000 | [diff] [blame] | 379 | #define pte_set_fixmap(addr) ((pte_t *)set_fixmap_offset(FIX_PTE, addr)) |
| 380 | #define pte_set_fixmap_offset(pmd, addr) pte_set_fixmap(pte_offset_phys(pmd, addr)) |
| 381 | #define pte_clear_fixmap() clear_fixmap(FIX_PTE) |
| 382 | |
Catalin Marinas | 4f04d8f | 2012-03-05 11:49:27 +0000 | [diff] [blame] | 383 | #define pmd_page(pmd) pfn_to_page(__phys_to_pfn(pmd_val(pmd) & PHYS_MASK)) |
| 384 | |
Ard Biesheuvel | 6533945 | 2016-02-16 13:52:37 +0100 | [diff] [blame] | 385 | /* use ONLY for statically allocated translation tables */ |
| 386 | #define pte_offset_kimg(dir,addr) ((pte_t *)__phys_to_kimg(pte_offset_phys((dir), (addr)))) |
| 387 | |
Catalin Marinas | 4f04d8f | 2012-03-05 11:49:27 +0000 | [diff] [blame] | 388 | /* |
| 389 | * Conversion functions: convert a page and protection to a page entry, |
| 390 | * and a page entry and page directory to the page they refer to. |
| 391 | */ |
| 392 | #define mk_pte(page,prot) pfn_pte(page_to_pfn(page),prot) |
| 393 | |
Kirill A. Shutemov | 9f25e6a | 2015-04-14 15:45:39 -0700 | [diff] [blame] | 394 | #if CONFIG_PGTABLE_LEVELS > 2 |
Catalin Marinas | 4f04d8f | 2012-03-05 11:49:27 +0000 | [diff] [blame] | 395 | |
Catalin Marinas | 7078db4 | 2014-07-21 14:52:49 +0100 | [diff] [blame] | 396 | #define pmd_ERROR(pmd) __pmd_error(__FILE__, __LINE__, pmd_val(pmd)) |
| 397 | |
Catalin Marinas | 4f04d8f | 2012-03-05 11:49:27 +0000 | [diff] [blame] | 398 | #define pud_none(pud) (!pud_val(pud)) |
| 399 | #define pud_bad(pud) (!(pud_val(pud) & 2)) |
| 400 | #define pud_present(pud) (pud_val(pud)) |
| 401 | |
| 402 | static inline void set_pud(pud_t *pudp, pud_t pud) |
| 403 | { |
| 404 | *pudp = pud; |
Will Deacon | 98f7685 | 2014-05-02 16:24:10 +0100 | [diff] [blame] | 405 | dsb(ishst); |
Catalin Marinas | 7f0b1bf | 2014-06-09 11:55:03 +0100 | [diff] [blame] | 406 | isb(); |
Catalin Marinas | 4f04d8f | 2012-03-05 11:49:27 +0000 | [diff] [blame] | 407 | } |
| 408 | |
| 409 | static inline void pud_clear(pud_t *pudp) |
| 410 | { |
| 411 | set_pud(pudp, __pud(0)); |
| 412 | } |
| 413 | |
Mark Rutland | dca56dc | 2016-01-25 11:45:04 +0000 | [diff] [blame] | 414 | static inline phys_addr_t pud_page_paddr(pud_t pud) |
Catalin Marinas | 4f04d8f | 2012-03-05 11:49:27 +0000 | [diff] [blame] | 415 | { |
Mark Rutland | dca56dc | 2016-01-25 11:45:04 +0000 | [diff] [blame] | 416 | return pud_val(pud) & PHYS_MASK & (s32)PAGE_MASK; |
Catalin Marinas | 4f04d8f | 2012-03-05 11:49:27 +0000 | [diff] [blame] | 417 | } |
| 418 | |
Catalin Marinas | 7078db4 | 2014-07-21 14:52:49 +0100 | [diff] [blame] | 419 | /* Find an entry in the second-level page table. */ |
| 420 | #define pmd_index(addr) (((addr) >> PMD_SHIFT) & (PTRS_PER_PMD - 1)) |
| 421 | |
Mark Rutland | dca56dc | 2016-01-25 11:45:04 +0000 | [diff] [blame] | 422 | #define pmd_offset_phys(dir, addr) (pud_page_paddr(*(dir)) + pmd_index(addr) * sizeof(pmd_t)) |
| 423 | #define pmd_offset(dir, addr) ((pmd_t *)__va(pmd_offset_phys((dir), (addr)))) |
Catalin Marinas | 7078db4 | 2014-07-21 14:52:49 +0100 | [diff] [blame] | 424 | |
Mark Rutland | 961faac | 2016-01-25 11:45:07 +0000 | [diff] [blame] | 425 | #define pmd_set_fixmap(addr) ((pmd_t *)set_fixmap_offset(FIX_PMD, addr)) |
| 426 | #define pmd_set_fixmap_offset(pud, addr) pmd_set_fixmap(pmd_offset_phys(pud, addr)) |
| 427 | #define pmd_clear_fixmap() clear_fixmap(FIX_PMD) |
Catalin Marinas | 4f04d8f | 2012-03-05 11:49:27 +0000 | [diff] [blame] | 428 | |
Jungseok Lee | 5d96e0c | 2014-12-20 00:49:40 +0000 | [diff] [blame] | 429 | #define pud_page(pud) pfn_to_page(__phys_to_pfn(pud_val(pud) & PHYS_MASK)) |
Steve Capper | 29e5694 | 2014-10-09 15:29:25 -0700 | [diff] [blame] | 430 | |
Ard Biesheuvel | 6533945 | 2016-02-16 13:52:37 +0100 | [diff] [blame] | 431 | /* use ONLY for statically allocated translation tables */ |
| 432 | #define pmd_offset_kimg(dir,addr) ((pmd_t *)__phys_to_kimg(pmd_offset_phys((dir), (addr)))) |
| 433 | |
Mark Rutland | dca56dc | 2016-01-25 11:45:04 +0000 | [diff] [blame] | 434 | #else |
| 435 | |
| 436 | #define pud_page_paddr(pud) ({ BUILD_BUG(); 0; }) |
| 437 | |
Mark Rutland | 961faac | 2016-01-25 11:45:07 +0000 | [diff] [blame] | 438 | /* Match pmd_offset folding in <asm/generic/pgtable-nopmd.h> */ |
| 439 | #define pmd_set_fixmap(addr) NULL |
| 440 | #define pmd_set_fixmap_offset(pudp, addr) ((pmd_t *)pudp) |
| 441 | #define pmd_clear_fixmap() |
| 442 | |
Ard Biesheuvel | 6533945 | 2016-02-16 13:52:37 +0100 | [diff] [blame] | 443 | #define pmd_offset_kimg(dir,addr) ((pmd_t *)dir) |
| 444 | |
Kirill A. Shutemov | 9f25e6a | 2015-04-14 15:45:39 -0700 | [diff] [blame] | 445 | #endif /* CONFIG_PGTABLE_LEVELS > 2 */ |
Catalin Marinas | 4f04d8f | 2012-03-05 11:49:27 +0000 | [diff] [blame] | 446 | |
Kirill A. Shutemov | 9f25e6a | 2015-04-14 15:45:39 -0700 | [diff] [blame] | 447 | #if CONFIG_PGTABLE_LEVELS > 3 |
Jungseok Lee | c79b954 | 2014-05-12 18:40:51 +0900 | [diff] [blame] | 448 | |
Catalin Marinas | 7078db4 | 2014-07-21 14:52:49 +0100 | [diff] [blame] | 449 | #define pud_ERROR(pud) __pud_error(__FILE__, __LINE__, pud_val(pud)) |
| 450 | |
Jungseok Lee | c79b954 | 2014-05-12 18:40:51 +0900 | [diff] [blame] | 451 | #define pgd_none(pgd) (!pgd_val(pgd)) |
| 452 | #define pgd_bad(pgd) (!(pgd_val(pgd) & 2)) |
| 453 | #define pgd_present(pgd) (pgd_val(pgd)) |
| 454 | |
| 455 | static inline void set_pgd(pgd_t *pgdp, pgd_t pgd) |
| 456 | { |
| 457 | *pgdp = pgd; |
| 458 | dsb(ishst); |
| 459 | } |
| 460 | |
| 461 | static inline void pgd_clear(pgd_t *pgdp) |
| 462 | { |
| 463 | set_pgd(pgdp, __pgd(0)); |
| 464 | } |
| 465 | |
Mark Rutland | dca56dc | 2016-01-25 11:45:04 +0000 | [diff] [blame] | 466 | static inline phys_addr_t pgd_page_paddr(pgd_t pgd) |
Jungseok Lee | c79b954 | 2014-05-12 18:40:51 +0900 | [diff] [blame] | 467 | { |
Mark Rutland | dca56dc | 2016-01-25 11:45:04 +0000 | [diff] [blame] | 468 | return pgd_val(pgd) & PHYS_MASK & (s32)PAGE_MASK; |
Jungseok Lee | c79b954 | 2014-05-12 18:40:51 +0900 | [diff] [blame] | 469 | } |
| 470 | |
Catalin Marinas | 7078db4 | 2014-07-21 14:52:49 +0100 | [diff] [blame] | 471 | /* Find an entry in the frst-level page table. */ |
| 472 | #define pud_index(addr) (((addr) >> PUD_SHIFT) & (PTRS_PER_PUD - 1)) |
| 473 | |
Mark Rutland | dca56dc | 2016-01-25 11:45:04 +0000 | [diff] [blame] | 474 | #define pud_offset_phys(dir, addr) (pgd_page_paddr(*(dir)) + pud_index(addr) * sizeof(pud_t)) |
| 475 | #define pud_offset(dir, addr) ((pud_t *)__va(pud_offset_phys((dir), (addr)))) |
Catalin Marinas | 7078db4 | 2014-07-21 14:52:49 +0100 | [diff] [blame] | 476 | |
Mark Rutland | 961faac | 2016-01-25 11:45:07 +0000 | [diff] [blame] | 477 | #define pud_set_fixmap(addr) ((pud_t *)set_fixmap_offset(FIX_PUD, addr)) |
| 478 | #define pud_set_fixmap_offset(pgd, addr) pud_set_fixmap(pud_offset_phys(pgd, addr)) |
| 479 | #define pud_clear_fixmap() clear_fixmap(FIX_PUD) |
Jungseok Lee | c79b954 | 2014-05-12 18:40:51 +0900 | [diff] [blame] | 480 | |
Jungseok Lee | 5d96e0c | 2014-12-20 00:49:40 +0000 | [diff] [blame] | 481 | #define pgd_page(pgd) pfn_to_page(__phys_to_pfn(pgd_val(pgd) & PHYS_MASK)) |
| 482 | |
Ard Biesheuvel | 6533945 | 2016-02-16 13:52:37 +0100 | [diff] [blame] | 483 | /* use ONLY for statically allocated translation tables */ |
| 484 | #define pud_offset_kimg(dir,addr) ((pud_t *)__phys_to_kimg(pud_offset_phys((dir), (addr)))) |
| 485 | |
Mark Rutland | dca56dc | 2016-01-25 11:45:04 +0000 | [diff] [blame] | 486 | #else |
| 487 | |
| 488 | #define pgd_page_paddr(pgd) ({ BUILD_BUG(); 0;}) |
| 489 | |
Mark Rutland | 961faac | 2016-01-25 11:45:07 +0000 | [diff] [blame] | 490 | /* Match pud_offset folding in <asm/generic/pgtable-nopud.h> */ |
| 491 | #define pud_set_fixmap(addr) NULL |
| 492 | #define pud_set_fixmap_offset(pgdp, addr) ((pud_t *)pgdp) |
| 493 | #define pud_clear_fixmap() |
| 494 | |
Ard Biesheuvel | 6533945 | 2016-02-16 13:52:37 +0100 | [diff] [blame] | 495 | #define pud_offset_kimg(dir,addr) ((pud_t *)dir) |
| 496 | |
Kirill A. Shutemov | 9f25e6a | 2015-04-14 15:45:39 -0700 | [diff] [blame] | 497 | #endif /* CONFIG_PGTABLE_LEVELS > 3 */ |
Jungseok Lee | c79b954 | 2014-05-12 18:40:51 +0900 | [diff] [blame] | 498 | |
Catalin Marinas | 7078db4 | 2014-07-21 14:52:49 +0100 | [diff] [blame] | 499 | #define pgd_ERROR(pgd) __pgd_error(__FILE__, __LINE__, pgd_val(pgd)) |
| 500 | |
Catalin Marinas | 4f04d8f | 2012-03-05 11:49:27 +0000 | [diff] [blame] | 501 | /* to find an entry in a page-table-directory */ |
| 502 | #define pgd_index(addr) (((addr) >> PGDIR_SHIFT) & (PTRS_PER_PGD - 1)) |
| 503 | |
Mark Rutland | dca56dc | 2016-01-25 11:45:04 +0000 | [diff] [blame] | 504 | #define pgd_offset_raw(pgd, addr) ((pgd) + pgd_index(addr)) |
| 505 | |
| 506 | #define pgd_offset(mm, addr) (pgd_offset_raw((mm)->pgd, (addr))) |
Catalin Marinas | 4f04d8f | 2012-03-05 11:49:27 +0000 | [diff] [blame] | 507 | |
| 508 | /* to find an entry in a kernel page-table-directory */ |
| 509 | #define pgd_offset_k(addr) pgd_offset(&init_mm, addr) |
| 510 | |
Mark Rutland | 961faac | 2016-01-25 11:45:07 +0000 | [diff] [blame] | 511 | #define pgd_set_fixmap(addr) ((pgd_t *)set_fixmap_offset(FIX_PGD, addr)) |
| 512 | #define pgd_clear_fixmap() clear_fixmap(FIX_PGD) |
| 513 | |
Catalin Marinas | 4f04d8f | 2012-03-05 11:49:27 +0000 | [diff] [blame] | 514 | static inline pte_t pte_modify(pte_t pte, pgprot_t newprot) |
| 515 | { |
Will Deacon | a6fadf7 | 2012-12-18 14:15:15 +0000 | [diff] [blame] | 516 | const pteval_t mask = PTE_USER | PTE_PXN | PTE_UXN | PTE_RDONLY | |
Steve Capper | 1a541b4 | 2015-10-01 13:06:07 +0100 | [diff] [blame] | 517 | PTE_PROT_NONE | PTE_VALID | PTE_WRITE; |
Catalin Marinas | 2f4b829 | 2015-07-10 17:24:28 +0100 | [diff] [blame] | 518 | /* preserve the hardware dirty information */ |
| 519 | if (pte_hw_dirty(pte)) |
Catalin Marinas | 62d96c7 | 2015-09-11 18:22:01 +0100 | [diff] [blame] | 520 | pte = pte_mkdirty(pte); |
Catalin Marinas | 4f04d8f | 2012-03-05 11:49:27 +0000 | [diff] [blame] | 521 | pte_val(pte) = (pte_val(pte) & ~mask) | (pgprot_val(newprot) & mask); |
| 522 | return pte; |
| 523 | } |
| 524 | |
Steve Capper | 9c7e535 | 2014-02-25 10:02:13 +0000 | [diff] [blame] | 525 | static inline pmd_t pmd_modify(pmd_t pmd, pgprot_t newprot) |
| 526 | { |
| 527 | return pte_pmd(pte_modify(pmd_pte(pmd), newprot)); |
| 528 | } |
| 529 | |
Catalin Marinas | 2f4b829 | 2015-07-10 17:24:28 +0100 | [diff] [blame] | 530 | #ifdef CONFIG_ARM64_HW_AFDBM |
| 531 | /* |
| 532 | * Atomic pte/pmd modifications. |
| 533 | */ |
| 534 | #define __HAVE_ARCH_PTEP_TEST_AND_CLEAR_YOUNG |
| 535 | static inline int ptep_test_and_clear_young(struct vm_area_struct *vma, |
| 536 | unsigned long address, |
| 537 | pte_t *ptep) |
| 538 | { |
| 539 | pteval_t pteval; |
| 540 | unsigned int tmp, res; |
| 541 | |
| 542 | asm volatile("// ptep_test_and_clear_young\n" |
| 543 | " prfm pstl1strm, %2\n" |
| 544 | "1: ldxr %0, %2\n" |
| 545 | " ubfx %w3, %w0, %5, #1 // extract PTE_AF (young)\n" |
| 546 | " and %0, %0, %4 // clear PTE_AF\n" |
| 547 | " stxr %w1, %0, %2\n" |
| 548 | " cbnz %w1, 1b\n" |
| 549 | : "=&r" (pteval), "=&r" (tmp), "+Q" (pte_val(*ptep)), "=&r" (res) |
| 550 | : "L" (~PTE_AF), "I" (ilog2(PTE_AF))); |
| 551 | |
| 552 | return res; |
| 553 | } |
| 554 | |
| 555 | #ifdef CONFIG_TRANSPARENT_HUGEPAGE |
| 556 | #define __HAVE_ARCH_PMDP_TEST_AND_CLEAR_YOUNG |
| 557 | static inline int pmdp_test_and_clear_young(struct vm_area_struct *vma, |
| 558 | unsigned long address, |
| 559 | pmd_t *pmdp) |
| 560 | { |
| 561 | return ptep_test_and_clear_young(vma, address, (pte_t *)pmdp); |
| 562 | } |
| 563 | #endif /* CONFIG_TRANSPARENT_HUGEPAGE */ |
| 564 | |
| 565 | #define __HAVE_ARCH_PTEP_GET_AND_CLEAR |
| 566 | static inline pte_t ptep_get_and_clear(struct mm_struct *mm, |
| 567 | unsigned long address, pte_t *ptep) |
| 568 | { |
| 569 | pteval_t old_pteval; |
| 570 | unsigned int tmp; |
| 571 | |
| 572 | asm volatile("// ptep_get_and_clear\n" |
| 573 | " prfm pstl1strm, %2\n" |
| 574 | "1: ldxr %0, %2\n" |
| 575 | " stxr %w1, xzr, %2\n" |
| 576 | " cbnz %w1, 1b\n" |
| 577 | : "=&r" (old_pteval), "=&r" (tmp), "+Q" (pte_val(*ptep))); |
| 578 | |
| 579 | return __pte(old_pteval); |
| 580 | } |
| 581 | |
| 582 | #ifdef CONFIG_TRANSPARENT_HUGEPAGE |
| 583 | #define __HAVE_ARCH_PMDP_GET_AND_CLEAR |
| 584 | static inline pmd_t pmdp_get_and_clear(struct mm_struct *mm, |
| 585 | unsigned long address, pmd_t *pmdp) |
| 586 | { |
| 587 | return pte_pmd(ptep_get_and_clear(mm, address, (pte_t *)pmdp)); |
| 588 | } |
| 589 | #endif /* CONFIG_TRANSPARENT_HUGEPAGE */ |
| 590 | |
| 591 | /* |
| 592 | * ptep_set_wrprotect - mark read-only while trasferring potential hardware |
| 593 | * dirty status (PTE_DBM && !PTE_RDONLY) to the software PTE_DIRTY bit. |
| 594 | */ |
| 595 | #define __HAVE_ARCH_PTEP_SET_WRPROTECT |
| 596 | static inline void ptep_set_wrprotect(struct mm_struct *mm, unsigned long address, pte_t *ptep) |
| 597 | { |
| 598 | pteval_t pteval; |
| 599 | unsigned long tmp; |
| 600 | |
| 601 | asm volatile("// ptep_set_wrprotect\n" |
| 602 | " prfm pstl1strm, %2\n" |
| 603 | "1: ldxr %0, %2\n" |
| 604 | " tst %0, %4 // check for hw dirty (!PTE_RDONLY)\n" |
| 605 | " csel %1, %3, xzr, eq // set PTE_DIRTY|PTE_RDONLY if dirty\n" |
| 606 | " orr %0, %0, %1 // if !dirty, PTE_RDONLY is already set\n" |
| 607 | " and %0, %0, %5 // clear PTE_WRITE/PTE_DBM\n" |
| 608 | " stxr %w1, %0, %2\n" |
| 609 | " cbnz %w1, 1b\n" |
| 610 | : "=&r" (pteval), "=&r" (tmp), "+Q" (pte_val(*ptep)) |
| 611 | : "r" (PTE_DIRTY|PTE_RDONLY), "L" (PTE_RDONLY), "L" (~PTE_WRITE) |
| 612 | : "cc"); |
| 613 | } |
| 614 | |
| 615 | #ifdef CONFIG_TRANSPARENT_HUGEPAGE |
| 616 | #define __HAVE_ARCH_PMDP_SET_WRPROTECT |
| 617 | static inline void pmdp_set_wrprotect(struct mm_struct *mm, |
| 618 | unsigned long address, pmd_t *pmdp) |
| 619 | { |
| 620 | ptep_set_wrprotect(mm, address, (pte_t *)pmdp); |
| 621 | } |
| 622 | #endif |
| 623 | #endif /* CONFIG_ARM64_HW_AFDBM */ |
| 624 | |
Catalin Marinas | 4f04d8f | 2012-03-05 11:49:27 +0000 | [diff] [blame] | 625 | extern pgd_t swapper_pg_dir[PTRS_PER_PGD]; |
| 626 | extern pgd_t idmap_pg_dir[PTRS_PER_PGD]; |
| 627 | |
Catalin Marinas | 4f04d8f | 2012-03-05 11:49:27 +0000 | [diff] [blame] | 628 | /* |
| 629 | * Encode and decode a swap entry: |
Catalin Marinas | 3676f9e | 2013-11-27 16:59:27 +0000 | [diff] [blame] | 630 | * bits 0-1: present (must be zero) |
Kirill A. Shutemov | 9b3e661 | 2015-02-10 14:10:15 -0800 | [diff] [blame] | 631 | * bits 2-7: swap type |
| 632 | * bits 8-57: swap offset |
Catalin Marinas | fdc69e7 | 2016-03-09 16:31:29 +0000 | [diff] [blame] | 633 | * bit 58: PTE_PROT_NONE (must be zero) |
Catalin Marinas | 4f04d8f | 2012-03-05 11:49:27 +0000 | [diff] [blame] | 634 | */ |
Kirill A. Shutemov | 9b3e661 | 2015-02-10 14:10:15 -0800 | [diff] [blame] | 635 | #define __SWP_TYPE_SHIFT 2 |
Catalin Marinas | 4f04d8f | 2012-03-05 11:49:27 +0000 | [diff] [blame] | 636 | #define __SWP_TYPE_BITS 6 |
Kirill A. Shutemov | 9b3e661 | 2015-02-10 14:10:15 -0800 | [diff] [blame] | 637 | #define __SWP_OFFSET_BITS 50 |
Catalin Marinas | 4f04d8f | 2012-03-05 11:49:27 +0000 | [diff] [blame] | 638 | #define __SWP_TYPE_MASK ((1 << __SWP_TYPE_BITS) - 1) |
| 639 | #define __SWP_OFFSET_SHIFT (__SWP_TYPE_BITS + __SWP_TYPE_SHIFT) |
Catalin Marinas | 3676f9e | 2013-11-27 16:59:27 +0000 | [diff] [blame] | 640 | #define __SWP_OFFSET_MASK ((1UL << __SWP_OFFSET_BITS) - 1) |
Catalin Marinas | 4f04d8f | 2012-03-05 11:49:27 +0000 | [diff] [blame] | 641 | |
| 642 | #define __swp_type(x) (((x).val >> __SWP_TYPE_SHIFT) & __SWP_TYPE_MASK) |
Catalin Marinas | 3676f9e | 2013-11-27 16:59:27 +0000 | [diff] [blame] | 643 | #define __swp_offset(x) (((x).val >> __SWP_OFFSET_SHIFT) & __SWP_OFFSET_MASK) |
Catalin Marinas | 4f04d8f | 2012-03-05 11:49:27 +0000 | [diff] [blame] | 644 | #define __swp_entry(type,offset) ((swp_entry_t) { ((type) << __SWP_TYPE_SHIFT) | ((offset) << __SWP_OFFSET_SHIFT) }) |
| 645 | |
| 646 | #define __pte_to_swp_entry(pte) ((swp_entry_t) { pte_val(pte) }) |
| 647 | #define __swp_entry_to_pte(swp) ((pte_t) { (swp).val }) |
| 648 | |
| 649 | /* |
| 650 | * Ensure that there are not more swap files than can be encoded in the kernel |
Geert Uytterhoeven | aad9061 | 2014-03-11 11:23:39 +0100 | [diff] [blame] | 651 | * PTEs. |
Catalin Marinas | 4f04d8f | 2012-03-05 11:49:27 +0000 | [diff] [blame] | 652 | */ |
| 653 | #define MAX_SWAPFILES_CHECK() BUILD_BUG_ON(MAX_SWAPFILES_SHIFT > __SWP_TYPE_BITS) |
| 654 | |
Catalin Marinas | 4f04d8f | 2012-03-05 11:49:27 +0000 | [diff] [blame] | 655 | extern int kern_addr_valid(unsigned long addr); |
| 656 | |
| 657 | #include <asm-generic/pgtable.h> |
| 658 | |
Will Deacon | 39b5be9 | 2016-01-05 15:36:59 +0000 | [diff] [blame] | 659 | void pgd_cache_init(void); |
| 660 | #define pgtable_cache_init pgd_cache_init |
Catalin Marinas | 4f04d8f | 2012-03-05 11:49:27 +0000 | [diff] [blame] | 661 | |
Will Deacon | cba3574 | 2015-07-16 19:26:02 +0100 | [diff] [blame] | 662 | /* |
| 663 | * On AArch64, the cache coherency is handled via the set_pte_at() function. |
| 664 | */ |
| 665 | static inline void update_mmu_cache(struct vm_area_struct *vma, |
| 666 | unsigned long addr, pte_t *ptep) |
| 667 | { |
| 668 | /* |
Will Deacon | 120798d | 2015-10-06 18:46:30 +0100 | [diff] [blame] | 669 | * We don't do anything here, so there's a very small chance of |
| 670 | * us retaking a user fault which we just fixed up. The alternative |
| 671 | * is doing a dsb(ishst), but that penalises the fastpath. |
Will Deacon | cba3574 | 2015-07-16 19:26:02 +0100 | [diff] [blame] | 672 | */ |
Will Deacon | cba3574 | 2015-07-16 19:26:02 +0100 | [diff] [blame] | 673 | } |
| 674 | |
| 675 | #define update_mmu_cache_pmd(vma, address, pmd) do { } while (0) |
| 676 | |
Catalin Marinas | 7db743c | 2015-10-16 14:34:50 +0100 | [diff] [blame] | 677 | #define kc_vaddr_to_offset(v) ((v) & ~VA_START) |
| 678 | #define kc_offset_to_vaddr(o) ((o) | VA_START) |
| 679 | |
Catalin Marinas | 4f04d8f | 2012-03-05 11:49:27 +0000 | [diff] [blame] | 680 | #endif /* !__ASSEMBLY__ */ |
| 681 | |
| 682 | #endif /* __ASM_PGTABLE_H */ |