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Paul Mackerrasde56a942011-06-29 00:21:34 +00001/*
2 * This program is free software; you can redistribute it and/or modify
3 * it under the terms of the GNU General Public License, version 2, as
4 * published by the Free Software Foundation.
5 *
6 * This program is distributed in the hope that it will be useful,
7 * but WITHOUT ANY WARRANTY; without even the implied warranty of
8 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
9 * GNU General Public License for more details.
10 *
11 * You should have received a copy of the GNU General Public License
12 * along with this program; if not, write to the Free Software
13 * Foundation, 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
14 *
15 * Copyright 2011 Paul Mackerras, IBM Corp. <paulus@au1.ibm.com>
16 *
17 * Derived from book3s_interrupts.S, which is:
18 * Copyright SUSE Linux Products GmbH 2009
19 *
20 * Authors: Alexander Graf <agraf@suse.de>
21 */
22
23#include <asm/ppc_asm.h>
24#include <asm/kvm_asm.h>
25#include <asm/reg.h>
26#include <asm/page.h>
27#include <asm/asm-offsets.h>
28#include <asm/exception-64s.h>
29#include <asm/ppc-opcode.h>
30
31/*****************************************************************************
32 * *
33 * Guest entry / exit code that is in kernel module memory (vmalloc) *
34 * *
35 ****************************************************************************/
36
37/* Registers:
38 * r4: vcpu pointer
39 */
40_GLOBAL(__kvmppc_vcore_entry)
41
42 /* Write correct stack frame */
43 mflr r0
44 std r0,PPC_LR_STKOFF(r1)
45
46 /* Save host state to the stack */
47 stdu r1, -SWITCH_FRAME_SIZE(r1)
48
Paul Mackerrasa5ddea02012-02-03 00:53:21 +000049 /* Save non-volatile registers (r14 - r31) and CR */
Paul Mackerrasde56a942011-06-29 00:21:34 +000050 SAVE_NVGPRS(r1)
Paul Mackerrasa5ddea02012-02-03 00:53:21 +000051 mfcr r3
52 std r3, _CCR(r1)
Paul Mackerrasde56a942011-06-29 00:21:34 +000053
54 /* Save host DSCR */
Paul Mackerras9e368f22011-06-29 00:40:08 +000055BEGIN_FTR_SECTION
Paul Mackerrasde56a942011-06-29 00:21:34 +000056 mfspr r3, SPRN_DSCR
57 std r3, HSTATE_DSCR(r13)
Paul Mackerras9e368f22011-06-29 00:40:08 +000058END_FTR_SECTION_IFSET(CPU_FTR_ARCH_206)
Paul Mackerrasde56a942011-06-29 00:21:34 +000059
60 /* Save host DABR */
61 mfspr r3, SPRN_DABR
62 std r3, HSTATE_DABR(r13)
63
64 /* Hard-disable interrupts */
65 mfmsr r10
66 std r10, HSTATE_HOST_MSR(r13)
67 rldicl r10,r10,48,1
68 rotldi r10,r10,16
69 mtmsrd r10,1
70
71 /* Save host PMU registers and load guest PMU registers */
72 /* R4 is live here (vcpu pointer) but not r3 or r5 */
73 li r3, 1
74 sldi r3, r3, 31 /* MMCR0_FC (freeze counters) bit */
75 mfspr r7, SPRN_MMCR0 /* save MMCR0 */
76 mtspr SPRN_MMCR0, r3 /* freeze all counters, disable interrupts */
77 isync
78 ld r3, PACALPPACAPTR(r13) /* is the host using the PMU? */
79 lbz r5, LPPACA_PMCINUSE(r3)
80 cmpwi r5, 0
81 beq 31f /* skip if not */
82 mfspr r5, SPRN_MMCR1
83 mfspr r6, SPRN_MMCRA
84 std r7, HSTATE_MMCR(r13)
85 std r5, HSTATE_MMCR + 8(r13)
86 std r6, HSTATE_MMCR + 16(r13)
87 mfspr r3, SPRN_PMC1
88 mfspr r5, SPRN_PMC2
89 mfspr r6, SPRN_PMC3
90 mfspr r7, SPRN_PMC4
91 mfspr r8, SPRN_PMC5
92 mfspr r9, SPRN_PMC6
Paul Mackerras9e368f22011-06-29 00:40:08 +000093BEGIN_FTR_SECTION
94 mfspr r10, SPRN_PMC7
95 mfspr r11, SPRN_PMC8
96END_FTR_SECTION_IFSET(CPU_FTR_ARCH_201)
Paul Mackerrasde56a942011-06-29 00:21:34 +000097 stw r3, HSTATE_PMC(r13)
98 stw r5, HSTATE_PMC + 4(r13)
99 stw r6, HSTATE_PMC + 8(r13)
100 stw r7, HSTATE_PMC + 12(r13)
101 stw r8, HSTATE_PMC + 16(r13)
102 stw r9, HSTATE_PMC + 20(r13)
Paul Mackerras9e368f22011-06-29 00:40:08 +0000103BEGIN_FTR_SECTION
104 stw r10, HSTATE_PMC + 24(r13)
105 stw r11, HSTATE_PMC + 28(r13)
106END_FTR_SECTION_IFSET(CPU_FTR_ARCH_201)
Paul Mackerrasde56a942011-06-29 00:21:34 +000010731:
108
109 /*
110 * Put whatever is in the decrementer into the
111 * hypervisor decrementer.
112 */
113 mfspr r8,SPRN_DEC
114 mftb r7
115 mtspr SPRN_HDEC,r8
116 extsw r8,r8
117 add r8,r8,r7
118 std r8,HSTATE_DECEXP(r13)
119
Paul Mackerras9e368f22011-06-29 00:40:08 +0000120 /*
121 * On PPC970, if the guest vcpu has an external interrupt pending,
122 * send ourselves an IPI so as to interrupt the guest once it
123 * enables interrupts. (It must have interrupts disabled,
124 * otherwise we would already have delivered the interrupt.)
125 */
126BEGIN_FTR_SECTION
127 ld r0, VCPU_PENDING_EXC(r4)
128 li r7, (1 << BOOK3S_IRQPRIO_EXTERNAL)
129 oris r7, r7, (1 << BOOK3S_IRQPRIO_EXTERNAL_LEVEL)@h
130 and. r0, r0, r7
131 beq 32f
132 mr r31, r4
133 lhz r3, PACAPACAINDEX(r13)
134 bl smp_send_reschedule
135 nop
136 mr r4, r31
13732:
138END_FTR_SECTION_IFSET(CPU_FTR_ARCH_201)
139
Paul Mackerrasde56a942011-06-29 00:21:34 +0000140 /* Jump to partition switch code */
141 bl .kvmppc_hv_entry_trampoline
142 nop
143
144/*
145 * We return here in virtual mode after the guest exits
146 * with something that we can't handle in real mode.
147 * Interrupts are enabled again at this point.
148 */
149
150.global kvmppc_handler_highmem
151kvmppc_handler_highmem:
152
153 /*
154 * Register usage at this point:
155 *
156 * R1 = host R1
157 * R2 = host R2
158 * R12 = exit handler id
159 * R13 = PACA
160 */
161
Paul Mackerrasa5ddea02012-02-03 00:53:21 +0000162 /* Restore non-volatile host registers (r14 - r31) and CR */
Paul Mackerrasde56a942011-06-29 00:21:34 +0000163 REST_NVGPRS(r1)
Paul Mackerrasa5ddea02012-02-03 00:53:21 +0000164 ld r4, _CCR(r1)
165 mtcr r4
Paul Mackerrasde56a942011-06-29 00:21:34 +0000166
167 addi r1, r1, SWITCH_FRAME_SIZE
168 ld r0, PPC_LR_STKOFF(r1)
169 mtlr r0
170 blr