Documentation/devicetree/bindings/mmc/mmc.txt

These properties are common to multiple MMC host controllers. Any host
that requires the respective functionality should implement them using
these definitions.

Interpreted by the OF core:
- reg: Registers location and length.
- interrupts: Interrupts used by the MMC controller.

Card detection:
If no property below is supplied, host native card detect is used.
Only one of the properties in this section should be supplied:
  - broken-cd: There is no card detection available; polling must be used.
  - cd-gpios: Specify GPIOs for card detection, see gpio binding
  - non-removable: non-removable slot (like eMMC); assume always present.

Optional properties:
- bus-width: Number of data lines, can be <1>, <4>, or <8>.  The default
  will be <1> if the property is absent.
- wp-gpios: Specify GPIOs for write protection, see gpio binding
- cd-inverted: when present, polarity on the CD line is inverted. See the note
  below for the case, when a GPIO is used for the CD line
- wp-inverted: when present, polarity on the WP line is inverted. See the note
  below for the case, when a GPIO is used for the WP line
- disable-wp: When set no physical WP line is present. This property should
  only be specified when the controller has a dedicated write-protect
  detection logic. If a GPIO is always used for the write-protect detection
  logic it is sufficient to not specify wp-gpios property in the absence of a WP
  line.
- max-frequency: maximum operating clock frequency
- no-1-8-v: when present, denotes that 1.8v card voltage is not supported on
  this system, even if the controller claims it is.
- cap-sd-highspeed: SD high-speed timing is supported
- cap-mmc-highspeed: MMC high-speed timing is supported
- sd-uhs-sdr12: SD UHS SDR12 speed is supported
- sd-uhs-sdr25: SD UHS SDR25 speed is supported
- sd-uhs-sdr50: SD UHS SDR50 speed is supported
- sd-uhs-sdr104: SD UHS SDR104 speed is supported
- sd-uhs-ddr50: SD UHS DDR50 speed is supported
- cap-power-off-card: powering off the card is safe
- cap-mmc-hw-reset: eMMC hardware reset is supported
- cap-sdio-irq: enable SDIO IRQ signalling on this interface
- full-pwr-cycle: full power cycle of the card is supported
- mmc-ddr-1_8v: eMMC high-speed DDR mode(1.8V I/O) is supported
- mmc-ddr-1_2v: eMMC high-speed DDR mode(1.2V I/O) is supported
- mmc-hs200-1_8v: eMMC HS200 mode(1.8V I/O) is supported
- mmc-hs200-1_2v: eMMC HS200 mode(1.2V I/O) is supported
- mmc-hs400-1_8v: eMMC HS400 mode(1.8V I/O) is supported
- mmc-hs400-1_2v: eMMC HS400 mode(1.2V I/O) is supported
- mmc-hs400-enhanced-strobe: eMMC HS400 enhanced strobe mode is supported
- dsr: Value the card's (optional) Driver Stage Register (DSR) should be
  programmed with. Valid range: [0 .. 0xffff].

*NOTE* on CD and WP polarity. To use common for all SD/MMC host controllers line
polarity properties, we have to fix the meaning of the "normal" and "inverted"
line levels. We choose to follow the SDHCI standard, which specifies both those
lines as "active low." Therefore, using the "cd-inverted" property means, that
the CD line is active high, i.e. it is high, when a card is inserted. Similar
logic applies to the "wp-inverted" property.

CD and WP lines can be implemented on the hardware in one of two ways: as GPIOs,
specified in cd-gpios and wp-gpios properties, or as dedicated pins. Polarity of
dedicated pins can be specified, using *-inverted properties. GPIO polarity can
also be specified using the OF_GPIO_ACTIVE_LOW flag. This creates an ambiguity
in the latter case. We choose to use the XOR logic for GPIO CD and WP lines.
This means, the two properties are "superimposed," for example leaving the
OF_GPIO_ACTIVE_LOW flag clear and specifying the respective *-inverted
property results in a double-inversion and actually means the "normal" line
polarity is in effect.

Optional SDIO properties:
- keep-power-in-suspend: Preserves card power during a suspend/resume cycle
- wakeup-source: Enables wake up of host system on SDIO IRQ assertion
		 (Legacy property supported: "enable-sdio-wakeup")


MMC power sequences:
--------------------

System on chip designs may specify a specific MMC power sequence. To
successfully detect an (e)MMC/SD/SDIO card, that power sequence must be
maintained while initializing the card.

Optional property:
- mmc-pwrseq: phandle to the MMC power sequence node. See "mmc-pwrseq-*"
	for documentation of MMC power sequence bindings.


Use of Function subnodes
------------------------

On embedded systems the cards connected to a host may need additional
properties. These can be specified in subnodes to the host controller node.
The subnodes are identified by the standard 'reg' property.
Which information exactly can be specified depends on the bindings for the
SDIO function driver for the subnode, as specified by the compatible string.

Required host node properties when using function subnodes:
- #address-cells: should be one. The cell is the slot id.
- #size-cells: should be zero.

Required function subnode properties:
- compatible: name of SDIO function following generic names recommended practice
- reg: Must contain the SDIO function number of the function this subnode
       describes. A value of 0 denotes the memory SD function, values from
       1 to 7 denote the SDIO functions.


Examples
--------

Basic example:

sdhci@ab000000 {
	compatible = "sdhci";
	reg = <0xab000000 0x200>;
	interrupts = <23>;
	bus-width = <4>;
	cd-gpios = <&gpio 69 0>;
	cd-inverted;
	wp-gpios = <&gpio 70 0>;
	max-frequency = <50000000>;
	keep-power-in-suspend;
	wakeup-source;
	mmc-pwrseq = <&sdhci0_pwrseq>
}

Example with sdio function subnode:

mmc3: mmc@01c12000 {
	#address-cells = <1>;
	#size-cells = <0>;

	pinctrl-names = "default";
	pinctrl-0 = <&mmc3_pins_a>;
	vmmc-supply = <&reg_vmmc3>;
	bus-width = <4>;
	non-removable;
	mmc-pwrseq = <&sdhci0_pwrseq>
	status = "okay";

	brcmf: bcrmf@1 {
		reg = <1>;
		compatible = "brcm,bcm43xx-fmac";
		interrupt-parent = <&pio>;
		interrupts = <10 8>; /* PH10 / EINT10 */
		interrupt-names = "host-wake";
	};
};