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David Howells108b42b2006-03-31 16:00:29 +01001 ============================
2 LINUX KERNEL MEMORY BARRIERS
3 ============================
4
5By: David Howells <dhowells@redhat.com>
David Howells90fddab2010-03-24 09:43:00 +00006 Paul E. McKenney <paulmck@linux.vnet.ibm.com>
David Howells108b42b2006-03-31 16:00:29 +01007
8Contents:
9
10 (*) Abstract memory access model.
11
12 - Device operations.
13 - Guarantees.
14
15 (*) What are memory barriers?
16
17 - Varieties of memory barrier.
18 - What may not be assumed about memory barriers?
19 - Data dependency barriers.
20 - Control dependencies.
21 - SMP barrier pairing.
22 - Examples of memory barrier sequences.
David Howells670bd952006-06-10 09:54:12 -070023 - Read memory barriers vs load speculation.
Paul E. McKenney241e6662011-02-10 16:54:50 -080024 - Transitivity
David Howells108b42b2006-03-31 16:00:29 +010025
26 (*) Explicit kernel barriers.
27
28 - Compiler barrier.
Jarek Poplawski81fc6322007-05-23 13:58:20 -070029 - CPU memory barriers.
David Howells108b42b2006-03-31 16:00:29 +010030 - MMIO write barrier.
31
32 (*) Implicit kernel memory barriers.
33
34 - Locking functions.
35 - Interrupt disabling functions.
David Howells50fa6102009-04-28 15:01:38 +010036 - Sleep and wake-up functions.
David Howells108b42b2006-03-31 16:00:29 +010037 - Miscellaneous functions.
38
39 (*) Inter-CPU locking barrier effects.
40
41 - Locks vs memory accesses.
42 - Locks vs I/O accesses.
43
44 (*) Where are memory barriers needed?
45
46 - Interprocessor interaction.
47 - Atomic operations.
48 - Accessing devices.
49 - Interrupts.
50
51 (*) Kernel I/O barrier effects.
52
53 (*) Assumed minimum execution ordering model.
54
55 (*) The effects of the cpu cache.
56
57 - Cache coherency.
58 - Cache coherency vs DMA.
59 - Cache coherency vs MMIO.
60
61 (*) The things CPUs get up to.
62
63 - And then there's the Alpha.
64
David Howells90fddab2010-03-24 09:43:00 +000065 (*) Example uses.
66
67 - Circular buffers.
68
David Howells108b42b2006-03-31 16:00:29 +010069 (*) References.
70
71
72============================
73ABSTRACT MEMORY ACCESS MODEL
74============================
75
76Consider the following abstract model of the system:
77
78 : :
79 : :
80 : :
81 +-------+ : +--------+ : +-------+
82 | | : | | : | |
83 | | : | | : | |
84 | CPU 1 |<----->| Memory |<----->| CPU 2 |
85 | | : | | : | |
86 | | : | | : | |
87 +-------+ : +--------+ : +-------+
88 ^ : ^ : ^
89 | : | : |
90 | : | : |
91 | : v : |
92 | : +--------+ : |
93 | : | | : |
94 | : | | : |
95 +---------->| Device |<----------+
96 : | | :
97 : | | :
98 : +--------+ :
99 : :
100
101Each CPU executes a program that generates memory access operations. In the
102abstract CPU, memory operation ordering is very relaxed, and a CPU may actually
103perform the memory operations in any order it likes, provided program causality
104appears to be maintained. Similarly, the compiler may also arrange the
105instructions it emits in any order it likes, provided it doesn't affect the
106apparent operation of the program.
107
108So in the above diagram, the effects of the memory operations performed by a
109CPU are perceived by the rest of the system as the operations cross the
110interface between the CPU and rest of the system (the dotted lines).
111
112
113For example, consider the following sequence of events:
114
115 CPU 1 CPU 2
116 =============== ===============
117 { A == 1; B == 2 }
118 A = 3; x = A;
119 B = 4; y = B;
120
121The set of accesses as seen by the memory system in the middle can be arranged
122in 24 different combinations:
123
124 STORE A=3, STORE B=4, x=LOAD A->3, y=LOAD B->4
125 STORE A=3, STORE B=4, y=LOAD B->4, x=LOAD A->3
126 STORE A=3, x=LOAD A->3, STORE B=4, y=LOAD B->4
127 STORE A=3, x=LOAD A->3, y=LOAD B->2, STORE B=4
128 STORE A=3, y=LOAD B->2, STORE B=4, x=LOAD A->3
129 STORE A=3, y=LOAD B->2, x=LOAD A->3, STORE B=4
130 STORE B=4, STORE A=3, x=LOAD A->3, y=LOAD B->4
131 STORE B=4, ...
132 ...
133
134and can thus result in four different combinations of values:
135
136 x == 1, y == 2
137 x == 1, y == 4
138 x == 3, y == 2
139 x == 3, y == 4
140
141
142Furthermore, the stores committed by a CPU to the memory system may not be
143perceived by the loads made by another CPU in the same order as the stores were
144committed.
145
146
147As a further example, consider this sequence of events:
148
149 CPU 1 CPU 2
150 =============== ===============
151 { A == 1, B == 2, C = 3, P == &A, Q == &C }
152 B = 4; Q = P;
153 P = &B D = *Q;
154
155There is an obvious data dependency here, as the value loaded into D depends on
156the address retrieved from P by CPU 2. At the end of the sequence, any of the
157following results are possible:
158
159 (Q == &A) and (D == 1)
160 (Q == &B) and (D == 2)
161 (Q == &B) and (D == 4)
162
163Note that CPU 2 will never try and load C into D because the CPU will load P
164into Q before issuing the load of *Q.
165
166
167DEVICE OPERATIONS
168-----------------
169
170Some devices present their control interfaces as collections of memory
171locations, but the order in which the control registers are accessed is very
172important. For instance, imagine an ethernet card with a set of internal
173registers that are accessed through an address port register (A) and a data
174port register (D). To read internal register 5, the following code might then
175be used:
176
177 *A = 5;
178 x = *D;
179
180but this might show up as either of the following two sequences:
181
182 STORE *A = 5, x = LOAD *D
183 x = LOAD *D, STORE *A = 5
184
185the second of which will almost certainly result in a malfunction, since it set
186the address _after_ attempting to read the register.
187
188
189GUARANTEES
190----------
191
192There are some minimal guarantees that may be expected of a CPU:
193
194 (*) On any given CPU, dependent memory accesses will be issued in order, with
195 respect to itself. This means that for:
196
Paul E. McKenney2ecf8102013-12-11 13:59:04 -0800197 ACCESS_ONCE(Q) = P; smp_read_barrier_depends(); D = ACCESS_ONCE(*Q);
David Howells108b42b2006-03-31 16:00:29 +0100198
199 the CPU will issue the following memory operations:
200
201 Q = LOAD P, D = LOAD *Q
202
Paul E. McKenney2ecf8102013-12-11 13:59:04 -0800203 and always in that order. On most systems, smp_read_barrier_depends()
204 does nothing, but it is required for DEC Alpha. The ACCESS_ONCE()
205 is required to prevent compiler mischief. Please note that you
206 should normally use something like rcu_dereference() instead of
207 open-coding smp_read_barrier_depends().
David Howells108b42b2006-03-31 16:00:29 +0100208
209 (*) Overlapping loads and stores within a particular CPU will appear to be
210 ordered within that CPU. This means that for:
211
Paul E. McKenney2ecf8102013-12-11 13:59:04 -0800212 a = ACCESS_ONCE(*X); ACCESS_ONCE(*X) = b;
David Howells108b42b2006-03-31 16:00:29 +0100213
214 the CPU will only issue the following sequence of memory operations:
215
216 a = LOAD *X, STORE *X = b
217
218 And for:
219
Paul E. McKenney2ecf8102013-12-11 13:59:04 -0800220 ACCESS_ONCE(*X) = c; d = ACCESS_ONCE(*X);
David Howells108b42b2006-03-31 16:00:29 +0100221
222 the CPU will only issue:
223
224 STORE *X = c, d = LOAD *X
225
Matt LaPlantefa00e7e2006-11-30 04:55:36 +0100226 (Loads and stores overlap if they are targeted at overlapping pieces of
David Howells108b42b2006-03-31 16:00:29 +0100227 memory).
228
229And there are a number of things that _must_ or _must_not_ be assumed:
230
Paul E. McKenney2ecf8102013-12-11 13:59:04 -0800231 (*) It _must_not_ be assumed that the compiler will do what you want with
232 memory references that are not protected by ACCESS_ONCE(). Without
233 ACCESS_ONCE(), the compiler is within its rights to do all sorts
Paul E. McKenney692118d2013-12-11 13:59:07 -0800234 of "creative" transformations, which are covered in the Compiler
235 Barrier section.
Paul E. McKenney2ecf8102013-12-11 13:59:04 -0800236
David Howells108b42b2006-03-31 16:00:29 +0100237 (*) It _must_not_ be assumed that independent loads and stores will be issued
238 in the order given. This means that for:
239
240 X = *A; Y = *B; *D = Z;
241
242 we may get any of the following sequences:
243
244 X = LOAD *A, Y = LOAD *B, STORE *D = Z
245 X = LOAD *A, STORE *D = Z, Y = LOAD *B
246 Y = LOAD *B, X = LOAD *A, STORE *D = Z
247 Y = LOAD *B, STORE *D = Z, X = LOAD *A
248 STORE *D = Z, X = LOAD *A, Y = LOAD *B
249 STORE *D = Z, Y = LOAD *B, X = LOAD *A
250
251 (*) It _must_ be assumed that overlapping memory accesses may be merged or
252 discarded. This means that for:
253
254 X = *A; Y = *(A + 4);
255
256 we may get any one of the following sequences:
257
258 X = LOAD *A; Y = LOAD *(A + 4);
259 Y = LOAD *(A + 4); X = LOAD *A;
260 {X, Y} = LOAD {*A, *(A + 4) };
261
262 And for:
263
Paul E. McKenneyf191eec2012-10-03 10:28:30 -0700264 *A = X; *(A + 4) = Y;
David Howells108b42b2006-03-31 16:00:29 +0100265
Paul E. McKenneyf191eec2012-10-03 10:28:30 -0700266 we may get any of:
David Howells108b42b2006-03-31 16:00:29 +0100267
Paul E. McKenneyf191eec2012-10-03 10:28:30 -0700268 STORE *A = X; STORE *(A + 4) = Y;
269 STORE *(A + 4) = Y; STORE *A = X;
270 STORE {*A, *(A + 4) } = {X, Y};
David Howells108b42b2006-03-31 16:00:29 +0100271
272
273=========================
274WHAT ARE MEMORY BARRIERS?
275=========================
276
277As can be seen above, independent memory operations are effectively performed
278in random order, but this can be a problem for CPU-CPU interaction and for I/O.
279What is required is some way of intervening to instruct the compiler and the
280CPU to restrict the order.
281
282Memory barriers are such interventions. They impose a perceived partial
David Howells2b948952006-06-25 05:48:49 -0700283ordering over the memory operations on either side of the barrier.
284
285Such enforcement is important because the CPUs and other devices in a system
Jarek Poplawski81fc6322007-05-23 13:58:20 -0700286can use a variety of tricks to improve performance, including reordering,
David Howells2b948952006-06-25 05:48:49 -0700287deferral and combination of memory operations; speculative loads; speculative
288branch prediction and various types of caching. Memory barriers are used to
289override or suppress these tricks, allowing the code to sanely control the
290interaction of multiple CPUs and/or devices.
David Howells108b42b2006-03-31 16:00:29 +0100291
292
293VARIETIES OF MEMORY BARRIER
294---------------------------
295
296Memory barriers come in four basic varieties:
297
298 (1) Write (or store) memory barriers.
299
300 A write memory barrier gives a guarantee that all the STORE operations
301 specified before the barrier will appear to happen before all the STORE
302 operations specified after the barrier with respect to the other
303 components of the system.
304
305 A write barrier is a partial ordering on stores only; it is not required
306 to have any effect on loads.
307
David Howells6bc39272006-06-25 05:49:22 -0700308 A CPU can be viewed as committing a sequence of store operations to the
David Howells108b42b2006-03-31 16:00:29 +0100309 memory system as time progresses. All stores before a write barrier will
310 occur in the sequence _before_ all the stores after the write barrier.
311
312 [!] Note that write barriers should normally be paired with read or data
313 dependency barriers; see the "SMP barrier pairing" subsection.
314
315
316 (2) Data dependency barriers.
317
318 A data dependency barrier is a weaker form of read barrier. In the case
319 where two loads are performed such that the second depends on the result
320 of the first (eg: the first load retrieves the address to which the second
321 load will be directed), a data dependency barrier would be required to
322 make sure that the target of the second load is updated before the address
323 obtained by the first load is accessed.
324
325 A data dependency barrier is a partial ordering on interdependent loads
326 only; it is not required to have any effect on stores, independent loads
327 or overlapping loads.
328
329 As mentioned in (1), the other CPUs in the system can be viewed as
330 committing sequences of stores to the memory system that the CPU being
331 considered can then perceive. A data dependency barrier issued by the CPU
332 under consideration guarantees that for any load preceding it, if that
333 load touches one of a sequence of stores from another CPU, then by the
334 time the barrier completes, the effects of all the stores prior to that
335 touched by the load will be perceptible to any loads issued after the data
336 dependency barrier.
337
338 See the "Examples of memory barrier sequences" subsection for diagrams
339 showing the ordering constraints.
340
341 [!] Note that the first load really has to have a _data_ dependency and
342 not a control dependency. If the address for the second load is dependent
343 on the first load, but the dependency is through a conditional rather than
344 actually loading the address itself, then it's a _control_ dependency and
345 a full read barrier or better is required. See the "Control dependencies"
346 subsection for more information.
347
348 [!] Note that data dependency barriers should normally be paired with
349 write barriers; see the "SMP barrier pairing" subsection.
350
351
352 (3) Read (or load) memory barriers.
353
354 A read barrier is a data dependency barrier plus a guarantee that all the
355 LOAD operations specified before the barrier will appear to happen before
356 all the LOAD operations specified after the barrier with respect to the
357 other components of the system.
358
359 A read barrier is a partial ordering on loads only; it is not required to
360 have any effect on stores.
361
362 Read memory barriers imply data dependency barriers, and so can substitute
363 for them.
364
365 [!] Note that read barriers should normally be paired with write barriers;
366 see the "SMP barrier pairing" subsection.
367
368
369 (4) General memory barriers.
370
David Howells670bd952006-06-10 09:54:12 -0700371 A general memory barrier gives a guarantee that all the LOAD and STORE
372 operations specified before the barrier will appear to happen before all
373 the LOAD and STORE operations specified after the barrier with respect to
374 the other components of the system.
375
376 A general memory barrier is a partial ordering over both loads and stores.
David Howells108b42b2006-03-31 16:00:29 +0100377
378 General memory barriers imply both read and write memory barriers, and so
379 can substitute for either.
380
381
382And a couple of implicit varieties:
383
Peter Zijlstra2e4f5382013-11-06 14:57:36 +0100384 (5) ACQUIRE operations.
David Howells108b42b2006-03-31 16:00:29 +0100385
386 This acts as a one-way permeable barrier. It guarantees that all memory
Peter Zijlstra2e4f5382013-11-06 14:57:36 +0100387 operations after the ACQUIRE operation will appear to happen after the
388 ACQUIRE operation with respect to the other components of the system.
389 ACQUIRE operations include LOCK operations and smp_load_acquire()
390 operations.
David Howells108b42b2006-03-31 16:00:29 +0100391
Peter Zijlstra2e4f5382013-11-06 14:57:36 +0100392 Memory operations that occur before an ACQUIRE operation may appear to
393 happen after it completes.
David Howells108b42b2006-03-31 16:00:29 +0100394
Peter Zijlstra2e4f5382013-11-06 14:57:36 +0100395 An ACQUIRE operation should almost always be paired with a RELEASE
396 operation.
David Howells108b42b2006-03-31 16:00:29 +0100397
398
Peter Zijlstra2e4f5382013-11-06 14:57:36 +0100399 (6) RELEASE operations.
David Howells108b42b2006-03-31 16:00:29 +0100400
401 This also acts as a one-way permeable barrier. It guarantees that all
Peter Zijlstra2e4f5382013-11-06 14:57:36 +0100402 memory operations before the RELEASE operation will appear to happen
403 before the RELEASE operation with respect to the other components of the
404 system. RELEASE operations include UNLOCK operations and
405 smp_store_release() operations.
David Howells108b42b2006-03-31 16:00:29 +0100406
Peter Zijlstra2e4f5382013-11-06 14:57:36 +0100407 Memory operations that occur after a RELEASE operation may appear to
David Howells108b42b2006-03-31 16:00:29 +0100408 happen before it completes.
409
Peter Zijlstra2e4f5382013-11-06 14:57:36 +0100410 The use of ACQUIRE and RELEASE operations generally precludes the need
411 for other sorts of memory barrier (but note the exceptions mentioned in
412 the subsection "MMIO write barrier"). In addition, a RELEASE+ACQUIRE
413 pair is -not- guaranteed to act as a full memory barrier. However, after
414 an ACQUIRE on a given variable, all memory accesses preceding any prior
415 RELEASE on that same variable are guaranteed to be visible. In other
416 words, within a given variable's critical section, all accesses of all
417 previous critical sections for that variable are guaranteed to have
418 completed.
Paul E. McKenney17eb88e2013-12-11 13:59:09 -0800419
Peter Zijlstra2e4f5382013-11-06 14:57:36 +0100420 This means that ACQUIRE acts as a minimal "acquire" operation and
421 RELEASE acts as a minimal "release" operation.
David Howells108b42b2006-03-31 16:00:29 +0100422
423
424Memory barriers are only required where there's a possibility of interaction
425between two CPUs or between a CPU and a device. If it can be guaranteed that
426there won't be any such interaction in any particular piece of code, then
427memory barriers are unnecessary in that piece of code.
428
429
430Note that these are the _minimum_ guarantees. Different architectures may give
431more substantial guarantees, but they may _not_ be relied upon outside of arch
432specific code.
433
434
435WHAT MAY NOT BE ASSUMED ABOUT MEMORY BARRIERS?
436----------------------------------------------
437
438There are certain things that the Linux kernel memory barriers do not guarantee:
439
440 (*) There is no guarantee that any of the memory accesses specified before a
441 memory barrier will be _complete_ by the completion of a memory barrier
442 instruction; the barrier can be considered to draw a line in that CPU's
443 access queue that accesses of the appropriate type may not cross.
444
445 (*) There is no guarantee that issuing a memory barrier on one CPU will have
446 any direct effect on another CPU or any other hardware in the system. The
447 indirect effect will be the order in which the second CPU sees the effects
448 of the first CPU's accesses occur, but see the next point:
449
David Howells6bc39272006-06-25 05:49:22 -0700450 (*) There is no guarantee that a CPU will see the correct order of effects
David Howells108b42b2006-03-31 16:00:29 +0100451 from a second CPU's accesses, even _if_ the second CPU uses a memory
452 barrier, unless the first CPU _also_ uses a matching memory barrier (see
453 the subsection on "SMP Barrier Pairing").
454
455 (*) There is no guarantee that some intervening piece of off-the-CPU
456 hardware[*] will not reorder the memory accesses. CPU cache coherency
457 mechanisms should propagate the indirect effects of a memory barrier
458 between CPUs, but might not do so in order.
459
460 [*] For information on bus mastering DMA and coherency please read:
461
Randy Dunlap4b5ff462008-03-10 17:16:32 -0700462 Documentation/PCI/pci.txt
Paul Bolle395cf962011-08-15 02:02:26 +0200463 Documentation/DMA-API-HOWTO.txt
David Howells108b42b2006-03-31 16:00:29 +0100464 Documentation/DMA-API.txt
465
466
467DATA DEPENDENCY BARRIERS
468------------------------
469
470The usage requirements of data dependency barriers are a little subtle, and
471it's not always obvious that they're needed. To illustrate, consider the
472following sequence of events:
473
Paul E. McKenney2ecf8102013-12-11 13:59:04 -0800474 CPU 1 CPU 2
475 =============== ===============
David Howells108b42b2006-03-31 16:00:29 +0100476 { A == 1, B == 2, C = 3, P == &A, Q == &C }
477 B = 4;
478 <write barrier>
Paul E. McKenney2ecf8102013-12-11 13:59:04 -0800479 ACCESS_ONCE(P) = &B
480 Q = ACCESS_ONCE(P);
481 D = *Q;
David Howells108b42b2006-03-31 16:00:29 +0100482
483There's a clear data dependency here, and it would seem that by the end of the
484sequence, Q must be either &A or &B, and that:
485
486 (Q == &A) implies (D == 1)
487 (Q == &B) implies (D == 4)
488
Jarek Poplawski81fc6322007-05-23 13:58:20 -0700489But! CPU 2's perception of P may be updated _before_ its perception of B, thus
David Howells108b42b2006-03-31 16:00:29 +0100490leading to the following situation:
491
492 (Q == &B) and (D == 2) ????
493
494Whilst this may seem like a failure of coherency or causality maintenance, it
495isn't, and this behaviour can be observed on certain real CPUs (such as the DEC
496Alpha).
497
David Howells2b948952006-06-25 05:48:49 -0700498To deal with this, a data dependency barrier or better must be inserted
499between the address load and the data load:
David Howells108b42b2006-03-31 16:00:29 +0100500
Paul E. McKenney2ecf8102013-12-11 13:59:04 -0800501 CPU 1 CPU 2
502 =============== ===============
David Howells108b42b2006-03-31 16:00:29 +0100503 { A == 1, B == 2, C = 3, P == &A, Q == &C }
504 B = 4;
505 <write barrier>
Paul E. McKenney2ecf8102013-12-11 13:59:04 -0800506 ACCESS_ONCE(P) = &B
507 Q = ACCESS_ONCE(P);
508 <data dependency barrier>
509 D = *Q;
David Howells108b42b2006-03-31 16:00:29 +0100510
511This enforces the occurrence of one of the two implications, and prevents the
512third possibility from arising.
513
514[!] Note that this extremely counterintuitive situation arises most easily on
515machines with split caches, so that, for example, one cache bank processes
516even-numbered cache lines and the other bank processes odd-numbered cache
517lines. The pointer P might be stored in an odd-numbered cache line, and the
518variable B might be stored in an even-numbered cache line. Then, if the
519even-numbered bank of the reading CPU's cache is extremely busy while the
520odd-numbered bank is idle, one can see the new value of the pointer P (&B),
David Howells6bc39272006-06-25 05:49:22 -0700521but the old value of the variable B (2).
David Howells108b42b2006-03-31 16:00:29 +0100522
523
Ingo Molnare0edc782013-11-22 11:24:53 +0100524Another example of where data dependency barriers might be required is where a
David Howells108b42b2006-03-31 16:00:29 +0100525number is read from memory and then used to calculate the index for an array
526access:
527
Paul E. McKenney2ecf8102013-12-11 13:59:04 -0800528 CPU 1 CPU 2
529 =============== ===============
David Howells108b42b2006-03-31 16:00:29 +0100530 { M[0] == 1, M[1] == 2, M[3] = 3, P == 0, Q == 3 }
531 M[1] = 4;
532 <write barrier>
Paul E. McKenney2ecf8102013-12-11 13:59:04 -0800533 ACCESS_ONCE(P) = 1
534 Q = ACCESS_ONCE(P);
535 <data dependency barrier>
536 D = M[Q];
David Howells108b42b2006-03-31 16:00:29 +0100537
538
Paul E. McKenney2ecf8102013-12-11 13:59:04 -0800539The data dependency barrier is very important to the RCU system,
540for example. See rcu_assign_pointer() and rcu_dereference() in
541include/linux/rcupdate.h. This permits the current target of an RCU'd
542pointer to be replaced with a new modified target, without the replacement
543target appearing to be incompletely initialised.
David Howells108b42b2006-03-31 16:00:29 +0100544
545See also the subsection on "Cache Coherency" for a more thorough example.
546
547
548CONTROL DEPENDENCIES
549--------------------
550
551A control dependency requires a full read memory barrier, not simply a data
552dependency barrier to make it work correctly. Consider the following bit of
553code:
554
Paul E. McKenney2ecf8102013-12-11 13:59:04 -0800555 q = ACCESS_ONCE(a);
Peter Zijlstra18c03c62013-12-11 13:59:06 -0800556 if (q) {
557 <data dependency barrier> /* BUG: No data dependency!!! */
558 p = ACCESS_ONCE(b);
Paul E. McKenney45c8a362013-07-02 15:24:09 -0700559 }
David Howells108b42b2006-03-31 16:00:29 +0100560
561This will not have the desired effect because there is no actual data
Paul E. McKenney2ecf8102013-12-11 13:59:04 -0800562dependency, but rather a control dependency that the CPU may short-circuit
563by attempting to predict the outcome in advance, so that other CPUs see
564the load from b as having happened before the load from a. In such a
565case what's actually required is:
David Howells108b42b2006-03-31 16:00:29 +0100566
Paul E. McKenney2ecf8102013-12-11 13:59:04 -0800567 q = ACCESS_ONCE(a);
Peter Zijlstra18c03c62013-12-11 13:59:06 -0800568 if (q) {
Paul E. McKenney45c8a362013-07-02 15:24:09 -0700569 <read barrier>
Peter Zijlstra18c03c62013-12-11 13:59:06 -0800570 p = ACCESS_ONCE(b);
Paul E. McKenney45c8a362013-07-02 15:24:09 -0700571 }
Peter Zijlstra18c03c62013-12-11 13:59:06 -0800572
573However, stores are not speculated. This means that ordering -is- provided
574in the following example:
575
576 q = ACCESS_ONCE(a);
577 if (ACCESS_ONCE(q)) {
578 ACCESS_ONCE(b) = p;
579 }
580
581Please note that ACCESS_ONCE() is not optional! Without the ACCESS_ONCE(),
582the compiler is within its rights to transform this example:
583
584 q = a;
585 if (q) {
586 b = p; /* BUG: Compiler can reorder!!! */
587 do_something();
588 } else {
589 b = p; /* BUG: Compiler can reorder!!! */
590 do_something_else();
591 }
592
593into this, which of course defeats the ordering:
594
595 b = p;
596 q = a;
597 if (q)
598 do_something();
599 else
600 do_something_else();
601
602Worse yet, if the compiler is able to prove (say) that the value of
603variable 'a' is always non-zero, it would be well within its rights
604to optimize the original example by eliminating the "if" statement
605as follows:
606
607 q = a;
608 b = p; /* BUG: Compiler can reorder!!! */
609 do_something();
610
611The solution is again ACCESS_ONCE(), which preserves the ordering between
612the load from variable 'a' and the store to variable 'b':
613
614 q = ACCESS_ONCE(a);
615 if (q) {
616 ACCESS_ONCE(b) = p;
617 do_something();
618 } else {
619 ACCESS_ONCE(b) = p;
620 do_something_else();
621 }
622
623You could also use barrier() to prevent the compiler from moving
624the stores to variable 'b', but barrier() would not prevent the
625compiler from proving to itself that a==1 always, so ACCESS_ONCE()
626is also needed.
627
628It is important to note that control dependencies absolutely require a
629a conditional. For example, the following "optimized" version of
630the above example breaks ordering:
631
632 q = ACCESS_ONCE(a);
633 ACCESS_ONCE(b) = p; /* BUG: No ordering vs. load from a!!! */
634 if (q) {
635 /* ACCESS_ONCE(b) = p; -- moved up, BUG!!! */
636 do_something();
637 } else {
638 /* ACCESS_ONCE(b) = p; -- moved up, BUG!!! */
639 do_something_else();
640 }
641
642It is of course legal for the prior load to be part of the conditional,
643for example, as follows:
644
645 if (ACCESS_ONCE(a) > 0) {
646 ACCESS_ONCE(b) = q / 2;
647 do_something();
648 } else {
649 ACCESS_ONCE(b) = q / 3;
650 do_something_else();
651 }
652
653This will again ensure that the load from variable 'a' is ordered before the
654stores to variable 'b'.
655
656In addition, you need to be careful what you do with the local variable 'q',
657otherwise the compiler might be able to guess the value and again remove
658the needed conditional. For example:
659
660 q = ACCESS_ONCE(a);
661 if (q % MAX) {
662 ACCESS_ONCE(b) = p;
663 do_something();
664 } else {
665 ACCESS_ONCE(b) = p;
666 do_something_else();
667 }
668
669If MAX is defined to be 1, then the compiler knows that (q % MAX) is
670equal to zero, in which case the compiler is within its rights to
671transform the above code into the following:
672
673 q = ACCESS_ONCE(a);
674 ACCESS_ONCE(b) = p;
675 do_something_else();
676
677This transformation loses the ordering between the load from variable 'a'
678and the store to variable 'b'. If you are relying on this ordering, you
679should do something like the following:
680
681 q = ACCESS_ONCE(a);
682 BUILD_BUG_ON(MAX <= 1); /* Order load from a with store to b. */
683 if (q % MAX) {
684 ACCESS_ONCE(b) = p;
685 do_something();
686 } else {
687 ACCESS_ONCE(b) = p;
688 do_something_else();
689 }
690
691Finally, control dependencies do -not- provide transitivity. This is
692demonstrated by two related examples:
693
694 CPU 0 CPU 1
695 ===================== =====================
696 r1 = ACCESS_ONCE(x); r2 = ACCESS_ONCE(y);
697 if (r1 >= 0) if (r2 >= 0)
698 ACCESS_ONCE(y) = 1; ACCESS_ONCE(x) = 1;
699
700 assert(!(r1 == 1 && r2 == 1));
701
702The above two-CPU example will never trigger the assert(). However,
703if control dependencies guaranteed transitivity (which they do not),
704then adding the following two CPUs would guarantee a related assertion:
705
706 CPU 2 CPU 3
707 ===================== =====================
708 ACCESS_ONCE(x) = 2; ACCESS_ONCE(y) = 2;
709
710 assert(!(r1 == 2 && r2 == 2 && x == 1 && y == 1)); /* FAILS!!! */
711
712But because control dependencies do -not- provide transitivity, the
713above assertion can fail after the combined four-CPU example completes.
714If you need the four-CPU example to provide ordering, you will need
715smp_mb() between the loads and stores in the CPU 0 and CPU 1 code fragments.
716
717In summary:
718
719 (*) Control dependencies can order prior loads against later stores.
720 However, they do -not- guarantee any other sort of ordering:
721 Not prior loads against later loads, nor prior stores against
722 later anything. If you need these other forms of ordering,
723 use smb_rmb(), smp_wmb(), or, in the case of prior stores and
724 later loads, smp_mb().
725
726 (*) Control dependencies require at least one run-time conditional
727 between the prior load and the subsequent store. If the compiler
728 is able to optimize the conditional away, it will have also
729 optimized away the ordering. Careful use of ACCESS_ONCE() can
730 help to preserve the needed conditional.
731
732 (*) Control dependencies require that the compiler avoid reordering the
733 dependency into nonexistence. Careful use of ACCESS_ONCE() or
Paul E. McKenney692118d2013-12-11 13:59:07 -0800734 barrier() can help to preserve your control dependency. Please
735 see the Compiler Barrier section for more information.
Peter Zijlstra18c03c62013-12-11 13:59:06 -0800736
737 (*) Control dependencies do -not- provide transitivity. If you
738 need transitivity, use smp_mb().
David Howells108b42b2006-03-31 16:00:29 +0100739
740
741SMP BARRIER PAIRING
742-------------------
743
744When dealing with CPU-CPU interactions, certain types of memory barrier should
745always be paired. A lack of appropriate pairing is almost certainly an error.
746
747A write barrier should always be paired with a data dependency barrier or read
748barrier, though a general barrier would also be viable. Similarly a read
749barrier or a data dependency barrier should always be paired with at least an
750write barrier, though, again, a general barrier is viable:
751
Paul E. McKenney2ecf8102013-12-11 13:59:04 -0800752 CPU 1 CPU 2
753 =============== ===============
754 ACCESS_ONCE(a) = 1;
David Howells108b42b2006-03-31 16:00:29 +0100755 <write barrier>
Paul E. McKenney2ecf8102013-12-11 13:59:04 -0800756 ACCESS_ONCE(b) = 2; x = ACCESS_ONCE(b);
757 <read barrier>
758 y = ACCESS_ONCE(a);
David Howells108b42b2006-03-31 16:00:29 +0100759
760Or:
761
Paul E. McKenney2ecf8102013-12-11 13:59:04 -0800762 CPU 1 CPU 2
763 =============== ===============================
David Howells108b42b2006-03-31 16:00:29 +0100764 a = 1;
765 <write barrier>
Paul E. McKenney2ecf8102013-12-11 13:59:04 -0800766 ACCESS_ONCE(b) = &a; x = ACCESS_ONCE(b);
767 <data dependency barrier>
768 y = *x;
David Howells108b42b2006-03-31 16:00:29 +0100769
770Basically, the read barrier always has to be there, even though it can be of
771the "weaker" type.
772
David Howells670bd952006-06-10 09:54:12 -0700773[!] Note that the stores before the write barrier would normally be expected to
Jarek Poplawski81fc6322007-05-23 13:58:20 -0700774match the loads after the read barrier or the data dependency barrier, and vice
David Howells670bd952006-06-10 09:54:12 -0700775versa:
776
Paul E. McKenney2ecf8102013-12-11 13:59:04 -0800777 CPU 1 CPU 2
778 =================== ===================
779 ACCESS_ONCE(a) = 1; }---- --->{ v = ACCESS_ONCE(c);
780 ACCESS_ONCE(b) = 2; } \ / { w = ACCESS_ONCE(d);
781 <write barrier> \ <read barrier>
782 ACCESS_ONCE(c) = 3; } / \ { x = ACCESS_ONCE(a);
783 ACCESS_ONCE(d) = 4; }---- --->{ y = ACCESS_ONCE(b);
David Howells670bd952006-06-10 09:54:12 -0700784
David Howells108b42b2006-03-31 16:00:29 +0100785
786EXAMPLES OF MEMORY BARRIER SEQUENCES
787------------------------------------
788
Jarek Poplawski81fc6322007-05-23 13:58:20 -0700789Firstly, write barriers act as partial orderings on store operations.
David Howells108b42b2006-03-31 16:00:29 +0100790Consider the following sequence of events:
791
792 CPU 1
793 =======================
794 STORE A = 1
795 STORE B = 2
796 STORE C = 3
797 <write barrier>
798 STORE D = 4
799 STORE E = 5
800
801This sequence of events is committed to the memory coherence system in an order
802that the rest of the system might perceive as the unordered set of { STORE A,
Adrian Bunk80f72282006-06-30 18:27:16 +0200803STORE B, STORE C } all occurring before the unordered set of { STORE D, STORE E
David Howells108b42b2006-03-31 16:00:29 +0100804}:
805
806 +-------+ : :
807 | | +------+
808 | |------>| C=3 | } /\
Jarek Poplawski81fc6322007-05-23 13:58:20 -0700809 | | : +------+ }----- \ -----> Events perceptible to
810 | | : | A=1 | } \/ the rest of the system
David Howells108b42b2006-03-31 16:00:29 +0100811 | | : +------+ }
812 | CPU 1 | : | B=2 | }
813 | | +------+ }
814 | | wwwwwwwwwwwwwwww } <--- At this point the write barrier
815 | | +------+ } requires all stores prior to the
816 | | : | E=5 | } barrier to be committed before
Jarek Poplawski81fc6322007-05-23 13:58:20 -0700817 | | : +------+ } further stores may take place
David Howells108b42b2006-03-31 16:00:29 +0100818 | |------>| D=4 | }
819 | | +------+
820 +-------+ : :
821 |
David Howells670bd952006-06-10 09:54:12 -0700822 | Sequence in which stores are committed to the
823 | memory system by CPU 1
David Howells108b42b2006-03-31 16:00:29 +0100824 V
825
826
Jarek Poplawski81fc6322007-05-23 13:58:20 -0700827Secondly, data dependency barriers act as partial orderings on data-dependent
David Howells108b42b2006-03-31 16:00:29 +0100828loads. Consider the following sequence of events:
829
830 CPU 1 CPU 2
831 ======================= =======================
David Howellsc14038c2006-04-10 22:54:24 -0700832 { B = 7; X = 9; Y = 8; C = &Y }
David Howells108b42b2006-03-31 16:00:29 +0100833 STORE A = 1
834 STORE B = 2
835 <write barrier>
836 STORE C = &B LOAD X
837 STORE D = 4 LOAD C (gets &B)
838 LOAD *C (reads B)
839
840Without intervention, CPU 2 may perceive the events on CPU 1 in some
841effectively random order, despite the write barrier issued by CPU 1:
842
843 +-------+ : : : :
844 | | +------+ +-------+ | Sequence of update
845 | |------>| B=2 |----- --->| Y->8 | | of perception on
846 | | : +------+ \ +-------+ | CPU 2
847 | CPU 1 | : | A=1 | \ --->| C->&Y | V
848 | | +------+ | +-------+
849 | | wwwwwwwwwwwwwwww | : :
850 | | +------+ | : :
851 | | : | C=&B |--- | : : +-------+
852 | | : +------+ \ | +-------+ | |
853 | |------>| D=4 | ----------->| C->&B |------>| |
854 | | +------+ | +-------+ | |
855 +-------+ : : | : : | |
856 | : : | |
857 | : : | CPU 2 |
858 | +-------+ | |
859 Apparently incorrect ---> | | B->7 |------>| |
860 perception of B (!) | +-------+ | |
861 | : : | |
862 | +-------+ | |
863 The load of X holds ---> \ | X->9 |------>| |
864 up the maintenance \ +-------+ | |
865 of coherence of B ----->| B->2 | +-------+
866 +-------+
867 : :
868
869
870In the above example, CPU 2 perceives that B is 7, despite the load of *C
Paolo Ornati670e9f32006-10-03 22:57:56 +0200871(which would be B) coming after the LOAD of C.
David Howells108b42b2006-03-31 16:00:29 +0100872
873If, however, a data dependency barrier were to be placed between the load of C
David Howellsc14038c2006-04-10 22:54:24 -0700874and the load of *C (ie: B) on CPU 2:
875
876 CPU 1 CPU 2
877 ======================= =======================
878 { B = 7; X = 9; Y = 8; C = &Y }
879 STORE A = 1
880 STORE B = 2
881 <write barrier>
882 STORE C = &B LOAD X
883 STORE D = 4 LOAD C (gets &B)
884 <data dependency barrier>
885 LOAD *C (reads B)
886
887then the following will occur:
David Howells108b42b2006-03-31 16:00:29 +0100888
889 +-------+ : : : :
890 | | +------+ +-------+
891 | |------>| B=2 |----- --->| Y->8 |
892 | | : +------+ \ +-------+
893 | CPU 1 | : | A=1 | \ --->| C->&Y |
894 | | +------+ | +-------+
895 | | wwwwwwwwwwwwwwww | : :
896 | | +------+ | : :
897 | | : | C=&B |--- | : : +-------+
898 | | : +------+ \ | +-------+ | |
899 | |------>| D=4 | ----------->| C->&B |------>| |
900 | | +------+ | +-------+ | |
901 +-------+ : : | : : | |
902 | : : | |
903 | : : | CPU 2 |
904 | +-------+ | |
David Howells670bd952006-06-10 09:54:12 -0700905 | | X->9 |------>| |
906 | +-------+ | |
907 Makes sure all effects ---> \ ddddddddddddddddd | |
908 prior to the store of C \ +-------+ | |
909 are perceptible to ----->| B->2 |------>| |
910 subsequent loads +-------+ | |
David Howells108b42b2006-03-31 16:00:29 +0100911 : : +-------+
912
913
914And thirdly, a read barrier acts as a partial order on loads. Consider the
915following sequence of events:
916
917 CPU 1 CPU 2
918 ======================= =======================
David Howells670bd952006-06-10 09:54:12 -0700919 { A = 0, B = 9 }
David Howells108b42b2006-03-31 16:00:29 +0100920 STORE A=1
David Howells108b42b2006-03-31 16:00:29 +0100921 <write barrier>
David Howells670bd952006-06-10 09:54:12 -0700922 STORE B=2
David Howells108b42b2006-03-31 16:00:29 +0100923 LOAD B
David Howells670bd952006-06-10 09:54:12 -0700924 LOAD A
David Howells108b42b2006-03-31 16:00:29 +0100925
926Without intervention, CPU 2 may then choose to perceive the events on CPU 1 in
927some effectively random order, despite the write barrier issued by CPU 1:
928
David Howells670bd952006-06-10 09:54:12 -0700929 +-------+ : : : :
930 | | +------+ +-------+
931 | |------>| A=1 |------ --->| A->0 |
932 | | +------+ \ +-------+
933 | CPU 1 | wwwwwwwwwwwwwwww \ --->| B->9 |
934 | | +------+ | +-------+
935 | |------>| B=2 |--- | : :
936 | | +------+ \ | : : +-------+
937 +-------+ : : \ | +-------+ | |
938 ---------->| B->2 |------>| |
939 | +-------+ | CPU 2 |
940 | | A->0 |------>| |
941 | +-------+ | |
942 | : : +-------+
943 \ : :
944 \ +-------+
945 ---->| A->1 |
946 +-------+
947 : :
David Howells108b42b2006-03-31 16:00:29 +0100948
949
David Howells6bc39272006-06-25 05:49:22 -0700950If, however, a read barrier were to be placed between the load of B and the
David Howells670bd952006-06-10 09:54:12 -0700951load of A on CPU 2:
David Howells108b42b2006-03-31 16:00:29 +0100952
David Howells670bd952006-06-10 09:54:12 -0700953 CPU 1 CPU 2
954 ======================= =======================
955 { A = 0, B = 9 }
956 STORE A=1
957 <write barrier>
958 STORE B=2
959 LOAD B
960 <read barrier>
961 LOAD A
962
963then the partial ordering imposed by CPU 1 will be perceived correctly by CPU
9642:
965
966 +-------+ : : : :
967 | | +------+ +-------+
968 | |------>| A=1 |------ --->| A->0 |
969 | | +------+ \ +-------+
970 | CPU 1 | wwwwwwwwwwwwwwww \ --->| B->9 |
971 | | +------+ | +-------+
972 | |------>| B=2 |--- | : :
973 | | +------+ \ | : : +-------+
974 +-------+ : : \ | +-------+ | |
975 ---------->| B->2 |------>| |
976 | +-------+ | CPU 2 |
977 | : : | |
978 | : : | |
979 At this point the read ----> \ rrrrrrrrrrrrrrrrr | |
980 barrier causes all effects \ +-------+ | |
981 prior to the storage of B ---->| A->1 |------>| |
982 to be perceptible to CPU 2 +-------+ | |
983 : : +-------+
984
985
986To illustrate this more completely, consider what could happen if the code
987contained a load of A either side of the read barrier:
988
989 CPU 1 CPU 2
990 ======================= =======================
991 { A = 0, B = 9 }
992 STORE A=1
993 <write barrier>
994 STORE B=2
995 LOAD B
996 LOAD A [first load of A]
997 <read barrier>
998 LOAD A [second load of A]
999
1000Even though the two loads of A both occur after the load of B, they may both
1001come up with different values:
1002
1003 +-------+ : : : :
1004 | | +------+ +-------+
1005 | |------>| A=1 |------ --->| A->0 |
1006 | | +------+ \ +-------+
1007 | CPU 1 | wwwwwwwwwwwwwwww \ --->| B->9 |
1008 | | +------+ | +-------+
1009 | |------>| B=2 |--- | : :
1010 | | +------+ \ | : : +-------+
1011 +-------+ : : \ | +-------+ | |
1012 ---------->| B->2 |------>| |
1013 | +-------+ | CPU 2 |
1014 | : : | |
1015 | : : | |
1016 | +-------+ | |
1017 | | A->0 |------>| 1st |
1018 | +-------+ | |
1019 At this point the read ----> \ rrrrrrrrrrrrrrrrr | |
1020 barrier causes all effects \ +-------+ | |
1021 prior to the storage of B ---->| A->1 |------>| 2nd |
1022 to be perceptible to CPU 2 +-------+ | |
1023 : : +-------+
1024
1025
1026But it may be that the update to A from CPU 1 becomes perceptible to CPU 2
1027before the read barrier completes anyway:
1028
1029 +-------+ : : : :
1030 | | +------+ +-------+
1031 | |------>| A=1 |------ --->| A->0 |
1032 | | +------+ \ +-------+
1033 | CPU 1 | wwwwwwwwwwwwwwww \ --->| B->9 |
1034 | | +------+ | +-------+
1035 | |------>| B=2 |--- | : :
1036 | | +------+ \ | : : +-------+
1037 +-------+ : : \ | +-------+ | |
1038 ---------->| B->2 |------>| |
1039 | +-------+ | CPU 2 |
1040 | : : | |
1041 \ : : | |
1042 \ +-------+ | |
1043 ---->| A->1 |------>| 1st |
1044 +-------+ | |
1045 rrrrrrrrrrrrrrrrr | |
1046 +-------+ | |
1047 | A->1 |------>| 2nd |
1048 +-------+ | |
1049 : : +-------+
1050
1051
1052The guarantee is that the second load will always come up with A == 1 if the
1053load of B came up with B == 2. No such guarantee exists for the first load of
1054A; that may come up with either A == 0 or A == 1.
1055
1056
1057READ MEMORY BARRIERS VS LOAD SPECULATION
1058----------------------------------------
1059
1060Many CPUs speculate with loads: that is they see that they will need to load an
1061item from memory, and they find a time where they're not using the bus for any
1062other loads, and so do the load in advance - even though they haven't actually
1063got to that point in the instruction execution flow yet. This permits the
1064actual load instruction to potentially complete immediately because the CPU
1065already has the value to hand.
1066
1067It may turn out that the CPU didn't actually need the value - perhaps because a
1068branch circumvented the load - in which case it can discard the value or just
1069cache it for later use.
1070
1071Consider:
1072
Ingo Molnare0edc782013-11-22 11:24:53 +01001073 CPU 1 CPU 2
David Howells670bd952006-06-10 09:54:12 -07001074 ======================= =======================
Ingo Molnare0edc782013-11-22 11:24:53 +01001075 LOAD B
1076 DIVIDE } Divide instructions generally
1077 DIVIDE } take a long time to perform
1078 LOAD A
David Howells670bd952006-06-10 09:54:12 -07001079
1080Which might appear as this:
1081
1082 : : +-------+
1083 +-------+ | |
1084 --->| B->2 |------>| |
1085 +-------+ | CPU 2 |
1086 : :DIVIDE | |
1087 +-------+ | |
1088 The CPU being busy doing a ---> --->| A->0 |~~~~ | |
1089 division speculates on the +-------+ ~ | |
1090 LOAD of A : : ~ | |
1091 : :DIVIDE | |
1092 : : ~ | |
1093 Once the divisions are complete --> : : ~-->| |
1094 the CPU can then perform the : : | |
1095 LOAD with immediate effect : : +-------+
1096
1097
1098Placing a read barrier or a data dependency barrier just before the second
1099load:
1100
Ingo Molnare0edc782013-11-22 11:24:53 +01001101 CPU 1 CPU 2
David Howells670bd952006-06-10 09:54:12 -07001102 ======================= =======================
Ingo Molnare0edc782013-11-22 11:24:53 +01001103 LOAD B
1104 DIVIDE
1105 DIVIDE
David Howells670bd952006-06-10 09:54:12 -07001106 <read barrier>
Ingo Molnare0edc782013-11-22 11:24:53 +01001107 LOAD A
David Howells670bd952006-06-10 09:54:12 -07001108
1109will force any value speculatively obtained to be reconsidered to an extent
1110dependent on the type of barrier used. If there was no change made to the
1111speculated memory location, then the speculated value will just be used:
1112
1113 : : +-------+
1114 +-------+ | |
1115 --->| B->2 |------>| |
1116 +-------+ | CPU 2 |
1117 : :DIVIDE | |
1118 +-------+ | |
1119 The CPU being busy doing a ---> --->| A->0 |~~~~ | |
1120 division speculates on the +-------+ ~ | |
1121 LOAD of A : : ~ | |
1122 : :DIVIDE | |
1123 : : ~ | |
1124 : : ~ | |
1125 rrrrrrrrrrrrrrrr~ | |
1126 : : ~ | |
1127 : : ~-->| |
1128 : : | |
1129 : : +-------+
1130
1131
1132but if there was an update or an invalidation from another CPU pending, then
1133the speculation will be cancelled and the value reloaded:
1134
1135 : : +-------+
1136 +-------+ | |
1137 --->| B->2 |------>| |
1138 +-------+ | CPU 2 |
1139 : :DIVIDE | |
1140 +-------+ | |
1141 The CPU being busy doing a ---> --->| A->0 |~~~~ | |
1142 division speculates on the +-------+ ~ | |
1143 LOAD of A : : ~ | |
1144 : :DIVIDE | |
1145 : : ~ | |
1146 : : ~ | |
1147 rrrrrrrrrrrrrrrrr | |
1148 +-------+ | |
1149 The speculation is discarded ---> --->| A->1 |------>| |
1150 and an updated value is +-------+ | |
1151 retrieved : : +-------+
David Howells108b42b2006-03-31 16:00:29 +01001152
1153
Paul E. McKenney241e6662011-02-10 16:54:50 -08001154TRANSITIVITY
1155------------
1156
1157Transitivity is a deeply intuitive notion about ordering that is not
1158always provided by real computer systems. The following example
1159demonstrates transitivity (also called "cumulativity"):
1160
1161 CPU 1 CPU 2 CPU 3
1162 ======================= ======================= =======================
1163 { X = 0, Y = 0 }
1164 STORE X=1 LOAD X STORE Y=1
1165 <general barrier> <general barrier>
1166 LOAD Y LOAD X
1167
1168Suppose that CPU 2's load from X returns 1 and its load from Y returns 0.
1169This indicates that CPU 2's load from X in some sense follows CPU 1's
1170store to X and that CPU 2's load from Y in some sense preceded CPU 3's
1171store to Y. The question is then "Can CPU 3's load from X return 0?"
1172
1173Because CPU 2's load from X in some sense came after CPU 1's store, it
1174is natural to expect that CPU 3's load from X must therefore return 1.
1175This expectation is an example of transitivity: if a load executing on
1176CPU A follows a load from the same variable executing on CPU B, then
1177CPU A's load must either return the same value that CPU B's load did,
1178or must return some later value.
1179
1180In the Linux kernel, use of general memory barriers guarantees
1181transitivity. Therefore, in the above example, if CPU 2's load from X
1182returns 1 and its load from Y returns 0, then CPU 3's load from X must
1183also return 1.
1184
1185However, transitivity is -not- guaranteed for read or write barriers.
1186For example, suppose that CPU 2's general barrier in the above example
1187is changed to a read barrier as shown below:
1188
1189 CPU 1 CPU 2 CPU 3
1190 ======================= ======================= =======================
1191 { X = 0, Y = 0 }
1192 STORE X=1 LOAD X STORE Y=1
1193 <read barrier> <general barrier>
1194 LOAD Y LOAD X
1195
1196This substitution destroys transitivity: in this example, it is perfectly
1197legal for CPU 2's load from X to return 1, its load from Y to return 0,
1198and CPU 3's load from X to return 0.
1199
1200The key point is that although CPU 2's read barrier orders its pair
1201of loads, it does not guarantee to order CPU 1's store. Therefore, if
1202this example runs on a system where CPUs 1 and 2 share a store buffer
1203or a level of cache, CPU 2 might have early access to CPU 1's writes.
1204General barriers are therefore required to ensure that all CPUs agree
1205on the combined order of CPU 1's and CPU 2's accesses.
1206
1207To reiterate, if your code requires transitivity, use general barriers
1208throughout.
1209
1210
David Howells108b42b2006-03-31 16:00:29 +01001211========================
1212EXPLICIT KERNEL BARRIERS
1213========================
1214
1215The Linux kernel has a variety of different barriers that act at different
1216levels:
1217
1218 (*) Compiler barrier.
1219
1220 (*) CPU memory barriers.
1221
1222 (*) MMIO write barrier.
1223
1224
1225COMPILER BARRIER
1226----------------
1227
1228The Linux kernel has an explicit compiler barrier function that prevents the
1229compiler from moving the memory accesses either side of it to the other side:
1230
1231 barrier();
1232
Peter Zijlstra18c03c62013-12-11 13:59:06 -08001233This is a general barrier -- there are no read-read or write-write variants
Paul E. McKenney692118d2013-12-11 13:59:07 -08001234of barrier(). However, ACCESS_ONCE() can be thought of as a weak form
Peter Zijlstra18c03c62013-12-11 13:59:06 -08001235for barrier() that affects only the specific accesses flagged by the
1236ACCESS_ONCE().
David Howells108b42b2006-03-31 16:00:29 +01001237
Paul E. McKenney692118d2013-12-11 13:59:07 -08001238The barrier() function has the following effects:
1239
1240 (*) Prevents the compiler from reordering accesses following the
1241 barrier() to precede any accesses preceding the barrier().
1242 One example use for this property is to ease communication between
1243 interrupt-handler code and the code that was interrupted.
1244
1245 (*) Within a loop, forces the compiler to load the variables used
1246 in that loop's conditional on each pass through that loop.
1247
1248The ACCESS_ONCE() function can prevent any number of optimizations that,
1249while perfectly safe in single-threaded code, can be fatal in concurrent
1250code. Here are some examples of these sorts of optimizations:
1251
1252 (*) The compiler is within its rights to merge successive loads from
1253 the same variable. Such merging can cause the compiler to "optimize"
1254 the following code:
1255
1256 while (tmp = a)
1257 do_something_with(tmp);
1258
1259 into the following code, which, although in some sense legitimate
1260 for single-threaded code, is almost certainly not what the developer
1261 intended:
1262
1263 if (tmp = a)
1264 for (;;)
1265 do_something_with(tmp);
1266
1267 Use ACCESS_ONCE() to prevent the compiler from doing this to you:
1268
1269 while (tmp = ACCESS_ONCE(a))
1270 do_something_with(tmp);
1271
1272 (*) The compiler is within its rights to reload a variable, for example,
1273 in cases where high register pressure prevents the compiler from
1274 keeping all data of interest in registers. The compiler might
1275 therefore optimize the variable 'tmp' out of our previous example:
1276
1277 while (tmp = a)
1278 do_something_with(tmp);
1279
1280 This could result in the following code, which is perfectly safe in
1281 single-threaded code, but can be fatal in concurrent code:
1282
1283 while (a)
1284 do_something_with(a);
1285
1286 For example, the optimized version of this code could result in
1287 passing a zero to do_something_with() in the case where the variable
1288 a was modified by some other CPU between the "while" statement and
1289 the call to do_something_with().
1290
1291 Again, use ACCESS_ONCE() to prevent the compiler from doing this:
1292
1293 while (tmp = ACCESS_ONCE(a))
1294 do_something_with(tmp);
1295
1296 Note that if the compiler runs short of registers, it might save
1297 tmp onto the stack. The overhead of this saving and later restoring
1298 is why compilers reload variables. Doing so is perfectly safe for
1299 single-threaded code, so you need to tell the compiler about cases
1300 where it is not safe.
1301
1302 (*) The compiler is within its rights to omit a load entirely if it knows
1303 what the value will be. For example, if the compiler can prove that
1304 the value of variable 'a' is always zero, it can optimize this code:
1305
1306 while (tmp = a)
1307 do_something_with(tmp);
1308
1309 Into this:
1310
1311 do { } while (0);
1312
1313 This transformation is a win for single-threaded code because it gets
1314 rid of a load and a branch. The problem is that the compiler will
1315 carry out its proof assuming that the current CPU is the only one
1316 updating variable 'a'. If variable 'a' is shared, then the compiler's
1317 proof will be erroneous. Use ACCESS_ONCE() to tell the compiler
1318 that it doesn't know as much as it thinks it does:
1319
1320 while (tmp = ACCESS_ONCE(a))
1321 do_something_with(tmp);
1322
1323 But please note that the compiler is also closely watching what you
1324 do with the value after the ACCESS_ONCE(). For example, suppose you
1325 do the following and MAX is a preprocessor macro with the value 1:
1326
1327 while ((tmp = ACCESS_ONCE(a)) % MAX)
1328 do_something_with(tmp);
1329
1330 Then the compiler knows that the result of the "%" operator applied
1331 to MAX will always be zero, again allowing the compiler to optimize
1332 the code into near-nonexistence. (It will still load from the
1333 variable 'a'.)
1334
1335 (*) Similarly, the compiler is within its rights to omit a store entirely
1336 if it knows that the variable already has the value being stored.
1337 Again, the compiler assumes that the current CPU is the only one
1338 storing into the variable, which can cause the compiler to do the
1339 wrong thing for shared variables. For example, suppose you have
1340 the following:
1341
1342 a = 0;
1343 /* Code that does not store to variable a. */
1344 a = 0;
1345
1346 The compiler sees that the value of variable 'a' is already zero, so
1347 it might well omit the second store. This would come as a fatal
1348 surprise if some other CPU might have stored to variable 'a' in the
1349 meantime.
1350
1351 Use ACCESS_ONCE() to prevent the compiler from making this sort of
1352 wrong guess:
1353
1354 ACCESS_ONCE(a) = 0;
1355 /* Code that does not store to variable a. */
1356 ACCESS_ONCE(a) = 0;
1357
1358 (*) The compiler is within its rights to reorder memory accesses unless
1359 you tell it not to. For example, consider the following interaction
1360 between process-level code and an interrupt handler:
1361
1362 void process_level(void)
1363 {
1364 msg = get_message();
1365 flag = true;
1366 }
1367
1368 void interrupt_handler(void)
1369 {
1370 if (flag)
1371 process_message(msg);
1372 }
1373
1374 There is nothing to prevent the the compiler from transforming
1375 process_level() to the following, in fact, this might well be a
1376 win for single-threaded code:
1377
1378 void process_level(void)
1379 {
1380 flag = true;
1381 msg = get_message();
1382 }
1383
1384 If the interrupt occurs between these two statement, then
1385 interrupt_handler() might be passed a garbled msg. Use ACCESS_ONCE()
1386 to prevent this as follows:
1387
1388 void process_level(void)
1389 {
1390 ACCESS_ONCE(msg) = get_message();
1391 ACCESS_ONCE(flag) = true;
1392 }
1393
1394 void interrupt_handler(void)
1395 {
1396 if (ACCESS_ONCE(flag))
1397 process_message(ACCESS_ONCE(msg));
1398 }
1399
1400 Note that the ACCESS_ONCE() wrappers in interrupt_handler()
1401 are needed if this interrupt handler can itself be interrupted
1402 by something that also accesses 'flag' and 'msg', for example,
1403 a nested interrupt or an NMI. Otherwise, ACCESS_ONCE() is not
1404 needed in interrupt_handler() other than for documentation purposes.
1405 (Note also that nested interrupts do not typically occur in modern
1406 Linux kernels, in fact, if an interrupt handler returns with
1407 interrupts enabled, you will get a WARN_ONCE() splat.)
1408
1409 You should assume that the compiler can move ACCESS_ONCE() past
1410 code not containing ACCESS_ONCE(), barrier(), or similar primitives.
1411
1412 This effect could also be achieved using barrier(), but ACCESS_ONCE()
1413 is more selective: With ACCESS_ONCE(), the compiler need only forget
1414 the contents of the indicated memory locations, while with barrier()
1415 the compiler must discard the value of all memory locations that
1416 it has currented cached in any machine registers. Of course,
1417 the compiler must also respect the order in which the ACCESS_ONCE()s
1418 occur, though the CPU of course need not do so.
1419
1420 (*) The compiler is within its rights to invent stores to a variable,
1421 as in the following example:
1422
1423 if (a)
1424 b = a;
1425 else
1426 b = 42;
1427
1428 The compiler might save a branch by optimizing this as follows:
1429
1430 b = 42;
1431 if (a)
1432 b = a;
1433
1434 In single-threaded code, this is not only safe, but also saves
1435 a branch. Unfortunately, in concurrent code, this optimization
1436 could cause some other CPU to see a spurious value of 42 -- even
1437 if variable 'a' was never zero -- when loading variable 'b'.
1438 Use ACCESS_ONCE() to prevent this as follows:
1439
1440 if (a)
1441 ACCESS_ONCE(b) = a;
1442 else
1443 ACCESS_ONCE(b) = 42;
1444
1445 The compiler can also invent loads. These are usually less
1446 damaging, but they can result in cache-line bouncing and thus in
1447 poor performance and scalability. Use ACCESS_ONCE() to prevent
1448 invented loads.
1449
1450 (*) For aligned memory locations whose size allows them to be accessed
1451 with a single memory-reference instruction, prevents "load tearing"
1452 and "store tearing," in which a single large access is replaced by
1453 multiple smaller accesses. For example, given an architecture having
1454 16-bit store instructions with 7-bit immediate fields, the compiler
1455 might be tempted to use two 16-bit store-immediate instructions to
1456 implement the following 32-bit store:
1457
1458 p = 0x00010002;
1459
1460 Please note that GCC really does use this sort of optimization,
1461 which is not surprising given that it would likely take more
1462 than two instructions to build the constant and then store it.
1463 This optimization can therefore be a win in single-threaded code.
1464 In fact, a recent bug (since fixed) caused GCC to incorrectly use
1465 this optimization in a volatile store. In the absence of such bugs,
1466 use of ACCESS_ONCE() prevents store tearing in the following example:
1467
1468 ACCESS_ONCE(p) = 0x00010002;
1469
1470 Use of packed structures can also result in load and store tearing,
1471 as in this example:
1472
1473 struct __attribute__((__packed__)) foo {
1474 short a;
1475 int b;
1476 short c;
1477 };
1478 struct foo foo1, foo2;
1479 ...
1480
1481 foo2.a = foo1.a;
1482 foo2.b = foo1.b;
1483 foo2.c = foo1.c;
1484
1485 Because there are no ACCESS_ONCE() wrappers and no volatile markings,
1486 the compiler would be well within its rights to implement these three
1487 assignment statements as a pair of 32-bit loads followed by a pair
1488 of 32-bit stores. This would result in load tearing on 'foo1.b'
1489 and store tearing on 'foo2.b'. ACCESS_ONCE() again prevents tearing
1490 in this example:
1491
1492 foo2.a = foo1.a;
1493 ACCESS_ONCE(foo2.b) = ACCESS_ONCE(foo1.b);
1494 foo2.c = foo1.c;
1495
1496All that aside, it is never necessary to use ACCESS_ONCE() on a variable
1497that has been marked volatile. For example, because 'jiffies' is marked
1498volatile, it is never necessary to say ACCESS_ONCE(jiffies). The reason
1499for this is that ACCESS_ONCE() is implemented as a volatile cast, which
1500has no effect when its argument is already marked volatile.
1501
1502Please note that these compiler barriers have no direct effect on the CPU,
1503which may then reorder things however it wishes.
David Howells108b42b2006-03-31 16:00:29 +01001504
1505
1506CPU MEMORY BARRIERS
1507-------------------
1508
1509The Linux kernel has eight basic CPU memory barriers:
1510
1511 TYPE MANDATORY SMP CONDITIONAL
1512 =============== ======================= ===========================
1513 GENERAL mb() smp_mb()
1514 WRITE wmb() smp_wmb()
1515 READ rmb() smp_rmb()
1516 DATA DEPENDENCY read_barrier_depends() smp_read_barrier_depends()
1517
1518
Nick Piggin73f10282008-05-14 06:35:11 +02001519All memory barriers except the data dependency barriers imply a compiler
1520barrier. Data dependencies do not impose any additional compiler ordering.
1521
1522Aside: In the case of data dependencies, the compiler would be expected to
1523issue the loads in the correct order (eg. `a[b]` would have to load the value
1524of b before loading a[b]), however there is no guarantee in the C specification
1525that the compiler may not speculate the value of b (eg. is equal to 1) and load
1526a before b (eg. tmp = a[1]; if (b != 1) tmp = a[b]; ). There is also the
1527problem of a compiler reloading b after having loaded a[b], thus having a newer
1528copy of b than a[b]. A consensus has not yet been reached about these problems,
1529however the ACCESS_ONCE macro is a good place to start looking.
David Howells108b42b2006-03-31 16:00:29 +01001530
1531SMP memory barriers are reduced to compiler barriers on uniprocessor compiled
Jarek Poplawski81fc6322007-05-23 13:58:20 -07001532systems because it is assumed that a CPU will appear to be self-consistent,
David Howells108b42b2006-03-31 16:00:29 +01001533and will order overlapping accesses correctly with respect to itself.
1534
1535[!] Note that SMP memory barriers _must_ be used to control the ordering of
1536references to shared memory on SMP systems, though the use of locking instead
1537is sufficient.
1538
1539Mandatory barriers should not be used to control SMP effects, since mandatory
1540barriers unnecessarily impose overhead on UP systems. They may, however, be
1541used to control MMIO effects on accesses through relaxed memory I/O windows.
1542These are required even on non-SMP systems as they affect the order in which
1543memory operations appear to a device by prohibiting both the compiler and the
1544CPU from reordering them.
1545
1546
1547There are some more advanced barrier functions:
1548
1549 (*) set_mb(var, value)
David Howells108b42b2006-03-31 16:00:29 +01001550
Oleg Nesterov75b2bd52006-11-08 17:44:38 -08001551 This assigns the value to the variable and then inserts a full memory
Steven Rostedtf92213b2006-07-14 16:05:01 -04001552 barrier after it, depending on the function. It isn't guaranteed to
David Howells108b42b2006-03-31 16:00:29 +01001553 insert anything more than a compiler barrier in a UP compilation.
1554
1555
1556 (*) smp_mb__before_atomic_dec();
1557 (*) smp_mb__after_atomic_dec();
1558 (*) smp_mb__before_atomic_inc();
1559 (*) smp_mb__after_atomic_inc();
1560
1561 These are for use with atomic add, subtract, increment and decrement
David Howellsdbc87002006-04-10 22:54:23 -07001562 functions that don't return a value, especially when used for reference
1563 counting. These functions do not imply memory barriers.
David Howells108b42b2006-03-31 16:00:29 +01001564
1565 As an example, consider a piece of code that marks an object as being dead
1566 and then decrements the object's reference count:
1567
1568 obj->dead = 1;
1569 smp_mb__before_atomic_dec();
1570 atomic_dec(&obj->ref_count);
1571
1572 This makes sure that the death mark on the object is perceived to be set
1573 *before* the reference counter is decremented.
1574
1575 See Documentation/atomic_ops.txt for more information. See the "Atomic
1576 operations" subsection for information on where to use these.
1577
1578
1579 (*) smp_mb__before_clear_bit(void);
1580 (*) smp_mb__after_clear_bit(void);
1581
1582 These are for use similar to the atomic inc/dec barriers. These are
1583 typically used for bitwise unlocking operations, so care must be taken as
1584 there are no implicit memory barriers here either.
1585
1586 Consider implementing an unlock operation of some nature by clearing a
1587 locking bit. The clear_bit() would then need to be barriered like this:
1588
1589 smp_mb__before_clear_bit();
1590 clear_bit( ... );
1591
1592 This prevents memory operations before the clear leaking to after it. See
Peter Zijlstra2e4f5382013-11-06 14:57:36 +01001593 the subsection on "Locking Functions" with reference to RELEASE operation
David Howells108b42b2006-03-31 16:00:29 +01001594 implications.
1595
1596 See Documentation/atomic_ops.txt for more information. See the "Atomic
1597 operations" subsection for information on where to use these.
1598
1599
1600MMIO WRITE BARRIER
1601------------------
1602
1603The Linux kernel also has a special barrier for use with memory-mapped I/O
1604writes:
1605
1606 mmiowb();
1607
1608This is a variation on the mandatory write barrier that causes writes to weakly
1609ordered I/O regions to be partially ordered. Its effects may go beyond the
1610CPU->Hardware interface and actually affect the hardware at some level.
1611
1612See the subsection "Locks vs I/O accesses" for more information.
1613
1614
1615===============================
1616IMPLICIT KERNEL MEMORY BARRIERS
1617===============================
1618
1619Some of the other functions in the linux kernel imply memory barriers, amongst
David Howells670bd952006-06-10 09:54:12 -07001620which are locking and scheduling functions.
David Howells108b42b2006-03-31 16:00:29 +01001621
1622This specification is a _minimum_ guarantee; any particular architecture may
1623provide more substantial guarantees, but these may not be relied upon outside
1624of arch specific code.
1625
1626
Peter Zijlstra2e4f5382013-11-06 14:57:36 +01001627ACQUIRING FUNCTIONS
1628-------------------
David Howells108b42b2006-03-31 16:00:29 +01001629
1630The Linux kernel has a number of locking constructs:
1631
1632 (*) spin locks
1633 (*) R/W spin locks
1634 (*) mutexes
1635 (*) semaphores
1636 (*) R/W semaphores
1637 (*) RCU
1638
Peter Zijlstra2e4f5382013-11-06 14:57:36 +01001639In all cases there are variants on "ACQUIRE" operations and "RELEASE" operations
David Howells108b42b2006-03-31 16:00:29 +01001640for each construct. These operations all imply certain barriers:
1641
Peter Zijlstra2e4f5382013-11-06 14:57:36 +01001642 (1) ACQUIRE operation implication:
David Howells108b42b2006-03-31 16:00:29 +01001643
Peter Zijlstra2e4f5382013-11-06 14:57:36 +01001644 Memory operations issued after the ACQUIRE will be completed after the
1645 ACQUIRE operation has completed.
David Howells108b42b2006-03-31 16:00:29 +01001646
Peter Zijlstra2e4f5382013-11-06 14:57:36 +01001647 Memory operations issued before the ACQUIRE may be completed after the
1648 ACQUIRE operation has completed. An smp_mb__before_spinlock(), combined
1649 with a following ACQUIRE, orders prior loads against subsequent stores and
1650 stores and prior stores against subsequent stores. Note that this is
1651 weaker than smp_mb()! The smp_mb__before_spinlock() primitive is free on
1652 many architectures.
David Howells108b42b2006-03-31 16:00:29 +01001653
Peter Zijlstra2e4f5382013-11-06 14:57:36 +01001654 (2) RELEASE operation implication:
David Howells108b42b2006-03-31 16:00:29 +01001655
Peter Zijlstra2e4f5382013-11-06 14:57:36 +01001656 Memory operations issued before the RELEASE will be completed before the
1657 RELEASE operation has completed.
David Howells108b42b2006-03-31 16:00:29 +01001658
Peter Zijlstra2e4f5382013-11-06 14:57:36 +01001659 Memory operations issued after the RELEASE may be completed before the
1660 RELEASE operation has completed.
David Howells108b42b2006-03-31 16:00:29 +01001661
Peter Zijlstra2e4f5382013-11-06 14:57:36 +01001662 (3) ACQUIRE vs ACQUIRE implication:
David Howells108b42b2006-03-31 16:00:29 +01001663
Peter Zijlstra2e4f5382013-11-06 14:57:36 +01001664 All ACQUIRE operations issued before another ACQUIRE operation will be
1665 completed before that ACQUIRE operation.
David Howells108b42b2006-03-31 16:00:29 +01001666
Peter Zijlstra2e4f5382013-11-06 14:57:36 +01001667 (4) ACQUIRE vs RELEASE implication:
David Howells108b42b2006-03-31 16:00:29 +01001668
Peter Zijlstra2e4f5382013-11-06 14:57:36 +01001669 All ACQUIRE operations issued before a RELEASE operation will be
1670 completed before the RELEASE operation.
David Howells108b42b2006-03-31 16:00:29 +01001671
Peter Zijlstra2e4f5382013-11-06 14:57:36 +01001672 (5) Failed conditional ACQUIRE implication:
David Howells108b42b2006-03-31 16:00:29 +01001673
Peter Zijlstra2e4f5382013-11-06 14:57:36 +01001674 Certain locking variants of the ACQUIRE operation may fail, either due to
1675 being unable to get the lock immediately, or due to receiving an unblocked
David Howells108b42b2006-03-31 16:00:29 +01001676 signal whilst asleep waiting for the lock to become available. Failed
1677 locks do not imply any sort of barrier.
1678
Peter Zijlstra2e4f5382013-11-06 14:57:36 +01001679[!] Note: one of the consequences of lock ACQUIREs and RELEASEs being only
1680one-way barriers is that the effects of instructions outside of a critical
1681section may seep into the inside of the critical section.
David Howells108b42b2006-03-31 16:00:29 +01001682
Peter Zijlstra2e4f5382013-11-06 14:57:36 +01001683An ACQUIRE followed by a RELEASE may not be assumed to be full memory barrier
1684because it is possible for an access preceding the ACQUIRE to happen after the
1685ACQUIRE, and an access following the RELEASE to happen before the RELEASE, and
1686the two accesses can themselves then cross:
David Howells670bd952006-06-10 09:54:12 -07001687
1688 *A = a;
Peter Zijlstra2e4f5382013-11-06 14:57:36 +01001689 ACQUIRE M
1690 RELEASE M
David Howells670bd952006-06-10 09:54:12 -07001691 *B = b;
1692
1693may occur as:
1694
Peter Zijlstra2e4f5382013-11-06 14:57:36 +01001695 ACQUIRE M, STORE *B, STORE *A, RELEASE M
Paul E. McKenney17eb88e2013-12-11 13:59:09 -08001696
Peter Zijlstra2e4f5382013-11-06 14:57:36 +01001697This same reordering can of course occur if the lock's ACQUIRE and RELEASE are
1698to the same lock variable, but only from the perspective of another CPU not
1699holding that lock.
Paul E. McKenney17eb88e2013-12-11 13:59:09 -08001700
Peter Zijlstra2e4f5382013-11-06 14:57:36 +01001701In short, a RELEASE followed by an ACQUIRE may -not- be assumed to be a full
1702memory barrier because it is possible for a preceding RELEASE to pass a
1703later ACQUIRE from the viewpoint of the CPU, but not from the viewpoint
Paul E. McKenney17eb88e2013-12-11 13:59:09 -08001704of the compiler. Note that deadlocks cannot be introduced by this
Peter Zijlstra2e4f5382013-11-06 14:57:36 +01001705interchange because if such a deadlock threatened, the RELEASE would
Paul E. McKenney17eb88e2013-12-11 13:59:09 -08001706simply complete.
1707
Peter Zijlstra2e4f5382013-11-06 14:57:36 +01001708If it is necessary for a RELEASE-ACQUIRE pair to produce a full barrier, the
1709ACQUIRE can be followed by an smp_mb__after_unlock_lock() invocation. This
1710will produce a full barrier if either (a) the RELEASE and the ACQUIRE are
1711executed by the same CPU or task, or (b) the RELEASE and ACQUIRE act on the
1712same variable. The smp_mb__after_unlock_lock() primitive is free on many
1713architectures. Without smp_mb__after_unlock_lock(), the critical sections
1714corresponding to the RELEASE and the ACQUIRE can cross:
Paul E. McKenney17eb88e2013-12-11 13:59:09 -08001715
1716 *A = a;
Peter Zijlstra2e4f5382013-11-06 14:57:36 +01001717 RELEASE M
1718 ACQUIRE N
Paul E. McKenney17eb88e2013-12-11 13:59:09 -08001719 *B = b;
1720
1721could occur as:
1722
Peter Zijlstra2e4f5382013-11-06 14:57:36 +01001723 ACQUIRE N, STORE *B, STORE *A, RELEASE M
Paul E. McKenney17eb88e2013-12-11 13:59:09 -08001724
1725With smp_mb__after_unlock_lock(), they cannot, so that:
1726
1727 *A = a;
Peter Zijlstra2e4f5382013-11-06 14:57:36 +01001728 RELEASE M
1729 ACQUIRE N
Paul E. McKenney17eb88e2013-12-11 13:59:09 -08001730 smp_mb__after_unlock_lock();
1731 *B = b;
1732
1733will always occur as either of the following:
1734
Peter Zijlstra2e4f5382013-11-06 14:57:36 +01001735 STORE *A, RELEASE, ACQUIRE, STORE *B
1736 STORE *A, ACQUIRE, RELEASE, STORE *B
Paul E. McKenney17eb88e2013-12-11 13:59:09 -08001737
Peter Zijlstra2e4f5382013-11-06 14:57:36 +01001738If the RELEASE and ACQUIRE were instead both operating on the same lock
Paul E. McKenney17eb88e2013-12-11 13:59:09 -08001739variable, only the first of these two alternatives can occur.
David Howells670bd952006-06-10 09:54:12 -07001740
David Howells108b42b2006-03-31 16:00:29 +01001741Locks and semaphores may not provide any guarantee of ordering on UP compiled
1742systems, and so cannot be counted on in such a situation to actually achieve
1743anything at all - especially with respect to I/O accesses - unless combined
1744with interrupt disabling operations.
1745
1746See also the section on "Inter-CPU locking barrier effects".
1747
1748
1749As an example, consider the following:
1750
1751 *A = a;
1752 *B = b;
Peter Zijlstra2e4f5382013-11-06 14:57:36 +01001753 ACQUIRE
David Howells108b42b2006-03-31 16:00:29 +01001754 *C = c;
1755 *D = d;
Peter Zijlstra2e4f5382013-11-06 14:57:36 +01001756 RELEASE
David Howells108b42b2006-03-31 16:00:29 +01001757 *E = e;
1758 *F = f;
1759
1760The following sequence of events is acceptable:
1761
Peter Zijlstra2e4f5382013-11-06 14:57:36 +01001762 ACQUIRE, {*F,*A}, *E, {*C,*D}, *B, RELEASE
David Howells108b42b2006-03-31 16:00:29 +01001763
1764 [+] Note that {*F,*A} indicates a combined access.
1765
1766But none of the following are:
1767
Peter Zijlstra2e4f5382013-11-06 14:57:36 +01001768 {*F,*A}, *B, ACQUIRE, *C, *D, RELEASE, *E
1769 *A, *B, *C, ACQUIRE, *D, RELEASE, *E, *F
1770 *A, *B, ACQUIRE, *C, RELEASE, *D, *E, *F
1771 *B, ACQUIRE, *C, *D, RELEASE, {*F,*A}, *E
David Howells108b42b2006-03-31 16:00:29 +01001772
1773
1774
1775INTERRUPT DISABLING FUNCTIONS
1776-----------------------------
1777
Peter Zijlstra2e4f5382013-11-06 14:57:36 +01001778Functions that disable interrupts (ACQUIRE equivalent) and enable interrupts
1779(RELEASE equivalent) will act as compiler barriers only. So if memory or I/O
David Howells108b42b2006-03-31 16:00:29 +01001780barriers are required in such a situation, they must be provided from some
1781other means.
1782
1783
David Howells50fa6102009-04-28 15:01:38 +01001784SLEEP AND WAKE-UP FUNCTIONS
1785---------------------------
1786
1787Sleeping and waking on an event flagged in global data can be viewed as an
1788interaction between two pieces of data: the task state of the task waiting for
1789the event and the global data used to indicate the event. To make sure that
1790these appear to happen in the right order, the primitives to begin the process
1791of going to sleep, and the primitives to initiate a wake up imply certain
1792barriers.
1793
1794Firstly, the sleeper normally follows something like this sequence of events:
1795
1796 for (;;) {
1797 set_current_state(TASK_UNINTERRUPTIBLE);
1798 if (event_indicated)
1799 break;
1800 schedule();
1801 }
1802
1803A general memory barrier is interpolated automatically by set_current_state()
1804after it has altered the task state:
1805
1806 CPU 1
1807 ===============================
1808 set_current_state();
1809 set_mb();
1810 STORE current->state
1811 <general barrier>
1812 LOAD event_indicated
1813
1814set_current_state() may be wrapped by:
1815
1816 prepare_to_wait();
1817 prepare_to_wait_exclusive();
1818
1819which therefore also imply a general memory barrier after setting the state.
1820The whole sequence above is available in various canned forms, all of which
1821interpolate the memory barrier in the right place:
1822
1823 wait_event();
1824 wait_event_interruptible();
1825 wait_event_interruptible_exclusive();
1826 wait_event_interruptible_timeout();
1827 wait_event_killable();
1828 wait_event_timeout();
1829 wait_on_bit();
1830 wait_on_bit_lock();
1831
1832
1833Secondly, code that performs a wake up normally follows something like this:
1834
1835 event_indicated = 1;
1836 wake_up(&event_wait_queue);
1837
1838or:
1839
1840 event_indicated = 1;
1841 wake_up_process(event_daemon);
1842
1843A write memory barrier is implied by wake_up() and co. if and only if they wake
1844something up. The barrier occurs before the task state is cleared, and so sits
1845between the STORE to indicate the event and the STORE to set TASK_RUNNING:
1846
1847 CPU 1 CPU 2
1848 =============================== ===============================
1849 set_current_state(); STORE event_indicated
1850 set_mb(); wake_up();
1851 STORE current->state <write barrier>
1852 <general barrier> STORE current->state
1853 LOAD event_indicated
1854
1855The available waker functions include:
1856
1857 complete();
1858 wake_up();
1859 wake_up_all();
1860 wake_up_bit();
1861 wake_up_interruptible();
1862 wake_up_interruptible_all();
1863 wake_up_interruptible_nr();
1864 wake_up_interruptible_poll();
1865 wake_up_interruptible_sync();
1866 wake_up_interruptible_sync_poll();
1867 wake_up_locked();
1868 wake_up_locked_poll();
1869 wake_up_nr();
1870 wake_up_poll();
1871 wake_up_process();
1872
1873
1874[!] Note that the memory barriers implied by the sleeper and the waker do _not_
1875order multiple stores before the wake-up with respect to loads of those stored
1876values after the sleeper has called set_current_state(). For instance, if the
1877sleeper does:
1878
1879 set_current_state(TASK_INTERRUPTIBLE);
1880 if (event_indicated)
1881 break;
1882 __set_current_state(TASK_RUNNING);
1883 do_something(my_data);
1884
1885and the waker does:
1886
1887 my_data = value;
1888 event_indicated = 1;
1889 wake_up(&event_wait_queue);
1890
1891there's no guarantee that the change to event_indicated will be perceived by
1892the sleeper as coming after the change to my_data. In such a circumstance, the
1893code on both sides must interpolate its own memory barriers between the
1894separate data accesses. Thus the above sleeper ought to do:
1895
1896 set_current_state(TASK_INTERRUPTIBLE);
1897 if (event_indicated) {
1898 smp_rmb();
1899 do_something(my_data);
1900 }
1901
1902and the waker should do:
1903
1904 my_data = value;
1905 smp_wmb();
1906 event_indicated = 1;
1907 wake_up(&event_wait_queue);
1908
1909
David Howells108b42b2006-03-31 16:00:29 +01001910MISCELLANEOUS FUNCTIONS
1911-----------------------
1912
1913Other functions that imply barriers:
1914
1915 (*) schedule() and similar imply full memory barriers.
1916
David Howells108b42b2006-03-31 16:00:29 +01001917
Peter Zijlstra2e4f5382013-11-06 14:57:36 +01001918===================================
1919INTER-CPU ACQUIRING BARRIER EFFECTS
1920===================================
David Howells108b42b2006-03-31 16:00:29 +01001921
1922On SMP systems locking primitives give a more substantial form of barrier: one
1923that does affect memory access ordering on other CPUs, within the context of
1924conflict on any particular lock.
1925
1926
Peter Zijlstra2e4f5382013-11-06 14:57:36 +01001927ACQUIRES VS MEMORY ACCESSES
1928---------------------------
David Howells108b42b2006-03-31 16:00:29 +01001929
Aneesh Kumar79afecf2006-05-15 09:44:36 -07001930Consider the following: the system has a pair of spinlocks (M) and (Q), and
David Howells108b42b2006-03-31 16:00:29 +01001931three CPUs; then should the following sequence of events occur:
1932
1933 CPU 1 CPU 2
1934 =============================== ===============================
Paul E. McKenney2ecf8102013-12-11 13:59:04 -08001935 ACCESS_ONCE(*A) = a; ACCESS_ONCE(*E) = e;
Peter Zijlstra2e4f5382013-11-06 14:57:36 +01001936 ACQUIRE M ACQUIRE Q
Paul E. McKenney2ecf8102013-12-11 13:59:04 -08001937 ACCESS_ONCE(*B) = b; ACCESS_ONCE(*F) = f;
1938 ACCESS_ONCE(*C) = c; ACCESS_ONCE(*G) = g;
Peter Zijlstra2e4f5382013-11-06 14:57:36 +01001939 RELEASE M RELEASE Q
Paul E. McKenney2ecf8102013-12-11 13:59:04 -08001940 ACCESS_ONCE(*D) = d; ACCESS_ONCE(*H) = h;
David Howells108b42b2006-03-31 16:00:29 +01001941
Jarek Poplawski81fc6322007-05-23 13:58:20 -07001942Then there is no guarantee as to what order CPU 3 will see the accesses to *A
David Howells108b42b2006-03-31 16:00:29 +01001943through *H occur in, other than the constraints imposed by the separate locks
1944on the separate CPUs. It might, for example, see:
1945
Peter Zijlstra2e4f5382013-11-06 14:57:36 +01001946 *E, ACQUIRE M, ACQUIRE Q, *G, *C, *F, *A, *B, RELEASE Q, *D, *H, RELEASE M
David Howells108b42b2006-03-31 16:00:29 +01001947
1948But it won't see any of:
1949
Peter Zijlstra2e4f5382013-11-06 14:57:36 +01001950 *B, *C or *D preceding ACQUIRE M
1951 *A, *B or *C following RELEASE M
1952 *F, *G or *H preceding ACQUIRE Q
1953 *E, *F or *G following RELEASE Q
David Howells108b42b2006-03-31 16:00:29 +01001954
1955
1956However, if the following occurs:
1957
1958 CPU 1 CPU 2
1959 =============================== ===============================
Paul E. McKenney2ecf8102013-12-11 13:59:04 -08001960 ACCESS_ONCE(*A) = a;
Peter Zijlstra2e4f5382013-11-06 14:57:36 +01001961 ACQUIRE M [1]
Paul E. McKenney2ecf8102013-12-11 13:59:04 -08001962 ACCESS_ONCE(*B) = b;
1963 ACCESS_ONCE(*C) = c;
Peter Zijlstra2e4f5382013-11-06 14:57:36 +01001964 RELEASE M [1]
Paul E. McKenney2ecf8102013-12-11 13:59:04 -08001965 ACCESS_ONCE(*D) = d; ACCESS_ONCE(*E) = e;
Peter Zijlstra2e4f5382013-11-06 14:57:36 +01001966 ACQUIRE M [2]
Paul E. McKenney17eb88e2013-12-11 13:59:09 -08001967 smp_mb__after_unlock_lock();
Paul E. McKenney2ecf8102013-12-11 13:59:04 -08001968 ACCESS_ONCE(*F) = f;
1969 ACCESS_ONCE(*G) = g;
Peter Zijlstra2e4f5382013-11-06 14:57:36 +01001970 RELEASE M [2]
Paul E. McKenney2ecf8102013-12-11 13:59:04 -08001971 ACCESS_ONCE(*H) = h;
David Howells108b42b2006-03-31 16:00:29 +01001972
Jarek Poplawski81fc6322007-05-23 13:58:20 -07001973CPU 3 might see:
David Howells108b42b2006-03-31 16:00:29 +01001974
Peter Zijlstra2e4f5382013-11-06 14:57:36 +01001975 *E, ACQUIRE M [1], *C, *B, *A, RELEASE M [1],
1976 ACQUIRE M [2], *H, *F, *G, RELEASE M [2], *D
David Howells108b42b2006-03-31 16:00:29 +01001977
Jarek Poplawski81fc6322007-05-23 13:58:20 -07001978But assuming CPU 1 gets the lock first, CPU 3 won't see any of:
David Howells108b42b2006-03-31 16:00:29 +01001979
Peter Zijlstra2e4f5382013-11-06 14:57:36 +01001980 *B, *C, *D, *F, *G or *H preceding ACQUIRE M [1]
1981 *A, *B or *C following RELEASE M [1]
1982 *F, *G or *H preceding ACQUIRE M [2]
1983 *A, *B, *C, *E, *F or *G following RELEASE M [2]
David Howells108b42b2006-03-31 16:00:29 +01001984
Paul E. McKenney17eb88e2013-12-11 13:59:09 -08001985Note that the smp_mb__after_unlock_lock() is critically important
1986here: Without it CPU 3 might see some of the above orderings.
1987Without smp_mb__after_unlock_lock(), the accesses are not guaranteed
1988to be seen in order unless CPU 3 holds lock M.
1989
David Howells108b42b2006-03-31 16:00:29 +01001990
Peter Zijlstra2e4f5382013-11-06 14:57:36 +01001991ACQUIRES VS I/O ACCESSES
1992------------------------
David Howells108b42b2006-03-31 16:00:29 +01001993
1994Under certain circumstances (especially involving NUMA), I/O accesses within
1995two spinlocked sections on two different CPUs may be seen as interleaved by the
1996PCI bridge, because the PCI bridge does not necessarily participate in the
1997cache-coherence protocol, and is therefore incapable of issuing the required
1998read memory barriers.
1999
2000For example:
2001
2002 CPU 1 CPU 2
2003 =============================== ===============================
2004 spin_lock(Q)
2005 writel(0, ADDR)
2006 writel(1, DATA);
2007 spin_unlock(Q);
2008 spin_lock(Q);
2009 writel(4, ADDR);
2010 writel(5, DATA);
2011 spin_unlock(Q);
2012
2013may be seen by the PCI bridge as follows:
2014
2015 STORE *ADDR = 0, STORE *ADDR = 4, STORE *DATA = 1, STORE *DATA = 5
2016
2017which would probably cause the hardware to malfunction.
2018
2019
2020What is necessary here is to intervene with an mmiowb() before dropping the
2021spinlock, for example:
2022
2023 CPU 1 CPU 2
2024 =============================== ===============================
2025 spin_lock(Q)
2026 writel(0, ADDR)
2027 writel(1, DATA);
2028 mmiowb();
2029 spin_unlock(Q);
2030 spin_lock(Q);
2031 writel(4, ADDR);
2032 writel(5, DATA);
2033 mmiowb();
2034 spin_unlock(Q);
2035
Jarek Poplawski81fc6322007-05-23 13:58:20 -07002036this will ensure that the two stores issued on CPU 1 appear at the PCI bridge
2037before either of the stores issued on CPU 2.
David Howells108b42b2006-03-31 16:00:29 +01002038
2039
Jarek Poplawski81fc6322007-05-23 13:58:20 -07002040Furthermore, following a store by a load from the same device obviates the need
2041for the mmiowb(), because the load forces the store to complete before the load
David Howells108b42b2006-03-31 16:00:29 +01002042is performed:
2043
2044 CPU 1 CPU 2
2045 =============================== ===============================
2046 spin_lock(Q)
2047 writel(0, ADDR)
2048 a = readl(DATA);
2049 spin_unlock(Q);
2050 spin_lock(Q);
2051 writel(4, ADDR);
2052 b = readl(DATA);
2053 spin_unlock(Q);
2054
2055
2056See Documentation/DocBook/deviceiobook.tmpl for more information.
2057
2058
2059=================================
2060WHERE ARE MEMORY BARRIERS NEEDED?
2061=================================
2062
2063Under normal operation, memory operation reordering is generally not going to
2064be a problem as a single-threaded linear piece of code will still appear to
David Howells50fa6102009-04-28 15:01:38 +01002065work correctly, even if it's in an SMP kernel. There are, however, four
David Howells108b42b2006-03-31 16:00:29 +01002066circumstances in which reordering definitely _could_ be a problem:
2067
2068 (*) Interprocessor interaction.
2069
2070 (*) Atomic operations.
2071
Jarek Poplawski81fc6322007-05-23 13:58:20 -07002072 (*) Accessing devices.
David Howells108b42b2006-03-31 16:00:29 +01002073
2074 (*) Interrupts.
2075
2076
2077INTERPROCESSOR INTERACTION
2078--------------------------
2079
2080When there's a system with more than one processor, more than one CPU in the
2081system may be working on the same data set at the same time. This can cause
2082synchronisation problems, and the usual way of dealing with them is to use
2083locks. Locks, however, are quite expensive, and so it may be preferable to
2084operate without the use of a lock if at all possible. In such a case
2085operations that affect both CPUs may have to be carefully ordered to prevent
2086a malfunction.
2087
2088Consider, for example, the R/W semaphore slow path. Here a waiting process is
2089queued on the semaphore, by virtue of it having a piece of its stack linked to
2090the semaphore's list of waiting processes:
2091
2092 struct rw_semaphore {
2093 ...
2094 spinlock_t lock;
2095 struct list_head waiters;
2096 };
2097
2098 struct rwsem_waiter {
2099 struct list_head list;
2100 struct task_struct *task;
2101 };
2102
2103To wake up a particular waiter, the up_read() or up_write() functions have to:
2104
2105 (1) read the next pointer from this waiter's record to know as to where the
2106 next waiter record is;
2107
Jarek Poplawski81fc6322007-05-23 13:58:20 -07002108 (2) read the pointer to the waiter's task structure;
David Howells108b42b2006-03-31 16:00:29 +01002109
2110 (3) clear the task pointer to tell the waiter it has been given the semaphore;
2111
2112 (4) call wake_up_process() on the task; and
2113
2114 (5) release the reference held on the waiter's task struct.
2115
Jarek Poplawski81fc6322007-05-23 13:58:20 -07002116In other words, it has to perform this sequence of events:
David Howells108b42b2006-03-31 16:00:29 +01002117
2118 LOAD waiter->list.next;
2119 LOAD waiter->task;
2120 STORE waiter->task;
2121 CALL wakeup
2122 RELEASE task
2123
2124and if any of these steps occur out of order, then the whole thing may
2125malfunction.
2126
2127Once it has queued itself and dropped the semaphore lock, the waiter does not
2128get the lock again; it instead just waits for its task pointer to be cleared
2129before proceeding. Since the record is on the waiter's stack, this means that
2130if the task pointer is cleared _before_ the next pointer in the list is read,
2131another CPU might start processing the waiter and might clobber the waiter's
2132stack before the up*() function has a chance to read the next pointer.
2133
2134Consider then what might happen to the above sequence of events:
2135
2136 CPU 1 CPU 2
2137 =============================== ===============================
2138 down_xxx()
2139 Queue waiter
2140 Sleep
2141 up_yyy()
2142 LOAD waiter->task;
2143 STORE waiter->task;
2144 Woken up by other event
2145 <preempt>
2146 Resume processing
2147 down_xxx() returns
2148 call foo()
2149 foo() clobbers *waiter
2150 </preempt>
2151 LOAD waiter->list.next;
2152 --- OOPS ---
2153
2154This could be dealt with using the semaphore lock, but then the down_xxx()
2155function has to needlessly get the spinlock again after being woken up.
2156
2157The way to deal with this is to insert a general SMP memory barrier:
2158
2159 LOAD waiter->list.next;
2160 LOAD waiter->task;
2161 smp_mb();
2162 STORE waiter->task;
2163 CALL wakeup
2164 RELEASE task
2165
2166In this case, the barrier makes a guarantee that all memory accesses before the
2167barrier will appear to happen before all the memory accesses after the barrier
2168with respect to the other CPUs on the system. It does _not_ guarantee that all
2169the memory accesses before the barrier will be complete by the time the barrier
2170instruction itself is complete.
2171
2172On a UP system - where this wouldn't be a problem - the smp_mb() is just a
2173compiler barrier, thus making sure the compiler emits the instructions in the
David Howells6bc39272006-06-25 05:49:22 -07002174right order without actually intervening in the CPU. Since there's only one
2175CPU, that CPU's dependency ordering logic will take care of everything else.
David Howells108b42b2006-03-31 16:00:29 +01002176
2177
2178ATOMIC OPERATIONS
2179-----------------
2180
David Howellsdbc87002006-04-10 22:54:23 -07002181Whilst they are technically interprocessor interaction considerations, atomic
2182operations are noted specially as some of them imply full memory barriers and
2183some don't, but they're very heavily relied on as a group throughout the
2184kernel.
2185
2186Any atomic operation that modifies some state in memory and returns information
2187about the state (old or new) implies an SMP-conditional general memory barrier
Nick Piggin26333572007-10-18 03:06:39 -07002188(smp_mb()) on each side of the actual operation (with the exception of
2189explicit lock operations, described later). These include:
David Howells108b42b2006-03-31 16:00:29 +01002190
2191 xchg();
2192 cmpxchg();
Paul E. McKenneyfb2b5812013-12-11 13:59:05 -08002193 atomic_xchg(); atomic_long_xchg();
2194 atomic_cmpxchg(); atomic_long_cmpxchg();
2195 atomic_inc_return(); atomic_long_inc_return();
2196 atomic_dec_return(); atomic_long_dec_return();
2197 atomic_add_return(); atomic_long_add_return();
2198 atomic_sub_return(); atomic_long_sub_return();
2199 atomic_inc_and_test(); atomic_long_inc_and_test();
2200 atomic_dec_and_test(); atomic_long_dec_and_test();
2201 atomic_sub_and_test(); atomic_long_sub_and_test();
2202 atomic_add_negative(); atomic_long_add_negative();
David Howellsdbc87002006-04-10 22:54:23 -07002203 test_and_set_bit();
2204 test_and_clear_bit();
2205 test_and_change_bit();
David Howells108b42b2006-03-31 16:00:29 +01002206
Paul E. McKenneyfb2b5812013-12-11 13:59:05 -08002207 /* when succeeds (returns 1) */
2208 atomic_add_unless(); atomic_long_add_unless();
2209
Peter Zijlstra2e4f5382013-11-06 14:57:36 +01002210These are used for such things as implementing ACQUIRE-class and RELEASE-class
David Howellsdbc87002006-04-10 22:54:23 -07002211operations and adjusting reference counters towards object destruction, and as
2212such the implicit memory barrier effects are necessary.
David Howells108b42b2006-03-31 16:00:29 +01002213
David Howells108b42b2006-03-31 16:00:29 +01002214
Jarek Poplawski81fc6322007-05-23 13:58:20 -07002215The following operations are potential problems as they do _not_ imply memory
Peter Zijlstra2e4f5382013-11-06 14:57:36 +01002216barriers, but might be used for implementing such things as RELEASE-class
David Howellsdbc87002006-04-10 22:54:23 -07002217operations:
2218
2219 atomic_set();
David Howells108b42b2006-03-31 16:00:29 +01002220 set_bit();
2221 clear_bit();
2222 change_bit();
David Howellsdbc87002006-04-10 22:54:23 -07002223
2224With these the appropriate explicit memory barrier should be used if necessary
2225(smp_mb__before_clear_bit() for instance).
David Howells108b42b2006-03-31 16:00:29 +01002226
2227
David Howellsdbc87002006-04-10 22:54:23 -07002228The following also do _not_ imply memory barriers, and so may require explicit
2229memory barriers under some circumstances (smp_mb__before_atomic_dec() for
Jarek Poplawski81fc6322007-05-23 13:58:20 -07002230instance):
David Howells108b42b2006-03-31 16:00:29 +01002231
2232 atomic_add();
2233 atomic_sub();
2234 atomic_inc();
2235 atomic_dec();
2236
2237If they're used for statistics generation, then they probably don't need memory
2238barriers, unless there's a coupling between statistical data.
2239
2240If they're used for reference counting on an object to control its lifetime,
2241they probably don't need memory barriers because either the reference count
2242will be adjusted inside a locked section, or the caller will already hold
2243sufficient references to make the lock, and thus a memory barrier unnecessary.
2244
2245If they're used for constructing a lock of some description, then they probably
2246do need memory barriers as a lock primitive generally has to do things in a
2247specific order.
2248
David Howells108b42b2006-03-31 16:00:29 +01002249Basically, each usage case has to be carefully considered as to whether memory
David Howellsdbc87002006-04-10 22:54:23 -07002250barriers are needed or not.
2251
Nick Piggin26333572007-10-18 03:06:39 -07002252The following operations are special locking primitives:
2253
2254 test_and_set_bit_lock();
2255 clear_bit_unlock();
2256 __clear_bit_unlock();
2257
Peter Zijlstra2e4f5382013-11-06 14:57:36 +01002258These implement ACQUIRE-class and RELEASE-class operations. These should be used in
Nick Piggin26333572007-10-18 03:06:39 -07002259preference to other operations when implementing locking primitives, because
2260their implementations can be optimised on many architectures.
2261
David Howellsdbc87002006-04-10 22:54:23 -07002262[!] Note that special memory barrier primitives are available for these
2263situations because on some CPUs the atomic instructions used imply full memory
2264barriers, and so barrier instructions are superfluous in conjunction with them,
2265and in such cases the special barrier primitives will be no-ops.
David Howells108b42b2006-03-31 16:00:29 +01002266
2267See Documentation/atomic_ops.txt for more information.
2268
2269
2270ACCESSING DEVICES
2271-----------------
2272
2273Many devices can be memory mapped, and so appear to the CPU as if they're just
2274a set of memory locations. To control such a device, the driver usually has to
2275make the right memory accesses in exactly the right order.
2276
2277However, having a clever CPU or a clever compiler creates a potential problem
2278in that the carefully sequenced accesses in the driver code won't reach the
2279device in the requisite order if the CPU or the compiler thinks it is more
2280efficient to reorder, combine or merge accesses - something that would cause
2281the device to malfunction.
2282
2283Inside of the Linux kernel, I/O should be done through the appropriate accessor
2284routines - such as inb() or writel() - which know how to make such accesses
2285appropriately sequential. Whilst this, for the most part, renders the explicit
2286use of memory barriers unnecessary, there are a couple of situations where they
2287might be needed:
2288
2289 (1) On some systems, I/O stores are not strongly ordered across all CPUs, and
2290 so for _all_ general drivers locks should be used and mmiowb() must be
2291 issued prior to unlocking the critical section.
2292
2293 (2) If the accessor functions are used to refer to an I/O memory window with
2294 relaxed memory access properties, then _mandatory_ memory barriers are
2295 required to enforce ordering.
2296
2297See Documentation/DocBook/deviceiobook.tmpl for more information.
2298
2299
2300INTERRUPTS
2301----------
2302
2303A driver may be interrupted by its own interrupt service routine, and thus the
2304two parts of the driver may interfere with each other's attempts to control or
2305access the device.
2306
2307This may be alleviated - at least in part - by disabling local interrupts (a
2308form of locking), such that the critical operations are all contained within
2309the interrupt-disabled section in the driver. Whilst the driver's interrupt
2310routine is executing, the driver's core may not run on the same CPU, and its
2311interrupt is not permitted to happen again until the current interrupt has been
2312handled, thus the interrupt handler does not need to lock against that.
2313
2314However, consider a driver that was talking to an ethernet card that sports an
2315address register and a data register. If that driver's core talks to the card
2316under interrupt-disablement and then the driver's interrupt handler is invoked:
2317
2318 LOCAL IRQ DISABLE
2319 writew(ADDR, 3);
2320 writew(DATA, y);
2321 LOCAL IRQ ENABLE
2322 <interrupt>
2323 writew(ADDR, 4);
2324 q = readw(DATA);
2325 </interrupt>
2326
2327The store to the data register might happen after the second store to the
2328address register if ordering rules are sufficiently relaxed:
2329
2330 STORE *ADDR = 3, STORE *ADDR = 4, STORE *DATA = y, q = LOAD *DATA
2331
2332
2333If ordering rules are relaxed, it must be assumed that accesses done inside an
2334interrupt disabled section may leak outside of it and may interleave with
2335accesses performed in an interrupt - and vice versa - unless implicit or
2336explicit barriers are used.
2337
2338Normally this won't be a problem because the I/O accesses done inside such
2339sections will include synchronous load operations on strictly ordered I/O
2340registers that form implicit I/O barriers. If this isn't sufficient then an
2341mmiowb() may need to be used explicitly.
2342
2343
2344A similar situation may occur between an interrupt routine and two routines
2345running on separate CPUs that communicate with each other. If such a case is
2346likely, then interrupt-disabling locks should be used to guarantee ordering.
2347
2348
2349==========================
2350KERNEL I/O BARRIER EFFECTS
2351==========================
2352
2353When accessing I/O memory, drivers should use the appropriate accessor
2354functions:
2355
2356 (*) inX(), outX():
2357
2358 These are intended to talk to I/O space rather than memory space, but
2359 that's primarily a CPU-specific concept. The i386 and x86_64 processors do
2360 indeed have special I/O space access cycles and instructions, but many
2361 CPUs don't have such a concept.
2362
Jarek Poplawski81fc6322007-05-23 13:58:20 -07002363 The PCI bus, amongst others, defines an I/O space concept which - on such
2364 CPUs as i386 and x86_64 - readily maps to the CPU's concept of I/O
David Howells6bc39272006-06-25 05:49:22 -07002365 space. However, it may also be mapped as a virtual I/O space in the CPU's
2366 memory map, particularly on those CPUs that don't support alternate I/O
2367 spaces.
David Howells108b42b2006-03-31 16:00:29 +01002368
2369 Accesses to this space may be fully synchronous (as on i386), but
2370 intermediary bridges (such as the PCI host bridge) may not fully honour
2371 that.
2372
2373 They are guaranteed to be fully ordered with respect to each other.
2374
2375 They are not guaranteed to be fully ordered with respect to other types of
2376 memory and I/O operation.
2377
2378 (*) readX(), writeX():
2379
2380 Whether these are guaranteed to be fully ordered and uncombined with
2381 respect to each other on the issuing CPU depends on the characteristics
2382 defined for the memory window through which they're accessing. On later
2383 i386 architecture machines, for example, this is controlled by way of the
2384 MTRR registers.
2385
Jarek Poplawski81fc6322007-05-23 13:58:20 -07002386 Ordinarily, these will be guaranteed to be fully ordered and uncombined,
David Howells108b42b2006-03-31 16:00:29 +01002387 provided they're not accessing a prefetchable device.
2388
2389 However, intermediary hardware (such as a PCI bridge) may indulge in
2390 deferral if it so wishes; to flush a store, a load from the same location
2391 is preferred[*], but a load from the same device or from configuration
2392 space should suffice for PCI.
2393
2394 [*] NOTE! attempting to load from the same location as was written to may
Ingo Molnare0edc782013-11-22 11:24:53 +01002395 cause a malfunction - consider the 16550 Rx/Tx serial registers for
2396 example.
David Howells108b42b2006-03-31 16:00:29 +01002397
2398 Used with prefetchable I/O memory, an mmiowb() barrier may be required to
2399 force stores to be ordered.
2400
2401 Please refer to the PCI specification for more information on interactions
2402 between PCI transactions.
2403
2404 (*) readX_relaxed()
2405
2406 These are similar to readX(), but are not guaranteed to be ordered in any
2407 way. Be aware that there is no I/O read barrier available.
2408
2409 (*) ioreadX(), iowriteX()
2410
Jarek Poplawski81fc6322007-05-23 13:58:20 -07002411 These will perform appropriately for the type of access they're actually
David Howells108b42b2006-03-31 16:00:29 +01002412 doing, be it inX()/outX() or readX()/writeX().
2413
2414
2415========================================
2416ASSUMED MINIMUM EXECUTION ORDERING MODEL
2417========================================
2418
2419It has to be assumed that the conceptual CPU is weakly-ordered but that it will
2420maintain the appearance of program causality with respect to itself. Some CPUs
2421(such as i386 or x86_64) are more constrained than others (such as powerpc or
2422frv), and so the most relaxed case (namely DEC Alpha) must be assumed outside
2423of arch-specific code.
2424
2425This means that it must be considered that the CPU will execute its instruction
2426stream in any order it feels like - or even in parallel - provided that if an
Jarek Poplawski81fc6322007-05-23 13:58:20 -07002427instruction in the stream depends on an earlier instruction, then that
David Howells108b42b2006-03-31 16:00:29 +01002428earlier instruction must be sufficiently complete[*] before the later
2429instruction may proceed; in other words: provided that the appearance of
2430causality is maintained.
2431
2432 [*] Some instructions have more than one effect - such as changing the
2433 condition codes, changing registers or changing memory - and different
2434 instructions may depend on different effects.
2435
2436A CPU may also discard any instruction sequence that winds up having no
2437ultimate effect. For example, if two adjacent instructions both load an
2438immediate value into the same register, the first may be discarded.
2439
2440
2441Similarly, it has to be assumed that compiler might reorder the instruction
2442stream in any way it sees fit, again provided the appearance of causality is
2443maintained.
2444
2445
2446============================
2447THE EFFECTS OF THE CPU CACHE
2448============================
2449
2450The way cached memory operations are perceived across the system is affected to
2451a certain extent by the caches that lie between CPUs and memory, and by the
2452memory coherence system that maintains the consistency of state in the system.
2453
2454As far as the way a CPU interacts with another part of the system through the
2455caches goes, the memory system has to include the CPU's caches, and memory
2456barriers for the most part act at the interface between the CPU and its cache
2457(memory barriers logically act on the dotted line in the following diagram):
2458
2459 <--- CPU ---> : <----------- Memory ----------->
2460 :
2461 +--------+ +--------+ : +--------+ +-----------+
2462 | | | | : | | | | +--------+
Ingo Molnare0edc782013-11-22 11:24:53 +01002463 | CPU | | Memory | : | CPU | | | | |
2464 | Core |--->| Access |----->| Cache |<-->| | | |
David Howells108b42b2006-03-31 16:00:29 +01002465 | | | Queue | : | | | |--->| Memory |
Ingo Molnare0edc782013-11-22 11:24:53 +01002466 | | | | : | | | | | |
2467 +--------+ +--------+ : +--------+ | | | |
David Howells108b42b2006-03-31 16:00:29 +01002468 : | Cache | +--------+
2469 : | Coherency |
2470 : | Mechanism | +--------+
2471 +--------+ +--------+ : +--------+ | | | |
2472 | | | | : | | | | | |
2473 | CPU | | Memory | : | CPU | | |--->| Device |
Ingo Molnare0edc782013-11-22 11:24:53 +01002474 | Core |--->| Access |----->| Cache |<-->| | | |
2475 | | | Queue | : | | | | | |
David Howells108b42b2006-03-31 16:00:29 +01002476 | | | | : | | | | +--------+
2477 +--------+ +--------+ : +--------+ +-----------+
2478 :
2479 :
2480
2481Although any particular load or store may not actually appear outside of the
2482CPU that issued it since it may have been satisfied within the CPU's own cache,
2483it will still appear as if the full memory access had taken place as far as the
2484other CPUs are concerned since the cache coherency mechanisms will migrate the
2485cacheline over to the accessing CPU and propagate the effects upon conflict.
2486
2487The CPU core may execute instructions in any order it deems fit, provided the
2488expected program causality appears to be maintained. Some of the instructions
2489generate load and store operations which then go into the queue of memory
2490accesses to be performed. The core may place these in the queue in any order
2491it wishes, and continue execution until it is forced to wait for an instruction
2492to complete.
2493
2494What memory barriers are concerned with is controlling the order in which
2495accesses cross from the CPU side of things to the memory side of things, and
2496the order in which the effects are perceived to happen by the other observers
2497in the system.
2498
2499[!] Memory barriers are _not_ needed within a given CPU, as CPUs always see
2500their own loads and stores as if they had happened in program order.
2501
2502[!] MMIO or other device accesses may bypass the cache system. This depends on
2503the properties of the memory window through which devices are accessed and/or
2504the use of any special device communication instructions the CPU may have.
2505
2506
2507CACHE COHERENCY
2508---------------
2509
2510Life isn't quite as simple as it may appear above, however: for while the
2511caches are expected to be coherent, there's no guarantee that that coherency
2512will be ordered. This means that whilst changes made on one CPU will
2513eventually become visible on all CPUs, there's no guarantee that they will
2514become apparent in the same order on those other CPUs.
2515
2516
Jarek Poplawski81fc6322007-05-23 13:58:20 -07002517Consider dealing with a system that has a pair of CPUs (1 & 2), each of which
2518has a pair of parallel data caches (CPU 1 has A/B, and CPU 2 has C/D):
David Howells108b42b2006-03-31 16:00:29 +01002519
2520 :
2521 : +--------+
2522 : +---------+ | |
2523 +--------+ : +--->| Cache A |<------->| |
2524 | | : | +---------+ | |
2525 | CPU 1 |<---+ | |
2526 | | : | +---------+ | |
2527 +--------+ : +--->| Cache B |<------->| |
2528 : +---------+ | |
2529 : | Memory |
2530 : +---------+ | System |
2531 +--------+ : +--->| Cache C |<------->| |
2532 | | : | +---------+ | |
2533 | CPU 2 |<---+ | |
2534 | | : | +---------+ | |
2535 +--------+ : +--->| Cache D |<------->| |
2536 : +---------+ | |
2537 : +--------+
2538 :
2539
2540Imagine the system has the following properties:
2541
2542 (*) an odd-numbered cache line may be in cache A, cache C or it may still be
2543 resident in memory;
2544
2545 (*) an even-numbered cache line may be in cache B, cache D or it may still be
2546 resident in memory;
2547
2548 (*) whilst the CPU core is interrogating one cache, the other cache may be
2549 making use of the bus to access the rest of the system - perhaps to
2550 displace a dirty cacheline or to do a speculative load;
2551
2552 (*) each cache has a queue of operations that need to be applied to that cache
2553 to maintain coherency with the rest of the system;
2554
2555 (*) the coherency queue is not flushed by normal loads to lines already
2556 present in the cache, even though the contents of the queue may
Jarek Poplawski81fc6322007-05-23 13:58:20 -07002557 potentially affect those loads.
David Howells108b42b2006-03-31 16:00:29 +01002558
2559Imagine, then, that two writes are made on the first CPU, with a write barrier
2560between them to guarantee that they will appear to reach that CPU's caches in
2561the requisite order:
2562
2563 CPU 1 CPU 2 COMMENT
2564 =============== =============== =======================================
2565 u == 0, v == 1 and p == &u, q == &u
2566 v = 2;
Jarek Poplawski81fc6322007-05-23 13:58:20 -07002567 smp_wmb(); Make sure change to v is visible before
David Howells108b42b2006-03-31 16:00:29 +01002568 change to p
2569 <A:modify v=2> v is now in cache A exclusively
2570 p = &v;
2571 <B:modify p=&v> p is now in cache B exclusively
2572
2573The write memory barrier forces the other CPUs in the system to perceive that
2574the local CPU's caches have apparently been updated in the correct order. But
Jarek Poplawski81fc6322007-05-23 13:58:20 -07002575now imagine that the second CPU wants to read those values:
David Howells108b42b2006-03-31 16:00:29 +01002576
2577 CPU 1 CPU 2 COMMENT
2578 =============== =============== =======================================
2579 ...
2580 q = p;
2581 x = *q;
2582
Jarek Poplawski81fc6322007-05-23 13:58:20 -07002583The above pair of reads may then fail to happen in the expected order, as the
David Howells108b42b2006-03-31 16:00:29 +01002584cacheline holding p may get updated in one of the second CPU's caches whilst
2585the update to the cacheline holding v is delayed in the other of the second
2586CPU's caches by some other cache event:
2587
2588 CPU 1 CPU 2 COMMENT
2589 =============== =============== =======================================
2590 u == 0, v == 1 and p == &u, q == &u
2591 v = 2;
2592 smp_wmb();
2593 <A:modify v=2> <C:busy>
2594 <C:queue v=2>
Aneesh Kumar79afecf2006-05-15 09:44:36 -07002595 p = &v; q = p;
David Howells108b42b2006-03-31 16:00:29 +01002596 <D:request p>
2597 <B:modify p=&v> <D:commit p=&v>
Ingo Molnare0edc782013-11-22 11:24:53 +01002598 <D:read p>
David Howells108b42b2006-03-31 16:00:29 +01002599 x = *q;
2600 <C:read *q> Reads from v before v updated in cache
2601 <C:unbusy>
2602 <C:commit v=2>
2603
2604Basically, whilst both cachelines will be updated on CPU 2 eventually, there's
2605no guarantee that, without intervention, the order of update will be the same
2606as that committed on CPU 1.
2607
2608
2609To intervene, we need to interpolate a data dependency barrier or a read
2610barrier between the loads. This will force the cache to commit its coherency
2611queue before processing any further requests:
2612
2613 CPU 1 CPU 2 COMMENT
2614 =============== =============== =======================================
2615 u == 0, v == 1 and p == &u, q == &u
2616 v = 2;
2617 smp_wmb();
2618 <A:modify v=2> <C:busy>
2619 <C:queue v=2>
Paolo 'Blaisorblade' Giarrusso3fda9822006-10-19 23:28:19 -07002620 p = &v; q = p;
David Howells108b42b2006-03-31 16:00:29 +01002621 <D:request p>
2622 <B:modify p=&v> <D:commit p=&v>
Ingo Molnare0edc782013-11-22 11:24:53 +01002623 <D:read p>
David Howells108b42b2006-03-31 16:00:29 +01002624 smp_read_barrier_depends()
2625 <C:unbusy>
2626 <C:commit v=2>
2627 x = *q;
2628 <C:read *q> Reads from v after v updated in cache
2629
2630
2631This sort of problem can be encountered on DEC Alpha processors as they have a
2632split cache that improves performance by making better use of the data bus.
2633Whilst most CPUs do imply a data dependency barrier on the read when a memory
2634access depends on a read, not all do, so it may not be relied on.
2635
2636Other CPUs may also have split caches, but must coordinate between the various
Matt LaPlante3f6dee92006-10-03 22:45:33 +02002637cachelets for normal memory accesses. The semantics of the Alpha removes the
Jarek Poplawski81fc6322007-05-23 13:58:20 -07002638need for coordination in the absence of memory barriers.
David Howells108b42b2006-03-31 16:00:29 +01002639
2640
2641CACHE COHERENCY VS DMA
2642----------------------
2643
2644Not all systems maintain cache coherency with respect to devices doing DMA. In
2645such cases, a device attempting DMA may obtain stale data from RAM because
2646dirty cache lines may be resident in the caches of various CPUs, and may not
2647have been written back to RAM yet. To deal with this, the appropriate part of
2648the kernel must flush the overlapping bits of cache on each CPU (and maybe
2649invalidate them as well).
2650
2651In addition, the data DMA'd to RAM by a device may be overwritten by dirty
2652cache lines being written back to RAM from a CPU's cache after the device has
Jarek Poplawski81fc6322007-05-23 13:58:20 -07002653installed its own data, or cache lines present in the CPU's cache may simply
2654obscure the fact that RAM has been updated, until at such time as the cacheline
2655is discarded from the CPU's cache and reloaded. To deal with this, the
2656appropriate part of the kernel must invalidate the overlapping bits of the
David Howells108b42b2006-03-31 16:00:29 +01002657cache on each CPU.
2658
2659See Documentation/cachetlb.txt for more information on cache management.
2660
2661
2662CACHE COHERENCY VS MMIO
2663-----------------------
2664
2665Memory mapped I/O usually takes place through memory locations that are part of
Jarek Poplawski81fc6322007-05-23 13:58:20 -07002666a window in the CPU's memory space that has different properties assigned than
David Howells108b42b2006-03-31 16:00:29 +01002667the usual RAM directed window.
2668
2669Amongst these properties is usually the fact that such accesses bypass the
2670caching entirely and go directly to the device buses. This means MMIO accesses
2671may, in effect, overtake accesses to cached memory that were emitted earlier.
2672A memory barrier isn't sufficient in such a case, but rather the cache must be
2673flushed between the cached memory write and the MMIO access if the two are in
2674any way dependent.
2675
2676
2677=========================
2678THE THINGS CPUS GET UP TO
2679=========================
2680
2681A programmer might take it for granted that the CPU will perform memory
Jarek Poplawski81fc6322007-05-23 13:58:20 -07002682operations in exactly the order specified, so that if the CPU is, for example,
David Howells108b42b2006-03-31 16:00:29 +01002683given the following piece of code to execute:
2684
Paul E. McKenney2ecf8102013-12-11 13:59:04 -08002685 a = ACCESS_ONCE(*A);
2686 ACCESS_ONCE(*B) = b;
2687 c = ACCESS_ONCE(*C);
2688 d = ACCESS_ONCE(*D);
2689 ACCESS_ONCE(*E) = e;
David Howells108b42b2006-03-31 16:00:29 +01002690
Jarek Poplawski81fc6322007-05-23 13:58:20 -07002691they would then expect that the CPU will complete the memory operation for each
David Howells108b42b2006-03-31 16:00:29 +01002692instruction before moving on to the next one, leading to a definite sequence of
2693operations as seen by external observers in the system:
2694
2695 LOAD *A, STORE *B, LOAD *C, LOAD *D, STORE *E.
2696
2697
2698Reality is, of course, much messier. With many CPUs and compilers, the above
2699assumption doesn't hold because:
2700
2701 (*) loads are more likely to need to be completed immediately to permit
2702 execution progress, whereas stores can often be deferred without a
2703 problem;
2704
2705 (*) loads may be done speculatively, and the result discarded should it prove
2706 to have been unnecessary;
2707
Jarek Poplawski81fc6322007-05-23 13:58:20 -07002708 (*) loads may be done speculatively, leading to the result having been fetched
2709 at the wrong time in the expected sequence of events;
David Howells108b42b2006-03-31 16:00:29 +01002710
2711 (*) the order of the memory accesses may be rearranged to promote better use
2712 of the CPU buses and caches;
2713
2714 (*) loads and stores may be combined to improve performance when talking to
2715 memory or I/O hardware that can do batched accesses of adjacent locations,
2716 thus cutting down on transaction setup costs (memory and PCI devices may
2717 both be able to do this); and
2718
2719 (*) the CPU's data cache may affect the ordering, and whilst cache-coherency
2720 mechanisms may alleviate this - once the store has actually hit the cache
2721 - there's no guarantee that the coherency management will be propagated in
2722 order to other CPUs.
2723
2724So what another CPU, say, might actually observe from the above piece of code
2725is:
2726
2727 LOAD *A, ..., LOAD {*C,*D}, STORE *E, STORE *B
2728
2729 (Where "LOAD {*C,*D}" is a combined load)
2730
2731
2732However, it is guaranteed that a CPU will be self-consistent: it will see its
2733_own_ accesses appear to be correctly ordered, without the need for a memory
2734barrier. For instance with the following code:
2735
Paul E. McKenney2ecf8102013-12-11 13:59:04 -08002736 U = ACCESS_ONCE(*A);
2737 ACCESS_ONCE(*A) = V;
2738 ACCESS_ONCE(*A) = W;
2739 X = ACCESS_ONCE(*A);
2740 ACCESS_ONCE(*A) = Y;
2741 Z = ACCESS_ONCE(*A);
David Howells108b42b2006-03-31 16:00:29 +01002742
2743and assuming no intervention by an external influence, it can be assumed that
2744the final result will appear to be:
2745
2746 U == the original value of *A
2747 X == W
2748 Z == Y
2749 *A == Y
2750
2751The code above may cause the CPU to generate the full sequence of memory
2752accesses:
2753
2754 U=LOAD *A, STORE *A=V, STORE *A=W, X=LOAD *A, STORE *A=Y, Z=LOAD *A
2755
2756in that order, but, without intervention, the sequence may have almost any
2757combination of elements combined or discarded, provided the program's view of
Paul E. McKenney2ecf8102013-12-11 13:59:04 -08002758the world remains consistent. Note that ACCESS_ONCE() is -not- optional
2759in the above example, as there are architectures where a given CPU might
2760interchange successive loads to the same location. On such architectures,
2761ACCESS_ONCE() does whatever is necessary to prevent this, for example, on
2762Itanium the volatile casts used by ACCESS_ONCE() cause GCC to emit the
2763special ld.acq and st.rel instructions that prevent such reordering.
David Howells108b42b2006-03-31 16:00:29 +01002764
2765The compiler may also combine, discard or defer elements of the sequence before
2766the CPU even sees them.
2767
2768For instance:
2769
2770 *A = V;
2771 *A = W;
2772
2773may be reduced to:
2774
2775 *A = W;
2776
Paul E. McKenney2ecf8102013-12-11 13:59:04 -08002777since, without either a write barrier or an ACCESS_ONCE(), it can be
2778assumed that the effect of the storage of V to *A is lost. Similarly:
David Howells108b42b2006-03-31 16:00:29 +01002779
2780 *A = Y;
2781 Z = *A;
2782
Paul E. McKenney2ecf8102013-12-11 13:59:04 -08002783may, without a memory barrier or an ACCESS_ONCE(), be reduced to:
David Howells108b42b2006-03-31 16:00:29 +01002784
2785 *A = Y;
2786 Z = Y;
2787
2788and the LOAD operation never appear outside of the CPU.
2789
2790
2791AND THEN THERE'S THE ALPHA
2792--------------------------
2793
2794The DEC Alpha CPU is one of the most relaxed CPUs there is. Not only that,
2795some versions of the Alpha CPU have a split data cache, permitting them to have
Jarek Poplawski81fc6322007-05-23 13:58:20 -07002796two semantically-related cache lines updated at separate times. This is where
David Howells108b42b2006-03-31 16:00:29 +01002797the data dependency barrier really becomes necessary as this synchronises both
2798caches with the memory coherence system, thus making it seem like pointer
2799changes vs new data occur in the right order.
2800
Jarek Poplawski81fc6322007-05-23 13:58:20 -07002801The Alpha defines the Linux kernel's memory barrier model.
David Howells108b42b2006-03-31 16:00:29 +01002802
2803See the subsection on "Cache Coherency" above.
2804
2805
David Howells90fddab2010-03-24 09:43:00 +00002806============
2807EXAMPLE USES
2808============
2809
2810CIRCULAR BUFFERS
2811----------------
2812
2813Memory barriers can be used to implement circular buffering without the need
2814of a lock to serialise the producer with the consumer. See:
2815
2816 Documentation/circular-buffers.txt
2817
2818for details.
2819
2820
David Howells108b42b2006-03-31 16:00:29 +01002821==========
2822REFERENCES
2823==========
2824
2825Alpha AXP Architecture Reference Manual, Second Edition (Sites & Witek,
2826Digital Press)
2827 Chapter 5.2: Physical Address Space Characteristics
2828 Chapter 5.4: Caches and Write Buffers
2829 Chapter 5.5: Data Sharing
2830 Chapter 5.6: Read/Write Ordering
2831
2832AMD64 Architecture Programmer's Manual Volume 2: System Programming
2833 Chapter 7.1: Memory-Access Ordering
2834 Chapter 7.4: Buffering and Combining Memory Writes
2835
2836IA-32 Intel Architecture Software Developer's Manual, Volume 3:
2837System Programming Guide
2838 Chapter 7.1: Locked Atomic Operations
2839 Chapter 7.2: Memory Ordering
2840 Chapter 7.4: Serializing Instructions
2841
2842The SPARC Architecture Manual, Version 9
2843 Chapter 8: Memory Models
2844 Appendix D: Formal Specification of the Memory Models
2845 Appendix J: Programming with the Memory Models
2846
2847UltraSPARC Programmer Reference Manual
2848 Chapter 5: Memory Accesses and Cacheability
2849 Chapter 15: Sparc-V9 Memory Models
2850
2851UltraSPARC III Cu User's Manual
2852 Chapter 9: Memory Models
2853
2854UltraSPARC IIIi Processor User's Manual
2855 Chapter 8: Memory Models
2856
2857UltraSPARC Architecture 2005
2858 Chapter 9: Memory
2859 Appendix D: Formal Specifications of the Memory Models
2860
2861UltraSPARC T1 Supplement to the UltraSPARC Architecture 2005
2862 Chapter 8: Memory Models
2863 Appendix F: Caches and Cache Coherency
2864
2865Solaris Internals, Core Kernel Architecture, p63-68:
2866 Chapter 3.3: Hardware Considerations for Locks and
2867 Synchronization
2868
2869Unix Systems for Modern Architectures, Symmetric Multiprocessing and Caching
2870for Kernel Programmers:
2871 Chapter 13: Other Memory Models
2872
2873Intel Itanium Architecture Software Developer's Manual: Volume 1:
2874 Section 2.6: Speculation
2875 Section 4.4: Memory Access