Lendacky, Thomas | c5aa9e3 | 2014-06-05 09:15:06 -0500 | [diff] [blame] | 1 | /* |
| 2 | * AMD 10Gb Ethernet driver |
| 3 | * |
| 4 | * This file is available to you under your choice of the following two |
| 5 | * licenses: |
| 6 | * |
| 7 | * License 1: GPLv2 |
| 8 | * |
| 9 | * Copyright (c) 2014 Advanced Micro Devices, Inc. |
| 10 | * |
| 11 | * This file is free software; you may copy, redistribute and/or modify |
| 12 | * it under the terms of the GNU General Public License as published by |
| 13 | * the Free Software Foundation, either version 2 of the License, or (at |
| 14 | * your option) any later version. |
| 15 | * |
| 16 | * This file is distributed in the hope that it will be useful, but |
| 17 | * WITHOUT ANY WARRANTY; without even the implied warranty of |
| 18 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU |
| 19 | * General Public License for more details. |
| 20 | * |
| 21 | * You should have received a copy of the GNU General Public License |
| 22 | * along with this program. If not, see <http://www.gnu.org/licenses/>. |
| 23 | * |
| 24 | * This file incorporates work covered by the following copyright and |
| 25 | * permission notice: |
| 26 | * The Synopsys DWC ETHER XGMAC Software Driver and documentation |
| 27 | * (hereinafter "Software") is an unsupported proprietary work of Synopsys, |
| 28 | * Inc. unless otherwise expressly agreed to in writing between Synopsys |
| 29 | * and you. |
| 30 | * |
| 31 | * The Software IS NOT an item of Licensed Software or Licensed Product |
| 32 | * under any End User Software License Agreement or Agreement for Licensed |
| 33 | * Product with Synopsys or any supplement thereto. Permission is hereby |
| 34 | * granted, free of charge, to any person obtaining a copy of this software |
| 35 | * annotated with this license and the Software, to deal in the Software |
| 36 | * without restriction, including without limitation the rights to use, |
| 37 | * copy, modify, merge, publish, distribute, sublicense, and/or sell copies |
| 38 | * of the Software, and to permit persons to whom the Software is furnished |
| 39 | * to do so, subject to the following conditions: |
| 40 | * |
| 41 | * The above copyright notice and this permission notice shall be included |
| 42 | * in all copies or substantial portions of the Software. |
| 43 | * |
| 44 | * THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS" |
| 45 | * BASIS AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED |
| 46 | * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A |
| 47 | * PARTICULAR PURPOSE ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS |
| 48 | * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR |
| 49 | * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF |
| 50 | * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS |
| 51 | * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN |
| 52 | * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) |
| 53 | * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF |
| 54 | * THE POSSIBILITY OF SUCH DAMAGE. |
| 55 | * |
| 56 | * |
| 57 | * License 2: Modified BSD |
| 58 | * |
| 59 | * Copyright (c) 2014 Advanced Micro Devices, Inc. |
| 60 | * All rights reserved. |
| 61 | * |
| 62 | * Redistribution and use in source and binary forms, with or without |
| 63 | * modification, are permitted provided that the following conditions are met: |
| 64 | * * Redistributions of source code must retain the above copyright |
| 65 | * notice, this list of conditions and the following disclaimer. |
| 66 | * * Redistributions in binary form must reproduce the above copyright |
| 67 | * notice, this list of conditions and the following disclaimer in the |
| 68 | * documentation and/or other materials provided with the distribution. |
| 69 | * * Neither the name of Advanced Micro Devices, Inc. nor the |
| 70 | * names of its contributors may be used to endorse or promote products |
| 71 | * derived from this software without specific prior written permission. |
| 72 | * |
| 73 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" |
| 74 | * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE |
| 75 | * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE |
| 76 | * ARE DISCLAIMED. IN NO EVENT SHALL <COPYRIGHT HOLDER> BE LIABLE FOR ANY |
| 77 | * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES |
| 78 | * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; |
| 79 | * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND |
| 80 | * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT |
| 81 | * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF |
| 82 | * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
| 83 | * |
| 84 | * This file incorporates work covered by the following copyright and |
| 85 | * permission notice: |
| 86 | * The Synopsys DWC ETHER XGMAC Software Driver and documentation |
| 87 | * (hereinafter "Software") is an unsupported proprietary work of Synopsys, |
| 88 | * Inc. unless otherwise expressly agreed to in writing between Synopsys |
| 89 | * and you. |
| 90 | * |
| 91 | * The Software IS NOT an item of Licensed Software or Licensed Product |
| 92 | * under any End User Software License Agreement or Agreement for Licensed |
| 93 | * Product with Synopsys or any supplement thereto. Permission is hereby |
| 94 | * granted, free of charge, to any person obtaining a copy of this software |
| 95 | * annotated with this license and the Software, to deal in the Software |
| 96 | * without restriction, including without limitation the rights to use, |
| 97 | * copy, modify, merge, publish, distribute, sublicense, and/or sell copies |
| 98 | * of the Software, and to permit persons to whom the Software is furnished |
| 99 | * to do so, subject to the following conditions: |
| 100 | * |
| 101 | * The above copyright notice and this permission notice shall be included |
| 102 | * in all copies or substantial portions of the Software. |
| 103 | * |
| 104 | * THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS" |
| 105 | * BASIS AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED |
| 106 | * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A |
| 107 | * PARTICULAR PURPOSE ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS |
| 108 | * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR |
| 109 | * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF |
| 110 | * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS |
| 111 | * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN |
| 112 | * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) |
| 113 | * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF |
| 114 | * THE POSSIBILITY OF SUCH DAMAGE. |
| 115 | */ |
| 116 | |
| 117 | #include <linux/phy.h> |
Lendacky, Thomas | c3152d4 | 2015-01-16 12:47:00 -0600 | [diff] [blame] | 118 | #include <linux/mdio.h> |
Lendacky, Thomas | c5aa9e3 | 2014-06-05 09:15:06 -0500 | [diff] [blame] | 119 | #include <linux/clk.h> |
Lendacky, Thomas | 801c62d | 2014-06-24 16:19:24 -0500 | [diff] [blame] | 120 | #include <linux/bitrev.h> |
Lendacky, Thomas | b85e4d8 | 2014-06-24 16:19:29 -0500 | [diff] [blame] | 121 | #include <linux/crc32.h> |
Lendacky, Thomas | c5aa9e3 | 2014-06-05 09:15:06 -0500 | [diff] [blame] | 122 | |
| 123 | #include "xgbe.h" |
| 124 | #include "xgbe-common.h" |
| 125 | |
Lendacky, Thomas | c5aa9e3 | 2014-06-05 09:15:06 -0500 | [diff] [blame] | 126 | static unsigned int xgbe_usec_to_riwt(struct xgbe_prv_data *pdata, |
| 127 | unsigned int usec) |
| 128 | { |
| 129 | unsigned long rate; |
| 130 | unsigned int ret; |
| 131 | |
| 132 | DBGPR("-->xgbe_usec_to_riwt\n"); |
| 133 | |
Lendacky, Thomas | 82a1903 | 2015-01-16 12:47:16 -0600 | [diff] [blame] | 134 | rate = pdata->sysclk_rate; |
Lendacky, Thomas | c5aa9e3 | 2014-06-05 09:15:06 -0500 | [diff] [blame] | 135 | |
| 136 | /* |
| 137 | * Convert the input usec value to the watchdog timer value. Each |
| 138 | * watchdog timer value is equivalent to 256 clock cycles. |
| 139 | * Calculate the required value as: |
| 140 | * ( usec * ( system_clock_mhz / 10^6 ) / 256 |
| 141 | */ |
| 142 | ret = (usec * (rate / 1000000)) / 256; |
| 143 | |
| 144 | DBGPR("<--xgbe_usec_to_riwt\n"); |
| 145 | |
| 146 | return ret; |
| 147 | } |
| 148 | |
| 149 | static unsigned int xgbe_riwt_to_usec(struct xgbe_prv_data *pdata, |
| 150 | unsigned int riwt) |
| 151 | { |
| 152 | unsigned long rate; |
| 153 | unsigned int ret; |
| 154 | |
| 155 | DBGPR("-->xgbe_riwt_to_usec\n"); |
| 156 | |
Lendacky, Thomas | 82a1903 | 2015-01-16 12:47:16 -0600 | [diff] [blame] | 157 | rate = pdata->sysclk_rate; |
Lendacky, Thomas | c5aa9e3 | 2014-06-05 09:15:06 -0500 | [diff] [blame] | 158 | |
| 159 | /* |
| 160 | * Convert the input watchdog timer value to the usec value. Each |
| 161 | * watchdog timer value is equivalent to 256 clock cycles. |
| 162 | * Calculate the required value as: |
| 163 | * ( riwt * 256 ) / ( system_clock_mhz / 10^6 ) |
| 164 | */ |
| 165 | ret = (riwt * 256) / (rate / 1000000); |
| 166 | |
| 167 | DBGPR("<--xgbe_riwt_to_usec\n"); |
| 168 | |
| 169 | return ret; |
| 170 | } |
| 171 | |
| 172 | static int xgbe_config_pblx8(struct xgbe_prv_data *pdata) |
| 173 | { |
| 174 | struct xgbe_channel *channel; |
| 175 | unsigned int i; |
| 176 | |
| 177 | channel = pdata->channel; |
| 178 | for (i = 0; i < pdata->channel_count; i++, channel++) |
| 179 | XGMAC_DMA_IOWRITE_BITS(channel, DMA_CH_CR, PBLX8, |
| 180 | pdata->pblx8); |
| 181 | |
| 182 | return 0; |
| 183 | } |
| 184 | |
| 185 | static int xgbe_get_tx_pbl_val(struct xgbe_prv_data *pdata) |
| 186 | { |
| 187 | return XGMAC_DMA_IOREAD_BITS(pdata->channel, DMA_CH_TCR, PBL); |
| 188 | } |
| 189 | |
| 190 | static int xgbe_config_tx_pbl_val(struct xgbe_prv_data *pdata) |
| 191 | { |
| 192 | struct xgbe_channel *channel; |
| 193 | unsigned int i; |
| 194 | |
| 195 | channel = pdata->channel; |
| 196 | for (i = 0; i < pdata->channel_count; i++, channel++) { |
| 197 | if (!channel->tx_ring) |
| 198 | break; |
| 199 | |
| 200 | XGMAC_DMA_IOWRITE_BITS(channel, DMA_CH_TCR, PBL, |
| 201 | pdata->tx_pbl); |
| 202 | } |
| 203 | |
| 204 | return 0; |
| 205 | } |
| 206 | |
| 207 | static int xgbe_get_rx_pbl_val(struct xgbe_prv_data *pdata) |
| 208 | { |
| 209 | return XGMAC_DMA_IOREAD_BITS(pdata->channel, DMA_CH_RCR, PBL); |
| 210 | } |
| 211 | |
| 212 | static int xgbe_config_rx_pbl_val(struct xgbe_prv_data *pdata) |
| 213 | { |
| 214 | struct xgbe_channel *channel; |
| 215 | unsigned int i; |
| 216 | |
| 217 | channel = pdata->channel; |
| 218 | for (i = 0; i < pdata->channel_count; i++, channel++) { |
| 219 | if (!channel->rx_ring) |
| 220 | break; |
| 221 | |
| 222 | XGMAC_DMA_IOWRITE_BITS(channel, DMA_CH_RCR, PBL, |
| 223 | pdata->rx_pbl); |
| 224 | } |
| 225 | |
| 226 | return 0; |
| 227 | } |
| 228 | |
| 229 | static int xgbe_config_osp_mode(struct xgbe_prv_data *pdata) |
| 230 | { |
| 231 | struct xgbe_channel *channel; |
| 232 | unsigned int i; |
| 233 | |
| 234 | channel = pdata->channel; |
| 235 | for (i = 0; i < pdata->channel_count; i++, channel++) { |
| 236 | if (!channel->tx_ring) |
| 237 | break; |
| 238 | |
| 239 | XGMAC_DMA_IOWRITE_BITS(channel, DMA_CH_TCR, OSP, |
| 240 | pdata->tx_osp_mode); |
| 241 | } |
| 242 | |
| 243 | return 0; |
| 244 | } |
| 245 | |
| 246 | static int xgbe_config_rsf_mode(struct xgbe_prv_data *pdata, unsigned int val) |
| 247 | { |
| 248 | unsigned int i; |
| 249 | |
Lendacky, Thomas | 853eb16 | 2014-07-29 08:57:31 -0500 | [diff] [blame] | 250 | for (i = 0; i < pdata->rx_q_count; i++) |
Lendacky, Thomas | c5aa9e3 | 2014-06-05 09:15:06 -0500 | [diff] [blame] | 251 | XGMAC_MTL_IOWRITE_BITS(pdata, i, MTL_Q_RQOMR, RSF, val); |
| 252 | |
| 253 | return 0; |
| 254 | } |
| 255 | |
| 256 | static int xgbe_config_tsf_mode(struct xgbe_prv_data *pdata, unsigned int val) |
| 257 | { |
| 258 | unsigned int i; |
| 259 | |
Lendacky, Thomas | 853eb16 | 2014-07-29 08:57:31 -0500 | [diff] [blame] | 260 | for (i = 0; i < pdata->tx_q_count; i++) |
Lendacky, Thomas | c5aa9e3 | 2014-06-05 09:15:06 -0500 | [diff] [blame] | 261 | XGMAC_MTL_IOWRITE_BITS(pdata, i, MTL_Q_TQOMR, TSF, val); |
| 262 | |
| 263 | return 0; |
| 264 | } |
| 265 | |
| 266 | static int xgbe_config_rx_threshold(struct xgbe_prv_data *pdata, |
| 267 | unsigned int val) |
| 268 | { |
| 269 | unsigned int i; |
| 270 | |
Lendacky, Thomas | 853eb16 | 2014-07-29 08:57:31 -0500 | [diff] [blame] | 271 | for (i = 0; i < pdata->rx_q_count; i++) |
Lendacky, Thomas | c5aa9e3 | 2014-06-05 09:15:06 -0500 | [diff] [blame] | 272 | XGMAC_MTL_IOWRITE_BITS(pdata, i, MTL_Q_RQOMR, RTC, val); |
| 273 | |
| 274 | return 0; |
| 275 | } |
| 276 | |
| 277 | static int xgbe_config_tx_threshold(struct xgbe_prv_data *pdata, |
| 278 | unsigned int val) |
| 279 | { |
| 280 | unsigned int i; |
| 281 | |
Lendacky, Thomas | 853eb16 | 2014-07-29 08:57:31 -0500 | [diff] [blame] | 282 | for (i = 0; i < pdata->tx_q_count; i++) |
Lendacky, Thomas | c5aa9e3 | 2014-06-05 09:15:06 -0500 | [diff] [blame] | 283 | XGMAC_MTL_IOWRITE_BITS(pdata, i, MTL_Q_TQOMR, TTC, val); |
| 284 | |
| 285 | return 0; |
| 286 | } |
| 287 | |
| 288 | static int xgbe_config_rx_coalesce(struct xgbe_prv_data *pdata) |
| 289 | { |
| 290 | struct xgbe_channel *channel; |
| 291 | unsigned int i; |
| 292 | |
| 293 | channel = pdata->channel; |
| 294 | for (i = 0; i < pdata->channel_count; i++, channel++) { |
| 295 | if (!channel->rx_ring) |
| 296 | break; |
| 297 | |
| 298 | XGMAC_DMA_IOWRITE_BITS(channel, DMA_CH_RIWT, RWT, |
| 299 | pdata->rx_riwt); |
| 300 | } |
| 301 | |
| 302 | return 0; |
| 303 | } |
| 304 | |
| 305 | static int xgbe_config_tx_coalesce(struct xgbe_prv_data *pdata) |
| 306 | { |
| 307 | return 0; |
| 308 | } |
| 309 | |
| 310 | static void xgbe_config_rx_buffer_size(struct xgbe_prv_data *pdata) |
| 311 | { |
| 312 | struct xgbe_channel *channel; |
| 313 | unsigned int i; |
| 314 | |
| 315 | channel = pdata->channel; |
| 316 | for (i = 0; i < pdata->channel_count; i++, channel++) { |
| 317 | if (!channel->rx_ring) |
| 318 | break; |
| 319 | |
| 320 | XGMAC_DMA_IOWRITE_BITS(channel, DMA_CH_RCR, RBSZ, |
| 321 | pdata->rx_buf_size); |
| 322 | } |
| 323 | } |
| 324 | |
| 325 | static void xgbe_config_tso_mode(struct xgbe_prv_data *pdata) |
| 326 | { |
| 327 | struct xgbe_channel *channel; |
| 328 | unsigned int i; |
| 329 | |
| 330 | channel = pdata->channel; |
| 331 | for (i = 0; i < pdata->channel_count; i++, channel++) { |
| 332 | if (!channel->tx_ring) |
| 333 | break; |
| 334 | |
| 335 | XGMAC_DMA_IOWRITE_BITS(channel, DMA_CH_TCR, TSE, 1); |
| 336 | } |
| 337 | } |
| 338 | |
Lendacky, Thomas | 174fd25 | 2014-11-04 16:06:50 -0600 | [diff] [blame] | 339 | static void xgbe_config_sph_mode(struct xgbe_prv_data *pdata) |
| 340 | { |
| 341 | struct xgbe_channel *channel; |
| 342 | unsigned int i; |
| 343 | |
| 344 | channel = pdata->channel; |
| 345 | for (i = 0; i < pdata->channel_count; i++, channel++) { |
| 346 | if (!channel->rx_ring) |
| 347 | break; |
| 348 | |
| 349 | XGMAC_DMA_IOWRITE_BITS(channel, DMA_CH_CR, SPH, 1); |
| 350 | } |
| 351 | |
| 352 | XGMAC_IOWRITE_BITS(pdata, MAC_RCR, HDSMS, XGBE_SPH_HDSMS_SIZE); |
| 353 | } |
| 354 | |
Lendacky, Thomas | 5b9dfe2 | 2014-11-04 16:07:02 -0600 | [diff] [blame] | 355 | static int xgbe_write_rss_reg(struct xgbe_prv_data *pdata, unsigned int type, |
| 356 | unsigned int index, unsigned int val) |
| 357 | { |
| 358 | unsigned int wait; |
| 359 | int ret = 0; |
| 360 | |
| 361 | mutex_lock(&pdata->rss_mutex); |
| 362 | |
| 363 | if (XGMAC_IOREAD_BITS(pdata, MAC_RSSAR, OB)) { |
| 364 | ret = -EBUSY; |
| 365 | goto unlock; |
| 366 | } |
| 367 | |
| 368 | XGMAC_IOWRITE(pdata, MAC_RSSDR, val); |
| 369 | |
| 370 | XGMAC_IOWRITE_BITS(pdata, MAC_RSSAR, RSSIA, index); |
| 371 | XGMAC_IOWRITE_BITS(pdata, MAC_RSSAR, ADDRT, type); |
| 372 | XGMAC_IOWRITE_BITS(pdata, MAC_RSSAR, CT, 0); |
| 373 | XGMAC_IOWRITE_BITS(pdata, MAC_RSSAR, OB, 1); |
| 374 | |
| 375 | wait = 1000; |
| 376 | while (wait--) { |
| 377 | if (!XGMAC_IOREAD_BITS(pdata, MAC_RSSAR, OB)) |
| 378 | goto unlock; |
| 379 | |
| 380 | usleep_range(1000, 1500); |
| 381 | } |
| 382 | |
| 383 | ret = -EBUSY; |
| 384 | |
| 385 | unlock: |
| 386 | mutex_unlock(&pdata->rss_mutex); |
| 387 | |
| 388 | return ret; |
| 389 | } |
| 390 | |
| 391 | static int xgbe_write_rss_hash_key(struct xgbe_prv_data *pdata) |
| 392 | { |
| 393 | unsigned int key_regs = sizeof(pdata->rss_key) / sizeof(u32); |
| 394 | unsigned int *key = (unsigned int *)&pdata->rss_key; |
| 395 | int ret; |
| 396 | |
| 397 | while (key_regs--) { |
| 398 | ret = xgbe_write_rss_reg(pdata, XGBE_RSS_HASH_KEY_TYPE, |
| 399 | key_regs, *key++); |
| 400 | if (ret) |
| 401 | return ret; |
| 402 | } |
| 403 | |
| 404 | return 0; |
| 405 | } |
| 406 | |
| 407 | static int xgbe_write_rss_lookup_table(struct xgbe_prv_data *pdata) |
| 408 | { |
| 409 | unsigned int i; |
| 410 | int ret; |
| 411 | |
| 412 | for (i = 0; i < ARRAY_SIZE(pdata->rss_table); i++) { |
| 413 | ret = xgbe_write_rss_reg(pdata, |
| 414 | XGBE_RSS_LOOKUP_TABLE_TYPE, i, |
| 415 | pdata->rss_table[i]); |
| 416 | if (ret) |
| 417 | return ret; |
| 418 | } |
| 419 | |
| 420 | return 0; |
| 421 | } |
| 422 | |
Lendacky, Thomas | f6ac862 | 2014-11-04 16:07:23 -0600 | [diff] [blame] | 423 | static int xgbe_set_rss_hash_key(struct xgbe_prv_data *pdata, const u8 *key) |
| 424 | { |
| 425 | memcpy(pdata->rss_key, key, sizeof(pdata->rss_key)); |
| 426 | |
| 427 | return xgbe_write_rss_hash_key(pdata); |
| 428 | } |
| 429 | |
| 430 | static int xgbe_set_rss_lookup_table(struct xgbe_prv_data *pdata, |
| 431 | const u32 *table) |
| 432 | { |
| 433 | unsigned int i; |
| 434 | |
| 435 | for (i = 0; i < ARRAY_SIZE(pdata->rss_table); i++) |
| 436 | XGMAC_SET_BITS(pdata->rss_table[i], MAC_RSSDR, DMCH, table[i]); |
| 437 | |
| 438 | return xgbe_write_rss_lookup_table(pdata); |
| 439 | } |
| 440 | |
Lendacky, Thomas | 5b9dfe2 | 2014-11-04 16:07:02 -0600 | [diff] [blame] | 441 | static int xgbe_enable_rss(struct xgbe_prv_data *pdata) |
| 442 | { |
| 443 | int ret; |
| 444 | |
| 445 | if (!pdata->hw_feat.rss) |
| 446 | return -EOPNOTSUPP; |
| 447 | |
| 448 | /* Program the hash key */ |
| 449 | ret = xgbe_write_rss_hash_key(pdata); |
| 450 | if (ret) |
| 451 | return ret; |
| 452 | |
| 453 | /* Program the lookup table */ |
| 454 | ret = xgbe_write_rss_lookup_table(pdata); |
| 455 | if (ret) |
| 456 | return ret; |
| 457 | |
| 458 | /* Set the RSS options */ |
| 459 | XGMAC_IOWRITE(pdata, MAC_RSSCR, pdata->rss_options); |
| 460 | |
| 461 | /* Enable RSS */ |
| 462 | XGMAC_IOWRITE_BITS(pdata, MAC_RSSCR, RSSE, 1); |
| 463 | |
| 464 | return 0; |
| 465 | } |
| 466 | |
| 467 | static int xgbe_disable_rss(struct xgbe_prv_data *pdata) |
| 468 | { |
| 469 | if (!pdata->hw_feat.rss) |
| 470 | return -EOPNOTSUPP; |
| 471 | |
| 472 | XGMAC_IOWRITE_BITS(pdata, MAC_RSSCR, RSSE, 0); |
| 473 | |
| 474 | return 0; |
| 475 | } |
| 476 | |
| 477 | static void xgbe_config_rss(struct xgbe_prv_data *pdata) |
| 478 | { |
| 479 | int ret; |
| 480 | |
| 481 | if (!pdata->hw_feat.rss) |
| 482 | return; |
| 483 | |
| 484 | if (pdata->netdev->features & NETIF_F_RXHASH) |
| 485 | ret = xgbe_enable_rss(pdata); |
| 486 | else |
| 487 | ret = xgbe_disable_rss(pdata); |
| 488 | |
| 489 | if (ret) |
| 490 | netdev_err(pdata->netdev, |
| 491 | "error configuring RSS, RSS disabled\n"); |
| 492 | } |
| 493 | |
Lendacky, Thomas | c5aa9e3 | 2014-06-05 09:15:06 -0500 | [diff] [blame] | 494 | static int xgbe_disable_tx_flow_control(struct xgbe_prv_data *pdata) |
| 495 | { |
| 496 | unsigned int max_q_count, q_count; |
| 497 | unsigned int reg, reg_val; |
| 498 | unsigned int i; |
| 499 | |
| 500 | /* Clear MTL flow control */ |
Lendacky, Thomas | 853eb16 | 2014-07-29 08:57:31 -0500 | [diff] [blame] | 501 | for (i = 0; i < pdata->rx_q_count; i++) |
Lendacky, Thomas | c5aa9e3 | 2014-06-05 09:15:06 -0500 | [diff] [blame] | 502 | XGMAC_MTL_IOWRITE_BITS(pdata, i, MTL_Q_RQOMR, EHFC, 0); |
| 503 | |
| 504 | /* Clear MAC flow control */ |
| 505 | max_q_count = XGMAC_MAX_FLOW_CONTROL_QUEUES; |
Lendacky, Thomas | 9fc69af | 2014-08-29 13:17:08 -0500 | [diff] [blame] | 506 | q_count = min_t(unsigned int, pdata->tx_q_count, max_q_count); |
Lendacky, Thomas | c5aa9e3 | 2014-06-05 09:15:06 -0500 | [diff] [blame] | 507 | reg = MAC_Q0TFCR; |
| 508 | for (i = 0; i < q_count; i++) { |
| 509 | reg_val = XGMAC_IOREAD(pdata, reg); |
| 510 | XGMAC_SET_BITS(reg_val, MAC_Q0TFCR, TFE, 0); |
| 511 | XGMAC_IOWRITE(pdata, reg, reg_val); |
| 512 | |
| 513 | reg += MAC_QTFCR_INC; |
| 514 | } |
| 515 | |
| 516 | return 0; |
| 517 | } |
| 518 | |
| 519 | static int xgbe_enable_tx_flow_control(struct xgbe_prv_data *pdata) |
| 520 | { |
| 521 | unsigned int max_q_count, q_count; |
| 522 | unsigned int reg, reg_val; |
| 523 | unsigned int i; |
| 524 | |
| 525 | /* Set MTL flow control */ |
Lendacky, Thomas | 853eb16 | 2014-07-29 08:57:31 -0500 | [diff] [blame] | 526 | for (i = 0; i < pdata->rx_q_count; i++) |
Lendacky, Thomas | c5aa9e3 | 2014-06-05 09:15:06 -0500 | [diff] [blame] | 527 | XGMAC_MTL_IOWRITE_BITS(pdata, i, MTL_Q_RQOMR, EHFC, 1); |
| 528 | |
| 529 | /* Set MAC flow control */ |
| 530 | max_q_count = XGMAC_MAX_FLOW_CONTROL_QUEUES; |
Lendacky, Thomas | 9fc69af | 2014-08-29 13:17:08 -0500 | [diff] [blame] | 531 | q_count = min_t(unsigned int, pdata->tx_q_count, max_q_count); |
Lendacky, Thomas | c5aa9e3 | 2014-06-05 09:15:06 -0500 | [diff] [blame] | 532 | reg = MAC_Q0TFCR; |
| 533 | for (i = 0; i < q_count; i++) { |
| 534 | reg_val = XGMAC_IOREAD(pdata, reg); |
| 535 | |
| 536 | /* Enable transmit flow control */ |
| 537 | XGMAC_SET_BITS(reg_val, MAC_Q0TFCR, TFE, 1); |
| 538 | /* Set pause time */ |
| 539 | XGMAC_SET_BITS(reg_val, MAC_Q0TFCR, PT, 0xffff); |
| 540 | |
| 541 | XGMAC_IOWRITE(pdata, reg, reg_val); |
| 542 | |
| 543 | reg += MAC_QTFCR_INC; |
| 544 | } |
| 545 | |
| 546 | return 0; |
| 547 | } |
| 548 | |
| 549 | static int xgbe_disable_rx_flow_control(struct xgbe_prv_data *pdata) |
| 550 | { |
| 551 | XGMAC_IOWRITE_BITS(pdata, MAC_RFCR, RFE, 0); |
| 552 | |
| 553 | return 0; |
| 554 | } |
| 555 | |
| 556 | static int xgbe_enable_rx_flow_control(struct xgbe_prv_data *pdata) |
| 557 | { |
| 558 | XGMAC_IOWRITE_BITS(pdata, MAC_RFCR, RFE, 1); |
| 559 | |
| 560 | return 0; |
| 561 | } |
| 562 | |
| 563 | static int xgbe_config_tx_flow_control(struct xgbe_prv_data *pdata) |
| 564 | { |
Lendacky, Thomas | fca2d99 | 2014-07-29 08:57:55 -0500 | [diff] [blame] | 565 | struct ieee_pfc *pfc = pdata->pfc; |
| 566 | |
| 567 | if (pdata->tx_pause || (pfc && pfc->pfc_en)) |
Lendacky, Thomas | c5aa9e3 | 2014-06-05 09:15:06 -0500 | [diff] [blame] | 568 | xgbe_enable_tx_flow_control(pdata); |
| 569 | else |
| 570 | xgbe_disable_tx_flow_control(pdata); |
| 571 | |
| 572 | return 0; |
| 573 | } |
| 574 | |
| 575 | static int xgbe_config_rx_flow_control(struct xgbe_prv_data *pdata) |
| 576 | { |
Lendacky, Thomas | fca2d99 | 2014-07-29 08:57:55 -0500 | [diff] [blame] | 577 | struct ieee_pfc *pfc = pdata->pfc; |
| 578 | |
| 579 | if (pdata->rx_pause || (pfc && pfc->pfc_en)) |
Lendacky, Thomas | c5aa9e3 | 2014-06-05 09:15:06 -0500 | [diff] [blame] | 580 | xgbe_enable_rx_flow_control(pdata); |
| 581 | else |
| 582 | xgbe_disable_rx_flow_control(pdata); |
| 583 | |
| 584 | return 0; |
| 585 | } |
| 586 | |
| 587 | static void xgbe_config_flow_control(struct xgbe_prv_data *pdata) |
| 588 | { |
Lendacky, Thomas | fca2d99 | 2014-07-29 08:57:55 -0500 | [diff] [blame] | 589 | struct ieee_pfc *pfc = pdata->pfc; |
| 590 | |
Lendacky, Thomas | c5aa9e3 | 2014-06-05 09:15:06 -0500 | [diff] [blame] | 591 | xgbe_config_tx_flow_control(pdata); |
| 592 | xgbe_config_rx_flow_control(pdata); |
Lendacky, Thomas | fca2d99 | 2014-07-29 08:57:55 -0500 | [diff] [blame] | 593 | |
| 594 | XGMAC_IOWRITE_BITS(pdata, MAC_RFCR, PFCE, |
| 595 | (pfc && pfc->pfc_en) ? 1 : 0); |
Lendacky, Thomas | c5aa9e3 | 2014-06-05 09:15:06 -0500 | [diff] [blame] | 596 | } |
| 597 | |
| 598 | static void xgbe_enable_dma_interrupts(struct xgbe_prv_data *pdata) |
| 599 | { |
| 600 | struct xgbe_channel *channel; |
| 601 | unsigned int dma_ch_isr, dma_ch_ier; |
| 602 | unsigned int i; |
| 603 | |
| 604 | channel = pdata->channel; |
| 605 | for (i = 0; i < pdata->channel_count; i++, channel++) { |
| 606 | /* Clear all the interrupts which are set */ |
| 607 | dma_ch_isr = XGMAC_DMA_IOREAD(channel, DMA_CH_SR); |
| 608 | XGMAC_DMA_IOWRITE(channel, DMA_CH_SR, dma_ch_isr); |
| 609 | |
| 610 | /* Clear all interrupt enable bits */ |
| 611 | dma_ch_ier = 0; |
| 612 | |
| 613 | /* Enable following interrupts |
| 614 | * NIE - Normal Interrupt Summary Enable |
| 615 | * AIE - Abnormal Interrupt Summary Enable |
| 616 | * FBEE - Fatal Bus Error Enable |
| 617 | */ |
| 618 | XGMAC_SET_BITS(dma_ch_ier, DMA_CH_IER, NIE, 1); |
| 619 | XGMAC_SET_BITS(dma_ch_ier, DMA_CH_IER, AIE, 1); |
| 620 | XGMAC_SET_BITS(dma_ch_ier, DMA_CH_IER, FBEE, 1); |
| 621 | |
| 622 | if (channel->tx_ring) { |
| 623 | /* Enable the following Tx interrupts |
Lendacky, Thomas | 9227dc5 | 2014-11-04 16:06:56 -0600 | [diff] [blame] | 624 | * TIE - Transmit Interrupt Enable (unless using |
| 625 | * per channel interrupts) |
Lendacky, Thomas | c5aa9e3 | 2014-06-05 09:15:06 -0500 | [diff] [blame] | 626 | */ |
Lendacky, Thomas | 9227dc5 | 2014-11-04 16:06:56 -0600 | [diff] [blame] | 627 | if (!pdata->per_channel_irq) |
| 628 | XGMAC_SET_BITS(dma_ch_ier, DMA_CH_IER, TIE, 1); |
Lendacky, Thomas | c5aa9e3 | 2014-06-05 09:15:06 -0500 | [diff] [blame] | 629 | } |
| 630 | if (channel->rx_ring) { |
| 631 | /* Enable following Rx interrupts |
| 632 | * RBUE - Receive Buffer Unavailable Enable |
Lendacky, Thomas | 9227dc5 | 2014-11-04 16:06:56 -0600 | [diff] [blame] | 633 | * RIE - Receive Interrupt Enable (unless using |
| 634 | * per channel interrupts) |
Lendacky, Thomas | c5aa9e3 | 2014-06-05 09:15:06 -0500 | [diff] [blame] | 635 | */ |
| 636 | XGMAC_SET_BITS(dma_ch_ier, DMA_CH_IER, RBUE, 1); |
Lendacky, Thomas | 9227dc5 | 2014-11-04 16:06:56 -0600 | [diff] [blame] | 637 | if (!pdata->per_channel_irq) |
| 638 | XGMAC_SET_BITS(dma_ch_ier, DMA_CH_IER, RIE, 1); |
Lendacky, Thomas | c5aa9e3 | 2014-06-05 09:15:06 -0500 | [diff] [blame] | 639 | } |
| 640 | |
| 641 | XGMAC_DMA_IOWRITE(channel, DMA_CH_IER, dma_ch_ier); |
| 642 | } |
| 643 | } |
| 644 | |
| 645 | static void xgbe_enable_mtl_interrupts(struct xgbe_prv_data *pdata) |
| 646 | { |
| 647 | unsigned int mtl_q_isr; |
| 648 | unsigned int q_count, i; |
| 649 | |
| 650 | q_count = max(pdata->hw_feat.tx_q_cnt, pdata->hw_feat.rx_q_cnt); |
| 651 | for (i = 0; i < q_count; i++) { |
| 652 | /* Clear all the interrupts which are set */ |
| 653 | mtl_q_isr = XGMAC_MTL_IOREAD(pdata, i, MTL_Q_ISR); |
| 654 | XGMAC_MTL_IOWRITE(pdata, i, MTL_Q_ISR, mtl_q_isr); |
| 655 | |
| 656 | /* No MTL interrupts to be enabled */ |
Lendacky, Thomas | 91f8734 | 2014-07-02 13:04:34 -0500 | [diff] [blame] | 657 | XGMAC_MTL_IOWRITE(pdata, i, MTL_Q_IER, 0); |
Lendacky, Thomas | c5aa9e3 | 2014-06-05 09:15:06 -0500 | [diff] [blame] | 658 | } |
| 659 | } |
| 660 | |
| 661 | static void xgbe_enable_mac_interrupts(struct xgbe_prv_data *pdata) |
| 662 | { |
Lendacky, Thomas | 23e4eef | 2014-07-29 08:57:19 -0500 | [diff] [blame] | 663 | unsigned int mac_ier = 0; |
| 664 | |
| 665 | /* Enable Timestamp interrupt */ |
| 666 | XGMAC_SET_BITS(mac_ier, MAC_IER, TSIE, 1); |
| 667 | |
| 668 | XGMAC_IOWRITE(pdata, MAC_IER, mac_ier); |
Lendacky, Thomas | c5aa9e3 | 2014-06-05 09:15:06 -0500 | [diff] [blame] | 669 | |
| 670 | /* Enable all counter interrupts */ |
Lendacky, Thomas | a3ba7c9 | 2014-09-05 18:02:36 -0500 | [diff] [blame] | 671 | XGMAC_IOWRITE_BITS(pdata, MMC_RIER, ALL_INTERRUPTS, 0xffffffff); |
| 672 | XGMAC_IOWRITE_BITS(pdata, MMC_TIER, ALL_INTERRUPTS, 0xffffffff); |
Lendacky, Thomas | c5aa9e3 | 2014-06-05 09:15:06 -0500 | [diff] [blame] | 673 | } |
| 674 | |
| 675 | static int xgbe_set_gmii_speed(struct xgbe_prv_data *pdata) |
| 676 | { |
Lendacky, Thomas | c3152d4 | 2015-01-16 12:47:00 -0600 | [diff] [blame] | 677 | if (XGMAC_IOREAD_BITS(pdata, MAC_TCR, SS) == 0x3) |
| 678 | return 0; |
| 679 | |
Lendacky, Thomas | c5aa9e3 | 2014-06-05 09:15:06 -0500 | [diff] [blame] | 680 | XGMAC_IOWRITE_BITS(pdata, MAC_TCR, SS, 0x3); |
| 681 | |
| 682 | return 0; |
| 683 | } |
| 684 | |
| 685 | static int xgbe_set_gmii_2500_speed(struct xgbe_prv_data *pdata) |
| 686 | { |
Lendacky, Thomas | c3152d4 | 2015-01-16 12:47:00 -0600 | [diff] [blame] | 687 | if (XGMAC_IOREAD_BITS(pdata, MAC_TCR, SS) == 0x2) |
| 688 | return 0; |
| 689 | |
Lendacky, Thomas | c5aa9e3 | 2014-06-05 09:15:06 -0500 | [diff] [blame] | 690 | XGMAC_IOWRITE_BITS(pdata, MAC_TCR, SS, 0x2); |
| 691 | |
| 692 | return 0; |
| 693 | } |
| 694 | |
| 695 | static int xgbe_set_xgmii_speed(struct xgbe_prv_data *pdata) |
| 696 | { |
Lendacky, Thomas | c3152d4 | 2015-01-16 12:47:00 -0600 | [diff] [blame] | 697 | if (XGMAC_IOREAD_BITS(pdata, MAC_TCR, SS) == 0) |
| 698 | return 0; |
| 699 | |
Lendacky, Thomas | c5aa9e3 | 2014-06-05 09:15:06 -0500 | [diff] [blame] | 700 | XGMAC_IOWRITE_BITS(pdata, MAC_TCR, SS, 0); |
| 701 | |
| 702 | return 0; |
| 703 | } |
| 704 | |
| 705 | static int xgbe_set_promiscuous_mode(struct xgbe_prv_data *pdata, |
| 706 | unsigned int enable) |
| 707 | { |
| 708 | unsigned int val = enable ? 1 : 0; |
| 709 | |
| 710 | if (XGMAC_IOREAD_BITS(pdata, MAC_PFR, PR) == val) |
| 711 | return 0; |
| 712 | |
Lendacky, Thomas | 34bf65d | 2015-05-14 11:44:03 -0500 | [diff] [blame] | 713 | netif_dbg(pdata, drv, pdata->netdev, "%s promiscuous mode\n", |
| 714 | enable ? "entering" : "leaving"); |
Lendacky, Thomas | c5aa9e3 | 2014-06-05 09:15:06 -0500 | [diff] [blame] | 715 | XGMAC_IOWRITE_BITS(pdata, MAC_PFR, PR, val); |
| 716 | |
| 717 | return 0; |
| 718 | } |
| 719 | |
| 720 | static int xgbe_set_all_multicast_mode(struct xgbe_prv_data *pdata, |
| 721 | unsigned int enable) |
| 722 | { |
| 723 | unsigned int val = enable ? 1 : 0; |
| 724 | |
| 725 | if (XGMAC_IOREAD_BITS(pdata, MAC_PFR, PM) == val) |
| 726 | return 0; |
| 727 | |
Lendacky, Thomas | 34bf65d | 2015-05-14 11:44:03 -0500 | [diff] [blame] | 728 | netif_dbg(pdata, drv, pdata->netdev, "%s allmulti mode\n", |
| 729 | enable ? "entering" : "leaving"); |
Lendacky, Thomas | c5aa9e3 | 2014-06-05 09:15:06 -0500 | [diff] [blame] | 730 | XGMAC_IOWRITE_BITS(pdata, MAC_PFR, PM, val); |
| 731 | |
| 732 | return 0; |
| 733 | } |
| 734 | |
Lendacky, Thomas | b85e4d8 | 2014-06-24 16:19:29 -0500 | [diff] [blame] | 735 | static void xgbe_set_mac_reg(struct xgbe_prv_data *pdata, |
| 736 | struct netdev_hw_addr *ha, unsigned int *mac_reg) |
Lendacky, Thomas | c5aa9e3 | 2014-06-05 09:15:06 -0500 | [diff] [blame] | 737 | { |
Lendacky, Thomas | c5aa9e3 | 2014-06-05 09:15:06 -0500 | [diff] [blame] | 738 | unsigned int mac_addr_hi, mac_addr_lo; |
| 739 | u8 *mac_addr; |
Lendacky, Thomas | c5aa9e3 | 2014-06-05 09:15:06 -0500 | [diff] [blame] | 740 | |
Lendacky, Thomas | b85e4d8 | 2014-06-24 16:19:29 -0500 | [diff] [blame] | 741 | mac_addr_lo = 0; |
| 742 | mac_addr_hi = 0; |
Lendacky, Thomas | c5aa9e3 | 2014-06-05 09:15:06 -0500 | [diff] [blame] | 743 | |
Lendacky, Thomas | b85e4d8 | 2014-06-24 16:19:29 -0500 | [diff] [blame] | 744 | if (ha) { |
Lendacky, Thomas | c5aa9e3 | 2014-06-05 09:15:06 -0500 | [diff] [blame] | 745 | mac_addr = (u8 *)&mac_addr_lo; |
| 746 | mac_addr[0] = ha->addr[0]; |
| 747 | mac_addr[1] = ha->addr[1]; |
| 748 | mac_addr[2] = ha->addr[2]; |
| 749 | mac_addr[3] = ha->addr[3]; |
| 750 | mac_addr = (u8 *)&mac_addr_hi; |
| 751 | mac_addr[0] = ha->addr[4]; |
| 752 | mac_addr[1] = ha->addr[5]; |
| 753 | |
Lendacky, Thomas | 34bf65d | 2015-05-14 11:44:03 -0500 | [diff] [blame] | 754 | netif_dbg(pdata, drv, pdata->netdev, |
| 755 | "adding mac address %pM at %#x\n", |
| 756 | ha->addr, *mac_reg); |
Lendacky, Thomas | c5aa9e3 | 2014-06-05 09:15:06 -0500 | [diff] [blame] | 757 | |
| 758 | XGMAC_SET_BITS(mac_addr_hi, MAC_MACA1HR, AE, 1); |
Lendacky, Thomas | c5aa9e3 | 2014-06-05 09:15:06 -0500 | [diff] [blame] | 759 | } |
| 760 | |
Lendacky, Thomas | b85e4d8 | 2014-06-24 16:19:29 -0500 | [diff] [blame] | 761 | XGMAC_IOWRITE(pdata, *mac_reg, mac_addr_hi); |
| 762 | *mac_reg += MAC_MACA_INC; |
| 763 | XGMAC_IOWRITE(pdata, *mac_reg, mac_addr_lo); |
| 764 | *mac_reg += MAC_MACA_INC; |
| 765 | } |
Lendacky, Thomas | c5aa9e3 | 2014-06-05 09:15:06 -0500 | [diff] [blame] | 766 | |
Lendacky, Thomas | b85e4d8 | 2014-06-24 16:19:29 -0500 | [diff] [blame] | 767 | static void xgbe_set_mac_addn_addrs(struct xgbe_prv_data *pdata) |
| 768 | { |
| 769 | struct net_device *netdev = pdata->netdev; |
| 770 | struct netdev_hw_addr *ha; |
| 771 | unsigned int mac_reg; |
| 772 | unsigned int addn_macs; |
Lendacky, Thomas | c5aa9e3 | 2014-06-05 09:15:06 -0500 | [diff] [blame] | 773 | |
Lendacky, Thomas | b85e4d8 | 2014-06-24 16:19:29 -0500 | [diff] [blame] | 774 | mac_reg = MAC_MACA1HR; |
| 775 | addn_macs = pdata->hw_feat.addn_mac; |
Lendacky, Thomas | c5aa9e3 | 2014-06-05 09:15:06 -0500 | [diff] [blame] | 776 | |
Lendacky, Thomas | b85e4d8 | 2014-06-24 16:19:29 -0500 | [diff] [blame] | 777 | if (netdev_uc_count(netdev) > addn_macs) { |
| 778 | xgbe_set_promiscuous_mode(pdata, 1); |
| 779 | } else { |
| 780 | netdev_for_each_uc_addr(ha, netdev) { |
| 781 | xgbe_set_mac_reg(pdata, ha, &mac_reg); |
| 782 | addn_macs--; |
| 783 | } |
Lendacky, Thomas | c5aa9e3 | 2014-06-05 09:15:06 -0500 | [diff] [blame] | 784 | |
Lendacky, Thomas | b85e4d8 | 2014-06-24 16:19:29 -0500 | [diff] [blame] | 785 | if (netdev_mc_count(netdev) > addn_macs) { |
| 786 | xgbe_set_all_multicast_mode(pdata, 1); |
| 787 | } else { |
| 788 | netdev_for_each_mc_addr(ha, netdev) { |
| 789 | xgbe_set_mac_reg(pdata, ha, &mac_reg); |
| 790 | addn_macs--; |
| 791 | } |
Lendacky, Thomas | c5aa9e3 | 2014-06-05 09:15:06 -0500 | [diff] [blame] | 792 | } |
| 793 | } |
| 794 | |
| 795 | /* Clear remaining additional MAC address entries */ |
Lendacky, Thomas | b85e4d8 | 2014-06-24 16:19:29 -0500 | [diff] [blame] | 796 | while (addn_macs--) |
| 797 | xgbe_set_mac_reg(pdata, NULL, &mac_reg); |
| 798 | } |
| 799 | |
| 800 | static void xgbe_set_mac_hash_table(struct xgbe_prv_data *pdata) |
| 801 | { |
| 802 | struct net_device *netdev = pdata->netdev; |
| 803 | struct netdev_hw_addr *ha; |
| 804 | unsigned int hash_reg; |
| 805 | unsigned int hash_table_shift, hash_table_count; |
| 806 | u32 hash_table[XGBE_MAC_HASH_TABLE_SIZE]; |
| 807 | u32 crc; |
| 808 | unsigned int i; |
| 809 | |
| 810 | hash_table_shift = 26 - (pdata->hw_feat.hash_table_size >> 7); |
| 811 | hash_table_count = pdata->hw_feat.hash_table_size / 32; |
| 812 | memset(hash_table, 0, sizeof(hash_table)); |
| 813 | |
| 814 | /* Build the MAC Hash Table register values */ |
| 815 | netdev_for_each_uc_addr(ha, netdev) { |
| 816 | crc = bitrev32(~crc32_le(~0, ha->addr, ETH_ALEN)); |
| 817 | crc >>= hash_table_shift; |
| 818 | hash_table[crc >> 5] |= (1 << (crc & 0x1f)); |
Lendacky, Thomas | c5aa9e3 | 2014-06-05 09:15:06 -0500 | [diff] [blame] | 819 | } |
| 820 | |
Lendacky, Thomas | b85e4d8 | 2014-06-24 16:19:29 -0500 | [diff] [blame] | 821 | netdev_for_each_mc_addr(ha, netdev) { |
| 822 | crc = bitrev32(~crc32_le(~0, ha->addr, ETH_ALEN)); |
| 823 | crc >>= hash_table_shift; |
| 824 | hash_table[crc >> 5] |= (1 << (crc & 0x1f)); |
| 825 | } |
| 826 | |
| 827 | /* Set the MAC Hash Table registers */ |
| 828 | hash_reg = MAC_HTR0; |
| 829 | for (i = 0; i < hash_table_count; i++) { |
| 830 | XGMAC_IOWRITE(pdata, hash_reg, hash_table[i]); |
| 831 | hash_reg += MAC_HTR_INC; |
| 832 | } |
| 833 | } |
| 834 | |
| 835 | static int xgbe_add_mac_addresses(struct xgbe_prv_data *pdata) |
| 836 | { |
| 837 | if (pdata->hw_feat.hash_table_size) |
| 838 | xgbe_set_mac_hash_table(pdata); |
| 839 | else |
| 840 | xgbe_set_mac_addn_addrs(pdata); |
| 841 | |
Lendacky, Thomas | c5aa9e3 | 2014-06-05 09:15:06 -0500 | [diff] [blame] | 842 | return 0; |
| 843 | } |
| 844 | |
| 845 | static int xgbe_set_mac_address(struct xgbe_prv_data *pdata, u8 *addr) |
| 846 | { |
| 847 | unsigned int mac_addr_hi, mac_addr_lo; |
| 848 | |
| 849 | mac_addr_hi = (addr[5] << 8) | (addr[4] << 0); |
| 850 | mac_addr_lo = (addr[3] << 24) | (addr[2] << 16) | |
| 851 | (addr[1] << 8) | (addr[0] << 0); |
| 852 | |
| 853 | XGMAC_IOWRITE(pdata, MAC_MACA0HR, mac_addr_hi); |
| 854 | XGMAC_IOWRITE(pdata, MAC_MACA0LR, mac_addr_lo); |
| 855 | |
| 856 | return 0; |
| 857 | } |
| 858 | |
Lendacky, Thomas | b876382 | 2015-04-09 12:11:57 -0500 | [diff] [blame] | 859 | static int xgbe_config_rx_mode(struct xgbe_prv_data *pdata) |
| 860 | { |
| 861 | struct net_device *netdev = pdata->netdev; |
| 862 | unsigned int pr_mode, am_mode; |
| 863 | |
| 864 | pr_mode = ((netdev->flags & IFF_PROMISC) != 0); |
| 865 | am_mode = ((netdev->flags & IFF_ALLMULTI) != 0); |
| 866 | |
| 867 | xgbe_set_promiscuous_mode(pdata, pr_mode); |
| 868 | xgbe_set_all_multicast_mode(pdata, am_mode); |
| 869 | |
| 870 | xgbe_add_mac_addresses(pdata); |
| 871 | |
| 872 | return 0; |
| 873 | } |
| 874 | |
Lendacky, Thomas | c5aa9e3 | 2014-06-05 09:15:06 -0500 | [diff] [blame] | 875 | static int xgbe_read_mmd_regs(struct xgbe_prv_data *pdata, int prtad, |
| 876 | int mmd_reg) |
| 877 | { |
| 878 | unsigned int mmd_address; |
| 879 | int mmd_data; |
| 880 | |
| 881 | if (mmd_reg & MII_ADDR_C45) |
| 882 | mmd_address = mmd_reg & ~MII_ADDR_C45; |
| 883 | else |
| 884 | mmd_address = (pdata->mdio_mmd << 16) | (mmd_reg & 0xffff); |
| 885 | |
| 886 | /* The PCS registers are accessed using mmio. The underlying APB3 |
| 887 | * management interface uses indirect addressing to access the MMD |
| 888 | * register sets. This requires accessing of the PCS register in two |
| 889 | * phases, an address phase and a data phase. |
| 890 | * |
| 891 | * The mmio interface is based on 32-bit offsets and values. All |
| 892 | * register offsets must therefore be adjusted by left shifting the |
| 893 | * offset 2 bits and reading 32 bits of data. |
| 894 | */ |
| 895 | mutex_lock(&pdata->xpcs_mutex); |
| 896 | XPCS_IOWRITE(pdata, PCS_MMD_SELECT << 2, mmd_address >> 8); |
| 897 | mmd_data = XPCS_IOREAD(pdata, (mmd_address & 0xff) << 2); |
| 898 | mutex_unlock(&pdata->xpcs_mutex); |
| 899 | |
| 900 | return mmd_data; |
| 901 | } |
| 902 | |
| 903 | static void xgbe_write_mmd_regs(struct xgbe_prv_data *pdata, int prtad, |
| 904 | int mmd_reg, int mmd_data) |
| 905 | { |
| 906 | unsigned int mmd_address; |
| 907 | |
| 908 | if (mmd_reg & MII_ADDR_C45) |
| 909 | mmd_address = mmd_reg & ~MII_ADDR_C45; |
| 910 | else |
| 911 | mmd_address = (pdata->mdio_mmd << 16) | (mmd_reg & 0xffff); |
| 912 | |
| 913 | /* The PCS registers are accessed using mmio. The underlying APB3 |
| 914 | * management interface uses indirect addressing to access the MMD |
| 915 | * register sets. This requires accessing of the PCS register in two |
| 916 | * phases, an address phase and a data phase. |
| 917 | * |
| 918 | * The mmio interface is based on 32-bit offsets and values. All |
| 919 | * register offsets must therefore be adjusted by left shifting the |
| 920 | * offset 2 bits and reading 32 bits of data. |
| 921 | */ |
| 922 | mutex_lock(&pdata->xpcs_mutex); |
| 923 | XPCS_IOWRITE(pdata, PCS_MMD_SELECT << 2, mmd_address >> 8); |
| 924 | XPCS_IOWRITE(pdata, (mmd_address & 0xff) << 2, mmd_data); |
| 925 | mutex_unlock(&pdata->xpcs_mutex); |
| 926 | } |
| 927 | |
| 928 | static int xgbe_tx_complete(struct xgbe_ring_desc *rdesc) |
| 929 | { |
| 930 | return !XGMAC_GET_BITS_LE(rdesc->desc3, TX_NORMAL_DESC3, OWN); |
| 931 | } |
| 932 | |
| 933 | static int xgbe_disable_rx_csum(struct xgbe_prv_data *pdata) |
| 934 | { |
| 935 | XGMAC_IOWRITE_BITS(pdata, MAC_RCR, IPC, 0); |
| 936 | |
| 937 | return 0; |
| 938 | } |
| 939 | |
| 940 | static int xgbe_enable_rx_csum(struct xgbe_prv_data *pdata) |
| 941 | { |
| 942 | XGMAC_IOWRITE_BITS(pdata, MAC_RCR, IPC, 1); |
| 943 | |
| 944 | return 0; |
| 945 | } |
| 946 | |
| 947 | static int xgbe_enable_rx_vlan_stripping(struct xgbe_prv_data *pdata) |
| 948 | { |
| 949 | /* Put the VLAN tag in the Rx descriptor */ |
| 950 | XGMAC_IOWRITE_BITS(pdata, MAC_VLANTR, EVLRXS, 1); |
| 951 | |
| 952 | /* Don't check the VLAN type */ |
| 953 | XGMAC_IOWRITE_BITS(pdata, MAC_VLANTR, DOVLTC, 1); |
| 954 | |
| 955 | /* Check only C-TAG (0x8100) packets */ |
| 956 | XGMAC_IOWRITE_BITS(pdata, MAC_VLANTR, ERSVLM, 0); |
| 957 | |
| 958 | /* Don't consider an S-TAG (0x88A8) packet as a VLAN packet */ |
| 959 | XGMAC_IOWRITE_BITS(pdata, MAC_VLANTR, ESVL, 0); |
| 960 | |
| 961 | /* Enable VLAN tag stripping */ |
| 962 | XGMAC_IOWRITE_BITS(pdata, MAC_VLANTR, EVLS, 0x3); |
| 963 | |
| 964 | return 0; |
| 965 | } |
| 966 | |
| 967 | static int xgbe_disable_rx_vlan_stripping(struct xgbe_prv_data *pdata) |
| 968 | { |
| 969 | XGMAC_IOWRITE_BITS(pdata, MAC_VLANTR, EVLS, 0); |
| 970 | |
| 971 | return 0; |
| 972 | } |
| 973 | |
Lendacky, Thomas | 801c62d | 2014-06-24 16:19:24 -0500 | [diff] [blame] | 974 | static int xgbe_enable_rx_vlan_filtering(struct xgbe_prv_data *pdata) |
| 975 | { |
| 976 | /* Enable VLAN filtering */ |
| 977 | XGMAC_IOWRITE_BITS(pdata, MAC_PFR, VTFE, 1); |
| 978 | |
| 979 | /* Enable VLAN Hash Table filtering */ |
| 980 | XGMAC_IOWRITE_BITS(pdata, MAC_VLANTR, VTHM, 1); |
| 981 | |
| 982 | /* Disable VLAN tag inverse matching */ |
| 983 | XGMAC_IOWRITE_BITS(pdata, MAC_VLANTR, VTIM, 0); |
| 984 | |
| 985 | /* Only filter on the lower 12-bits of the VLAN tag */ |
| 986 | XGMAC_IOWRITE_BITS(pdata, MAC_VLANTR, ETV, 1); |
| 987 | |
| 988 | /* In order for the VLAN Hash Table filtering to be effective, |
| 989 | * the VLAN tag identifier in the VLAN Tag Register must not |
| 990 | * be zero. Set the VLAN tag identifier to "1" to enable the |
| 991 | * VLAN Hash Table filtering. This implies that a VLAN tag of |
| 992 | * 1 will always pass filtering. |
| 993 | */ |
| 994 | XGMAC_IOWRITE_BITS(pdata, MAC_VLANTR, VL, 1); |
| 995 | |
| 996 | return 0; |
| 997 | } |
| 998 | |
| 999 | static int xgbe_disable_rx_vlan_filtering(struct xgbe_prv_data *pdata) |
| 1000 | { |
| 1001 | /* Disable VLAN filtering */ |
| 1002 | XGMAC_IOWRITE_BITS(pdata, MAC_PFR, VTFE, 0); |
| 1003 | |
| 1004 | return 0; |
| 1005 | } |
| 1006 | |
| 1007 | #ifndef CRCPOLY_LE |
| 1008 | #define CRCPOLY_LE 0xedb88320 |
| 1009 | #endif |
| 1010 | static u32 xgbe_vid_crc32_le(__le16 vid_le) |
| 1011 | { |
| 1012 | u32 poly = CRCPOLY_LE; |
| 1013 | u32 crc = ~0; |
| 1014 | u32 temp = 0; |
| 1015 | unsigned char *data = (unsigned char *)&vid_le; |
| 1016 | unsigned char data_byte = 0; |
| 1017 | int i, bits; |
| 1018 | |
| 1019 | bits = get_bitmask_order(VLAN_VID_MASK); |
| 1020 | for (i = 0; i < bits; i++) { |
| 1021 | if ((i % 8) == 0) |
| 1022 | data_byte = data[i / 8]; |
| 1023 | |
| 1024 | temp = ((crc & 1) ^ data_byte) & 1; |
| 1025 | crc >>= 1; |
| 1026 | data_byte >>= 1; |
| 1027 | |
| 1028 | if (temp) |
| 1029 | crc ^= poly; |
| 1030 | } |
| 1031 | |
| 1032 | return crc; |
| 1033 | } |
| 1034 | |
| 1035 | static int xgbe_update_vlan_hash_table(struct xgbe_prv_data *pdata) |
| 1036 | { |
| 1037 | u32 crc; |
| 1038 | u16 vid; |
| 1039 | __le16 vid_le; |
| 1040 | u16 vlan_hash_table = 0; |
| 1041 | |
| 1042 | /* Generate the VLAN Hash Table value */ |
| 1043 | for_each_set_bit(vid, pdata->active_vlans, VLAN_N_VID) { |
| 1044 | /* Get the CRC32 value of the VLAN ID */ |
| 1045 | vid_le = cpu_to_le16(vid); |
| 1046 | crc = bitrev32(~xgbe_vid_crc32_le(vid_le)) >> 28; |
| 1047 | |
| 1048 | vlan_hash_table |= (1 << crc); |
| 1049 | } |
| 1050 | |
| 1051 | /* Set the VLAN Hash Table filtering register */ |
| 1052 | XGMAC_IOWRITE_BITS(pdata, MAC_VLANHTR, VLHT, vlan_hash_table); |
| 1053 | |
| 1054 | return 0; |
| 1055 | } |
| 1056 | |
Lendacky, Thomas | c5aa9e3 | 2014-06-05 09:15:06 -0500 | [diff] [blame] | 1057 | static void xgbe_tx_desc_reset(struct xgbe_ring_data *rdata) |
| 1058 | { |
| 1059 | struct xgbe_ring_desc *rdesc = rdata->rdesc; |
| 1060 | |
| 1061 | /* Reset the Tx descriptor |
| 1062 | * Set buffer 1 (lo) address to zero |
| 1063 | * Set buffer 1 (hi) address to zero |
| 1064 | * Reset all other control bits (IC, TTSE, B2L & B1L) |
| 1065 | * Reset all other control bits (OWN, CTXT, FD, LD, CPC, CIC, etc) |
| 1066 | */ |
| 1067 | rdesc->desc0 = 0; |
| 1068 | rdesc->desc1 = 0; |
| 1069 | rdesc->desc2 = 0; |
| 1070 | rdesc->desc3 = 0; |
Lendacky, Thomas | 08dcc47 | 2014-11-04 16:06:44 -0600 | [diff] [blame] | 1071 | |
| 1072 | /* Make sure ownership is written to the descriptor */ |
Lendacky, Thomas | ceb8f6b | 2015-03-20 11:50:16 -0500 | [diff] [blame] | 1073 | dma_wmb(); |
Lendacky, Thomas | c5aa9e3 | 2014-06-05 09:15:06 -0500 | [diff] [blame] | 1074 | } |
| 1075 | |
| 1076 | static void xgbe_tx_desc_init(struct xgbe_channel *channel) |
| 1077 | { |
| 1078 | struct xgbe_ring *ring = channel->tx_ring; |
| 1079 | struct xgbe_ring_data *rdata; |
Lendacky, Thomas | c5aa9e3 | 2014-06-05 09:15:06 -0500 | [diff] [blame] | 1080 | int i; |
| 1081 | int start_index = ring->cur; |
| 1082 | |
| 1083 | DBGPR("-->tx_desc_init\n"); |
| 1084 | |
| 1085 | /* Initialze all descriptors */ |
| 1086 | for (i = 0; i < ring->rdesc_count; i++) { |
Lendacky, Thomas | d0a8ba6 | 2014-06-24 16:19:06 -0500 | [diff] [blame] | 1087 | rdata = XGBE_GET_DESC_DATA(ring, i); |
Lendacky, Thomas | c5aa9e3 | 2014-06-05 09:15:06 -0500 | [diff] [blame] | 1088 | |
Lendacky, Thomas | 08dcc47 | 2014-11-04 16:06:44 -0600 | [diff] [blame] | 1089 | /* Initialize Tx descriptor */ |
| 1090 | xgbe_tx_desc_reset(rdata); |
Lendacky, Thomas | c5aa9e3 | 2014-06-05 09:15:06 -0500 | [diff] [blame] | 1091 | } |
| 1092 | |
Lendacky, Thomas | c5aa9e3 | 2014-06-05 09:15:06 -0500 | [diff] [blame] | 1093 | /* Update the total number of Tx descriptors */ |
| 1094 | XGMAC_DMA_IOWRITE(channel, DMA_CH_TDRLR, ring->rdesc_count - 1); |
| 1095 | |
| 1096 | /* Update the starting address of descriptor ring */ |
Lendacky, Thomas | d0a8ba6 | 2014-06-24 16:19:06 -0500 | [diff] [blame] | 1097 | rdata = XGBE_GET_DESC_DATA(ring, start_index); |
Lendacky, Thomas | c5aa9e3 | 2014-06-05 09:15:06 -0500 | [diff] [blame] | 1098 | XGMAC_DMA_IOWRITE(channel, DMA_CH_TDLR_HI, |
| 1099 | upper_32_bits(rdata->rdesc_dma)); |
| 1100 | XGMAC_DMA_IOWRITE(channel, DMA_CH_TDLR_LO, |
| 1101 | lower_32_bits(rdata->rdesc_dma)); |
| 1102 | |
| 1103 | DBGPR("<--tx_desc_init\n"); |
| 1104 | } |
| 1105 | |
Lendacky, Thomas | 8dee19e | 2015-04-09 12:11:51 -0500 | [diff] [blame] | 1106 | static void xgbe_rx_desc_reset(struct xgbe_prv_data *pdata, |
| 1107 | struct xgbe_ring_data *rdata, unsigned int index) |
Lendacky, Thomas | c5aa9e3 | 2014-06-05 09:15:06 -0500 | [diff] [blame] | 1108 | { |
| 1109 | struct xgbe_ring_desc *rdesc = rdata->rdesc; |
Lendacky, Thomas | 8dee19e | 2015-04-09 12:11:51 -0500 | [diff] [blame] | 1110 | unsigned int rx_usecs = pdata->rx_usecs; |
| 1111 | unsigned int rx_frames = pdata->rx_frames; |
| 1112 | unsigned int inte; |
Lendacky, Thomas | cfbfd86 | 2015-07-06 11:57:37 -0500 | [diff] [blame] | 1113 | dma_addr_t hdr_dma, buf_dma; |
Lendacky, Thomas | 8dee19e | 2015-04-09 12:11:51 -0500 | [diff] [blame] | 1114 | |
| 1115 | if (!rx_usecs && !rx_frames) { |
| 1116 | /* No coalescing, interrupt for every descriptor */ |
| 1117 | inte = 1; |
| 1118 | } else { |
| 1119 | /* Set interrupt based on Rx frame coalescing setting */ |
| 1120 | if (rx_frames && !((index + 1) % rx_frames)) |
| 1121 | inte = 1; |
| 1122 | else |
| 1123 | inte = 0; |
| 1124 | } |
Lendacky, Thomas | c5aa9e3 | 2014-06-05 09:15:06 -0500 | [diff] [blame] | 1125 | |
| 1126 | /* Reset the Rx descriptor |
Lendacky, Thomas | 174fd25 | 2014-11-04 16:06:50 -0600 | [diff] [blame] | 1127 | * Set buffer 1 (lo) address to header dma address (lo) |
| 1128 | * Set buffer 1 (hi) address to header dma address (hi) |
| 1129 | * Set buffer 2 (lo) address to buffer dma address (lo) |
| 1130 | * Set buffer 2 (hi) address to buffer dma address (hi) and |
| 1131 | * set control bits OWN and INTE |
Lendacky, Thomas | c5aa9e3 | 2014-06-05 09:15:06 -0500 | [diff] [blame] | 1132 | */ |
Lendacky, Thomas | cfbfd86 | 2015-07-06 11:57:37 -0500 | [diff] [blame] | 1133 | hdr_dma = rdata->rx.hdr.dma_base + rdata->rx.hdr.dma_off; |
| 1134 | buf_dma = rdata->rx.buf.dma_base + rdata->rx.buf.dma_off; |
| 1135 | rdesc->desc0 = cpu_to_le32(lower_32_bits(hdr_dma)); |
| 1136 | rdesc->desc1 = cpu_to_le32(upper_32_bits(hdr_dma)); |
| 1137 | rdesc->desc2 = cpu_to_le32(lower_32_bits(buf_dma)); |
| 1138 | rdesc->desc3 = cpu_to_le32(upper_32_bits(buf_dma)); |
Lendacky, Thomas | c5aa9e3 | 2014-06-05 09:15:06 -0500 | [diff] [blame] | 1139 | |
Lendacky, Thomas | 8dee19e | 2015-04-09 12:11:51 -0500 | [diff] [blame] | 1140 | XGMAC_SET_BITS_LE(rdesc->desc3, RX_NORMAL_DESC3, INTE, inte); |
Lendacky, Thomas | c5aa9e3 | 2014-06-05 09:15:06 -0500 | [diff] [blame] | 1141 | |
| 1142 | /* Since the Rx DMA engine is likely running, make sure everything |
| 1143 | * is written to the descriptor(s) before setting the OWN bit |
| 1144 | * for the descriptor |
| 1145 | */ |
Lendacky, Thomas | ceb8f6b | 2015-03-20 11:50:16 -0500 | [diff] [blame] | 1146 | dma_wmb(); |
Lendacky, Thomas | c5aa9e3 | 2014-06-05 09:15:06 -0500 | [diff] [blame] | 1147 | |
| 1148 | XGMAC_SET_BITS_LE(rdesc->desc3, RX_NORMAL_DESC3, OWN, 1); |
| 1149 | |
| 1150 | /* Make sure ownership is written to the descriptor */ |
Lendacky, Thomas | ceb8f6b | 2015-03-20 11:50:16 -0500 | [diff] [blame] | 1151 | dma_wmb(); |
Lendacky, Thomas | c5aa9e3 | 2014-06-05 09:15:06 -0500 | [diff] [blame] | 1152 | } |
| 1153 | |
| 1154 | static void xgbe_rx_desc_init(struct xgbe_channel *channel) |
| 1155 | { |
| 1156 | struct xgbe_prv_data *pdata = channel->pdata; |
| 1157 | struct xgbe_ring *ring = channel->rx_ring; |
| 1158 | struct xgbe_ring_data *rdata; |
Lendacky, Thomas | c5aa9e3 | 2014-06-05 09:15:06 -0500 | [diff] [blame] | 1159 | unsigned int start_index = ring->cur; |
Lendacky, Thomas | c5aa9e3 | 2014-06-05 09:15:06 -0500 | [diff] [blame] | 1160 | unsigned int i; |
| 1161 | |
| 1162 | DBGPR("-->rx_desc_init\n"); |
| 1163 | |
Lendacky, Thomas | c5aa9e3 | 2014-06-05 09:15:06 -0500 | [diff] [blame] | 1164 | /* Initialize all descriptors */ |
| 1165 | for (i = 0; i < ring->rdesc_count; i++) { |
Lendacky, Thomas | d0a8ba6 | 2014-06-24 16:19:06 -0500 | [diff] [blame] | 1166 | rdata = XGBE_GET_DESC_DATA(ring, i); |
Lendacky, Thomas | c5aa9e3 | 2014-06-05 09:15:06 -0500 | [diff] [blame] | 1167 | |
Lendacky, Thomas | 08dcc47 | 2014-11-04 16:06:44 -0600 | [diff] [blame] | 1168 | /* Initialize Rx descriptor */ |
Lendacky, Thomas | 8dee19e | 2015-04-09 12:11:51 -0500 | [diff] [blame] | 1169 | xgbe_rx_desc_reset(pdata, rdata, i); |
Lendacky, Thomas | 08dcc47 | 2014-11-04 16:06:44 -0600 | [diff] [blame] | 1170 | } |
Lendacky, Thomas | c5aa9e3 | 2014-06-05 09:15:06 -0500 | [diff] [blame] | 1171 | |
| 1172 | /* Update the total number of Rx descriptors */ |
| 1173 | XGMAC_DMA_IOWRITE(channel, DMA_CH_RDRLR, ring->rdesc_count - 1); |
| 1174 | |
| 1175 | /* Update the starting address of descriptor ring */ |
Lendacky, Thomas | d0a8ba6 | 2014-06-24 16:19:06 -0500 | [diff] [blame] | 1176 | rdata = XGBE_GET_DESC_DATA(ring, start_index); |
Lendacky, Thomas | c5aa9e3 | 2014-06-05 09:15:06 -0500 | [diff] [blame] | 1177 | XGMAC_DMA_IOWRITE(channel, DMA_CH_RDLR_HI, |
| 1178 | upper_32_bits(rdata->rdesc_dma)); |
| 1179 | XGMAC_DMA_IOWRITE(channel, DMA_CH_RDLR_LO, |
| 1180 | lower_32_bits(rdata->rdesc_dma)); |
| 1181 | |
| 1182 | /* Update the Rx Descriptor Tail Pointer */ |
Lendacky, Thomas | d0a8ba6 | 2014-06-24 16:19:06 -0500 | [diff] [blame] | 1183 | rdata = XGBE_GET_DESC_DATA(ring, start_index + ring->rdesc_count - 1); |
Lendacky, Thomas | c5aa9e3 | 2014-06-05 09:15:06 -0500 | [diff] [blame] | 1184 | XGMAC_DMA_IOWRITE(channel, DMA_CH_RDTR_LO, |
| 1185 | lower_32_bits(rdata->rdesc_dma)); |
| 1186 | |
| 1187 | DBGPR("<--rx_desc_init\n"); |
| 1188 | } |
| 1189 | |
Lendacky, Thomas | 23e4eef | 2014-07-29 08:57:19 -0500 | [diff] [blame] | 1190 | static void xgbe_update_tstamp_addend(struct xgbe_prv_data *pdata, |
| 1191 | unsigned int addend) |
| 1192 | { |
| 1193 | /* Set the addend register value and tell the device */ |
| 1194 | XGMAC_IOWRITE(pdata, MAC_TSAR, addend); |
| 1195 | XGMAC_IOWRITE_BITS(pdata, MAC_TSCR, TSADDREG, 1); |
| 1196 | |
| 1197 | /* Wait for addend update to complete */ |
| 1198 | while (XGMAC_IOREAD_BITS(pdata, MAC_TSCR, TSADDREG)) |
| 1199 | udelay(5); |
| 1200 | } |
| 1201 | |
| 1202 | static void xgbe_set_tstamp_time(struct xgbe_prv_data *pdata, unsigned int sec, |
| 1203 | unsigned int nsec) |
| 1204 | { |
| 1205 | /* Set the time values and tell the device */ |
| 1206 | XGMAC_IOWRITE(pdata, MAC_STSUR, sec); |
| 1207 | XGMAC_IOWRITE(pdata, MAC_STNUR, nsec); |
| 1208 | XGMAC_IOWRITE_BITS(pdata, MAC_TSCR, TSINIT, 1); |
| 1209 | |
| 1210 | /* Wait for time update to complete */ |
| 1211 | while (XGMAC_IOREAD_BITS(pdata, MAC_TSCR, TSINIT)) |
| 1212 | udelay(5); |
| 1213 | } |
| 1214 | |
| 1215 | static u64 xgbe_get_tstamp_time(struct xgbe_prv_data *pdata) |
| 1216 | { |
| 1217 | u64 nsec; |
| 1218 | |
| 1219 | nsec = XGMAC_IOREAD(pdata, MAC_STSR); |
| 1220 | nsec *= NSEC_PER_SEC; |
| 1221 | nsec += XGMAC_IOREAD(pdata, MAC_STNR); |
| 1222 | |
| 1223 | return nsec; |
| 1224 | } |
| 1225 | |
| 1226 | static u64 xgbe_get_tx_tstamp(struct xgbe_prv_data *pdata) |
| 1227 | { |
| 1228 | unsigned int tx_snr; |
| 1229 | u64 nsec; |
| 1230 | |
| 1231 | tx_snr = XGMAC_IOREAD(pdata, MAC_TXSNR); |
| 1232 | if (XGMAC_GET_BITS(tx_snr, MAC_TXSNR, TXTSSTSMIS)) |
| 1233 | return 0; |
| 1234 | |
| 1235 | nsec = XGMAC_IOREAD(pdata, MAC_TXSSR); |
| 1236 | nsec *= NSEC_PER_SEC; |
| 1237 | nsec += tx_snr; |
| 1238 | |
| 1239 | return nsec; |
| 1240 | } |
| 1241 | |
| 1242 | static void xgbe_get_rx_tstamp(struct xgbe_packet_data *packet, |
| 1243 | struct xgbe_ring_desc *rdesc) |
| 1244 | { |
| 1245 | u64 nsec; |
| 1246 | |
| 1247 | if (XGMAC_GET_BITS_LE(rdesc->desc3, RX_CONTEXT_DESC3, TSA) && |
| 1248 | !XGMAC_GET_BITS_LE(rdesc->desc3, RX_CONTEXT_DESC3, TSD)) { |
| 1249 | nsec = le32_to_cpu(rdesc->desc1); |
| 1250 | nsec <<= 32; |
| 1251 | nsec |= le32_to_cpu(rdesc->desc0); |
| 1252 | if (nsec != 0xffffffffffffffffULL) { |
| 1253 | packet->rx_tstamp = nsec; |
| 1254 | XGMAC_SET_BITS(packet->attributes, RX_PACKET_ATTRIBUTES, |
| 1255 | RX_TSTAMP, 1); |
| 1256 | } |
| 1257 | } |
| 1258 | } |
| 1259 | |
| 1260 | static int xgbe_config_tstamp(struct xgbe_prv_data *pdata, |
| 1261 | unsigned int mac_tscr) |
| 1262 | { |
| 1263 | /* Set one nano-second accuracy */ |
| 1264 | XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSCTRLSSR, 1); |
| 1265 | |
| 1266 | /* Set fine timestamp update */ |
| 1267 | XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSCFUPDT, 1); |
| 1268 | |
| 1269 | /* Overwrite earlier timestamps */ |
| 1270 | XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TXTSSTSM, 1); |
| 1271 | |
| 1272 | XGMAC_IOWRITE(pdata, MAC_TSCR, mac_tscr); |
| 1273 | |
| 1274 | /* Exit if timestamping is not enabled */ |
| 1275 | if (!XGMAC_GET_BITS(mac_tscr, MAC_TSCR, TSENA)) |
| 1276 | return 0; |
| 1277 | |
| 1278 | /* Initialize time registers */ |
| 1279 | XGMAC_IOWRITE_BITS(pdata, MAC_SSIR, SSINC, XGBE_TSTAMP_SSINC); |
| 1280 | XGMAC_IOWRITE_BITS(pdata, MAC_SSIR, SNSINC, XGBE_TSTAMP_SNSINC); |
| 1281 | xgbe_update_tstamp_addend(pdata, pdata->tstamp_addend); |
| 1282 | xgbe_set_tstamp_time(pdata, 0, 0); |
| 1283 | |
| 1284 | /* Initialize the timecounter */ |
| 1285 | timecounter_init(&pdata->tstamp_tc, &pdata->tstamp_cc, |
| 1286 | ktime_to_ns(ktime_get_real())); |
| 1287 | |
| 1288 | return 0; |
| 1289 | } |
| 1290 | |
Lendacky, Thomas | fca2d99 | 2014-07-29 08:57:55 -0500 | [diff] [blame] | 1291 | static void xgbe_config_dcb_tc(struct xgbe_prv_data *pdata) |
| 1292 | { |
| 1293 | struct ieee_ets *ets = pdata->ets; |
| 1294 | unsigned int total_weight, min_weight, weight; |
| 1295 | unsigned int i; |
| 1296 | |
| 1297 | if (!ets) |
| 1298 | return; |
| 1299 | |
| 1300 | /* Set Tx to deficit weighted round robin scheduling algorithm (when |
| 1301 | * traffic class is using ETS algorithm) |
| 1302 | */ |
| 1303 | XGMAC_IOWRITE_BITS(pdata, MTL_OMR, ETSALG, MTL_ETSALG_DWRR); |
| 1304 | |
| 1305 | /* Set Traffic Class algorithms */ |
| 1306 | total_weight = pdata->netdev->mtu * pdata->hw_feat.tc_cnt; |
| 1307 | min_weight = total_weight / 100; |
| 1308 | if (!min_weight) |
| 1309 | min_weight = 1; |
| 1310 | |
| 1311 | for (i = 0; i < pdata->hw_feat.tc_cnt; i++) { |
| 1312 | switch (ets->tc_tsa[i]) { |
| 1313 | case IEEE_8021QAZ_TSA_STRICT: |
Lendacky, Thomas | 34bf65d | 2015-05-14 11:44:03 -0500 | [diff] [blame] | 1314 | netif_dbg(pdata, drv, pdata->netdev, |
| 1315 | "TC%u using SP\n", i); |
Lendacky, Thomas | fca2d99 | 2014-07-29 08:57:55 -0500 | [diff] [blame] | 1316 | XGMAC_MTL_IOWRITE_BITS(pdata, i, MTL_TC_ETSCR, TSA, |
| 1317 | MTL_TSA_SP); |
| 1318 | break; |
| 1319 | case IEEE_8021QAZ_TSA_ETS: |
| 1320 | weight = total_weight * ets->tc_tx_bw[i] / 100; |
| 1321 | weight = clamp(weight, min_weight, total_weight); |
| 1322 | |
Lendacky, Thomas | 34bf65d | 2015-05-14 11:44:03 -0500 | [diff] [blame] | 1323 | netif_dbg(pdata, drv, pdata->netdev, |
| 1324 | "TC%u using DWRR (weight %u)\n", i, weight); |
Lendacky, Thomas | fca2d99 | 2014-07-29 08:57:55 -0500 | [diff] [blame] | 1325 | XGMAC_MTL_IOWRITE_BITS(pdata, i, MTL_TC_ETSCR, TSA, |
| 1326 | MTL_TSA_ETS); |
| 1327 | XGMAC_MTL_IOWRITE_BITS(pdata, i, MTL_TC_QWR, QW, |
| 1328 | weight); |
| 1329 | break; |
| 1330 | } |
| 1331 | } |
| 1332 | } |
| 1333 | |
| 1334 | static void xgbe_config_dcb_pfc(struct xgbe_prv_data *pdata) |
| 1335 | { |
| 1336 | struct ieee_pfc *pfc = pdata->pfc; |
| 1337 | struct ieee_ets *ets = pdata->ets; |
| 1338 | unsigned int mask, reg, reg_val; |
| 1339 | unsigned int tc, prio; |
| 1340 | |
| 1341 | if (!pfc || !ets) |
| 1342 | return; |
| 1343 | |
| 1344 | for (tc = 0; tc < pdata->hw_feat.tc_cnt; tc++) { |
| 1345 | mask = 0; |
| 1346 | for (prio = 0; prio < IEEE_8021QAZ_MAX_TCS; prio++) { |
| 1347 | if ((pfc->pfc_en & (1 << prio)) && |
| 1348 | (ets->prio_tc[prio] == tc)) |
| 1349 | mask |= (1 << prio); |
| 1350 | } |
| 1351 | mask &= 0xff; |
| 1352 | |
Lendacky, Thomas | 34bf65d | 2015-05-14 11:44:03 -0500 | [diff] [blame] | 1353 | netif_dbg(pdata, drv, pdata->netdev, "TC%u PFC mask=%#x\n", |
| 1354 | tc, mask); |
Lendacky, Thomas | fca2d99 | 2014-07-29 08:57:55 -0500 | [diff] [blame] | 1355 | reg = MTL_TCPM0R + (MTL_TCPM_INC * (tc / MTL_TCPM_TC_PER_REG)); |
| 1356 | reg_val = XGMAC_IOREAD(pdata, reg); |
| 1357 | |
| 1358 | reg_val &= ~(0xff << ((tc % MTL_TCPM_TC_PER_REG) << 3)); |
| 1359 | reg_val |= (mask << ((tc % MTL_TCPM_TC_PER_REG) << 3)); |
| 1360 | |
| 1361 | XGMAC_IOWRITE(pdata, reg, reg_val); |
| 1362 | } |
| 1363 | |
| 1364 | xgbe_config_flow_control(pdata); |
| 1365 | } |
| 1366 | |
Lendacky, Thomas | 16958a2 | 2014-11-20 11:04:08 -0600 | [diff] [blame] | 1367 | static void xgbe_tx_start_xmit(struct xgbe_channel *channel, |
| 1368 | struct xgbe_ring *ring) |
| 1369 | { |
| 1370 | struct xgbe_prv_data *pdata = channel->pdata; |
| 1371 | struct xgbe_ring_data *rdata; |
| 1372 | |
Lendacky, Thomas | ceb8f6b | 2015-03-20 11:50:16 -0500 | [diff] [blame] | 1373 | /* Make sure everything is written before the register write */ |
| 1374 | wmb(); |
| 1375 | |
Lendacky, Thomas | 16958a2 | 2014-11-20 11:04:08 -0600 | [diff] [blame] | 1376 | /* Issue a poll command to Tx DMA by writing address |
| 1377 | * of next immediate free descriptor */ |
| 1378 | rdata = XGBE_GET_DESC_DATA(ring, ring->cur); |
| 1379 | XGMAC_DMA_IOWRITE(channel, DMA_CH_TDTR_LO, |
| 1380 | lower_32_bits(rdata->rdesc_dma)); |
| 1381 | |
Lendacky, Thomas | c635eaa | 2015-03-20 11:50:28 -0500 | [diff] [blame] | 1382 | /* Start the Tx timer */ |
Lendacky, Thomas | 16958a2 | 2014-11-20 11:04:08 -0600 | [diff] [blame] | 1383 | if (pdata->tx_usecs && !channel->tx_timer_active) { |
| 1384 | channel->tx_timer_active = 1; |
Lendacky, Thomas | c635eaa | 2015-03-20 11:50:28 -0500 | [diff] [blame] | 1385 | mod_timer(&channel->tx_timer, |
| 1386 | jiffies + usecs_to_jiffies(pdata->tx_usecs)); |
Lendacky, Thomas | 16958a2 | 2014-11-20 11:04:08 -0600 | [diff] [blame] | 1387 | } |
| 1388 | |
| 1389 | ring->tx.xmit_more = 0; |
| 1390 | } |
| 1391 | |
Lendacky, Thomas | a9d4198 | 2014-11-04 16:06:32 -0600 | [diff] [blame] | 1392 | static void xgbe_dev_xmit(struct xgbe_channel *channel) |
Lendacky, Thomas | c5aa9e3 | 2014-06-05 09:15:06 -0500 | [diff] [blame] | 1393 | { |
| 1394 | struct xgbe_prv_data *pdata = channel->pdata; |
| 1395 | struct xgbe_ring *ring = channel->tx_ring; |
| 1396 | struct xgbe_ring_data *rdata; |
| 1397 | struct xgbe_ring_desc *rdesc; |
| 1398 | struct xgbe_packet_data *packet = &ring->packet_data; |
| 1399 | unsigned int csum, tso, vlan; |
| 1400 | unsigned int tso_context, vlan_context; |
Lendacky, Thomas | eb79e64 | 2014-11-20 11:04:02 -0600 | [diff] [blame] | 1401 | unsigned int tx_set_ic; |
Lendacky, Thomas | c5aa9e3 | 2014-06-05 09:15:06 -0500 | [diff] [blame] | 1402 | int start_index = ring->cur; |
Lendacky, Thomas | a83ef42 | 2015-01-16 12:46:55 -0600 | [diff] [blame] | 1403 | int cur_index = ring->cur; |
Lendacky, Thomas | c5aa9e3 | 2014-06-05 09:15:06 -0500 | [diff] [blame] | 1404 | int i; |
| 1405 | |
Lendacky, Thomas | a9d4198 | 2014-11-04 16:06:32 -0600 | [diff] [blame] | 1406 | DBGPR("-->xgbe_dev_xmit\n"); |
Lendacky, Thomas | c5aa9e3 | 2014-06-05 09:15:06 -0500 | [diff] [blame] | 1407 | |
| 1408 | csum = XGMAC_GET_BITS(packet->attributes, TX_PACKET_ATTRIBUTES, |
| 1409 | CSUM_ENABLE); |
| 1410 | tso = XGMAC_GET_BITS(packet->attributes, TX_PACKET_ATTRIBUTES, |
| 1411 | TSO_ENABLE); |
| 1412 | vlan = XGMAC_GET_BITS(packet->attributes, TX_PACKET_ATTRIBUTES, |
| 1413 | VLAN_CTAG); |
| 1414 | |
| 1415 | if (tso && (packet->mss != ring->tx.cur_mss)) |
| 1416 | tso_context = 1; |
| 1417 | else |
| 1418 | tso_context = 0; |
| 1419 | |
| 1420 | if (vlan && (packet->vlan_ctag != ring->tx.cur_vlan_ctag)) |
| 1421 | vlan_context = 1; |
| 1422 | else |
| 1423 | vlan_context = 0; |
| 1424 | |
Lendacky, Thomas | eb79e64 | 2014-11-20 11:04:02 -0600 | [diff] [blame] | 1425 | /* Determine if an interrupt should be generated for this Tx: |
| 1426 | * Interrupt: |
| 1427 | * - Tx frame count exceeds the frame count setting |
| 1428 | * - Addition of Tx frame count to the frame count since the |
| 1429 | * last interrupt was set exceeds the frame count setting |
| 1430 | * No interrupt: |
| 1431 | * - No frame count setting specified (ethtool -C ethX tx-frames 0) |
| 1432 | * - Addition of Tx frame count to the frame count since the |
| 1433 | * last interrupt was set does not exceed the frame count setting |
| 1434 | */ |
| 1435 | ring->coalesce_count += packet->tx_packets; |
| 1436 | if (!pdata->tx_frames) |
| 1437 | tx_set_ic = 0; |
| 1438 | else if (packet->tx_packets > pdata->tx_frames) |
| 1439 | tx_set_ic = 1; |
| 1440 | else if ((ring->coalesce_count % pdata->tx_frames) < |
| 1441 | packet->tx_packets) |
| 1442 | tx_set_ic = 1; |
| 1443 | else |
| 1444 | tx_set_ic = 0; |
Lendacky, Thomas | c5aa9e3 | 2014-06-05 09:15:06 -0500 | [diff] [blame] | 1445 | |
Lendacky, Thomas | a83ef42 | 2015-01-16 12:46:55 -0600 | [diff] [blame] | 1446 | rdata = XGBE_GET_DESC_DATA(ring, cur_index); |
Lendacky, Thomas | c5aa9e3 | 2014-06-05 09:15:06 -0500 | [diff] [blame] | 1447 | rdesc = rdata->rdesc; |
| 1448 | |
| 1449 | /* Create a context descriptor if this is a TSO packet */ |
| 1450 | if (tso_context || vlan_context) { |
| 1451 | if (tso_context) { |
Lendacky, Thomas | 34bf65d | 2015-05-14 11:44:03 -0500 | [diff] [blame] | 1452 | netif_dbg(pdata, tx_queued, pdata->netdev, |
| 1453 | "TSO context descriptor, mss=%u\n", |
| 1454 | packet->mss); |
Lendacky, Thomas | c5aa9e3 | 2014-06-05 09:15:06 -0500 | [diff] [blame] | 1455 | |
| 1456 | /* Set the MSS size */ |
| 1457 | XGMAC_SET_BITS_LE(rdesc->desc2, TX_CONTEXT_DESC2, |
| 1458 | MSS, packet->mss); |
| 1459 | |
| 1460 | /* Mark it as a CONTEXT descriptor */ |
| 1461 | XGMAC_SET_BITS_LE(rdesc->desc3, TX_CONTEXT_DESC3, |
| 1462 | CTXT, 1); |
| 1463 | |
| 1464 | /* Indicate this descriptor contains the MSS */ |
| 1465 | XGMAC_SET_BITS_LE(rdesc->desc3, TX_CONTEXT_DESC3, |
| 1466 | TCMSSV, 1); |
| 1467 | |
| 1468 | ring->tx.cur_mss = packet->mss; |
| 1469 | } |
| 1470 | |
| 1471 | if (vlan_context) { |
Lendacky, Thomas | 34bf65d | 2015-05-14 11:44:03 -0500 | [diff] [blame] | 1472 | netif_dbg(pdata, tx_queued, pdata->netdev, |
| 1473 | "VLAN context descriptor, ctag=%u\n", |
| 1474 | packet->vlan_ctag); |
Lendacky, Thomas | c5aa9e3 | 2014-06-05 09:15:06 -0500 | [diff] [blame] | 1475 | |
| 1476 | /* Mark it as a CONTEXT descriptor */ |
| 1477 | XGMAC_SET_BITS_LE(rdesc->desc3, TX_CONTEXT_DESC3, |
| 1478 | CTXT, 1); |
| 1479 | |
| 1480 | /* Set the VLAN tag */ |
| 1481 | XGMAC_SET_BITS_LE(rdesc->desc3, TX_CONTEXT_DESC3, |
| 1482 | VT, packet->vlan_ctag); |
| 1483 | |
| 1484 | /* Indicate this descriptor contains the VLAN tag */ |
| 1485 | XGMAC_SET_BITS_LE(rdesc->desc3, TX_CONTEXT_DESC3, |
| 1486 | VLTV, 1); |
| 1487 | |
| 1488 | ring->tx.cur_vlan_ctag = packet->vlan_ctag; |
| 1489 | } |
| 1490 | |
Lendacky, Thomas | a83ef42 | 2015-01-16 12:46:55 -0600 | [diff] [blame] | 1491 | cur_index++; |
| 1492 | rdata = XGBE_GET_DESC_DATA(ring, cur_index); |
Lendacky, Thomas | c5aa9e3 | 2014-06-05 09:15:06 -0500 | [diff] [blame] | 1493 | rdesc = rdata->rdesc; |
| 1494 | } |
| 1495 | |
| 1496 | /* Update buffer address (for TSO this is the header) */ |
| 1497 | rdesc->desc0 = cpu_to_le32(lower_32_bits(rdata->skb_dma)); |
| 1498 | rdesc->desc1 = cpu_to_le32(upper_32_bits(rdata->skb_dma)); |
| 1499 | |
| 1500 | /* Update the buffer length */ |
| 1501 | XGMAC_SET_BITS_LE(rdesc->desc2, TX_NORMAL_DESC2, HL_B1L, |
| 1502 | rdata->skb_dma_len); |
| 1503 | |
| 1504 | /* VLAN tag insertion check */ |
| 1505 | if (vlan) |
| 1506 | XGMAC_SET_BITS_LE(rdesc->desc2, TX_NORMAL_DESC2, VTIR, |
| 1507 | TX_NORMAL_DESC2_VLAN_INSERT); |
| 1508 | |
Lendacky, Thomas | 23e4eef | 2014-07-29 08:57:19 -0500 | [diff] [blame] | 1509 | /* Timestamp enablement check */ |
| 1510 | if (XGMAC_GET_BITS(packet->attributes, TX_PACKET_ATTRIBUTES, PTP)) |
| 1511 | XGMAC_SET_BITS_LE(rdesc->desc2, TX_NORMAL_DESC2, TTSE, 1); |
| 1512 | |
Lendacky, Thomas | c5aa9e3 | 2014-06-05 09:15:06 -0500 | [diff] [blame] | 1513 | /* Mark it as First Descriptor */ |
| 1514 | XGMAC_SET_BITS_LE(rdesc->desc3, TX_NORMAL_DESC3, FD, 1); |
| 1515 | |
| 1516 | /* Mark it as a NORMAL descriptor */ |
| 1517 | XGMAC_SET_BITS_LE(rdesc->desc3, TX_NORMAL_DESC3, CTXT, 0); |
| 1518 | |
| 1519 | /* Set OWN bit if not the first descriptor */ |
Lendacky, Thomas | a83ef42 | 2015-01-16 12:46:55 -0600 | [diff] [blame] | 1520 | if (cur_index != start_index) |
Lendacky, Thomas | c5aa9e3 | 2014-06-05 09:15:06 -0500 | [diff] [blame] | 1521 | XGMAC_SET_BITS_LE(rdesc->desc3, TX_NORMAL_DESC3, OWN, 1); |
| 1522 | |
| 1523 | if (tso) { |
| 1524 | /* Enable TSO */ |
| 1525 | XGMAC_SET_BITS_LE(rdesc->desc3, TX_NORMAL_DESC3, TSE, 1); |
| 1526 | XGMAC_SET_BITS_LE(rdesc->desc3, TX_NORMAL_DESC3, TCPPL, |
| 1527 | packet->tcp_payload_len); |
| 1528 | XGMAC_SET_BITS_LE(rdesc->desc3, TX_NORMAL_DESC3, TCPHDRLEN, |
| 1529 | packet->tcp_header_len / 4); |
Lendacky, Thomas | 5452b2d | 2015-05-14 11:43:57 -0500 | [diff] [blame] | 1530 | |
| 1531 | pdata->ext_stats.tx_tso_packets++; |
Lendacky, Thomas | c5aa9e3 | 2014-06-05 09:15:06 -0500 | [diff] [blame] | 1532 | } else { |
| 1533 | /* Enable CRC and Pad Insertion */ |
| 1534 | XGMAC_SET_BITS_LE(rdesc->desc3, TX_NORMAL_DESC3, CPC, 0); |
| 1535 | |
| 1536 | /* Enable HW CSUM */ |
| 1537 | if (csum) |
| 1538 | XGMAC_SET_BITS_LE(rdesc->desc3, TX_NORMAL_DESC3, |
| 1539 | CIC, 0x3); |
| 1540 | |
| 1541 | /* Set the total length to be transmitted */ |
| 1542 | XGMAC_SET_BITS_LE(rdesc->desc3, TX_NORMAL_DESC3, FL, |
| 1543 | packet->length); |
| 1544 | } |
| 1545 | |
Lendacky, Thomas | a83ef42 | 2015-01-16 12:46:55 -0600 | [diff] [blame] | 1546 | for (i = cur_index - start_index + 1; i < packet->rdesc_count; i++) { |
| 1547 | cur_index++; |
| 1548 | rdata = XGBE_GET_DESC_DATA(ring, cur_index); |
Lendacky, Thomas | c5aa9e3 | 2014-06-05 09:15:06 -0500 | [diff] [blame] | 1549 | rdesc = rdata->rdesc; |
| 1550 | |
| 1551 | /* Update buffer address */ |
| 1552 | rdesc->desc0 = cpu_to_le32(lower_32_bits(rdata->skb_dma)); |
| 1553 | rdesc->desc1 = cpu_to_le32(upper_32_bits(rdata->skb_dma)); |
| 1554 | |
| 1555 | /* Update the buffer length */ |
| 1556 | XGMAC_SET_BITS_LE(rdesc->desc2, TX_NORMAL_DESC2, HL_B1L, |
| 1557 | rdata->skb_dma_len); |
| 1558 | |
Lendacky, Thomas | c5aa9e3 | 2014-06-05 09:15:06 -0500 | [diff] [blame] | 1559 | /* Set OWN bit */ |
| 1560 | XGMAC_SET_BITS_LE(rdesc->desc3, TX_NORMAL_DESC3, OWN, 1); |
| 1561 | |
| 1562 | /* Mark it as NORMAL descriptor */ |
| 1563 | XGMAC_SET_BITS_LE(rdesc->desc3, TX_NORMAL_DESC3, CTXT, 0); |
| 1564 | |
| 1565 | /* Enable HW CSUM */ |
| 1566 | if (csum) |
| 1567 | XGMAC_SET_BITS_LE(rdesc->desc3, TX_NORMAL_DESC3, |
| 1568 | CIC, 0x3); |
| 1569 | } |
| 1570 | |
| 1571 | /* Set LAST bit for the last descriptor */ |
| 1572 | XGMAC_SET_BITS_LE(rdesc->desc3, TX_NORMAL_DESC3, LD, 1); |
| 1573 | |
Lendacky, Thomas | eb79e64 | 2014-11-20 11:04:02 -0600 | [diff] [blame] | 1574 | /* Set IC bit based on Tx coalescing settings */ |
| 1575 | if (tx_set_ic) |
| 1576 | XGMAC_SET_BITS_LE(rdesc->desc2, TX_NORMAL_DESC2, IC, 1); |
| 1577 | |
Lendacky, Thomas | 5fb4b86 | 2014-11-20 11:03:50 -0600 | [diff] [blame] | 1578 | /* Save the Tx info to report back during cleanup */ |
| 1579 | rdata->tx.packets = packet->tx_packets; |
| 1580 | rdata->tx.bytes = packet->tx_bytes; |
| 1581 | |
Lendacky, Thomas | c5aa9e3 | 2014-06-05 09:15:06 -0500 | [diff] [blame] | 1582 | /* In case the Tx DMA engine is running, make sure everything |
| 1583 | * is written to the descriptor(s) before setting the OWN bit |
| 1584 | * for the first descriptor |
| 1585 | */ |
Lendacky, Thomas | ceb8f6b | 2015-03-20 11:50:16 -0500 | [diff] [blame] | 1586 | dma_wmb(); |
Lendacky, Thomas | c5aa9e3 | 2014-06-05 09:15:06 -0500 | [diff] [blame] | 1587 | |
| 1588 | /* Set OWN bit for the first descriptor */ |
Lendacky, Thomas | d0a8ba6 | 2014-06-24 16:19:06 -0500 | [diff] [blame] | 1589 | rdata = XGBE_GET_DESC_DATA(ring, start_index); |
Lendacky, Thomas | c5aa9e3 | 2014-06-05 09:15:06 -0500 | [diff] [blame] | 1590 | rdesc = rdata->rdesc; |
| 1591 | XGMAC_SET_BITS_LE(rdesc->desc3, TX_NORMAL_DESC3, OWN, 1); |
| 1592 | |
Lendacky, Thomas | 34bf65d | 2015-05-14 11:44:03 -0500 | [diff] [blame] | 1593 | if (netif_msg_tx_queued(pdata)) |
| 1594 | xgbe_dump_tx_desc(pdata, ring, start_index, |
| 1595 | packet->rdesc_count, 1); |
Lendacky, Thomas | c5aa9e3 | 2014-06-05 09:15:06 -0500 | [diff] [blame] | 1596 | |
| 1597 | /* Make sure ownership is written to the descriptor */ |
Lendacky, Thomas | ceb8f6b | 2015-03-20 11:50:16 -0500 | [diff] [blame] | 1598 | dma_wmb(); |
Lendacky, Thomas | c5aa9e3 | 2014-06-05 09:15:06 -0500 | [diff] [blame] | 1599 | |
Lendacky, Thomas | a83ef42 | 2015-01-16 12:46:55 -0600 | [diff] [blame] | 1600 | ring->cur = cur_index + 1; |
Lendacky, Thomas | 16958a2 | 2014-11-20 11:04:08 -0600 | [diff] [blame] | 1601 | if (!packet->skb->xmit_more || |
| 1602 | netif_xmit_stopped(netdev_get_tx_queue(pdata->netdev, |
| 1603 | channel->queue_index))) |
| 1604 | xgbe_tx_start_xmit(channel, ring); |
| 1605 | else |
| 1606 | ring->tx.xmit_more = 1; |
Lendacky, Thomas | c5aa9e3 | 2014-06-05 09:15:06 -0500 | [diff] [blame] | 1607 | |
| 1608 | DBGPR(" %s: descriptors %u to %u written\n", |
| 1609 | channel->name, start_index & (ring->rdesc_count - 1), |
| 1610 | (ring->cur - 1) & (ring->rdesc_count - 1)); |
| 1611 | |
Lendacky, Thomas | a9d4198 | 2014-11-04 16:06:32 -0600 | [diff] [blame] | 1612 | DBGPR("<--xgbe_dev_xmit\n"); |
Lendacky, Thomas | c5aa9e3 | 2014-06-05 09:15:06 -0500 | [diff] [blame] | 1613 | } |
| 1614 | |
| 1615 | static int xgbe_dev_read(struct xgbe_channel *channel) |
| 1616 | { |
Lendacky, Thomas | 5452b2d | 2015-05-14 11:43:57 -0500 | [diff] [blame] | 1617 | struct xgbe_prv_data *pdata = channel->pdata; |
Lendacky, Thomas | c5aa9e3 | 2014-06-05 09:15:06 -0500 | [diff] [blame] | 1618 | struct xgbe_ring *ring = channel->rx_ring; |
| 1619 | struct xgbe_ring_data *rdata; |
| 1620 | struct xgbe_ring_desc *rdesc; |
| 1621 | struct xgbe_packet_data *packet = &ring->packet_data; |
Lendacky, Thomas | 5452b2d | 2015-05-14 11:43:57 -0500 | [diff] [blame] | 1622 | struct net_device *netdev = pdata->netdev; |
Lendacky, Thomas | 5b9dfe2 | 2014-11-04 16:07:02 -0600 | [diff] [blame] | 1623 | unsigned int err, etlt, l34t; |
Lendacky, Thomas | c5aa9e3 | 2014-06-05 09:15:06 -0500 | [diff] [blame] | 1624 | |
| 1625 | DBGPR("-->xgbe_dev_read: cur = %d\n", ring->cur); |
| 1626 | |
Lendacky, Thomas | d0a8ba6 | 2014-06-24 16:19:06 -0500 | [diff] [blame] | 1627 | rdata = XGBE_GET_DESC_DATA(ring, ring->cur); |
Lendacky, Thomas | c5aa9e3 | 2014-06-05 09:15:06 -0500 | [diff] [blame] | 1628 | rdesc = rdata->rdesc; |
| 1629 | |
| 1630 | /* Check for data availability */ |
| 1631 | if (XGMAC_GET_BITS_LE(rdesc->desc3, RX_NORMAL_DESC3, OWN)) |
| 1632 | return 1; |
| 1633 | |
Lendacky, Thomas | 5449e27 | 2014-11-20 11:03:26 -0600 | [diff] [blame] | 1634 | /* Make sure descriptor fields are read after reading the OWN bit */ |
Lendacky, Thomas | ceb8f6b | 2015-03-20 11:50:16 -0500 | [diff] [blame] | 1635 | dma_rmb(); |
Lendacky, Thomas | 5449e27 | 2014-11-20 11:03:26 -0600 | [diff] [blame] | 1636 | |
Lendacky, Thomas | 34bf65d | 2015-05-14 11:44:03 -0500 | [diff] [blame] | 1637 | if (netif_msg_rx_status(pdata)) |
| 1638 | xgbe_dump_rx_desc(pdata, ring, ring->cur); |
Lendacky, Thomas | c5aa9e3 | 2014-06-05 09:15:06 -0500 | [diff] [blame] | 1639 | |
Lendacky, Thomas | 23e4eef | 2014-07-29 08:57:19 -0500 | [diff] [blame] | 1640 | if (XGMAC_GET_BITS_LE(rdesc->desc3, RX_NORMAL_DESC3, CTXT)) { |
| 1641 | /* Timestamp Context Descriptor */ |
| 1642 | xgbe_get_rx_tstamp(packet, rdesc); |
| 1643 | |
| 1644 | XGMAC_SET_BITS(packet->attributes, RX_PACKET_ATTRIBUTES, |
| 1645 | CONTEXT, 1); |
| 1646 | XGMAC_SET_BITS(packet->attributes, RX_PACKET_ATTRIBUTES, |
| 1647 | CONTEXT_NEXT, 0); |
| 1648 | return 0; |
| 1649 | } |
| 1650 | |
| 1651 | /* Normal Descriptor, be sure Context Descriptor bit is off */ |
| 1652 | XGMAC_SET_BITS(packet->attributes, RX_PACKET_ATTRIBUTES, CONTEXT, 0); |
| 1653 | |
| 1654 | /* Indicate if a Context Descriptor is next */ |
| 1655 | if (XGMAC_GET_BITS_LE(rdesc->desc3, RX_NORMAL_DESC3, CDA)) |
| 1656 | XGMAC_SET_BITS(packet->attributes, RX_PACKET_ATTRIBUTES, |
| 1657 | CONTEXT_NEXT, 1); |
| 1658 | |
Lendacky, Thomas | 174fd25 | 2014-11-04 16:06:50 -0600 | [diff] [blame] | 1659 | /* Get the header length */ |
Lendacky, Thomas | 5452b2d | 2015-05-14 11:43:57 -0500 | [diff] [blame] | 1660 | if (XGMAC_GET_BITS_LE(rdesc->desc3, RX_NORMAL_DESC3, FD)) { |
Lendacky, Thomas | c9f140e | 2014-11-20 11:03:44 -0600 | [diff] [blame] | 1661 | rdata->rx.hdr_len = XGMAC_GET_BITS_LE(rdesc->desc2, |
| 1662 | RX_NORMAL_DESC2, HL); |
Lendacky, Thomas | 5452b2d | 2015-05-14 11:43:57 -0500 | [diff] [blame] | 1663 | if (rdata->rx.hdr_len) |
| 1664 | pdata->ext_stats.rx_split_header_packets++; |
| 1665 | } |
Lendacky, Thomas | 174fd25 | 2014-11-04 16:06:50 -0600 | [diff] [blame] | 1666 | |
Lendacky, Thomas | 5b9dfe2 | 2014-11-04 16:07:02 -0600 | [diff] [blame] | 1667 | /* Get the RSS hash */ |
| 1668 | if (XGMAC_GET_BITS_LE(rdesc->desc3, RX_NORMAL_DESC3, RSV)) { |
| 1669 | XGMAC_SET_BITS(packet->attributes, RX_PACKET_ATTRIBUTES, |
| 1670 | RSS_HASH, 1); |
| 1671 | |
| 1672 | packet->rss_hash = le32_to_cpu(rdesc->desc1); |
| 1673 | |
| 1674 | l34t = XGMAC_GET_BITS_LE(rdesc->desc3, RX_NORMAL_DESC3, L34T); |
| 1675 | switch (l34t) { |
| 1676 | case RX_DESC3_L34T_IPV4_TCP: |
| 1677 | case RX_DESC3_L34T_IPV4_UDP: |
| 1678 | case RX_DESC3_L34T_IPV6_TCP: |
| 1679 | case RX_DESC3_L34T_IPV6_UDP: |
| 1680 | packet->rss_hash_type = PKT_HASH_TYPE_L4; |
Dan Carpenter | b6267d3 | 2014-11-13 09:19:06 +0300 | [diff] [blame] | 1681 | break; |
Lendacky, Thomas | 5b9dfe2 | 2014-11-04 16:07:02 -0600 | [diff] [blame] | 1682 | default: |
| 1683 | packet->rss_hash_type = PKT_HASH_TYPE_L3; |
| 1684 | } |
| 1685 | } |
| 1686 | |
Lendacky, Thomas | c5aa9e3 | 2014-06-05 09:15:06 -0500 | [diff] [blame] | 1687 | /* Get the packet length */ |
Lendacky, Thomas | c9f140e | 2014-11-20 11:03:44 -0600 | [diff] [blame] | 1688 | rdata->rx.len = XGMAC_GET_BITS_LE(rdesc->desc3, RX_NORMAL_DESC3, PL); |
Lendacky, Thomas | c5aa9e3 | 2014-06-05 09:15:06 -0500 | [diff] [blame] | 1689 | |
| 1690 | if (!XGMAC_GET_BITS_LE(rdesc->desc3, RX_NORMAL_DESC3, LD)) { |
| 1691 | /* Not all the data has been transferred for this packet */ |
| 1692 | XGMAC_SET_BITS(packet->attributes, RX_PACKET_ATTRIBUTES, |
| 1693 | INCOMPLETE, 1); |
| 1694 | return 0; |
| 1695 | } |
| 1696 | |
| 1697 | /* This is the last of the data for this packet */ |
| 1698 | XGMAC_SET_BITS(packet->attributes, RX_PACKET_ATTRIBUTES, |
| 1699 | INCOMPLETE, 0); |
| 1700 | |
| 1701 | /* Set checksum done indicator as appropriate */ |
Lendacky, Thomas | 5452b2d | 2015-05-14 11:43:57 -0500 | [diff] [blame] | 1702 | if (netdev->features & NETIF_F_RXCSUM) |
Lendacky, Thomas | c5aa9e3 | 2014-06-05 09:15:06 -0500 | [diff] [blame] | 1703 | XGMAC_SET_BITS(packet->attributes, RX_PACKET_ATTRIBUTES, |
| 1704 | CSUM_DONE, 1); |
| 1705 | |
| 1706 | /* Check for errors (only valid in last descriptor) */ |
| 1707 | err = XGMAC_GET_BITS_LE(rdesc->desc3, RX_NORMAL_DESC3, ES); |
| 1708 | etlt = XGMAC_GET_BITS_LE(rdesc->desc3, RX_NORMAL_DESC3, ETLT); |
Lendacky, Thomas | 34bf65d | 2015-05-14 11:44:03 -0500 | [diff] [blame] | 1709 | netif_dbg(pdata, rx_status, netdev, "err=%u, etlt=%#x\n", err, etlt); |
Lendacky, Thomas | c5aa9e3 | 2014-06-05 09:15:06 -0500 | [diff] [blame] | 1710 | |
Lendacky, Thomas | 7bba35b | 2014-11-20 11:03:38 -0600 | [diff] [blame] | 1711 | if (!err || !etlt) { |
| 1712 | /* No error if err is 0 or etlt is 0 */ |
Lendacky, Thomas | c52e9c6 | 2014-06-24 16:19:18 -0500 | [diff] [blame] | 1713 | if ((etlt == 0x09) && |
| 1714 | (netdev->features & NETIF_F_HW_VLAN_CTAG_RX)) { |
Lendacky, Thomas | c5aa9e3 | 2014-06-05 09:15:06 -0500 | [diff] [blame] | 1715 | XGMAC_SET_BITS(packet->attributes, RX_PACKET_ATTRIBUTES, |
| 1716 | VLAN_CTAG, 1); |
| 1717 | packet->vlan_ctag = XGMAC_GET_BITS_LE(rdesc->desc0, |
| 1718 | RX_NORMAL_DESC0, |
| 1719 | OVT); |
Lendacky, Thomas | 34bf65d | 2015-05-14 11:44:03 -0500 | [diff] [blame] | 1720 | netif_dbg(pdata, rx_status, netdev, "vlan-ctag=%#06x\n", |
| 1721 | packet->vlan_ctag); |
Lendacky, Thomas | c5aa9e3 | 2014-06-05 09:15:06 -0500 | [diff] [blame] | 1722 | } |
| 1723 | } else { |
| 1724 | if ((etlt == 0x05) || (etlt == 0x06)) |
| 1725 | XGMAC_SET_BITS(packet->attributes, RX_PACKET_ATTRIBUTES, |
| 1726 | CSUM_DONE, 0); |
| 1727 | else |
| 1728 | XGMAC_SET_BITS(packet->errors, RX_PACKET_ERRORS, |
| 1729 | FRAME, 1); |
| 1730 | } |
| 1731 | |
| 1732 | DBGPR("<--xgbe_dev_read: %s - descriptor=%u (cur=%d)\n", channel->name, |
| 1733 | ring->cur & (ring->rdesc_count - 1), ring->cur); |
| 1734 | |
| 1735 | return 0; |
| 1736 | } |
| 1737 | |
| 1738 | static int xgbe_is_context_desc(struct xgbe_ring_desc *rdesc) |
| 1739 | { |
| 1740 | /* Rx and Tx share CTXT bit, so check TDES3.CTXT bit */ |
| 1741 | return XGMAC_GET_BITS_LE(rdesc->desc3, TX_NORMAL_DESC3, CTXT); |
| 1742 | } |
| 1743 | |
| 1744 | static int xgbe_is_last_desc(struct xgbe_ring_desc *rdesc) |
| 1745 | { |
| 1746 | /* Rx and Tx share LD bit, so check TDES3.LD bit */ |
| 1747 | return XGMAC_GET_BITS_LE(rdesc->desc3, TX_NORMAL_DESC3, LD); |
| 1748 | } |
| 1749 | |
Lendacky, Thomas | c5aa9e3 | 2014-06-05 09:15:06 -0500 | [diff] [blame] | 1750 | static int xgbe_enable_int(struct xgbe_channel *channel, |
| 1751 | enum xgbe_int int_id) |
| 1752 | { |
Lendacky, Thomas | 9867e8f | 2014-07-02 13:04:46 -0500 | [diff] [blame] | 1753 | unsigned int dma_ch_ier; |
| 1754 | |
| 1755 | dma_ch_ier = XGMAC_DMA_IOREAD(channel, DMA_CH_IER); |
| 1756 | |
Lendacky, Thomas | c5aa9e3 | 2014-06-05 09:15:06 -0500 | [diff] [blame] | 1757 | switch (int_id) { |
Lendacky, Thomas | c5aa9e3 | 2014-06-05 09:15:06 -0500 | [diff] [blame] | 1758 | case XGMAC_INT_DMA_CH_SR_TI: |
Lendacky, Thomas | 9867e8f | 2014-07-02 13:04:46 -0500 | [diff] [blame] | 1759 | XGMAC_SET_BITS(dma_ch_ier, DMA_CH_IER, TIE, 1); |
Lendacky, Thomas | c5aa9e3 | 2014-06-05 09:15:06 -0500 | [diff] [blame] | 1760 | break; |
| 1761 | case XGMAC_INT_DMA_CH_SR_TPS: |
Lendacky, Thomas | 9867e8f | 2014-07-02 13:04:46 -0500 | [diff] [blame] | 1762 | XGMAC_SET_BITS(dma_ch_ier, DMA_CH_IER, TXSE, 1); |
Lendacky, Thomas | c5aa9e3 | 2014-06-05 09:15:06 -0500 | [diff] [blame] | 1763 | break; |
| 1764 | case XGMAC_INT_DMA_CH_SR_TBU: |
Lendacky, Thomas | 9867e8f | 2014-07-02 13:04:46 -0500 | [diff] [blame] | 1765 | XGMAC_SET_BITS(dma_ch_ier, DMA_CH_IER, TBUE, 1); |
Lendacky, Thomas | c5aa9e3 | 2014-06-05 09:15:06 -0500 | [diff] [blame] | 1766 | break; |
| 1767 | case XGMAC_INT_DMA_CH_SR_RI: |
Lendacky, Thomas | 9867e8f | 2014-07-02 13:04:46 -0500 | [diff] [blame] | 1768 | XGMAC_SET_BITS(dma_ch_ier, DMA_CH_IER, RIE, 1); |
Lendacky, Thomas | c5aa9e3 | 2014-06-05 09:15:06 -0500 | [diff] [blame] | 1769 | break; |
| 1770 | case XGMAC_INT_DMA_CH_SR_RBU: |
Lendacky, Thomas | 9867e8f | 2014-07-02 13:04:46 -0500 | [diff] [blame] | 1771 | XGMAC_SET_BITS(dma_ch_ier, DMA_CH_IER, RBUE, 1); |
Lendacky, Thomas | c5aa9e3 | 2014-06-05 09:15:06 -0500 | [diff] [blame] | 1772 | break; |
| 1773 | case XGMAC_INT_DMA_CH_SR_RPS: |
Lendacky, Thomas | 9867e8f | 2014-07-02 13:04:46 -0500 | [diff] [blame] | 1774 | XGMAC_SET_BITS(dma_ch_ier, DMA_CH_IER, RSE, 1); |
| 1775 | break; |
| 1776 | case XGMAC_INT_DMA_CH_SR_TI_RI: |
| 1777 | XGMAC_SET_BITS(dma_ch_ier, DMA_CH_IER, TIE, 1); |
| 1778 | XGMAC_SET_BITS(dma_ch_ier, DMA_CH_IER, RIE, 1); |
Lendacky, Thomas | c5aa9e3 | 2014-06-05 09:15:06 -0500 | [diff] [blame] | 1779 | break; |
| 1780 | case XGMAC_INT_DMA_CH_SR_FBE: |
Lendacky, Thomas | 9867e8f | 2014-07-02 13:04:46 -0500 | [diff] [blame] | 1781 | XGMAC_SET_BITS(dma_ch_ier, DMA_CH_IER, FBEE, 1); |
Lendacky, Thomas | c5aa9e3 | 2014-06-05 09:15:06 -0500 | [diff] [blame] | 1782 | break; |
| 1783 | case XGMAC_INT_DMA_ALL: |
Lendacky, Thomas | 9867e8f | 2014-07-02 13:04:46 -0500 | [diff] [blame] | 1784 | dma_ch_ier |= channel->saved_ier; |
Lendacky, Thomas | c5aa9e3 | 2014-06-05 09:15:06 -0500 | [diff] [blame] | 1785 | break; |
| 1786 | default: |
| 1787 | return -1; |
| 1788 | } |
| 1789 | |
Lendacky, Thomas | 9867e8f | 2014-07-02 13:04:46 -0500 | [diff] [blame] | 1790 | XGMAC_DMA_IOWRITE(channel, DMA_CH_IER, dma_ch_ier); |
| 1791 | |
Lendacky, Thomas | c5aa9e3 | 2014-06-05 09:15:06 -0500 | [diff] [blame] | 1792 | return 0; |
| 1793 | } |
| 1794 | |
| 1795 | static int xgbe_disable_int(struct xgbe_channel *channel, |
| 1796 | enum xgbe_int int_id) |
| 1797 | { |
| 1798 | unsigned int dma_ch_ier; |
| 1799 | |
Lendacky, Thomas | 9867e8f | 2014-07-02 13:04:46 -0500 | [diff] [blame] | 1800 | dma_ch_ier = XGMAC_DMA_IOREAD(channel, DMA_CH_IER); |
| 1801 | |
Lendacky, Thomas | c5aa9e3 | 2014-06-05 09:15:06 -0500 | [diff] [blame] | 1802 | switch (int_id) { |
Lendacky, Thomas | c5aa9e3 | 2014-06-05 09:15:06 -0500 | [diff] [blame] | 1803 | case XGMAC_INT_DMA_CH_SR_TI: |
Lendacky, Thomas | 9867e8f | 2014-07-02 13:04:46 -0500 | [diff] [blame] | 1804 | XGMAC_SET_BITS(dma_ch_ier, DMA_CH_IER, TIE, 0); |
Lendacky, Thomas | c5aa9e3 | 2014-06-05 09:15:06 -0500 | [diff] [blame] | 1805 | break; |
| 1806 | case XGMAC_INT_DMA_CH_SR_TPS: |
Lendacky, Thomas | 9867e8f | 2014-07-02 13:04:46 -0500 | [diff] [blame] | 1807 | XGMAC_SET_BITS(dma_ch_ier, DMA_CH_IER, TXSE, 0); |
Lendacky, Thomas | c5aa9e3 | 2014-06-05 09:15:06 -0500 | [diff] [blame] | 1808 | break; |
| 1809 | case XGMAC_INT_DMA_CH_SR_TBU: |
Lendacky, Thomas | 9867e8f | 2014-07-02 13:04:46 -0500 | [diff] [blame] | 1810 | XGMAC_SET_BITS(dma_ch_ier, DMA_CH_IER, TBUE, 0); |
Lendacky, Thomas | c5aa9e3 | 2014-06-05 09:15:06 -0500 | [diff] [blame] | 1811 | break; |
| 1812 | case XGMAC_INT_DMA_CH_SR_RI: |
Lendacky, Thomas | 9867e8f | 2014-07-02 13:04:46 -0500 | [diff] [blame] | 1813 | XGMAC_SET_BITS(dma_ch_ier, DMA_CH_IER, RIE, 0); |
Lendacky, Thomas | c5aa9e3 | 2014-06-05 09:15:06 -0500 | [diff] [blame] | 1814 | break; |
| 1815 | case XGMAC_INT_DMA_CH_SR_RBU: |
Lendacky, Thomas | 9867e8f | 2014-07-02 13:04:46 -0500 | [diff] [blame] | 1816 | XGMAC_SET_BITS(dma_ch_ier, DMA_CH_IER, RBUE, 0); |
Lendacky, Thomas | c5aa9e3 | 2014-06-05 09:15:06 -0500 | [diff] [blame] | 1817 | break; |
| 1818 | case XGMAC_INT_DMA_CH_SR_RPS: |
Lendacky, Thomas | 9867e8f | 2014-07-02 13:04:46 -0500 | [diff] [blame] | 1819 | XGMAC_SET_BITS(dma_ch_ier, DMA_CH_IER, RSE, 0); |
| 1820 | break; |
| 1821 | case XGMAC_INT_DMA_CH_SR_TI_RI: |
| 1822 | XGMAC_SET_BITS(dma_ch_ier, DMA_CH_IER, TIE, 0); |
| 1823 | XGMAC_SET_BITS(dma_ch_ier, DMA_CH_IER, RIE, 0); |
Lendacky, Thomas | c5aa9e3 | 2014-06-05 09:15:06 -0500 | [diff] [blame] | 1824 | break; |
| 1825 | case XGMAC_INT_DMA_CH_SR_FBE: |
Lendacky, Thomas | 9867e8f | 2014-07-02 13:04:46 -0500 | [diff] [blame] | 1826 | XGMAC_SET_BITS(dma_ch_ier, DMA_CH_IER, FBEE, 0); |
Lendacky, Thomas | c5aa9e3 | 2014-06-05 09:15:06 -0500 | [diff] [blame] | 1827 | break; |
| 1828 | case XGMAC_INT_DMA_ALL: |
Lendacky, Thomas | 9867e8f | 2014-07-02 13:04:46 -0500 | [diff] [blame] | 1829 | channel->saved_ier = dma_ch_ier & XGBE_DMA_INTERRUPT_MASK; |
Lendacky, Thomas | d0a8ba6 | 2014-06-24 16:19:06 -0500 | [diff] [blame] | 1830 | dma_ch_ier &= ~XGBE_DMA_INTERRUPT_MASK; |
Lendacky, Thomas | c5aa9e3 | 2014-06-05 09:15:06 -0500 | [diff] [blame] | 1831 | break; |
| 1832 | default: |
| 1833 | return -1; |
| 1834 | } |
| 1835 | |
Lendacky, Thomas | 9867e8f | 2014-07-02 13:04:46 -0500 | [diff] [blame] | 1836 | XGMAC_DMA_IOWRITE(channel, DMA_CH_IER, dma_ch_ier); |
| 1837 | |
Lendacky, Thomas | c5aa9e3 | 2014-06-05 09:15:06 -0500 | [diff] [blame] | 1838 | return 0; |
| 1839 | } |
| 1840 | |
| 1841 | static int xgbe_exit(struct xgbe_prv_data *pdata) |
| 1842 | { |
| 1843 | unsigned int count = 2000; |
| 1844 | |
| 1845 | DBGPR("-->xgbe_exit\n"); |
| 1846 | |
| 1847 | /* Issue a software reset */ |
| 1848 | XGMAC_IOWRITE_BITS(pdata, DMA_MR, SWR, 1); |
| 1849 | usleep_range(10, 15); |
| 1850 | |
| 1851 | /* Poll Until Poll Condition */ |
| 1852 | while (count-- && XGMAC_IOREAD_BITS(pdata, DMA_MR, SWR)) |
| 1853 | usleep_range(500, 600); |
| 1854 | |
| 1855 | if (!count) |
| 1856 | return -EBUSY; |
| 1857 | |
| 1858 | DBGPR("<--xgbe_exit\n"); |
| 1859 | |
| 1860 | return 0; |
| 1861 | } |
| 1862 | |
| 1863 | static int xgbe_flush_tx_queues(struct xgbe_prv_data *pdata) |
| 1864 | { |
| 1865 | unsigned int i, count; |
| 1866 | |
Lendacky, Thomas | a9a4a2d | 2014-08-29 13:16:50 -0500 | [diff] [blame] | 1867 | if (XGMAC_GET_BITS(pdata->hw_feat.version, MAC_VR, SNPSVER) < 0x21) |
| 1868 | return 0; |
| 1869 | |
Lendacky, Thomas | 853eb16 | 2014-07-29 08:57:31 -0500 | [diff] [blame] | 1870 | for (i = 0; i < pdata->tx_q_count; i++) |
Lendacky, Thomas | c5aa9e3 | 2014-06-05 09:15:06 -0500 | [diff] [blame] | 1871 | XGMAC_MTL_IOWRITE_BITS(pdata, i, MTL_Q_TQOMR, FTQ, 1); |
| 1872 | |
| 1873 | /* Poll Until Poll Condition */ |
Lendacky, Thomas | 853eb16 | 2014-07-29 08:57:31 -0500 | [diff] [blame] | 1874 | for (i = 0; i < pdata->tx_q_count; i++) { |
Lendacky, Thomas | c5aa9e3 | 2014-06-05 09:15:06 -0500 | [diff] [blame] | 1875 | count = 2000; |
| 1876 | while (count-- && XGMAC_MTL_IOREAD_BITS(pdata, i, |
| 1877 | MTL_Q_TQOMR, FTQ)) |
| 1878 | usleep_range(500, 600); |
| 1879 | |
| 1880 | if (!count) |
| 1881 | return -EBUSY; |
| 1882 | } |
| 1883 | |
| 1884 | return 0; |
| 1885 | } |
| 1886 | |
| 1887 | static void xgbe_config_dma_bus(struct xgbe_prv_data *pdata) |
| 1888 | { |
| 1889 | /* Set enhanced addressing mode */ |
| 1890 | XGMAC_IOWRITE_BITS(pdata, DMA_SBMR, EAME, 1); |
| 1891 | |
| 1892 | /* Set the System Bus mode */ |
| 1893 | XGMAC_IOWRITE_BITS(pdata, DMA_SBMR, UNDEF, 1); |
Lendacky, Thomas | 9867e8f | 2014-07-02 13:04:46 -0500 | [diff] [blame] | 1894 | XGMAC_IOWRITE_BITS(pdata, DMA_SBMR, BLEN_256, 1); |
Lendacky, Thomas | c5aa9e3 | 2014-06-05 09:15:06 -0500 | [diff] [blame] | 1895 | } |
| 1896 | |
| 1897 | static void xgbe_config_dma_cache(struct xgbe_prv_data *pdata) |
| 1898 | { |
| 1899 | unsigned int arcache, awcache; |
| 1900 | |
| 1901 | arcache = 0; |
Lendacky, Thomas | cfa50c7 | 2014-07-02 13:04:57 -0500 | [diff] [blame] | 1902 | XGMAC_SET_BITS(arcache, DMA_AXIARCR, DRC, pdata->arcache); |
| 1903 | XGMAC_SET_BITS(arcache, DMA_AXIARCR, DRD, pdata->axdomain); |
| 1904 | XGMAC_SET_BITS(arcache, DMA_AXIARCR, TEC, pdata->arcache); |
| 1905 | XGMAC_SET_BITS(arcache, DMA_AXIARCR, TED, pdata->axdomain); |
| 1906 | XGMAC_SET_BITS(arcache, DMA_AXIARCR, THC, pdata->arcache); |
| 1907 | XGMAC_SET_BITS(arcache, DMA_AXIARCR, THD, pdata->axdomain); |
Lendacky, Thomas | c5aa9e3 | 2014-06-05 09:15:06 -0500 | [diff] [blame] | 1908 | XGMAC_IOWRITE(pdata, DMA_AXIARCR, arcache); |
| 1909 | |
| 1910 | awcache = 0; |
Lendacky, Thomas | cfa50c7 | 2014-07-02 13:04:57 -0500 | [diff] [blame] | 1911 | XGMAC_SET_BITS(awcache, DMA_AXIAWCR, DWC, pdata->awcache); |
| 1912 | XGMAC_SET_BITS(awcache, DMA_AXIAWCR, DWD, pdata->axdomain); |
| 1913 | XGMAC_SET_BITS(awcache, DMA_AXIAWCR, RPC, pdata->awcache); |
| 1914 | XGMAC_SET_BITS(awcache, DMA_AXIAWCR, RPD, pdata->axdomain); |
| 1915 | XGMAC_SET_BITS(awcache, DMA_AXIAWCR, RHC, pdata->awcache); |
| 1916 | XGMAC_SET_BITS(awcache, DMA_AXIAWCR, RHD, pdata->axdomain); |
| 1917 | XGMAC_SET_BITS(awcache, DMA_AXIAWCR, TDC, pdata->awcache); |
| 1918 | XGMAC_SET_BITS(awcache, DMA_AXIAWCR, TDD, pdata->axdomain); |
Lendacky, Thomas | c5aa9e3 | 2014-06-05 09:15:06 -0500 | [diff] [blame] | 1919 | XGMAC_IOWRITE(pdata, DMA_AXIAWCR, awcache); |
| 1920 | } |
| 1921 | |
| 1922 | static void xgbe_config_mtl_mode(struct xgbe_prv_data *pdata) |
| 1923 | { |
| 1924 | unsigned int i; |
| 1925 | |
Lendacky, Thomas | fca2d99 | 2014-07-29 08:57:55 -0500 | [diff] [blame] | 1926 | /* Set Tx to weighted round robin scheduling algorithm */ |
Lendacky, Thomas | c5aa9e3 | 2014-06-05 09:15:06 -0500 | [diff] [blame] | 1927 | XGMAC_IOWRITE_BITS(pdata, MTL_OMR, ETSALG, MTL_ETSALG_WRR); |
| 1928 | |
Lendacky, Thomas | fca2d99 | 2014-07-29 08:57:55 -0500 | [diff] [blame] | 1929 | /* Set Tx traffic classes to use WRR algorithm with equal weights */ |
| 1930 | for (i = 0; i < pdata->hw_feat.tc_cnt; i++) { |
| 1931 | XGMAC_MTL_IOWRITE_BITS(pdata, i, MTL_TC_ETSCR, TSA, |
| 1932 | MTL_TSA_ETS); |
| 1933 | XGMAC_MTL_IOWRITE_BITS(pdata, i, MTL_TC_QWR, QW, 1); |
| 1934 | } |
Lendacky, Thomas | c5aa9e3 | 2014-06-05 09:15:06 -0500 | [diff] [blame] | 1935 | |
| 1936 | /* Set Rx to strict priority algorithm */ |
| 1937 | XGMAC_IOWRITE_BITS(pdata, MTL_OMR, RAA, MTL_RAA_SP); |
| 1938 | } |
| 1939 | |
Lendacky, Thomas | f076f45 | 2014-08-29 13:16:56 -0500 | [diff] [blame] | 1940 | static unsigned int xgbe_calculate_per_queue_fifo(unsigned int fifo_size, |
| 1941 | unsigned int queue_count) |
Lendacky, Thomas | c5aa9e3 | 2014-06-05 09:15:06 -0500 | [diff] [blame] | 1942 | { |
| 1943 | unsigned int q_fifo_size = 0; |
| 1944 | enum xgbe_mtl_fifo_size p_fifo = XGMAC_MTL_FIFO_SIZE_256; |
| 1945 | |
| 1946 | /* Calculate Tx/Rx fifo share per queue */ |
| 1947 | switch (fifo_size) { |
| 1948 | case 0: |
Lendacky, Thomas | d0a8ba6 | 2014-06-24 16:19:06 -0500 | [diff] [blame] | 1949 | q_fifo_size = XGBE_FIFO_SIZE_B(128); |
Lendacky, Thomas | c5aa9e3 | 2014-06-05 09:15:06 -0500 | [diff] [blame] | 1950 | break; |
| 1951 | case 1: |
Lendacky, Thomas | d0a8ba6 | 2014-06-24 16:19:06 -0500 | [diff] [blame] | 1952 | q_fifo_size = XGBE_FIFO_SIZE_B(256); |
Lendacky, Thomas | c5aa9e3 | 2014-06-05 09:15:06 -0500 | [diff] [blame] | 1953 | break; |
| 1954 | case 2: |
Lendacky, Thomas | d0a8ba6 | 2014-06-24 16:19:06 -0500 | [diff] [blame] | 1955 | q_fifo_size = XGBE_FIFO_SIZE_B(512); |
Lendacky, Thomas | c5aa9e3 | 2014-06-05 09:15:06 -0500 | [diff] [blame] | 1956 | break; |
| 1957 | case 3: |
Lendacky, Thomas | d0a8ba6 | 2014-06-24 16:19:06 -0500 | [diff] [blame] | 1958 | q_fifo_size = XGBE_FIFO_SIZE_KB(1); |
Lendacky, Thomas | c5aa9e3 | 2014-06-05 09:15:06 -0500 | [diff] [blame] | 1959 | break; |
| 1960 | case 4: |
Lendacky, Thomas | d0a8ba6 | 2014-06-24 16:19:06 -0500 | [diff] [blame] | 1961 | q_fifo_size = XGBE_FIFO_SIZE_KB(2); |
Lendacky, Thomas | c5aa9e3 | 2014-06-05 09:15:06 -0500 | [diff] [blame] | 1962 | break; |
| 1963 | case 5: |
Lendacky, Thomas | d0a8ba6 | 2014-06-24 16:19:06 -0500 | [diff] [blame] | 1964 | q_fifo_size = XGBE_FIFO_SIZE_KB(4); |
Lendacky, Thomas | c5aa9e3 | 2014-06-05 09:15:06 -0500 | [diff] [blame] | 1965 | break; |
| 1966 | case 6: |
Lendacky, Thomas | d0a8ba6 | 2014-06-24 16:19:06 -0500 | [diff] [blame] | 1967 | q_fifo_size = XGBE_FIFO_SIZE_KB(8); |
Lendacky, Thomas | c5aa9e3 | 2014-06-05 09:15:06 -0500 | [diff] [blame] | 1968 | break; |
| 1969 | case 7: |
Lendacky, Thomas | d0a8ba6 | 2014-06-24 16:19:06 -0500 | [diff] [blame] | 1970 | q_fifo_size = XGBE_FIFO_SIZE_KB(16); |
Lendacky, Thomas | c5aa9e3 | 2014-06-05 09:15:06 -0500 | [diff] [blame] | 1971 | break; |
| 1972 | case 8: |
Lendacky, Thomas | d0a8ba6 | 2014-06-24 16:19:06 -0500 | [diff] [blame] | 1973 | q_fifo_size = XGBE_FIFO_SIZE_KB(32); |
Lendacky, Thomas | c5aa9e3 | 2014-06-05 09:15:06 -0500 | [diff] [blame] | 1974 | break; |
| 1975 | case 9: |
Lendacky, Thomas | d0a8ba6 | 2014-06-24 16:19:06 -0500 | [diff] [blame] | 1976 | q_fifo_size = XGBE_FIFO_SIZE_KB(64); |
Lendacky, Thomas | c5aa9e3 | 2014-06-05 09:15:06 -0500 | [diff] [blame] | 1977 | break; |
| 1978 | case 10: |
Lendacky, Thomas | d0a8ba6 | 2014-06-24 16:19:06 -0500 | [diff] [blame] | 1979 | q_fifo_size = XGBE_FIFO_SIZE_KB(128); |
Lendacky, Thomas | c5aa9e3 | 2014-06-05 09:15:06 -0500 | [diff] [blame] | 1980 | break; |
| 1981 | case 11: |
Lendacky, Thomas | d0a8ba6 | 2014-06-24 16:19:06 -0500 | [diff] [blame] | 1982 | q_fifo_size = XGBE_FIFO_SIZE_KB(256); |
Lendacky, Thomas | c5aa9e3 | 2014-06-05 09:15:06 -0500 | [diff] [blame] | 1983 | break; |
| 1984 | } |
Lendacky, Thomas | f076f45 | 2014-08-29 13:16:56 -0500 | [diff] [blame] | 1985 | |
| 1986 | /* The configured value is not the actual amount of fifo RAM */ |
| 1987 | q_fifo_size = min_t(unsigned int, XGBE_FIFO_MAX, q_fifo_size); |
| 1988 | |
Lendacky, Thomas | c5aa9e3 | 2014-06-05 09:15:06 -0500 | [diff] [blame] | 1989 | q_fifo_size = q_fifo_size / queue_count; |
| 1990 | |
| 1991 | /* Set the queue fifo size programmable value */ |
Lendacky, Thomas | d0a8ba6 | 2014-06-24 16:19:06 -0500 | [diff] [blame] | 1992 | if (q_fifo_size >= XGBE_FIFO_SIZE_KB(256)) |
Lendacky, Thomas | c5aa9e3 | 2014-06-05 09:15:06 -0500 | [diff] [blame] | 1993 | p_fifo = XGMAC_MTL_FIFO_SIZE_256K; |
Lendacky, Thomas | d0a8ba6 | 2014-06-24 16:19:06 -0500 | [diff] [blame] | 1994 | else if (q_fifo_size >= XGBE_FIFO_SIZE_KB(128)) |
Lendacky, Thomas | c5aa9e3 | 2014-06-05 09:15:06 -0500 | [diff] [blame] | 1995 | p_fifo = XGMAC_MTL_FIFO_SIZE_128K; |
Lendacky, Thomas | d0a8ba6 | 2014-06-24 16:19:06 -0500 | [diff] [blame] | 1996 | else if (q_fifo_size >= XGBE_FIFO_SIZE_KB(64)) |
Lendacky, Thomas | c5aa9e3 | 2014-06-05 09:15:06 -0500 | [diff] [blame] | 1997 | p_fifo = XGMAC_MTL_FIFO_SIZE_64K; |
Lendacky, Thomas | d0a8ba6 | 2014-06-24 16:19:06 -0500 | [diff] [blame] | 1998 | else if (q_fifo_size >= XGBE_FIFO_SIZE_KB(32)) |
Lendacky, Thomas | c5aa9e3 | 2014-06-05 09:15:06 -0500 | [diff] [blame] | 1999 | p_fifo = XGMAC_MTL_FIFO_SIZE_32K; |
Lendacky, Thomas | d0a8ba6 | 2014-06-24 16:19:06 -0500 | [diff] [blame] | 2000 | else if (q_fifo_size >= XGBE_FIFO_SIZE_KB(16)) |
Lendacky, Thomas | c5aa9e3 | 2014-06-05 09:15:06 -0500 | [diff] [blame] | 2001 | p_fifo = XGMAC_MTL_FIFO_SIZE_16K; |
Lendacky, Thomas | d0a8ba6 | 2014-06-24 16:19:06 -0500 | [diff] [blame] | 2002 | else if (q_fifo_size >= XGBE_FIFO_SIZE_KB(8)) |
Lendacky, Thomas | c5aa9e3 | 2014-06-05 09:15:06 -0500 | [diff] [blame] | 2003 | p_fifo = XGMAC_MTL_FIFO_SIZE_8K; |
Lendacky, Thomas | d0a8ba6 | 2014-06-24 16:19:06 -0500 | [diff] [blame] | 2004 | else if (q_fifo_size >= XGBE_FIFO_SIZE_KB(4)) |
Lendacky, Thomas | c5aa9e3 | 2014-06-05 09:15:06 -0500 | [diff] [blame] | 2005 | p_fifo = XGMAC_MTL_FIFO_SIZE_4K; |
Lendacky, Thomas | d0a8ba6 | 2014-06-24 16:19:06 -0500 | [diff] [blame] | 2006 | else if (q_fifo_size >= XGBE_FIFO_SIZE_KB(2)) |
Lendacky, Thomas | c5aa9e3 | 2014-06-05 09:15:06 -0500 | [diff] [blame] | 2007 | p_fifo = XGMAC_MTL_FIFO_SIZE_2K; |
Lendacky, Thomas | d0a8ba6 | 2014-06-24 16:19:06 -0500 | [diff] [blame] | 2008 | else if (q_fifo_size >= XGBE_FIFO_SIZE_KB(1)) |
Lendacky, Thomas | c5aa9e3 | 2014-06-05 09:15:06 -0500 | [diff] [blame] | 2009 | p_fifo = XGMAC_MTL_FIFO_SIZE_1K; |
Lendacky, Thomas | d0a8ba6 | 2014-06-24 16:19:06 -0500 | [diff] [blame] | 2010 | else if (q_fifo_size >= XGBE_FIFO_SIZE_B(512)) |
Lendacky, Thomas | c5aa9e3 | 2014-06-05 09:15:06 -0500 | [diff] [blame] | 2011 | p_fifo = XGMAC_MTL_FIFO_SIZE_512; |
Lendacky, Thomas | d0a8ba6 | 2014-06-24 16:19:06 -0500 | [diff] [blame] | 2012 | else if (q_fifo_size >= XGBE_FIFO_SIZE_B(256)) |
Lendacky, Thomas | c5aa9e3 | 2014-06-05 09:15:06 -0500 | [diff] [blame] | 2013 | p_fifo = XGMAC_MTL_FIFO_SIZE_256; |
| 2014 | |
| 2015 | return p_fifo; |
| 2016 | } |
| 2017 | |
| 2018 | static void xgbe_config_tx_fifo_size(struct xgbe_prv_data *pdata) |
| 2019 | { |
| 2020 | enum xgbe_mtl_fifo_size fifo_size; |
| 2021 | unsigned int i; |
| 2022 | |
| 2023 | fifo_size = xgbe_calculate_per_queue_fifo(pdata->hw_feat.tx_fifo_size, |
Lendacky, Thomas | 853eb16 | 2014-07-29 08:57:31 -0500 | [diff] [blame] | 2024 | pdata->tx_q_count); |
Lendacky, Thomas | c5aa9e3 | 2014-06-05 09:15:06 -0500 | [diff] [blame] | 2025 | |
Lendacky, Thomas | 853eb16 | 2014-07-29 08:57:31 -0500 | [diff] [blame] | 2026 | for (i = 0; i < pdata->tx_q_count; i++) |
Lendacky, Thomas | c5aa9e3 | 2014-06-05 09:15:06 -0500 | [diff] [blame] | 2027 | XGMAC_MTL_IOWRITE_BITS(pdata, i, MTL_Q_TQOMR, TQS, fifo_size); |
| 2028 | |
Lendacky, Thomas | 34bf65d | 2015-05-14 11:44:03 -0500 | [diff] [blame] | 2029 | netif_info(pdata, drv, pdata->netdev, |
| 2030 | "%d Tx hardware queues, %d byte fifo per queue\n", |
| 2031 | pdata->tx_q_count, ((fifo_size + 1) * 256)); |
Lendacky, Thomas | c5aa9e3 | 2014-06-05 09:15:06 -0500 | [diff] [blame] | 2032 | } |
| 2033 | |
| 2034 | static void xgbe_config_rx_fifo_size(struct xgbe_prv_data *pdata) |
| 2035 | { |
| 2036 | enum xgbe_mtl_fifo_size fifo_size; |
| 2037 | unsigned int i; |
| 2038 | |
| 2039 | fifo_size = xgbe_calculate_per_queue_fifo(pdata->hw_feat.rx_fifo_size, |
Lendacky, Thomas | 853eb16 | 2014-07-29 08:57:31 -0500 | [diff] [blame] | 2040 | pdata->rx_q_count); |
Lendacky, Thomas | c5aa9e3 | 2014-06-05 09:15:06 -0500 | [diff] [blame] | 2041 | |
Lendacky, Thomas | 853eb16 | 2014-07-29 08:57:31 -0500 | [diff] [blame] | 2042 | for (i = 0; i < pdata->rx_q_count; i++) |
Lendacky, Thomas | c5aa9e3 | 2014-06-05 09:15:06 -0500 | [diff] [blame] | 2043 | XGMAC_MTL_IOWRITE_BITS(pdata, i, MTL_Q_RQOMR, RQS, fifo_size); |
| 2044 | |
Lendacky, Thomas | 34bf65d | 2015-05-14 11:44:03 -0500 | [diff] [blame] | 2045 | netif_info(pdata, drv, pdata->netdev, |
| 2046 | "%d Rx hardware queues, %d byte fifo per queue\n", |
| 2047 | pdata->rx_q_count, ((fifo_size + 1) * 256)); |
Lendacky, Thomas | c5aa9e3 | 2014-06-05 09:15:06 -0500 | [diff] [blame] | 2048 | } |
| 2049 | |
Lendacky, Thomas | fca2d99 | 2014-07-29 08:57:55 -0500 | [diff] [blame] | 2050 | static void xgbe_config_queue_mapping(struct xgbe_prv_data *pdata) |
Lendacky, Thomas | c5aa9e3 | 2014-06-05 09:15:06 -0500 | [diff] [blame] | 2051 | { |
Lendacky, Thomas | fca2d99 | 2014-07-29 08:57:55 -0500 | [diff] [blame] | 2052 | unsigned int qptc, qptc_extra, queue; |
| 2053 | unsigned int prio_queues; |
| 2054 | unsigned int ppq, ppq_extra, prio; |
| 2055 | unsigned int mask; |
| 2056 | unsigned int i, j, reg, reg_val; |
| 2057 | |
| 2058 | /* Map the MTL Tx Queues to Traffic Classes |
| 2059 | * Note: Tx Queues >= Traffic Classes |
| 2060 | */ |
| 2061 | qptc = pdata->tx_q_count / pdata->hw_feat.tc_cnt; |
| 2062 | qptc_extra = pdata->tx_q_count % pdata->hw_feat.tc_cnt; |
| 2063 | |
| 2064 | for (i = 0, queue = 0; i < pdata->hw_feat.tc_cnt; i++) { |
| 2065 | for (j = 0; j < qptc; j++) { |
Lendacky, Thomas | 34bf65d | 2015-05-14 11:44:03 -0500 | [diff] [blame] | 2066 | netif_dbg(pdata, drv, pdata->netdev, |
| 2067 | "TXq%u mapped to TC%u\n", queue, i); |
Lendacky, Thomas | fca2d99 | 2014-07-29 08:57:55 -0500 | [diff] [blame] | 2068 | XGMAC_MTL_IOWRITE_BITS(pdata, queue, MTL_Q_TQOMR, |
| 2069 | Q2TCMAP, i); |
| 2070 | pdata->q2tc_map[queue++] = i; |
| 2071 | } |
| 2072 | |
| 2073 | if (i < qptc_extra) { |
Lendacky, Thomas | 34bf65d | 2015-05-14 11:44:03 -0500 | [diff] [blame] | 2074 | netif_dbg(pdata, drv, pdata->netdev, |
| 2075 | "TXq%u mapped to TC%u\n", queue, i); |
Lendacky, Thomas | fca2d99 | 2014-07-29 08:57:55 -0500 | [diff] [blame] | 2076 | XGMAC_MTL_IOWRITE_BITS(pdata, queue, MTL_Q_TQOMR, |
| 2077 | Q2TCMAP, i); |
| 2078 | pdata->q2tc_map[queue++] = i; |
| 2079 | } |
| 2080 | } |
| 2081 | |
| 2082 | /* Map the 8 VLAN priority values to available MTL Rx queues */ |
| 2083 | prio_queues = min_t(unsigned int, IEEE_8021QAZ_MAX_TCS, |
| 2084 | pdata->rx_q_count); |
| 2085 | ppq = IEEE_8021QAZ_MAX_TCS / prio_queues; |
| 2086 | ppq_extra = IEEE_8021QAZ_MAX_TCS % prio_queues; |
| 2087 | |
| 2088 | reg = MAC_RQC2R; |
| 2089 | reg_val = 0; |
| 2090 | for (i = 0, prio = 0; i < prio_queues;) { |
| 2091 | mask = 0; |
| 2092 | for (j = 0; j < ppq; j++) { |
Lendacky, Thomas | 34bf65d | 2015-05-14 11:44:03 -0500 | [diff] [blame] | 2093 | netif_dbg(pdata, drv, pdata->netdev, |
| 2094 | "PRIO%u mapped to RXq%u\n", prio, i); |
Lendacky, Thomas | fca2d99 | 2014-07-29 08:57:55 -0500 | [diff] [blame] | 2095 | mask |= (1 << prio); |
| 2096 | pdata->prio2q_map[prio++] = i; |
| 2097 | } |
| 2098 | |
| 2099 | if (i < ppq_extra) { |
Lendacky, Thomas | 34bf65d | 2015-05-14 11:44:03 -0500 | [diff] [blame] | 2100 | netif_dbg(pdata, drv, pdata->netdev, |
| 2101 | "PRIO%u mapped to RXq%u\n", prio, i); |
Lendacky, Thomas | fca2d99 | 2014-07-29 08:57:55 -0500 | [diff] [blame] | 2102 | mask |= (1 << prio); |
| 2103 | pdata->prio2q_map[prio++] = i; |
| 2104 | } |
| 2105 | |
| 2106 | reg_val |= (mask << ((i++ % MAC_RQC2_Q_PER_REG) << 3)); |
| 2107 | |
| 2108 | if ((i % MAC_RQC2_Q_PER_REG) && (i != prio_queues)) |
| 2109 | continue; |
| 2110 | |
| 2111 | XGMAC_IOWRITE(pdata, reg, reg_val); |
| 2112 | reg += MAC_RQC2_INC; |
| 2113 | reg_val = 0; |
| 2114 | } |
Lendacky, Thomas | c5aa9e3 | 2014-06-05 09:15:06 -0500 | [diff] [blame] | 2115 | |
| 2116 | /* Select dynamic mapping of MTL Rx queue to DMA Rx channel */ |
| 2117 | reg = MTL_RQDCM0R; |
| 2118 | reg_val = 0; |
Lendacky, Thomas | fca2d99 | 2014-07-29 08:57:55 -0500 | [diff] [blame] | 2119 | for (i = 0; i < pdata->rx_q_count;) { |
Lendacky, Thomas | c5aa9e3 | 2014-06-05 09:15:06 -0500 | [diff] [blame] | 2120 | reg_val |= (0x80 << ((i++ % MTL_RQDCM_Q_PER_REG) << 3)); |
| 2121 | |
Lendacky, Thomas | fca2d99 | 2014-07-29 08:57:55 -0500 | [diff] [blame] | 2122 | if ((i % MTL_RQDCM_Q_PER_REG) && (i != pdata->rx_q_count)) |
Lendacky, Thomas | c5aa9e3 | 2014-06-05 09:15:06 -0500 | [diff] [blame] | 2123 | continue; |
| 2124 | |
| 2125 | XGMAC_IOWRITE(pdata, reg, reg_val); |
| 2126 | |
| 2127 | reg += MTL_RQDCM_INC; |
| 2128 | reg_val = 0; |
| 2129 | } |
| 2130 | } |
| 2131 | |
| 2132 | static void xgbe_config_flow_control_threshold(struct xgbe_prv_data *pdata) |
| 2133 | { |
| 2134 | unsigned int i; |
| 2135 | |
Lendacky, Thomas | 853eb16 | 2014-07-29 08:57:31 -0500 | [diff] [blame] | 2136 | for (i = 0; i < pdata->rx_q_count; i++) { |
Lendacky, Thomas | c5aa9e3 | 2014-06-05 09:15:06 -0500 | [diff] [blame] | 2137 | /* Activate flow control when less than 4k left in fifo */ |
Lendacky, Thomas | e2a2729 | 2015-01-20 12:20:31 -0600 | [diff] [blame] | 2138 | XGMAC_MTL_IOWRITE_BITS(pdata, i, MTL_Q_RQFCR, RFA, 2); |
Lendacky, Thomas | c5aa9e3 | 2014-06-05 09:15:06 -0500 | [diff] [blame] | 2139 | |
| 2140 | /* De-activate flow control when more than 6k left in fifo */ |
Lendacky, Thomas | e2a2729 | 2015-01-20 12:20:31 -0600 | [diff] [blame] | 2141 | XGMAC_MTL_IOWRITE_BITS(pdata, i, MTL_Q_RQFCR, RFD, 4); |
Lendacky, Thomas | c5aa9e3 | 2014-06-05 09:15:06 -0500 | [diff] [blame] | 2142 | } |
| 2143 | } |
| 2144 | |
| 2145 | static void xgbe_config_mac_address(struct xgbe_prv_data *pdata) |
| 2146 | { |
| 2147 | xgbe_set_mac_address(pdata, pdata->netdev->dev_addr); |
Lendacky, Thomas | b85e4d8 | 2014-06-24 16:19:29 -0500 | [diff] [blame] | 2148 | |
| 2149 | /* Filtering is done using perfect filtering and hash filtering */ |
| 2150 | if (pdata->hw_feat.hash_table_size) { |
| 2151 | XGMAC_IOWRITE_BITS(pdata, MAC_PFR, HPF, 1); |
| 2152 | XGMAC_IOWRITE_BITS(pdata, MAC_PFR, HUC, 1); |
| 2153 | XGMAC_IOWRITE_BITS(pdata, MAC_PFR, HMC, 1); |
| 2154 | } |
Lendacky, Thomas | c5aa9e3 | 2014-06-05 09:15:06 -0500 | [diff] [blame] | 2155 | } |
| 2156 | |
| 2157 | static void xgbe_config_jumbo_enable(struct xgbe_prv_data *pdata) |
| 2158 | { |
| 2159 | unsigned int val; |
| 2160 | |
| 2161 | val = (pdata->netdev->mtu > XGMAC_STD_PACKET_MTU) ? 1 : 0; |
| 2162 | |
| 2163 | XGMAC_IOWRITE_BITS(pdata, MAC_RCR, JE, val); |
| 2164 | } |
| 2165 | |
Lendacky, Thomas | 916102c | 2015-01-16 12:46:45 -0600 | [diff] [blame] | 2166 | static void xgbe_config_mac_speed(struct xgbe_prv_data *pdata) |
| 2167 | { |
| 2168 | switch (pdata->phy_speed) { |
| 2169 | case SPEED_10000: |
| 2170 | xgbe_set_xgmii_speed(pdata); |
| 2171 | break; |
| 2172 | |
| 2173 | case SPEED_2500: |
| 2174 | xgbe_set_gmii_2500_speed(pdata); |
| 2175 | break; |
| 2176 | |
| 2177 | case SPEED_1000: |
| 2178 | xgbe_set_gmii_speed(pdata); |
| 2179 | break; |
| 2180 | } |
| 2181 | } |
| 2182 | |
Lendacky, Thomas | c5aa9e3 | 2014-06-05 09:15:06 -0500 | [diff] [blame] | 2183 | static void xgbe_config_checksum_offload(struct xgbe_prv_data *pdata) |
| 2184 | { |
| 2185 | if (pdata->netdev->features & NETIF_F_RXCSUM) |
| 2186 | xgbe_enable_rx_csum(pdata); |
| 2187 | else |
| 2188 | xgbe_disable_rx_csum(pdata); |
| 2189 | } |
| 2190 | |
| 2191 | static void xgbe_config_vlan_support(struct xgbe_prv_data *pdata) |
| 2192 | { |
Lendacky, Thomas | 6e5eed0 | 2014-06-24 16:19:12 -0500 | [diff] [blame] | 2193 | /* Indicate that VLAN Tx CTAGs come from context descriptors */ |
| 2194 | XGMAC_IOWRITE_BITS(pdata, MAC_VLANIR, CSVL, 0); |
| 2195 | XGMAC_IOWRITE_BITS(pdata, MAC_VLANIR, VLTI, 1); |
| 2196 | |
Lendacky, Thomas | 801c62d | 2014-06-24 16:19:24 -0500 | [diff] [blame] | 2197 | /* Set the current VLAN Hash Table register value */ |
| 2198 | xgbe_update_vlan_hash_table(pdata); |
| 2199 | |
| 2200 | if (pdata->netdev->features & NETIF_F_HW_VLAN_CTAG_FILTER) |
| 2201 | xgbe_enable_rx_vlan_filtering(pdata); |
| 2202 | else |
| 2203 | xgbe_disable_rx_vlan_filtering(pdata); |
| 2204 | |
Lendacky, Thomas | c5aa9e3 | 2014-06-05 09:15:06 -0500 | [diff] [blame] | 2205 | if (pdata->netdev->features & NETIF_F_HW_VLAN_CTAG_RX) |
| 2206 | xgbe_enable_rx_vlan_stripping(pdata); |
| 2207 | else |
| 2208 | xgbe_disable_rx_vlan_stripping(pdata); |
| 2209 | } |
| 2210 | |
Lendacky, Thomas | 6026510 | 2014-09-05 18:02:30 -0500 | [diff] [blame] | 2211 | static u64 xgbe_mmc_read(struct xgbe_prv_data *pdata, unsigned int reg_lo) |
| 2212 | { |
| 2213 | bool read_hi; |
| 2214 | u64 val; |
| 2215 | |
| 2216 | switch (reg_lo) { |
| 2217 | /* These registers are always 64 bit */ |
| 2218 | case MMC_TXOCTETCOUNT_GB_LO: |
| 2219 | case MMC_TXOCTETCOUNT_G_LO: |
| 2220 | case MMC_RXOCTETCOUNT_GB_LO: |
| 2221 | case MMC_RXOCTETCOUNT_G_LO: |
| 2222 | read_hi = true; |
| 2223 | break; |
| 2224 | |
| 2225 | default: |
| 2226 | read_hi = false; |
| 2227 | }; |
| 2228 | |
| 2229 | val = XGMAC_IOREAD(pdata, reg_lo); |
| 2230 | |
| 2231 | if (read_hi) |
| 2232 | val |= ((u64)XGMAC_IOREAD(pdata, reg_lo + 4) << 32); |
| 2233 | |
| 2234 | return val; |
| 2235 | } |
| 2236 | |
Lendacky, Thomas | c5aa9e3 | 2014-06-05 09:15:06 -0500 | [diff] [blame] | 2237 | static void xgbe_tx_mmc_int(struct xgbe_prv_data *pdata) |
| 2238 | { |
| 2239 | struct xgbe_mmc_stats *stats = &pdata->mmc_stats; |
| 2240 | unsigned int mmc_isr = XGMAC_IOREAD(pdata, MMC_TISR); |
| 2241 | |
| 2242 | if (XGMAC_GET_BITS(mmc_isr, MMC_TISR, TXOCTETCOUNT_GB)) |
| 2243 | stats->txoctetcount_gb += |
Lendacky, Thomas | 6026510 | 2014-09-05 18:02:30 -0500 | [diff] [blame] | 2244 | xgbe_mmc_read(pdata, MMC_TXOCTETCOUNT_GB_LO); |
Lendacky, Thomas | c5aa9e3 | 2014-06-05 09:15:06 -0500 | [diff] [blame] | 2245 | |
| 2246 | if (XGMAC_GET_BITS(mmc_isr, MMC_TISR, TXFRAMECOUNT_GB)) |
| 2247 | stats->txframecount_gb += |
Lendacky, Thomas | 6026510 | 2014-09-05 18:02:30 -0500 | [diff] [blame] | 2248 | xgbe_mmc_read(pdata, MMC_TXFRAMECOUNT_GB_LO); |
Lendacky, Thomas | c5aa9e3 | 2014-06-05 09:15:06 -0500 | [diff] [blame] | 2249 | |
| 2250 | if (XGMAC_GET_BITS(mmc_isr, MMC_TISR, TXBROADCASTFRAMES_G)) |
| 2251 | stats->txbroadcastframes_g += |
Lendacky, Thomas | 6026510 | 2014-09-05 18:02:30 -0500 | [diff] [blame] | 2252 | xgbe_mmc_read(pdata, MMC_TXBROADCASTFRAMES_G_LO); |
Lendacky, Thomas | c5aa9e3 | 2014-06-05 09:15:06 -0500 | [diff] [blame] | 2253 | |
| 2254 | if (XGMAC_GET_BITS(mmc_isr, MMC_TISR, TXMULTICASTFRAMES_G)) |
| 2255 | stats->txmulticastframes_g += |
Lendacky, Thomas | 6026510 | 2014-09-05 18:02:30 -0500 | [diff] [blame] | 2256 | xgbe_mmc_read(pdata, MMC_TXMULTICASTFRAMES_G_LO); |
Lendacky, Thomas | c5aa9e3 | 2014-06-05 09:15:06 -0500 | [diff] [blame] | 2257 | |
| 2258 | if (XGMAC_GET_BITS(mmc_isr, MMC_TISR, TX64OCTETS_GB)) |
| 2259 | stats->tx64octets_gb += |
Lendacky, Thomas | 6026510 | 2014-09-05 18:02:30 -0500 | [diff] [blame] | 2260 | xgbe_mmc_read(pdata, MMC_TX64OCTETS_GB_LO); |
Lendacky, Thomas | c5aa9e3 | 2014-06-05 09:15:06 -0500 | [diff] [blame] | 2261 | |
| 2262 | if (XGMAC_GET_BITS(mmc_isr, MMC_TISR, TX65TO127OCTETS_GB)) |
| 2263 | stats->tx65to127octets_gb += |
Lendacky, Thomas | 6026510 | 2014-09-05 18:02:30 -0500 | [diff] [blame] | 2264 | xgbe_mmc_read(pdata, MMC_TX65TO127OCTETS_GB_LO); |
Lendacky, Thomas | c5aa9e3 | 2014-06-05 09:15:06 -0500 | [diff] [blame] | 2265 | |
| 2266 | if (XGMAC_GET_BITS(mmc_isr, MMC_TISR, TX128TO255OCTETS_GB)) |
| 2267 | stats->tx128to255octets_gb += |
Lendacky, Thomas | 6026510 | 2014-09-05 18:02:30 -0500 | [diff] [blame] | 2268 | xgbe_mmc_read(pdata, MMC_TX128TO255OCTETS_GB_LO); |
Lendacky, Thomas | c5aa9e3 | 2014-06-05 09:15:06 -0500 | [diff] [blame] | 2269 | |
| 2270 | if (XGMAC_GET_BITS(mmc_isr, MMC_TISR, TX256TO511OCTETS_GB)) |
| 2271 | stats->tx256to511octets_gb += |
Lendacky, Thomas | 6026510 | 2014-09-05 18:02:30 -0500 | [diff] [blame] | 2272 | xgbe_mmc_read(pdata, MMC_TX256TO511OCTETS_GB_LO); |
Lendacky, Thomas | c5aa9e3 | 2014-06-05 09:15:06 -0500 | [diff] [blame] | 2273 | |
| 2274 | if (XGMAC_GET_BITS(mmc_isr, MMC_TISR, TX512TO1023OCTETS_GB)) |
| 2275 | stats->tx512to1023octets_gb += |
Lendacky, Thomas | 6026510 | 2014-09-05 18:02:30 -0500 | [diff] [blame] | 2276 | xgbe_mmc_read(pdata, MMC_TX512TO1023OCTETS_GB_LO); |
Lendacky, Thomas | c5aa9e3 | 2014-06-05 09:15:06 -0500 | [diff] [blame] | 2277 | |
| 2278 | if (XGMAC_GET_BITS(mmc_isr, MMC_TISR, TX1024TOMAXOCTETS_GB)) |
| 2279 | stats->tx1024tomaxoctets_gb += |
Lendacky, Thomas | 6026510 | 2014-09-05 18:02:30 -0500 | [diff] [blame] | 2280 | xgbe_mmc_read(pdata, MMC_TX1024TOMAXOCTETS_GB_LO); |
Lendacky, Thomas | c5aa9e3 | 2014-06-05 09:15:06 -0500 | [diff] [blame] | 2281 | |
| 2282 | if (XGMAC_GET_BITS(mmc_isr, MMC_TISR, TXUNICASTFRAMES_GB)) |
| 2283 | stats->txunicastframes_gb += |
Lendacky, Thomas | 6026510 | 2014-09-05 18:02:30 -0500 | [diff] [blame] | 2284 | xgbe_mmc_read(pdata, MMC_TXUNICASTFRAMES_GB_LO); |
Lendacky, Thomas | c5aa9e3 | 2014-06-05 09:15:06 -0500 | [diff] [blame] | 2285 | |
| 2286 | if (XGMAC_GET_BITS(mmc_isr, MMC_TISR, TXMULTICASTFRAMES_GB)) |
| 2287 | stats->txmulticastframes_gb += |
Lendacky, Thomas | 6026510 | 2014-09-05 18:02:30 -0500 | [diff] [blame] | 2288 | xgbe_mmc_read(pdata, MMC_TXMULTICASTFRAMES_GB_LO); |
Lendacky, Thomas | c5aa9e3 | 2014-06-05 09:15:06 -0500 | [diff] [blame] | 2289 | |
| 2290 | if (XGMAC_GET_BITS(mmc_isr, MMC_TISR, TXBROADCASTFRAMES_GB)) |
| 2291 | stats->txbroadcastframes_g += |
Lendacky, Thomas | 6026510 | 2014-09-05 18:02:30 -0500 | [diff] [blame] | 2292 | xgbe_mmc_read(pdata, MMC_TXBROADCASTFRAMES_GB_LO); |
Lendacky, Thomas | c5aa9e3 | 2014-06-05 09:15:06 -0500 | [diff] [blame] | 2293 | |
| 2294 | if (XGMAC_GET_BITS(mmc_isr, MMC_TISR, TXUNDERFLOWERROR)) |
| 2295 | stats->txunderflowerror += |
Lendacky, Thomas | 6026510 | 2014-09-05 18:02:30 -0500 | [diff] [blame] | 2296 | xgbe_mmc_read(pdata, MMC_TXUNDERFLOWERROR_LO); |
Lendacky, Thomas | c5aa9e3 | 2014-06-05 09:15:06 -0500 | [diff] [blame] | 2297 | |
| 2298 | if (XGMAC_GET_BITS(mmc_isr, MMC_TISR, TXOCTETCOUNT_G)) |
| 2299 | stats->txoctetcount_g += |
Lendacky, Thomas | 6026510 | 2014-09-05 18:02:30 -0500 | [diff] [blame] | 2300 | xgbe_mmc_read(pdata, MMC_TXOCTETCOUNT_G_LO); |
Lendacky, Thomas | c5aa9e3 | 2014-06-05 09:15:06 -0500 | [diff] [blame] | 2301 | |
| 2302 | if (XGMAC_GET_BITS(mmc_isr, MMC_TISR, TXFRAMECOUNT_G)) |
| 2303 | stats->txframecount_g += |
Lendacky, Thomas | 6026510 | 2014-09-05 18:02:30 -0500 | [diff] [blame] | 2304 | xgbe_mmc_read(pdata, MMC_TXFRAMECOUNT_G_LO); |
Lendacky, Thomas | c5aa9e3 | 2014-06-05 09:15:06 -0500 | [diff] [blame] | 2305 | |
| 2306 | if (XGMAC_GET_BITS(mmc_isr, MMC_TISR, TXPAUSEFRAMES)) |
| 2307 | stats->txpauseframes += |
Lendacky, Thomas | 6026510 | 2014-09-05 18:02:30 -0500 | [diff] [blame] | 2308 | xgbe_mmc_read(pdata, MMC_TXPAUSEFRAMES_LO); |
Lendacky, Thomas | c5aa9e3 | 2014-06-05 09:15:06 -0500 | [diff] [blame] | 2309 | |
| 2310 | if (XGMAC_GET_BITS(mmc_isr, MMC_TISR, TXVLANFRAMES_G)) |
| 2311 | stats->txvlanframes_g += |
Lendacky, Thomas | 6026510 | 2014-09-05 18:02:30 -0500 | [diff] [blame] | 2312 | xgbe_mmc_read(pdata, MMC_TXVLANFRAMES_G_LO); |
Lendacky, Thomas | c5aa9e3 | 2014-06-05 09:15:06 -0500 | [diff] [blame] | 2313 | } |
| 2314 | |
| 2315 | static void xgbe_rx_mmc_int(struct xgbe_prv_data *pdata) |
| 2316 | { |
| 2317 | struct xgbe_mmc_stats *stats = &pdata->mmc_stats; |
| 2318 | unsigned int mmc_isr = XGMAC_IOREAD(pdata, MMC_RISR); |
| 2319 | |
| 2320 | if (XGMAC_GET_BITS(mmc_isr, MMC_RISR, RXFRAMECOUNT_GB)) |
| 2321 | stats->rxframecount_gb += |
Lendacky, Thomas | 6026510 | 2014-09-05 18:02:30 -0500 | [diff] [blame] | 2322 | xgbe_mmc_read(pdata, MMC_RXFRAMECOUNT_GB_LO); |
Lendacky, Thomas | c5aa9e3 | 2014-06-05 09:15:06 -0500 | [diff] [blame] | 2323 | |
| 2324 | if (XGMAC_GET_BITS(mmc_isr, MMC_RISR, RXOCTETCOUNT_GB)) |
| 2325 | stats->rxoctetcount_gb += |
Lendacky, Thomas | 6026510 | 2014-09-05 18:02:30 -0500 | [diff] [blame] | 2326 | xgbe_mmc_read(pdata, MMC_RXOCTETCOUNT_GB_LO); |
Lendacky, Thomas | c5aa9e3 | 2014-06-05 09:15:06 -0500 | [diff] [blame] | 2327 | |
| 2328 | if (XGMAC_GET_BITS(mmc_isr, MMC_RISR, RXOCTETCOUNT_G)) |
| 2329 | stats->rxoctetcount_g += |
Lendacky, Thomas | 6026510 | 2014-09-05 18:02:30 -0500 | [diff] [blame] | 2330 | xgbe_mmc_read(pdata, MMC_RXOCTETCOUNT_G_LO); |
Lendacky, Thomas | c5aa9e3 | 2014-06-05 09:15:06 -0500 | [diff] [blame] | 2331 | |
| 2332 | if (XGMAC_GET_BITS(mmc_isr, MMC_RISR, RXBROADCASTFRAMES_G)) |
| 2333 | stats->rxbroadcastframes_g += |
Lendacky, Thomas | 6026510 | 2014-09-05 18:02:30 -0500 | [diff] [blame] | 2334 | xgbe_mmc_read(pdata, MMC_RXBROADCASTFRAMES_G_LO); |
Lendacky, Thomas | c5aa9e3 | 2014-06-05 09:15:06 -0500 | [diff] [blame] | 2335 | |
| 2336 | if (XGMAC_GET_BITS(mmc_isr, MMC_RISR, RXMULTICASTFRAMES_G)) |
| 2337 | stats->rxmulticastframes_g += |
Lendacky, Thomas | 6026510 | 2014-09-05 18:02:30 -0500 | [diff] [blame] | 2338 | xgbe_mmc_read(pdata, MMC_RXMULTICASTFRAMES_G_LO); |
Lendacky, Thomas | c5aa9e3 | 2014-06-05 09:15:06 -0500 | [diff] [blame] | 2339 | |
| 2340 | if (XGMAC_GET_BITS(mmc_isr, MMC_RISR, RXCRCERROR)) |
| 2341 | stats->rxcrcerror += |
Lendacky, Thomas | 6026510 | 2014-09-05 18:02:30 -0500 | [diff] [blame] | 2342 | xgbe_mmc_read(pdata, MMC_RXCRCERROR_LO); |
Lendacky, Thomas | c5aa9e3 | 2014-06-05 09:15:06 -0500 | [diff] [blame] | 2343 | |
| 2344 | if (XGMAC_GET_BITS(mmc_isr, MMC_RISR, RXRUNTERROR)) |
| 2345 | stats->rxrunterror += |
Lendacky, Thomas | 6026510 | 2014-09-05 18:02:30 -0500 | [diff] [blame] | 2346 | xgbe_mmc_read(pdata, MMC_RXRUNTERROR); |
Lendacky, Thomas | c5aa9e3 | 2014-06-05 09:15:06 -0500 | [diff] [blame] | 2347 | |
| 2348 | if (XGMAC_GET_BITS(mmc_isr, MMC_RISR, RXJABBERERROR)) |
| 2349 | stats->rxjabbererror += |
Lendacky, Thomas | 6026510 | 2014-09-05 18:02:30 -0500 | [diff] [blame] | 2350 | xgbe_mmc_read(pdata, MMC_RXJABBERERROR); |
Lendacky, Thomas | c5aa9e3 | 2014-06-05 09:15:06 -0500 | [diff] [blame] | 2351 | |
| 2352 | if (XGMAC_GET_BITS(mmc_isr, MMC_RISR, RXUNDERSIZE_G)) |
| 2353 | stats->rxundersize_g += |
Lendacky, Thomas | 6026510 | 2014-09-05 18:02:30 -0500 | [diff] [blame] | 2354 | xgbe_mmc_read(pdata, MMC_RXUNDERSIZE_G); |
Lendacky, Thomas | c5aa9e3 | 2014-06-05 09:15:06 -0500 | [diff] [blame] | 2355 | |
| 2356 | if (XGMAC_GET_BITS(mmc_isr, MMC_RISR, RXOVERSIZE_G)) |
| 2357 | stats->rxoversize_g += |
Lendacky, Thomas | 6026510 | 2014-09-05 18:02:30 -0500 | [diff] [blame] | 2358 | xgbe_mmc_read(pdata, MMC_RXOVERSIZE_G); |
Lendacky, Thomas | c5aa9e3 | 2014-06-05 09:15:06 -0500 | [diff] [blame] | 2359 | |
| 2360 | if (XGMAC_GET_BITS(mmc_isr, MMC_RISR, RX64OCTETS_GB)) |
| 2361 | stats->rx64octets_gb += |
Lendacky, Thomas | 6026510 | 2014-09-05 18:02:30 -0500 | [diff] [blame] | 2362 | xgbe_mmc_read(pdata, MMC_RX64OCTETS_GB_LO); |
Lendacky, Thomas | c5aa9e3 | 2014-06-05 09:15:06 -0500 | [diff] [blame] | 2363 | |
| 2364 | if (XGMAC_GET_BITS(mmc_isr, MMC_RISR, RX65TO127OCTETS_GB)) |
| 2365 | stats->rx65to127octets_gb += |
Lendacky, Thomas | 6026510 | 2014-09-05 18:02:30 -0500 | [diff] [blame] | 2366 | xgbe_mmc_read(pdata, MMC_RX65TO127OCTETS_GB_LO); |
Lendacky, Thomas | c5aa9e3 | 2014-06-05 09:15:06 -0500 | [diff] [blame] | 2367 | |
| 2368 | if (XGMAC_GET_BITS(mmc_isr, MMC_RISR, RX128TO255OCTETS_GB)) |
| 2369 | stats->rx128to255octets_gb += |
Lendacky, Thomas | 6026510 | 2014-09-05 18:02:30 -0500 | [diff] [blame] | 2370 | xgbe_mmc_read(pdata, MMC_RX128TO255OCTETS_GB_LO); |
Lendacky, Thomas | c5aa9e3 | 2014-06-05 09:15:06 -0500 | [diff] [blame] | 2371 | |
| 2372 | if (XGMAC_GET_BITS(mmc_isr, MMC_RISR, RX256TO511OCTETS_GB)) |
| 2373 | stats->rx256to511octets_gb += |
Lendacky, Thomas | 6026510 | 2014-09-05 18:02:30 -0500 | [diff] [blame] | 2374 | xgbe_mmc_read(pdata, MMC_RX256TO511OCTETS_GB_LO); |
Lendacky, Thomas | c5aa9e3 | 2014-06-05 09:15:06 -0500 | [diff] [blame] | 2375 | |
| 2376 | if (XGMAC_GET_BITS(mmc_isr, MMC_RISR, RX512TO1023OCTETS_GB)) |
| 2377 | stats->rx512to1023octets_gb += |
Lendacky, Thomas | 6026510 | 2014-09-05 18:02:30 -0500 | [diff] [blame] | 2378 | xgbe_mmc_read(pdata, MMC_RX512TO1023OCTETS_GB_LO); |
Lendacky, Thomas | c5aa9e3 | 2014-06-05 09:15:06 -0500 | [diff] [blame] | 2379 | |
| 2380 | if (XGMAC_GET_BITS(mmc_isr, MMC_RISR, RX1024TOMAXOCTETS_GB)) |
| 2381 | stats->rx1024tomaxoctets_gb += |
Lendacky, Thomas | 6026510 | 2014-09-05 18:02:30 -0500 | [diff] [blame] | 2382 | xgbe_mmc_read(pdata, MMC_RX1024TOMAXOCTETS_GB_LO); |
Lendacky, Thomas | c5aa9e3 | 2014-06-05 09:15:06 -0500 | [diff] [blame] | 2383 | |
| 2384 | if (XGMAC_GET_BITS(mmc_isr, MMC_RISR, RXUNICASTFRAMES_G)) |
| 2385 | stats->rxunicastframes_g += |
Lendacky, Thomas | 6026510 | 2014-09-05 18:02:30 -0500 | [diff] [blame] | 2386 | xgbe_mmc_read(pdata, MMC_RXUNICASTFRAMES_G_LO); |
Lendacky, Thomas | c5aa9e3 | 2014-06-05 09:15:06 -0500 | [diff] [blame] | 2387 | |
| 2388 | if (XGMAC_GET_BITS(mmc_isr, MMC_RISR, RXLENGTHERROR)) |
| 2389 | stats->rxlengtherror += |
Lendacky, Thomas | 6026510 | 2014-09-05 18:02:30 -0500 | [diff] [blame] | 2390 | xgbe_mmc_read(pdata, MMC_RXLENGTHERROR_LO); |
Lendacky, Thomas | c5aa9e3 | 2014-06-05 09:15:06 -0500 | [diff] [blame] | 2391 | |
| 2392 | if (XGMAC_GET_BITS(mmc_isr, MMC_RISR, RXOUTOFRANGETYPE)) |
| 2393 | stats->rxoutofrangetype += |
Lendacky, Thomas | 6026510 | 2014-09-05 18:02:30 -0500 | [diff] [blame] | 2394 | xgbe_mmc_read(pdata, MMC_RXOUTOFRANGETYPE_LO); |
Lendacky, Thomas | c5aa9e3 | 2014-06-05 09:15:06 -0500 | [diff] [blame] | 2395 | |
| 2396 | if (XGMAC_GET_BITS(mmc_isr, MMC_RISR, RXPAUSEFRAMES)) |
| 2397 | stats->rxpauseframes += |
Lendacky, Thomas | 6026510 | 2014-09-05 18:02:30 -0500 | [diff] [blame] | 2398 | xgbe_mmc_read(pdata, MMC_RXPAUSEFRAMES_LO); |
Lendacky, Thomas | c5aa9e3 | 2014-06-05 09:15:06 -0500 | [diff] [blame] | 2399 | |
| 2400 | if (XGMAC_GET_BITS(mmc_isr, MMC_RISR, RXFIFOOVERFLOW)) |
| 2401 | stats->rxfifooverflow += |
Lendacky, Thomas | 6026510 | 2014-09-05 18:02:30 -0500 | [diff] [blame] | 2402 | xgbe_mmc_read(pdata, MMC_RXFIFOOVERFLOW_LO); |
Lendacky, Thomas | c5aa9e3 | 2014-06-05 09:15:06 -0500 | [diff] [blame] | 2403 | |
| 2404 | if (XGMAC_GET_BITS(mmc_isr, MMC_RISR, RXVLANFRAMES_GB)) |
| 2405 | stats->rxvlanframes_gb += |
Lendacky, Thomas | 6026510 | 2014-09-05 18:02:30 -0500 | [diff] [blame] | 2406 | xgbe_mmc_read(pdata, MMC_RXVLANFRAMES_GB_LO); |
Lendacky, Thomas | c5aa9e3 | 2014-06-05 09:15:06 -0500 | [diff] [blame] | 2407 | |
| 2408 | if (XGMAC_GET_BITS(mmc_isr, MMC_RISR, RXWATCHDOGERROR)) |
| 2409 | stats->rxwatchdogerror += |
Lendacky, Thomas | 6026510 | 2014-09-05 18:02:30 -0500 | [diff] [blame] | 2410 | xgbe_mmc_read(pdata, MMC_RXWATCHDOGERROR); |
Lendacky, Thomas | c5aa9e3 | 2014-06-05 09:15:06 -0500 | [diff] [blame] | 2411 | } |
| 2412 | |
| 2413 | static void xgbe_read_mmc_stats(struct xgbe_prv_data *pdata) |
| 2414 | { |
| 2415 | struct xgbe_mmc_stats *stats = &pdata->mmc_stats; |
| 2416 | |
| 2417 | /* Freeze counters */ |
| 2418 | XGMAC_IOWRITE_BITS(pdata, MMC_CR, MCF, 1); |
| 2419 | |
| 2420 | stats->txoctetcount_gb += |
Lendacky, Thomas | 6026510 | 2014-09-05 18:02:30 -0500 | [diff] [blame] | 2421 | xgbe_mmc_read(pdata, MMC_TXOCTETCOUNT_GB_LO); |
Lendacky, Thomas | c5aa9e3 | 2014-06-05 09:15:06 -0500 | [diff] [blame] | 2422 | |
| 2423 | stats->txframecount_gb += |
Lendacky, Thomas | 6026510 | 2014-09-05 18:02:30 -0500 | [diff] [blame] | 2424 | xgbe_mmc_read(pdata, MMC_TXFRAMECOUNT_GB_LO); |
Lendacky, Thomas | c5aa9e3 | 2014-06-05 09:15:06 -0500 | [diff] [blame] | 2425 | |
| 2426 | stats->txbroadcastframes_g += |
Lendacky, Thomas | 6026510 | 2014-09-05 18:02:30 -0500 | [diff] [blame] | 2427 | xgbe_mmc_read(pdata, MMC_TXBROADCASTFRAMES_G_LO); |
Lendacky, Thomas | c5aa9e3 | 2014-06-05 09:15:06 -0500 | [diff] [blame] | 2428 | |
| 2429 | stats->txmulticastframes_g += |
Lendacky, Thomas | 6026510 | 2014-09-05 18:02:30 -0500 | [diff] [blame] | 2430 | xgbe_mmc_read(pdata, MMC_TXMULTICASTFRAMES_G_LO); |
Lendacky, Thomas | c5aa9e3 | 2014-06-05 09:15:06 -0500 | [diff] [blame] | 2431 | |
| 2432 | stats->tx64octets_gb += |
Lendacky, Thomas | 6026510 | 2014-09-05 18:02:30 -0500 | [diff] [blame] | 2433 | xgbe_mmc_read(pdata, MMC_TX64OCTETS_GB_LO); |
Lendacky, Thomas | c5aa9e3 | 2014-06-05 09:15:06 -0500 | [diff] [blame] | 2434 | |
| 2435 | stats->tx65to127octets_gb += |
Lendacky, Thomas | 6026510 | 2014-09-05 18:02:30 -0500 | [diff] [blame] | 2436 | xgbe_mmc_read(pdata, MMC_TX65TO127OCTETS_GB_LO); |
Lendacky, Thomas | c5aa9e3 | 2014-06-05 09:15:06 -0500 | [diff] [blame] | 2437 | |
| 2438 | stats->tx128to255octets_gb += |
Lendacky, Thomas | 6026510 | 2014-09-05 18:02:30 -0500 | [diff] [blame] | 2439 | xgbe_mmc_read(pdata, MMC_TX128TO255OCTETS_GB_LO); |
Lendacky, Thomas | c5aa9e3 | 2014-06-05 09:15:06 -0500 | [diff] [blame] | 2440 | |
| 2441 | stats->tx256to511octets_gb += |
Lendacky, Thomas | 6026510 | 2014-09-05 18:02:30 -0500 | [diff] [blame] | 2442 | xgbe_mmc_read(pdata, MMC_TX256TO511OCTETS_GB_LO); |
Lendacky, Thomas | c5aa9e3 | 2014-06-05 09:15:06 -0500 | [diff] [blame] | 2443 | |
| 2444 | stats->tx512to1023octets_gb += |
Lendacky, Thomas | 6026510 | 2014-09-05 18:02:30 -0500 | [diff] [blame] | 2445 | xgbe_mmc_read(pdata, MMC_TX512TO1023OCTETS_GB_LO); |
Lendacky, Thomas | c5aa9e3 | 2014-06-05 09:15:06 -0500 | [diff] [blame] | 2446 | |
| 2447 | stats->tx1024tomaxoctets_gb += |
Lendacky, Thomas | 6026510 | 2014-09-05 18:02:30 -0500 | [diff] [blame] | 2448 | xgbe_mmc_read(pdata, MMC_TX1024TOMAXOCTETS_GB_LO); |
Lendacky, Thomas | c5aa9e3 | 2014-06-05 09:15:06 -0500 | [diff] [blame] | 2449 | |
| 2450 | stats->txunicastframes_gb += |
Lendacky, Thomas | 6026510 | 2014-09-05 18:02:30 -0500 | [diff] [blame] | 2451 | xgbe_mmc_read(pdata, MMC_TXUNICASTFRAMES_GB_LO); |
Lendacky, Thomas | c5aa9e3 | 2014-06-05 09:15:06 -0500 | [diff] [blame] | 2452 | |
| 2453 | stats->txmulticastframes_gb += |
Lendacky, Thomas | 6026510 | 2014-09-05 18:02:30 -0500 | [diff] [blame] | 2454 | xgbe_mmc_read(pdata, MMC_TXMULTICASTFRAMES_GB_LO); |
Lendacky, Thomas | c5aa9e3 | 2014-06-05 09:15:06 -0500 | [diff] [blame] | 2455 | |
| 2456 | stats->txbroadcastframes_g += |
Lendacky, Thomas | 6026510 | 2014-09-05 18:02:30 -0500 | [diff] [blame] | 2457 | xgbe_mmc_read(pdata, MMC_TXBROADCASTFRAMES_GB_LO); |
Lendacky, Thomas | c5aa9e3 | 2014-06-05 09:15:06 -0500 | [diff] [blame] | 2458 | |
| 2459 | stats->txunderflowerror += |
Lendacky, Thomas | 6026510 | 2014-09-05 18:02:30 -0500 | [diff] [blame] | 2460 | xgbe_mmc_read(pdata, MMC_TXUNDERFLOWERROR_LO); |
Lendacky, Thomas | c5aa9e3 | 2014-06-05 09:15:06 -0500 | [diff] [blame] | 2461 | |
| 2462 | stats->txoctetcount_g += |
Lendacky, Thomas | 6026510 | 2014-09-05 18:02:30 -0500 | [diff] [blame] | 2463 | xgbe_mmc_read(pdata, MMC_TXOCTETCOUNT_G_LO); |
Lendacky, Thomas | c5aa9e3 | 2014-06-05 09:15:06 -0500 | [diff] [blame] | 2464 | |
| 2465 | stats->txframecount_g += |
Lendacky, Thomas | 6026510 | 2014-09-05 18:02:30 -0500 | [diff] [blame] | 2466 | xgbe_mmc_read(pdata, MMC_TXFRAMECOUNT_G_LO); |
Lendacky, Thomas | c5aa9e3 | 2014-06-05 09:15:06 -0500 | [diff] [blame] | 2467 | |
| 2468 | stats->txpauseframes += |
Lendacky, Thomas | 6026510 | 2014-09-05 18:02:30 -0500 | [diff] [blame] | 2469 | xgbe_mmc_read(pdata, MMC_TXPAUSEFRAMES_LO); |
Lendacky, Thomas | c5aa9e3 | 2014-06-05 09:15:06 -0500 | [diff] [blame] | 2470 | |
| 2471 | stats->txvlanframes_g += |
Lendacky, Thomas | 6026510 | 2014-09-05 18:02:30 -0500 | [diff] [blame] | 2472 | xgbe_mmc_read(pdata, MMC_TXVLANFRAMES_G_LO); |
Lendacky, Thomas | c5aa9e3 | 2014-06-05 09:15:06 -0500 | [diff] [blame] | 2473 | |
| 2474 | stats->rxframecount_gb += |
Lendacky, Thomas | 6026510 | 2014-09-05 18:02:30 -0500 | [diff] [blame] | 2475 | xgbe_mmc_read(pdata, MMC_RXFRAMECOUNT_GB_LO); |
Lendacky, Thomas | c5aa9e3 | 2014-06-05 09:15:06 -0500 | [diff] [blame] | 2476 | |
| 2477 | stats->rxoctetcount_gb += |
Lendacky, Thomas | 6026510 | 2014-09-05 18:02:30 -0500 | [diff] [blame] | 2478 | xgbe_mmc_read(pdata, MMC_RXOCTETCOUNT_GB_LO); |
Lendacky, Thomas | c5aa9e3 | 2014-06-05 09:15:06 -0500 | [diff] [blame] | 2479 | |
| 2480 | stats->rxoctetcount_g += |
Lendacky, Thomas | 6026510 | 2014-09-05 18:02:30 -0500 | [diff] [blame] | 2481 | xgbe_mmc_read(pdata, MMC_RXOCTETCOUNT_G_LO); |
Lendacky, Thomas | c5aa9e3 | 2014-06-05 09:15:06 -0500 | [diff] [blame] | 2482 | |
| 2483 | stats->rxbroadcastframes_g += |
Lendacky, Thomas | 6026510 | 2014-09-05 18:02:30 -0500 | [diff] [blame] | 2484 | xgbe_mmc_read(pdata, MMC_RXBROADCASTFRAMES_G_LO); |
Lendacky, Thomas | c5aa9e3 | 2014-06-05 09:15:06 -0500 | [diff] [blame] | 2485 | |
| 2486 | stats->rxmulticastframes_g += |
Lendacky, Thomas | 6026510 | 2014-09-05 18:02:30 -0500 | [diff] [blame] | 2487 | xgbe_mmc_read(pdata, MMC_RXMULTICASTFRAMES_G_LO); |
Lendacky, Thomas | c5aa9e3 | 2014-06-05 09:15:06 -0500 | [diff] [blame] | 2488 | |
| 2489 | stats->rxcrcerror += |
Lendacky, Thomas | 6026510 | 2014-09-05 18:02:30 -0500 | [diff] [blame] | 2490 | xgbe_mmc_read(pdata, MMC_RXCRCERROR_LO); |
Lendacky, Thomas | c5aa9e3 | 2014-06-05 09:15:06 -0500 | [diff] [blame] | 2491 | |
| 2492 | stats->rxrunterror += |
Lendacky, Thomas | 6026510 | 2014-09-05 18:02:30 -0500 | [diff] [blame] | 2493 | xgbe_mmc_read(pdata, MMC_RXRUNTERROR); |
Lendacky, Thomas | c5aa9e3 | 2014-06-05 09:15:06 -0500 | [diff] [blame] | 2494 | |
| 2495 | stats->rxjabbererror += |
Lendacky, Thomas | 6026510 | 2014-09-05 18:02:30 -0500 | [diff] [blame] | 2496 | xgbe_mmc_read(pdata, MMC_RXJABBERERROR); |
Lendacky, Thomas | c5aa9e3 | 2014-06-05 09:15:06 -0500 | [diff] [blame] | 2497 | |
| 2498 | stats->rxundersize_g += |
Lendacky, Thomas | 6026510 | 2014-09-05 18:02:30 -0500 | [diff] [blame] | 2499 | xgbe_mmc_read(pdata, MMC_RXUNDERSIZE_G); |
Lendacky, Thomas | c5aa9e3 | 2014-06-05 09:15:06 -0500 | [diff] [blame] | 2500 | |
| 2501 | stats->rxoversize_g += |
Lendacky, Thomas | 6026510 | 2014-09-05 18:02:30 -0500 | [diff] [blame] | 2502 | xgbe_mmc_read(pdata, MMC_RXOVERSIZE_G); |
Lendacky, Thomas | c5aa9e3 | 2014-06-05 09:15:06 -0500 | [diff] [blame] | 2503 | |
| 2504 | stats->rx64octets_gb += |
Lendacky, Thomas | 6026510 | 2014-09-05 18:02:30 -0500 | [diff] [blame] | 2505 | xgbe_mmc_read(pdata, MMC_RX64OCTETS_GB_LO); |
Lendacky, Thomas | c5aa9e3 | 2014-06-05 09:15:06 -0500 | [diff] [blame] | 2506 | |
| 2507 | stats->rx65to127octets_gb += |
Lendacky, Thomas | 6026510 | 2014-09-05 18:02:30 -0500 | [diff] [blame] | 2508 | xgbe_mmc_read(pdata, MMC_RX65TO127OCTETS_GB_LO); |
Lendacky, Thomas | c5aa9e3 | 2014-06-05 09:15:06 -0500 | [diff] [blame] | 2509 | |
| 2510 | stats->rx128to255octets_gb += |
Lendacky, Thomas | 6026510 | 2014-09-05 18:02:30 -0500 | [diff] [blame] | 2511 | xgbe_mmc_read(pdata, MMC_RX128TO255OCTETS_GB_LO); |
Lendacky, Thomas | c5aa9e3 | 2014-06-05 09:15:06 -0500 | [diff] [blame] | 2512 | |
| 2513 | stats->rx256to511octets_gb += |
Lendacky, Thomas | 6026510 | 2014-09-05 18:02:30 -0500 | [diff] [blame] | 2514 | xgbe_mmc_read(pdata, MMC_RX256TO511OCTETS_GB_LO); |
Lendacky, Thomas | c5aa9e3 | 2014-06-05 09:15:06 -0500 | [diff] [blame] | 2515 | |
| 2516 | stats->rx512to1023octets_gb += |
Lendacky, Thomas | 6026510 | 2014-09-05 18:02:30 -0500 | [diff] [blame] | 2517 | xgbe_mmc_read(pdata, MMC_RX512TO1023OCTETS_GB_LO); |
Lendacky, Thomas | c5aa9e3 | 2014-06-05 09:15:06 -0500 | [diff] [blame] | 2518 | |
| 2519 | stats->rx1024tomaxoctets_gb += |
Lendacky, Thomas | 6026510 | 2014-09-05 18:02:30 -0500 | [diff] [blame] | 2520 | xgbe_mmc_read(pdata, MMC_RX1024TOMAXOCTETS_GB_LO); |
Lendacky, Thomas | c5aa9e3 | 2014-06-05 09:15:06 -0500 | [diff] [blame] | 2521 | |
| 2522 | stats->rxunicastframes_g += |
Lendacky, Thomas | 6026510 | 2014-09-05 18:02:30 -0500 | [diff] [blame] | 2523 | xgbe_mmc_read(pdata, MMC_RXUNICASTFRAMES_G_LO); |
Lendacky, Thomas | c5aa9e3 | 2014-06-05 09:15:06 -0500 | [diff] [blame] | 2524 | |
| 2525 | stats->rxlengtherror += |
Lendacky, Thomas | 6026510 | 2014-09-05 18:02:30 -0500 | [diff] [blame] | 2526 | xgbe_mmc_read(pdata, MMC_RXLENGTHERROR_LO); |
Lendacky, Thomas | c5aa9e3 | 2014-06-05 09:15:06 -0500 | [diff] [blame] | 2527 | |
| 2528 | stats->rxoutofrangetype += |
Lendacky, Thomas | 6026510 | 2014-09-05 18:02:30 -0500 | [diff] [blame] | 2529 | xgbe_mmc_read(pdata, MMC_RXOUTOFRANGETYPE_LO); |
Lendacky, Thomas | c5aa9e3 | 2014-06-05 09:15:06 -0500 | [diff] [blame] | 2530 | |
| 2531 | stats->rxpauseframes += |
Lendacky, Thomas | 6026510 | 2014-09-05 18:02:30 -0500 | [diff] [blame] | 2532 | xgbe_mmc_read(pdata, MMC_RXPAUSEFRAMES_LO); |
Lendacky, Thomas | c5aa9e3 | 2014-06-05 09:15:06 -0500 | [diff] [blame] | 2533 | |
| 2534 | stats->rxfifooverflow += |
Lendacky, Thomas | 6026510 | 2014-09-05 18:02:30 -0500 | [diff] [blame] | 2535 | xgbe_mmc_read(pdata, MMC_RXFIFOOVERFLOW_LO); |
Lendacky, Thomas | c5aa9e3 | 2014-06-05 09:15:06 -0500 | [diff] [blame] | 2536 | |
| 2537 | stats->rxvlanframes_gb += |
Lendacky, Thomas | 6026510 | 2014-09-05 18:02:30 -0500 | [diff] [blame] | 2538 | xgbe_mmc_read(pdata, MMC_RXVLANFRAMES_GB_LO); |
Lendacky, Thomas | c5aa9e3 | 2014-06-05 09:15:06 -0500 | [diff] [blame] | 2539 | |
| 2540 | stats->rxwatchdogerror += |
Lendacky, Thomas | 6026510 | 2014-09-05 18:02:30 -0500 | [diff] [blame] | 2541 | xgbe_mmc_read(pdata, MMC_RXWATCHDOGERROR); |
Lendacky, Thomas | c5aa9e3 | 2014-06-05 09:15:06 -0500 | [diff] [blame] | 2542 | |
| 2543 | /* Un-freeze counters */ |
| 2544 | XGMAC_IOWRITE_BITS(pdata, MMC_CR, MCF, 0); |
| 2545 | } |
| 2546 | |
| 2547 | static void xgbe_config_mmc(struct xgbe_prv_data *pdata) |
| 2548 | { |
| 2549 | /* Set counters to reset on read */ |
| 2550 | XGMAC_IOWRITE_BITS(pdata, MMC_CR, ROR, 1); |
| 2551 | |
| 2552 | /* Reset the counters */ |
| 2553 | XGMAC_IOWRITE_BITS(pdata, MMC_CR, CR, 1); |
| 2554 | } |
| 2555 | |
Lendacky, Thomas | 16edd34 | 2014-11-20 11:03:32 -0600 | [diff] [blame] | 2556 | static void xgbe_prepare_tx_stop(struct xgbe_prv_data *pdata, |
| 2557 | struct xgbe_channel *channel) |
| 2558 | { |
| 2559 | unsigned int tx_dsr, tx_pos, tx_qidx; |
| 2560 | unsigned int tx_status; |
| 2561 | unsigned long tx_timeout; |
| 2562 | |
| 2563 | /* Calculate the status register to read and the position within */ |
| 2564 | if (channel->queue_index < DMA_DSRX_FIRST_QUEUE) { |
| 2565 | tx_dsr = DMA_DSR0; |
| 2566 | tx_pos = (channel->queue_index * DMA_DSR_Q_WIDTH) + |
| 2567 | DMA_DSR0_TPS_START; |
| 2568 | } else { |
| 2569 | tx_qidx = channel->queue_index - DMA_DSRX_FIRST_QUEUE; |
| 2570 | |
| 2571 | tx_dsr = DMA_DSR1 + ((tx_qidx / DMA_DSRX_QPR) * DMA_DSRX_INC); |
| 2572 | tx_pos = ((tx_qidx % DMA_DSRX_QPR) * DMA_DSR_Q_WIDTH) + |
| 2573 | DMA_DSRX_TPS_START; |
| 2574 | } |
| 2575 | |
| 2576 | /* The Tx engine cannot be stopped if it is actively processing |
| 2577 | * descriptors. Wait for the Tx engine to enter the stopped or |
| 2578 | * suspended state. Don't wait forever though... |
| 2579 | */ |
| 2580 | tx_timeout = jiffies + (XGBE_DMA_STOP_TIMEOUT * HZ); |
| 2581 | while (time_before(jiffies, tx_timeout)) { |
| 2582 | tx_status = XGMAC_IOREAD(pdata, tx_dsr); |
| 2583 | tx_status = GET_BITS(tx_status, tx_pos, DMA_DSR_TPS_WIDTH); |
| 2584 | if ((tx_status == DMA_TPS_STOPPED) || |
| 2585 | (tx_status == DMA_TPS_SUSPENDED)) |
| 2586 | break; |
| 2587 | |
| 2588 | usleep_range(500, 1000); |
| 2589 | } |
| 2590 | |
| 2591 | if (!time_before(jiffies, tx_timeout)) |
| 2592 | netdev_info(pdata->netdev, |
| 2593 | "timed out waiting for Tx DMA channel %u to stop\n", |
| 2594 | channel->queue_index); |
| 2595 | } |
| 2596 | |
Lendacky, Thomas | c5aa9e3 | 2014-06-05 09:15:06 -0500 | [diff] [blame] | 2597 | static void xgbe_enable_tx(struct xgbe_prv_data *pdata) |
| 2598 | { |
| 2599 | struct xgbe_channel *channel; |
| 2600 | unsigned int i; |
| 2601 | |
| 2602 | /* Enable each Tx DMA channel */ |
| 2603 | channel = pdata->channel; |
| 2604 | for (i = 0; i < pdata->channel_count; i++, channel++) { |
| 2605 | if (!channel->tx_ring) |
| 2606 | break; |
| 2607 | |
| 2608 | XGMAC_DMA_IOWRITE_BITS(channel, DMA_CH_TCR, ST, 1); |
| 2609 | } |
| 2610 | |
| 2611 | /* Enable each Tx queue */ |
Lendacky, Thomas | 853eb16 | 2014-07-29 08:57:31 -0500 | [diff] [blame] | 2612 | for (i = 0; i < pdata->tx_q_count; i++) |
Lendacky, Thomas | c5aa9e3 | 2014-06-05 09:15:06 -0500 | [diff] [blame] | 2613 | XGMAC_MTL_IOWRITE_BITS(pdata, i, MTL_Q_TQOMR, TXQEN, |
| 2614 | MTL_Q_ENABLED); |
| 2615 | |
| 2616 | /* Enable MAC Tx */ |
| 2617 | XGMAC_IOWRITE_BITS(pdata, MAC_TCR, TE, 1); |
| 2618 | } |
| 2619 | |
| 2620 | static void xgbe_disable_tx(struct xgbe_prv_data *pdata) |
| 2621 | { |
| 2622 | struct xgbe_channel *channel; |
| 2623 | unsigned int i; |
| 2624 | |
Lendacky, Thomas | 16edd34 | 2014-11-20 11:03:32 -0600 | [diff] [blame] | 2625 | /* Prepare for Tx DMA channel stop */ |
| 2626 | channel = pdata->channel; |
| 2627 | for (i = 0; i < pdata->channel_count; i++, channel++) { |
| 2628 | if (!channel->tx_ring) |
| 2629 | break; |
| 2630 | |
| 2631 | xgbe_prepare_tx_stop(pdata, channel); |
| 2632 | } |
| 2633 | |
Lendacky, Thomas | c5aa9e3 | 2014-06-05 09:15:06 -0500 | [diff] [blame] | 2634 | /* Disable MAC Tx */ |
| 2635 | XGMAC_IOWRITE_BITS(pdata, MAC_TCR, TE, 0); |
| 2636 | |
| 2637 | /* Disable each Tx queue */ |
Lendacky, Thomas | 853eb16 | 2014-07-29 08:57:31 -0500 | [diff] [blame] | 2638 | for (i = 0; i < pdata->tx_q_count; i++) |
Lendacky, Thomas | c5aa9e3 | 2014-06-05 09:15:06 -0500 | [diff] [blame] | 2639 | XGMAC_MTL_IOWRITE_BITS(pdata, i, MTL_Q_TQOMR, TXQEN, 0); |
| 2640 | |
| 2641 | /* Disable each Tx DMA channel */ |
| 2642 | channel = pdata->channel; |
| 2643 | for (i = 0; i < pdata->channel_count; i++, channel++) { |
| 2644 | if (!channel->tx_ring) |
| 2645 | break; |
| 2646 | |
| 2647 | XGMAC_DMA_IOWRITE_BITS(channel, DMA_CH_TCR, ST, 0); |
| 2648 | } |
| 2649 | } |
| 2650 | |
| 2651 | static void xgbe_enable_rx(struct xgbe_prv_data *pdata) |
| 2652 | { |
| 2653 | struct xgbe_channel *channel; |
| 2654 | unsigned int reg_val, i; |
| 2655 | |
| 2656 | /* Enable each Rx DMA channel */ |
| 2657 | channel = pdata->channel; |
| 2658 | for (i = 0; i < pdata->channel_count; i++, channel++) { |
| 2659 | if (!channel->rx_ring) |
| 2660 | break; |
| 2661 | |
| 2662 | XGMAC_DMA_IOWRITE_BITS(channel, DMA_CH_RCR, SR, 1); |
| 2663 | } |
| 2664 | |
| 2665 | /* Enable each Rx queue */ |
| 2666 | reg_val = 0; |
Lendacky, Thomas | 853eb16 | 2014-07-29 08:57:31 -0500 | [diff] [blame] | 2667 | for (i = 0; i < pdata->rx_q_count; i++) |
Lendacky, Thomas | c5aa9e3 | 2014-06-05 09:15:06 -0500 | [diff] [blame] | 2668 | reg_val |= (0x02 << (i << 1)); |
| 2669 | XGMAC_IOWRITE(pdata, MAC_RQC0R, reg_val); |
| 2670 | |
| 2671 | /* Enable MAC Rx */ |
| 2672 | XGMAC_IOWRITE_BITS(pdata, MAC_RCR, DCRCC, 1); |
| 2673 | XGMAC_IOWRITE_BITS(pdata, MAC_RCR, CST, 1); |
| 2674 | XGMAC_IOWRITE_BITS(pdata, MAC_RCR, ACS, 1); |
| 2675 | XGMAC_IOWRITE_BITS(pdata, MAC_RCR, RE, 1); |
| 2676 | } |
| 2677 | |
| 2678 | static void xgbe_disable_rx(struct xgbe_prv_data *pdata) |
| 2679 | { |
| 2680 | struct xgbe_channel *channel; |
| 2681 | unsigned int i; |
| 2682 | |
| 2683 | /* Disable MAC Rx */ |
| 2684 | XGMAC_IOWRITE_BITS(pdata, MAC_RCR, DCRCC, 0); |
| 2685 | XGMAC_IOWRITE_BITS(pdata, MAC_RCR, CST, 0); |
| 2686 | XGMAC_IOWRITE_BITS(pdata, MAC_RCR, ACS, 0); |
| 2687 | XGMAC_IOWRITE_BITS(pdata, MAC_RCR, RE, 0); |
| 2688 | |
| 2689 | /* Disable each Rx queue */ |
| 2690 | XGMAC_IOWRITE(pdata, MAC_RQC0R, 0); |
| 2691 | |
| 2692 | /* Disable each Rx DMA channel */ |
| 2693 | channel = pdata->channel; |
| 2694 | for (i = 0; i < pdata->channel_count; i++, channel++) { |
| 2695 | if (!channel->rx_ring) |
| 2696 | break; |
| 2697 | |
| 2698 | XGMAC_DMA_IOWRITE_BITS(channel, DMA_CH_RCR, SR, 0); |
| 2699 | } |
| 2700 | } |
| 2701 | |
| 2702 | static void xgbe_powerup_tx(struct xgbe_prv_data *pdata) |
| 2703 | { |
| 2704 | struct xgbe_channel *channel; |
| 2705 | unsigned int i; |
| 2706 | |
| 2707 | /* Enable each Tx DMA channel */ |
| 2708 | channel = pdata->channel; |
| 2709 | for (i = 0; i < pdata->channel_count; i++, channel++) { |
| 2710 | if (!channel->tx_ring) |
| 2711 | break; |
| 2712 | |
| 2713 | XGMAC_DMA_IOWRITE_BITS(channel, DMA_CH_TCR, ST, 1); |
| 2714 | } |
| 2715 | |
| 2716 | /* Enable MAC Tx */ |
| 2717 | XGMAC_IOWRITE_BITS(pdata, MAC_TCR, TE, 1); |
| 2718 | } |
| 2719 | |
| 2720 | static void xgbe_powerdown_tx(struct xgbe_prv_data *pdata) |
| 2721 | { |
| 2722 | struct xgbe_channel *channel; |
| 2723 | unsigned int i; |
| 2724 | |
Lendacky, Thomas | 16edd34 | 2014-11-20 11:03:32 -0600 | [diff] [blame] | 2725 | /* Prepare for Tx DMA channel stop */ |
| 2726 | channel = pdata->channel; |
| 2727 | for (i = 0; i < pdata->channel_count; i++, channel++) { |
| 2728 | if (!channel->tx_ring) |
| 2729 | break; |
| 2730 | |
| 2731 | xgbe_prepare_tx_stop(pdata, channel); |
| 2732 | } |
| 2733 | |
Lendacky, Thomas | c5aa9e3 | 2014-06-05 09:15:06 -0500 | [diff] [blame] | 2734 | /* Disable MAC Tx */ |
| 2735 | XGMAC_IOWRITE_BITS(pdata, MAC_TCR, TE, 0); |
| 2736 | |
| 2737 | /* Disable each Tx DMA channel */ |
| 2738 | channel = pdata->channel; |
| 2739 | for (i = 0; i < pdata->channel_count; i++, channel++) { |
| 2740 | if (!channel->tx_ring) |
| 2741 | break; |
| 2742 | |
| 2743 | XGMAC_DMA_IOWRITE_BITS(channel, DMA_CH_TCR, ST, 0); |
| 2744 | } |
| 2745 | } |
| 2746 | |
| 2747 | static void xgbe_powerup_rx(struct xgbe_prv_data *pdata) |
| 2748 | { |
| 2749 | struct xgbe_channel *channel; |
| 2750 | unsigned int i; |
| 2751 | |
| 2752 | /* Enable each Rx DMA channel */ |
| 2753 | channel = pdata->channel; |
| 2754 | for (i = 0; i < pdata->channel_count; i++, channel++) { |
| 2755 | if (!channel->rx_ring) |
| 2756 | break; |
| 2757 | |
| 2758 | XGMAC_DMA_IOWRITE_BITS(channel, DMA_CH_RCR, SR, 1); |
| 2759 | } |
| 2760 | } |
| 2761 | |
| 2762 | static void xgbe_powerdown_rx(struct xgbe_prv_data *pdata) |
| 2763 | { |
| 2764 | struct xgbe_channel *channel; |
| 2765 | unsigned int i; |
| 2766 | |
| 2767 | /* Disable each Rx DMA channel */ |
| 2768 | channel = pdata->channel; |
| 2769 | for (i = 0; i < pdata->channel_count; i++, channel++) { |
| 2770 | if (!channel->rx_ring) |
| 2771 | break; |
| 2772 | |
| 2773 | XGMAC_DMA_IOWRITE_BITS(channel, DMA_CH_RCR, SR, 0); |
| 2774 | } |
| 2775 | } |
| 2776 | |
| 2777 | static int xgbe_init(struct xgbe_prv_data *pdata) |
| 2778 | { |
| 2779 | struct xgbe_desc_if *desc_if = &pdata->desc_if; |
| 2780 | int ret; |
| 2781 | |
| 2782 | DBGPR("-->xgbe_init\n"); |
| 2783 | |
| 2784 | /* Flush Tx queues */ |
| 2785 | ret = xgbe_flush_tx_queues(pdata); |
| 2786 | if (ret) |
| 2787 | return ret; |
| 2788 | |
| 2789 | /* |
| 2790 | * Initialize DMA related features |
| 2791 | */ |
| 2792 | xgbe_config_dma_bus(pdata); |
| 2793 | xgbe_config_dma_cache(pdata); |
| 2794 | xgbe_config_osp_mode(pdata); |
| 2795 | xgbe_config_pblx8(pdata); |
| 2796 | xgbe_config_tx_pbl_val(pdata); |
| 2797 | xgbe_config_rx_pbl_val(pdata); |
| 2798 | xgbe_config_rx_coalesce(pdata); |
| 2799 | xgbe_config_tx_coalesce(pdata); |
| 2800 | xgbe_config_rx_buffer_size(pdata); |
| 2801 | xgbe_config_tso_mode(pdata); |
Lendacky, Thomas | 174fd25 | 2014-11-04 16:06:50 -0600 | [diff] [blame] | 2802 | xgbe_config_sph_mode(pdata); |
Lendacky, Thomas | 5b9dfe2 | 2014-11-04 16:07:02 -0600 | [diff] [blame] | 2803 | xgbe_config_rss(pdata); |
Lendacky, Thomas | c5aa9e3 | 2014-06-05 09:15:06 -0500 | [diff] [blame] | 2804 | desc_if->wrapper_tx_desc_init(pdata); |
| 2805 | desc_if->wrapper_rx_desc_init(pdata); |
| 2806 | xgbe_enable_dma_interrupts(pdata); |
| 2807 | |
| 2808 | /* |
| 2809 | * Initialize MTL related features |
| 2810 | */ |
| 2811 | xgbe_config_mtl_mode(pdata); |
Lendacky, Thomas | fca2d99 | 2014-07-29 08:57:55 -0500 | [diff] [blame] | 2812 | xgbe_config_queue_mapping(pdata); |
Lendacky, Thomas | c5aa9e3 | 2014-06-05 09:15:06 -0500 | [diff] [blame] | 2813 | xgbe_config_tsf_mode(pdata, pdata->tx_sf_mode); |
| 2814 | xgbe_config_rsf_mode(pdata, pdata->rx_sf_mode); |
| 2815 | xgbe_config_tx_threshold(pdata, pdata->tx_threshold); |
| 2816 | xgbe_config_rx_threshold(pdata, pdata->rx_threshold); |
| 2817 | xgbe_config_tx_fifo_size(pdata); |
| 2818 | xgbe_config_rx_fifo_size(pdata); |
| 2819 | xgbe_config_flow_control_threshold(pdata); |
Lendacky, Thomas | c5aa9e3 | 2014-06-05 09:15:06 -0500 | [diff] [blame] | 2820 | /*TODO: Error Packet and undersized good Packet forwarding enable |
| 2821 | (FEP and FUP) |
| 2822 | */ |
Lendacky, Thomas | fca2d99 | 2014-07-29 08:57:55 -0500 | [diff] [blame] | 2823 | xgbe_config_dcb_tc(pdata); |
| 2824 | xgbe_config_dcb_pfc(pdata); |
Lendacky, Thomas | c5aa9e3 | 2014-06-05 09:15:06 -0500 | [diff] [blame] | 2825 | xgbe_enable_mtl_interrupts(pdata); |
| 2826 | |
Lendacky, Thomas | c5aa9e3 | 2014-06-05 09:15:06 -0500 | [diff] [blame] | 2827 | /* |
| 2828 | * Initialize MAC related features |
| 2829 | */ |
| 2830 | xgbe_config_mac_address(pdata); |
Lendacky, Thomas | b876382 | 2015-04-09 12:11:57 -0500 | [diff] [blame] | 2831 | xgbe_config_rx_mode(pdata); |
Lendacky, Thomas | c5aa9e3 | 2014-06-05 09:15:06 -0500 | [diff] [blame] | 2832 | xgbe_config_jumbo_enable(pdata); |
| 2833 | xgbe_config_flow_control(pdata); |
Lendacky, Thomas | 916102c | 2015-01-16 12:46:45 -0600 | [diff] [blame] | 2834 | xgbe_config_mac_speed(pdata); |
Lendacky, Thomas | c5aa9e3 | 2014-06-05 09:15:06 -0500 | [diff] [blame] | 2835 | xgbe_config_checksum_offload(pdata); |
| 2836 | xgbe_config_vlan_support(pdata); |
| 2837 | xgbe_config_mmc(pdata); |
| 2838 | xgbe_enable_mac_interrupts(pdata); |
| 2839 | |
| 2840 | DBGPR("<--xgbe_init\n"); |
| 2841 | |
| 2842 | return 0; |
| 2843 | } |
| 2844 | |
| 2845 | void xgbe_init_function_ptrs_dev(struct xgbe_hw_if *hw_if) |
| 2846 | { |
| 2847 | DBGPR("-->xgbe_init_function_ptrs\n"); |
| 2848 | |
| 2849 | hw_if->tx_complete = xgbe_tx_complete; |
| 2850 | |
Lendacky, Thomas | c5aa9e3 | 2014-06-05 09:15:06 -0500 | [diff] [blame] | 2851 | hw_if->set_mac_address = xgbe_set_mac_address; |
Lendacky, Thomas | b876382 | 2015-04-09 12:11:57 -0500 | [diff] [blame] | 2852 | hw_if->config_rx_mode = xgbe_config_rx_mode; |
Lendacky, Thomas | c5aa9e3 | 2014-06-05 09:15:06 -0500 | [diff] [blame] | 2853 | |
| 2854 | hw_if->enable_rx_csum = xgbe_enable_rx_csum; |
| 2855 | hw_if->disable_rx_csum = xgbe_disable_rx_csum; |
| 2856 | |
| 2857 | hw_if->enable_rx_vlan_stripping = xgbe_enable_rx_vlan_stripping; |
| 2858 | hw_if->disable_rx_vlan_stripping = xgbe_disable_rx_vlan_stripping; |
Lendacky, Thomas | 801c62d | 2014-06-24 16:19:24 -0500 | [diff] [blame] | 2859 | hw_if->enable_rx_vlan_filtering = xgbe_enable_rx_vlan_filtering; |
| 2860 | hw_if->disable_rx_vlan_filtering = xgbe_disable_rx_vlan_filtering; |
| 2861 | hw_if->update_vlan_hash_table = xgbe_update_vlan_hash_table; |
Lendacky, Thomas | c5aa9e3 | 2014-06-05 09:15:06 -0500 | [diff] [blame] | 2862 | |
| 2863 | hw_if->read_mmd_regs = xgbe_read_mmd_regs; |
| 2864 | hw_if->write_mmd_regs = xgbe_write_mmd_regs; |
| 2865 | |
| 2866 | hw_if->set_gmii_speed = xgbe_set_gmii_speed; |
| 2867 | hw_if->set_gmii_2500_speed = xgbe_set_gmii_2500_speed; |
| 2868 | hw_if->set_xgmii_speed = xgbe_set_xgmii_speed; |
| 2869 | |
| 2870 | hw_if->enable_tx = xgbe_enable_tx; |
| 2871 | hw_if->disable_tx = xgbe_disable_tx; |
| 2872 | hw_if->enable_rx = xgbe_enable_rx; |
| 2873 | hw_if->disable_rx = xgbe_disable_rx; |
| 2874 | |
| 2875 | hw_if->powerup_tx = xgbe_powerup_tx; |
| 2876 | hw_if->powerdown_tx = xgbe_powerdown_tx; |
| 2877 | hw_if->powerup_rx = xgbe_powerup_rx; |
| 2878 | hw_if->powerdown_rx = xgbe_powerdown_rx; |
| 2879 | |
Lendacky, Thomas | a9d4198 | 2014-11-04 16:06:32 -0600 | [diff] [blame] | 2880 | hw_if->dev_xmit = xgbe_dev_xmit; |
Lendacky, Thomas | c5aa9e3 | 2014-06-05 09:15:06 -0500 | [diff] [blame] | 2881 | hw_if->dev_read = xgbe_dev_read; |
| 2882 | hw_if->enable_int = xgbe_enable_int; |
| 2883 | hw_if->disable_int = xgbe_disable_int; |
| 2884 | hw_if->init = xgbe_init; |
| 2885 | hw_if->exit = xgbe_exit; |
| 2886 | |
| 2887 | /* Descriptor related Sequences have to be initialized here */ |
| 2888 | hw_if->tx_desc_init = xgbe_tx_desc_init; |
| 2889 | hw_if->rx_desc_init = xgbe_rx_desc_init; |
| 2890 | hw_if->tx_desc_reset = xgbe_tx_desc_reset; |
| 2891 | hw_if->rx_desc_reset = xgbe_rx_desc_reset; |
| 2892 | hw_if->is_last_desc = xgbe_is_last_desc; |
| 2893 | hw_if->is_context_desc = xgbe_is_context_desc; |
Lendacky, Thomas | 16958a2 | 2014-11-20 11:04:08 -0600 | [diff] [blame] | 2894 | hw_if->tx_start_xmit = xgbe_tx_start_xmit; |
Lendacky, Thomas | c5aa9e3 | 2014-06-05 09:15:06 -0500 | [diff] [blame] | 2895 | |
| 2896 | /* For FLOW ctrl */ |
| 2897 | hw_if->config_tx_flow_control = xgbe_config_tx_flow_control; |
| 2898 | hw_if->config_rx_flow_control = xgbe_config_rx_flow_control; |
| 2899 | |
| 2900 | /* For RX coalescing */ |
| 2901 | hw_if->config_rx_coalesce = xgbe_config_rx_coalesce; |
| 2902 | hw_if->config_tx_coalesce = xgbe_config_tx_coalesce; |
| 2903 | hw_if->usec_to_riwt = xgbe_usec_to_riwt; |
| 2904 | hw_if->riwt_to_usec = xgbe_riwt_to_usec; |
| 2905 | |
| 2906 | /* For RX and TX threshold config */ |
| 2907 | hw_if->config_rx_threshold = xgbe_config_rx_threshold; |
| 2908 | hw_if->config_tx_threshold = xgbe_config_tx_threshold; |
| 2909 | |
| 2910 | /* For RX and TX Store and Forward Mode config */ |
| 2911 | hw_if->config_rsf_mode = xgbe_config_rsf_mode; |
| 2912 | hw_if->config_tsf_mode = xgbe_config_tsf_mode; |
| 2913 | |
| 2914 | /* For TX DMA Operating on Second Frame config */ |
| 2915 | hw_if->config_osp_mode = xgbe_config_osp_mode; |
| 2916 | |
| 2917 | /* For RX and TX PBL config */ |
| 2918 | hw_if->config_rx_pbl_val = xgbe_config_rx_pbl_val; |
| 2919 | hw_if->get_rx_pbl_val = xgbe_get_rx_pbl_val; |
| 2920 | hw_if->config_tx_pbl_val = xgbe_config_tx_pbl_val; |
| 2921 | hw_if->get_tx_pbl_val = xgbe_get_tx_pbl_val; |
| 2922 | hw_if->config_pblx8 = xgbe_config_pblx8; |
| 2923 | |
| 2924 | /* For MMC statistics support */ |
| 2925 | hw_if->tx_mmc_int = xgbe_tx_mmc_int; |
| 2926 | hw_if->rx_mmc_int = xgbe_rx_mmc_int; |
| 2927 | hw_if->read_mmc_stats = xgbe_read_mmc_stats; |
| 2928 | |
Lendacky, Thomas | 23e4eef | 2014-07-29 08:57:19 -0500 | [diff] [blame] | 2929 | /* For PTP config */ |
| 2930 | hw_if->config_tstamp = xgbe_config_tstamp; |
| 2931 | hw_if->update_tstamp_addend = xgbe_update_tstamp_addend; |
| 2932 | hw_if->set_tstamp_time = xgbe_set_tstamp_time; |
| 2933 | hw_if->get_tstamp_time = xgbe_get_tstamp_time; |
| 2934 | hw_if->get_tx_tstamp = xgbe_get_tx_tstamp; |
| 2935 | |
Lendacky, Thomas | fca2d99 | 2014-07-29 08:57:55 -0500 | [diff] [blame] | 2936 | /* For Data Center Bridging config */ |
| 2937 | hw_if->config_dcb_tc = xgbe_config_dcb_tc; |
| 2938 | hw_if->config_dcb_pfc = xgbe_config_dcb_pfc; |
| 2939 | |
Lendacky, Thomas | 5b9dfe2 | 2014-11-04 16:07:02 -0600 | [diff] [blame] | 2940 | /* For Receive Side Scaling */ |
| 2941 | hw_if->enable_rss = xgbe_enable_rss; |
| 2942 | hw_if->disable_rss = xgbe_disable_rss; |
Lendacky, Thomas | f6ac862 | 2014-11-04 16:07:23 -0600 | [diff] [blame] | 2943 | hw_if->set_rss_hash_key = xgbe_set_rss_hash_key; |
| 2944 | hw_if->set_rss_lookup_table = xgbe_set_rss_lookup_table; |
Lendacky, Thomas | 5b9dfe2 | 2014-11-04 16:07:02 -0600 | [diff] [blame] | 2945 | |
Lendacky, Thomas | c5aa9e3 | 2014-06-05 09:15:06 -0500 | [diff] [blame] | 2946 | DBGPR("<--xgbe_init_function_ptrs\n"); |
| 2947 | } |