blob: 94c526669a4db68966041f8372de392f80f13f88 [file] [log] [blame]
Luis R. Rodriguezf078f202008-08-04 00:16:41 -07001/*
2 * Copyright (c) 2008 Atheros Communications Inc.
3 *
4 * Permission to use, copy, modify, and/or distribute this software for any
5 * purpose with or without fee is hereby granted, provided that the above
6 * copyright notice and this permission notice appear in all copies.
7 *
8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
15 */
16
Luis R. Rodriguezf078f202008-08-04 00:16:41 -070017#include <linux/nl80211.h>
18#include "core.h"
Benoit PAPILLAULT392dff82008-11-06 22:26:49 +010019#include "reg.h"
Sujith2a163c62008-11-28 22:21:08 +053020#include "hw.h"
Luis R. Rodriguezf078f202008-08-04 00:16:41 -070021
22#define ATH_PCI_VERSION "0.1"
23
Luis R. Rodriguezf078f202008-08-04 00:16:41 -070024static char *dev_info = "ath9k";
25
26MODULE_AUTHOR("Atheros Communications");
27MODULE_DESCRIPTION("Support for Atheros 802.11n wireless LAN cards.");
28MODULE_SUPPORTED_DEVICE("Atheros 802.11n WLAN cards");
29MODULE_LICENSE("Dual BSD/GPL");
30
31static struct pci_device_id ath_pci_id_table[] __devinitdata = {
32 { PCI_VDEVICE(ATHEROS, 0x0023) }, /* PCI */
33 { PCI_VDEVICE(ATHEROS, 0x0024) }, /* PCI-E */
34 { PCI_VDEVICE(ATHEROS, 0x0027) }, /* PCI */
35 { PCI_VDEVICE(ATHEROS, 0x0029) }, /* PCI */
36 { PCI_VDEVICE(ATHEROS, 0x002A) }, /* PCI-E */
Senthil Balasubramaniane7594072008-12-08 19:43:48 +053037 { PCI_VDEVICE(ATHEROS, 0x002B) }, /* PCI-E */
Luis R. Rodriguezf078f202008-08-04 00:16:41 -070038 { 0 }
39};
40
Sujith9757d552008-11-04 18:25:27 +053041static void ath_detach(struct ath_softc *sc);
42
Sujithff37e332008-11-24 12:07:55 +053043/* return bus cachesize in 4B word units */
44
45static void bus_read_cachesize(struct ath_softc *sc, int *csz)
46{
47 u8 u8tmp;
48
49 pci_read_config_byte(sc->pdev, PCI_CACHE_LINE_SIZE, (u8 *)&u8tmp);
50 *csz = (int)u8tmp;
51
52 /*
53 * This check was put in to avoid "unplesant" consequences if
54 * the bootrom has not fully initialized all PCI devices.
55 * Sometimes the cache line size register is not set
56 */
57
58 if (*csz == 0)
59 *csz = DEFAULT_CACHELINE >> 2; /* Use the default size */
60}
61
62static void ath_setcurmode(struct ath_softc *sc, enum wireless_mode mode)
63{
Sujith9d8eed12008-12-12 11:59:07 +053064 sc->cur_rate_table = sc->hw_rate_table[mode];
Sujithff37e332008-11-24 12:07:55 +053065 /*
66 * All protection frames are transmited at 2Mb/s for
67 * 11g, otherwise at 1Mb/s.
68 * XXX select protection rate index from rate table.
69 */
70 sc->sc_protrix = (mode == ATH9K_MODE_11G ? 1 : 0);
71}
72
73static enum wireless_mode ath_chan2mode(struct ath9k_channel *chan)
74{
75 if (chan->chanmode == CHANNEL_A)
76 return ATH9K_MODE_11A;
77 else if (chan->chanmode == CHANNEL_G)
78 return ATH9K_MODE_11G;
79 else if (chan->chanmode == CHANNEL_B)
80 return ATH9K_MODE_11B;
81 else if (chan->chanmode == CHANNEL_A_HT20)
82 return ATH9K_MODE_11NA_HT20;
83 else if (chan->chanmode == CHANNEL_G_HT20)
84 return ATH9K_MODE_11NG_HT20;
85 else if (chan->chanmode == CHANNEL_A_HT40PLUS)
86 return ATH9K_MODE_11NA_HT40PLUS;
87 else if (chan->chanmode == CHANNEL_A_HT40MINUS)
88 return ATH9K_MODE_11NA_HT40MINUS;
89 else if (chan->chanmode == CHANNEL_G_HT40PLUS)
90 return ATH9K_MODE_11NG_HT40PLUS;
91 else if (chan->chanmode == CHANNEL_G_HT40MINUS)
92 return ATH9K_MODE_11NG_HT40MINUS;
93
94 WARN_ON(1); /* should not get here */
95
96 return ATH9K_MODE_11B;
97}
98
99static void ath_update_txpow(struct ath_softc *sc)
100{
101 struct ath_hal *ah = sc->sc_ah;
102 u32 txpow;
103
104 if (sc->sc_curtxpow != sc->sc_config.txpowlimit) {
105 ath9k_hw_set_txpowerlimit(ah, sc->sc_config.txpowlimit);
106 /* read back in case value is clamped */
107 ath9k_hw_getcapability(ah, ATH9K_CAP_TXPOW, 1, &txpow);
108 sc->sc_curtxpow = txpow;
109 }
110}
111
112static u8 parse_mpdudensity(u8 mpdudensity)
113{
114 /*
115 * 802.11n D2.0 defined values for "Minimum MPDU Start Spacing":
116 * 0 for no restriction
117 * 1 for 1/4 us
118 * 2 for 1/2 us
119 * 3 for 1 us
120 * 4 for 2 us
121 * 5 for 4 us
122 * 6 for 8 us
123 * 7 for 16 us
124 */
125 switch (mpdudensity) {
126 case 0:
127 return 0;
128 case 1:
129 case 2:
130 case 3:
131 /* Our lower layer calculations limit our precision to
132 1 microsecond */
133 return 1;
134 case 4:
135 return 2;
136 case 5:
137 return 4;
138 case 6:
139 return 8;
140 case 7:
141 return 16;
142 default:
143 return 0;
144 }
145}
146
147static void ath_setup_rates(struct ath_softc *sc, enum ieee80211_band band)
148{
149 struct ath_rate_table *rate_table = NULL;
150 struct ieee80211_supported_band *sband;
151 struct ieee80211_rate *rate;
152 int i, maxrates;
153
154 switch (band) {
155 case IEEE80211_BAND_2GHZ:
156 rate_table = sc->hw_rate_table[ATH9K_MODE_11G];
157 break;
158 case IEEE80211_BAND_5GHZ:
159 rate_table = sc->hw_rate_table[ATH9K_MODE_11A];
160 break;
161 default:
162 break;
163 }
164
165 if (rate_table == NULL)
166 return;
167
168 sband = &sc->sbands[band];
169 rate = sc->rates[band];
170
171 if (rate_table->rate_cnt > ATH_RATE_MAX)
172 maxrates = ATH_RATE_MAX;
173 else
174 maxrates = rate_table->rate_cnt;
175
176 for (i = 0; i < maxrates; i++) {
177 rate[i].bitrate = rate_table->info[i].ratekbps / 100;
178 rate[i].hw_value = rate_table->info[i].ratecode;
179 sband->n_bitrates++;
Sujith04bd4632008-11-28 22:18:05 +0530180 DPRINTF(sc, ATH_DBG_CONFIG, "Rate: %2dMbps, ratecode: %2d\n",
181 rate[i].bitrate / 10, rate[i].hw_value);
Sujithff37e332008-11-24 12:07:55 +0530182 }
183}
184
185static int ath_setup_channels(struct ath_softc *sc)
186{
187 struct ath_hal *ah = sc->sc_ah;
188 int nchan, i, a = 0, b = 0;
189 u8 regclassids[ATH_REGCLASSIDS_MAX];
190 u32 nregclass = 0;
191 struct ieee80211_supported_band *band_2ghz;
192 struct ieee80211_supported_band *band_5ghz;
193 struct ieee80211_channel *chan_2ghz;
194 struct ieee80211_channel *chan_5ghz;
195 struct ath9k_channel *c;
196
197 /* Fill in ah->ah_channels */
198 if (!ath9k_regd_init_channels(ah, ATH_CHAN_MAX, (u32 *)&nchan,
199 regclassids, ATH_REGCLASSIDS_MAX,
200 &nregclass, CTRY_DEFAULT, false, 1)) {
201 u32 rd = ah->ah_currentRD;
202 DPRINTF(sc, ATH_DBG_FATAL,
Sujith04bd4632008-11-28 22:18:05 +0530203 "Unable to collect channel list; "
Sujithff37e332008-11-24 12:07:55 +0530204 "regdomain likely %u country code %u\n",
Sujith04bd4632008-11-28 22:18:05 +0530205 rd, CTRY_DEFAULT);
Sujithff37e332008-11-24 12:07:55 +0530206 return -EINVAL;
207 }
208
209 band_2ghz = &sc->sbands[IEEE80211_BAND_2GHZ];
210 band_5ghz = &sc->sbands[IEEE80211_BAND_5GHZ];
211 chan_2ghz = sc->channels[IEEE80211_BAND_2GHZ];
212 chan_5ghz = sc->channels[IEEE80211_BAND_5GHZ];
213
214 for (i = 0; i < nchan; i++) {
215 c = &ah->ah_channels[i];
216 if (IS_CHAN_2GHZ(c)) {
217 chan_2ghz[a].band = IEEE80211_BAND_2GHZ;
218 chan_2ghz[a].center_freq = c->channel;
219 chan_2ghz[a].max_power = c->maxTxPower;
220
221 if (c->privFlags & CHANNEL_DISALLOW_ADHOC)
222 chan_2ghz[a].flags |= IEEE80211_CHAN_NO_IBSS;
223 if (c->channelFlags & CHANNEL_PASSIVE)
224 chan_2ghz[a].flags |= IEEE80211_CHAN_PASSIVE_SCAN;
225
226 band_2ghz->n_channels = ++a;
227
Sujith04bd4632008-11-28 22:18:05 +0530228 DPRINTF(sc, ATH_DBG_CONFIG, "2MHz channel: %d, "
Sujithff37e332008-11-24 12:07:55 +0530229 "channelFlags: 0x%x\n",
Sujith04bd4632008-11-28 22:18:05 +0530230 c->channel, c->channelFlags);
Sujithff37e332008-11-24 12:07:55 +0530231 } else if (IS_CHAN_5GHZ(c)) {
232 chan_5ghz[b].band = IEEE80211_BAND_5GHZ;
233 chan_5ghz[b].center_freq = c->channel;
234 chan_5ghz[b].max_power = c->maxTxPower;
235
236 if (c->privFlags & CHANNEL_DISALLOW_ADHOC)
237 chan_5ghz[b].flags |= IEEE80211_CHAN_NO_IBSS;
238 if (c->channelFlags & CHANNEL_PASSIVE)
239 chan_5ghz[b].flags |= IEEE80211_CHAN_PASSIVE_SCAN;
240
241 band_5ghz->n_channels = ++b;
242
Sujith04bd4632008-11-28 22:18:05 +0530243 DPRINTF(sc, ATH_DBG_CONFIG, "5MHz channel: %d, "
Sujithff37e332008-11-24 12:07:55 +0530244 "channelFlags: 0x%x\n",
Sujith04bd4632008-11-28 22:18:05 +0530245 c->channel, c->channelFlags);
Sujithff37e332008-11-24 12:07:55 +0530246 }
247 }
248
249 return 0;
250}
251
252/*
253 * Set/change channels. If the channel is really being changed, it's done
254 * by reseting the chip. To accomplish this we must first cleanup any pending
255 * DMA, then restart stuff.
256*/
257static int ath_set_channel(struct ath_softc *sc, struct ath9k_channel *hchan)
258{
259 struct ath_hal *ah = sc->sc_ah;
260 bool fastcc = true, stopped;
261
262 if (sc->sc_flags & SC_OP_INVALID)
263 return -EIO;
264
Sujithff37e332008-11-24 12:07:55 +0530265 if (hchan->channel != sc->sc_ah->ah_curchan->channel ||
266 hchan->channelFlags != sc->sc_ah->ah_curchan->channelFlags ||
267 (sc->sc_flags & SC_OP_CHAINMASK_UPDATE) ||
268 (sc->sc_flags & SC_OP_FULL_RESET)) {
269 int status;
270 /*
271 * This is only performed if the channel settings have
272 * actually changed.
273 *
274 * To switch channels clear any pending DMA operations;
275 * wait long enough for the RX fifo to drain, reset the
276 * hardware at the new frequency, and then re-enable
277 * the relevant bits of the h/w.
278 */
Sujith04bd4632008-11-28 22:18:05 +0530279 ath9k_hw_set_interrupts(ah, 0);
280 ath_draintxq(sc, false);
281 stopped = ath_stoprecv(sc);
Sujithff37e332008-11-24 12:07:55 +0530282
283 /* XXX: do not flush receive queue here. We don't want
284 * to flush data frames already in queue because of
285 * changing channel. */
286
287 if (!stopped || (sc->sc_flags & SC_OP_FULL_RESET))
288 fastcc = false;
289
Sujith99405f92008-11-24 12:08:35 +0530290 DPRINTF(sc, ATH_DBG_CONFIG,
Sujith04bd4632008-11-28 22:18:05 +0530291 "(%u MHz) -> (%u MHz), cflags:%x, chanwidth: %d\n",
Sujith99405f92008-11-24 12:08:35 +0530292 sc->sc_ah->ah_curchan->channel,
293 hchan->channel, hchan->channelFlags, sc->tx_chan_width);
294
Sujithff37e332008-11-24 12:07:55 +0530295 spin_lock_bh(&sc->sc_resetlock);
Sujith99405f92008-11-24 12:08:35 +0530296 if (!ath9k_hw_reset(ah, hchan, sc->tx_chan_width,
Sujithff37e332008-11-24 12:07:55 +0530297 sc->sc_tx_chainmask, sc->sc_rx_chainmask,
298 sc->sc_ht_extprotspacing, fastcc, &status)) {
299 DPRINTF(sc, ATH_DBG_FATAL,
Sujith04bd4632008-11-28 22:18:05 +0530300 "Unable to reset channel %u (%uMhz) "
301 "flags 0x%x hal status %u\n",
Sujithff37e332008-11-24 12:07:55 +0530302 ath9k_hw_mhz2ieee(ah, hchan->channel,
303 hchan->channelFlags),
304 hchan->channel, hchan->channelFlags, status);
305 spin_unlock_bh(&sc->sc_resetlock);
306 return -EIO;
307 }
308 spin_unlock_bh(&sc->sc_resetlock);
309
310 sc->sc_flags &= ~SC_OP_CHAINMASK_UPDATE;
311 sc->sc_flags &= ~SC_OP_FULL_RESET;
312
313 if (ath_startrecv(sc) != 0) {
314 DPRINTF(sc, ATH_DBG_FATAL,
Sujith04bd4632008-11-28 22:18:05 +0530315 "Unable to restart recv logic\n");
Sujithff37e332008-11-24 12:07:55 +0530316 return -EIO;
317 }
318
319 ath_setcurmode(sc, ath_chan2mode(hchan));
320 ath_update_txpow(sc);
321 ath9k_hw_set_interrupts(ah, sc->sc_imask);
322 }
323 return 0;
324}
325
326/*
327 * This routine performs the periodic noise floor calibration function
328 * that is used to adjust and optimize the chip performance. This
329 * takes environmental changes (location, temperature) into account.
330 * When the task is complete, it reschedules itself depending on the
331 * appropriate interval that was calculated.
332 */
333static void ath_ani_calibrate(unsigned long data)
334{
335 struct ath_softc *sc;
336 struct ath_hal *ah;
337 bool longcal = false;
338 bool shortcal = false;
339 bool aniflag = false;
340 unsigned int timestamp = jiffies_to_msecs(jiffies);
341 u32 cal_interval;
342
343 sc = (struct ath_softc *)data;
344 ah = sc->sc_ah;
345
346 /*
347 * don't calibrate when we're scanning.
348 * we are most likely not on our home channel.
349 */
Sujithb77f4832008-12-07 21:44:03 +0530350 if (sc->rx.rxfilter & FIF_BCN_PRBRESP_PROMISC)
Sujithff37e332008-11-24 12:07:55 +0530351 return;
352
353 /* Long calibration runs independently of short calibration. */
354 if ((timestamp - sc->sc_ani.sc_longcal_timer) >= ATH_LONG_CALINTERVAL) {
355 longcal = true;
Sujith04bd4632008-11-28 22:18:05 +0530356 DPRINTF(sc, ATH_DBG_ANI, "longcal @%lu\n", jiffies);
Sujithff37e332008-11-24 12:07:55 +0530357 sc->sc_ani.sc_longcal_timer = timestamp;
358 }
359
360 /* Short calibration applies only while sc_caldone is false */
361 if (!sc->sc_ani.sc_caldone) {
362 if ((timestamp - sc->sc_ani.sc_shortcal_timer) >=
363 ATH_SHORT_CALINTERVAL) {
364 shortcal = true;
Sujith04bd4632008-11-28 22:18:05 +0530365 DPRINTF(sc, ATH_DBG_ANI, "shortcal @%lu\n", jiffies);
Sujithff37e332008-11-24 12:07:55 +0530366 sc->sc_ani.sc_shortcal_timer = timestamp;
367 sc->sc_ani.sc_resetcal_timer = timestamp;
368 }
369 } else {
370 if ((timestamp - sc->sc_ani.sc_resetcal_timer) >=
371 ATH_RESTART_CALINTERVAL) {
372 ath9k_hw_reset_calvalid(ah, ah->ah_curchan,
373 &sc->sc_ani.sc_caldone);
374 if (sc->sc_ani.sc_caldone)
375 sc->sc_ani.sc_resetcal_timer = timestamp;
376 }
377 }
378
379 /* Verify whether we must check ANI */
380 if ((timestamp - sc->sc_ani.sc_checkani_timer) >=
381 ATH_ANI_POLLINTERVAL) {
382 aniflag = true;
383 sc->sc_ani.sc_checkani_timer = timestamp;
384 }
385
386 /* Skip all processing if there's nothing to do. */
387 if (longcal || shortcal || aniflag) {
388 /* Call ANI routine if necessary */
389 if (aniflag)
390 ath9k_hw_ani_monitor(ah, &sc->sc_halstats,
391 ah->ah_curchan);
392
393 /* Perform calibration if necessary */
394 if (longcal || shortcal) {
395 bool iscaldone = false;
396
397 if (ath9k_hw_calibrate(ah, ah->ah_curchan,
398 sc->sc_rx_chainmask, longcal,
399 &iscaldone)) {
400 if (longcal)
401 sc->sc_ani.sc_noise_floor =
402 ath9k_hw_getchan_noise(ah,
403 ah->ah_curchan);
404
405 DPRINTF(sc, ATH_DBG_ANI,
Sujith04bd4632008-11-28 22:18:05 +0530406 "calibrate chan %u/%x nf: %d\n",
Sujithff37e332008-11-24 12:07:55 +0530407 ah->ah_curchan->channel,
408 ah->ah_curchan->channelFlags,
409 sc->sc_ani.sc_noise_floor);
410 } else {
411 DPRINTF(sc, ATH_DBG_ANY,
Sujith04bd4632008-11-28 22:18:05 +0530412 "calibrate chan %u/%x failed\n",
Sujithff37e332008-11-24 12:07:55 +0530413 ah->ah_curchan->channel,
414 ah->ah_curchan->channelFlags);
415 }
416 sc->sc_ani.sc_caldone = iscaldone;
417 }
418 }
419
420 /*
421 * Set timer interval based on previous results.
422 * The interval must be the shortest necessary to satisfy ANI,
423 * short calibration and long calibration.
424 */
Sujithaac92072008-12-02 18:37:54 +0530425 cal_interval = ATH_LONG_CALINTERVAL;
426 if (sc->sc_ah->ah_config.enable_ani)
427 cal_interval = min(cal_interval, (u32)ATH_ANI_POLLINTERVAL);
Sujithff37e332008-11-24 12:07:55 +0530428 if (!sc->sc_ani.sc_caldone)
429 cal_interval = min(cal_interval, (u32)ATH_SHORT_CALINTERVAL);
430
431 mod_timer(&sc->sc_ani.timer, jiffies + msecs_to_jiffies(cal_interval));
432}
433
434/*
435 * Update tx/rx chainmask. For legacy association,
436 * hard code chainmask to 1x1, for 11n association, use
437 * the chainmask configuration.
438 */
439static void ath_update_chainmask(struct ath_softc *sc, int is_ht)
440{
441 sc->sc_flags |= SC_OP_CHAINMASK_UPDATE;
442 if (is_ht) {
443 sc->sc_tx_chainmask = sc->sc_ah->ah_caps.tx_chainmask;
444 sc->sc_rx_chainmask = sc->sc_ah->ah_caps.rx_chainmask;
445 } else {
446 sc->sc_tx_chainmask = 1;
447 sc->sc_rx_chainmask = 1;
448 }
449
Sujith04bd4632008-11-28 22:18:05 +0530450 DPRINTF(sc, ATH_DBG_CONFIG, "tx chmask: %d, rx chmask: %d\n",
451 sc->sc_tx_chainmask, sc->sc_rx_chainmask);
Sujithff37e332008-11-24 12:07:55 +0530452}
453
454static void ath_node_attach(struct ath_softc *sc, struct ieee80211_sta *sta)
455{
456 struct ath_node *an;
457
458 an = (struct ath_node *)sta->drv_priv;
459
460 if (sc->sc_flags & SC_OP_TXAGGR)
461 ath_tx_node_init(sc, an);
462
463 an->maxampdu = 1 << (IEEE80211_HTCAP_MAXRXAMPDU_FACTOR +
464 sta->ht_cap.ampdu_factor);
465 an->mpdudensity = parse_mpdudensity(sta->ht_cap.ampdu_density);
466}
467
468static void ath_node_detach(struct ath_softc *sc, struct ieee80211_sta *sta)
469{
470 struct ath_node *an = (struct ath_node *)sta->drv_priv;
471
472 if (sc->sc_flags & SC_OP_TXAGGR)
473 ath_tx_node_cleanup(sc, an);
474}
475
476static void ath9k_tasklet(unsigned long data)
477{
478 struct ath_softc *sc = (struct ath_softc *)data;
479 u32 status = sc->sc_intrstatus;
480
481 if (status & ATH9K_INT_FATAL) {
482 /* need a chip reset */
483 ath_reset(sc, false);
484 return;
485 } else {
486
487 if (status &
488 (ATH9K_INT_RX | ATH9K_INT_RXEOL | ATH9K_INT_RXORN)) {
Sujithb77f4832008-12-07 21:44:03 +0530489 spin_lock_bh(&sc->rx.rxflushlock);
Sujithff37e332008-11-24 12:07:55 +0530490 ath_rx_tasklet(sc, 0);
Sujithb77f4832008-12-07 21:44:03 +0530491 spin_unlock_bh(&sc->rx.rxflushlock);
Sujithff37e332008-11-24 12:07:55 +0530492 }
493 /* XXX: optimize this */
494 if (status & ATH9K_INT_TX)
495 ath_tx_tasklet(sc);
496 }
497
498 /* re-enable hardware interrupt */
499 ath9k_hw_set_interrupts(sc->sc_ah, sc->sc_imask);
500}
501
502static irqreturn_t ath_isr(int irq, void *dev)
503{
504 struct ath_softc *sc = dev;
505 struct ath_hal *ah = sc->sc_ah;
506 enum ath9k_int status;
507 bool sched = false;
508
509 do {
510 if (sc->sc_flags & SC_OP_INVALID) {
511 /*
512 * The hardware is not ready/present, don't
513 * touch anything. Note this can happen early
514 * on if the IRQ is shared.
515 */
516 return IRQ_NONE;
517 }
518 if (!ath9k_hw_intrpend(ah)) { /* shared irq, not for us */
519 return IRQ_NONE;
520 }
521
522 /*
523 * Figure out the reason(s) for the interrupt. Note
524 * that the hal returns a pseudo-ISR that may include
525 * bits we haven't explicitly enabled so we mask the
526 * value to insure we only process bits we requested.
527 */
528 ath9k_hw_getisr(ah, &status); /* NB: clears ISR too */
529
530 status &= sc->sc_imask; /* discard unasked-for bits */
531
532 /*
533 * If there are no status bits set, then this interrupt was not
534 * for me (should have been caught above).
535 */
536 if (!status)
537 return IRQ_NONE;
538
539 sc->sc_intrstatus = status;
540
541 if (status & ATH9K_INT_FATAL) {
542 /* need a chip reset */
543 sched = true;
544 } else if (status & ATH9K_INT_RXORN) {
545 /* need a chip reset */
546 sched = true;
547 } else {
548 if (status & ATH9K_INT_SWBA) {
549 /* schedule a tasklet for beacon handling */
550 tasklet_schedule(&sc->bcon_tasklet);
551 }
552 if (status & ATH9K_INT_RXEOL) {
553 /*
554 * NB: the hardware should re-read the link when
555 * RXE bit is written, but it doesn't work
556 * at least on older hardware revs.
557 */
558 sched = true;
559 }
560
561 if (status & ATH9K_INT_TXURN)
562 /* bump tx trigger level */
563 ath9k_hw_updatetxtriglevel(ah, true);
564 /* XXX: optimize this */
565 if (status & ATH9K_INT_RX)
566 sched = true;
567 if (status & ATH9K_INT_TX)
568 sched = true;
569 if (status & ATH9K_INT_BMISS)
570 sched = true;
571 /* carrier sense timeout */
572 if (status & ATH9K_INT_CST)
573 sched = true;
574 if (status & ATH9K_INT_MIB) {
575 /*
576 * Disable interrupts until we service the MIB
577 * interrupt; otherwise it will continue to
578 * fire.
579 */
580 ath9k_hw_set_interrupts(ah, 0);
581 /*
582 * Let the hal handle the event. We assume
583 * it will clear whatever condition caused
584 * the interrupt.
585 */
586 ath9k_hw_procmibevent(ah, &sc->sc_halstats);
587 ath9k_hw_set_interrupts(ah, sc->sc_imask);
588 }
589 if (status & ATH9K_INT_TIM_TIMER) {
590 if (!(ah->ah_caps.hw_caps &
591 ATH9K_HW_CAP_AUTOSLEEP)) {
592 /* Clear RxAbort bit so that we can
593 * receive frames */
594 ath9k_hw_setrxabort(ah, 0);
595 sched = true;
596 }
597 }
598 }
599 } while (0);
600
Sujith817e11d2008-12-07 21:42:44 +0530601 ath_debug_stat_interrupt(sc, status);
602
Sujithff37e332008-11-24 12:07:55 +0530603 if (sched) {
604 /* turn off every interrupt except SWBA */
605 ath9k_hw_set_interrupts(ah, (sc->sc_imask & ATH9K_INT_SWBA));
606 tasklet_schedule(&sc->intr_tq);
607 }
608
609 return IRQ_HANDLED;
610}
611
Luis R. Rodriguezf078f202008-08-04 00:16:41 -0700612static int ath_get_channel(struct ath_softc *sc,
613 struct ieee80211_channel *chan)
614{
615 int i;
616
617 for (i = 0; i < sc->sc_ah->ah_nchan; i++) {
618 if (sc->sc_ah->ah_channels[i].channel == chan->center_freq)
619 return i;
620 }
621
622 return -1;
623}
624
625static u32 ath_get_extchanmode(struct ath_softc *sc,
Sujith99405f92008-11-24 12:08:35 +0530626 struct ieee80211_channel *chan,
Sujith094d05d2008-12-12 11:57:43 +0530627 enum nl80211_channel_type channel_type)
Luis R. Rodriguezf078f202008-08-04 00:16:41 -0700628{
629 u32 chanmode = 0;
Luis R. Rodriguezf078f202008-08-04 00:16:41 -0700630
631 switch (chan->band) {
632 case IEEE80211_BAND_2GHZ:
Sujith094d05d2008-12-12 11:57:43 +0530633 switch(channel_type) {
634 case NL80211_CHAN_NO_HT:
635 case NL80211_CHAN_HT20:
Luis R. Rodriguezf078f202008-08-04 00:16:41 -0700636 chanmode = CHANNEL_G_HT20;
Sujith094d05d2008-12-12 11:57:43 +0530637 break;
638 case NL80211_CHAN_HT40PLUS:
Luis R. Rodriguezf078f202008-08-04 00:16:41 -0700639 chanmode = CHANNEL_G_HT40PLUS;
Sujith094d05d2008-12-12 11:57:43 +0530640 break;
641 case NL80211_CHAN_HT40MINUS:
Luis R. Rodriguezf078f202008-08-04 00:16:41 -0700642 chanmode = CHANNEL_G_HT40MINUS;
Sujith094d05d2008-12-12 11:57:43 +0530643 break;
644 }
Luis R. Rodriguezf078f202008-08-04 00:16:41 -0700645 break;
646 case IEEE80211_BAND_5GHZ:
Sujith094d05d2008-12-12 11:57:43 +0530647 switch(channel_type) {
648 case NL80211_CHAN_NO_HT:
649 case NL80211_CHAN_HT20:
Luis R. Rodriguezf078f202008-08-04 00:16:41 -0700650 chanmode = CHANNEL_A_HT20;
Sujith094d05d2008-12-12 11:57:43 +0530651 break;
652 case NL80211_CHAN_HT40PLUS:
Luis R. Rodriguezf078f202008-08-04 00:16:41 -0700653 chanmode = CHANNEL_A_HT40PLUS;
Sujith094d05d2008-12-12 11:57:43 +0530654 break;
655 case NL80211_CHAN_HT40MINUS:
Luis R. Rodriguezf078f202008-08-04 00:16:41 -0700656 chanmode = CHANNEL_A_HT40MINUS;
Sujith094d05d2008-12-12 11:57:43 +0530657 break;
658 }
Luis R. Rodriguezf078f202008-08-04 00:16:41 -0700659 break;
660 default:
661 break;
662 }
663
664 return chanmode;
665}
666
Sujithff37e332008-11-24 12:07:55 +0530667static int ath_keyset(struct ath_softc *sc, u16 keyix,
668 struct ath9k_keyval *hk, const u8 mac[ETH_ALEN])
669{
670 bool status;
671
672 status = ath9k_hw_set_keycache_entry(sc->sc_ah,
673 keyix, hk, mac, false);
674
675 return status != false;
676}
Luis R. Rodriguezf078f202008-08-04 00:16:41 -0700677
Jouni Malinen6ace2892008-12-17 13:32:17 +0200678static int ath_setkey_tkip(struct ath_softc *sc, u16 keyix, const u8 *key,
Luis R. Rodriguezf078f202008-08-04 00:16:41 -0700679 struct ath9k_keyval *hk,
680 const u8 *addr)
681{
Jouni Malinen6ace2892008-12-17 13:32:17 +0200682 const u8 *key_rxmic;
683 const u8 *key_txmic;
Luis R. Rodriguezf078f202008-08-04 00:16:41 -0700684
Jouni Malinen6ace2892008-12-17 13:32:17 +0200685 key_txmic = key + NL80211_TKIP_DATA_OFFSET_TX_MIC_KEY;
686 key_rxmic = key + NL80211_TKIP_DATA_OFFSET_RX_MIC_KEY;
Luis R. Rodriguezf078f202008-08-04 00:16:41 -0700687
688 if (addr == NULL) {
689 /* Group key installation */
Jouni Malinen6ace2892008-12-17 13:32:17 +0200690 memcpy(hk->kv_mic, key_rxmic, sizeof(hk->kv_mic));
691 return ath_keyset(sc, keyix, hk, addr);
Luis R. Rodriguezf078f202008-08-04 00:16:41 -0700692 }
693 if (!sc->sc_splitmic) {
694 /*
695 * data key goes at first index,
696 * the hal handles the MIC keys at index+64.
697 */
698 memcpy(hk->kv_mic, key_rxmic, sizeof(hk->kv_mic));
699 memcpy(hk->kv_txmic, key_txmic, sizeof(hk->kv_txmic));
Jouni Malinen6ace2892008-12-17 13:32:17 +0200700 return ath_keyset(sc, keyix, hk, addr);
Luis R. Rodriguezf078f202008-08-04 00:16:41 -0700701 }
702 /*
703 * TX key goes at first index, RX key at +32.
704 * The hal handles the MIC keys at index+64.
705 */
706 memcpy(hk->kv_mic, key_txmic, sizeof(hk->kv_mic));
Jouni Malinen6ace2892008-12-17 13:32:17 +0200707 if (!ath_keyset(sc, keyix, hk, NULL)) {
Luis R. Rodriguezf078f202008-08-04 00:16:41 -0700708 /* Txmic entry failed. No need to proceed further */
709 DPRINTF(sc, ATH_DBG_KEYCACHE,
Sujith04bd4632008-11-28 22:18:05 +0530710 "Setting TX MIC Key Failed\n");
Luis R. Rodriguezf078f202008-08-04 00:16:41 -0700711 return 0;
712 }
713
714 memcpy(hk->kv_mic, key_rxmic, sizeof(hk->kv_mic));
715 /* XXX delete tx key on failure? */
Jouni Malinen6ace2892008-12-17 13:32:17 +0200716 return ath_keyset(sc, keyix + 32, hk, addr);
717}
718
719static int ath_reserve_key_cache_slot_tkip(struct ath_softc *sc)
720{
721 int i;
722
723 for (i = IEEE80211_WEP_NKID; i < sc->sc_keymax / 2; i++) {
724 if (test_bit(i, sc->sc_keymap) ||
725 test_bit(i + 64, sc->sc_keymap))
726 continue; /* At least one part of TKIP key allocated */
727 if (sc->sc_splitmic &&
728 (test_bit(i + 32, sc->sc_keymap) ||
729 test_bit(i + 64 + 32, sc->sc_keymap)))
730 continue; /* At least one part of TKIP key allocated */
731
732 /* Found a free slot for a TKIP key */
733 return i;
734 }
735 return -1;
736}
737
738static int ath_reserve_key_cache_slot(struct ath_softc *sc)
739{
740 int i;
741
742 /* First, try to find slots that would not be available for TKIP. */
743 if (sc->sc_splitmic) {
744 for (i = IEEE80211_WEP_NKID; i < sc->sc_keymax / 4; i++) {
745 if (!test_bit(i, sc->sc_keymap) &&
746 (test_bit(i + 32, sc->sc_keymap) ||
747 test_bit(i + 64, sc->sc_keymap) ||
748 test_bit(i + 64 + 32, sc->sc_keymap)))
749 return i;
750 if (!test_bit(i + 32, sc->sc_keymap) &&
751 (test_bit(i, sc->sc_keymap) ||
752 test_bit(i + 64, sc->sc_keymap) ||
753 test_bit(i + 64 + 32, sc->sc_keymap)))
754 return i + 32;
755 if (!test_bit(i + 64, sc->sc_keymap) &&
756 (test_bit(i , sc->sc_keymap) ||
757 test_bit(i + 32, sc->sc_keymap) ||
758 test_bit(i + 64 + 32, sc->sc_keymap)))
759 return i;
760 if (!test_bit(i + 64 + 32, sc->sc_keymap) &&
761 (test_bit(i, sc->sc_keymap) ||
762 test_bit(i + 32, sc->sc_keymap) ||
763 test_bit(i + 64, sc->sc_keymap)))
764 return i;
765 }
766 } else {
767 for (i = IEEE80211_WEP_NKID; i < sc->sc_keymax / 2; i++) {
768 if (!test_bit(i, sc->sc_keymap) &&
769 test_bit(i + 64, sc->sc_keymap))
770 return i;
771 if (test_bit(i, sc->sc_keymap) &&
772 !test_bit(i + 64, sc->sc_keymap))
773 return i + 64;
774 }
775 }
776
777 /* No partially used TKIP slots, pick any available slot */
778 for (i = IEEE80211_WEP_NKID; i < sc->sc_keymax; i++) {
779 if (!test_bit(i, sc->sc_keymap))
780 return i; /* Found a free slot for a key */
781 }
782
783 /* No free slot found */
784 return -1;
Luis R. Rodriguezf078f202008-08-04 00:16:41 -0700785}
786
787static int ath_key_config(struct ath_softc *sc,
788 const u8 *addr,
789 struct ieee80211_key_conf *key)
790{
Luis R. Rodriguezf078f202008-08-04 00:16:41 -0700791 struct ath9k_keyval hk;
792 const u8 *mac = NULL;
793 int ret = 0;
Jouni Malinen6ace2892008-12-17 13:32:17 +0200794 int idx;
Luis R. Rodriguezf078f202008-08-04 00:16:41 -0700795
796 memset(&hk, 0, sizeof(hk));
797
798 switch (key->alg) {
799 case ALG_WEP:
800 hk.kv_type = ATH9K_CIPHER_WEP;
801 break;
802 case ALG_TKIP:
803 hk.kv_type = ATH9K_CIPHER_TKIP;
804 break;
805 case ALG_CCMP:
806 hk.kv_type = ATH9K_CIPHER_AES_CCM;
807 break;
808 default:
809 return -EINVAL;
810 }
811
Jouni Malinen6ace2892008-12-17 13:32:17 +0200812 hk.kv_len = key->keylen;
Luis R. Rodriguezf078f202008-08-04 00:16:41 -0700813 memcpy(hk.kv_val, key->key, key->keylen);
814
Jouni Malinen6ace2892008-12-17 13:32:17 +0200815 if (!(key->flags & IEEE80211_KEY_FLAG_PAIRWISE)) {
816 /* For now, use the default keys for broadcast keys. This may
817 * need to change with virtual interfaces. */
818 idx = key->keyidx;
819 } else if (key->keyidx) {
820 struct ieee80211_vif *vif;
Luis R. Rodriguezf078f202008-08-04 00:16:41 -0700821
Jouni Malinen6ace2892008-12-17 13:32:17 +0200822 mac = addr;
823 vif = sc->sc_vaps[0];
824 if (vif->type != NL80211_IFTYPE_AP) {
825 /* Only keyidx 0 should be used with unicast key, but
826 * allow this for client mode for now. */
827 idx = key->keyidx;
828 } else
829 return -EIO;
Luis R. Rodriguezf078f202008-08-04 00:16:41 -0700830 } else {
831 mac = addr;
Jouni Malinen6ace2892008-12-17 13:32:17 +0200832 if (key->alg == ALG_TKIP)
833 idx = ath_reserve_key_cache_slot_tkip(sc);
834 else
835 idx = ath_reserve_key_cache_slot(sc);
836 if (idx < 0)
837 return -EIO; /* no free key cache entries */
Luis R. Rodriguezf078f202008-08-04 00:16:41 -0700838 }
839
840 if (key->alg == ALG_TKIP)
Jouni Malinen6ace2892008-12-17 13:32:17 +0200841 ret = ath_setkey_tkip(sc, idx, key->key, &hk, mac);
Luis R. Rodriguezf078f202008-08-04 00:16:41 -0700842 else
Jouni Malinen6ace2892008-12-17 13:32:17 +0200843 ret = ath_keyset(sc, idx, &hk, mac);
Luis R. Rodriguezf078f202008-08-04 00:16:41 -0700844
845 if (!ret)
846 return -EIO;
847
Jouni Malinen6ace2892008-12-17 13:32:17 +0200848 set_bit(idx, sc->sc_keymap);
849 if (key->alg == ALG_TKIP) {
850 set_bit(idx + 64, sc->sc_keymap);
851 if (sc->sc_splitmic) {
852 set_bit(idx + 32, sc->sc_keymap);
853 set_bit(idx + 64 + 32, sc->sc_keymap);
854 }
855 }
856
857 return idx;
Luis R. Rodriguezf078f202008-08-04 00:16:41 -0700858}
859
860static void ath_key_delete(struct ath_softc *sc, struct ieee80211_key_conf *key)
861{
Jouni Malinen6ace2892008-12-17 13:32:17 +0200862 ath9k_hw_keyreset(sc->sc_ah, key->hw_key_idx);
863 if (key->hw_key_idx < IEEE80211_WEP_NKID)
864 return;
Luis R. Rodriguezf078f202008-08-04 00:16:41 -0700865
Jouni Malinen6ace2892008-12-17 13:32:17 +0200866 clear_bit(key->hw_key_idx, sc->sc_keymap);
867 if (key->alg != ALG_TKIP)
868 return;
869
870 clear_bit(key->hw_key_idx + 64, sc->sc_keymap);
871 if (sc->sc_splitmic) {
872 clear_bit(key->hw_key_idx + 32, sc->sc_keymap);
873 clear_bit(key->hw_key_idx + 64 + 32, sc->sc_keymap);
874 }
Luis R. Rodriguezf078f202008-08-04 00:16:41 -0700875}
876
Johannes Bergd9fe60d2008-10-09 12:13:49 +0200877static void setup_ht_cap(struct ieee80211_sta_ht_cap *ht_info)
Luis R. Rodriguezf078f202008-08-04 00:16:41 -0700878{
Sujith60653672008-08-14 13:28:02 +0530879#define ATH9K_HT_CAP_MAXRXAMPDU_65536 0x3 /* 2 ^ 16 */
880#define ATH9K_HT_CAP_MPDUDENSITY_8 0x6 /* 8 usec */
Luis R. Rodriguezf078f202008-08-04 00:16:41 -0700881
Johannes Bergd9fe60d2008-10-09 12:13:49 +0200882 ht_info->ht_supported = true;
883 ht_info->cap = IEEE80211_HT_CAP_SUP_WIDTH_20_40 |
884 IEEE80211_HT_CAP_SM_PS |
885 IEEE80211_HT_CAP_SGI_40 |
886 IEEE80211_HT_CAP_DSSSCCK40;
Luis R. Rodriguezf078f202008-08-04 00:16:41 -0700887
Sujith60653672008-08-14 13:28:02 +0530888 ht_info->ampdu_factor = ATH9K_HT_CAP_MAXRXAMPDU_65536;
889 ht_info->ampdu_density = ATH9K_HT_CAP_MPDUDENSITY_8;
Johannes Bergd9fe60d2008-10-09 12:13:49 +0200890 /* set up supported mcs set */
891 memset(&ht_info->mcs, 0, sizeof(ht_info->mcs));
892 ht_info->mcs.rx_mask[0] = 0xff;
893 ht_info->mcs.rx_mask[1] = 0xff;
894 ht_info->mcs.tx_params = IEEE80211_HT_MCS_TX_DEFINED;
Luis R. Rodriguezf078f202008-08-04 00:16:41 -0700895}
896
Vasanthakumar Thiagarajan8feceb62008-09-10 18:49:27 +0530897static void ath9k_bss_assoc_info(struct ath_softc *sc,
Sujith5640b082008-10-29 10:16:06 +0530898 struct ieee80211_vif *vif,
Vasanthakumar Thiagarajan8feceb62008-09-10 18:49:27 +0530899 struct ieee80211_bss_conf *bss_conf)
900{
Sujith5640b082008-10-29 10:16:06 +0530901 struct ath_vap *avp = (void *)vif->drv_priv;
Vasanthakumar Thiagarajan8feceb62008-09-10 18:49:27 +0530902
903 if (bss_conf->assoc) {
Sujith094d05d2008-12-12 11:57:43 +0530904 DPRINTF(sc, ATH_DBG_CONFIG, "Bss Info ASSOC %d, bssid: %pM\n",
905 bss_conf->aid, sc->sc_curbssid);
Vasanthakumar Thiagarajan8feceb62008-09-10 18:49:27 +0530906
Vasanthakumar Thiagarajan8feceb62008-09-10 18:49:27 +0530907 /* New association, store aid */
Colin McCabed97809d2008-12-01 13:38:55 -0800908 if (avp->av_opmode == NL80211_IFTYPE_STATION) {
Vasanthakumar Thiagarajan8feceb62008-09-10 18:49:27 +0530909 sc->sc_curaid = bss_conf->aid;
910 ath9k_hw_write_associd(sc->sc_ah, sc->sc_curbssid,
911 sc->sc_curaid);
912 }
913
914 /* Configure the beacon */
915 ath_beacon_config(sc, 0);
916 sc->sc_flags |= SC_OP_BEACONS;
917
918 /* Reset rssi stats */
919 sc->sc_halstats.ns_avgbrssi = ATH_RSSI_DUMMY_MARKER;
920 sc->sc_halstats.ns_avgrssi = ATH_RSSI_DUMMY_MARKER;
921 sc->sc_halstats.ns_avgtxrssi = ATH_RSSI_DUMMY_MARKER;
922 sc->sc_halstats.ns_avgtxrate = ATH_RATE_DUMMY_MARKER;
923
Luis R. Rodriguez6f255422008-10-03 15:45:27 -0700924 /* Start ANI */
925 mod_timer(&sc->sc_ani.timer,
926 jiffies + msecs_to_jiffies(ATH_ANI_POLLINTERVAL));
927
Vasanthakumar Thiagarajan8feceb62008-09-10 18:49:27 +0530928 } else {
Sujith04bd4632008-11-28 22:18:05 +0530929 DPRINTF(sc, ATH_DBG_CONFIG, "Bss Info DISSOC\n");
Vasanthakumar Thiagarajan8feceb62008-09-10 18:49:27 +0530930 sc->sc_curaid = 0;
931 }
932}
933
Vasanthakumar Thiagarajan8feceb62008-09-10 18:49:27 +0530934/********************************/
935/* LED functions */
936/********************************/
937
938static void ath_led_brightness(struct led_classdev *led_cdev,
939 enum led_brightness brightness)
940{
941 struct ath_led *led = container_of(led_cdev, struct ath_led, led_cdev);
942 struct ath_softc *sc = led->sc;
943
944 switch (brightness) {
945 case LED_OFF:
946 if (led->led_type == ATH_LED_ASSOC ||
947 led->led_type == ATH_LED_RADIO)
948 sc->sc_flags &= ~SC_OP_LED_ASSOCIATED;
949 ath9k_hw_set_gpio(sc->sc_ah, ATH_LED_PIN,
950 (led->led_type == ATH_LED_RADIO) ? 1 :
951 !!(sc->sc_flags & SC_OP_LED_ASSOCIATED));
952 break;
953 case LED_FULL:
954 if (led->led_type == ATH_LED_ASSOC)
955 sc->sc_flags |= SC_OP_LED_ASSOCIATED;
956 ath9k_hw_set_gpio(sc->sc_ah, ATH_LED_PIN, 0);
957 break;
958 default:
959 break;
960 }
961}
962
963static int ath_register_led(struct ath_softc *sc, struct ath_led *led,
964 char *trigger)
965{
966 int ret;
967
968 led->sc = sc;
969 led->led_cdev.name = led->name;
970 led->led_cdev.default_trigger = trigger;
971 led->led_cdev.brightness_set = ath_led_brightness;
972
973 ret = led_classdev_register(wiphy_dev(sc->hw->wiphy), &led->led_cdev);
974 if (ret)
975 DPRINTF(sc, ATH_DBG_FATAL,
976 "Failed to register led:%s", led->name);
977 else
978 led->registered = 1;
979 return ret;
980}
981
982static void ath_unregister_led(struct ath_led *led)
983{
984 if (led->registered) {
985 led_classdev_unregister(&led->led_cdev);
986 led->registered = 0;
987 }
988}
989
990static void ath_deinit_leds(struct ath_softc *sc)
991{
992 ath_unregister_led(&sc->assoc_led);
993 sc->sc_flags &= ~SC_OP_LED_ASSOCIATED;
994 ath_unregister_led(&sc->tx_led);
995 ath_unregister_led(&sc->rx_led);
996 ath_unregister_led(&sc->radio_led);
997 ath9k_hw_set_gpio(sc->sc_ah, ATH_LED_PIN, 1);
998}
999
1000static void ath_init_leds(struct ath_softc *sc)
1001{
1002 char *trigger;
1003 int ret;
1004
1005 /* Configure gpio 1 for output */
1006 ath9k_hw_cfg_output(sc->sc_ah, ATH_LED_PIN,
1007 AR_GPIO_OUTPUT_MUX_AS_OUTPUT);
1008 /* LED off, active low */
1009 ath9k_hw_set_gpio(sc->sc_ah, ATH_LED_PIN, 1);
1010
1011 trigger = ieee80211_get_radio_led_name(sc->hw);
1012 snprintf(sc->radio_led.name, sizeof(sc->radio_led.name),
1013 "ath9k-%s:radio", wiphy_name(sc->hw->wiphy));
1014 ret = ath_register_led(sc, &sc->radio_led, trigger);
1015 sc->radio_led.led_type = ATH_LED_RADIO;
1016 if (ret)
1017 goto fail;
1018
1019 trigger = ieee80211_get_assoc_led_name(sc->hw);
1020 snprintf(sc->assoc_led.name, sizeof(sc->assoc_led.name),
1021 "ath9k-%s:assoc", wiphy_name(sc->hw->wiphy));
1022 ret = ath_register_led(sc, &sc->assoc_led, trigger);
1023 sc->assoc_led.led_type = ATH_LED_ASSOC;
1024 if (ret)
1025 goto fail;
1026
1027 trigger = ieee80211_get_tx_led_name(sc->hw);
1028 snprintf(sc->tx_led.name, sizeof(sc->tx_led.name),
1029 "ath9k-%s:tx", wiphy_name(sc->hw->wiphy));
1030 ret = ath_register_led(sc, &sc->tx_led, trigger);
1031 sc->tx_led.led_type = ATH_LED_TX;
1032 if (ret)
1033 goto fail;
1034
1035 trigger = ieee80211_get_rx_led_name(sc->hw);
1036 snprintf(sc->rx_led.name, sizeof(sc->rx_led.name),
1037 "ath9k-%s:rx", wiphy_name(sc->hw->wiphy));
1038 ret = ath_register_led(sc, &sc->rx_led, trigger);
1039 sc->rx_led.led_type = ATH_LED_RX;
1040 if (ret)
1041 goto fail;
1042
1043 return;
1044
1045fail:
1046 ath_deinit_leds(sc);
1047}
1048
Senthil Balasubramaniane97275c2008-11-13 18:00:02 +05301049#if defined(CONFIG_RFKILL) || defined(CONFIG_RFKILL_MODULE)
Sujith9c84b792008-10-29 10:17:13 +05301050
Vasanthakumar Thiagarajan500c0642008-09-10 18:50:17 +05301051/*******************/
1052/* Rfkill */
1053/*******************/
1054
1055static void ath_radio_enable(struct ath_softc *sc)
1056{
1057 struct ath_hal *ah = sc->sc_ah;
1058 int status;
1059
1060 spin_lock_bh(&sc->sc_resetlock);
1061 if (!ath9k_hw_reset(ah, ah->ah_curchan,
Sujith99405f92008-11-24 12:08:35 +05301062 sc->tx_chan_width,
Vasanthakumar Thiagarajan500c0642008-09-10 18:50:17 +05301063 sc->sc_tx_chainmask,
1064 sc->sc_rx_chainmask,
1065 sc->sc_ht_extprotspacing,
1066 false, &status)) {
1067 DPRINTF(sc, ATH_DBG_FATAL,
Sujith04bd4632008-11-28 22:18:05 +05301068 "Unable to reset channel %u (%uMhz) "
1069 "flags 0x%x hal status %u\n",
Vasanthakumar Thiagarajan500c0642008-09-10 18:50:17 +05301070 ath9k_hw_mhz2ieee(ah,
1071 ah->ah_curchan->channel,
1072 ah->ah_curchan->channelFlags),
1073 ah->ah_curchan->channel,
1074 ah->ah_curchan->channelFlags, status);
1075 }
1076 spin_unlock_bh(&sc->sc_resetlock);
1077
1078 ath_update_txpow(sc);
1079 if (ath_startrecv(sc) != 0) {
1080 DPRINTF(sc, ATH_DBG_FATAL,
Sujith04bd4632008-11-28 22:18:05 +05301081 "Unable to restart recv logic\n");
Vasanthakumar Thiagarajan500c0642008-09-10 18:50:17 +05301082 return;
1083 }
1084
1085 if (sc->sc_flags & SC_OP_BEACONS)
1086 ath_beacon_config(sc, ATH_IF_ID_ANY); /* restart beacons */
1087
1088 /* Re-Enable interrupts */
1089 ath9k_hw_set_interrupts(ah, sc->sc_imask);
1090
1091 /* Enable LED */
1092 ath9k_hw_cfg_output(ah, ATH_LED_PIN,
1093 AR_GPIO_OUTPUT_MUX_AS_OUTPUT);
1094 ath9k_hw_set_gpio(ah, ATH_LED_PIN, 0);
1095
1096 ieee80211_wake_queues(sc->hw);
1097}
1098
1099static void ath_radio_disable(struct ath_softc *sc)
1100{
1101 struct ath_hal *ah = sc->sc_ah;
1102 int status;
1103
1104
1105 ieee80211_stop_queues(sc->hw);
1106
1107 /* Disable LED */
1108 ath9k_hw_set_gpio(ah, ATH_LED_PIN, 1);
1109 ath9k_hw_cfg_gpio_input(ah, ATH_LED_PIN);
1110
1111 /* Disable interrupts */
1112 ath9k_hw_set_interrupts(ah, 0);
1113
1114 ath_draintxq(sc, false); /* clear pending tx frames */
1115 ath_stoprecv(sc); /* turn off frame recv */
1116 ath_flushrecv(sc); /* flush recv queue */
1117
1118 spin_lock_bh(&sc->sc_resetlock);
1119 if (!ath9k_hw_reset(ah, ah->ah_curchan,
Sujith99405f92008-11-24 12:08:35 +05301120 sc->tx_chan_width,
Vasanthakumar Thiagarajan500c0642008-09-10 18:50:17 +05301121 sc->sc_tx_chainmask,
1122 sc->sc_rx_chainmask,
1123 sc->sc_ht_extprotspacing,
1124 false, &status)) {
1125 DPRINTF(sc, ATH_DBG_FATAL,
Sujith04bd4632008-11-28 22:18:05 +05301126 "Unable to reset channel %u (%uMhz) "
1127 "flags 0x%x hal status %u\n",
Vasanthakumar Thiagarajan500c0642008-09-10 18:50:17 +05301128 ath9k_hw_mhz2ieee(ah,
1129 ah->ah_curchan->channel,
1130 ah->ah_curchan->channelFlags),
1131 ah->ah_curchan->channel,
1132 ah->ah_curchan->channelFlags, status);
1133 }
1134 spin_unlock_bh(&sc->sc_resetlock);
1135
1136 ath9k_hw_phy_disable(ah);
1137 ath9k_hw_setpower(ah, ATH9K_PM_FULL_SLEEP);
1138}
1139
1140static bool ath_is_rfkill_set(struct ath_softc *sc)
1141{
1142 struct ath_hal *ah = sc->sc_ah;
1143
1144 return ath9k_hw_gpio_get(ah, ah->ah_rfkill_gpio) ==
1145 ah->ah_rfkill_polarity;
1146}
1147
1148/* h/w rfkill poll function */
1149static void ath_rfkill_poll(struct work_struct *work)
1150{
1151 struct ath_softc *sc = container_of(work, struct ath_softc,
1152 rf_kill.rfkill_poll.work);
1153 bool radio_on;
1154
1155 if (sc->sc_flags & SC_OP_INVALID)
1156 return;
1157
1158 radio_on = !ath_is_rfkill_set(sc);
1159
1160 /*
1161 * enable/disable radio only when there is a
1162 * state change in RF switch
1163 */
1164 if (radio_on == !!(sc->sc_flags & SC_OP_RFKILL_HW_BLOCKED)) {
1165 enum rfkill_state state;
1166
1167 if (sc->sc_flags & SC_OP_RFKILL_SW_BLOCKED) {
1168 state = radio_on ? RFKILL_STATE_SOFT_BLOCKED
1169 : RFKILL_STATE_HARD_BLOCKED;
1170 } else if (radio_on) {
1171 ath_radio_enable(sc);
1172 state = RFKILL_STATE_UNBLOCKED;
1173 } else {
1174 ath_radio_disable(sc);
1175 state = RFKILL_STATE_HARD_BLOCKED;
1176 }
1177
1178 if (state == RFKILL_STATE_HARD_BLOCKED)
1179 sc->sc_flags |= SC_OP_RFKILL_HW_BLOCKED;
1180 else
1181 sc->sc_flags &= ~SC_OP_RFKILL_HW_BLOCKED;
1182
1183 rfkill_force_state(sc->rf_kill.rfkill, state);
1184 }
1185
1186 queue_delayed_work(sc->hw->workqueue, &sc->rf_kill.rfkill_poll,
1187 msecs_to_jiffies(ATH_RFKILL_POLL_INTERVAL));
1188}
1189
1190/* s/w rfkill handler */
1191static int ath_sw_toggle_radio(void *data, enum rfkill_state state)
1192{
1193 struct ath_softc *sc = data;
1194
1195 switch (state) {
1196 case RFKILL_STATE_SOFT_BLOCKED:
1197 if (!(sc->sc_flags & (SC_OP_RFKILL_HW_BLOCKED |
1198 SC_OP_RFKILL_SW_BLOCKED)))
1199 ath_radio_disable(sc);
1200 sc->sc_flags |= SC_OP_RFKILL_SW_BLOCKED;
1201 return 0;
1202 case RFKILL_STATE_UNBLOCKED:
1203 if ((sc->sc_flags & SC_OP_RFKILL_SW_BLOCKED)) {
1204 sc->sc_flags &= ~SC_OP_RFKILL_SW_BLOCKED;
1205 if (sc->sc_flags & SC_OP_RFKILL_HW_BLOCKED) {
1206 DPRINTF(sc, ATH_DBG_FATAL, "Can't turn on the"
Sujith04bd4632008-11-28 22:18:05 +05301207 "radio as it is disabled by h/w\n");
Vasanthakumar Thiagarajan500c0642008-09-10 18:50:17 +05301208 return -EPERM;
1209 }
1210 ath_radio_enable(sc);
1211 }
1212 return 0;
1213 default:
1214 return -EINVAL;
1215 }
1216}
1217
1218/* Init s/w rfkill */
1219static int ath_init_sw_rfkill(struct ath_softc *sc)
1220{
1221 sc->rf_kill.rfkill = rfkill_allocate(wiphy_dev(sc->hw->wiphy),
1222 RFKILL_TYPE_WLAN);
1223 if (!sc->rf_kill.rfkill) {
1224 DPRINTF(sc, ATH_DBG_FATAL, "Failed to allocate rfkill\n");
1225 return -ENOMEM;
1226 }
1227
1228 snprintf(sc->rf_kill.rfkill_name, sizeof(sc->rf_kill.rfkill_name),
1229 "ath9k-%s:rfkill", wiphy_name(sc->hw->wiphy));
1230 sc->rf_kill.rfkill->name = sc->rf_kill.rfkill_name;
1231 sc->rf_kill.rfkill->data = sc;
1232 sc->rf_kill.rfkill->toggle_radio = ath_sw_toggle_radio;
1233 sc->rf_kill.rfkill->state = RFKILL_STATE_UNBLOCKED;
1234 sc->rf_kill.rfkill->user_claim_unsupported = 1;
1235
1236 return 0;
1237}
1238
1239/* Deinitialize rfkill */
1240static void ath_deinit_rfkill(struct ath_softc *sc)
1241{
1242 if (sc->sc_ah->ah_caps.hw_caps & ATH9K_HW_CAP_RFSILENT)
1243 cancel_delayed_work_sync(&sc->rf_kill.rfkill_poll);
1244
1245 if (sc->sc_flags & SC_OP_RFKILL_REGISTERED) {
1246 rfkill_unregister(sc->rf_kill.rfkill);
1247 sc->sc_flags &= ~SC_OP_RFKILL_REGISTERED;
1248 sc->rf_kill.rfkill = NULL;
1249 }
1250}
Sujith9c84b792008-10-29 10:17:13 +05301251
1252static int ath_start_rfkill_poll(struct ath_softc *sc)
1253{
1254 if (sc->sc_ah->ah_caps.hw_caps & ATH9K_HW_CAP_RFSILENT)
1255 queue_delayed_work(sc->hw->workqueue,
1256 &sc->rf_kill.rfkill_poll, 0);
1257
1258 if (!(sc->sc_flags & SC_OP_RFKILL_REGISTERED)) {
1259 if (rfkill_register(sc->rf_kill.rfkill)) {
1260 DPRINTF(sc, ATH_DBG_FATAL,
1261 "Unable to register rfkill\n");
1262 rfkill_free(sc->rf_kill.rfkill);
1263
1264 /* Deinitialize the device */
Senthil Balasubramanian306efdd2008-11-13 18:00:37 +05301265 ath_detach(sc);
Sujith9c84b792008-10-29 10:17:13 +05301266 if (sc->pdev->irq)
1267 free_irq(sc->pdev->irq, sc);
Sujith9c84b792008-10-29 10:17:13 +05301268 pci_iounmap(sc->pdev, sc->mem);
1269 pci_release_region(sc->pdev, 0);
1270 pci_disable_device(sc->pdev);
Sujith9757d552008-11-04 18:25:27 +05301271 ieee80211_free_hw(sc->hw);
Sujith9c84b792008-10-29 10:17:13 +05301272 return -EIO;
1273 } else {
1274 sc->sc_flags |= SC_OP_RFKILL_REGISTERED;
1275 }
1276 }
1277
1278 return 0;
1279}
Vasanthakumar Thiagarajan500c0642008-09-10 18:50:17 +05301280#endif /* CONFIG_RFKILL */
1281
Sujith9c84b792008-10-29 10:17:13 +05301282static void ath_detach(struct ath_softc *sc)
Vasanthakumar Thiagarajan8feceb62008-09-10 18:49:27 +05301283{
1284 struct ieee80211_hw *hw = sc->hw;
Sujith9c84b792008-10-29 10:17:13 +05301285 int i = 0;
Vasanthakumar Thiagarajan8feceb62008-09-10 18:49:27 +05301286
Sujith04bd4632008-11-28 22:18:05 +05301287 DPRINTF(sc, ATH_DBG_CONFIG, "Detach ATH hw\n");
Vasanthakumar Thiagarajan8feceb62008-09-10 18:49:27 +05301288
Senthil Balasubramaniane97275c2008-11-13 18:00:02 +05301289#if defined(CONFIG_RFKILL) || defined(CONFIG_RFKILL_MODULE)
Vasanthakumar Thiagarajan500c0642008-09-10 18:50:17 +05301290 ath_deinit_rfkill(sc);
1291#endif
Vasanthakumar Thiagarajan3fcdfb42008-11-18 01:19:56 +05301292 ath_deinit_leds(sc);
1293
1294 ieee80211_unregister_hw(hw);
Vasanthakumar Thiagarajan8feceb62008-09-10 18:49:27 +05301295 ath_rx_cleanup(sc);
1296 ath_tx_cleanup(sc);
1297
Sujith9c84b792008-10-29 10:17:13 +05301298 tasklet_kill(&sc->intr_tq);
1299 tasklet_kill(&sc->bcon_tasklet);
Vasanthakumar Thiagarajan8feceb62008-09-10 18:49:27 +05301300
Sujith9c84b792008-10-29 10:17:13 +05301301 if (!(sc->sc_flags & SC_OP_INVALID))
1302 ath9k_hw_setpower(sc->sc_ah, ATH9K_PM_AWAKE);
Vasanthakumar Thiagarajan8feceb62008-09-10 18:49:27 +05301303
Sujith9c84b792008-10-29 10:17:13 +05301304 /* cleanup tx queues */
1305 for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++)
1306 if (ATH_TXQ_SETUP(sc, i))
Sujithb77f4832008-12-07 21:44:03 +05301307 ath_tx_cleanupq(sc, &sc->tx.txq[i]);
Sujith9c84b792008-10-29 10:17:13 +05301308
1309 ath9k_hw_detach(sc->sc_ah);
Sujith826d2682008-11-28 22:20:23 +05301310 ath9k_exit_debug(sc);
Vasanthakumar Thiagarajan8feceb62008-09-10 18:49:27 +05301311}
1312
Sujithff37e332008-11-24 12:07:55 +05301313static int ath_init(u16 devid, struct ath_softc *sc)
1314{
1315 struct ath_hal *ah = NULL;
1316 int status;
1317 int error = 0, i;
1318 int csz = 0;
1319
1320 /* XXX: hardware will not be ready until ath_open() being called */
1321 sc->sc_flags |= SC_OP_INVALID;
Sujith88b126a2008-11-28 22:19:02 +05301322
Sujith826d2682008-11-28 22:20:23 +05301323 if (ath9k_init_debug(sc) < 0)
1324 printk(KERN_ERR "Unable to create debugfs files\n");
Sujithff37e332008-11-24 12:07:55 +05301325
1326 spin_lock_init(&sc->sc_resetlock);
Sujithaa33de02008-12-18 11:40:16 +05301327 mutex_init(&sc->mutex);
Sujithff37e332008-11-24 12:07:55 +05301328 tasklet_init(&sc->intr_tq, ath9k_tasklet, (unsigned long)sc);
1329 tasklet_init(&sc->bcon_tasklet, ath9k_beacon_tasklet,
1330 (unsigned long)sc);
1331
1332 /*
1333 * Cache line size is used to size and align various
1334 * structures used to communicate with the hardware.
1335 */
1336 bus_read_cachesize(sc, &csz);
1337 /* XXX assert csz is non-zero */
1338 sc->sc_cachelsz = csz << 2; /* convert to bytes */
1339
1340 ah = ath9k_hw_attach(devid, sc, sc->mem, &status);
1341 if (ah == NULL) {
1342 DPRINTF(sc, ATH_DBG_FATAL,
Sujith04bd4632008-11-28 22:18:05 +05301343 "Unable to attach hardware; HAL status %u\n", status);
Sujithff37e332008-11-24 12:07:55 +05301344 error = -ENXIO;
1345 goto bad;
1346 }
1347 sc->sc_ah = ah;
1348
1349 /* Get the hardware key cache size. */
1350 sc->sc_keymax = ah->ah_caps.keycache_size;
1351 if (sc->sc_keymax > ATH_KEYMAX) {
1352 DPRINTF(sc, ATH_DBG_KEYCACHE,
Sujith04bd4632008-11-28 22:18:05 +05301353 "Warning, using only %u entries in %u key cache\n",
1354 ATH_KEYMAX, sc->sc_keymax);
Sujithff37e332008-11-24 12:07:55 +05301355 sc->sc_keymax = ATH_KEYMAX;
1356 }
1357
1358 /*
1359 * Reset the key cache since some parts do not
1360 * reset the contents on initial power up.
1361 */
1362 for (i = 0; i < sc->sc_keymax; i++)
1363 ath9k_hw_keyreset(ah, (u16) i);
1364 /*
1365 * Mark key cache slots associated with global keys
1366 * as in use. If we knew TKIP was not to be used we
1367 * could leave the +32, +64, and +32+64 slots free.
Sujithff37e332008-11-24 12:07:55 +05301368 */
1369 for (i = 0; i < IEEE80211_WEP_NKID; i++) {
1370 set_bit(i, sc->sc_keymap);
Sujithff37e332008-11-24 12:07:55 +05301371 set_bit(i + 64, sc->sc_keymap);
Jouni Malinen6ace2892008-12-17 13:32:17 +02001372 if (ath9k_hw_getcapability(ah, ATH9K_CAP_TKIP_SPLIT,
1373 0, NULL)) {
1374 set_bit(i + 32, sc->sc_keymap);
1375 set_bit(i + 32 + 64, sc->sc_keymap);
1376 }
Sujithff37e332008-11-24 12:07:55 +05301377 }
1378
1379 /* Collect the channel list using the default country code */
1380
1381 error = ath_setup_channels(sc);
1382 if (error)
1383 goto bad;
1384
1385 /* default to MONITOR mode */
Colin McCabed97809d2008-12-01 13:38:55 -08001386 sc->sc_ah->ah_opmode = NL80211_IFTYPE_MONITOR;
1387
Sujithff37e332008-11-24 12:07:55 +05301388
1389 /* Setup rate tables */
1390
1391 ath_rate_attach(sc);
1392 ath_setup_rates(sc, IEEE80211_BAND_2GHZ);
1393 ath_setup_rates(sc, IEEE80211_BAND_5GHZ);
1394
1395 /*
1396 * Allocate hardware transmit queues: one queue for
1397 * beacon frames and one data queue for each QoS
1398 * priority. Note that the hal handles reseting
1399 * these queues at the needed time.
1400 */
Sujithb77f4832008-12-07 21:44:03 +05301401 sc->beacon.beaconq = ath_beaconq_setup(ah);
1402 if (sc->beacon.beaconq == -1) {
Sujithff37e332008-11-24 12:07:55 +05301403 DPRINTF(sc, ATH_DBG_FATAL,
Sujith04bd4632008-11-28 22:18:05 +05301404 "Unable to setup a beacon xmit queue\n");
Sujithff37e332008-11-24 12:07:55 +05301405 error = -EIO;
1406 goto bad2;
1407 }
Sujithb77f4832008-12-07 21:44:03 +05301408 sc->beacon.cabq = ath_txq_setup(sc, ATH9K_TX_QUEUE_CAB, 0);
1409 if (sc->beacon.cabq == NULL) {
Sujithff37e332008-11-24 12:07:55 +05301410 DPRINTF(sc, ATH_DBG_FATAL,
Sujith04bd4632008-11-28 22:18:05 +05301411 "Unable to setup CAB xmit queue\n");
Sujithff37e332008-11-24 12:07:55 +05301412 error = -EIO;
1413 goto bad2;
1414 }
1415
1416 sc->sc_config.cabqReadytime = ATH_CABQ_READY_TIME;
1417 ath_cabq_update(sc);
1418
Sujithb77f4832008-12-07 21:44:03 +05301419 for (i = 0; i < ARRAY_SIZE(sc->tx.hwq_map); i++)
1420 sc->tx.hwq_map[i] = -1;
Sujithff37e332008-11-24 12:07:55 +05301421
1422 /* Setup data queues */
1423 /* NB: ensure BK queue is the lowest priority h/w queue */
1424 if (!ath_tx_setup(sc, ATH9K_WME_AC_BK)) {
1425 DPRINTF(sc, ATH_DBG_FATAL,
Sujith04bd4632008-11-28 22:18:05 +05301426 "Unable to setup xmit queue for BK traffic\n");
Sujithff37e332008-11-24 12:07:55 +05301427 error = -EIO;
1428 goto bad2;
1429 }
1430
1431 if (!ath_tx_setup(sc, ATH9K_WME_AC_BE)) {
1432 DPRINTF(sc, ATH_DBG_FATAL,
Sujith04bd4632008-11-28 22:18:05 +05301433 "Unable to setup xmit queue for BE traffic\n");
Sujithff37e332008-11-24 12:07:55 +05301434 error = -EIO;
1435 goto bad2;
1436 }
1437 if (!ath_tx_setup(sc, ATH9K_WME_AC_VI)) {
1438 DPRINTF(sc, ATH_DBG_FATAL,
Sujith04bd4632008-11-28 22:18:05 +05301439 "Unable to setup xmit queue for VI traffic\n");
Sujithff37e332008-11-24 12:07:55 +05301440 error = -EIO;
1441 goto bad2;
1442 }
1443 if (!ath_tx_setup(sc, ATH9K_WME_AC_VO)) {
1444 DPRINTF(sc, ATH_DBG_FATAL,
Sujith04bd4632008-11-28 22:18:05 +05301445 "Unable to setup xmit queue for VO traffic\n");
Sujithff37e332008-11-24 12:07:55 +05301446 error = -EIO;
1447 goto bad2;
1448 }
1449
1450 /* Initializes the noise floor to a reasonable default value.
1451 * Later on this will be updated during ANI processing. */
1452
1453 sc->sc_ani.sc_noise_floor = ATH_DEFAULT_NOISE_FLOOR;
1454 setup_timer(&sc->sc_ani.timer, ath_ani_calibrate, (unsigned long)sc);
1455
1456 if (ath9k_hw_getcapability(ah, ATH9K_CAP_CIPHER,
1457 ATH9K_CIPHER_TKIP, NULL)) {
1458 /*
1459 * Whether we should enable h/w TKIP MIC.
1460 * XXX: if we don't support WME TKIP MIC, then we wouldn't
1461 * report WMM capable, so it's always safe to turn on
1462 * TKIP MIC in this case.
1463 */
1464 ath9k_hw_setcapability(sc->sc_ah, ATH9K_CAP_TKIP_MIC,
1465 0, 1, NULL);
1466 }
1467
1468 /*
1469 * Check whether the separate key cache entries
1470 * are required to handle both tx+rx MIC keys.
1471 * With split mic keys the number of stations is limited
1472 * to 27 otherwise 59.
1473 */
1474 if (ath9k_hw_getcapability(ah, ATH9K_CAP_CIPHER,
1475 ATH9K_CIPHER_TKIP, NULL)
1476 && ath9k_hw_getcapability(ah, ATH9K_CAP_CIPHER,
1477 ATH9K_CIPHER_MIC, NULL)
1478 && ath9k_hw_getcapability(ah, ATH9K_CAP_TKIP_SPLIT,
1479 0, NULL))
1480 sc->sc_splitmic = 1;
1481
1482 /* turn on mcast key search if possible */
1483 if (!ath9k_hw_getcapability(ah, ATH9K_CAP_MCAST_KEYSRCH, 0, NULL))
1484 (void)ath9k_hw_setcapability(ah, ATH9K_CAP_MCAST_KEYSRCH, 1,
1485 1, NULL);
1486
1487 sc->sc_config.txpowlimit = ATH_TXPOWER_MAX;
1488 sc->sc_config.txpowlimit_override = 0;
1489
1490 /* 11n Capabilities */
1491 if (ah->ah_caps.hw_caps & ATH9K_HW_CAP_HT) {
1492 sc->sc_flags |= SC_OP_TXAGGR;
1493 sc->sc_flags |= SC_OP_RXAGGR;
1494 }
1495
1496 sc->sc_tx_chainmask = ah->ah_caps.tx_chainmask;
1497 sc->sc_rx_chainmask = ah->ah_caps.rx_chainmask;
1498
1499 ath9k_hw_setcapability(ah, ATH9K_CAP_DIVERSITY, 1, true, NULL);
Sujithb77f4832008-12-07 21:44:03 +05301500 sc->rx.defant = ath9k_hw_getdefantenna(ah);
Sujithff37e332008-11-24 12:07:55 +05301501
1502 ath9k_hw_getmac(ah, sc->sc_myaddr);
1503 if (ah->ah_caps.hw_caps & ATH9K_HW_CAP_BSSIDMASK) {
1504 ath9k_hw_getbssidmask(ah, sc->sc_bssidmask);
1505 ATH_SET_VAP_BSSID_MASK(sc->sc_bssidmask);
1506 ath9k_hw_setbssidmask(ah, sc->sc_bssidmask);
1507 }
1508
Sujithb77f4832008-12-07 21:44:03 +05301509 sc->beacon.slottime = ATH9K_SLOT_TIME_9; /* default to short slot time */
Sujithff37e332008-11-24 12:07:55 +05301510
1511 /* initialize beacon slots */
Sujithb77f4832008-12-07 21:44:03 +05301512 for (i = 0; i < ARRAY_SIZE(sc->beacon.bslot); i++)
1513 sc->beacon.bslot[i] = ATH_IF_ID_ANY;
Sujithff37e332008-11-24 12:07:55 +05301514
1515 /* save MISC configurations */
1516 sc->sc_config.swBeaconProcess = 1;
1517
Sujithff37e332008-11-24 12:07:55 +05301518 /* setup channels and rates */
1519
1520 sc->sbands[IEEE80211_BAND_2GHZ].channels =
1521 sc->channels[IEEE80211_BAND_2GHZ];
1522 sc->sbands[IEEE80211_BAND_2GHZ].bitrates =
1523 sc->rates[IEEE80211_BAND_2GHZ];
1524 sc->sbands[IEEE80211_BAND_2GHZ].band = IEEE80211_BAND_2GHZ;
1525
1526 if (test_bit(ATH9K_MODE_11A, sc->sc_ah->ah_caps.wireless_modes)) {
1527 sc->sbands[IEEE80211_BAND_5GHZ].channels =
1528 sc->channels[IEEE80211_BAND_5GHZ];
1529 sc->sbands[IEEE80211_BAND_5GHZ].bitrates =
1530 sc->rates[IEEE80211_BAND_5GHZ];
1531 sc->sbands[IEEE80211_BAND_5GHZ].band = IEEE80211_BAND_5GHZ;
1532 }
1533
1534 return 0;
1535bad2:
1536 /* cleanup tx queues */
1537 for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++)
1538 if (ATH_TXQ_SETUP(sc, i))
Sujithb77f4832008-12-07 21:44:03 +05301539 ath_tx_cleanupq(sc, &sc->tx.txq[i]);
Sujithff37e332008-11-24 12:07:55 +05301540bad:
1541 if (ah)
1542 ath9k_hw_detach(ah);
1543
1544 return error;
1545}
1546
Sujith9c84b792008-10-29 10:17:13 +05301547static int ath_attach(u16 devid, struct ath_softc *sc)
Vasanthakumar Thiagarajan8feceb62008-09-10 18:49:27 +05301548{
1549 struct ieee80211_hw *hw = sc->hw;
1550 int error = 0;
1551
Sujith04bd4632008-11-28 22:18:05 +05301552 DPRINTF(sc, ATH_DBG_CONFIG, "Attach ATH hw\n");
Vasanthakumar Thiagarajan8feceb62008-09-10 18:49:27 +05301553
1554 error = ath_init(devid, sc);
1555 if (error != 0)
1556 return error;
1557
Vasanthakumar Thiagarajan8feceb62008-09-10 18:49:27 +05301558 /* get mac address from hardware and set in mac80211 */
1559
1560 SET_IEEE80211_PERM_ADDR(hw, sc->sc_myaddr);
1561
Sujith9c84b792008-10-29 10:17:13 +05301562 hw->flags = IEEE80211_HW_RX_INCLUDES_FCS |
1563 IEEE80211_HW_HOST_BROADCAST_PS_BUFFERING |
1564 IEEE80211_HW_SIGNAL_DBM |
1565 IEEE80211_HW_AMPDU_AGGREGATION;
Vasanthakumar Thiagarajan8feceb62008-09-10 18:49:27 +05301566
Sujith9c84b792008-10-29 10:17:13 +05301567 hw->wiphy->interface_modes =
1568 BIT(NL80211_IFTYPE_AP) |
1569 BIT(NL80211_IFTYPE_STATION) |
1570 BIT(NL80211_IFTYPE_ADHOC);
Vasanthakumar Thiagarajan8feceb62008-09-10 18:49:27 +05301571
Vasanthakumar Thiagarajan8feceb62008-09-10 18:49:27 +05301572 hw->queues = 4;
Sujithe63835b2008-11-18 09:07:53 +05301573 hw->max_rates = 4;
1574 hw->max_rate_tries = ATH_11N_TXMAXTRY;
Sujith528f0c62008-10-29 10:14:26 +05301575 hw->sta_data_size = sizeof(struct ath_node);
Sujith5640b082008-10-29 10:16:06 +05301576 hw->vif_data_size = sizeof(struct ath_vap);
Vasanthakumar Thiagarajan8feceb62008-09-10 18:49:27 +05301577
Vasanthakumar Thiagarajan8feceb62008-09-10 18:49:27 +05301578 hw->rate_control_algorithm = "ath9k_rate_control";
Vasanthakumar Thiagarajan8feceb62008-09-10 18:49:27 +05301579
Sujith9c84b792008-10-29 10:17:13 +05301580 if (sc->sc_ah->ah_caps.hw_caps & ATH9K_HW_CAP_HT) {
1581 setup_ht_cap(&sc->sbands[IEEE80211_BAND_2GHZ].ht_cap);
1582 if (test_bit(ATH9K_MODE_11A, sc->sc_ah->ah_caps.wireless_modes))
1583 setup_ht_cap(&sc->sbands[IEEE80211_BAND_5GHZ].ht_cap);
1584 }
1585
1586 hw->wiphy->bands[IEEE80211_BAND_2GHZ] = &sc->sbands[IEEE80211_BAND_2GHZ];
1587 if (test_bit(ATH9K_MODE_11A, sc->sc_ah->ah_caps.wireless_modes))
1588 hw->wiphy->bands[IEEE80211_BAND_5GHZ] =
1589 &sc->sbands[IEEE80211_BAND_5GHZ];
1590
Senthil Balasubramaniandb93e7b2008-11-13 18:01:08 +05301591 /* initialize tx/rx engine */
1592 error = ath_tx_init(sc, ATH_TXBUF);
1593 if (error != 0)
1594 goto detach;
Vasanthakumar Thiagarajan8feceb62008-09-10 18:49:27 +05301595
Senthil Balasubramaniandb93e7b2008-11-13 18:01:08 +05301596 error = ath_rx_init(sc, ATH_RXBUF);
1597 if (error != 0)
1598 goto detach;
Vasanthakumar Thiagarajan8feceb62008-09-10 18:49:27 +05301599
Senthil Balasubramaniane97275c2008-11-13 18:00:02 +05301600#if defined(CONFIG_RFKILL) || defined(CONFIG_RFKILL_MODULE)
Vasanthakumar Thiagarajan500c0642008-09-10 18:50:17 +05301601 /* Initialze h/w Rfkill */
1602 if (sc->sc_ah->ah_caps.hw_caps & ATH9K_HW_CAP_RFSILENT)
1603 INIT_DELAYED_WORK(&sc->rf_kill.rfkill_poll, ath_rfkill_poll);
1604
1605 /* Initialize s/w rfkill */
1606 if (ath_init_sw_rfkill(sc))
1607 goto detach;
1608#endif
1609
Senthil Balasubramaniandb93e7b2008-11-13 18:01:08 +05301610 error = ieee80211_register_hw(hw);
Vasanthakumar Thiagarajan8feceb62008-09-10 18:49:27 +05301611
Senthil Balasubramaniandb93e7b2008-11-13 18:01:08 +05301612 /* Initialize LED control */
1613 ath_init_leds(sc);
Vasanthakumar Thiagarajan8feceb62008-09-10 18:49:27 +05301614
1615 return 0;
1616detach:
1617 ath_detach(sc);
Vasanthakumar Thiagarajan8feceb62008-09-10 18:49:27 +05301618 return error;
1619}
1620
Sujithff37e332008-11-24 12:07:55 +05301621int ath_reset(struct ath_softc *sc, bool retry_tx)
1622{
1623 struct ath_hal *ah = sc->sc_ah;
1624 int status;
1625 int error = 0;
1626
1627 ath9k_hw_set_interrupts(ah, 0);
1628 ath_draintxq(sc, retry_tx);
1629 ath_stoprecv(sc);
1630 ath_flushrecv(sc);
1631
1632 spin_lock_bh(&sc->sc_resetlock);
1633 if (!ath9k_hw_reset(ah, sc->sc_ah->ah_curchan,
Sujith99405f92008-11-24 12:08:35 +05301634 sc->tx_chan_width,
Sujithff37e332008-11-24 12:07:55 +05301635 sc->sc_tx_chainmask, sc->sc_rx_chainmask,
1636 sc->sc_ht_extprotspacing, false, &status)) {
1637 DPRINTF(sc, ATH_DBG_FATAL,
Sujith04bd4632008-11-28 22:18:05 +05301638 "Unable to reset hardware; hal status %u\n", status);
Sujithff37e332008-11-24 12:07:55 +05301639 error = -EIO;
1640 }
1641 spin_unlock_bh(&sc->sc_resetlock);
1642
1643 if (ath_startrecv(sc) != 0)
Sujith04bd4632008-11-28 22:18:05 +05301644 DPRINTF(sc, ATH_DBG_FATAL, "Unable to start recv logic\n");
Sujithff37e332008-11-24 12:07:55 +05301645
1646 /*
1647 * We may be doing a reset in response to a request
1648 * that changes the channel so update any state that
1649 * might change as a result.
1650 */
1651 ath_setcurmode(sc, ath_chan2mode(sc->sc_ah->ah_curchan));
1652
1653 ath_update_txpow(sc);
1654
1655 if (sc->sc_flags & SC_OP_BEACONS)
1656 ath_beacon_config(sc, ATH_IF_ID_ANY); /* restart beacons */
1657
1658 ath9k_hw_set_interrupts(ah, sc->sc_imask);
1659
1660 if (retry_tx) {
1661 int i;
1662 for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++) {
1663 if (ATH_TXQ_SETUP(sc, i)) {
Sujithb77f4832008-12-07 21:44:03 +05301664 spin_lock_bh(&sc->tx.txq[i].axq_lock);
1665 ath_txq_schedule(sc, &sc->tx.txq[i]);
1666 spin_unlock_bh(&sc->tx.txq[i].axq_lock);
Sujithff37e332008-11-24 12:07:55 +05301667 }
1668 }
1669 }
1670
1671 return error;
1672}
1673
1674/*
1675 * This function will allocate both the DMA descriptor structure, and the
1676 * buffers it contains. These are used to contain the descriptors used
1677 * by the system.
1678*/
1679int ath_descdma_setup(struct ath_softc *sc, struct ath_descdma *dd,
1680 struct list_head *head, const char *name,
1681 int nbuf, int ndesc)
1682{
1683#define DS2PHYS(_dd, _ds) \
1684 ((_dd)->dd_desc_paddr + ((caddr_t)(_ds) - (caddr_t)(_dd)->dd_desc))
1685#define ATH_DESC_4KB_BOUND_CHECK(_daddr) ((((_daddr) & 0xFFF) > 0xF7F) ? 1 : 0)
1686#define ATH_DESC_4KB_BOUND_NUM_SKIPPED(_len) ((_len) / 4096)
1687
1688 struct ath_desc *ds;
1689 struct ath_buf *bf;
1690 int i, bsize, error;
1691
Sujith04bd4632008-11-28 22:18:05 +05301692 DPRINTF(sc, ATH_DBG_CONFIG, "%s DMA: %u buffers %u desc/buf\n",
1693 name, nbuf, ndesc);
Sujithff37e332008-11-24 12:07:55 +05301694
1695 /* ath_desc must be a multiple of DWORDs */
1696 if ((sizeof(struct ath_desc) % 4) != 0) {
Sujith04bd4632008-11-28 22:18:05 +05301697 DPRINTF(sc, ATH_DBG_FATAL, "ath_desc not DWORD aligned\n");
Sujithff37e332008-11-24 12:07:55 +05301698 ASSERT((sizeof(struct ath_desc) % 4) == 0);
1699 error = -ENOMEM;
1700 goto fail;
1701 }
1702
1703 dd->dd_name = name;
1704 dd->dd_desc_len = sizeof(struct ath_desc) * nbuf * ndesc;
1705
1706 /*
1707 * Need additional DMA memory because we can't use
1708 * descriptors that cross the 4K page boundary. Assume
1709 * one skipped descriptor per 4K page.
1710 */
1711 if (!(sc->sc_ah->ah_caps.hw_caps & ATH9K_HW_CAP_4KB_SPLITTRANS)) {
1712 u32 ndesc_skipped =
1713 ATH_DESC_4KB_BOUND_NUM_SKIPPED(dd->dd_desc_len);
1714 u32 dma_len;
1715
1716 while (ndesc_skipped) {
1717 dma_len = ndesc_skipped * sizeof(struct ath_desc);
1718 dd->dd_desc_len += dma_len;
1719
1720 ndesc_skipped = ATH_DESC_4KB_BOUND_NUM_SKIPPED(dma_len);
1721 };
1722 }
1723
1724 /* allocate descriptors */
1725 dd->dd_desc = pci_alloc_consistent(sc->pdev,
1726 dd->dd_desc_len,
1727 &dd->dd_desc_paddr);
1728 if (dd->dd_desc == NULL) {
1729 error = -ENOMEM;
1730 goto fail;
1731 }
1732 ds = dd->dd_desc;
Sujith04bd4632008-11-28 22:18:05 +05301733 DPRINTF(sc, ATH_DBG_CONFIG, "%s DMA map: %p (%u) -> %llx (%u)\n",
1734 dd->dd_name, ds, (u32) dd->dd_desc_len,
Sujithff37e332008-11-24 12:07:55 +05301735 ito64(dd->dd_desc_paddr), /*XXX*/(u32) dd->dd_desc_len);
1736
1737 /* allocate buffers */
1738 bsize = sizeof(struct ath_buf) * nbuf;
1739 bf = kmalloc(bsize, GFP_KERNEL);
1740 if (bf == NULL) {
1741 error = -ENOMEM;
1742 goto fail2;
1743 }
1744 memset(bf, 0, bsize);
1745 dd->dd_bufptr = bf;
1746
1747 INIT_LIST_HEAD(head);
1748 for (i = 0; i < nbuf; i++, bf++, ds += ndesc) {
1749 bf->bf_desc = ds;
1750 bf->bf_daddr = DS2PHYS(dd, ds);
1751
1752 if (!(sc->sc_ah->ah_caps.hw_caps &
1753 ATH9K_HW_CAP_4KB_SPLITTRANS)) {
1754 /*
1755 * Skip descriptor addresses which can cause 4KB
1756 * boundary crossing (addr + length) with a 32 dword
1757 * descriptor fetch.
1758 */
1759 while (ATH_DESC_4KB_BOUND_CHECK(bf->bf_daddr)) {
1760 ASSERT((caddr_t) bf->bf_desc <
1761 ((caddr_t) dd->dd_desc +
1762 dd->dd_desc_len));
1763
1764 ds += ndesc;
1765 bf->bf_desc = ds;
1766 bf->bf_daddr = DS2PHYS(dd, ds);
1767 }
1768 }
1769 list_add_tail(&bf->list, head);
1770 }
1771 return 0;
1772fail2:
1773 pci_free_consistent(sc->pdev,
1774 dd->dd_desc_len, dd->dd_desc, dd->dd_desc_paddr);
1775fail:
1776 memset(dd, 0, sizeof(*dd));
1777 return error;
1778#undef ATH_DESC_4KB_BOUND_CHECK
1779#undef ATH_DESC_4KB_BOUND_NUM_SKIPPED
1780#undef DS2PHYS
1781}
1782
1783void ath_descdma_cleanup(struct ath_softc *sc,
1784 struct ath_descdma *dd,
1785 struct list_head *head)
1786{
1787 pci_free_consistent(sc->pdev,
1788 dd->dd_desc_len, dd->dd_desc, dd->dd_desc_paddr);
1789
1790 INIT_LIST_HEAD(head);
1791 kfree(dd->dd_bufptr);
1792 memset(dd, 0, sizeof(*dd));
1793}
1794
1795int ath_get_hal_qnum(u16 queue, struct ath_softc *sc)
1796{
1797 int qnum;
1798
1799 switch (queue) {
1800 case 0:
Sujithb77f4832008-12-07 21:44:03 +05301801 qnum = sc->tx.hwq_map[ATH9K_WME_AC_VO];
Sujithff37e332008-11-24 12:07:55 +05301802 break;
1803 case 1:
Sujithb77f4832008-12-07 21:44:03 +05301804 qnum = sc->tx.hwq_map[ATH9K_WME_AC_VI];
Sujithff37e332008-11-24 12:07:55 +05301805 break;
1806 case 2:
Sujithb77f4832008-12-07 21:44:03 +05301807 qnum = sc->tx.hwq_map[ATH9K_WME_AC_BE];
Sujithff37e332008-11-24 12:07:55 +05301808 break;
1809 case 3:
Sujithb77f4832008-12-07 21:44:03 +05301810 qnum = sc->tx.hwq_map[ATH9K_WME_AC_BK];
Sujithff37e332008-11-24 12:07:55 +05301811 break;
1812 default:
Sujithb77f4832008-12-07 21:44:03 +05301813 qnum = sc->tx.hwq_map[ATH9K_WME_AC_BE];
Sujithff37e332008-11-24 12:07:55 +05301814 break;
1815 }
1816
1817 return qnum;
1818}
1819
1820int ath_get_mac80211_qnum(u32 queue, struct ath_softc *sc)
1821{
1822 int qnum;
1823
1824 switch (queue) {
1825 case ATH9K_WME_AC_VO:
1826 qnum = 0;
1827 break;
1828 case ATH9K_WME_AC_VI:
1829 qnum = 1;
1830 break;
1831 case ATH9K_WME_AC_BE:
1832 qnum = 2;
1833 break;
1834 case ATH9K_WME_AC_BK:
1835 qnum = 3;
1836 break;
1837 default:
1838 qnum = -1;
1839 break;
1840 }
1841
1842 return qnum;
1843}
1844
1845/**********************/
1846/* mac80211 callbacks */
1847/**********************/
1848
Luis R. Rodriguezf078f202008-08-04 00:16:41 -07001849static int ath9k_start(struct ieee80211_hw *hw)
1850{
1851 struct ath_softc *sc = hw->priv;
1852 struct ieee80211_channel *curchan = hw->conf.channel;
Sujithff37e332008-11-24 12:07:55 +05301853 struct ath9k_channel *init_channel;
1854 int error = 0, pos, status;
Luis R. Rodriguezf078f202008-08-04 00:16:41 -07001855
Sujith04bd4632008-11-28 22:18:05 +05301856 DPRINTF(sc, ATH_DBG_CONFIG, "Starting driver with "
1857 "initial channel: %d MHz\n", curchan->center_freq);
Luis R. Rodriguezf078f202008-08-04 00:16:41 -07001858
1859 /* setup initial channel */
1860
1861 pos = ath_get_channel(sc, curchan);
1862 if (pos == -1) {
Sujith04bd4632008-11-28 22:18:05 +05301863 DPRINTF(sc, ATH_DBG_FATAL, "Invalid channel: %d\n", curchan->center_freq);
Sujith9c84b792008-10-29 10:17:13 +05301864 error = -EINVAL;
Sujithff37e332008-11-24 12:07:55 +05301865 goto error;
Luis R. Rodriguezf078f202008-08-04 00:16:41 -07001866 }
1867
Sujith99405f92008-11-24 12:08:35 +05301868 sc->tx_chan_width = ATH9K_HT_MACMODE_20;
Luis R. Rodriguezf078f202008-08-04 00:16:41 -07001869 sc->sc_ah->ah_channels[pos].chanmode =
1870 (curchan->band == IEEE80211_BAND_2GHZ) ? CHANNEL_G : CHANNEL_A;
Sujithff37e332008-11-24 12:07:55 +05301871 init_channel = &sc->sc_ah->ah_channels[pos];
Luis R. Rodriguezf078f202008-08-04 00:16:41 -07001872
Sujithff37e332008-11-24 12:07:55 +05301873 /* Reset SERDES registers */
1874 ath9k_hw_configpcipowersave(sc->sc_ah, 0);
1875
1876 /*
1877 * The basic interface to setting the hardware in a good
1878 * state is ``reset''. On return the hardware is known to
1879 * be powered up and with interrupts disabled. This must
1880 * be followed by initialization of the appropriate bits
1881 * and then setup of the interrupt mask.
1882 */
1883 spin_lock_bh(&sc->sc_resetlock);
1884 if (!ath9k_hw_reset(sc->sc_ah, init_channel,
Sujith99405f92008-11-24 12:08:35 +05301885 sc->tx_chan_width,
Sujithff37e332008-11-24 12:07:55 +05301886 sc->sc_tx_chainmask, sc->sc_rx_chainmask,
1887 sc->sc_ht_extprotspacing, false, &status)) {
Luis R. Rodriguezf078f202008-08-04 00:16:41 -07001888 DPRINTF(sc, ATH_DBG_FATAL,
Sujith04bd4632008-11-28 22:18:05 +05301889 "Unable to reset hardware; hal status %u "
1890 "(freq %u flags 0x%x)\n", status,
Sujithff37e332008-11-24 12:07:55 +05301891 init_channel->channel, init_channel->channelFlags);
1892 error = -EIO;
1893 spin_unlock_bh(&sc->sc_resetlock);
1894 goto error;
Luis R. Rodriguezf078f202008-08-04 00:16:41 -07001895 }
Sujithff37e332008-11-24 12:07:55 +05301896 spin_unlock_bh(&sc->sc_resetlock);
1897
1898 /*
1899 * This is needed only to setup initial state
1900 * but it's best done after a reset.
1901 */
1902 ath_update_txpow(sc);
1903
1904 /*
1905 * Setup the hardware after reset:
1906 * The receive engine is set going.
1907 * Frame transmit is handled entirely
1908 * in the frame output path; there's nothing to do
1909 * here except setup the interrupt mask.
1910 */
1911 if (ath_startrecv(sc) != 0) {
1912 DPRINTF(sc, ATH_DBG_FATAL,
Sujith04bd4632008-11-28 22:18:05 +05301913 "Unable to start recv logic\n");
Sujithff37e332008-11-24 12:07:55 +05301914 error = -EIO;
1915 goto error;
1916 }
1917
1918 /* Setup our intr mask. */
1919 sc->sc_imask = ATH9K_INT_RX | ATH9K_INT_TX
1920 | ATH9K_INT_RXEOL | ATH9K_INT_RXORN
1921 | ATH9K_INT_FATAL | ATH9K_INT_GLOBAL;
1922
1923 if (sc->sc_ah->ah_caps.hw_caps & ATH9K_HW_CAP_GTT)
1924 sc->sc_imask |= ATH9K_INT_GTT;
1925
1926 if (sc->sc_ah->ah_caps.hw_caps & ATH9K_HW_CAP_HT)
1927 sc->sc_imask |= ATH9K_INT_CST;
1928
1929 /*
1930 * Enable MIB interrupts when there are hardware phy counters.
1931 * Note we only do this (at the moment) for station mode.
1932 */
1933 if (ath9k_hw_phycounters(sc->sc_ah) &&
Colin McCabed97809d2008-12-01 13:38:55 -08001934 ((sc->sc_ah->ah_opmode == NL80211_IFTYPE_STATION) ||
1935 (sc->sc_ah->ah_opmode == NL80211_IFTYPE_ADHOC)))
Sujithff37e332008-11-24 12:07:55 +05301936 sc->sc_imask |= ATH9K_INT_MIB;
1937 /*
1938 * Some hardware processes the TIM IE and fires an
1939 * interrupt when the TIM bit is set. For hardware
1940 * that does, if not overridden by configuration,
1941 * enable the TIM interrupt when operating as station.
1942 */
1943 if ((sc->sc_ah->ah_caps.hw_caps & ATH9K_HW_CAP_ENHANCEDPM) &&
Colin McCabed97809d2008-12-01 13:38:55 -08001944 (sc->sc_ah->ah_opmode == NL80211_IFTYPE_STATION) &&
Sujithff37e332008-11-24 12:07:55 +05301945 !sc->sc_config.swBeaconProcess)
1946 sc->sc_imask |= ATH9K_INT_TIM;
1947
1948 ath_setcurmode(sc, ath_chan2mode(init_channel));
1949
1950 sc->sc_flags &= ~SC_OP_INVALID;
1951
1952 /* Disable BMISS interrupt when we're not associated */
1953 sc->sc_imask &= ~(ATH9K_INT_SWBA | ATH9K_INT_BMISS);
1954 ath9k_hw_set_interrupts(sc->sc_ah, sc->sc_imask);
1955
1956 ieee80211_wake_queues(sc->hw);
Luis R. Rodriguezf078f202008-08-04 00:16:41 -07001957
Senthil Balasubramaniane97275c2008-11-13 18:00:02 +05301958#if defined(CONFIG_RFKILL) || defined(CONFIG_RFKILL_MODULE)
Sujith9c84b792008-10-29 10:17:13 +05301959 error = ath_start_rfkill_poll(sc);
Vasanthakumar Thiagarajan500c0642008-09-10 18:50:17 +05301960#endif
1961
Sujithff37e332008-11-24 12:07:55 +05301962error:
Sujith9c84b792008-10-29 10:17:13 +05301963 return error;
Luis R. Rodriguezf078f202008-08-04 00:16:41 -07001964}
1965
1966static int ath9k_tx(struct ieee80211_hw *hw,
1967 struct sk_buff *skb)
1968{
Jouni Malinen147583c2008-08-11 14:01:50 +03001969 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb);
Sujith528f0c62008-10-29 10:14:26 +05301970 struct ath_softc *sc = hw->priv;
1971 struct ath_tx_control txctl;
1972 int hdrlen, padsize;
1973
1974 memset(&txctl, 0, sizeof(struct ath_tx_control));
Jouni Malinen147583c2008-08-11 14:01:50 +03001975
1976 /*
1977 * As a temporary workaround, assign seq# here; this will likely need
1978 * to be cleaned up to work better with Beacon transmission and virtual
1979 * BSSes.
1980 */
1981 if (info->flags & IEEE80211_TX_CTL_ASSIGN_SEQ) {
1982 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *) skb->data;
1983 if (info->flags & IEEE80211_TX_CTL_FIRST_FRAGMENT)
Sujithb77f4832008-12-07 21:44:03 +05301984 sc->tx.seq_no += 0x10;
Jouni Malinen147583c2008-08-11 14:01:50 +03001985 hdr->seq_ctrl &= cpu_to_le16(IEEE80211_SCTL_FRAG);
Sujithb77f4832008-12-07 21:44:03 +05301986 hdr->seq_ctrl |= cpu_to_le16(sc->tx.seq_no);
Jouni Malinen147583c2008-08-11 14:01:50 +03001987 }
Luis R. Rodriguezf078f202008-08-04 00:16:41 -07001988
1989 /* Add the padding after the header if this is not already done */
1990 hdrlen = ieee80211_get_hdrlen_from_skb(skb);
1991 if (hdrlen & 3) {
1992 padsize = hdrlen % 4;
1993 if (skb_headroom(skb) < padsize)
1994 return -1;
1995 skb_push(skb, padsize);
1996 memmove(skb->data, skb->data + padsize, hdrlen);
1997 }
1998
Sujith528f0c62008-10-29 10:14:26 +05301999 /* Check if a tx queue is available */
2000
2001 txctl.txq = ath_test_get_txq(sc, skb);
2002 if (!txctl.txq)
2003 goto exit;
2004
Sujith04bd4632008-11-28 22:18:05 +05302005 DPRINTF(sc, ATH_DBG_XMIT, "transmitting packet, skb: %p\n", skb);
Luis R. Rodriguezf078f202008-08-04 00:16:41 -07002006
Sujith528f0c62008-10-29 10:14:26 +05302007 if (ath_tx_start(sc, skb, &txctl) != 0) {
Sujith04bd4632008-11-28 22:18:05 +05302008 DPRINTF(sc, ATH_DBG_XMIT, "TX failed\n");
Sujith528f0c62008-10-29 10:14:26 +05302009 goto exit;
Luis R. Rodriguezf078f202008-08-04 00:16:41 -07002010 }
2011
2012 return 0;
Sujith528f0c62008-10-29 10:14:26 +05302013exit:
2014 dev_kfree_skb_any(skb);
2015 return 0;
Luis R. Rodriguezf078f202008-08-04 00:16:41 -07002016}
2017
2018static void ath9k_stop(struct ieee80211_hw *hw)
2019{
2020 struct ath_softc *sc = hw->priv;
Sujith9c84b792008-10-29 10:17:13 +05302021
2022 if (sc->sc_flags & SC_OP_INVALID) {
Sujith04bd4632008-11-28 22:18:05 +05302023 DPRINTF(sc, ATH_DBG_ANY, "Device not present\n");
Sujith9c84b792008-10-29 10:17:13 +05302024 return;
2025 }
2026
Sujith04bd4632008-11-28 22:18:05 +05302027 DPRINTF(sc, ATH_DBG_CONFIG, "Cleaning up\n");
Sujithff37e332008-11-24 12:07:55 +05302028
2029 ieee80211_stop_queues(sc->hw);
2030
2031 /* make sure h/w will not generate any interrupt
2032 * before setting the invalid flag. */
2033 ath9k_hw_set_interrupts(sc->sc_ah, 0);
2034
2035 if (!(sc->sc_flags & SC_OP_INVALID)) {
2036 ath_draintxq(sc, false);
2037 ath_stoprecv(sc);
2038 ath9k_hw_phy_disable(sc->sc_ah);
2039 } else
Sujithb77f4832008-12-07 21:44:03 +05302040 sc->rx.rxlink = NULL;
Sujithff37e332008-11-24 12:07:55 +05302041
2042#if defined(CONFIG_RFKILL) || defined(CONFIG_RFKILL_MODULE)
2043 if (sc->sc_ah->ah_caps.hw_caps & ATH9K_HW_CAP_RFSILENT)
2044 cancel_delayed_work_sync(&sc->rf_kill.rfkill_poll);
2045#endif
2046 /* disable HAL and put h/w to sleep */
2047 ath9k_hw_disable(sc->sc_ah);
2048 ath9k_hw_configpcipowersave(sc->sc_ah, 1);
2049
2050 sc->sc_flags |= SC_OP_INVALID;
Luis R. Rodriguezf078f202008-08-04 00:16:41 -07002051
Sujith04bd4632008-11-28 22:18:05 +05302052 DPRINTF(sc, ATH_DBG_CONFIG, "Driver halt\n");
Luis R. Rodriguezf078f202008-08-04 00:16:41 -07002053}
2054
2055static int ath9k_add_interface(struct ieee80211_hw *hw,
2056 struct ieee80211_if_init_conf *conf)
2057{
2058 struct ath_softc *sc = hw->priv;
Sujith5640b082008-10-29 10:16:06 +05302059 struct ath_vap *avp = (void *)conf->vif->drv_priv;
Colin McCabed97809d2008-12-01 13:38:55 -08002060 enum nl80211_iftype ic_opmode = NL80211_IFTYPE_UNSPECIFIED;
Luis R. Rodriguezf078f202008-08-04 00:16:41 -07002061
2062 /* Support only vap for now */
2063
2064 if (sc->sc_nvaps)
2065 return -ENOBUFS;
2066
2067 switch (conf->type) {
Johannes Berg05c914f2008-09-11 00:01:58 +02002068 case NL80211_IFTYPE_STATION:
Colin McCabed97809d2008-12-01 13:38:55 -08002069 ic_opmode = NL80211_IFTYPE_STATION;
Luis R. Rodriguezf078f202008-08-04 00:16:41 -07002070 break;
Johannes Berg05c914f2008-09-11 00:01:58 +02002071 case NL80211_IFTYPE_ADHOC:
Colin McCabed97809d2008-12-01 13:38:55 -08002072 ic_opmode = NL80211_IFTYPE_ADHOC;
Luis R. Rodriguezf078f202008-08-04 00:16:41 -07002073 break;
Johannes Berg05c914f2008-09-11 00:01:58 +02002074 case NL80211_IFTYPE_AP:
Colin McCabed97809d2008-12-01 13:38:55 -08002075 ic_opmode = NL80211_IFTYPE_AP;
Jouni Malinen2ad67de2008-08-11 14:01:47 +03002076 break;
Luis R. Rodriguezf078f202008-08-04 00:16:41 -07002077 default:
2078 DPRINTF(sc, ATH_DBG_FATAL,
Sujith04bd4632008-11-28 22:18:05 +05302079 "Interface type %d not yet supported\n", conf->type);
Luis R. Rodriguezf078f202008-08-04 00:16:41 -07002080 return -EOPNOTSUPP;
2081 }
2082
Sujith04bd4632008-11-28 22:18:05 +05302083 DPRINTF(sc, ATH_DBG_CONFIG, "Attach a VAP of type: %d\n", ic_opmode);
Luis R. Rodriguezf078f202008-08-04 00:16:41 -07002084
Sujith5640b082008-10-29 10:16:06 +05302085 /* Set the VAP opmode */
2086 avp->av_opmode = ic_opmode;
2087 avp->av_bslot = -1;
2088
Colin McCabed97809d2008-12-01 13:38:55 -08002089 if (ic_opmode == NL80211_IFTYPE_AP)
Sujith5640b082008-10-29 10:16:06 +05302090 ath9k_hw_set_tsfadjust(sc->sc_ah, 1);
2091
2092 sc->sc_vaps[0] = conf->vif;
2093 sc->sc_nvaps++;
2094
2095 /* Set the device opmode */
2096 sc->sc_ah->ah_opmode = ic_opmode;
2097
Luis R. Rodriguez6f255422008-10-03 15:45:27 -07002098 if (conf->type == NL80211_IFTYPE_AP) {
2099 /* TODO: is this a suitable place to start ANI for AP mode? */
2100 /* Start ANI */
2101 mod_timer(&sc->sc_ani.timer,
2102 jiffies + msecs_to_jiffies(ATH_ANI_POLLINTERVAL));
2103 }
2104
Luis R. Rodriguezf078f202008-08-04 00:16:41 -07002105 return 0;
2106}
2107
2108static void ath9k_remove_interface(struct ieee80211_hw *hw,
2109 struct ieee80211_if_init_conf *conf)
2110{
2111 struct ath_softc *sc = hw->priv;
Sujith5640b082008-10-29 10:16:06 +05302112 struct ath_vap *avp = (void *)conf->vif->drv_priv;
Luis R. Rodriguezf078f202008-08-04 00:16:41 -07002113
Sujith04bd4632008-11-28 22:18:05 +05302114 DPRINTF(sc, ATH_DBG_CONFIG, "Detach Interface\n");
Luis R. Rodriguezf078f202008-08-04 00:16:41 -07002115
Luis R. Rodriguez6f255422008-10-03 15:45:27 -07002116 /* Stop ANI */
2117 del_timer_sync(&sc->sc_ani.timer);
Luis R. Rodriguezf078f202008-08-04 00:16:41 -07002118
Luis R. Rodriguezf078f202008-08-04 00:16:41 -07002119 /* Reclaim beacon resources */
Colin McCabed97809d2008-12-01 13:38:55 -08002120 if (sc->sc_ah->ah_opmode == NL80211_IFTYPE_AP ||
2121 sc->sc_ah->ah_opmode == NL80211_IFTYPE_ADHOC) {
Sujithb77f4832008-12-07 21:44:03 +05302122 ath9k_hw_stoptxdma(sc->sc_ah, sc->beacon.beaconq);
Luis R. Rodriguezf078f202008-08-04 00:16:41 -07002123 ath_beacon_return(sc, avp);
2124 }
2125
Sujith672840a2008-08-11 14:05:08 +05302126 sc->sc_flags &= ~SC_OP_BEACONS;
Luis R. Rodriguezf078f202008-08-04 00:16:41 -07002127
Sujith5640b082008-10-29 10:16:06 +05302128 sc->sc_vaps[0] = NULL;
2129 sc->sc_nvaps--;
Luis R. Rodriguezf078f202008-08-04 00:16:41 -07002130}
2131
Johannes Berge8975582008-10-09 12:18:51 +02002132static int ath9k_config(struct ieee80211_hw *hw, u32 changed)
Luis R. Rodriguezf078f202008-08-04 00:16:41 -07002133{
2134 struct ath_softc *sc = hw->priv;
Johannes Berge8975582008-10-09 12:18:51 +02002135 struct ieee80211_conf *conf = &hw->conf;
Luis R. Rodriguezf078f202008-08-04 00:16:41 -07002136
Sujithaa33de02008-12-18 11:40:16 +05302137 mutex_lock(&sc->mutex);
Sujith094d05d2008-12-12 11:57:43 +05302138 if (changed & (IEEE80211_CONF_CHANGE_CHANNEL |
2139 IEEE80211_CONF_CHANGE_HT)) {
Sujith99405f92008-11-24 12:08:35 +05302140 struct ieee80211_channel *curchan = hw->conf.channel;
2141 int pos;
Luis R. Rodriguezf078f202008-08-04 00:16:41 -07002142
Sujith04bd4632008-11-28 22:18:05 +05302143 DPRINTF(sc, ATH_DBG_CONFIG, "Set channel: %d MHz\n",
2144 curchan->center_freq);
Johannes Bergae5eb022008-10-14 16:58:37 +02002145
Sujith99405f92008-11-24 12:08:35 +05302146 pos = ath_get_channel(sc, curchan);
2147 if (pos == -1) {
Sujith04bd4632008-11-28 22:18:05 +05302148 DPRINTF(sc, ATH_DBG_FATAL, "Invalid channel: %d\n",
2149 curchan->center_freq);
Sujithaa33de02008-12-18 11:40:16 +05302150 mutex_unlock(&sc->mutex);
Sujith99405f92008-11-24 12:08:35 +05302151 return -EINVAL;
2152 }
2153
2154 sc->tx_chan_width = ATH9K_HT_MACMODE_20;
2155 sc->sc_ah->ah_channels[pos].chanmode =
2156 (curchan->band == IEEE80211_BAND_2GHZ) ?
2157 CHANNEL_G : CHANNEL_A;
2158
Sujith094d05d2008-12-12 11:57:43 +05302159 if (conf->ht.enabled) {
2160 if (conf->ht.channel_type == NL80211_CHAN_HT40PLUS ||
2161 conf->ht.channel_type == NL80211_CHAN_HT40MINUS)
2162 sc->tx_chan_width = ATH9K_HT_MACMODE_2040;
Sujithe11602b2008-11-27 09:46:27 +05302163
2164 sc->sc_ah->ah_channels[pos].chanmode =
2165 ath_get_extchanmode(sc, curchan,
Sujith094d05d2008-12-12 11:57:43 +05302166 conf->ht.channel_type);
Sujithe11602b2008-11-27 09:46:27 +05302167 }
2168
2169 if (ath_set_channel(sc, &sc->sc_ah->ah_channels[pos]) < 0) {
Sujith04bd4632008-11-28 22:18:05 +05302170 DPRINTF(sc, ATH_DBG_FATAL, "Unable to set channel\n");
Sujithaa33de02008-12-18 11:40:16 +05302171 mutex_unlock(&sc->mutex);
Sujithe11602b2008-11-27 09:46:27 +05302172 return -EINVAL;
2173 }
Luis R. Rodriguezf078f202008-08-04 00:16:41 -07002174
Sujith99405f92008-11-24 12:08:35 +05302175 ath_update_chainmask(sc, conf->ht.enabled);
Sujith094d05d2008-12-12 11:57:43 +05302176 }
Sujith86b89ee2008-08-07 10:54:57 +05302177
Luis R. Rodriguez5c020dc2008-10-22 13:28:45 -07002178 if (changed & IEEE80211_CONF_CHANGE_POWER)
2179 sc->sc_config.txpowlimit = 2 * conf->power_level;
Luis R. Rodriguezf078f202008-08-04 00:16:41 -07002180
Sujithaa33de02008-12-18 11:40:16 +05302181 mutex_unlock(&sc->mutex);
Luis R. Rodriguezf078f202008-08-04 00:16:41 -07002182 return 0;
2183}
2184
2185static int ath9k_config_interface(struct ieee80211_hw *hw,
2186 struct ieee80211_vif *vif,
2187 struct ieee80211_if_conf *conf)
2188{
2189 struct ath_softc *sc = hw->priv;
Jouni Malinen2ad67de2008-08-11 14:01:47 +03002190 struct ath_hal *ah = sc->sc_ah;
Sujith5640b082008-10-29 10:16:06 +05302191 struct ath_vap *avp = (void *)vif->drv_priv;
Luis R. Rodriguezf078f202008-08-04 00:16:41 -07002192 u32 rfilt = 0;
2193 int error, i;
Luis R. Rodriguezf078f202008-08-04 00:16:41 -07002194
Jouni Malinen2ad67de2008-08-11 14:01:47 +03002195 /* TODO: Need to decide which hw opmode to use for multi-interface
2196 * cases */
Johannes Berg05c914f2008-09-11 00:01:58 +02002197 if (vif->type == NL80211_IFTYPE_AP &&
Colin McCabed97809d2008-12-01 13:38:55 -08002198 ah->ah_opmode != NL80211_IFTYPE_AP) {
2199 ah->ah_opmode = NL80211_IFTYPE_STATION;
Jouni Malinen2ad67de2008-08-11 14:01:47 +03002200 ath9k_hw_setopmode(ah);
2201 ath9k_hw_write_associd(ah, sc->sc_myaddr, 0);
2202 /* Request full reset to get hw opmode changed properly */
2203 sc->sc_flags |= SC_OP_FULL_RESET;
2204 }
2205
Luis R. Rodriguezf078f202008-08-04 00:16:41 -07002206 if ((conf->changed & IEEE80211_IFCC_BSSID) &&
2207 !is_zero_ether_addr(conf->bssid)) {
2208 switch (vif->type) {
Johannes Berg05c914f2008-09-11 00:01:58 +02002209 case NL80211_IFTYPE_STATION:
2210 case NL80211_IFTYPE_ADHOC:
Luis R. Rodriguezf078f202008-08-04 00:16:41 -07002211 /* Set BSSID */
2212 memcpy(sc->sc_curbssid, conf->bssid, ETH_ALEN);
2213 sc->sc_curaid = 0;
2214 ath9k_hw_write_associd(sc->sc_ah, sc->sc_curbssid,
2215 sc->sc_curaid);
2216
2217 /* Set aggregation protection mode parameters */
2218 sc->sc_config.ath_aggr_prot = 0;
2219
Luis R. Rodriguezf078f202008-08-04 00:16:41 -07002220 DPRINTF(sc, ATH_DBG_CONFIG,
Sujith04bd4632008-11-28 22:18:05 +05302221 "RX filter 0x%x bssid %pM aid 0x%x\n",
2222 rfilt, sc->sc_curbssid, sc->sc_curaid);
Luis R. Rodriguezf078f202008-08-04 00:16:41 -07002223
2224 /* need to reconfigure the beacon */
Sujith672840a2008-08-11 14:05:08 +05302225 sc->sc_flags &= ~SC_OP_BEACONS ;
Luis R. Rodriguezf078f202008-08-04 00:16:41 -07002226
2227 break;
2228 default:
2229 break;
2230 }
2231 }
2232
2233 if ((conf->changed & IEEE80211_IFCC_BEACON) &&
Johannes Berg05c914f2008-09-11 00:01:58 +02002234 ((vif->type == NL80211_IFTYPE_ADHOC) ||
2235 (vif->type == NL80211_IFTYPE_AP))) {
Luis R. Rodriguezf078f202008-08-04 00:16:41 -07002236 /*
2237 * Allocate and setup the beacon frame.
2238 *
2239 * Stop any previous beacon DMA. This may be
2240 * necessary, for example, when an ibss merge
2241 * causes reconfiguration; we may be called
2242 * with beacon transmission active.
2243 */
Sujithb77f4832008-12-07 21:44:03 +05302244 ath9k_hw_stoptxdma(sc->sc_ah, sc->beacon.beaconq);
Luis R. Rodriguezf078f202008-08-04 00:16:41 -07002245
2246 error = ath_beacon_alloc(sc, 0);
2247 if (error != 0)
2248 return error;
2249
2250 ath_beacon_sync(sc, 0);
2251 }
2252
2253 /* Check for WLAN_CAPABILITY_PRIVACY ? */
Colin McCabed97809d2008-12-01 13:38:55 -08002254 if ((avp->av_opmode != NL80211_IFTYPE_STATION)) {
Luis R. Rodriguezf078f202008-08-04 00:16:41 -07002255 for (i = 0; i < IEEE80211_WEP_NKID; i++)
2256 if (ath9k_hw_keyisvalid(sc->sc_ah, (u16)i))
2257 ath9k_hw_keysetmac(sc->sc_ah,
2258 (u16)i,
2259 sc->sc_curbssid);
2260 }
2261
2262 /* Only legacy IBSS for now */
Johannes Berg05c914f2008-09-11 00:01:58 +02002263 if (vif->type == NL80211_IFTYPE_ADHOC)
Luis R. Rodriguezf078f202008-08-04 00:16:41 -07002264 ath_update_chainmask(sc, 0);
2265
2266 return 0;
2267}
2268
2269#define SUPPORTED_FILTERS \
2270 (FIF_PROMISC_IN_BSS | \
2271 FIF_ALLMULTI | \
2272 FIF_CONTROL | \
2273 FIF_OTHER_BSS | \
2274 FIF_BCN_PRBRESP_PROMISC | \
2275 FIF_FCSFAIL)
2276
Sujith7dcfdcd2008-08-11 14:03:13 +05302277/* FIXME: sc->sc_full_reset ? */
Luis R. Rodriguezf078f202008-08-04 00:16:41 -07002278static void ath9k_configure_filter(struct ieee80211_hw *hw,
2279 unsigned int changed_flags,
2280 unsigned int *total_flags,
2281 int mc_count,
2282 struct dev_mc_list *mclist)
2283{
2284 struct ath_softc *sc = hw->priv;
Sujith7dcfdcd2008-08-11 14:03:13 +05302285 u32 rfilt;
Luis R. Rodriguezf078f202008-08-04 00:16:41 -07002286
2287 changed_flags &= SUPPORTED_FILTERS;
2288 *total_flags &= SUPPORTED_FILTERS;
2289
Sujithb77f4832008-12-07 21:44:03 +05302290 sc->rx.rxfilter = *total_flags;
Sujith7dcfdcd2008-08-11 14:03:13 +05302291 rfilt = ath_calcrxfilter(sc);
2292 ath9k_hw_setrxfilter(sc->sc_ah, rfilt);
2293
Luis R. Rodriguezf078f202008-08-04 00:16:41 -07002294 if (changed_flags & FIF_BCN_PRBRESP_PROMISC) {
2295 if (*total_flags & FIF_BCN_PRBRESP_PROMISC)
Sujith7dcfdcd2008-08-11 14:03:13 +05302296 ath9k_hw_write_associd(sc->sc_ah, ath_bcast_mac, 0);
Luis R. Rodriguezf078f202008-08-04 00:16:41 -07002297 }
Sujith7dcfdcd2008-08-11 14:03:13 +05302298
Sujithb77f4832008-12-07 21:44:03 +05302299 DPRINTF(sc, ATH_DBG_CONFIG, "Set HW RX filter: 0x%x\n", sc->rx.rxfilter);
Luis R. Rodriguezf078f202008-08-04 00:16:41 -07002300}
2301
2302static void ath9k_sta_notify(struct ieee80211_hw *hw,
2303 struct ieee80211_vif *vif,
2304 enum sta_notify_cmd cmd,
Johannes Berg17741cd2008-09-11 00:02:02 +02002305 struct ieee80211_sta *sta)
Luis R. Rodriguezf078f202008-08-04 00:16:41 -07002306{
2307 struct ath_softc *sc = hw->priv;
Luis R. Rodriguezf078f202008-08-04 00:16:41 -07002308
2309 switch (cmd) {
2310 case STA_NOTIFY_ADD:
Sujith5640b082008-10-29 10:16:06 +05302311 ath_node_attach(sc, sta);
Luis R. Rodriguezf078f202008-08-04 00:16:41 -07002312 break;
2313 case STA_NOTIFY_REMOVE:
Sujithb5aa9bf2008-10-29 10:13:31 +05302314 ath_node_detach(sc, sta);
Luis R. Rodriguezf078f202008-08-04 00:16:41 -07002315 break;
2316 default:
2317 break;
2318 }
2319}
2320
2321static int ath9k_conf_tx(struct ieee80211_hw *hw,
2322 u16 queue,
2323 const struct ieee80211_tx_queue_params *params)
2324{
2325 struct ath_softc *sc = hw->priv;
Sujithea9880f2008-08-07 10:53:10 +05302326 struct ath9k_tx_queue_info qi;
Luis R. Rodriguezf078f202008-08-04 00:16:41 -07002327 int ret = 0, qnum;
2328
2329 if (queue >= WME_NUM_AC)
2330 return 0;
2331
2332 qi.tqi_aifs = params->aifs;
2333 qi.tqi_cwmin = params->cw_min;
2334 qi.tqi_cwmax = params->cw_max;
2335 qi.tqi_burstTime = params->txop;
2336 qnum = ath_get_hal_qnum(queue, sc);
2337
2338 DPRINTF(sc, ATH_DBG_CONFIG,
Sujith04bd4632008-11-28 22:18:05 +05302339 "Configure tx [queue/halq] [%d/%d], "
Luis R. Rodriguezf078f202008-08-04 00:16:41 -07002340 "aifs: %d, cw_min: %d, cw_max: %d, txop: %d\n",
Sujith04bd4632008-11-28 22:18:05 +05302341 queue, qnum, params->aifs, params->cw_min,
2342 params->cw_max, params->txop);
Luis R. Rodriguezf078f202008-08-04 00:16:41 -07002343
2344 ret = ath_txq_update(sc, qnum, &qi);
2345 if (ret)
Sujith04bd4632008-11-28 22:18:05 +05302346 DPRINTF(sc, ATH_DBG_FATAL, "TXQ Update failed\n");
Luis R. Rodriguezf078f202008-08-04 00:16:41 -07002347
2348 return ret;
2349}
2350
2351static int ath9k_set_key(struct ieee80211_hw *hw,
2352 enum set_key_cmd cmd,
2353 const u8 *local_addr,
2354 const u8 *addr,
2355 struct ieee80211_key_conf *key)
2356{
2357 struct ath_softc *sc = hw->priv;
2358 int ret = 0;
2359
Sujith04bd4632008-11-28 22:18:05 +05302360 DPRINTF(sc, ATH_DBG_KEYCACHE, "Set HW Key\n");
Luis R. Rodriguezf078f202008-08-04 00:16:41 -07002361
2362 switch (cmd) {
2363 case SET_KEY:
2364 ret = ath_key_config(sc, addr, key);
Jouni Malinen6ace2892008-12-17 13:32:17 +02002365 if (ret >= 0) {
2366 key->hw_key_idx = ret;
Luis R. Rodriguezf078f202008-08-04 00:16:41 -07002367 /* push IV and Michael MIC generation to stack */
2368 key->flags |= IEEE80211_KEY_FLAG_GENERATE_IV;
Senthil Balasubramanian1b961752008-09-01 19:45:21 +05302369 if (key->alg == ALG_TKIP)
2370 key->flags |= IEEE80211_KEY_FLAG_GENERATE_MMIC;
Jouni Malinen6ace2892008-12-17 13:32:17 +02002371 ret = 0;
Luis R. Rodriguezf078f202008-08-04 00:16:41 -07002372 }
2373 break;
2374 case DISABLE_KEY:
2375 ath_key_delete(sc, key);
Luis R. Rodriguezf078f202008-08-04 00:16:41 -07002376 break;
2377 default:
2378 ret = -EINVAL;
2379 }
2380
2381 return ret;
2382}
2383
Luis R. Rodriguezf078f202008-08-04 00:16:41 -07002384static void ath9k_bss_info_changed(struct ieee80211_hw *hw,
2385 struct ieee80211_vif *vif,
2386 struct ieee80211_bss_conf *bss_conf,
2387 u32 changed)
2388{
2389 struct ath_softc *sc = hw->priv;
2390
2391 if (changed & BSS_CHANGED_ERP_PREAMBLE) {
Sujith04bd4632008-11-28 22:18:05 +05302392 DPRINTF(sc, ATH_DBG_CONFIG, "BSS Changed PREAMBLE %d\n",
Luis R. Rodriguezf078f202008-08-04 00:16:41 -07002393 bss_conf->use_short_preamble);
2394 if (bss_conf->use_short_preamble)
Sujith672840a2008-08-11 14:05:08 +05302395 sc->sc_flags |= SC_OP_PREAMBLE_SHORT;
Luis R. Rodriguezf078f202008-08-04 00:16:41 -07002396 else
Sujith672840a2008-08-11 14:05:08 +05302397 sc->sc_flags &= ~SC_OP_PREAMBLE_SHORT;
Luis R. Rodriguezf078f202008-08-04 00:16:41 -07002398 }
2399
2400 if (changed & BSS_CHANGED_ERP_CTS_PROT) {
Sujith04bd4632008-11-28 22:18:05 +05302401 DPRINTF(sc, ATH_DBG_CONFIG, "BSS Changed CTS PROT %d\n",
Luis R. Rodriguezf078f202008-08-04 00:16:41 -07002402 bss_conf->use_cts_prot);
2403 if (bss_conf->use_cts_prot &&
2404 hw->conf.channel->band != IEEE80211_BAND_5GHZ)
Sujith672840a2008-08-11 14:05:08 +05302405 sc->sc_flags |= SC_OP_PROTECT_ENABLE;
Luis R. Rodriguezf078f202008-08-04 00:16:41 -07002406 else
Sujith672840a2008-08-11 14:05:08 +05302407 sc->sc_flags &= ~SC_OP_PROTECT_ENABLE;
Luis R. Rodriguezf078f202008-08-04 00:16:41 -07002408 }
2409
Luis R. Rodriguezf078f202008-08-04 00:16:41 -07002410 if (changed & BSS_CHANGED_ASSOC) {
Sujith04bd4632008-11-28 22:18:05 +05302411 DPRINTF(sc, ATH_DBG_CONFIG, "BSS Changed ASSOC %d\n",
Luis R. Rodriguezf078f202008-08-04 00:16:41 -07002412 bss_conf->assoc);
Sujith5640b082008-10-29 10:16:06 +05302413 ath9k_bss_assoc_info(sc, vif, bss_conf);
Luis R. Rodriguezf078f202008-08-04 00:16:41 -07002414 }
2415}
2416
2417static u64 ath9k_get_tsf(struct ieee80211_hw *hw)
2418{
2419 u64 tsf;
2420 struct ath_softc *sc = hw->priv;
2421 struct ath_hal *ah = sc->sc_ah;
2422
2423 tsf = ath9k_hw_gettsf64(ah);
2424
2425 return tsf;
2426}
2427
2428static void ath9k_reset_tsf(struct ieee80211_hw *hw)
2429{
2430 struct ath_softc *sc = hw->priv;
2431 struct ath_hal *ah = sc->sc_ah;
2432
2433 ath9k_hw_reset_tsf(ah);
2434}
2435
2436static int ath9k_ampdu_action(struct ieee80211_hw *hw,
2437 enum ieee80211_ampdu_mlme_action action,
Johannes Berg17741cd2008-09-11 00:02:02 +02002438 struct ieee80211_sta *sta,
2439 u16 tid, u16 *ssn)
Luis R. Rodriguezf078f202008-08-04 00:16:41 -07002440{
2441 struct ath_softc *sc = hw->priv;
2442 int ret = 0;
2443
2444 switch (action) {
2445 case IEEE80211_AMPDU_RX_START:
Sujithdca3edb2008-10-29 10:19:01 +05302446 if (!(sc->sc_flags & SC_OP_RXAGGR))
2447 ret = -ENOTSUPP;
Luis R. Rodriguezf078f202008-08-04 00:16:41 -07002448 break;
2449 case IEEE80211_AMPDU_RX_STOP:
Luis R. Rodriguezf078f202008-08-04 00:16:41 -07002450 break;
2451 case IEEE80211_AMPDU_TX_START:
Sujithb5aa9bf2008-10-29 10:13:31 +05302452 ret = ath_tx_aggr_start(sc, sta, tid, ssn);
Luis R. Rodriguezf078f202008-08-04 00:16:41 -07002453 if (ret < 0)
2454 DPRINTF(sc, ATH_DBG_FATAL,
Sujith04bd4632008-11-28 22:18:05 +05302455 "Unable to start TX aggregation\n");
Luis R. Rodriguezf078f202008-08-04 00:16:41 -07002456 else
Johannes Berg17741cd2008-09-11 00:02:02 +02002457 ieee80211_start_tx_ba_cb_irqsafe(hw, sta->addr, tid);
Luis R. Rodriguezf078f202008-08-04 00:16:41 -07002458 break;
2459 case IEEE80211_AMPDU_TX_STOP:
Sujithb5aa9bf2008-10-29 10:13:31 +05302460 ret = ath_tx_aggr_stop(sc, sta, tid);
Luis R. Rodriguezf078f202008-08-04 00:16:41 -07002461 if (ret < 0)
2462 DPRINTF(sc, ATH_DBG_FATAL,
Sujith04bd4632008-11-28 22:18:05 +05302463 "Unable to stop TX aggregation\n");
Luis R. Rodriguezf078f202008-08-04 00:16:41 -07002464
Johannes Berg17741cd2008-09-11 00:02:02 +02002465 ieee80211_stop_tx_ba_cb_irqsafe(hw, sta->addr, tid);
Luis R. Rodriguezf078f202008-08-04 00:16:41 -07002466 break;
Sujith8469cde2008-10-29 10:19:28 +05302467 case IEEE80211_AMPDU_TX_RESUME:
2468 ath_tx_aggr_resume(sc, sta, tid);
2469 break;
Luis R. Rodriguezf078f202008-08-04 00:16:41 -07002470 default:
Sujith04bd4632008-11-28 22:18:05 +05302471 DPRINTF(sc, ATH_DBG_FATAL, "Unknown AMPDU action\n");
Luis R. Rodriguezf078f202008-08-04 00:16:41 -07002472 }
2473
2474 return ret;
2475}
2476
2477static struct ieee80211_ops ath9k_ops = {
2478 .tx = ath9k_tx,
2479 .start = ath9k_start,
2480 .stop = ath9k_stop,
2481 .add_interface = ath9k_add_interface,
2482 .remove_interface = ath9k_remove_interface,
2483 .config = ath9k_config,
2484 .config_interface = ath9k_config_interface,
2485 .configure_filter = ath9k_configure_filter,
Luis R. Rodriguezf078f202008-08-04 00:16:41 -07002486 .sta_notify = ath9k_sta_notify,
2487 .conf_tx = ath9k_conf_tx,
Luis R. Rodriguezf078f202008-08-04 00:16:41 -07002488 .bss_info_changed = ath9k_bss_info_changed,
Luis R. Rodriguezf078f202008-08-04 00:16:41 -07002489 .set_key = ath9k_set_key,
Luis R. Rodriguezf078f202008-08-04 00:16:41 -07002490 .get_tsf = ath9k_get_tsf,
2491 .reset_tsf = ath9k_reset_tsf,
Johannes Berg4233df62008-10-13 13:35:05 +02002492 .ampdu_action = ath9k_ampdu_action,
Luis R. Rodriguezf078f202008-08-04 00:16:41 -07002493};
2494
Benoit PAPILLAULT392dff82008-11-06 22:26:49 +01002495static struct {
2496 u32 version;
2497 const char * name;
2498} ath_mac_bb_names[] = {
2499 { AR_SREV_VERSION_5416_PCI, "5416" },
2500 { AR_SREV_VERSION_5416_PCIE, "5418" },
2501 { AR_SREV_VERSION_9100, "9100" },
2502 { AR_SREV_VERSION_9160, "9160" },
2503 { AR_SREV_VERSION_9280, "9280" },
2504 { AR_SREV_VERSION_9285, "9285" }
2505};
2506
2507static struct {
2508 u16 version;
2509 const char * name;
2510} ath_rf_names[] = {
2511 { 0, "5133" },
2512 { AR_RAD5133_SREV_MAJOR, "5133" },
2513 { AR_RAD5122_SREV_MAJOR, "5122" },
2514 { AR_RAD2133_SREV_MAJOR, "2133" },
2515 { AR_RAD2122_SREV_MAJOR, "2122" }
2516};
2517
2518/*
2519 * Return the MAC/BB name. "????" is returned if the MAC/BB is unknown.
2520 */
Benoit PAPILLAULT392dff82008-11-06 22:26:49 +01002521static const char *
2522ath_mac_bb_name(u32 mac_bb_version)
2523{
2524 int i;
2525
2526 for (i=0; i<ARRAY_SIZE(ath_mac_bb_names); i++) {
2527 if (ath_mac_bb_names[i].version == mac_bb_version) {
2528 return ath_mac_bb_names[i].name;
2529 }
2530 }
2531
2532 return "????";
2533}
2534
2535/*
2536 * Return the RF name. "????" is returned if the RF is unknown.
2537 */
Benoit PAPILLAULT392dff82008-11-06 22:26:49 +01002538static const char *
2539ath_rf_name(u16 rf_version)
2540{
2541 int i;
2542
2543 for (i=0; i<ARRAY_SIZE(ath_rf_names); i++) {
2544 if (ath_rf_names[i].version == rf_version) {
2545 return ath_rf_names[i].name;
2546 }
2547 }
2548
2549 return "????";
2550}
2551
Luis R. Rodriguezf078f202008-08-04 00:16:41 -07002552static int ath_pci_probe(struct pci_dev *pdev, const struct pci_device_id *id)
2553{
2554 void __iomem *mem;
2555 struct ath_softc *sc;
2556 struct ieee80211_hw *hw;
Luis R. Rodriguezf078f202008-08-04 00:16:41 -07002557 u8 csz;
2558 u32 val;
2559 int ret = 0;
Benoit PAPILLAULT392dff82008-11-06 22:26:49 +01002560 struct ath_hal *ah;
Luis R. Rodriguezf078f202008-08-04 00:16:41 -07002561
2562 if (pci_enable_device(pdev))
2563 return -EIO;
2564
Luis R. Rodriguez97b777d2008-11-13 19:11:57 -08002565 ret = pci_set_dma_mask(pdev, DMA_32BIT_MASK);
2566
2567 if (ret) {
Luis R. Rodriguez1d450cf2008-11-13 19:11:56 -08002568 printk(KERN_ERR "ath9k: 32-bit DMA not available\n");
Luis R. Rodriguez97b777d2008-11-13 19:11:57 -08002569 goto bad;
2570 }
2571
2572 ret = pci_set_consistent_dma_mask(pdev, DMA_32BIT_MASK);
2573
2574 if (ret) {
2575 printk(KERN_ERR "ath9k: 32-bit DMA consistent "
Sujith04bd4632008-11-28 22:18:05 +05302576 "DMA enable failed\n");
Luis R. Rodriguezf078f202008-08-04 00:16:41 -07002577 goto bad;
2578 }
2579
2580 /*
2581 * Cache line size is used to size and align various
2582 * structures used to communicate with the hardware.
2583 */
2584 pci_read_config_byte(pdev, PCI_CACHE_LINE_SIZE, &csz);
2585 if (csz == 0) {
2586 /*
2587 * Linux 2.4.18 (at least) writes the cache line size
2588 * register as a 16-bit wide register which is wrong.
2589 * We must have this setup properly for rx buffer
2590 * DMA to work so force a reasonable value here if it
2591 * comes up zero.
2592 */
2593 csz = L1_CACHE_BYTES / sizeof(u32);
2594 pci_write_config_byte(pdev, PCI_CACHE_LINE_SIZE, csz);
2595 }
2596 /*
2597 * The default setting of latency timer yields poor results,
2598 * set it to the value used by other systems. It may be worth
2599 * tweaking this setting more.
2600 */
2601 pci_write_config_byte(pdev, PCI_LATENCY_TIMER, 0xa8);
2602
2603 pci_set_master(pdev);
2604
2605 /*
2606 * Disable the RETRY_TIMEOUT register (0x41) to keep
2607 * PCI Tx retries from interfering with C3 CPU state.
2608 */
2609 pci_read_config_dword(pdev, 0x40, &val);
2610 if ((val & 0x0000ff00) != 0)
2611 pci_write_config_dword(pdev, 0x40, val & 0xffff00ff);
2612
2613 ret = pci_request_region(pdev, 0, "ath9k");
2614 if (ret) {
2615 dev_err(&pdev->dev, "PCI memory region reserve error\n");
2616 ret = -ENODEV;
2617 goto bad;
2618 }
2619
2620 mem = pci_iomap(pdev, 0, 0);
2621 if (!mem) {
2622 printk(KERN_ERR "PCI memory map error\n") ;
2623 ret = -EIO;
2624 goto bad1;
2625 }
2626
2627 hw = ieee80211_alloc_hw(sizeof(struct ath_softc), &ath9k_ops);
2628 if (hw == NULL) {
2629 printk(KERN_ERR "ath_pci: no memory for ieee80211_hw\n");
2630 goto bad2;
2631 }
2632
Luis R. Rodriguezf078f202008-08-04 00:16:41 -07002633 SET_IEEE80211_DEV(hw, &pdev->dev);
2634 pci_set_drvdata(pdev, hw);
2635
2636 sc = hw->priv;
2637 sc->hw = hw;
2638 sc->pdev = pdev;
2639 sc->mem = mem;
2640
2641 if (ath_attach(id->device, sc) != 0) {
2642 ret = -ENODEV;
2643 goto bad3;
2644 }
2645
2646 /* setup interrupt service routine */
2647
2648 if (request_irq(pdev->irq, ath_isr, IRQF_SHARED, "ath", sc)) {
2649 printk(KERN_ERR "%s: request_irq failed\n",
2650 wiphy_name(hw->wiphy));
2651 ret = -EIO;
2652 goto bad4;
2653 }
2654
Benoit PAPILLAULT392dff82008-11-06 22:26:49 +01002655 ah = sc->sc_ah;
2656 printk(KERN_INFO
2657 "%s: Atheros AR%s MAC/BB Rev:%x "
2658 "AR%s RF Rev:%x: mem=0x%lx, irq=%d\n",
Luis R. Rodriguezf078f202008-08-04 00:16:41 -07002659 wiphy_name(hw->wiphy),
Benoit PAPILLAULT392dff82008-11-06 22:26:49 +01002660 ath_mac_bb_name(ah->ah_macVersion),
2661 ah->ah_macRev,
2662 ath_rf_name((ah->ah_analog5GhzRev & AR_RADIO_SREV_MAJOR)),
2663 ah->ah_phyRev,
Luis R. Rodriguezf078f202008-08-04 00:16:41 -07002664 (unsigned long)mem, pdev->irq);
2665
2666 return 0;
2667bad4:
2668 ath_detach(sc);
2669bad3:
2670 ieee80211_free_hw(hw);
2671bad2:
2672 pci_iounmap(pdev, mem);
2673bad1:
2674 pci_release_region(pdev, 0);
2675bad:
2676 pci_disable_device(pdev);
2677 return ret;
2678}
2679
2680static void ath_pci_remove(struct pci_dev *pdev)
2681{
2682 struct ieee80211_hw *hw = pci_get_drvdata(pdev);
2683 struct ath_softc *sc = hw->priv;
2684
Luis R. Rodriguezf078f202008-08-04 00:16:41 -07002685 ath_detach(sc);
Sujith9c84b792008-10-29 10:17:13 +05302686 if (pdev->irq)
2687 free_irq(pdev->irq, sc);
Luis R. Rodriguezf078f202008-08-04 00:16:41 -07002688 pci_iounmap(pdev, sc->mem);
2689 pci_release_region(pdev, 0);
2690 pci_disable_device(pdev);
2691 ieee80211_free_hw(hw);
2692}
2693
2694#ifdef CONFIG_PM
2695
2696static int ath_pci_suspend(struct pci_dev *pdev, pm_message_t state)
2697{
Vasanthakumar Thiagarajanc83be682008-08-25 20:47:29 +05302698 struct ieee80211_hw *hw = pci_get_drvdata(pdev);
2699 struct ath_softc *sc = hw->priv;
2700
2701 ath9k_hw_set_gpio(sc->sc_ah, ATH_LED_PIN, 1);
Vasanthakumar Thiagarajan500c0642008-09-10 18:50:17 +05302702
Senthil Balasubramaniane97275c2008-11-13 18:00:02 +05302703#if defined(CONFIG_RFKILL) || defined(CONFIG_RFKILL_MODULE)
Vasanthakumar Thiagarajan500c0642008-09-10 18:50:17 +05302704 if (sc->sc_ah->ah_caps.hw_caps & ATH9K_HW_CAP_RFSILENT)
2705 cancel_delayed_work_sync(&sc->rf_kill.rfkill_poll);
2706#endif
2707
Luis R. Rodriguezf078f202008-08-04 00:16:41 -07002708 pci_save_state(pdev);
2709 pci_disable_device(pdev);
2710 pci_set_power_state(pdev, 3);
2711
2712 return 0;
2713}
2714
2715static int ath_pci_resume(struct pci_dev *pdev)
2716{
Vasanthakumar Thiagarajanc83be682008-08-25 20:47:29 +05302717 struct ieee80211_hw *hw = pci_get_drvdata(pdev);
2718 struct ath_softc *sc = hw->priv;
Luis R. Rodriguezf078f202008-08-04 00:16:41 -07002719 u32 val;
2720 int err;
2721
2722 err = pci_enable_device(pdev);
2723 if (err)
2724 return err;
2725 pci_restore_state(pdev);
2726 /*
2727 * Suspend/Resume resets the PCI configuration space, so we have to
2728 * re-disable the RETRY_TIMEOUT register (0x41) to keep
2729 * PCI Tx retries from interfering with C3 CPU state
2730 */
2731 pci_read_config_dword(pdev, 0x40, &val);
2732 if ((val & 0x0000ff00) != 0)
2733 pci_write_config_dword(pdev, 0x40, val & 0xffff00ff);
2734
Vasanthakumar Thiagarajanc83be682008-08-25 20:47:29 +05302735 /* Enable LED */
2736 ath9k_hw_cfg_output(sc->sc_ah, ATH_LED_PIN,
2737 AR_GPIO_OUTPUT_MUX_AS_OUTPUT);
2738 ath9k_hw_set_gpio(sc->sc_ah, ATH_LED_PIN, 1);
2739
Senthil Balasubramaniane97275c2008-11-13 18:00:02 +05302740#if defined(CONFIG_RFKILL) || defined(CONFIG_RFKILL_MODULE)
Vasanthakumar Thiagarajan500c0642008-09-10 18:50:17 +05302741 /*
2742 * check the h/w rfkill state on resume
2743 * and start the rfkill poll timer
2744 */
2745 if (sc->sc_ah->ah_caps.hw_caps & ATH9K_HW_CAP_RFSILENT)
2746 queue_delayed_work(sc->hw->workqueue,
2747 &sc->rf_kill.rfkill_poll, 0);
2748#endif
2749
Luis R. Rodriguezf078f202008-08-04 00:16:41 -07002750 return 0;
2751}
2752
2753#endif /* CONFIG_PM */
2754
2755MODULE_DEVICE_TABLE(pci, ath_pci_id_table);
2756
2757static struct pci_driver ath_pci_driver = {
2758 .name = "ath9k",
2759 .id_table = ath_pci_id_table,
2760 .probe = ath_pci_probe,
2761 .remove = ath_pci_remove,
2762#ifdef CONFIG_PM
2763 .suspend = ath_pci_suspend,
2764 .resume = ath_pci_resume,
2765#endif /* CONFIG_PM */
2766};
2767
2768static int __init init_ath_pci(void)
2769{
Vasanthakumar Thiagarajanca8a8562008-12-16 12:37:38 +05302770 int error;
2771
Luis R. Rodriguezf078f202008-08-04 00:16:41 -07002772 printk(KERN_INFO "%s: %s\n", dev_info, ATH_PCI_VERSION);
2773
Vasanthakumar Thiagarajanca8a8562008-12-16 12:37:38 +05302774 /* Register rate control algorithm */
2775 error = ath_rate_control_register();
2776 if (error != 0) {
2777 printk(KERN_ERR
2778 "Unable to register rate control algorithm: %d\n",
2779 error);
2780 ath_rate_control_unregister();
2781 return error;
2782 }
2783
Luis R. Rodriguezf078f202008-08-04 00:16:41 -07002784 if (pci_register_driver(&ath_pci_driver) < 0) {
2785 printk(KERN_ERR
2786 "ath_pci: No devices found, driver not installed.\n");
Vasanthakumar Thiagarajanca8a8562008-12-16 12:37:38 +05302787 ath_rate_control_unregister();
Luis R. Rodriguezf078f202008-08-04 00:16:41 -07002788 pci_unregister_driver(&ath_pci_driver);
2789 return -ENODEV;
2790 }
2791
2792 return 0;
2793}
2794module_init(init_ath_pci);
2795
2796static void __exit exit_ath_pci(void)
2797{
Vasanthakumar Thiagarajanca8a8562008-12-16 12:37:38 +05302798 ath_rate_control_unregister();
Luis R. Rodriguezf078f202008-08-04 00:16:41 -07002799 pci_unregister_driver(&ath_pci_driver);
Sujith04bd4632008-11-28 22:18:05 +05302800 printk(KERN_INFO "%s: Driver unloaded\n", dev_info);
Luis R. Rodriguezf078f202008-08-04 00:16:41 -07002801}
2802module_exit(exit_ath_pci);