Eric W. Biederman | 3b7d192 | 2006-10-04 02:16:59 -0700 | [diff] [blame] | 1 | #ifndef LINUX_MSI_H |
| 2 | #define LINUX_MSI_H |
| 3 | |
Neil Horman | b50cac5 | 2011-10-06 14:08:18 -0400 | [diff] [blame] | 4 | #include <linux/kobject.h> |
Michael Ellerman | 4aa9bc9 | 2007-04-05 17:19:10 +1000 | [diff] [blame] | 5 | #include <linux/list.h> |
| 6 | |
Eric W. Biederman | 3b7d192 | 2006-10-04 02:16:59 -0700 | [diff] [blame] | 7 | struct msi_msg { |
| 8 | u32 address_lo; /* low 32 bits of msi message address */ |
| 9 | u32 address_hi; /* high 32 bits of msi message address */ |
| 10 | u32 data; /* 16 bits of msi message data */ |
| 11 | }; |
| 12 | |
Yijing Wang | 38737d8 | 2014-10-27 10:44:36 +0800 | [diff] [blame] | 13 | extern int pci_msi_ignore_mask; |
Satoru Takeuchi | c54c187 | 2007-01-18 13:50:05 +0900 | [diff] [blame] | 14 | /* Helper functions */ |
Thomas Gleixner | 1c9db52 | 2010-09-28 16:46:51 +0200 | [diff] [blame] | 15 | struct irq_data; |
Thomas Gleixner | 39431ac | 2010-09-28 19:09:51 +0200 | [diff] [blame] | 16 | struct msi_desc; |
Jiang Liu | 25a98bd | 2015-07-09 16:00:45 +0800 | [diff] [blame] | 17 | struct pci_dev; |
Bjorn Helgaas | 2366d06 | 2013-04-18 10:55:46 -0600 | [diff] [blame] | 18 | void __get_cached_msi_msg(struct msi_desc *entry, struct msi_msg *msg); |
Bjorn Helgaas | 2366d06 | 2013-04-18 10:55:46 -0600 | [diff] [blame] | 19 | void get_cached_msi_msg(unsigned int irq, struct msi_msg *msg); |
Jiang Liu | 891d4a4 | 2014-11-09 23:10:33 +0800 | [diff] [blame] | 20 | |
Jiang Liu | fc88419 | 2015-07-09 16:00:46 +0800 | [diff] [blame] | 21 | /** |
| 22 | * struct msi_desc - Descriptor structure for MSI based interrupts |
| 23 | * @list: List head for management |
| 24 | * @irq: The base interrupt number |
| 25 | * @nvec_used: The number of vectors used |
| 26 | * @dev: Pointer to the device which uses this descriptor |
| 27 | * @msg: The last set MSI message cached for reuse |
| 28 | * |
| 29 | * @masked: [PCI MSI/X] Mask bits |
| 30 | * @is_msix: [PCI MSI/X] True if MSI-X |
| 31 | * @multiple: [PCI MSI/X] log2 num of messages allocated |
| 32 | * @multi_cap: [PCI MSI/X] log2 num of messages supported |
| 33 | * @maskbit: [PCI MSI/X] Mask-Pending bit supported? |
| 34 | * @is_64: [PCI MSI/X] Address size: 0=32bit 1=64bit |
| 35 | * @entry_nr: [PCI MSI/X] Entry which is described by this descriptor |
| 36 | * @default_irq:[PCI MSI/X] The default pre-assigned non-MSI irq |
| 37 | * @mask_pos: [PCI MSI] Mask register position |
| 38 | * @mask_base: [PCI MSI-X] Mask register base address |
| 39 | */ |
Eric W. Biederman | 3b7d192 | 2006-10-04 02:16:59 -0700 | [diff] [blame] | 40 | struct msi_desc { |
Jiang Liu | fc88419 | 2015-07-09 16:00:46 +0800 | [diff] [blame] | 41 | /* Shared device/bus type independent data */ |
| 42 | struct list_head list; |
| 43 | unsigned int irq; |
| 44 | unsigned int nvec_used; |
| 45 | struct device *dev; |
| 46 | struct msi_msg msg; |
Eric W. Biederman | 3b7d192 | 2006-10-04 02:16:59 -0700 | [diff] [blame] | 47 | |
Matthew Wilcox | 264d9ca | 2009-03-17 08:54:08 -0400 | [diff] [blame] | 48 | union { |
Jiang Liu | fc88419 | 2015-07-09 16:00:46 +0800 | [diff] [blame] | 49 | /* PCI MSI/X specific data */ |
| 50 | struct { |
| 51 | u32 masked; |
| 52 | struct { |
| 53 | __u8 is_msix : 1; |
| 54 | __u8 multiple : 3; |
| 55 | __u8 multi_cap : 3; |
| 56 | __u8 maskbit : 1; |
| 57 | __u8 is_64 : 1; |
| 58 | __u16 entry_nr; |
| 59 | unsigned default_irq; |
| 60 | } msi_attrib; |
| 61 | union { |
| 62 | u8 mask_pos; |
| 63 | void __iomem *mask_base; |
| 64 | }; |
| 65 | }; |
Eric W. Biederman | 3b7d192 | 2006-10-04 02:16:59 -0700 | [diff] [blame] | 66 | |
Jiang Liu | fc88419 | 2015-07-09 16:00:46 +0800 | [diff] [blame] | 67 | /* |
| 68 | * Non PCI variants add their data structure here. New |
| 69 | * entries need to use a named structure. We want |
| 70 | * proper name spaces for this. The PCI part is |
| 71 | * anonymous for now as it would require an immediate |
| 72 | * tree wide cleanup. |
| 73 | */ |
| 74 | }; |
Eric W. Biederman | 3b7d192 | 2006-10-04 02:16:59 -0700 | [diff] [blame] | 75 | }; |
| 76 | |
Jiang Liu | d31eb34 | 2014-11-15 22:24:03 +0800 | [diff] [blame] | 77 | /* Helpers to hide struct msi_desc implementation details */ |
Jiang Liu | 25a98bd | 2015-07-09 16:00:45 +0800 | [diff] [blame] | 78 | #define msi_desc_to_dev(desc) ((desc)->dev) |
Jiang Liu | 4a7cc83 | 2015-07-09 16:00:44 +0800 | [diff] [blame] | 79 | #define dev_to_msi_list(dev) (&(dev)->msi_list) |
Jiang Liu | d31eb34 | 2014-11-15 22:24:03 +0800 | [diff] [blame] | 80 | #define first_msi_entry(dev) \ |
| 81 | list_first_entry(dev_to_msi_list((dev)), struct msi_desc, list) |
| 82 | #define for_each_msi_entry(desc, dev) \ |
| 83 | list_for_each_entry((desc), dev_to_msi_list((dev)), list) |
| 84 | |
| 85 | #ifdef CONFIG_PCI_MSI |
| 86 | #define first_pci_msi_entry(pdev) first_msi_entry(&(pdev)->dev) |
| 87 | #define for_each_pci_msi_entry(desc, pdev) \ |
| 88 | for_each_msi_entry((desc), &(pdev)->dev) |
| 89 | |
Jiang Liu | 25a98bd | 2015-07-09 16:00:45 +0800 | [diff] [blame] | 90 | struct pci_dev *msi_desc_to_pci_dev(struct msi_desc *desc); |
Jiang Liu | c179c9b | 2015-07-09 16:00:36 +0800 | [diff] [blame] | 91 | void *msi_desc_to_pci_sysdata(struct msi_desc *desc); |
| 92 | #else /* CONFIG_PCI_MSI */ |
| 93 | static inline void *msi_desc_to_pci_sysdata(struct msi_desc *desc) |
| 94 | { |
| 95 | return NULL; |
| 96 | } |
Jiang Liu | d31eb34 | 2014-11-15 22:24:03 +0800 | [diff] [blame] | 97 | #endif /* CONFIG_PCI_MSI */ |
| 98 | |
Jiang Liu | aa48b6f | 2015-07-09 16:00:47 +0800 | [diff] [blame^] | 99 | struct msi_desc *alloc_msi_entry(struct device *dev); |
| 100 | void free_msi_entry(struct msi_desc *entry); |
Jiang Liu | 891d4a4 | 2014-11-09 23:10:33 +0800 | [diff] [blame] | 101 | void __pci_read_msi_msg(struct msi_desc *entry, struct msi_msg *msg); |
Jiang Liu | 83a1891 | 2014-11-09 23:10:34 +0800 | [diff] [blame] | 102 | void __pci_write_msi_msg(struct msi_desc *entry, struct msi_msg *msg); |
| 103 | void pci_write_msi_msg(unsigned int irq, struct msi_msg *msg); |
| 104 | |
Thomas Gleixner | 23ed8d5 | 2014-11-23 11:55:58 +0100 | [diff] [blame] | 105 | u32 __pci_msix_desc_mask_irq(struct msi_desc *desc, u32 flag); |
| 106 | u32 __pci_msi_desc_mask_irq(struct msi_desc *desc, u32 mask, u32 flag); |
| 107 | void pci_msi_mask_irq(struct irq_data *data); |
| 108 | void pci_msi_unmask_irq(struct irq_data *data); |
| 109 | |
Jiang Liu | 83a1891 | 2014-11-09 23:10:34 +0800 | [diff] [blame] | 110 | /* Conversion helpers. Should be removed after merging */ |
| 111 | static inline void __write_msi_msg(struct msi_desc *entry, struct msi_msg *msg) |
| 112 | { |
| 113 | __pci_write_msi_msg(entry, msg); |
| 114 | } |
| 115 | static inline void write_msi_msg(int irq, struct msi_msg *msg) |
| 116 | { |
| 117 | pci_write_msi_msg(irq, msg); |
| 118 | } |
Thomas Gleixner | 23ed8d5 | 2014-11-23 11:55:58 +0100 | [diff] [blame] | 119 | static inline void mask_msi_irq(struct irq_data *data) |
| 120 | { |
| 121 | pci_msi_mask_irq(data); |
| 122 | } |
| 123 | static inline void unmask_msi_irq(struct irq_data *data) |
| 124 | { |
| 125 | pci_msi_unmask_irq(data); |
| 126 | } |
Jiang Liu | 891d4a4 | 2014-11-09 23:10:33 +0800 | [diff] [blame] | 127 | |
Eric W. Biederman | 3b7d192 | 2006-10-04 02:16:59 -0700 | [diff] [blame] | 128 | /* |
Thomas Petazzoni | 4287d82 | 2013-08-09 22:27:06 +0200 | [diff] [blame] | 129 | * The arch hooks to setup up msi irqs. Those functions are |
| 130 | * implemented as weak symbols so that they /can/ be overriden by |
| 131 | * architecture specific code if needed. |
Eric W. Biederman | 3b7d192 | 2006-10-04 02:16:59 -0700 | [diff] [blame] | 132 | */ |
Eric W. Biederman | f7feaca | 2007-01-28 12:56:37 -0700 | [diff] [blame] | 133 | int arch_setup_msi_irq(struct pci_dev *dev, struct msi_desc *desc); |
Eric W. Biederman | 3b7d192 | 2006-10-04 02:16:59 -0700 | [diff] [blame] | 134 | void arch_teardown_msi_irq(unsigned int irq); |
Bjorn Helgaas | 2366d06 | 2013-04-18 10:55:46 -0600 | [diff] [blame] | 135 | int arch_setup_msi_irqs(struct pci_dev *dev, int nvec, int type); |
| 136 | void arch_teardown_msi_irqs(struct pci_dev *dev); |
DuanZhenzhong | ac8344c | 2013-12-04 13:09:16 +0800 | [diff] [blame] | 137 | void arch_restore_msi_irqs(struct pci_dev *dev); |
Thomas Petazzoni | 4287d82 | 2013-08-09 22:27:06 +0200 | [diff] [blame] | 138 | |
| 139 | void default_teardown_msi_irqs(struct pci_dev *dev); |
DuanZhenzhong | ac8344c | 2013-12-04 13:09:16 +0800 | [diff] [blame] | 140 | void default_restore_msi_irqs(struct pci_dev *dev); |
Eric W. Biederman | 3b7d192 | 2006-10-04 02:16:59 -0700 | [diff] [blame] | 141 | |
Yijing Wang | c2791b8 | 2014-11-11 17:45:45 -0700 | [diff] [blame] | 142 | struct msi_controller { |
Thierry Reding | 0cbdcfc | 2013-08-09 22:27:08 +0200 | [diff] [blame] | 143 | struct module *owner; |
| 144 | struct device *dev; |
Thomas Petazzoni | 0d5a6db | 2013-08-09 22:27:09 +0200 | [diff] [blame] | 145 | struct device_node *of_node; |
| 146 | struct list_head list; |
Marc Zyngier | 020c312 | 2014-11-15 10:49:12 +0000 | [diff] [blame] | 147 | #ifdef CONFIG_GENERIC_MSI_IRQ_DOMAIN |
| 148 | struct irq_domain *domain; |
| 149 | #endif |
Thierry Reding | 0cbdcfc | 2013-08-09 22:27:08 +0200 | [diff] [blame] | 150 | |
Yijing Wang | c2791b8 | 2014-11-11 17:45:45 -0700 | [diff] [blame] | 151 | int (*setup_irq)(struct msi_controller *chip, struct pci_dev *dev, |
Thierry Reding | 0cbdcfc | 2013-08-09 22:27:08 +0200 | [diff] [blame] | 152 | struct msi_desc *desc); |
Yijing Wang | c2791b8 | 2014-11-11 17:45:45 -0700 | [diff] [blame] | 153 | void (*teardown_irq)(struct msi_controller *chip, unsigned int irq); |
Thierry Reding | 0cbdcfc | 2013-08-09 22:27:08 +0200 | [diff] [blame] | 154 | }; |
| 155 | |
Jiang Liu | f3cf8bb | 2014-11-12 11:39:03 +0100 | [diff] [blame] | 156 | #ifdef CONFIG_GENERIC_MSI_IRQ_DOMAIN |
Jiang Liu | d910969 | 2014-11-15 22:24:04 +0800 | [diff] [blame] | 157 | |
Jiang Liu | aeeb596 | 2014-11-15 22:24:05 +0800 | [diff] [blame] | 158 | #include <linux/irqhandler.h> |
Jiang Liu | d910969 | 2014-11-15 22:24:04 +0800 | [diff] [blame] | 159 | #include <asm/msi.h> |
| 160 | |
Jiang Liu | f3cf8bb | 2014-11-12 11:39:03 +0100 | [diff] [blame] | 161 | struct irq_domain; |
| 162 | struct irq_chip; |
| 163 | struct device_node; |
| 164 | struct msi_domain_info; |
| 165 | |
| 166 | /** |
| 167 | * struct msi_domain_ops - MSI interrupt domain callbacks |
| 168 | * @get_hwirq: Retrieve the resulting hw irq number |
| 169 | * @msi_init: Domain specific init function for MSI interrupts |
| 170 | * @msi_free: Domain specific function to free a MSI interrupts |
Jiang Liu | d910969 | 2014-11-15 22:24:04 +0800 | [diff] [blame] | 171 | * @msi_check: Callback for verification of the domain/info/dev data |
| 172 | * @msi_prepare: Prepare the allocation of the interrupts in the domain |
| 173 | * @msi_finish: Optional callbacl to finalize the allocation |
| 174 | * @set_desc: Set the msi descriptor for an interrupt |
| 175 | * @handle_error: Optional error handler if the allocation fails |
| 176 | * |
| 177 | * @get_hwirq, @msi_init and @msi_free are callbacks used by |
| 178 | * msi_create_irq_domain() and related interfaces |
| 179 | * |
| 180 | * @msi_check, @msi_prepare, @msi_finish, @set_desc and @handle_error |
| 181 | * are callbacks used by msi_irq_domain_alloc_irqs() and related |
| 182 | * interfaces which are based on msi_desc. |
Jiang Liu | f3cf8bb | 2014-11-12 11:39:03 +0100 | [diff] [blame] | 183 | */ |
| 184 | struct msi_domain_ops { |
Jiang Liu | aeeb596 | 2014-11-15 22:24:05 +0800 | [diff] [blame] | 185 | irq_hw_number_t (*get_hwirq)(struct msi_domain_info *info, |
| 186 | msi_alloc_info_t *arg); |
Jiang Liu | f3cf8bb | 2014-11-12 11:39:03 +0100 | [diff] [blame] | 187 | int (*msi_init)(struct irq_domain *domain, |
| 188 | struct msi_domain_info *info, |
| 189 | unsigned int virq, irq_hw_number_t hwirq, |
Jiang Liu | aeeb596 | 2014-11-15 22:24:05 +0800 | [diff] [blame] | 190 | msi_alloc_info_t *arg); |
Jiang Liu | f3cf8bb | 2014-11-12 11:39:03 +0100 | [diff] [blame] | 191 | void (*msi_free)(struct irq_domain *domain, |
| 192 | struct msi_domain_info *info, |
| 193 | unsigned int virq); |
Jiang Liu | d910969 | 2014-11-15 22:24:04 +0800 | [diff] [blame] | 194 | int (*msi_check)(struct irq_domain *domain, |
| 195 | struct msi_domain_info *info, |
| 196 | struct device *dev); |
| 197 | int (*msi_prepare)(struct irq_domain *domain, |
| 198 | struct device *dev, int nvec, |
| 199 | msi_alloc_info_t *arg); |
| 200 | void (*msi_finish)(msi_alloc_info_t *arg, int retval); |
| 201 | void (*set_desc)(msi_alloc_info_t *arg, |
| 202 | struct msi_desc *desc); |
| 203 | int (*handle_error)(struct irq_domain *domain, |
| 204 | struct msi_desc *desc, int error); |
Jiang Liu | f3cf8bb | 2014-11-12 11:39:03 +0100 | [diff] [blame] | 205 | }; |
| 206 | |
| 207 | /** |
| 208 | * struct msi_domain_info - MSI interrupt domain data |
Jiang Liu | aeeb596 | 2014-11-15 22:24:05 +0800 | [diff] [blame] | 209 | * @flags: Flags to decribe features and capabilities |
| 210 | * @ops: The callback data structure |
| 211 | * @chip: Optional: associated interrupt chip |
| 212 | * @chip_data: Optional: associated interrupt chip data |
| 213 | * @handler: Optional: associated interrupt flow handler |
| 214 | * @handler_data: Optional: associated interrupt flow handler data |
| 215 | * @handler_name: Optional: associated interrupt flow handler name |
| 216 | * @data: Optional: domain specific data |
Jiang Liu | f3cf8bb | 2014-11-12 11:39:03 +0100 | [diff] [blame] | 217 | */ |
| 218 | struct msi_domain_info { |
Jiang Liu | aeeb596 | 2014-11-15 22:24:05 +0800 | [diff] [blame] | 219 | u32 flags; |
Jiang Liu | f3cf8bb | 2014-11-12 11:39:03 +0100 | [diff] [blame] | 220 | struct msi_domain_ops *ops; |
| 221 | struct irq_chip *chip; |
Jiang Liu | aeeb596 | 2014-11-15 22:24:05 +0800 | [diff] [blame] | 222 | void *chip_data; |
| 223 | irq_flow_handler_t handler; |
| 224 | void *handler_data; |
| 225 | const char *handler_name; |
Jiang Liu | f3cf8bb | 2014-11-12 11:39:03 +0100 | [diff] [blame] | 226 | void *data; |
| 227 | }; |
| 228 | |
Jiang Liu | aeeb596 | 2014-11-15 22:24:05 +0800 | [diff] [blame] | 229 | /* Flags for msi_domain_info */ |
| 230 | enum { |
| 231 | /* |
| 232 | * Init non implemented ops callbacks with default MSI domain |
| 233 | * callbacks. |
| 234 | */ |
| 235 | MSI_FLAG_USE_DEF_DOM_OPS = (1 << 0), |
| 236 | /* |
| 237 | * Init non implemented chip callbacks with default MSI chip |
| 238 | * callbacks. |
| 239 | */ |
| 240 | MSI_FLAG_USE_DEF_CHIP_OPS = (1 << 1), |
| 241 | /* Build identity map between hwirq and irq */ |
| 242 | MSI_FLAG_IDENTITY_MAP = (1 << 2), |
| 243 | /* Support multiple PCI MSI interrupts */ |
| 244 | MSI_FLAG_MULTI_PCI_MSI = (1 << 3), |
| 245 | /* Support PCI MSIX interrupts */ |
| 246 | MSI_FLAG_PCI_MSIX = (1 << 4), |
| 247 | }; |
| 248 | |
Jiang Liu | f3cf8bb | 2014-11-12 11:39:03 +0100 | [diff] [blame] | 249 | int msi_domain_set_affinity(struct irq_data *data, const struct cpumask *mask, |
| 250 | bool force); |
| 251 | |
| 252 | struct irq_domain *msi_create_irq_domain(struct device_node *of_node, |
| 253 | struct msi_domain_info *info, |
| 254 | struct irq_domain *parent); |
Jiang Liu | d910969 | 2014-11-15 22:24:04 +0800 | [diff] [blame] | 255 | int msi_domain_alloc_irqs(struct irq_domain *domain, struct device *dev, |
| 256 | int nvec); |
| 257 | void msi_domain_free_irqs(struct irq_domain *domain, struct device *dev); |
Jiang Liu | f3cf8bb | 2014-11-12 11:39:03 +0100 | [diff] [blame] | 258 | struct msi_domain_info *msi_get_domain_info(struct irq_domain *domain); |
| 259 | |
| 260 | #endif /* CONFIG_GENERIC_MSI_IRQ_DOMAIN */ |
| 261 | |
Jiang Liu | 3878eae | 2014-11-11 21:02:18 +0800 | [diff] [blame] | 262 | #ifdef CONFIG_PCI_MSI_IRQ_DOMAIN |
| 263 | void pci_msi_domain_write_msg(struct irq_data *irq_data, struct msi_msg *msg); |
| 264 | struct irq_domain *pci_msi_create_irq_domain(struct device_node *node, |
| 265 | struct msi_domain_info *info, |
| 266 | struct irq_domain *parent); |
| 267 | int pci_msi_domain_alloc_irqs(struct irq_domain *domain, struct pci_dev *dev, |
| 268 | int nvec, int type); |
| 269 | void pci_msi_domain_free_irqs(struct irq_domain *domain, struct pci_dev *dev); |
Jiang Liu | 8e047ad | 2014-11-15 22:24:07 +0800 | [diff] [blame] | 270 | struct irq_domain *pci_msi_create_default_irq_domain(struct device_node *node, |
| 271 | struct msi_domain_info *info, struct irq_domain *parent); |
| 272 | |
Jiang Liu | 3878eae | 2014-11-11 21:02:18 +0800 | [diff] [blame] | 273 | irq_hw_number_t pci_msi_domain_calc_hwirq(struct pci_dev *dev, |
| 274 | struct msi_desc *desc); |
| 275 | int pci_msi_domain_check_cap(struct irq_domain *domain, |
| 276 | struct msi_domain_info *info, struct device *dev); |
| 277 | #endif /* CONFIG_PCI_MSI_IRQ_DOMAIN */ |
| 278 | |
Eric W. Biederman | 3b7d192 | 2006-10-04 02:16:59 -0700 | [diff] [blame] | 279 | #endif /* LINUX_MSI_H */ |