Andy Walls | 29f8a0a | 2009-09-26 23:17:30 -0300 | [diff] [blame] | 1 | /* |
| 2 | * Driver for the Conexant CX23885/7/8 PCIe bridge |
| 3 | * |
| 4 | * CX23888 Integrated Consumer Infrared Controller |
| 5 | * |
Andy Walls | 6afdeaf | 2010-05-23 18:53:35 -0300 | [diff] [blame] | 6 | * Copyright (C) 2009 Andy Walls <awalls@md.metrocast.net> |
Andy Walls | 29f8a0a | 2009-09-26 23:17:30 -0300 | [diff] [blame] | 7 | * |
| 8 | * This program is free software; you can redistribute it and/or |
| 9 | * modify it under the terms of the GNU General Public License |
| 10 | * as published by the Free Software Foundation; either version 2 |
| 11 | * of the License, or (at your option) any later version. |
| 12 | * |
| 13 | * This program is distributed in the hope that it will be useful, |
| 14 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 15 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 16 | * GNU General Public License for more details. |
| 17 | * |
| 18 | * You should have received a copy of the GNU General Public License |
| 19 | * along with this program; if not, write to the Free Software |
| 20 | * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA |
| 21 | * 02110-1301, USA. |
| 22 | */ |
| 23 | |
Andy Walls | 1a0b9d8 | 2009-09-27 18:31:37 -0300 | [diff] [blame] | 24 | #include <linux/kfifo.h> |
Tejun Heo | 5a0e3ad | 2010-03-24 17:04:11 +0900 | [diff] [blame] | 25 | #include <linux/slab.h> |
Andy Walls | 1a0b9d8 | 2009-09-27 18:31:37 -0300 | [diff] [blame] | 26 | |
Andy Walls | 29f8a0a | 2009-09-26 23:17:30 -0300 | [diff] [blame] | 27 | #include <media/v4l2-device.h> |
| 28 | #include <media/v4l2-chip-ident.h> |
Mauro Carvalho Chehab | 6bda964 | 2010-11-17 13:28:38 -0300 | [diff] [blame] | 29 | #include <media/rc-core.h> |
Andy Walls | 29f8a0a | 2009-09-26 23:17:30 -0300 | [diff] [blame] | 30 | |
| 31 | #include "cx23885.h" |
Mauro Carvalho Chehab | ada73ee | 2012-10-27 11:29:23 -0300 | [diff] [blame] | 32 | #include "cx23888-ir.h" |
Andy Walls | 29f8a0a | 2009-09-26 23:17:30 -0300 | [diff] [blame] | 33 | |
Andy Walls | 1a0b9d8 | 2009-09-27 18:31:37 -0300 | [diff] [blame] | 34 | static unsigned int ir_888_debug; |
| 35 | module_param(ir_888_debug, int, 0644); |
| 36 | MODULE_PARM_DESC(ir_888_debug, "enable debug messages [CX23888 IR controller]"); |
| 37 | |
Andy Walls | 29f8a0a | 2009-09-26 23:17:30 -0300 | [diff] [blame] | 38 | #define CX23888_IR_REG_BASE 0x170000 |
| 39 | /* |
| 40 | * These CX23888 register offsets have a straightforward one to one mapping |
| 41 | * to the CX23885 register offsets of 0x200 through 0x218 |
| 42 | */ |
| 43 | #define CX23888_IR_CNTRL_REG 0x170000 |
Andy Walls | 1a0b9d8 | 2009-09-27 18:31:37 -0300 | [diff] [blame] | 44 | #define CNTRL_WIN_3_3 0x00000000 |
| 45 | #define CNTRL_WIN_4_3 0x00000001 |
| 46 | #define CNTRL_WIN_3_4 0x00000002 |
| 47 | #define CNTRL_WIN_4_4 0x00000003 |
| 48 | #define CNTRL_WIN 0x00000003 |
| 49 | #define CNTRL_EDG_NONE 0x00000000 |
| 50 | #define CNTRL_EDG_FALL 0x00000004 |
| 51 | #define CNTRL_EDG_RISE 0x00000008 |
| 52 | #define CNTRL_EDG_BOTH 0x0000000C |
| 53 | #define CNTRL_EDG 0x0000000C |
| 54 | #define CNTRL_DMD 0x00000010 |
| 55 | #define CNTRL_MOD 0x00000020 |
| 56 | #define CNTRL_RFE 0x00000040 |
| 57 | #define CNTRL_TFE 0x00000080 |
| 58 | #define CNTRL_RXE 0x00000100 |
| 59 | #define CNTRL_TXE 0x00000200 |
| 60 | #define CNTRL_RIC 0x00000400 |
| 61 | #define CNTRL_TIC 0x00000800 |
| 62 | #define CNTRL_CPL 0x00001000 |
| 63 | #define CNTRL_LBM 0x00002000 |
| 64 | #define CNTRL_R 0x00004000 |
Andy Walls | 5a28d9a | 2010-07-18 19:57:25 -0300 | [diff] [blame] | 65 | /* CX23888 specific control flag */ |
| 66 | #define CNTRL_IVO 0x00008000 |
Andy Walls | 1a0b9d8 | 2009-09-27 18:31:37 -0300 | [diff] [blame] | 67 | |
Andy Walls | 29f8a0a | 2009-09-26 23:17:30 -0300 | [diff] [blame] | 68 | #define CX23888_IR_TXCLK_REG 0x170004 |
Andy Walls | 1a0b9d8 | 2009-09-27 18:31:37 -0300 | [diff] [blame] | 69 | #define TXCLK_TCD 0x0000FFFF |
| 70 | |
Andy Walls | 29f8a0a | 2009-09-26 23:17:30 -0300 | [diff] [blame] | 71 | #define CX23888_IR_RXCLK_REG 0x170008 |
Andy Walls | 1a0b9d8 | 2009-09-27 18:31:37 -0300 | [diff] [blame] | 72 | #define RXCLK_RCD 0x0000FFFF |
| 73 | |
Andy Walls | 29f8a0a | 2009-09-26 23:17:30 -0300 | [diff] [blame] | 74 | #define CX23888_IR_CDUTY_REG 0x17000C |
Andy Walls | 1a0b9d8 | 2009-09-27 18:31:37 -0300 | [diff] [blame] | 75 | #define CDUTY_CDC 0x0000000F |
| 76 | |
Andy Walls | 29f8a0a | 2009-09-26 23:17:30 -0300 | [diff] [blame] | 77 | #define CX23888_IR_STATS_REG 0x170010 |
Andy Walls | 1a0b9d8 | 2009-09-27 18:31:37 -0300 | [diff] [blame] | 78 | #define STATS_RTO 0x00000001 |
| 79 | #define STATS_ROR 0x00000002 |
| 80 | #define STATS_RBY 0x00000004 |
| 81 | #define STATS_TBY 0x00000008 |
| 82 | #define STATS_RSR 0x00000010 |
| 83 | #define STATS_TSR 0x00000020 |
| 84 | |
Andy Walls | 29f8a0a | 2009-09-26 23:17:30 -0300 | [diff] [blame] | 85 | #define CX23888_IR_IRQEN_REG 0x170014 |
Andy Walls | 1a0b9d8 | 2009-09-27 18:31:37 -0300 | [diff] [blame] | 86 | #define IRQEN_RTE 0x00000001 |
| 87 | #define IRQEN_ROE 0x00000002 |
| 88 | #define IRQEN_RSE 0x00000010 |
| 89 | #define IRQEN_TSE 0x00000020 |
| 90 | |
Andy Walls | 29f8a0a | 2009-09-26 23:17:30 -0300 | [diff] [blame] | 91 | #define CX23888_IR_FILTR_REG 0x170018 |
Andy Walls | 1a0b9d8 | 2009-09-27 18:31:37 -0300 | [diff] [blame] | 92 | #define FILTR_LPF 0x0000FFFF |
| 93 | |
Andy Walls | 29f8a0a | 2009-09-26 23:17:30 -0300 | [diff] [blame] | 94 | /* This register doesn't follow the pattern; it's 0x23C on a CX23885 */ |
| 95 | #define CX23888_IR_FIFO_REG 0x170040 |
Andy Walls | 1a0b9d8 | 2009-09-27 18:31:37 -0300 | [diff] [blame] | 96 | #define FIFO_RXTX 0x0000FFFF |
| 97 | #define FIFO_RXTX_LVL 0x00010000 |
| 98 | #define FIFO_RXTX_RTO 0x0001FFFF |
| 99 | #define FIFO_RX_NDV 0x00020000 |
| 100 | #define FIFO_RX_DEPTH 8 |
| 101 | #define FIFO_TX_DEPTH 8 |
Andy Walls | 29f8a0a | 2009-09-26 23:17:30 -0300 | [diff] [blame] | 102 | |
| 103 | /* CX23888 unique registers */ |
| 104 | #define CX23888_IR_SEEDP_REG 0x17001C |
| 105 | #define CX23888_IR_TIMOL_REG 0x170020 |
| 106 | #define CX23888_IR_WAKE0_REG 0x170024 |
| 107 | #define CX23888_IR_WAKE1_REG 0x170028 |
| 108 | #define CX23888_IR_WAKE2_REG 0x17002C |
| 109 | #define CX23888_IR_MASK0_REG 0x170030 |
| 110 | #define CX23888_IR_MASK1_REG 0x170034 |
| 111 | #define CX23888_IR_MAKS2_REG 0x170038 |
| 112 | #define CX23888_IR_DPIPG_REG 0x17003C |
| 113 | #define CX23888_IR_LEARN_REG 0x170044 |
| 114 | |
Andy Walls | 1a0b9d8 | 2009-09-27 18:31:37 -0300 | [diff] [blame] | 115 | #define CX23888_VIDCLK_FREQ 108000000 /* 108 MHz, BT.656 */ |
Andy Walls | 928213a | 2009-10-29 22:24:34 -0300 | [diff] [blame] | 116 | #define CX23888_IR_REFCLK_FREQ (CX23888_VIDCLK_FREQ / 2) |
Andy Walls | 1a0b9d8 | 2009-09-27 18:31:37 -0300 | [diff] [blame] | 117 | |
Andy Walls | c02e0d1 | 2010-08-01 02:18:13 -0300 | [diff] [blame] | 118 | /* |
| 119 | * We use this union internally for convenience, but callers to tx_write |
| 120 | * and rx_read will be expecting records of type struct ir_raw_event. |
| 121 | * Always ensure the size of this union is dictated by struct ir_raw_event. |
| 122 | */ |
| 123 | union cx23888_ir_fifo_rec { |
| 124 | u32 hw_fifo_data; |
| 125 | struct ir_raw_event ir_core_data; |
| 126 | }; |
| 127 | |
| 128 | #define CX23888_IR_RX_KFIFO_SIZE (256 * sizeof(union cx23888_ir_fifo_rec)) |
| 129 | #define CX23888_IR_TX_KFIFO_SIZE (256 * sizeof(union cx23888_ir_fifo_rec)) |
Andy Walls | 29f8a0a | 2009-09-26 23:17:30 -0300 | [diff] [blame] | 130 | |
| 131 | struct cx23888_ir_state { |
| 132 | struct v4l2_subdev sd; |
| 133 | struct cx23885_dev *dev; |
| 134 | u32 id; |
| 135 | u32 rev; |
Andy Walls | 1a0b9d8 | 2009-09-27 18:31:37 -0300 | [diff] [blame] | 136 | |
| 137 | struct v4l2_subdev_ir_parameters rx_params; |
| 138 | struct mutex rx_params_lock; |
| 139 | atomic_t rxclk_divider; |
| 140 | atomic_t rx_invert; |
| 141 | |
Stefani Seibold | 7801edb | 2009-12-21 14:37:33 -0800 | [diff] [blame] | 142 | struct kfifo rx_kfifo; |
Andy Walls | 1a0b9d8 | 2009-09-27 18:31:37 -0300 | [diff] [blame] | 143 | spinlock_t rx_kfifo_lock; |
| 144 | |
| 145 | struct v4l2_subdev_ir_parameters tx_params; |
| 146 | struct mutex tx_params_lock; |
| 147 | atomic_t txclk_divider; |
Andy Walls | 29f8a0a | 2009-09-26 23:17:30 -0300 | [diff] [blame] | 148 | }; |
| 149 | |
| 150 | static inline struct cx23888_ir_state *to_state(struct v4l2_subdev *sd) |
| 151 | { |
| 152 | return v4l2_get_subdevdata(sd); |
| 153 | } |
| 154 | |
Andy Walls | 1a0b9d8 | 2009-09-27 18:31:37 -0300 | [diff] [blame] | 155 | /* |
| 156 | * IR register block read and write functions |
| 157 | */ |
Andy Walls | 29f8a0a | 2009-09-26 23:17:30 -0300 | [diff] [blame] | 158 | static |
| 159 | inline int cx23888_ir_write4(struct cx23885_dev *dev, u32 addr, u32 value) |
| 160 | { |
| 161 | cx_write(addr, value); |
| 162 | return 0; |
| 163 | } |
| 164 | |
Andy Walls | 29f8a0a | 2009-09-26 23:17:30 -0300 | [diff] [blame] | 165 | static inline u32 cx23888_ir_read4(struct cx23885_dev *dev, u32 addr) |
| 166 | { |
| 167 | return cx_read(addr); |
| 168 | } |
| 169 | |
Andy Walls | 29f8a0a | 2009-09-26 23:17:30 -0300 | [diff] [blame] | 170 | static inline int cx23888_ir_and_or4(struct cx23885_dev *dev, u32 addr, |
| 171 | u32 and_mask, u32 or_value) |
| 172 | { |
Andy Walls | 1a0b9d8 | 2009-09-27 18:31:37 -0300 | [diff] [blame] | 173 | cx_andor(addr, ~and_mask, or_value); |
Andy Walls | 29f8a0a | 2009-09-26 23:17:30 -0300 | [diff] [blame] | 174 | return 0; |
| 175 | } |
| 176 | |
Andy Walls | 1a0b9d8 | 2009-09-27 18:31:37 -0300 | [diff] [blame] | 177 | /* |
| 178 | * Rx and Tx Clock Divider register computations |
| 179 | * |
| 180 | * Note the largest clock divider value of 0xffff corresponds to: |
| 181 | * (0xffff + 1) * 1000 / 108/2 MHz = 1,213,629.629... ns |
| 182 | * which fits in 21 bits, so we'll use unsigned int for time arguments. |
| 183 | */ |
| 184 | static inline u16 count_to_clock_divider(unsigned int d) |
| 185 | { |
Andy Walls | 928213a | 2009-10-29 22:24:34 -0300 | [diff] [blame] | 186 | if (d > RXCLK_RCD + 1) |
Andy Walls | 1a0b9d8 | 2009-09-27 18:31:37 -0300 | [diff] [blame] | 187 | d = RXCLK_RCD; |
| 188 | else if (d < 2) |
| 189 | d = 1; |
| 190 | else |
| 191 | d--; |
| 192 | return (u16) d; |
| 193 | } |
| 194 | |
| 195 | static inline u16 ns_to_clock_divider(unsigned int ns) |
| 196 | { |
| 197 | return count_to_clock_divider( |
Andy Walls | 928213a | 2009-10-29 22:24:34 -0300 | [diff] [blame] | 198 | DIV_ROUND_CLOSEST(CX23888_IR_REFCLK_FREQ / 1000000 * ns, 1000)); |
Andy Walls | 1a0b9d8 | 2009-09-27 18:31:37 -0300 | [diff] [blame] | 199 | } |
| 200 | |
| 201 | static inline unsigned int clock_divider_to_ns(unsigned int divider) |
| 202 | { |
| 203 | /* Period of the Rx or Tx clock in ns */ |
| 204 | return DIV_ROUND_CLOSEST((divider + 1) * 1000, |
Andy Walls | 928213a | 2009-10-29 22:24:34 -0300 | [diff] [blame] | 205 | CX23888_IR_REFCLK_FREQ / 1000000); |
Andy Walls | 1a0b9d8 | 2009-09-27 18:31:37 -0300 | [diff] [blame] | 206 | } |
| 207 | |
| 208 | static inline u16 carrier_freq_to_clock_divider(unsigned int freq) |
| 209 | { |
| 210 | return count_to_clock_divider( |
| 211 | DIV_ROUND_CLOSEST(CX23888_IR_REFCLK_FREQ, freq * 16)); |
| 212 | } |
| 213 | |
| 214 | static inline unsigned int clock_divider_to_carrier_freq(unsigned int divider) |
| 215 | { |
| 216 | return DIV_ROUND_CLOSEST(CX23888_IR_REFCLK_FREQ, (divider + 1) * 16); |
| 217 | } |
| 218 | |
| 219 | static inline u16 freq_to_clock_divider(unsigned int freq, |
| 220 | unsigned int rollovers) |
| 221 | { |
| 222 | return count_to_clock_divider( |
| 223 | DIV_ROUND_CLOSEST(CX23888_IR_REFCLK_FREQ, freq * rollovers)); |
| 224 | } |
| 225 | |
| 226 | static inline unsigned int clock_divider_to_freq(unsigned int divider, |
| 227 | unsigned int rollovers) |
| 228 | { |
| 229 | return DIV_ROUND_CLOSEST(CX23888_IR_REFCLK_FREQ, |
| 230 | (divider + 1) * rollovers); |
| 231 | } |
| 232 | |
| 233 | /* |
| 234 | * Low Pass Filter register calculations |
| 235 | * |
| 236 | * Note the largest count value of 0xffff corresponds to: |
| 237 | * 0xffff * 1000 / 108/2 MHz = 1,213,611.11... ns |
| 238 | * which fits in 21 bits, so we'll use unsigned int for time arguments. |
| 239 | */ |
| 240 | static inline u16 count_to_lpf_count(unsigned int d) |
| 241 | { |
| 242 | if (d > FILTR_LPF) |
| 243 | d = FILTR_LPF; |
| 244 | else if (d < 4) |
| 245 | d = 0; |
| 246 | return (u16) d; |
| 247 | } |
| 248 | |
| 249 | static inline u16 ns_to_lpf_count(unsigned int ns) |
| 250 | { |
| 251 | return count_to_lpf_count( |
Andy Walls | 928213a | 2009-10-29 22:24:34 -0300 | [diff] [blame] | 252 | DIV_ROUND_CLOSEST(CX23888_IR_REFCLK_FREQ / 1000000 * ns, 1000)); |
Andy Walls | 1a0b9d8 | 2009-09-27 18:31:37 -0300 | [diff] [blame] | 253 | } |
| 254 | |
| 255 | static inline unsigned int lpf_count_to_ns(unsigned int count) |
| 256 | { |
| 257 | /* Duration of the Low Pass Filter rejection window in ns */ |
Andy Walls | 928213a | 2009-10-29 22:24:34 -0300 | [diff] [blame] | 258 | return DIV_ROUND_CLOSEST(count * 1000, |
| 259 | CX23888_IR_REFCLK_FREQ / 1000000); |
Andy Walls | 1a0b9d8 | 2009-09-27 18:31:37 -0300 | [diff] [blame] | 260 | } |
| 261 | |
| 262 | static inline unsigned int lpf_count_to_us(unsigned int count) |
| 263 | { |
| 264 | /* Duration of the Low Pass Filter rejection window in us */ |
Andy Walls | 928213a | 2009-10-29 22:24:34 -0300 | [diff] [blame] | 265 | return DIV_ROUND_CLOSEST(count, CX23888_IR_REFCLK_FREQ / 1000000); |
Andy Walls | 1a0b9d8 | 2009-09-27 18:31:37 -0300 | [diff] [blame] | 266 | } |
| 267 | |
| 268 | /* |
| 269 | * FIFO register pulse width count compuations |
| 270 | */ |
| 271 | static u32 clock_divider_to_resolution(u16 divider) |
| 272 | { |
| 273 | /* |
| 274 | * Resolution is the duration of 1 tick of the readable portion of |
| 275 | * of the pulse width counter as read from the FIFO. The two lsb's are |
| 276 | * not readable, hence the << 2. This function returns ns. |
| 277 | */ |
| 278 | return DIV_ROUND_CLOSEST((1 << 2) * ((u32) divider + 1) * 1000, |
Andy Walls | 928213a | 2009-10-29 22:24:34 -0300 | [diff] [blame] | 279 | CX23888_IR_REFCLK_FREQ / 1000000); |
Andy Walls | 1a0b9d8 | 2009-09-27 18:31:37 -0300 | [diff] [blame] | 280 | } |
| 281 | |
| 282 | static u64 pulse_width_count_to_ns(u16 count, u16 divider) |
| 283 | { |
| 284 | u64 n; |
| 285 | u32 rem; |
| 286 | |
| 287 | /* |
| 288 | * The 2 lsb's of the pulse width timer count are not readable, hence |
| 289 | * the (count << 2) | 0x3 |
| 290 | */ |
| 291 | n = (((u64) count << 2) | 0x3) * (divider + 1) * 1000; /* millicycles */ |
Andy Walls | 928213a | 2009-10-29 22:24:34 -0300 | [diff] [blame] | 292 | rem = do_div(n, CX23888_IR_REFCLK_FREQ / 1000000); /* / MHz => ns */ |
| 293 | if (rem >= CX23888_IR_REFCLK_FREQ / 1000000 / 2) |
Andy Walls | 1a0b9d8 | 2009-09-27 18:31:37 -0300 | [diff] [blame] | 294 | n++; |
| 295 | return n; |
| 296 | } |
| 297 | |
| 298 | static unsigned int pulse_width_count_to_us(u16 count, u16 divider) |
| 299 | { |
| 300 | u64 n; |
| 301 | u32 rem; |
| 302 | |
| 303 | /* |
| 304 | * The 2 lsb's of the pulse width timer count are not readable, hence |
| 305 | * the (count << 2) | 0x3 |
| 306 | */ |
Andy Walls | 928213a | 2009-10-29 22:24:34 -0300 | [diff] [blame] | 307 | n = (((u64) count << 2) | 0x3) * (divider + 1); /* cycles */ |
| 308 | rem = do_div(n, CX23888_IR_REFCLK_FREQ / 1000000); /* / MHz => us */ |
| 309 | if (rem >= CX23888_IR_REFCLK_FREQ / 1000000 / 2) |
Andy Walls | 1a0b9d8 | 2009-09-27 18:31:37 -0300 | [diff] [blame] | 310 | n++; |
| 311 | return (unsigned int) n; |
| 312 | } |
| 313 | |
| 314 | /* |
| 315 | * Pulse Clocks computations: Combined Pulse Width Count & Rx Clock Counts |
| 316 | * |
| 317 | * The total pulse clock count is an 18 bit pulse width timer count as the most |
| 318 | * significant part and (up to) 16 bit clock divider count as a modulus. |
| 319 | * When the Rx clock divider ticks down to 0, it increments the 18 bit pulse |
| 320 | * width timer count's least significant bit. |
| 321 | */ |
| 322 | static u64 ns_to_pulse_clocks(u32 ns) |
| 323 | { |
| 324 | u64 clocks; |
| 325 | u32 rem; |
Andy Walls | 928213a | 2009-10-29 22:24:34 -0300 | [diff] [blame] | 326 | clocks = CX23888_IR_REFCLK_FREQ / 1000000 * (u64) ns; /* millicycles */ |
Andy Walls | 1a0b9d8 | 2009-09-27 18:31:37 -0300 | [diff] [blame] | 327 | rem = do_div(clocks, 1000); /* /1000 = cycles */ |
Andy Walls | 928213a | 2009-10-29 22:24:34 -0300 | [diff] [blame] | 328 | if (rem >= 1000 / 2) |
Andy Walls | 1a0b9d8 | 2009-09-27 18:31:37 -0300 | [diff] [blame] | 329 | clocks++; |
| 330 | return clocks; |
| 331 | } |
| 332 | |
| 333 | static u16 pulse_clocks_to_clock_divider(u64 count) |
| 334 | { |
Hans Verkuil | e92ba28 | 2012-05-14 10:17:35 -0300 | [diff] [blame] | 335 | do_div(count, (FIFO_RXTX << 2) | 0x3); |
Andy Walls | 1a0b9d8 | 2009-09-27 18:31:37 -0300 | [diff] [blame] | 336 | |
| 337 | /* net result needs to be rounded down and decremented by 1 */ |
Andy Walls | 928213a | 2009-10-29 22:24:34 -0300 | [diff] [blame] | 338 | if (count > RXCLK_RCD + 1) |
Andy Walls | 1a0b9d8 | 2009-09-27 18:31:37 -0300 | [diff] [blame] | 339 | count = RXCLK_RCD; |
| 340 | else if (count < 2) |
| 341 | count = 1; |
| 342 | else |
| 343 | count--; |
| 344 | return (u16) count; |
| 345 | } |
| 346 | |
| 347 | /* |
| 348 | * IR Control Register helpers |
| 349 | */ |
| 350 | enum tx_fifo_watermark { |
| 351 | TX_FIFO_HALF_EMPTY = 0, |
| 352 | TX_FIFO_EMPTY = CNTRL_TIC, |
| 353 | }; |
| 354 | |
| 355 | enum rx_fifo_watermark { |
| 356 | RX_FIFO_HALF_FULL = 0, |
| 357 | RX_FIFO_NOT_EMPTY = CNTRL_RIC, |
| 358 | }; |
| 359 | |
| 360 | static inline void control_tx_irq_watermark(struct cx23885_dev *dev, |
| 361 | enum tx_fifo_watermark level) |
| 362 | { |
| 363 | cx23888_ir_and_or4(dev, CX23888_IR_CNTRL_REG, ~CNTRL_TIC, level); |
| 364 | } |
| 365 | |
| 366 | static inline void control_rx_irq_watermark(struct cx23885_dev *dev, |
| 367 | enum rx_fifo_watermark level) |
| 368 | { |
| 369 | cx23888_ir_and_or4(dev, CX23888_IR_CNTRL_REG, ~CNTRL_RIC, level); |
| 370 | } |
| 371 | |
| 372 | static inline void control_tx_enable(struct cx23885_dev *dev, bool enable) |
| 373 | { |
| 374 | cx23888_ir_and_or4(dev, CX23888_IR_CNTRL_REG, ~(CNTRL_TXE | CNTRL_TFE), |
| 375 | enable ? (CNTRL_TXE | CNTRL_TFE) : 0); |
| 376 | } |
| 377 | |
| 378 | static inline void control_rx_enable(struct cx23885_dev *dev, bool enable) |
| 379 | { |
| 380 | cx23888_ir_and_or4(dev, CX23888_IR_CNTRL_REG, ~(CNTRL_RXE | CNTRL_RFE), |
| 381 | enable ? (CNTRL_RXE | CNTRL_RFE) : 0); |
| 382 | } |
| 383 | |
| 384 | static inline void control_tx_modulation_enable(struct cx23885_dev *dev, |
| 385 | bool enable) |
| 386 | { |
| 387 | cx23888_ir_and_or4(dev, CX23888_IR_CNTRL_REG, ~CNTRL_MOD, |
| 388 | enable ? CNTRL_MOD : 0); |
| 389 | } |
| 390 | |
| 391 | static inline void control_rx_demodulation_enable(struct cx23885_dev *dev, |
| 392 | bool enable) |
| 393 | { |
| 394 | cx23888_ir_and_or4(dev, CX23888_IR_CNTRL_REG, ~CNTRL_DMD, |
| 395 | enable ? CNTRL_DMD : 0); |
| 396 | } |
| 397 | |
| 398 | static inline void control_rx_s_edge_detection(struct cx23885_dev *dev, |
| 399 | u32 edge_types) |
| 400 | { |
| 401 | cx23888_ir_and_or4(dev, CX23888_IR_CNTRL_REG, ~CNTRL_EDG_BOTH, |
| 402 | edge_types & CNTRL_EDG_BOTH); |
| 403 | } |
| 404 | |
| 405 | static void control_rx_s_carrier_window(struct cx23885_dev *dev, |
| 406 | unsigned int carrier, |
| 407 | unsigned int *carrier_range_low, |
| 408 | unsigned int *carrier_range_high) |
| 409 | { |
| 410 | u32 v; |
| 411 | unsigned int c16 = carrier * 16; |
| 412 | |
| 413 | if (*carrier_range_low < DIV_ROUND_CLOSEST(c16, 16 + 3)) { |
| 414 | v = CNTRL_WIN_3_4; |
| 415 | *carrier_range_low = DIV_ROUND_CLOSEST(c16, 16 + 4); |
| 416 | } else { |
| 417 | v = CNTRL_WIN_3_3; |
| 418 | *carrier_range_low = DIV_ROUND_CLOSEST(c16, 16 + 3); |
| 419 | } |
| 420 | |
| 421 | if (*carrier_range_high > DIV_ROUND_CLOSEST(c16, 16 - 3)) { |
| 422 | v |= CNTRL_WIN_4_3; |
| 423 | *carrier_range_high = DIV_ROUND_CLOSEST(c16, 16 - 4); |
| 424 | } else { |
| 425 | v |= CNTRL_WIN_3_3; |
| 426 | *carrier_range_high = DIV_ROUND_CLOSEST(c16, 16 - 3); |
| 427 | } |
| 428 | cx23888_ir_and_or4(dev, CX23888_IR_CNTRL_REG, ~CNTRL_WIN, v); |
| 429 | } |
| 430 | |
| 431 | static inline void control_tx_polarity_invert(struct cx23885_dev *dev, |
| 432 | bool invert) |
| 433 | { |
| 434 | cx23888_ir_and_or4(dev, CX23888_IR_CNTRL_REG, ~CNTRL_CPL, |
| 435 | invert ? CNTRL_CPL : 0); |
| 436 | } |
| 437 | |
Andy Walls | 5a28d9a | 2010-07-18 19:57:25 -0300 | [diff] [blame] | 438 | static inline void control_tx_level_invert(struct cx23885_dev *dev, |
| 439 | bool invert) |
| 440 | { |
| 441 | cx23888_ir_and_or4(dev, CX23888_IR_CNTRL_REG, ~CNTRL_IVO, |
| 442 | invert ? CNTRL_IVO : 0); |
| 443 | } |
| 444 | |
Andy Walls | 1a0b9d8 | 2009-09-27 18:31:37 -0300 | [diff] [blame] | 445 | /* |
| 446 | * IR Rx & Tx Clock Register helpers |
| 447 | */ |
| 448 | static unsigned int txclk_tx_s_carrier(struct cx23885_dev *dev, |
| 449 | unsigned int freq, |
| 450 | u16 *divider) |
| 451 | { |
| 452 | *divider = carrier_freq_to_clock_divider(freq); |
| 453 | cx23888_ir_write4(dev, CX23888_IR_TXCLK_REG, *divider); |
| 454 | return clock_divider_to_carrier_freq(*divider); |
| 455 | } |
| 456 | |
| 457 | static unsigned int rxclk_rx_s_carrier(struct cx23885_dev *dev, |
| 458 | unsigned int freq, |
| 459 | u16 *divider) |
| 460 | { |
| 461 | *divider = carrier_freq_to_clock_divider(freq); |
| 462 | cx23888_ir_write4(dev, CX23888_IR_RXCLK_REG, *divider); |
| 463 | return clock_divider_to_carrier_freq(*divider); |
| 464 | } |
| 465 | |
| 466 | static u32 txclk_tx_s_max_pulse_width(struct cx23885_dev *dev, u32 ns, |
| 467 | u16 *divider) |
| 468 | { |
| 469 | u64 pulse_clocks; |
| 470 | |
Andy Walls | c02e0d1 | 2010-08-01 02:18:13 -0300 | [diff] [blame] | 471 | if (ns > IR_MAX_DURATION) |
| 472 | ns = IR_MAX_DURATION; |
Andy Walls | 1a0b9d8 | 2009-09-27 18:31:37 -0300 | [diff] [blame] | 473 | pulse_clocks = ns_to_pulse_clocks(ns); |
| 474 | *divider = pulse_clocks_to_clock_divider(pulse_clocks); |
| 475 | cx23888_ir_write4(dev, CX23888_IR_TXCLK_REG, *divider); |
| 476 | return (u32) pulse_width_count_to_ns(FIFO_RXTX, *divider); |
| 477 | } |
| 478 | |
| 479 | static u32 rxclk_rx_s_max_pulse_width(struct cx23885_dev *dev, u32 ns, |
| 480 | u16 *divider) |
| 481 | { |
| 482 | u64 pulse_clocks; |
| 483 | |
Andy Walls | c02e0d1 | 2010-08-01 02:18:13 -0300 | [diff] [blame] | 484 | if (ns > IR_MAX_DURATION) |
| 485 | ns = IR_MAX_DURATION; |
Andy Walls | 1a0b9d8 | 2009-09-27 18:31:37 -0300 | [diff] [blame] | 486 | pulse_clocks = ns_to_pulse_clocks(ns); |
| 487 | *divider = pulse_clocks_to_clock_divider(pulse_clocks); |
| 488 | cx23888_ir_write4(dev, CX23888_IR_RXCLK_REG, *divider); |
| 489 | return (u32) pulse_width_count_to_ns(FIFO_RXTX, *divider); |
| 490 | } |
| 491 | |
| 492 | /* |
| 493 | * IR Tx Carrier Duty Cycle register helpers |
| 494 | */ |
| 495 | static unsigned int cduty_tx_s_duty_cycle(struct cx23885_dev *dev, |
| 496 | unsigned int duty_cycle) |
| 497 | { |
| 498 | u32 n; |
| 499 | n = DIV_ROUND_CLOSEST(duty_cycle * 100, 625); /* 16ths of 100% */ |
| 500 | if (n != 0) |
| 501 | n--; |
| 502 | if (n > 15) |
| 503 | n = 15; |
| 504 | cx23888_ir_write4(dev, CX23888_IR_CDUTY_REG, n); |
Andy Walls | 928213a | 2009-10-29 22:24:34 -0300 | [diff] [blame] | 505 | return DIV_ROUND_CLOSEST((n + 1) * 100, 16); |
Andy Walls | 1a0b9d8 | 2009-09-27 18:31:37 -0300 | [diff] [blame] | 506 | } |
| 507 | |
| 508 | /* |
| 509 | * IR Filter Register helpers |
| 510 | */ |
| 511 | static u32 filter_rx_s_min_width(struct cx23885_dev *dev, u32 min_width_ns) |
| 512 | { |
| 513 | u32 count = ns_to_lpf_count(min_width_ns); |
| 514 | cx23888_ir_write4(dev, CX23888_IR_FILTR_REG, count); |
| 515 | return lpf_count_to_ns(count); |
| 516 | } |
| 517 | |
| 518 | /* |
| 519 | * IR IRQ Enable Register helpers |
| 520 | */ |
| 521 | static inline void irqenable_rx(struct cx23885_dev *dev, u32 mask) |
| 522 | { |
| 523 | mask &= (IRQEN_RTE | IRQEN_ROE | IRQEN_RSE); |
| 524 | cx23888_ir_and_or4(dev, CX23888_IR_IRQEN_REG, |
| 525 | ~(IRQEN_RTE | IRQEN_ROE | IRQEN_RSE), mask); |
| 526 | } |
| 527 | |
| 528 | static inline void irqenable_tx(struct cx23885_dev *dev, u32 mask) |
| 529 | { |
| 530 | mask &= IRQEN_TSE; |
| 531 | cx23888_ir_and_or4(dev, CX23888_IR_IRQEN_REG, ~IRQEN_TSE, mask); |
| 532 | } |
| 533 | |
| 534 | /* |
| 535 | * V4L2 Subdevice IR Ops |
| 536 | */ |
| 537 | static int cx23888_ir_irq_handler(struct v4l2_subdev *sd, u32 status, |
| 538 | bool *handled) |
| 539 | { |
| 540 | struct cx23888_ir_state *state = to_state(sd); |
| 541 | struct cx23885_dev *dev = state->dev; |
Stefani Seibold | 7801edb | 2009-12-21 14:37:33 -0800 | [diff] [blame] | 542 | unsigned long flags; |
Andy Walls | 1a0b9d8 | 2009-09-27 18:31:37 -0300 | [diff] [blame] | 543 | |
| 544 | u32 cntrl = cx23888_ir_read4(dev, CX23888_IR_CNTRL_REG); |
| 545 | u32 irqen = cx23888_ir_read4(dev, CX23888_IR_IRQEN_REG); |
| 546 | u32 stats = cx23888_ir_read4(dev, CX23888_IR_STATS_REG); |
| 547 | |
Andy Walls | c02e0d1 | 2010-08-01 02:18:13 -0300 | [diff] [blame] | 548 | union cx23888_ir_fifo_rec rx_data[FIFO_RX_DEPTH]; |
| 549 | unsigned int i, j, k; |
Andy Walls | 1a0b9d8 | 2009-09-27 18:31:37 -0300 | [diff] [blame] | 550 | u32 events, v; |
| 551 | int tsr, rsr, rto, ror, tse, rse, rte, roe, kror; |
| 552 | |
| 553 | tsr = stats & STATS_TSR; /* Tx FIFO Service Request */ |
| 554 | rsr = stats & STATS_RSR; /* Rx FIFO Service Request */ |
| 555 | rto = stats & STATS_RTO; /* Rx Pulse Width Timer Time Out */ |
| 556 | ror = stats & STATS_ROR; /* Rx FIFO Over Run */ |
| 557 | |
| 558 | tse = irqen & IRQEN_TSE; /* Tx FIFO Service Request IRQ Enable */ |
| 559 | rse = irqen & IRQEN_RSE; /* Rx FIFO Service Reuqest IRQ Enable */ |
| 560 | rte = irqen & IRQEN_RTE; /* Rx Pulse Width Timer Time Out IRQ Enable */ |
| 561 | roe = irqen & IRQEN_ROE; /* Rx FIFO Over Run IRQ Enable */ |
| 562 | |
| 563 | *handled = false; |
| 564 | v4l2_dbg(2, ir_888_debug, sd, "IRQ Status: %s %s %s %s %s %s\n", |
| 565 | tsr ? "tsr" : " ", rsr ? "rsr" : " ", |
| 566 | rto ? "rto" : " ", ror ? "ror" : " ", |
| 567 | stats & STATS_TBY ? "tby" : " ", |
| 568 | stats & STATS_RBY ? "rby" : " "); |
| 569 | |
| 570 | v4l2_dbg(2, ir_888_debug, sd, "IRQ Enables: %s %s %s %s\n", |
| 571 | tse ? "tse" : " ", rse ? "rse" : " ", |
| 572 | rte ? "rte" : " ", roe ? "roe" : " "); |
| 573 | |
| 574 | /* |
| 575 | * Transmitter interrupt service |
| 576 | */ |
| 577 | if (tse && tsr) { |
| 578 | /* |
| 579 | * TODO: |
| 580 | * Check the watermark threshold setting |
| 581 | * Pull FIFO_TX_DEPTH or FIFO_TX_DEPTH/2 entries from tx_kfifo |
| 582 | * Push the data to the hardware FIFO. |
| 583 | * If there was nothing more to send in the tx_kfifo, disable |
| 584 | * the TSR IRQ and notify the v4l2_device. |
| 585 | * If there was something in the tx_kfifo, check the tx_kfifo |
| 586 | * level and notify the v4l2_device, if it is low. |
| 587 | */ |
| 588 | /* For now, inhibit TSR interrupt until Tx is implemented */ |
| 589 | irqenable_tx(dev, 0); |
| 590 | events = V4L2_SUBDEV_IR_TX_FIFO_SERVICE_REQ; |
| 591 | v4l2_subdev_notify(sd, V4L2_SUBDEV_IR_TX_NOTIFY, &events); |
| 592 | *handled = true; |
| 593 | } |
| 594 | |
| 595 | /* |
| 596 | * Receiver interrupt service |
| 597 | */ |
| 598 | kror = 0; |
| 599 | if ((rse && rsr) || (rte && rto)) { |
| 600 | /* |
| 601 | * Receive data on RSR to clear the STATS_RSR. |
| 602 | * Receive data on RTO, since we may not have yet hit the RSR |
| 603 | * watermark when we receive the RTO. |
| 604 | */ |
| 605 | for (i = 0, v = FIFO_RX_NDV; |
| 606 | (v & FIFO_RX_NDV) && !kror; i = 0) { |
| 607 | for (j = 0; |
| 608 | (v & FIFO_RX_NDV) && j < FIFO_RX_DEPTH; j++) { |
| 609 | v = cx23888_ir_read4(dev, CX23888_IR_FIFO_REG); |
Andy Walls | c02e0d1 | 2010-08-01 02:18:13 -0300 | [diff] [blame] | 610 | rx_data[i].hw_fifo_data = v & ~FIFO_RX_NDV; |
| 611 | i++; |
Andy Walls | 1a0b9d8 | 2009-09-27 18:31:37 -0300 | [diff] [blame] | 612 | } |
| 613 | if (i == 0) |
| 614 | break; |
Andy Walls | c02e0d1 | 2010-08-01 02:18:13 -0300 | [diff] [blame] | 615 | j = i * sizeof(union cx23888_ir_fifo_rec); |
Stefani Seibold | 7801edb | 2009-12-21 14:37:33 -0800 | [diff] [blame] | 616 | k = kfifo_in_locked(&state->rx_kfifo, |
| 617 | (unsigned char *) rx_data, j, |
| 618 | &state->rx_kfifo_lock); |
Andy Walls | 1a0b9d8 | 2009-09-27 18:31:37 -0300 | [diff] [blame] | 619 | if (k != j) |
| 620 | kror++; /* rx_kfifo over run */ |
| 621 | } |
| 622 | *handled = true; |
| 623 | } |
| 624 | |
| 625 | events = 0; |
| 626 | v = 0; |
| 627 | if (kror) { |
| 628 | events |= V4L2_SUBDEV_IR_RX_SW_FIFO_OVERRUN; |
| 629 | v4l2_err(sd, "IR receiver software FIFO overrun\n"); |
| 630 | } |
| 631 | if (roe && ror) { |
| 632 | /* |
| 633 | * The RX FIFO Enable (CNTRL_RFE) must be toggled to clear |
| 634 | * the Rx FIFO Over Run status (STATS_ROR) |
| 635 | */ |
| 636 | v |= CNTRL_RFE; |
| 637 | events |= V4L2_SUBDEV_IR_RX_HW_FIFO_OVERRUN; |
| 638 | v4l2_err(sd, "IR receiver hardware FIFO overrun\n"); |
| 639 | } |
| 640 | if (rte && rto) { |
| 641 | /* |
| 642 | * The IR Receiver Enable (CNTRL_RXE) must be toggled to clear |
| 643 | * the Rx Pulse Width Timer Time Out (STATS_RTO) |
| 644 | */ |
| 645 | v |= CNTRL_RXE; |
| 646 | events |= V4L2_SUBDEV_IR_RX_END_OF_RX_DETECTED; |
| 647 | } |
| 648 | if (v) { |
| 649 | /* Clear STATS_ROR & STATS_RTO as needed by reseting hardware */ |
| 650 | cx23888_ir_write4(dev, CX23888_IR_CNTRL_REG, cntrl & ~v); |
| 651 | cx23888_ir_write4(dev, CX23888_IR_CNTRL_REG, cntrl); |
| 652 | *handled = true; |
| 653 | } |
Stefani Seibold | 7801edb | 2009-12-21 14:37:33 -0800 | [diff] [blame] | 654 | |
| 655 | spin_lock_irqsave(&state->rx_kfifo_lock, flags); |
| 656 | if (kfifo_len(&state->rx_kfifo) >= CX23888_IR_RX_KFIFO_SIZE / 2) |
Andy Walls | 1a0b9d8 | 2009-09-27 18:31:37 -0300 | [diff] [blame] | 657 | events |= V4L2_SUBDEV_IR_RX_FIFO_SERVICE_REQ; |
Stefani Seibold | 7801edb | 2009-12-21 14:37:33 -0800 | [diff] [blame] | 658 | spin_unlock_irqrestore(&state->rx_kfifo_lock, flags); |
Andy Walls | 1a0b9d8 | 2009-09-27 18:31:37 -0300 | [diff] [blame] | 659 | |
| 660 | if (events) |
| 661 | v4l2_subdev_notify(sd, V4L2_SUBDEV_IR_RX_NOTIFY, &events); |
| 662 | return 0; |
| 663 | } |
| 664 | |
| 665 | /* Receiver */ |
| 666 | static int cx23888_ir_rx_read(struct v4l2_subdev *sd, u8 *buf, size_t count, |
| 667 | ssize_t *num) |
| 668 | { |
| 669 | struct cx23888_ir_state *state = to_state(sd); |
| 670 | bool invert = (bool) atomic_read(&state->rx_invert); |
| 671 | u16 divider = (u16) atomic_read(&state->rxclk_divider); |
| 672 | |
| 673 | unsigned int i, n; |
Andy Walls | c02e0d1 | 2010-08-01 02:18:13 -0300 | [diff] [blame] | 674 | union cx23888_ir_fifo_rec *p; |
Andy Walls | bd829e9 | 2010-12-19 19:10:28 -0300 | [diff] [blame] | 675 | unsigned u, v, w; |
Andy Walls | 1a0b9d8 | 2009-09-27 18:31:37 -0300 | [diff] [blame] | 676 | |
Andy Walls | c02e0d1 | 2010-08-01 02:18:13 -0300 | [diff] [blame] | 677 | n = count / sizeof(union cx23888_ir_fifo_rec) |
| 678 | * sizeof(union cx23888_ir_fifo_rec); |
Andy Walls | 1a0b9d8 | 2009-09-27 18:31:37 -0300 | [diff] [blame] | 679 | if (n == 0) { |
| 680 | *num = 0; |
| 681 | return 0; |
| 682 | } |
| 683 | |
Stefani Seibold | 7801edb | 2009-12-21 14:37:33 -0800 | [diff] [blame] | 684 | n = kfifo_out_locked(&state->rx_kfifo, buf, n, &state->rx_kfifo_lock); |
Andy Walls | 1a0b9d8 | 2009-09-27 18:31:37 -0300 | [diff] [blame] | 685 | |
Andy Walls | c02e0d1 | 2010-08-01 02:18:13 -0300 | [diff] [blame] | 686 | n /= sizeof(union cx23888_ir_fifo_rec); |
| 687 | *num = n * sizeof(union cx23888_ir_fifo_rec); |
Andy Walls | 1a0b9d8 | 2009-09-27 18:31:37 -0300 | [diff] [blame] | 688 | |
Andy Walls | c02e0d1 | 2010-08-01 02:18:13 -0300 | [diff] [blame] | 689 | for (p = (union cx23888_ir_fifo_rec *) buf, i = 0; i < n; p++, i++) { |
Andy Walls | 1a0b9d8 | 2009-09-27 18:31:37 -0300 | [diff] [blame] | 690 | |
Andy Walls | c02e0d1 | 2010-08-01 02:18:13 -0300 | [diff] [blame] | 691 | if ((p->hw_fifo_data & FIFO_RXTX_RTO) == FIFO_RXTX_RTO) { |
Andy Walls | 2560d94 | 2010-07-31 23:28:37 -0300 | [diff] [blame] | 692 | /* Assume RTO was because of no IR light input */ |
| 693 | u = 0; |
Andy Walls | bd829e9 | 2010-12-19 19:10:28 -0300 | [diff] [blame] | 694 | w = 1; |
Andy Walls | 2560d94 | 2010-07-31 23:28:37 -0300 | [diff] [blame] | 695 | } else { |
Andy Walls | c02e0d1 | 2010-08-01 02:18:13 -0300 | [diff] [blame] | 696 | u = (p->hw_fifo_data & FIFO_RXTX_LVL) ? 1 : 0; |
Andy Walls | 2560d94 | 2010-07-31 23:28:37 -0300 | [diff] [blame] | 697 | if (invert) |
Andy Walls | c02e0d1 | 2010-08-01 02:18:13 -0300 | [diff] [blame] | 698 | u = u ? 0 : 1; |
Andy Walls | bd829e9 | 2010-12-19 19:10:28 -0300 | [diff] [blame] | 699 | w = 0; |
Andy Walls | 2560d94 | 2010-07-31 23:28:37 -0300 | [diff] [blame] | 700 | } |
Andy Walls | 1a0b9d8 | 2009-09-27 18:31:37 -0300 | [diff] [blame] | 701 | |
Andy Walls | c02e0d1 | 2010-08-01 02:18:13 -0300 | [diff] [blame] | 702 | v = (unsigned) pulse_width_count_to_ns( |
| 703 | (u16) (p->hw_fifo_data & FIFO_RXTX), divider); |
| 704 | if (v > IR_MAX_DURATION) |
| 705 | v = IR_MAX_DURATION; |
Andy Walls | 1a0b9d8 | 2009-09-27 18:31:37 -0300 | [diff] [blame] | 706 | |
Maxim Levitsky | dc69798 | 2010-10-24 23:05:29 -0300 | [diff] [blame] | 707 | init_ir_raw_event(&p->ir_core_data); |
Andy Walls | c02e0d1 | 2010-08-01 02:18:13 -0300 | [diff] [blame] | 708 | p->ir_core_data.pulse = u; |
| 709 | p->ir_core_data.duration = v; |
Andy Walls | bd829e9 | 2010-12-19 19:10:28 -0300 | [diff] [blame] | 710 | p->ir_core_data.timeout = w; |
Andy Walls | 1a0b9d8 | 2009-09-27 18:31:37 -0300 | [diff] [blame] | 711 | |
Andy Walls | bd829e9 | 2010-12-19 19:10:28 -0300 | [diff] [blame] | 712 | v4l2_dbg(2, ir_888_debug, sd, "rx read: %10u ns %s %s\n", |
| 713 | v, u ? "mark" : "space", w ? "(timed out)" : ""); |
| 714 | if (w) |
| 715 | v4l2_dbg(2, ir_888_debug, sd, "rx read: end of rx\n"); |
Andy Walls | 1a0b9d8 | 2009-09-27 18:31:37 -0300 | [diff] [blame] | 716 | } |
| 717 | return 0; |
| 718 | } |
| 719 | |
| 720 | static int cx23888_ir_rx_g_parameters(struct v4l2_subdev *sd, |
| 721 | struct v4l2_subdev_ir_parameters *p) |
| 722 | { |
| 723 | struct cx23888_ir_state *state = to_state(sd); |
| 724 | mutex_lock(&state->rx_params_lock); |
| 725 | memcpy(p, &state->rx_params, sizeof(struct v4l2_subdev_ir_parameters)); |
| 726 | mutex_unlock(&state->rx_params_lock); |
| 727 | return 0; |
| 728 | } |
| 729 | |
| 730 | static int cx23888_ir_rx_shutdown(struct v4l2_subdev *sd) |
| 731 | { |
| 732 | struct cx23888_ir_state *state = to_state(sd); |
| 733 | struct cx23885_dev *dev = state->dev; |
| 734 | |
| 735 | mutex_lock(&state->rx_params_lock); |
| 736 | |
| 737 | /* Disable or slow down all IR Rx circuits and counters */ |
| 738 | irqenable_rx(dev, 0); |
| 739 | control_rx_enable(dev, false); |
| 740 | control_rx_demodulation_enable(dev, false); |
| 741 | control_rx_s_edge_detection(dev, CNTRL_EDG_NONE); |
| 742 | filter_rx_s_min_width(dev, 0); |
| 743 | cx23888_ir_write4(dev, CX23888_IR_RXCLK_REG, RXCLK_RCD); |
| 744 | |
| 745 | state->rx_params.shutdown = true; |
| 746 | |
| 747 | mutex_unlock(&state->rx_params_lock); |
| 748 | return 0; |
| 749 | } |
| 750 | |
| 751 | static int cx23888_ir_rx_s_parameters(struct v4l2_subdev *sd, |
| 752 | struct v4l2_subdev_ir_parameters *p) |
| 753 | { |
| 754 | struct cx23888_ir_state *state = to_state(sd); |
| 755 | struct cx23885_dev *dev = state->dev; |
| 756 | struct v4l2_subdev_ir_parameters *o = &state->rx_params; |
| 757 | u16 rxclk_divider; |
| 758 | |
| 759 | if (p->shutdown) |
| 760 | return cx23888_ir_rx_shutdown(sd); |
| 761 | |
| 762 | if (p->mode != V4L2_SUBDEV_IR_MODE_PULSE_WIDTH) |
| 763 | return -ENOSYS; |
| 764 | |
| 765 | mutex_lock(&state->rx_params_lock); |
| 766 | |
| 767 | o->shutdown = p->shutdown; |
| 768 | |
| 769 | o->mode = p->mode = V4L2_SUBDEV_IR_MODE_PULSE_WIDTH; |
| 770 | |
Andy Walls | c02e0d1 | 2010-08-01 02:18:13 -0300 | [diff] [blame] | 771 | o->bytes_per_data_element = p->bytes_per_data_element |
| 772 | = sizeof(union cx23888_ir_fifo_rec); |
Andy Walls | 1a0b9d8 | 2009-09-27 18:31:37 -0300 | [diff] [blame] | 773 | |
| 774 | /* Before we tweak the hardware, we have to disable the receiver */ |
| 775 | irqenable_rx(dev, 0); |
| 776 | control_rx_enable(dev, false); |
| 777 | |
| 778 | control_rx_demodulation_enable(dev, p->modulation); |
| 779 | o->modulation = p->modulation; |
| 780 | |
| 781 | if (p->modulation) { |
| 782 | p->carrier_freq = rxclk_rx_s_carrier(dev, p->carrier_freq, |
| 783 | &rxclk_divider); |
| 784 | |
| 785 | o->carrier_freq = p->carrier_freq; |
| 786 | |
| 787 | o->duty_cycle = p->duty_cycle = 50; |
| 788 | |
| 789 | control_rx_s_carrier_window(dev, p->carrier_freq, |
| 790 | &p->carrier_range_lower, |
| 791 | &p->carrier_range_upper); |
| 792 | o->carrier_range_lower = p->carrier_range_lower; |
| 793 | o->carrier_range_upper = p->carrier_range_upper; |
Andy Walls | ceb152a | 2010-07-31 21:57:42 -0300 | [diff] [blame] | 794 | |
| 795 | p->max_pulse_width = |
| 796 | (u32) pulse_width_count_to_ns(FIFO_RXTX, rxclk_divider); |
Andy Walls | 1a0b9d8 | 2009-09-27 18:31:37 -0300 | [diff] [blame] | 797 | } else { |
| 798 | p->max_pulse_width = |
| 799 | rxclk_rx_s_max_pulse_width(dev, p->max_pulse_width, |
| 800 | &rxclk_divider); |
Andy Walls | 1a0b9d8 | 2009-09-27 18:31:37 -0300 | [diff] [blame] | 801 | } |
Andy Walls | ceb152a | 2010-07-31 21:57:42 -0300 | [diff] [blame] | 802 | o->max_pulse_width = p->max_pulse_width; |
Andy Walls | 1a0b9d8 | 2009-09-27 18:31:37 -0300 | [diff] [blame] | 803 | atomic_set(&state->rxclk_divider, rxclk_divider); |
| 804 | |
| 805 | p->noise_filter_min_width = |
| 806 | filter_rx_s_min_width(dev, p->noise_filter_min_width); |
| 807 | o->noise_filter_min_width = p->noise_filter_min_width; |
| 808 | |
| 809 | p->resolution = clock_divider_to_resolution(rxclk_divider); |
| 810 | o->resolution = p->resolution; |
| 811 | |
| 812 | /* FIXME - make this dependent on resolution for better performance */ |
| 813 | control_rx_irq_watermark(dev, RX_FIFO_HALF_FULL); |
| 814 | |
| 815 | control_rx_s_edge_detection(dev, CNTRL_EDG_BOTH); |
| 816 | |
Andy Walls | 5a28d9a | 2010-07-18 19:57:25 -0300 | [diff] [blame] | 817 | o->invert_level = p->invert_level; |
| 818 | atomic_set(&state->rx_invert, p->invert_level); |
Andy Walls | 1a0b9d8 | 2009-09-27 18:31:37 -0300 | [diff] [blame] | 819 | |
| 820 | o->interrupt_enable = p->interrupt_enable; |
| 821 | o->enable = p->enable; |
| 822 | if (p->enable) { |
Stefani Seibold | 7801edb | 2009-12-21 14:37:33 -0800 | [diff] [blame] | 823 | unsigned long flags; |
| 824 | |
| 825 | spin_lock_irqsave(&state->rx_kfifo_lock, flags); |
| 826 | kfifo_reset(&state->rx_kfifo); |
| 827 | /* reset tx_fifo too if there is one... */ |
| 828 | spin_unlock_irqrestore(&state->rx_kfifo_lock, flags); |
Andy Walls | 1a0b9d8 | 2009-09-27 18:31:37 -0300 | [diff] [blame] | 829 | if (p->interrupt_enable) |
| 830 | irqenable_rx(dev, IRQEN_RSE | IRQEN_RTE | IRQEN_ROE); |
| 831 | control_rx_enable(dev, p->enable); |
| 832 | } |
| 833 | |
| 834 | mutex_unlock(&state->rx_params_lock); |
| 835 | return 0; |
| 836 | } |
| 837 | |
| 838 | /* Transmitter */ |
| 839 | static int cx23888_ir_tx_write(struct v4l2_subdev *sd, u8 *buf, size_t count, |
| 840 | ssize_t *num) |
| 841 | { |
| 842 | struct cx23888_ir_state *state = to_state(sd); |
| 843 | struct cx23885_dev *dev = state->dev; |
| 844 | /* For now enable the Tx FIFO Service interrupt & pretend we did work */ |
| 845 | irqenable_tx(dev, IRQEN_TSE); |
| 846 | *num = count; |
| 847 | return 0; |
| 848 | } |
| 849 | |
| 850 | static int cx23888_ir_tx_g_parameters(struct v4l2_subdev *sd, |
| 851 | struct v4l2_subdev_ir_parameters *p) |
| 852 | { |
| 853 | struct cx23888_ir_state *state = to_state(sd); |
| 854 | mutex_lock(&state->tx_params_lock); |
| 855 | memcpy(p, &state->tx_params, sizeof(struct v4l2_subdev_ir_parameters)); |
| 856 | mutex_unlock(&state->tx_params_lock); |
| 857 | return 0; |
| 858 | } |
| 859 | |
| 860 | static int cx23888_ir_tx_shutdown(struct v4l2_subdev *sd) |
| 861 | { |
| 862 | struct cx23888_ir_state *state = to_state(sd); |
| 863 | struct cx23885_dev *dev = state->dev; |
| 864 | |
| 865 | mutex_lock(&state->tx_params_lock); |
| 866 | |
| 867 | /* Disable or slow down all IR Tx circuits and counters */ |
| 868 | irqenable_tx(dev, 0); |
| 869 | control_tx_enable(dev, false); |
| 870 | control_tx_modulation_enable(dev, false); |
| 871 | cx23888_ir_write4(dev, CX23888_IR_TXCLK_REG, TXCLK_TCD); |
| 872 | |
| 873 | state->tx_params.shutdown = true; |
| 874 | |
| 875 | mutex_unlock(&state->tx_params_lock); |
| 876 | return 0; |
| 877 | } |
| 878 | |
| 879 | static int cx23888_ir_tx_s_parameters(struct v4l2_subdev *sd, |
| 880 | struct v4l2_subdev_ir_parameters *p) |
| 881 | { |
| 882 | struct cx23888_ir_state *state = to_state(sd); |
| 883 | struct cx23885_dev *dev = state->dev; |
| 884 | struct v4l2_subdev_ir_parameters *o = &state->tx_params; |
| 885 | u16 txclk_divider; |
| 886 | |
| 887 | if (p->shutdown) |
| 888 | return cx23888_ir_tx_shutdown(sd); |
| 889 | |
| 890 | if (p->mode != V4L2_SUBDEV_IR_MODE_PULSE_WIDTH) |
| 891 | return -ENOSYS; |
| 892 | |
| 893 | mutex_lock(&state->tx_params_lock); |
| 894 | |
| 895 | o->shutdown = p->shutdown; |
| 896 | |
| 897 | o->mode = p->mode = V4L2_SUBDEV_IR_MODE_PULSE_WIDTH; |
| 898 | |
Andy Walls | c02e0d1 | 2010-08-01 02:18:13 -0300 | [diff] [blame] | 899 | o->bytes_per_data_element = p->bytes_per_data_element |
| 900 | = sizeof(union cx23888_ir_fifo_rec); |
Andy Walls | 1a0b9d8 | 2009-09-27 18:31:37 -0300 | [diff] [blame] | 901 | |
| 902 | /* Before we tweak the hardware, we have to disable the transmitter */ |
| 903 | irqenable_tx(dev, 0); |
| 904 | control_tx_enable(dev, false); |
| 905 | |
| 906 | control_tx_modulation_enable(dev, p->modulation); |
| 907 | o->modulation = p->modulation; |
| 908 | |
| 909 | if (p->modulation) { |
| 910 | p->carrier_freq = txclk_tx_s_carrier(dev, p->carrier_freq, |
| 911 | &txclk_divider); |
| 912 | o->carrier_freq = p->carrier_freq; |
| 913 | |
| 914 | p->duty_cycle = cduty_tx_s_duty_cycle(dev, p->duty_cycle); |
| 915 | o->duty_cycle = p->duty_cycle; |
Andy Walls | ceb152a | 2010-07-31 21:57:42 -0300 | [diff] [blame] | 916 | |
| 917 | p->max_pulse_width = |
| 918 | (u32) pulse_width_count_to_ns(FIFO_RXTX, txclk_divider); |
Andy Walls | 1a0b9d8 | 2009-09-27 18:31:37 -0300 | [diff] [blame] | 919 | } else { |
| 920 | p->max_pulse_width = |
| 921 | txclk_tx_s_max_pulse_width(dev, p->max_pulse_width, |
| 922 | &txclk_divider); |
Andy Walls | 1a0b9d8 | 2009-09-27 18:31:37 -0300 | [diff] [blame] | 923 | } |
Andy Walls | ceb152a | 2010-07-31 21:57:42 -0300 | [diff] [blame] | 924 | o->max_pulse_width = p->max_pulse_width; |
Andy Walls | 1a0b9d8 | 2009-09-27 18:31:37 -0300 | [diff] [blame] | 925 | atomic_set(&state->txclk_divider, txclk_divider); |
| 926 | |
| 927 | p->resolution = clock_divider_to_resolution(txclk_divider); |
| 928 | o->resolution = p->resolution; |
| 929 | |
| 930 | /* FIXME - make this dependent on resolution for better performance */ |
| 931 | control_tx_irq_watermark(dev, TX_FIFO_HALF_EMPTY); |
| 932 | |
Andy Walls | 5a28d9a | 2010-07-18 19:57:25 -0300 | [diff] [blame] | 933 | control_tx_polarity_invert(dev, p->invert_carrier_sense); |
| 934 | o->invert_carrier_sense = p->invert_carrier_sense; |
| 935 | |
| 936 | control_tx_level_invert(dev, p->invert_level); |
| 937 | o->invert_level = p->invert_level; |
Andy Walls | 1a0b9d8 | 2009-09-27 18:31:37 -0300 | [diff] [blame] | 938 | |
| 939 | o->interrupt_enable = p->interrupt_enable; |
| 940 | o->enable = p->enable; |
| 941 | if (p->enable) { |
Andy Walls | 1a0b9d8 | 2009-09-27 18:31:37 -0300 | [diff] [blame] | 942 | if (p->interrupt_enable) |
| 943 | irqenable_tx(dev, IRQEN_TSE); |
| 944 | control_tx_enable(dev, p->enable); |
| 945 | } |
| 946 | |
| 947 | mutex_unlock(&state->tx_params_lock); |
| 948 | return 0; |
| 949 | } |
| 950 | |
| 951 | |
| 952 | /* |
| 953 | * V4L2 Subdevice Core Ops |
| 954 | */ |
Andy Walls | 29f8a0a | 2009-09-26 23:17:30 -0300 | [diff] [blame] | 955 | static int cx23888_ir_log_status(struct v4l2_subdev *sd) |
| 956 | { |
| 957 | struct cx23888_ir_state *state = to_state(sd); |
| 958 | struct cx23885_dev *dev = state->dev; |
Andy Walls | 1a0b9d8 | 2009-09-27 18:31:37 -0300 | [diff] [blame] | 959 | char *s; |
| 960 | int i, j; |
| 961 | |
| 962 | u32 cntrl = cx23888_ir_read4(dev, CX23888_IR_CNTRL_REG); |
| 963 | u32 txclk = cx23888_ir_read4(dev, CX23888_IR_TXCLK_REG) & TXCLK_TCD; |
| 964 | u32 rxclk = cx23888_ir_read4(dev, CX23888_IR_RXCLK_REG) & RXCLK_RCD; |
| 965 | u32 cduty = cx23888_ir_read4(dev, CX23888_IR_CDUTY_REG) & CDUTY_CDC; |
| 966 | u32 stats = cx23888_ir_read4(dev, CX23888_IR_STATS_REG); |
| 967 | u32 irqen = cx23888_ir_read4(dev, CX23888_IR_IRQEN_REG); |
| 968 | u32 filtr = cx23888_ir_read4(dev, CX23888_IR_FILTR_REG) & FILTR_LPF; |
| 969 | |
| 970 | v4l2_info(sd, "IR Receiver:\n"); |
| 971 | v4l2_info(sd, "\tEnabled: %s\n", |
| 972 | cntrl & CNTRL_RXE ? "yes" : "no"); |
| 973 | v4l2_info(sd, "\tDemodulation from a carrier: %s\n", |
| 974 | cntrl & CNTRL_DMD ? "enabled" : "disabled"); |
| 975 | v4l2_info(sd, "\tFIFO: %s\n", |
| 976 | cntrl & CNTRL_RFE ? "enabled" : "disabled"); |
| 977 | switch (cntrl & CNTRL_EDG) { |
| 978 | case CNTRL_EDG_NONE: |
| 979 | s = "disabled"; |
| 980 | break; |
| 981 | case CNTRL_EDG_FALL: |
| 982 | s = "falling edge"; |
| 983 | break; |
| 984 | case CNTRL_EDG_RISE: |
| 985 | s = "rising edge"; |
| 986 | break; |
| 987 | case CNTRL_EDG_BOTH: |
| 988 | s = "rising & falling edges"; |
| 989 | break; |
| 990 | default: |
| 991 | s = "??? edge"; |
| 992 | break; |
| 993 | } |
| 994 | v4l2_info(sd, "\tPulse timers' start/stop trigger: %s\n", s); |
| 995 | v4l2_info(sd, "\tFIFO data on pulse timer overflow: %s\n", |
| 996 | cntrl & CNTRL_R ? "not loaded" : "overflow marker"); |
| 997 | v4l2_info(sd, "\tFIFO interrupt watermark: %s\n", |
| 998 | cntrl & CNTRL_RIC ? "not empty" : "half full or greater"); |
| 999 | v4l2_info(sd, "\tLoopback mode: %s\n", |
| 1000 | cntrl & CNTRL_LBM ? "loopback active" : "normal receive"); |
| 1001 | if (cntrl & CNTRL_DMD) { |
| 1002 | v4l2_info(sd, "\tExpected carrier (16 clocks): %u Hz\n", |
| 1003 | clock_divider_to_carrier_freq(rxclk)); |
| 1004 | switch (cntrl & CNTRL_WIN) { |
| 1005 | case CNTRL_WIN_3_3: |
| 1006 | i = 3; |
| 1007 | j = 3; |
| 1008 | break; |
| 1009 | case CNTRL_WIN_4_3: |
| 1010 | i = 4; |
| 1011 | j = 3; |
| 1012 | break; |
| 1013 | case CNTRL_WIN_3_4: |
| 1014 | i = 3; |
| 1015 | j = 4; |
| 1016 | break; |
| 1017 | case CNTRL_WIN_4_4: |
| 1018 | i = 4; |
| 1019 | j = 4; |
| 1020 | break; |
| 1021 | default: |
| 1022 | i = 0; |
| 1023 | j = 0; |
| 1024 | break; |
| 1025 | } |
| 1026 | v4l2_info(sd, "\tNext carrier edge window: 16 clocks " |
| 1027 | "-%1d/+%1d, %u to %u Hz\n", i, j, |
| 1028 | clock_divider_to_freq(rxclk, 16 + j), |
| 1029 | clock_divider_to_freq(rxclk, 16 - i)); |
Andy Walls | 1a0b9d8 | 2009-09-27 18:31:37 -0300 | [diff] [blame] | 1030 | } |
Andy Walls | ceb152a | 2010-07-31 21:57:42 -0300 | [diff] [blame] | 1031 | v4l2_info(sd, "\tMax measurable pulse width: %u us, %llu ns\n", |
| 1032 | pulse_width_count_to_us(FIFO_RXTX, rxclk), |
| 1033 | pulse_width_count_to_ns(FIFO_RXTX, rxclk)); |
Andy Walls | 1a0b9d8 | 2009-09-27 18:31:37 -0300 | [diff] [blame] | 1034 | v4l2_info(sd, "\tLow pass filter: %s\n", |
| 1035 | filtr ? "enabled" : "disabled"); |
| 1036 | if (filtr) |
| 1037 | v4l2_info(sd, "\tMin acceptable pulse width (LPF): %u us, " |
| 1038 | "%u ns\n", |
| 1039 | lpf_count_to_us(filtr), |
| 1040 | lpf_count_to_ns(filtr)); |
| 1041 | v4l2_info(sd, "\tPulse width timer timed-out: %s\n", |
| 1042 | stats & STATS_RTO ? "yes" : "no"); |
| 1043 | v4l2_info(sd, "\tPulse width timer time-out intr: %s\n", |
| 1044 | irqen & IRQEN_RTE ? "enabled" : "disabled"); |
| 1045 | v4l2_info(sd, "\tFIFO overrun: %s\n", |
| 1046 | stats & STATS_ROR ? "yes" : "no"); |
| 1047 | v4l2_info(sd, "\tFIFO overrun interrupt: %s\n", |
| 1048 | irqen & IRQEN_ROE ? "enabled" : "disabled"); |
| 1049 | v4l2_info(sd, "\tBusy: %s\n", |
| 1050 | stats & STATS_RBY ? "yes" : "no"); |
| 1051 | v4l2_info(sd, "\tFIFO service requested: %s\n", |
| 1052 | stats & STATS_RSR ? "yes" : "no"); |
| 1053 | v4l2_info(sd, "\tFIFO service request interrupt: %s\n", |
| 1054 | irqen & IRQEN_RSE ? "enabled" : "disabled"); |
| 1055 | |
| 1056 | v4l2_info(sd, "IR Transmitter:\n"); |
| 1057 | v4l2_info(sd, "\tEnabled: %s\n", |
| 1058 | cntrl & CNTRL_TXE ? "yes" : "no"); |
| 1059 | v4l2_info(sd, "\tModulation onto a carrier: %s\n", |
| 1060 | cntrl & CNTRL_MOD ? "enabled" : "disabled"); |
| 1061 | v4l2_info(sd, "\tFIFO: %s\n", |
| 1062 | cntrl & CNTRL_TFE ? "enabled" : "disabled"); |
| 1063 | v4l2_info(sd, "\tFIFO interrupt watermark: %s\n", |
| 1064 | cntrl & CNTRL_TIC ? "not empty" : "half full or less"); |
Andy Walls | 5a28d9a | 2010-07-18 19:57:25 -0300 | [diff] [blame] | 1065 | v4l2_info(sd, "\tOutput pin level inversion %s\n", |
| 1066 | cntrl & CNTRL_IVO ? "yes" : "no"); |
| 1067 | v4l2_info(sd, "\tCarrier polarity: %s\n", |
| 1068 | cntrl & CNTRL_CPL ? "space:burst mark:noburst" |
| 1069 | : "space:noburst mark:burst"); |
Andy Walls | 1a0b9d8 | 2009-09-27 18:31:37 -0300 | [diff] [blame] | 1070 | if (cntrl & CNTRL_MOD) { |
| 1071 | v4l2_info(sd, "\tCarrier (16 clocks): %u Hz\n", |
| 1072 | clock_divider_to_carrier_freq(txclk)); |
| 1073 | v4l2_info(sd, "\tCarrier duty cycle: %2u/16\n", |
| 1074 | cduty + 1); |
Andy Walls | 1a0b9d8 | 2009-09-27 18:31:37 -0300 | [diff] [blame] | 1075 | } |
Andy Walls | ceb152a | 2010-07-31 21:57:42 -0300 | [diff] [blame] | 1076 | v4l2_info(sd, "\tMax pulse width: %u us, %llu ns\n", |
| 1077 | pulse_width_count_to_us(FIFO_RXTX, txclk), |
| 1078 | pulse_width_count_to_ns(FIFO_RXTX, txclk)); |
Andy Walls | 1a0b9d8 | 2009-09-27 18:31:37 -0300 | [diff] [blame] | 1079 | v4l2_info(sd, "\tBusy: %s\n", |
| 1080 | stats & STATS_TBY ? "yes" : "no"); |
| 1081 | v4l2_info(sd, "\tFIFO service requested: %s\n", |
| 1082 | stats & STATS_TSR ? "yes" : "no"); |
| 1083 | v4l2_info(sd, "\tFIFO service request interrupt: %s\n", |
| 1084 | irqen & IRQEN_TSE ? "enabled" : "disabled"); |
| 1085 | |
Andy Walls | 29f8a0a | 2009-09-26 23:17:30 -0300 | [diff] [blame] | 1086 | return 0; |
| 1087 | } |
| 1088 | |
| 1089 | static inline int cx23888_ir_dbg_match(const struct v4l2_dbg_match *match) |
| 1090 | { |
| 1091 | return match->type == V4L2_CHIP_MATCH_HOST && match->addr == 2; |
| 1092 | } |
| 1093 | |
| 1094 | static int cx23888_ir_g_chip_ident(struct v4l2_subdev *sd, |
| 1095 | struct v4l2_dbg_chip_ident *chip) |
| 1096 | { |
| 1097 | struct cx23888_ir_state *state = to_state(sd); |
| 1098 | |
| 1099 | if (cx23888_ir_dbg_match(&chip->match)) { |
| 1100 | chip->ident = state->id; |
| 1101 | chip->revision = state->rev; |
| 1102 | } |
| 1103 | return 0; |
| 1104 | } |
| 1105 | |
| 1106 | #ifdef CONFIG_VIDEO_ADV_DEBUG |
| 1107 | static int cx23888_ir_g_register(struct v4l2_subdev *sd, |
| 1108 | struct v4l2_dbg_register *reg) |
| 1109 | { |
| 1110 | struct cx23888_ir_state *state = to_state(sd); |
| 1111 | u32 addr = CX23888_IR_REG_BASE + (u32) reg->reg; |
| 1112 | |
| 1113 | if (!cx23888_ir_dbg_match(®->match)) |
| 1114 | return -EINVAL; |
| 1115 | if ((addr & 0x3) != 0) |
| 1116 | return -EINVAL; |
| 1117 | if (addr < CX23888_IR_CNTRL_REG || addr > CX23888_IR_LEARN_REG) |
| 1118 | return -EINVAL; |
| 1119 | if (!capable(CAP_SYS_ADMIN)) |
| 1120 | return -EPERM; |
| 1121 | reg->size = 4; |
| 1122 | reg->val = cx23888_ir_read4(state->dev, addr); |
| 1123 | return 0; |
| 1124 | } |
| 1125 | |
| 1126 | static int cx23888_ir_s_register(struct v4l2_subdev *sd, |
| 1127 | struct v4l2_dbg_register *reg) |
| 1128 | { |
| 1129 | struct cx23888_ir_state *state = to_state(sd); |
| 1130 | u32 addr = CX23888_IR_REG_BASE + (u32) reg->reg; |
| 1131 | |
| 1132 | if (!cx23888_ir_dbg_match(®->match)) |
| 1133 | return -EINVAL; |
| 1134 | if ((addr & 0x3) != 0) |
| 1135 | return -EINVAL; |
| 1136 | if (addr < CX23888_IR_CNTRL_REG || addr > CX23888_IR_LEARN_REG) |
| 1137 | return -EINVAL; |
| 1138 | if (!capable(CAP_SYS_ADMIN)) |
| 1139 | return -EPERM; |
| 1140 | cx23888_ir_write4(state->dev, addr, reg->val); |
| 1141 | return 0; |
| 1142 | } |
| 1143 | #endif |
| 1144 | |
| 1145 | static const struct v4l2_subdev_core_ops cx23888_ir_core_ops = { |
| 1146 | .g_chip_ident = cx23888_ir_g_chip_ident, |
| 1147 | .log_status = cx23888_ir_log_status, |
| 1148 | #ifdef CONFIG_VIDEO_ADV_DEBUG |
| 1149 | .g_register = cx23888_ir_g_register, |
| 1150 | .s_register = cx23888_ir_s_register, |
| 1151 | #endif |
Andy Walls | 260e689b | 2010-07-18 20:54:52 -0300 | [diff] [blame] | 1152 | .interrupt_service_routine = cx23888_ir_irq_handler, |
Andy Walls | 29f8a0a | 2009-09-26 23:17:30 -0300 | [diff] [blame] | 1153 | }; |
| 1154 | |
Andy Walls | 1a0b9d8 | 2009-09-27 18:31:37 -0300 | [diff] [blame] | 1155 | static const struct v4l2_subdev_ir_ops cx23888_ir_ir_ops = { |
Andy Walls | 1a0b9d8 | 2009-09-27 18:31:37 -0300 | [diff] [blame] | 1156 | .rx_read = cx23888_ir_rx_read, |
| 1157 | .rx_g_parameters = cx23888_ir_rx_g_parameters, |
| 1158 | .rx_s_parameters = cx23888_ir_rx_s_parameters, |
| 1159 | |
| 1160 | .tx_write = cx23888_ir_tx_write, |
| 1161 | .tx_g_parameters = cx23888_ir_tx_g_parameters, |
| 1162 | .tx_s_parameters = cx23888_ir_tx_s_parameters, |
| 1163 | }; |
| 1164 | |
Andy Walls | 29f8a0a | 2009-09-26 23:17:30 -0300 | [diff] [blame] | 1165 | static const struct v4l2_subdev_ops cx23888_ir_controller_ops = { |
| 1166 | .core = &cx23888_ir_core_ops, |
Andy Walls | 1a0b9d8 | 2009-09-27 18:31:37 -0300 | [diff] [blame] | 1167 | .ir = &cx23888_ir_ir_ops, |
| 1168 | }; |
| 1169 | |
| 1170 | static const struct v4l2_subdev_ir_parameters default_rx_params = { |
Andy Walls | c02e0d1 | 2010-08-01 02:18:13 -0300 | [diff] [blame] | 1171 | .bytes_per_data_element = sizeof(union cx23888_ir_fifo_rec), |
Andy Walls | 1a0b9d8 | 2009-09-27 18:31:37 -0300 | [diff] [blame] | 1172 | .mode = V4L2_SUBDEV_IR_MODE_PULSE_WIDTH, |
| 1173 | |
| 1174 | .enable = false, |
| 1175 | .interrupt_enable = false, |
| 1176 | .shutdown = true, |
| 1177 | |
| 1178 | .modulation = true, |
| 1179 | .carrier_freq = 36000, /* 36 kHz - RC-5, RC-6, and RC-6A carrier */ |
| 1180 | |
| 1181 | /* RC-5: 666,667 ns = 1/36 kHz * 32 cycles * 1 mark * 0.75 */ |
| 1182 | /* RC-6A: 333,333 ns = 1/36 kHz * 16 cycles * 1 mark * 0.75 */ |
| 1183 | .noise_filter_min_width = 333333, /* ns */ |
| 1184 | .carrier_range_lower = 35000, |
| 1185 | .carrier_range_upper = 37000, |
Andy Walls | 5a28d9a | 2010-07-18 19:57:25 -0300 | [diff] [blame] | 1186 | .invert_level = false, |
Andy Walls | 1a0b9d8 | 2009-09-27 18:31:37 -0300 | [diff] [blame] | 1187 | }; |
| 1188 | |
| 1189 | static const struct v4l2_subdev_ir_parameters default_tx_params = { |
Andy Walls | c02e0d1 | 2010-08-01 02:18:13 -0300 | [diff] [blame] | 1190 | .bytes_per_data_element = sizeof(union cx23888_ir_fifo_rec), |
Andy Walls | 1a0b9d8 | 2009-09-27 18:31:37 -0300 | [diff] [blame] | 1191 | .mode = V4L2_SUBDEV_IR_MODE_PULSE_WIDTH, |
| 1192 | |
| 1193 | .enable = false, |
| 1194 | .interrupt_enable = false, |
| 1195 | .shutdown = true, |
| 1196 | |
| 1197 | .modulation = true, |
| 1198 | .carrier_freq = 36000, /* 36 kHz - RC-5 carrier */ |
| 1199 | .duty_cycle = 25, /* 25 % - RC-5 carrier */ |
Andy Walls | 5a28d9a | 2010-07-18 19:57:25 -0300 | [diff] [blame] | 1200 | .invert_level = false, |
| 1201 | .invert_carrier_sense = false, |
Andy Walls | 29f8a0a | 2009-09-26 23:17:30 -0300 | [diff] [blame] | 1202 | }; |
| 1203 | |
| 1204 | int cx23888_ir_probe(struct cx23885_dev *dev) |
| 1205 | { |
| 1206 | struct cx23888_ir_state *state; |
| 1207 | struct v4l2_subdev *sd; |
Andy Walls | 1a0b9d8 | 2009-09-27 18:31:37 -0300 | [diff] [blame] | 1208 | struct v4l2_subdev_ir_parameters default_params; |
| 1209 | int ret; |
Andy Walls | 29f8a0a | 2009-09-26 23:17:30 -0300 | [diff] [blame] | 1210 | |
| 1211 | state = kzalloc(sizeof(struct cx23888_ir_state), GFP_KERNEL); |
| 1212 | if (state == NULL) |
| 1213 | return -ENOMEM; |
| 1214 | |
Andy Walls | 1a0b9d8 | 2009-09-27 18:31:37 -0300 | [diff] [blame] | 1215 | spin_lock_init(&state->rx_kfifo_lock); |
Stefani Seibold | 7801edb | 2009-12-21 14:37:33 -0800 | [diff] [blame] | 1216 | if (kfifo_alloc(&state->rx_kfifo, CX23888_IR_RX_KFIFO_SIZE, GFP_KERNEL)) |
Andy Walls | 1a0b9d8 | 2009-09-27 18:31:37 -0300 | [diff] [blame] | 1217 | return -ENOMEM; |
| 1218 | |
Andy Walls | 29f8a0a | 2009-09-26 23:17:30 -0300 | [diff] [blame] | 1219 | state->dev = dev; |
| 1220 | state->id = V4L2_IDENT_CX23888_IR; |
| 1221 | state->rev = 0; |
| 1222 | sd = &state->sd; |
| 1223 | |
| 1224 | v4l2_subdev_init(sd, &cx23888_ir_controller_ops); |
| 1225 | v4l2_set_subdevdata(sd, state); |
| 1226 | /* FIXME - fix the formatting of dev->v4l2_dev.name and use it */ |
| 1227 | snprintf(sd->name, sizeof(sd->name), "%s/888-ir", dev->name); |
| 1228 | sd->grp_id = CX23885_HW_888_IR; |
Andy Walls | 1a0b9d8 | 2009-09-27 18:31:37 -0300 | [diff] [blame] | 1229 | |
| 1230 | ret = v4l2_device_register_subdev(&dev->v4l2_dev, sd); |
| 1231 | if (ret == 0) { |
| 1232 | /* |
| 1233 | * Ensure no interrupts arrive from '888 specific conditions, |
| 1234 | * since we ignore them in this driver to have commonality with |
| 1235 | * similar IR controller cores. |
| 1236 | */ |
| 1237 | cx23888_ir_write4(dev, CX23888_IR_IRQEN_REG, 0); |
| 1238 | |
| 1239 | mutex_init(&state->rx_params_lock); |
| 1240 | memcpy(&default_params, &default_rx_params, |
| 1241 | sizeof(struct v4l2_subdev_ir_parameters)); |
| 1242 | v4l2_subdev_call(sd, ir, rx_s_parameters, &default_params); |
| 1243 | |
| 1244 | mutex_init(&state->tx_params_lock); |
| 1245 | memcpy(&default_params, &default_tx_params, |
| 1246 | sizeof(struct v4l2_subdev_ir_parameters)); |
| 1247 | v4l2_subdev_call(sd, ir, tx_s_parameters, &default_params); |
| 1248 | } else { |
Stefani Seibold | 7801edb | 2009-12-21 14:37:33 -0800 | [diff] [blame] | 1249 | kfifo_free(&state->rx_kfifo); |
Andy Walls | 1a0b9d8 | 2009-09-27 18:31:37 -0300 | [diff] [blame] | 1250 | } |
| 1251 | return ret; |
Andy Walls | 29f8a0a | 2009-09-26 23:17:30 -0300 | [diff] [blame] | 1252 | } |
| 1253 | |
| 1254 | int cx23888_ir_remove(struct cx23885_dev *dev) |
| 1255 | { |
| 1256 | struct v4l2_subdev *sd; |
| 1257 | struct cx23888_ir_state *state; |
| 1258 | |
| 1259 | sd = cx23885_find_hw(dev, CX23885_HW_888_IR); |
| 1260 | if (sd == NULL) |
| 1261 | return -ENODEV; |
| 1262 | |
Andy Walls | 1a0b9d8 | 2009-09-27 18:31:37 -0300 | [diff] [blame] | 1263 | cx23888_ir_rx_shutdown(sd); |
| 1264 | cx23888_ir_tx_shutdown(sd); |
Andy Walls | 29f8a0a | 2009-09-26 23:17:30 -0300 | [diff] [blame] | 1265 | |
| 1266 | state = to_state(sd); |
| 1267 | v4l2_device_unregister_subdev(sd); |
Stefani Seibold | 7801edb | 2009-12-21 14:37:33 -0800 | [diff] [blame] | 1268 | kfifo_free(&state->rx_kfifo); |
Andy Walls | 29f8a0a | 2009-09-26 23:17:30 -0300 | [diff] [blame] | 1269 | kfree(state); |
| 1270 | /* Nothing more to free() as state held the actual v4l2_subdev object */ |
| 1271 | return 0; |
| 1272 | } |