Pawel Moll | 90556ca | 2012-11-21 11:44:28 +0000 | [diff] [blame] | 1 | /* |
| 2 | * ARM Ltd. |
| 3 | * |
| 4 | * ARMv8 Foundation model DTS |
| 5 | */ |
| 6 | |
| 7 | /dts-v1/; |
| 8 | |
Catalin Marinas | df503ba | 2013-11-14 15:15:37 +0000 | [diff] [blame] | 9 | /memreserve/ 0x80000000 0x00010000; |
| 10 | |
Pawel Moll | 90556ca | 2012-11-21 11:44:28 +0000 | [diff] [blame] | 11 | / { |
| 12 | model = "Foundation-v8A"; |
| 13 | compatible = "arm,foundation-aarch64", "arm,vexpress"; |
| 14 | interrupt-parent = <&gic>; |
| 15 | #address-cells = <2>; |
| 16 | #size-cells = <2>; |
| 17 | |
| 18 | chosen { }; |
| 19 | |
| 20 | aliases { |
| 21 | serial0 = &v2m_serial0; |
| 22 | serial1 = &v2m_serial1; |
| 23 | serial2 = &v2m_serial2; |
| 24 | serial3 = &v2m_serial3; |
| 25 | }; |
| 26 | |
| 27 | cpus { |
Mark Rutland | ed1f236 | 2013-05-07 14:04:03 +0100 | [diff] [blame] | 28 | #address-cells = <2>; |
Pawel Moll | 90556ca | 2012-11-21 11:44:28 +0000 | [diff] [blame] | 29 | #size-cells = <0>; |
| 30 | |
| 31 | cpu@0 { |
| 32 | device_type = "cpu"; |
| 33 | compatible = "arm,armv8"; |
| 34 | reg = <0x0 0x0>; |
| 35 | enable-method = "spin-table"; |
| 36 | cpu-release-addr = <0x0 0x8000fff8>; |
| 37 | }; |
| 38 | cpu@1 { |
| 39 | device_type = "cpu"; |
| 40 | compatible = "arm,armv8"; |
| 41 | reg = <0x0 0x1>; |
| 42 | enable-method = "spin-table"; |
| 43 | cpu-release-addr = <0x0 0x8000fff8>; |
| 44 | }; |
| 45 | cpu@2 { |
| 46 | device_type = "cpu"; |
| 47 | compatible = "arm,armv8"; |
| 48 | reg = <0x0 0x2>; |
| 49 | enable-method = "spin-table"; |
| 50 | cpu-release-addr = <0x0 0x8000fff8>; |
| 51 | }; |
| 52 | cpu@3 { |
| 53 | device_type = "cpu"; |
| 54 | compatible = "arm,armv8"; |
| 55 | reg = <0x0 0x3>; |
| 56 | enable-method = "spin-table"; |
| 57 | cpu-release-addr = <0x0 0x8000fff8>; |
| 58 | }; |
| 59 | }; |
| 60 | |
| 61 | memory@80000000 { |
| 62 | device_type = "memory"; |
| 63 | reg = <0x00000000 0x80000000 0 0x80000000>, |
| 64 | <0x00000008 0x80000000 0 0x80000000>; |
| 65 | }; |
| 66 | |
| 67 | gic: interrupt-controller@2c001000 { |
| 68 | compatible = "arm,cortex-a15-gic", "arm,cortex-a9-gic"; |
| 69 | #interrupt-cells = <3>; |
| 70 | #address-cells = <0>; |
| 71 | interrupt-controller; |
| 72 | reg = <0x0 0x2c001000 0 0x1000>, |
| 73 | <0x0 0x2c002000 0 0x1000>, |
| 74 | <0x0 0x2c004000 0 0x2000>, |
| 75 | <0x0 0x2c006000 0 0x2000>; |
| 76 | interrupts = <1 9 0xf04>; |
| 77 | }; |
| 78 | |
| 79 | timer { |
| 80 | compatible = "arm,armv8-timer"; |
| 81 | interrupts = <1 13 0xff01>, |
| 82 | <1 14 0xff01>, |
| 83 | <1 11 0xff01>, |
| 84 | <1 10 0xff01>; |
| 85 | clock-frequency = <100000000>; |
| 86 | }; |
| 87 | |
| 88 | pmu { |
| 89 | compatible = "arm,armv8-pmuv3"; |
| 90 | interrupts = <0 60 4>, |
| 91 | <0 61 4>, |
| 92 | <0 62 4>, |
| 93 | <0 63 4>; |
| 94 | }; |
| 95 | |
| 96 | smb { |
| 97 | compatible = "arm,vexpress,v2m-p1", "simple-bus"; |
| 98 | arm,v2m-memory-map = "rs1"; |
| 99 | #address-cells = <2>; /* SMB chipselect number and offset */ |
| 100 | #size-cells = <1>; |
| 101 | |
| 102 | ranges = <0 0 0 0x08000000 0x04000000>, |
| 103 | <1 0 0 0x14000000 0x04000000>, |
| 104 | <2 0 0 0x18000000 0x04000000>, |
| 105 | <3 0 0 0x1c000000 0x04000000>, |
| 106 | <4 0 0 0x0c000000 0x04000000>, |
| 107 | <5 0 0 0x10000000 0x04000000>; |
| 108 | |
| 109 | #interrupt-cells = <1>; |
| 110 | interrupt-map-mask = <0 0 63>; |
| 111 | interrupt-map = <0 0 0 &gic 0 0 4>, |
| 112 | <0 0 1 &gic 0 1 4>, |
| 113 | <0 0 2 &gic 0 2 4>, |
| 114 | <0 0 3 &gic 0 3 4>, |
| 115 | <0 0 4 &gic 0 4 4>, |
| 116 | <0 0 5 &gic 0 5 4>, |
| 117 | <0 0 6 &gic 0 6 4>, |
| 118 | <0 0 7 &gic 0 7 4>, |
| 119 | <0 0 8 &gic 0 8 4>, |
| 120 | <0 0 9 &gic 0 9 4>, |
| 121 | <0 0 10 &gic 0 10 4>, |
| 122 | <0 0 11 &gic 0 11 4>, |
| 123 | <0 0 12 &gic 0 12 4>, |
| 124 | <0 0 13 &gic 0 13 4>, |
| 125 | <0 0 14 &gic 0 14 4>, |
| 126 | <0 0 15 &gic 0 15 4>, |
| 127 | <0 0 16 &gic 0 16 4>, |
| 128 | <0 0 17 &gic 0 17 4>, |
| 129 | <0 0 18 &gic 0 18 4>, |
| 130 | <0 0 19 &gic 0 19 4>, |
| 131 | <0 0 20 &gic 0 20 4>, |
| 132 | <0 0 21 &gic 0 21 4>, |
| 133 | <0 0 22 &gic 0 22 4>, |
| 134 | <0 0 23 &gic 0 23 4>, |
| 135 | <0 0 24 &gic 0 24 4>, |
| 136 | <0 0 25 &gic 0 25 4>, |
| 137 | <0 0 26 &gic 0 26 4>, |
| 138 | <0 0 27 &gic 0 27 4>, |
| 139 | <0 0 28 &gic 0 28 4>, |
| 140 | <0 0 29 &gic 0 29 4>, |
| 141 | <0 0 30 &gic 0 30 4>, |
| 142 | <0 0 31 &gic 0 31 4>, |
| 143 | <0 0 32 &gic 0 32 4>, |
| 144 | <0 0 33 &gic 0 33 4>, |
| 145 | <0 0 34 &gic 0 34 4>, |
| 146 | <0 0 35 &gic 0 35 4>, |
| 147 | <0 0 36 &gic 0 36 4>, |
| 148 | <0 0 37 &gic 0 37 4>, |
| 149 | <0 0 38 &gic 0 38 4>, |
| 150 | <0 0 39 &gic 0 39 4>, |
| 151 | <0 0 40 &gic 0 40 4>, |
| 152 | <0 0 41 &gic 0 41 4>, |
| 153 | <0 0 42 &gic 0 42 4>; |
| 154 | |
| 155 | ethernet@2,02000000 { |
| 156 | compatible = "smsc,lan91c111"; |
| 157 | reg = <2 0x02000000 0x10000>; |
| 158 | interrupts = <15>; |
| 159 | }; |
| 160 | |
| 161 | v2m_clk24mhz: clk24mhz { |
| 162 | compatible = "fixed-clock"; |
| 163 | #clock-cells = <0>; |
| 164 | clock-frequency = <24000000>; |
| 165 | clock-output-names = "v2m:clk24mhz"; |
| 166 | }; |
| 167 | |
| 168 | v2m_refclk1mhz: refclk1mhz { |
| 169 | compatible = "fixed-clock"; |
| 170 | #clock-cells = <0>; |
| 171 | clock-frequency = <1000000>; |
| 172 | clock-output-names = "v2m:refclk1mhz"; |
| 173 | }; |
| 174 | |
| 175 | v2m_refclk32khz: refclk32khz { |
| 176 | compatible = "fixed-clock"; |
| 177 | #clock-cells = <0>; |
| 178 | clock-frequency = <32768>; |
| 179 | clock-output-names = "v2m:refclk32khz"; |
| 180 | }; |
| 181 | |
| 182 | iofpga@3,00000000 { |
| 183 | compatible = "arm,amba-bus", "simple-bus"; |
| 184 | #address-cells = <1>; |
| 185 | #size-cells = <1>; |
| 186 | ranges = <0 3 0 0x200000>; |
| 187 | |
| 188 | v2m_sysreg: sysreg@010000 { |
| 189 | compatible = "arm,vexpress-sysreg"; |
| 190 | reg = <0x010000 0x1000>; |
| 191 | }; |
| 192 | |
| 193 | v2m_serial0: uart@090000 { |
| 194 | compatible = "arm,pl011", "arm,primecell"; |
| 195 | reg = <0x090000 0x1000>; |
| 196 | interrupts = <5>; |
| 197 | clocks = <&v2m_clk24mhz>, <&v2m_clk24mhz>; |
| 198 | clock-names = "uartclk", "apb_pclk"; |
| 199 | }; |
| 200 | |
| 201 | v2m_serial1: uart@0a0000 { |
| 202 | compatible = "arm,pl011", "arm,primecell"; |
| 203 | reg = <0x0a0000 0x1000>; |
| 204 | interrupts = <6>; |
| 205 | clocks = <&v2m_clk24mhz>, <&v2m_clk24mhz>; |
| 206 | clock-names = "uartclk", "apb_pclk"; |
| 207 | }; |
| 208 | |
| 209 | v2m_serial2: uart@0b0000 { |
| 210 | compatible = "arm,pl011", "arm,primecell"; |
| 211 | reg = <0x0b0000 0x1000>; |
| 212 | interrupts = <7>; |
| 213 | clocks = <&v2m_clk24mhz>, <&v2m_clk24mhz>; |
| 214 | clock-names = "uartclk", "apb_pclk"; |
| 215 | }; |
| 216 | |
| 217 | v2m_serial3: uart@0c0000 { |
| 218 | compatible = "arm,pl011", "arm,primecell"; |
| 219 | reg = <0x0c0000 0x1000>; |
| 220 | interrupts = <8>; |
| 221 | clocks = <&v2m_clk24mhz>, <&v2m_clk24mhz>; |
| 222 | clock-names = "uartclk", "apb_pclk"; |
| 223 | }; |
| 224 | |
| 225 | virtio_block@0130000 { |
| 226 | compatible = "virtio,mmio"; |
| 227 | reg = <0x130000 0x1000>; |
| 228 | interrupts = <42>; |
| 229 | }; |
| 230 | }; |
| 231 | }; |
| 232 | }; |