Alan Ott | 3731a33 | 2012-09-02 15:44:13 +0000 | [diff] [blame] | 1 | /* |
| 2 | * Driver for Microchip MRF24J40 802.15.4 Wireless-PAN Networking controller |
| 3 | * |
| 4 | * Copyright (C) 2012 Alan Ott <alan@signal11.us> |
| 5 | * Signal 11 Software |
| 6 | * |
| 7 | * This program is free software; you can redistribute it and/or modify |
| 8 | * it under the terms of the GNU General Public License as published by |
| 9 | * the Free Software Foundation; either version 2 of the License, or |
| 10 | * (at your option) any later version. |
| 11 | * |
| 12 | * This program is distributed in the hope that it will be useful, |
| 13 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 14 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 15 | * GNU General Public License for more details. |
Alan Ott | 3731a33 | 2012-09-02 15:44:13 +0000 | [diff] [blame] | 16 | */ |
| 17 | |
| 18 | #include <linux/spi/spi.h> |
| 19 | #include <linux/interrupt.h> |
| 20 | #include <linux/module.h> |
Alexander Aring | b015679 | 2015-09-21 11:24:30 +0200 | [diff] [blame^] | 21 | #include <linux/regmap.h> |
Alexander Aring | 4ca24ac | 2014-10-25 09:41:04 +0200 | [diff] [blame] | 22 | #include <linux/ieee802154.h> |
Alexander Aring | 5ad60d3 | 2014-10-25 09:41:02 +0200 | [diff] [blame] | 23 | #include <net/cfg802154.h> |
Alan Ott | 3731a33 | 2012-09-02 15:44:13 +0000 | [diff] [blame] | 24 | #include <net/mac802154.h> |
| 25 | |
| 26 | /* MRF24J40 Short Address Registers */ |
Alexander Aring | c9f883f | 2015-09-21 11:24:22 +0200 | [diff] [blame] | 27 | #define REG_RXMCR 0x00 /* Receive MAC control */ |
| 28 | #define REG_PANIDL 0x01 /* PAN ID (low) */ |
| 29 | #define REG_PANIDH 0x02 /* PAN ID (high) */ |
| 30 | #define REG_SADRL 0x03 /* Short address (low) */ |
| 31 | #define REG_SADRH 0x04 /* Short address (high) */ |
| 32 | #define REG_EADR0 0x05 /* Long address (low) (high is EADR7) */ |
Alexander Aring | 554b494 | 2015-09-21 11:24:29 +0200 | [diff] [blame] | 33 | #define REG_EADR1 0x06 |
| 34 | #define REG_EADR2 0x07 |
| 35 | #define REG_EADR3 0x08 |
| 36 | #define REG_EADR4 0x09 |
| 37 | #define REG_EADR5 0x0A |
| 38 | #define REG_EADR6 0x0B |
| 39 | #define REG_EADR7 0x0C |
| 40 | #define REG_RXFLUSH 0x0D |
| 41 | #define REG_ORDER 0x10 |
Alexander Aring | c9f883f | 2015-09-21 11:24:22 +0200 | [diff] [blame] | 42 | #define REG_TXMCR 0x11 /* Transmit MAC control */ |
Alexander Aring | 554b494 | 2015-09-21 11:24:29 +0200 | [diff] [blame] | 43 | #define REG_ACKTMOUT 0x12 |
| 44 | #define REG_ESLOTG1 0x13 |
| 45 | #define REG_SYMTICKL 0x14 |
| 46 | #define REG_SYMTICKH 0x15 |
Alexander Aring | c9f883f | 2015-09-21 11:24:22 +0200 | [diff] [blame] | 47 | #define REG_PACON0 0x16 /* Power Amplifier Control */ |
| 48 | #define REG_PACON1 0x17 /* Power Amplifier Control */ |
| 49 | #define REG_PACON2 0x18 /* Power Amplifier Control */ |
Alexander Aring | 554b494 | 2015-09-21 11:24:29 +0200 | [diff] [blame] | 50 | #define REG_TXBCON0 0x1A |
Alexander Aring | c9f883f | 2015-09-21 11:24:22 +0200 | [diff] [blame] | 51 | #define REG_TXNCON 0x1B /* Transmit Normal FIFO Control */ |
Alexander Aring | 554b494 | 2015-09-21 11:24:29 +0200 | [diff] [blame] | 52 | #define REG_TXG1CON 0x1C |
| 53 | #define REG_TXG2CON 0x1D |
| 54 | #define REG_ESLOTG23 0x1E |
| 55 | #define REG_ESLOTG45 0x1F |
| 56 | #define REG_ESLOTG67 0x20 |
| 57 | #define REG_TXPEND 0x21 |
| 58 | #define REG_WAKECON 0x22 |
| 59 | #define REG_FROMOFFSET 0x23 |
Alexander Aring | c9f883f | 2015-09-21 11:24:22 +0200 | [diff] [blame] | 60 | #define REG_TXSTAT 0x24 /* TX MAC Status Register */ |
Alexander Aring | 554b494 | 2015-09-21 11:24:29 +0200 | [diff] [blame] | 61 | #define REG_TXBCON1 0x25 |
| 62 | #define REG_GATECLK 0x26 |
| 63 | #define REG_TXTIME 0x27 |
| 64 | #define REG_HSYMTMRL 0x28 |
| 65 | #define REG_HSYMTMRH 0x29 |
Alexander Aring | c9f883f | 2015-09-21 11:24:22 +0200 | [diff] [blame] | 66 | #define REG_SOFTRST 0x2A /* Soft Reset */ |
Alexander Aring | 554b494 | 2015-09-21 11:24:29 +0200 | [diff] [blame] | 67 | #define REG_SECCON0 0x2C |
| 68 | #define REG_SECCON1 0x2D |
Alexander Aring | c9f883f | 2015-09-21 11:24:22 +0200 | [diff] [blame] | 69 | #define REG_TXSTBL 0x2E /* TX Stabilization */ |
Alexander Aring | 554b494 | 2015-09-21 11:24:29 +0200 | [diff] [blame] | 70 | #define REG_RXSR 0x30 |
Alexander Aring | c9f883f | 2015-09-21 11:24:22 +0200 | [diff] [blame] | 71 | #define REG_INTSTAT 0x31 /* Interrupt Status */ |
| 72 | #define REG_INTCON 0x32 /* Interrupt Control */ |
| 73 | #define REG_GPIO 0x33 /* GPIO */ |
| 74 | #define REG_TRISGPIO 0x34 /* GPIO direction */ |
Alexander Aring | 554b494 | 2015-09-21 11:24:29 +0200 | [diff] [blame] | 75 | #define REG_SLPACK 0x35 |
Alexander Aring | c9f883f | 2015-09-21 11:24:22 +0200 | [diff] [blame] | 76 | #define REG_RFCTL 0x36 /* RF Control Mode Register */ |
Alexander Aring | 554b494 | 2015-09-21 11:24:29 +0200 | [diff] [blame] | 77 | #define REG_SECCR2 0x37 |
| 78 | #define REG_BBREG0 0x38 |
Alexander Aring | c9f883f | 2015-09-21 11:24:22 +0200 | [diff] [blame] | 79 | #define REG_BBREG1 0x39 /* Baseband Registers */ |
| 80 | #define REG_BBREG2 0x3A /* */ |
Alexander Aring | 554b494 | 2015-09-21 11:24:29 +0200 | [diff] [blame] | 81 | #define REG_BBREG3 0x3B |
| 82 | #define REG_BBREG4 0x3C |
Alexander Aring | c9f883f | 2015-09-21 11:24:22 +0200 | [diff] [blame] | 83 | #define REG_BBREG6 0x3E /* */ |
| 84 | #define REG_CCAEDTH 0x3F /* Energy Detection Threshold */ |
Alan Ott | 3731a33 | 2012-09-02 15:44:13 +0000 | [diff] [blame] | 85 | |
| 86 | /* MRF24J40 Long Address Registers */ |
Alexander Aring | c9f883f | 2015-09-21 11:24:22 +0200 | [diff] [blame] | 87 | #define REG_RFCON0 0x200 /* RF Control Registers */ |
| 88 | #define REG_RFCON1 0x201 |
| 89 | #define REG_RFCON2 0x202 |
| 90 | #define REG_RFCON3 0x203 |
| 91 | #define REG_RFCON5 0x205 |
| 92 | #define REG_RFCON6 0x206 |
| 93 | #define REG_RFCON7 0x207 |
| 94 | #define REG_RFCON8 0x208 |
Alexander Aring | 554b494 | 2015-09-21 11:24:29 +0200 | [diff] [blame] | 95 | #define REG_SLPCAL0 0x209 |
| 96 | #define REG_SLPCAL1 0x20A |
| 97 | #define REG_SLPCAL2 0x20B |
| 98 | #define REG_RFSTATE 0x20F |
Alexander Aring | c9f883f | 2015-09-21 11:24:22 +0200 | [diff] [blame] | 99 | #define REG_RSSI 0x210 |
| 100 | #define REG_SLPCON0 0x211 /* Sleep Clock Control Registers */ |
| 101 | #define REG_SLPCON1 0x220 |
| 102 | #define REG_WAKETIMEL 0x222 /* Wake-up Time Match Value Low */ |
| 103 | #define REG_WAKETIMEH 0x223 /* Wake-up Time Match Value High */ |
Alexander Aring | 554b494 | 2015-09-21 11:24:29 +0200 | [diff] [blame] | 104 | #define REG_REMCNTL 0x224 |
| 105 | #define REG_REMCNTH 0x225 |
| 106 | #define REG_MAINCNT0 0x226 |
| 107 | #define REG_MAINCNT1 0x227 |
| 108 | #define REG_MAINCNT2 0x228 |
| 109 | #define REG_MAINCNT3 0x229 |
Alexander Aring | c9f883f | 2015-09-21 11:24:22 +0200 | [diff] [blame] | 110 | #define REG_TESTMODE 0x22F /* Test mode */ |
Alexander Aring | 554b494 | 2015-09-21 11:24:29 +0200 | [diff] [blame] | 111 | #define REG_ASSOEAR0 0x230 |
| 112 | #define REG_ASSOEAR1 0x231 |
| 113 | #define REG_ASSOEAR2 0x232 |
| 114 | #define REG_ASSOEAR3 0x233 |
| 115 | #define REG_ASSOEAR4 0x234 |
| 116 | #define REG_ASSOEAR5 0x235 |
| 117 | #define REG_ASSOEAR6 0x236 |
| 118 | #define REG_ASSOEAR7 0x237 |
| 119 | #define REG_ASSOSAR0 0x238 |
| 120 | #define REG_ASSOSAR1 0x239 |
| 121 | #define REG_UNONCE0 0x240 |
| 122 | #define REG_UNONCE1 0x241 |
| 123 | #define REG_UNONCE2 0x242 |
| 124 | #define REG_UNONCE3 0x243 |
| 125 | #define REG_UNONCE4 0x244 |
| 126 | #define REG_UNONCE5 0x245 |
| 127 | #define REG_UNONCE6 0x246 |
| 128 | #define REG_UNONCE7 0x247 |
| 129 | #define REG_UNONCE8 0x248 |
| 130 | #define REG_UNONCE9 0x249 |
| 131 | #define REG_UNONCE10 0x24A |
| 132 | #define REG_UNONCE11 0x24B |
| 133 | #define REG_UNONCE12 0x24C |
Alexander Aring | c9f883f | 2015-09-21 11:24:22 +0200 | [diff] [blame] | 134 | #define REG_RX_FIFO 0x300 /* Receive FIFO */ |
Alan Ott | 3731a33 | 2012-09-02 15:44:13 +0000 | [diff] [blame] | 135 | |
| 136 | /* Device configuration: Only channels 11-26 on page 0 are supported. */ |
| 137 | #define MRF24J40_CHAN_MIN 11 |
| 138 | #define MRF24J40_CHAN_MAX 26 |
| 139 | #define CHANNEL_MASK (((u32)1 << (MRF24J40_CHAN_MAX + 1)) \ |
| 140 | - ((u32)1 << MRF24J40_CHAN_MIN)) |
| 141 | |
| 142 | #define TX_FIFO_SIZE 128 /* From datasheet */ |
| 143 | #define RX_FIFO_SIZE 144 /* From datasheet */ |
| 144 | #define SET_CHANNEL_DELAY_US 192 /* From datasheet */ |
| 145 | |
Simon Vincent | db9e0ee | 2014-10-06 10:39:45 +0100 | [diff] [blame] | 146 | enum mrf24j40_modules { MRF24J40, MRF24J40MA, MRF24J40MC }; |
| 147 | |
Alan Ott | 3731a33 | 2012-09-02 15:44:13 +0000 | [diff] [blame] | 148 | /* Device Private Data */ |
| 149 | struct mrf24j40 { |
| 150 | struct spi_device *spi; |
Alexander Aring | 5a50439 | 2014-10-25 17:16:34 +0200 | [diff] [blame] | 151 | struct ieee802154_hw *hw; |
Alan Ott | 3731a33 | 2012-09-02 15:44:13 +0000 | [diff] [blame] | 152 | |
Alexander Aring | b015679 | 2015-09-21 11:24:30 +0200 | [diff] [blame^] | 153 | struct regmap *regmap_short; |
| 154 | struct regmap *regmap_long; |
Alan Ott | 3731a33 | 2012-09-02 15:44:13 +0000 | [diff] [blame] | 155 | struct mutex buffer_mutex; /* only used to protect buf */ |
| 156 | struct completion tx_complete; |
Alan Ott | 3731a33 | 2012-09-02 15:44:13 +0000 | [diff] [blame] | 157 | u8 *buf; /* 3 bytes. Used for SPI single-register transfers. */ |
| 158 | }; |
| 159 | |
Alexander Aring | b015679 | 2015-09-21 11:24:30 +0200 | [diff] [blame^] | 160 | /* regmap information for short address register access */ |
| 161 | #define MRF24J40_SHORT_WRITE 0x01 |
| 162 | #define MRF24J40_SHORT_READ 0x00 |
| 163 | #define MRF24J40_SHORT_NUMREGS 0x3F |
| 164 | |
| 165 | /* regmap information for long address register access */ |
| 166 | #define MRF24J40_LONG_ACCESS 0x80 |
| 167 | #define MRF24J40_LONG_NUMREGS 0x38F |
| 168 | |
Alan Ott | 3731a33 | 2012-09-02 15:44:13 +0000 | [diff] [blame] | 169 | /* Read/Write SPI Commands for Short and Long Address registers. */ |
| 170 | #define MRF24J40_READSHORT(reg) ((reg) << 1) |
| 171 | #define MRF24J40_WRITESHORT(reg) ((reg) << 1 | 1) |
| 172 | #define MRF24J40_READLONG(reg) (1 << 15 | (reg) << 5) |
| 173 | #define MRF24J40_WRITELONG(reg) (1 << 15 | (reg) << 5 | 1 << 4) |
| 174 | |
Alan Ott | cf82dab | 2013-03-18 12:06:42 +0000 | [diff] [blame] | 175 | /* The datasheet indicates the theoretical maximum for SCK to be 10MHz */ |
| 176 | #define MAX_SPI_SPEED_HZ 10000000 |
Alan Ott | 3731a33 | 2012-09-02 15:44:13 +0000 | [diff] [blame] | 177 | |
| 178 | #define printdev(X) (&X->spi->dev) |
| 179 | |
Alexander Aring | b015679 | 2015-09-21 11:24:30 +0200 | [diff] [blame^] | 180 | static bool |
| 181 | mrf24j40_short_reg_writeable(struct device *dev, unsigned int reg) |
| 182 | { |
| 183 | switch (reg) { |
| 184 | case REG_RXMCR: |
| 185 | case REG_PANIDL: |
| 186 | case REG_PANIDH: |
| 187 | case REG_SADRL: |
| 188 | case REG_SADRH: |
| 189 | case REG_EADR0: |
| 190 | case REG_EADR1: |
| 191 | case REG_EADR2: |
| 192 | case REG_EADR3: |
| 193 | case REG_EADR4: |
| 194 | case REG_EADR5: |
| 195 | case REG_EADR6: |
| 196 | case REG_EADR7: |
| 197 | case REG_RXFLUSH: |
| 198 | case REG_ORDER: |
| 199 | case REG_TXMCR: |
| 200 | case REG_ACKTMOUT: |
| 201 | case REG_ESLOTG1: |
| 202 | case REG_SYMTICKL: |
| 203 | case REG_SYMTICKH: |
| 204 | case REG_PACON0: |
| 205 | case REG_PACON1: |
| 206 | case REG_PACON2: |
| 207 | case REG_TXBCON0: |
| 208 | case REG_TXNCON: |
| 209 | case REG_TXG1CON: |
| 210 | case REG_TXG2CON: |
| 211 | case REG_ESLOTG23: |
| 212 | case REG_ESLOTG45: |
| 213 | case REG_ESLOTG67: |
| 214 | case REG_TXPEND: |
| 215 | case REG_WAKECON: |
| 216 | case REG_FROMOFFSET: |
| 217 | case REG_TXBCON1: |
| 218 | case REG_GATECLK: |
| 219 | case REG_TXTIME: |
| 220 | case REG_HSYMTMRL: |
| 221 | case REG_HSYMTMRH: |
| 222 | case REG_SOFTRST: |
| 223 | case REG_SECCON0: |
| 224 | case REG_SECCON1: |
| 225 | case REG_TXSTBL: |
| 226 | case REG_RXSR: |
| 227 | case REG_INTCON: |
| 228 | case REG_TRISGPIO: |
| 229 | case REG_GPIO: |
| 230 | case REG_RFCTL: |
| 231 | case REG_SLPACK: |
| 232 | case REG_BBREG0: |
| 233 | case REG_BBREG1: |
| 234 | case REG_BBREG2: |
| 235 | case REG_BBREG3: |
| 236 | case REG_BBREG4: |
| 237 | case REG_BBREG6: |
| 238 | case REG_CCAEDTH: |
| 239 | return true; |
| 240 | default: |
| 241 | return false; |
| 242 | } |
| 243 | } |
| 244 | |
| 245 | static bool |
| 246 | mrf24j40_short_reg_readable(struct device *dev, unsigned int reg) |
| 247 | { |
| 248 | bool rc; |
| 249 | |
| 250 | /* all writeable are also readable */ |
| 251 | rc = mrf24j40_short_reg_writeable(dev, reg); |
| 252 | if (rc) |
| 253 | return rc; |
| 254 | |
| 255 | /* readonly regs */ |
| 256 | switch (reg) { |
| 257 | case REG_TXSTAT: |
| 258 | case REG_INTSTAT: |
| 259 | return true; |
| 260 | default: |
| 261 | return false; |
| 262 | } |
| 263 | } |
| 264 | |
| 265 | static bool |
| 266 | mrf24j40_short_reg_volatile(struct device *dev, unsigned int reg) |
| 267 | { |
| 268 | /* can be changed during runtime */ |
| 269 | switch (reg) { |
| 270 | case REG_TXSTAT: |
| 271 | case REG_INTSTAT: |
| 272 | case REG_RXFLUSH: |
| 273 | case REG_TXNCON: |
| 274 | case REG_SOFTRST: |
| 275 | case REG_RFCTL: |
| 276 | case REG_TXBCON0: |
| 277 | case REG_TXG1CON: |
| 278 | case REG_TXG2CON: |
| 279 | case REG_TXBCON1: |
| 280 | case REG_SECCON0: |
| 281 | case REG_RXSR: |
| 282 | case REG_SLPACK: |
| 283 | case REG_SECCR2: |
| 284 | case REG_BBREG6: |
| 285 | /* use them in spi_async and regmap so it's volatile */ |
| 286 | case REG_BBREG1: |
| 287 | return true; |
| 288 | default: |
| 289 | return false; |
| 290 | } |
| 291 | } |
| 292 | |
| 293 | static bool |
| 294 | mrf24j40_short_reg_precious(struct device *dev, unsigned int reg) |
| 295 | { |
| 296 | /* don't clear irq line on read */ |
| 297 | switch (reg) { |
| 298 | case REG_INTSTAT: |
| 299 | return true; |
| 300 | default: |
| 301 | return false; |
| 302 | } |
| 303 | } |
| 304 | |
| 305 | static const struct regmap_config mrf24j40_short_regmap = { |
| 306 | .name = "mrf24j40_short", |
| 307 | .reg_bits = 7, |
| 308 | .val_bits = 8, |
| 309 | .pad_bits = 1, |
| 310 | .write_flag_mask = MRF24J40_SHORT_WRITE, |
| 311 | .read_flag_mask = MRF24J40_SHORT_READ, |
| 312 | .cache_type = REGCACHE_RBTREE, |
| 313 | .max_register = MRF24J40_SHORT_NUMREGS, |
| 314 | .writeable_reg = mrf24j40_short_reg_writeable, |
| 315 | .readable_reg = mrf24j40_short_reg_readable, |
| 316 | .volatile_reg = mrf24j40_short_reg_volatile, |
| 317 | .precious_reg = mrf24j40_short_reg_precious, |
| 318 | }; |
| 319 | |
| 320 | static bool |
| 321 | mrf24j40_long_reg_writeable(struct device *dev, unsigned int reg) |
| 322 | { |
| 323 | switch (reg) { |
| 324 | case REG_RFCON0: |
| 325 | case REG_RFCON1: |
| 326 | case REG_RFCON2: |
| 327 | case REG_RFCON3: |
| 328 | case REG_RFCON5: |
| 329 | case REG_RFCON6: |
| 330 | case REG_RFCON7: |
| 331 | case REG_RFCON8: |
| 332 | case REG_SLPCAL2: |
| 333 | case REG_SLPCON0: |
| 334 | case REG_SLPCON1: |
| 335 | case REG_WAKETIMEL: |
| 336 | case REG_WAKETIMEH: |
| 337 | case REG_REMCNTL: |
| 338 | case REG_REMCNTH: |
| 339 | case REG_MAINCNT0: |
| 340 | case REG_MAINCNT1: |
| 341 | case REG_MAINCNT2: |
| 342 | case REG_MAINCNT3: |
| 343 | case REG_TESTMODE: |
| 344 | case REG_ASSOEAR0: |
| 345 | case REG_ASSOEAR1: |
| 346 | case REG_ASSOEAR2: |
| 347 | case REG_ASSOEAR3: |
| 348 | case REG_ASSOEAR4: |
| 349 | case REG_ASSOEAR5: |
| 350 | case REG_ASSOEAR6: |
| 351 | case REG_ASSOEAR7: |
| 352 | case REG_ASSOSAR0: |
| 353 | case REG_ASSOSAR1: |
| 354 | case REG_UNONCE0: |
| 355 | case REG_UNONCE1: |
| 356 | case REG_UNONCE2: |
| 357 | case REG_UNONCE3: |
| 358 | case REG_UNONCE4: |
| 359 | case REG_UNONCE5: |
| 360 | case REG_UNONCE6: |
| 361 | case REG_UNONCE7: |
| 362 | case REG_UNONCE8: |
| 363 | case REG_UNONCE9: |
| 364 | case REG_UNONCE10: |
| 365 | case REG_UNONCE11: |
| 366 | case REG_UNONCE12: |
| 367 | return true; |
| 368 | default: |
| 369 | return false; |
| 370 | } |
| 371 | } |
| 372 | |
| 373 | static bool |
| 374 | mrf24j40_long_reg_readable(struct device *dev, unsigned int reg) |
| 375 | { |
| 376 | bool rc; |
| 377 | |
| 378 | /* all writeable are also readable */ |
| 379 | rc = mrf24j40_long_reg_writeable(dev, reg); |
| 380 | if (rc) |
| 381 | return rc; |
| 382 | |
| 383 | /* readonly regs */ |
| 384 | switch (reg) { |
| 385 | case REG_SLPCAL0: |
| 386 | case REG_SLPCAL1: |
| 387 | case REG_RFSTATE: |
| 388 | case REG_RSSI: |
| 389 | return true; |
| 390 | default: |
| 391 | return false; |
| 392 | } |
| 393 | } |
| 394 | |
| 395 | static bool |
| 396 | mrf24j40_long_reg_volatile(struct device *dev, unsigned int reg) |
| 397 | { |
| 398 | /* can be changed during runtime */ |
| 399 | switch (reg) { |
| 400 | case REG_SLPCAL0: |
| 401 | case REG_SLPCAL1: |
| 402 | case REG_SLPCAL2: |
| 403 | case REG_RFSTATE: |
| 404 | case REG_RSSI: |
| 405 | case REG_MAINCNT3: |
| 406 | return true; |
| 407 | default: |
| 408 | return false; |
| 409 | } |
| 410 | } |
| 411 | |
| 412 | static const struct regmap_config mrf24j40_long_regmap = { |
| 413 | .name = "mrf24j40_long", |
| 414 | .reg_bits = 11, |
| 415 | .val_bits = 8, |
| 416 | .pad_bits = 5, |
| 417 | .write_flag_mask = MRF24J40_LONG_ACCESS, |
| 418 | .read_flag_mask = MRF24J40_LONG_ACCESS, |
| 419 | .cache_type = REGCACHE_RBTREE, |
| 420 | .max_register = MRF24J40_LONG_NUMREGS, |
| 421 | .writeable_reg = mrf24j40_long_reg_writeable, |
| 422 | .readable_reg = mrf24j40_long_reg_readable, |
| 423 | .volatile_reg = mrf24j40_long_reg_volatile, |
| 424 | }; |
| 425 | |
| 426 | static int mrf24j40_long_regmap_write(void *context, const void *data, |
| 427 | size_t count) |
| 428 | { |
| 429 | struct spi_device *spi = context; |
| 430 | u8 buf[3]; |
| 431 | |
| 432 | if (count > 3) |
| 433 | return -EINVAL; |
| 434 | |
| 435 | /* regmap supports read/write mask only in frist byte |
| 436 | * long write access need to set the 12th bit, so we |
| 437 | * make special handling for write. |
| 438 | */ |
| 439 | memcpy(buf, data, count); |
| 440 | buf[1] |= (1 << 4); |
| 441 | |
| 442 | return spi_write(spi, buf, count); |
| 443 | } |
| 444 | |
| 445 | static int |
| 446 | mrf24j40_long_regmap_read(void *context, const void *reg, size_t reg_size, |
| 447 | void *val, size_t val_size) |
| 448 | { |
| 449 | struct spi_device *spi = context; |
| 450 | |
| 451 | return spi_write_then_read(spi, reg, reg_size, val, val_size); |
| 452 | } |
| 453 | |
| 454 | static const struct regmap_bus mrf24j40_long_regmap_bus = { |
| 455 | .write = mrf24j40_long_regmap_write, |
| 456 | .read = mrf24j40_long_regmap_read, |
| 457 | .reg_format_endian_default = REGMAP_ENDIAN_BIG, |
| 458 | .val_format_endian_default = REGMAP_ENDIAN_BIG, |
| 459 | }; |
| 460 | |
Alan Ott | 3731a33 | 2012-09-02 15:44:13 +0000 | [diff] [blame] | 461 | static int write_short_reg(struct mrf24j40 *devrec, u8 reg, u8 value) |
| 462 | { |
| 463 | int ret; |
| 464 | struct spi_message msg; |
| 465 | struct spi_transfer xfer = { |
| 466 | .len = 2, |
| 467 | .tx_buf = devrec->buf, |
| 468 | .rx_buf = devrec->buf, |
| 469 | }; |
| 470 | |
| 471 | spi_message_init(&msg); |
| 472 | spi_message_add_tail(&xfer, &msg); |
| 473 | |
| 474 | mutex_lock(&devrec->buffer_mutex); |
| 475 | devrec->buf[0] = MRF24J40_WRITESHORT(reg); |
| 476 | devrec->buf[1] = value; |
| 477 | |
| 478 | ret = spi_sync(devrec->spi, &msg); |
| 479 | if (ret) |
| 480 | dev_err(printdev(devrec), |
| 481 | "SPI write Failed for short register 0x%hhx\n", reg); |
| 482 | |
| 483 | mutex_unlock(&devrec->buffer_mutex); |
| 484 | return ret; |
| 485 | } |
| 486 | |
| 487 | static int read_short_reg(struct mrf24j40 *devrec, u8 reg, u8 *val) |
| 488 | { |
| 489 | int ret = -1; |
| 490 | struct spi_message msg; |
| 491 | struct spi_transfer xfer = { |
| 492 | .len = 2, |
| 493 | .tx_buf = devrec->buf, |
| 494 | .rx_buf = devrec->buf, |
| 495 | }; |
| 496 | |
| 497 | spi_message_init(&msg); |
| 498 | spi_message_add_tail(&xfer, &msg); |
| 499 | |
| 500 | mutex_lock(&devrec->buffer_mutex); |
| 501 | devrec->buf[0] = MRF24J40_READSHORT(reg); |
| 502 | devrec->buf[1] = 0; |
| 503 | |
| 504 | ret = spi_sync(devrec->spi, &msg); |
| 505 | if (ret) |
| 506 | dev_err(printdev(devrec), |
| 507 | "SPI read Failed for short register 0x%hhx\n", reg); |
| 508 | else |
| 509 | *val = devrec->buf[1]; |
| 510 | |
| 511 | mutex_unlock(&devrec->buffer_mutex); |
| 512 | return ret; |
| 513 | } |
| 514 | |
| 515 | static int read_long_reg(struct mrf24j40 *devrec, u16 reg, u8 *value) |
| 516 | { |
| 517 | int ret; |
| 518 | u16 cmd; |
| 519 | struct spi_message msg; |
| 520 | struct spi_transfer xfer = { |
| 521 | .len = 3, |
| 522 | .tx_buf = devrec->buf, |
| 523 | .rx_buf = devrec->buf, |
| 524 | }; |
| 525 | |
| 526 | spi_message_init(&msg); |
| 527 | spi_message_add_tail(&xfer, &msg); |
| 528 | |
| 529 | cmd = MRF24J40_READLONG(reg); |
| 530 | mutex_lock(&devrec->buffer_mutex); |
| 531 | devrec->buf[0] = cmd >> 8 & 0xff; |
| 532 | devrec->buf[1] = cmd & 0xff; |
| 533 | devrec->buf[2] = 0; |
| 534 | |
| 535 | ret = spi_sync(devrec->spi, &msg); |
| 536 | if (ret) |
| 537 | dev_err(printdev(devrec), |
| 538 | "SPI read Failed for long register 0x%hx\n", reg); |
| 539 | else |
| 540 | *value = devrec->buf[2]; |
| 541 | |
| 542 | mutex_unlock(&devrec->buffer_mutex); |
| 543 | return ret; |
| 544 | } |
| 545 | |
| 546 | static int write_long_reg(struct mrf24j40 *devrec, u16 reg, u8 val) |
| 547 | { |
| 548 | int ret; |
| 549 | u16 cmd; |
| 550 | struct spi_message msg; |
| 551 | struct spi_transfer xfer = { |
| 552 | .len = 3, |
| 553 | .tx_buf = devrec->buf, |
| 554 | .rx_buf = devrec->buf, |
| 555 | }; |
| 556 | |
| 557 | spi_message_init(&msg); |
| 558 | spi_message_add_tail(&xfer, &msg); |
| 559 | |
| 560 | cmd = MRF24J40_WRITELONG(reg); |
| 561 | mutex_lock(&devrec->buffer_mutex); |
| 562 | devrec->buf[0] = cmd >> 8 & 0xff; |
| 563 | devrec->buf[1] = cmd & 0xff; |
| 564 | devrec->buf[2] = val; |
| 565 | |
| 566 | ret = spi_sync(devrec->spi, &msg); |
| 567 | if (ret) |
| 568 | dev_err(printdev(devrec), |
| 569 | "SPI write Failed for long register 0x%hx\n", reg); |
| 570 | |
| 571 | mutex_unlock(&devrec->buffer_mutex); |
| 572 | return ret; |
| 573 | } |
| 574 | |
| 575 | /* This function relies on an undocumented write method. Once a write command |
| 576 | and address is set, as many bytes of data as desired can be clocked into |
| 577 | the device. The datasheet only shows setting one byte at a time. */ |
| 578 | static int write_tx_buf(struct mrf24j40 *devrec, u16 reg, |
| 579 | const u8 *data, size_t length) |
| 580 | { |
| 581 | int ret; |
| 582 | u16 cmd; |
| 583 | u8 lengths[2]; |
| 584 | struct spi_message msg; |
| 585 | struct spi_transfer addr_xfer = { |
| 586 | .len = 2, |
| 587 | .tx_buf = devrec->buf, |
| 588 | }; |
| 589 | struct spi_transfer lengths_xfer = { |
| 590 | .len = 2, |
| 591 | .tx_buf = &lengths, /* TODO: Is DMA really required for SPI? */ |
| 592 | }; |
| 593 | struct spi_transfer data_xfer = { |
| 594 | .len = length, |
| 595 | .tx_buf = data, |
| 596 | }; |
| 597 | |
| 598 | /* Range check the length. 2 bytes are used for the length fields.*/ |
| 599 | if (length > TX_FIFO_SIZE-2) { |
| 600 | dev_err(printdev(devrec), "write_tx_buf() was passed too large a buffer. Performing short write.\n"); |
| 601 | length = TX_FIFO_SIZE-2; |
| 602 | } |
| 603 | |
| 604 | spi_message_init(&msg); |
| 605 | spi_message_add_tail(&addr_xfer, &msg); |
| 606 | spi_message_add_tail(&lengths_xfer, &msg); |
| 607 | spi_message_add_tail(&data_xfer, &msg); |
| 608 | |
| 609 | cmd = MRF24J40_WRITELONG(reg); |
| 610 | mutex_lock(&devrec->buffer_mutex); |
| 611 | devrec->buf[0] = cmd >> 8 & 0xff; |
| 612 | devrec->buf[1] = cmd & 0xff; |
| 613 | lengths[0] = 0x0; /* Header Length. Set to 0 for now. TODO */ |
| 614 | lengths[1] = length; /* Total length */ |
| 615 | |
| 616 | ret = spi_sync(devrec->spi, &msg); |
| 617 | if (ret) |
| 618 | dev_err(printdev(devrec), "SPI write Failed for TX buf\n"); |
| 619 | |
| 620 | mutex_unlock(&devrec->buffer_mutex); |
| 621 | return ret; |
| 622 | } |
| 623 | |
| 624 | static int mrf24j40_read_rx_buf(struct mrf24j40 *devrec, |
| 625 | u8 *data, u8 *len, u8 *lqi) |
| 626 | { |
| 627 | u8 rx_len; |
| 628 | u8 addr[2]; |
| 629 | u8 lqi_rssi[2]; |
| 630 | u16 cmd; |
| 631 | int ret; |
| 632 | struct spi_message msg; |
| 633 | struct spi_transfer addr_xfer = { |
| 634 | .len = 2, |
| 635 | .tx_buf = &addr, |
| 636 | }; |
| 637 | struct spi_transfer data_xfer = { |
| 638 | .len = 0x0, /* set below */ |
| 639 | .rx_buf = data, |
| 640 | }; |
| 641 | struct spi_transfer status_xfer = { |
| 642 | .len = 2, |
| 643 | .rx_buf = &lqi_rssi, |
| 644 | }; |
| 645 | |
| 646 | /* Get the length of the data in the RX FIFO. The length in this |
| 647 | * register exclues the 1-byte length field at the beginning. */ |
| 648 | ret = read_long_reg(devrec, REG_RX_FIFO, &rx_len); |
| 649 | if (ret) |
| 650 | goto out; |
| 651 | |
| 652 | /* Range check the RX FIFO length, accounting for the one-byte |
Stefan Schmidt | 5c1be06 | 2014-12-12 12:45:32 +0100 | [diff] [blame] | 653 | * length field at the beginning. */ |
Alan Ott | 3731a33 | 2012-09-02 15:44:13 +0000 | [diff] [blame] | 654 | if (rx_len > RX_FIFO_SIZE-1) { |
| 655 | dev_err(printdev(devrec), "Invalid length read from device. Performing short read.\n"); |
| 656 | rx_len = RX_FIFO_SIZE-1; |
| 657 | } |
| 658 | |
| 659 | if (rx_len > *len) { |
| 660 | /* Passed in buffer wasn't big enough. Should never happen. */ |
| 661 | dev_err(printdev(devrec), "Buffer not big enough. Performing short read\n"); |
| 662 | rx_len = *len; |
| 663 | } |
| 664 | |
| 665 | /* Set up the commands to read the data. */ |
| 666 | cmd = MRF24J40_READLONG(REG_RX_FIFO+1); |
| 667 | addr[0] = cmd >> 8 & 0xff; |
| 668 | addr[1] = cmd & 0xff; |
| 669 | data_xfer.len = rx_len; |
| 670 | |
| 671 | spi_message_init(&msg); |
| 672 | spi_message_add_tail(&addr_xfer, &msg); |
| 673 | spi_message_add_tail(&data_xfer, &msg); |
| 674 | spi_message_add_tail(&status_xfer, &msg); |
| 675 | |
| 676 | ret = spi_sync(devrec->spi, &msg); |
| 677 | if (ret) { |
| 678 | dev_err(printdev(devrec), "SPI RX Buffer Read Failed.\n"); |
| 679 | goto out; |
| 680 | } |
| 681 | |
| 682 | *lqi = lqi_rssi[0]; |
| 683 | *len = rx_len; |
| 684 | |
| 685 | #ifdef DEBUG |
| 686 | print_hex_dump(KERN_DEBUG, "mrf24j40 rx: ", |
Stefan Schmidt | ce261bc | 2014-12-12 12:45:33 +0100 | [diff] [blame] | 687 | DUMP_PREFIX_OFFSET, 16, 1, data, *len, 0); |
Varka Bhadram | ca079ad | 2014-09-24 12:21:32 +0200 | [diff] [blame] | 688 | pr_debug("mrf24j40 rx: lqi: %02hhx rssi: %02hhx\n", |
| 689 | lqi_rssi[0], lqi_rssi[1]); |
Alan Ott | 3731a33 | 2012-09-02 15:44:13 +0000 | [diff] [blame] | 690 | #endif |
| 691 | |
| 692 | out: |
| 693 | return ret; |
| 694 | } |
| 695 | |
Alexander Aring | 5a50439 | 2014-10-25 17:16:34 +0200 | [diff] [blame] | 696 | static int mrf24j40_tx(struct ieee802154_hw *hw, struct sk_buff *skb) |
Alan Ott | 3731a33 | 2012-09-02 15:44:13 +0000 | [diff] [blame] | 697 | { |
Alexander Aring | 5a50439 | 2014-10-25 17:16:34 +0200 | [diff] [blame] | 698 | struct mrf24j40 *devrec = hw->priv; |
Alan Ott | 3731a33 | 2012-09-02 15:44:13 +0000 | [diff] [blame] | 699 | u8 val; |
| 700 | int ret = 0; |
| 701 | |
| 702 | dev_dbg(printdev(devrec), "tx packet of %d bytes\n", skb->len); |
| 703 | |
| 704 | ret = write_tx_buf(devrec, 0x000, skb->data, skb->len); |
| 705 | if (ret) |
| 706 | goto err; |
| 707 | |
Wolfram Sang | 16735d0 | 2013-11-14 14:32:02 -0800 | [diff] [blame] | 708 | reinit_completion(&devrec->tx_complete); |
Alan Ott | 9757f1d | 2013-10-05 23:52:22 -0400 | [diff] [blame] | 709 | |
Alan Ott | 3731a33 | 2012-09-02 15:44:13 +0000 | [diff] [blame] | 710 | /* Set TXNTRIG bit of TXNCON to send packet */ |
| 711 | ret = read_short_reg(devrec, REG_TXNCON, &val); |
| 712 | if (ret) |
| 713 | goto err; |
| 714 | val |= 0x1; |
Alan Ott | cbde812 | 2013-04-05 10:34:51 +0000 | [diff] [blame] | 715 | /* Set TXNACKREQ if the ACK bit is set in the packet. */ |
| 716 | if (skb->data[0] & IEEE802154_FC_ACK_REQ) |
| 717 | val |= 0x4; |
Alan Ott | 3731a33 | 2012-09-02 15:44:13 +0000 | [diff] [blame] | 718 | write_short_reg(devrec, REG_TXNCON, val); |
| 719 | |
Alan Ott | 3731a33 | 2012-09-02 15:44:13 +0000 | [diff] [blame] | 720 | /* Wait for the device to send the TX complete interrupt. */ |
| 721 | ret = wait_for_completion_interruptible_timeout( |
| 722 | &devrec->tx_complete, |
| 723 | 5 * HZ); |
| 724 | if (ret == -ERESTARTSYS) |
| 725 | goto err; |
| 726 | if (ret == 0) { |
Alan Ott | 7a1c231 | 2013-03-18 12:06:41 +0000 | [diff] [blame] | 727 | dev_warn(printdev(devrec), "Timeout waiting for TX interrupt\n"); |
Alan Ott | 3731a33 | 2012-09-02 15:44:13 +0000 | [diff] [blame] | 728 | ret = -ETIMEDOUT; |
| 729 | goto err; |
| 730 | } |
| 731 | |
| 732 | /* Check for send error from the device. */ |
| 733 | ret = read_short_reg(devrec, REG_TXSTAT, &val); |
| 734 | if (ret) |
| 735 | goto err; |
| 736 | if (val & 0x1) { |
Alan Ott | cbde812 | 2013-04-05 10:34:51 +0000 | [diff] [blame] | 737 | dev_dbg(printdev(devrec), "Error Sending. Retry count exceeded\n"); |
Alan Ott | 3731a33 | 2012-09-02 15:44:13 +0000 | [diff] [blame] | 738 | ret = -ECOMM; /* TODO: Better error code ? */ |
| 739 | } else |
| 740 | dev_dbg(printdev(devrec), "Packet Sent\n"); |
| 741 | |
| 742 | err: |
| 743 | |
| 744 | return ret; |
| 745 | } |
| 746 | |
Alexander Aring | 5a50439 | 2014-10-25 17:16:34 +0200 | [diff] [blame] | 747 | static int mrf24j40_ed(struct ieee802154_hw *hw, u8 *level) |
Alan Ott | 3731a33 | 2012-09-02 15:44:13 +0000 | [diff] [blame] | 748 | { |
| 749 | /* TODO: */ |
Varka Bhadram | ca079ad | 2014-09-24 12:21:32 +0200 | [diff] [blame] | 750 | pr_warn("mrf24j40: ed not implemented\n"); |
Alan Ott | 3731a33 | 2012-09-02 15:44:13 +0000 | [diff] [blame] | 751 | *level = 0; |
| 752 | return 0; |
| 753 | } |
| 754 | |
Alexander Aring | 5a50439 | 2014-10-25 17:16:34 +0200 | [diff] [blame] | 755 | static int mrf24j40_start(struct ieee802154_hw *hw) |
Alan Ott | 3731a33 | 2012-09-02 15:44:13 +0000 | [diff] [blame] | 756 | { |
Alexander Aring | 5a50439 | 2014-10-25 17:16:34 +0200 | [diff] [blame] | 757 | struct mrf24j40 *devrec = hw->priv; |
Alan Ott | 3731a33 | 2012-09-02 15:44:13 +0000 | [diff] [blame] | 758 | u8 val; |
| 759 | int ret; |
| 760 | |
| 761 | dev_dbg(printdev(devrec), "start\n"); |
| 762 | |
| 763 | ret = read_short_reg(devrec, REG_INTCON, &val); |
| 764 | if (ret) |
| 765 | return ret; |
| 766 | val &= ~(0x1|0x8); /* Clear TXNIE and RXIE. Enable interrupts */ |
| 767 | write_short_reg(devrec, REG_INTCON, val); |
| 768 | |
| 769 | return 0; |
| 770 | } |
| 771 | |
Alexander Aring | 5a50439 | 2014-10-25 17:16:34 +0200 | [diff] [blame] | 772 | static void mrf24j40_stop(struct ieee802154_hw *hw) |
Alan Ott | 3731a33 | 2012-09-02 15:44:13 +0000 | [diff] [blame] | 773 | { |
Alexander Aring | 5a50439 | 2014-10-25 17:16:34 +0200 | [diff] [blame] | 774 | struct mrf24j40 *devrec = hw->priv; |
Alan Ott | 3731a33 | 2012-09-02 15:44:13 +0000 | [diff] [blame] | 775 | u8 val; |
| 776 | int ret; |
Varka Bhadram | 529160d | 2014-09-24 12:21:30 +0200 | [diff] [blame] | 777 | |
Alan Ott | 3731a33 | 2012-09-02 15:44:13 +0000 | [diff] [blame] | 778 | dev_dbg(printdev(devrec), "stop\n"); |
| 779 | |
| 780 | ret = read_short_reg(devrec, REG_INTCON, &val); |
| 781 | if (ret) |
| 782 | return; |
| 783 | val |= 0x1|0x8; /* Set TXNIE and RXIE. Disable Interrupts */ |
| 784 | write_short_reg(devrec, REG_INTCON, val); |
Alan Ott | 3731a33 | 2012-09-02 15:44:13 +0000 | [diff] [blame] | 785 | } |
| 786 | |
Alexander Aring | e37d2ec | 2014-10-28 18:21:19 +0100 | [diff] [blame] | 787 | static int mrf24j40_set_channel(struct ieee802154_hw *hw, u8 page, u8 channel) |
Alan Ott | 3731a33 | 2012-09-02 15:44:13 +0000 | [diff] [blame] | 788 | { |
Alexander Aring | 5a50439 | 2014-10-25 17:16:34 +0200 | [diff] [blame] | 789 | struct mrf24j40 *devrec = hw->priv; |
Alan Ott | 3731a33 | 2012-09-02 15:44:13 +0000 | [diff] [blame] | 790 | u8 val; |
| 791 | int ret; |
| 792 | |
| 793 | dev_dbg(printdev(devrec), "Set Channel %d\n", channel); |
| 794 | |
| 795 | WARN_ON(page != 0); |
| 796 | WARN_ON(channel < MRF24J40_CHAN_MIN); |
| 797 | WARN_ON(channel > MRF24J40_CHAN_MAX); |
| 798 | |
| 799 | /* Set Channel TODO */ |
| 800 | val = (channel-11) << 4 | 0x03; |
| 801 | write_long_reg(devrec, REG_RFCON0, val); |
| 802 | |
| 803 | /* RF Reset */ |
| 804 | ret = read_short_reg(devrec, REG_RFCTL, &val); |
| 805 | if (ret) |
| 806 | return ret; |
| 807 | val |= 0x04; |
| 808 | write_short_reg(devrec, REG_RFCTL, val); |
| 809 | val &= ~0x04; |
| 810 | write_short_reg(devrec, REG_RFCTL, val); |
| 811 | |
| 812 | udelay(SET_CHANNEL_DELAY_US); /* per datasheet */ |
| 813 | |
| 814 | return 0; |
| 815 | } |
| 816 | |
Alexander Aring | 5a50439 | 2014-10-25 17:16:34 +0200 | [diff] [blame] | 817 | static int mrf24j40_filter(struct ieee802154_hw *hw, |
Alan Ott | 3731a33 | 2012-09-02 15:44:13 +0000 | [diff] [blame] | 818 | struct ieee802154_hw_addr_filt *filt, |
| 819 | unsigned long changed) |
| 820 | { |
Alexander Aring | 5a50439 | 2014-10-25 17:16:34 +0200 | [diff] [blame] | 821 | struct mrf24j40 *devrec = hw->priv; |
Alan Ott | 3731a33 | 2012-09-02 15:44:13 +0000 | [diff] [blame] | 822 | |
| 823 | dev_dbg(printdev(devrec), "filter\n"); |
| 824 | |
Alexander Aring | 57205c1 | 2014-10-25 05:25:09 +0200 | [diff] [blame] | 825 | if (changed & IEEE802154_AFILT_SADDR_CHANGED) { |
Alan Ott | 3731a33 | 2012-09-02 15:44:13 +0000 | [diff] [blame] | 826 | /* Short Addr */ |
| 827 | u8 addrh, addrl; |
Varka Bhadram | 529160d | 2014-09-24 12:21:30 +0200 | [diff] [blame] | 828 | |
Phoebe Buckheister | b70ab2e | 2014-03-14 21:23:59 +0100 | [diff] [blame] | 829 | addrh = le16_to_cpu(filt->short_addr) >> 8 & 0xff; |
| 830 | addrl = le16_to_cpu(filt->short_addr) & 0xff; |
Alan Ott | 3731a33 | 2012-09-02 15:44:13 +0000 | [diff] [blame] | 831 | |
| 832 | write_short_reg(devrec, REG_SADRH, addrh); |
| 833 | write_short_reg(devrec, REG_SADRL, addrl); |
| 834 | dev_dbg(printdev(devrec), |
| 835 | "Set short addr to %04hx\n", filt->short_addr); |
| 836 | } |
| 837 | |
Alexander Aring | 57205c1 | 2014-10-25 05:25:09 +0200 | [diff] [blame] | 838 | if (changed & IEEE802154_AFILT_IEEEADDR_CHANGED) { |
Alan Ott | 3731a33 | 2012-09-02 15:44:13 +0000 | [diff] [blame] | 839 | /* Device Address */ |
Phoebe Buckheister | b70ab2e | 2014-03-14 21:23:59 +0100 | [diff] [blame] | 840 | u8 i, addr[8]; |
| 841 | |
| 842 | memcpy(addr, &filt->ieee_addr, 8); |
Alan Ott | 3731a33 | 2012-09-02 15:44:13 +0000 | [diff] [blame] | 843 | for (i = 0; i < 8; i++) |
Phoebe Buckheister | b70ab2e | 2014-03-14 21:23:59 +0100 | [diff] [blame] | 844 | write_short_reg(devrec, REG_EADR0 + i, addr[i]); |
Alan Ott | 3731a33 | 2012-09-02 15:44:13 +0000 | [diff] [blame] | 845 | |
| 846 | #ifdef DEBUG |
Varka Bhadram | ca079ad | 2014-09-24 12:21:32 +0200 | [diff] [blame] | 847 | pr_debug("Set long addr to: "); |
Alan Ott | 3731a33 | 2012-09-02 15:44:13 +0000 | [diff] [blame] | 848 | for (i = 0; i < 8; i++) |
Varka Bhadram | ca079ad | 2014-09-24 12:21:32 +0200 | [diff] [blame] | 849 | pr_debug("%02hhx ", addr[7 - i]); |
| 850 | pr_debug("\n"); |
Alan Ott | 3731a33 | 2012-09-02 15:44:13 +0000 | [diff] [blame] | 851 | #endif |
| 852 | } |
| 853 | |
Alexander Aring | 57205c1 | 2014-10-25 05:25:09 +0200 | [diff] [blame] | 854 | if (changed & IEEE802154_AFILT_PANID_CHANGED) { |
Alan Ott | 3731a33 | 2012-09-02 15:44:13 +0000 | [diff] [blame] | 855 | /* PAN ID */ |
| 856 | u8 panidl, panidh; |
Varka Bhadram | 529160d | 2014-09-24 12:21:30 +0200 | [diff] [blame] | 857 | |
Phoebe Buckheister | b70ab2e | 2014-03-14 21:23:59 +0100 | [diff] [blame] | 858 | panidh = le16_to_cpu(filt->pan_id) >> 8 & 0xff; |
| 859 | panidl = le16_to_cpu(filt->pan_id) & 0xff; |
Alan Ott | 3731a33 | 2012-09-02 15:44:13 +0000 | [diff] [blame] | 860 | write_short_reg(devrec, REG_PANIDH, panidh); |
| 861 | write_short_reg(devrec, REG_PANIDL, panidl); |
| 862 | |
| 863 | dev_dbg(printdev(devrec), "Set PANID to %04hx\n", filt->pan_id); |
| 864 | } |
| 865 | |
Alexander Aring | 57205c1 | 2014-10-25 05:25:09 +0200 | [diff] [blame] | 866 | if (changed & IEEE802154_AFILT_PANC_CHANGED) { |
Alan Ott | 3731a33 | 2012-09-02 15:44:13 +0000 | [diff] [blame] | 867 | /* Pan Coordinator */ |
| 868 | u8 val; |
| 869 | int ret; |
| 870 | |
| 871 | ret = read_short_reg(devrec, REG_RXMCR, &val); |
| 872 | if (ret) |
| 873 | return ret; |
| 874 | if (filt->pan_coord) |
| 875 | val |= 0x8; |
| 876 | else |
| 877 | val &= ~0x8; |
| 878 | write_short_reg(devrec, REG_RXMCR, val); |
| 879 | |
| 880 | /* REG_SLOTTED is maintained as default (unslotted/CSMA-CA). |
| 881 | * REG_ORDER is maintained as default (no beacon/superframe). |
| 882 | */ |
| 883 | |
| 884 | dev_dbg(printdev(devrec), "Set Pan Coord to %s\n", |
Stefan Schmidt | ce261bc | 2014-12-12 12:45:33 +0100 | [diff] [blame] | 885 | filt->pan_coord ? "on" : "off"); |
Alan Ott | 3731a33 | 2012-09-02 15:44:13 +0000 | [diff] [blame] | 886 | } |
| 887 | |
| 888 | return 0; |
| 889 | } |
| 890 | |
| 891 | static int mrf24j40_handle_rx(struct mrf24j40 *devrec) |
| 892 | { |
| 893 | u8 len = RX_FIFO_SIZE; |
| 894 | u8 lqi = 0; |
| 895 | u8 val; |
| 896 | int ret = 0; |
Stefan Schmidt | e5719b6 | 2015-06-09 10:52:26 +0200 | [diff] [blame] | 897 | int ret2; |
Alan Ott | 3731a33 | 2012-09-02 15:44:13 +0000 | [diff] [blame] | 898 | struct sk_buff *skb; |
| 899 | |
| 900 | /* Turn off reception of packets off the air. This prevents the |
| 901 | * device from overwriting the buffer while we're reading it. */ |
| 902 | ret = read_short_reg(devrec, REG_BBREG1, &val); |
| 903 | if (ret) |
| 904 | goto out; |
| 905 | val |= 4; /* SET RXDECINV */ |
| 906 | write_short_reg(devrec, REG_BBREG1, val); |
| 907 | |
Alexander Aring | 61a2281 | 2014-10-27 17:13:29 +0100 | [diff] [blame] | 908 | skb = dev_alloc_skb(len); |
Alan Ott | 3731a33 | 2012-09-02 15:44:13 +0000 | [diff] [blame] | 909 | if (!skb) { |
| 910 | ret = -ENOMEM; |
| 911 | goto out; |
| 912 | } |
| 913 | |
| 914 | ret = mrf24j40_read_rx_buf(devrec, skb_put(skb, len), &len, &lqi); |
| 915 | if (ret < 0) { |
| 916 | dev_err(printdev(devrec), "Failure reading RX FIFO\n"); |
| 917 | kfree_skb(skb); |
| 918 | ret = -EINVAL; |
| 919 | goto out; |
| 920 | } |
| 921 | |
| 922 | /* Cut off the checksum */ |
| 923 | skb_trim(skb, len-2); |
| 924 | |
| 925 | /* TODO: Other drivers call ieee20154_rx_irqsafe() here (eg: cc2040, |
| 926 | * also from a workqueue). I think irqsafe is not necessary here. |
| 927 | * Can someone confirm? */ |
Alexander Aring | 5a50439 | 2014-10-25 17:16:34 +0200 | [diff] [blame] | 928 | ieee802154_rx_irqsafe(devrec->hw, skb, lqi); |
Alan Ott | 3731a33 | 2012-09-02 15:44:13 +0000 | [diff] [blame] | 929 | |
| 930 | dev_dbg(printdev(devrec), "RX Handled\n"); |
| 931 | |
| 932 | out: |
| 933 | /* Turn back on reception of packets off the air. */ |
Stefan Schmidt | e5719b6 | 2015-06-09 10:52:26 +0200 | [diff] [blame] | 934 | ret2 = read_short_reg(devrec, REG_BBREG1, &val); |
| 935 | if (ret2) |
| 936 | return ret2; |
Alan Ott | 3731a33 | 2012-09-02 15:44:13 +0000 | [diff] [blame] | 937 | val &= ~0x4; /* Clear RXDECINV */ |
| 938 | write_short_reg(devrec, REG_BBREG1, val); |
| 939 | |
| 940 | return ret; |
| 941 | } |
| 942 | |
Alexander Aring | 1630186 | 2014-10-28 18:21:18 +0100 | [diff] [blame] | 943 | static const struct ieee802154_ops mrf24j40_ops = { |
Alan Ott | 3731a33 | 2012-09-02 15:44:13 +0000 | [diff] [blame] | 944 | .owner = THIS_MODULE, |
Alexander Aring | ed0a5dc | 2014-10-26 09:37:08 +0100 | [diff] [blame] | 945 | .xmit_sync = mrf24j40_tx, |
Alan Ott | 3731a33 | 2012-09-02 15:44:13 +0000 | [diff] [blame] | 946 | .ed = mrf24j40_ed, |
| 947 | .start = mrf24j40_start, |
| 948 | .stop = mrf24j40_stop, |
| 949 | .set_channel = mrf24j40_set_channel, |
| 950 | .set_hw_addr_filt = mrf24j40_filter, |
| 951 | }; |
| 952 | |
| 953 | static irqreturn_t mrf24j40_isr(int irq, void *data) |
| 954 | { |
| 955 | struct mrf24j40 *devrec = data; |
Alan Ott | 3731a33 | 2012-09-02 15:44:13 +0000 | [diff] [blame] | 956 | u8 intstat; |
| 957 | int ret; |
| 958 | |
| 959 | /* Read the interrupt status */ |
| 960 | ret = read_short_reg(devrec, REG_INTSTAT, &intstat); |
| 961 | if (ret) |
| 962 | goto out; |
| 963 | |
| 964 | /* Check for TX complete */ |
| 965 | if (intstat & 0x1) |
| 966 | complete(&devrec->tx_complete); |
| 967 | |
| 968 | /* Check for Rx */ |
| 969 | if (intstat & 0x8) |
| 970 | mrf24j40_handle_rx(devrec); |
| 971 | |
| 972 | out: |
Alan Ott | 4a4e1da | 2013-10-05 23:52:23 -0400 | [diff] [blame] | 973 | return IRQ_HANDLED; |
Alan Ott | 3731a33 | 2012-09-02 15:44:13 +0000 | [diff] [blame] | 974 | } |
| 975 | |
Varka Bhadram | 3dac9a7 | 2014-06-16 09:12:31 +0530 | [diff] [blame] | 976 | static int mrf24j40_hw_init(struct mrf24j40 *devrec) |
| 977 | { |
| 978 | int ret; |
| 979 | u8 val; |
| 980 | |
| 981 | /* Initialize the device. |
| 982 | From datasheet section 3.2: Initialization. */ |
| 983 | ret = write_short_reg(devrec, REG_SOFTRST, 0x07); |
| 984 | if (ret) |
| 985 | goto err_ret; |
| 986 | |
| 987 | ret = write_short_reg(devrec, REG_PACON2, 0x98); |
| 988 | if (ret) |
| 989 | goto err_ret; |
| 990 | |
| 991 | ret = write_short_reg(devrec, REG_TXSTBL, 0x95); |
| 992 | if (ret) |
| 993 | goto err_ret; |
| 994 | |
| 995 | ret = write_long_reg(devrec, REG_RFCON0, 0x03); |
| 996 | if (ret) |
| 997 | goto err_ret; |
| 998 | |
| 999 | ret = write_long_reg(devrec, REG_RFCON1, 0x01); |
| 1000 | if (ret) |
| 1001 | goto err_ret; |
| 1002 | |
| 1003 | ret = write_long_reg(devrec, REG_RFCON2, 0x80); |
| 1004 | if (ret) |
| 1005 | goto err_ret; |
| 1006 | |
| 1007 | ret = write_long_reg(devrec, REG_RFCON6, 0x90); |
| 1008 | if (ret) |
| 1009 | goto err_ret; |
| 1010 | |
| 1011 | ret = write_long_reg(devrec, REG_RFCON7, 0x80); |
| 1012 | if (ret) |
| 1013 | goto err_ret; |
| 1014 | |
| 1015 | ret = write_long_reg(devrec, REG_RFCON8, 0x10); |
| 1016 | if (ret) |
| 1017 | goto err_ret; |
| 1018 | |
| 1019 | ret = write_long_reg(devrec, REG_SLPCON1, 0x21); |
| 1020 | if (ret) |
| 1021 | goto err_ret; |
| 1022 | |
| 1023 | ret = write_short_reg(devrec, REG_BBREG2, 0x80); |
| 1024 | if (ret) |
| 1025 | goto err_ret; |
| 1026 | |
| 1027 | ret = write_short_reg(devrec, REG_CCAEDTH, 0x60); |
| 1028 | if (ret) |
| 1029 | goto err_ret; |
| 1030 | |
| 1031 | ret = write_short_reg(devrec, REG_BBREG6, 0x40); |
| 1032 | if (ret) |
| 1033 | goto err_ret; |
| 1034 | |
| 1035 | ret = write_short_reg(devrec, REG_RFCTL, 0x04); |
| 1036 | if (ret) |
| 1037 | goto err_ret; |
| 1038 | |
| 1039 | ret = write_short_reg(devrec, REG_RFCTL, 0x0); |
| 1040 | if (ret) |
| 1041 | goto err_ret; |
| 1042 | |
| 1043 | udelay(192); |
| 1044 | |
| 1045 | /* Set RX Mode. RXMCR<1:0>: 0x0 normal, 0x1 promisc, 0x2 error */ |
| 1046 | ret = read_short_reg(devrec, REG_RXMCR, &val); |
| 1047 | if (ret) |
| 1048 | goto err_ret; |
| 1049 | |
| 1050 | val &= ~0x3; /* Clear RX mode (normal) */ |
| 1051 | |
| 1052 | ret = write_short_reg(devrec, REG_RXMCR, val); |
| 1053 | if (ret) |
| 1054 | goto err_ret; |
| 1055 | |
Simon Vincent | db9e0ee | 2014-10-06 10:39:45 +0100 | [diff] [blame] | 1056 | if (spi_get_device_id(devrec->spi)->driver_data == MRF24J40MC) { |
| 1057 | /* Enable external amplifier. |
| 1058 | * From MRF24J40MC datasheet section 1.3: Operation. |
| 1059 | */ |
| 1060 | read_long_reg(devrec, REG_TESTMODE, &val); |
| 1061 | val |= 0x7; /* Configure GPIO 0-2 to control amplifier */ |
| 1062 | write_long_reg(devrec, REG_TESTMODE, val); |
| 1063 | |
| 1064 | read_short_reg(devrec, REG_TRISGPIO, &val); |
| 1065 | val |= 0x8; /* Set GPIO3 as output. */ |
| 1066 | write_short_reg(devrec, REG_TRISGPIO, val); |
| 1067 | |
| 1068 | read_short_reg(devrec, REG_GPIO, &val); |
| 1069 | val |= 0x8; /* Set GPIO3 HIGH to enable U5 voltage regulator */ |
| 1070 | write_short_reg(devrec, REG_GPIO, val); |
| 1071 | |
| 1072 | /* Reduce TX pwr to meet FCC requirements. |
| 1073 | * From MRF24J40MC datasheet section 3.1.1 |
| 1074 | */ |
| 1075 | write_long_reg(devrec, REG_RFCON3, 0x28); |
| 1076 | } |
| 1077 | |
Varka Bhadram | 3dac9a7 | 2014-06-16 09:12:31 +0530 | [diff] [blame] | 1078 | return 0; |
| 1079 | |
| 1080 | err_ret: |
| 1081 | return ret; |
| 1082 | } |
| 1083 | |
Alexander Aring | 766928f | 2015-09-21 11:24:27 +0200 | [diff] [blame] | 1084 | static void mrf24j40_phy_setup(struct mrf24j40 *devrec) |
| 1085 | { |
Alexander Aring | d344c91 | 2015-09-21 11:24:28 +0200 | [diff] [blame] | 1086 | ieee802154_random_extended_addr(&devrec->hw->phy->perm_extended_addr); |
Alexander Aring | 766928f | 2015-09-21 11:24:27 +0200 | [diff] [blame] | 1087 | devrec->hw->phy->current_channel = 11; |
| 1088 | } |
| 1089 | |
Bill Pemberton | bb1f460 | 2012-12-03 09:24:12 -0500 | [diff] [blame] | 1090 | static int mrf24j40_probe(struct spi_device *spi) |
Alan Ott | 3731a33 | 2012-09-02 15:44:13 +0000 | [diff] [blame] | 1091 | { |
| 1092 | int ret = -ENOMEM; |
Alexander Aring | b2cfdf3 | 2015-09-21 11:24:23 +0200 | [diff] [blame] | 1093 | struct ieee802154_hw *hw; |
Alan Ott | 3731a33 | 2012-09-02 15:44:13 +0000 | [diff] [blame] | 1094 | struct mrf24j40 *devrec; |
| 1095 | |
Varka Bhadram | ca079ad | 2014-09-24 12:21:32 +0200 | [diff] [blame] | 1096 | dev_info(&spi->dev, "probe(). IRQ: %d\n", spi->irq); |
Alan Ott | 3731a33 | 2012-09-02 15:44:13 +0000 | [diff] [blame] | 1097 | |
Alexander Aring | b2cfdf3 | 2015-09-21 11:24:23 +0200 | [diff] [blame] | 1098 | /* Register with the 802154 subsystem */ |
| 1099 | |
| 1100 | hw = ieee802154_alloc_hw(sizeof(*devrec), &mrf24j40_ops); |
| 1101 | if (!hw) |
Varka Bhadram | 0aaf43f | 2014-06-11 10:04:44 +0530 | [diff] [blame] | 1102 | goto err_ret; |
Alexander Aring | b2cfdf3 | 2015-09-21 11:24:23 +0200 | [diff] [blame] | 1103 | |
| 1104 | devrec = hw->priv; |
| 1105 | devrec->spi = spi; |
| 1106 | spi_set_drvdata(spi, devrec); |
| 1107 | devrec->hw = hw; |
| 1108 | devrec->hw->parent = &spi->dev; |
| 1109 | devrec->hw->phy->supported.channels[0] = CHANNEL_MASK; |
| 1110 | devrec->hw->flags = IEEE802154_HW_OMIT_CKSUM | IEEE802154_HW_AFILT; |
| 1111 | |
Alexander Aring | b015679 | 2015-09-21 11:24:30 +0200 | [diff] [blame^] | 1112 | devrec->regmap_short = devm_regmap_init_spi(spi, |
| 1113 | &mrf24j40_short_regmap); |
| 1114 | if (IS_ERR(devrec->regmap_short)) { |
| 1115 | ret = PTR_ERR(devrec->regmap_short); |
| 1116 | dev_err(&spi->dev, "Failed to allocate short register map: %d\n", |
| 1117 | ret); |
| 1118 | goto err_register_device; |
| 1119 | } |
| 1120 | |
| 1121 | devrec->regmap_long = devm_regmap_init(&spi->dev, |
| 1122 | &mrf24j40_long_regmap_bus, |
| 1123 | spi, &mrf24j40_long_regmap); |
| 1124 | if (IS_ERR(devrec->regmap_long)) { |
| 1125 | ret = PTR_ERR(devrec->regmap_long); |
| 1126 | dev_err(&spi->dev, "Failed to allocate long register map: %d\n", |
| 1127 | ret); |
| 1128 | goto err_register_device; |
| 1129 | } |
| 1130 | |
Varka Bhadram | 0aaf43f | 2014-06-11 10:04:44 +0530 | [diff] [blame] | 1131 | devrec->buf = devm_kzalloc(&spi->dev, 3, GFP_KERNEL); |
Alan Ott | 3731a33 | 2012-09-02 15:44:13 +0000 | [diff] [blame] | 1132 | if (!devrec->buf) |
Alexander Aring | b2cfdf3 | 2015-09-21 11:24:23 +0200 | [diff] [blame] | 1133 | goto err_register_device; |
Alan Ott | 3731a33 | 2012-09-02 15:44:13 +0000 | [diff] [blame] | 1134 | |
Alexander Aring | 78aedb6 | 2015-09-21 11:24:25 +0200 | [diff] [blame] | 1135 | if (spi->max_speed_hz > MAX_SPI_SPEED_HZ) { |
| 1136 | dev_warn(&spi->dev, "spi clock above possible maximum: %d", |
| 1137 | MAX_SPI_SPEED_HZ); |
| 1138 | return -EINVAL; |
| 1139 | } |
Alan Ott | 3731a33 | 2012-09-02 15:44:13 +0000 | [diff] [blame] | 1140 | |
| 1141 | mutex_init(&devrec->buffer_mutex); |
| 1142 | init_completion(&devrec->tx_complete); |
Alan Ott | 3731a33 | 2012-09-02 15:44:13 +0000 | [diff] [blame] | 1143 | |
Varka Bhadram | 3dac9a7 | 2014-06-16 09:12:31 +0530 | [diff] [blame] | 1144 | ret = mrf24j40_hw_init(devrec); |
Alan Ott | 3731a33 | 2012-09-02 15:44:13 +0000 | [diff] [blame] | 1145 | if (ret) |
Alexander Aring | a339e18 | 2015-09-21 11:24:24 +0200 | [diff] [blame] | 1146 | goto err_register_device; |
Alan Ott | 3731a33 | 2012-09-02 15:44:13 +0000 | [diff] [blame] | 1147 | |
Alexander Aring | 766928f | 2015-09-21 11:24:27 +0200 | [diff] [blame] | 1148 | mrf24j40_phy_setup(devrec); |
| 1149 | |
Varka Bhadram | 0aaf43f | 2014-06-11 10:04:44 +0530 | [diff] [blame] | 1150 | ret = devm_request_threaded_irq(&spi->dev, |
| 1151 | spi->irq, |
| 1152 | NULL, |
| 1153 | mrf24j40_isr, |
| 1154 | IRQF_TRIGGER_LOW|IRQF_ONESHOT, |
| 1155 | dev_name(&spi->dev), |
| 1156 | devrec); |
Alan Ott | 3731a33 | 2012-09-02 15:44:13 +0000 | [diff] [blame] | 1157 | |
| 1158 | if (ret) { |
| 1159 | dev_err(printdev(devrec), "Unable to get IRQ"); |
Alexander Aring | a339e18 | 2015-09-21 11:24:24 +0200 | [diff] [blame] | 1160 | goto err_register_device; |
Alan Ott | 3731a33 | 2012-09-02 15:44:13 +0000 | [diff] [blame] | 1161 | } |
| 1162 | |
Alexander Aring | a339e18 | 2015-09-21 11:24:24 +0200 | [diff] [blame] | 1163 | dev_dbg(printdev(devrec), "registered mrf24j40\n"); |
| 1164 | ret = ieee802154_register_hw(devrec->hw); |
| 1165 | if (ret) |
| 1166 | goto err_register_device; |
| 1167 | |
Alan Ott | 3731a33 | 2012-09-02 15:44:13 +0000 | [diff] [blame] | 1168 | return 0; |
| 1169 | |
Alan Ott | 3731a33 | 2012-09-02 15:44:13 +0000 | [diff] [blame] | 1170 | err_register_device: |
Alexander Aring | 5a50439 | 2014-10-25 17:16:34 +0200 | [diff] [blame] | 1171 | ieee802154_free_hw(devrec->hw); |
Varka Bhadram | 0aaf43f | 2014-06-11 10:04:44 +0530 | [diff] [blame] | 1172 | err_ret: |
Alan Ott | 3731a33 | 2012-09-02 15:44:13 +0000 | [diff] [blame] | 1173 | return ret; |
| 1174 | } |
| 1175 | |
Bill Pemberton | bb1f460 | 2012-12-03 09:24:12 -0500 | [diff] [blame] | 1176 | static int mrf24j40_remove(struct spi_device *spi) |
Alan Ott | 3731a33 | 2012-09-02 15:44:13 +0000 | [diff] [blame] | 1177 | { |
Jingoo Han | 4fa0a0e | 2013-04-05 20:34:18 +0000 | [diff] [blame] | 1178 | struct mrf24j40 *devrec = spi_get_drvdata(spi); |
Alan Ott | 3731a33 | 2012-09-02 15:44:13 +0000 | [diff] [blame] | 1179 | |
| 1180 | dev_dbg(printdev(devrec), "remove\n"); |
| 1181 | |
Alexander Aring | 5a50439 | 2014-10-25 17:16:34 +0200 | [diff] [blame] | 1182 | ieee802154_unregister_hw(devrec->hw); |
| 1183 | ieee802154_free_hw(devrec->hw); |
Alan Ott | 3731a33 | 2012-09-02 15:44:13 +0000 | [diff] [blame] | 1184 | /* TODO: Will ieee802154_free_device() wait until ->xmit() is |
| 1185 | * complete? */ |
| 1186 | |
Alan Ott | 3731a33 | 2012-09-02 15:44:13 +0000 | [diff] [blame] | 1187 | return 0; |
| 1188 | } |
| 1189 | |
Alexander Aring | 2e6fd64 | 2015-09-21 11:24:26 +0200 | [diff] [blame] | 1190 | static const struct of_device_id mrf24j40_of_match[] = { |
| 1191 | { .compatible = "microchip,mrf24j40", .data = (void *)MRF24J40 }, |
| 1192 | { .compatible = "microchip,mrf24j40ma", .data = (void *)MRF24J40MA }, |
| 1193 | { .compatible = "microchip,mrf24j40mc", .data = (void *)MRF24J40MC }, |
| 1194 | { }, |
| 1195 | }; |
| 1196 | MODULE_DEVICE_TABLE(of, mrf24j40_of_match); |
| 1197 | |
Alan Ott | 3731a33 | 2012-09-02 15:44:13 +0000 | [diff] [blame] | 1198 | static const struct spi_device_id mrf24j40_ids[] = { |
Simon Vincent | db9e0ee | 2014-10-06 10:39:45 +0100 | [diff] [blame] | 1199 | { "mrf24j40", MRF24J40 }, |
| 1200 | { "mrf24j40ma", MRF24J40MA }, |
| 1201 | { "mrf24j40mc", MRF24J40MC }, |
Alan Ott | 3731a33 | 2012-09-02 15:44:13 +0000 | [diff] [blame] | 1202 | { }, |
| 1203 | }; |
| 1204 | MODULE_DEVICE_TABLE(spi, mrf24j40_ids); |
| 1205 | |
| 1206 | static struct spi_driver mrf24j40_driver = { |
| 1207 | .driver = { |
Alexander Aring | 2e6fd64 | 2015-09-21 11:24:26 +0200 | [diff] [blame] | 1208 | .of_match_table = of_match_ptr(mrf24j40_of_match), |
Alan Ott | 3731a33 | 2012-09-02 15:44:13 +0000 | [diff] [blame] | 1209 | .name = "mrf24j40", |
Alan Ott | 3731a33 | 2012-09-02 15:44:13 +0000 | [diff] [blame] | 1210 | .owner = THIS_MODULE, |
| 1211 | }, |
| 1212 | .id_table = mrf24j40_ids, |
| 1213 | .probe = mrf24j40_probe, |
Bill Pemberton | bb1f460 | 2012-12-03 09:24:12 -0500 | [diff] [blame] | 1214 | .remove = mrf24j40_remove, |
Alan Ott | 3731a33 | 2012-09-02 15:44:13 +0000 | [diff] [blame] | 1215 | }; |
| 1216 | |
Wei Yongjun | 3d4a131 | 2013-04-08 20:34:44 +0000 | [diff] [blame] | 1217 | module_spi_driver(mrf24j40_driver); |
Alan Ott | 3731a33 | 2012-09-02 15:44:13 +0000 | [diff] [blame] | 1218 | |
| 1219 | MODULE_LICENSE("GPL"); |
| 1220 | MODULE_AUTHOR("Alan Ott"); |
| 1221 | MODULE_DESCRIPTION("MRF24J40 SPI 802.15.4 Controller Driver"); |