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Grant Likelyc103de22011-06-04 18:38:28 -06001/*
David Cohena0bbf032014-01-17 07:30:01 -08002 * Intel MID GPIO driver
Grant Likelyc103de22011-06-04 18:38:28 -06003 *
David Cohena0bbf032014-01-17 07:30:01 -08004 * Copyright (c) 2008-2014 Intel Corporation.
Alek Du8bf02612009-09-22 16:46:36 -07005 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
Alek Du8bf02612009-09-22 16:46:36 -070014 */
15
16/* Supports:
17 * Moorestown platform Langwell chip.
Alek Du8081c842010-05-26 14:42:25 -070018 * Medfield platform Penwell chip.
David Cohenf89a7682013-10-04 13:01:42 -070019 * Clovertrail platform Cloverview chip.
20 * Merrifield platform Tangier chip.
Alek Du8bf02612009-09-22 16:46:36 -070021 */
22
23#include <linux/module.h>
24#include <linux/pci.h>
Alan Cox72b43792010-10-27 15:33:23 -070025#include <linux/platform_device.h>
Alek Du8bf02612009-09-22 16:46:36 -070026#include <linux/kernel.h>
27#include <linux/delay.h>
28#include <linux/stddef.h>
29#include <linux/interrupt.h>
30#include <linux/init.h>
31#include <linux/irq.h>
32#include <linux/io.h>
33#include <linux/gpio.h>
Tejun Heo5a0e3ad2010-03-24 17:04:11 +090034#include <linux/slab.h>
Kristen Carlson Accardi78128032011-05-10 14:23:45 +010035#include <linux/pm_runtime.h>
Mika Westerberg465f2bd2012-05-02 11:15:50 +030036#include <linux/irqdomain.h>
Alek Du8bf02612009-09-22 16:46:36 -070037
David Cohenf89a7682013-10-04 13:01:42 -070038#define INTEL_MID_IRQ_TYPE_EDGE (1 << 0)
39#define INTEL_MID_IRQ_TYPE_LEVEL (1 << 1)
David Cohend56d6b32013-10-04 13:01:40 -070040
Alek Du8081c842010-05-26 14:42:25 -070041/*
42 * Langwell chip has 64 pins and thus there are 2 32bit registers to control
43 * each feature, while Penwell chip has 96 pins for each block, and need 3 32bit
44 * registers to control them, so we only define the order here instead of a
45 * structure, to get a bit offset for a pin (use GPDR as an example):
46 *
47 * nreg = ngpio / 32;
48 * reg = offset / 32;
49 * bit = offset % 32;
50 * reg_addr = reg_base + GPDR * nreg * 4 + reg * 4;
51 *
52 * so the bit of reg_addr is to control pin offset's GPDR feature
53*/
54
55enum GPIO_REG {
56 GPLR = 0, /* pin level read-only */
57 GPDR, /* pin direction */
58 GPSR, /* pin set */
59 GPCR, /* pin clear */
60 GRER, /* rising edge detect */
61 GFER, /* falling edge detect */
62 GEDR, /* edge detect result */
Adrian Hunter8c0f7b12011-10-03 14:36:07 +030063 GAFR, /* alt function */
Alek Du8bf02612009-09-22 16:46:36 -070064};
65
David Cohenf89a7682013-10-04 13:01:42 -070066/* intel_mid gpio driver data */
67struct intel_mid_gpio_ddata {
David Cohend56d6b32013-10-04 13:01:40 -070068 u16 ngpio; /* number of gpio pins */
69 u32 gplr_offset; /* offset of first GPLR register from base */
70 u32 flis_base; /* base address of FLIS registers */
71 u32 flis_len; /* length of FLIS registers */
72 u32 (*get_flis_offset)(int gpio);
73 u32 chip_irq_type; /* chip interrupt type */
74};
75
David Cohenf89a7682013-10-04 13:01:42 -070076struct intel_mid_gpio {
Alek Du8bf02612009-09-22 16:46:36 -070077 struct gpio_chip chip;
Andy Shevchenko64c8cbc2013-05-22 13:20:11 +030078 void __iomem *reg_base;
Alek Du8bf02612009-09-22 16:46:36 -070079 spinlock_t lock;
Kristen Carlson Accardi78128032011-05-10 14:23:45 +010080 struct pci_dev *pdev;
Mika Westerberg465f2bd2012-05-02 11:15:50 +030081 struct irq_domain *domain;
Alek Du8bf02612009-09-22 16:46:36 -070082};
83
David Cohenf89a7682013-10-04 13:01:42 -070084#define to_intel_gpio_priv(chip) container_of(chip, struct intel_mid_gpio, chip)
David Cohen46ebfbc2012-12-20 14:45:51 -080085
Alek Du8081c842010-05-26 14:42:25 -070086static void __iomem *gpio_reg(struct gpio_chip *chip, unsigned offset,
Andy Shevchenko611a4852013-05-22 13:20:14 +030087 enum GPIO_REG reg_type)
Alek Du8bf02612009-09-22 16:46:36 -070088{
David Cohenf89a7682013-10-04 13:01:42 -070089 struct intel_mid_gpio *priv = to_intel_gpio_priv(chip);
Alek Du8081c842010-05-26 14:42:25 -070090 unsigned nreg = chip->ngpio / 32;
Alek Du8bf02612009-09-22 16:46:36 -070091 u8 reg = offset / 32;
Alek Du8bf02612009-09-22 16:46:36 -070092
David Cohenf89a7682013-10-04 13:01:42 -070093 return priv->reg_base + reg_type * nreg * 4 + reg * 4;
Alek Du8081c842010-05-26 14:42:25 -070094}
95
Adrian Hunter8c0f7b12011-10-03 14:36:07 +030096static void __iomem *gpio_reg_2bit(struct gpio_chip *chip, unsigned offset,
97 enum GPIO_REG reg_type)
98{
David Cohenf89a7682013-10-04 13:01:42 -070099 struct intel_mid_gpio *priv = to_intel_gpio_priv(chip);
Adrian Hunter8c0f7b12011-10-03 14:36:07 +0300100 unsigned nreg = chip->ngpio / 32;
101 u8 reg = offset / 16;
Adrian Hunter8c0f7b12011-10-03 14:36:07 +0300102
David Cohenf89a7682013-10-04 13:01:42 -0700103 return priv->reg_base + reg_type * nreg * 4 + reg * 4;
Adrian Hunter8c0f7b12011-10-03 14:36:07 +0300104}
105
David Cohenf89a7682013-10-04 13:01:42 -0700106static int intel_gpio_request(struct gpio_chip *chip, unsigned offset)
Adrian Hunter8c0f7b12011-10-03 14:36:07 +0300107{
108 void __iomem *gafr = gpio_reg_2bit(chip, offset, GAFR);
109 u32 value = readl(gafr);
110 int shift = (offset % 16) << 1, af = (value >> shift) & 3;
111
112 if (af) {
113 value &= ~(3 << shift);
114 writel(value, gafr);
115 }
116 return 0;
117}
118
David Cohenf89a7682013-10-04 13:01:42 -0700119static int intel_gpio_get(struct gpio_chip *chip, unsigned offset)
Alek Du8081c842010-05-26 14:42:25 -0700120{
121 void __iomem *gplr = gpio_reg(chip, offset, GPLR);
122
Alek Du8bf02612009-09-22 16:46:36 -0700123 return readl(gplr) & BIT(offset % 32);
124}
125
David Cohenf89a7682013-10-04 13:01:42 -0700126static void intel_gpio_set(struct gpio_chip *chip, unsigned offset, int value)
Alek Du8bf02612009-09-22 16:46:36 -0700127{
Alek Du8bf02612009-09-22 16:46:36 -0700128 void __iomem *gpsr, *gpcr;
129
130 if (value) {
Alek Du8081c842010-05-26 14:42:25 -0700131 gpsr = gpio_reg(chip, offset, GPSR);
Alek Du8bf02612009-09-22 16:46:36 -0700132 writel(BIT(offset % 32), gpsr);
133 } else {
Alek Du8081c842010-05-26 14:42:25 -0700134 gpcr = gpio_reg(chip, offset, GPCR);
Alek Du8bf02612009-09-22 16:46:36 -0700135 writel(BIT(offset % 32), gpcr);
136 }
137}
138
David Cohenf89a7682013-10-04 13:01:42 -0700139static int intel_gpio_direction_input(struct gpio_chip *chip, unsigned offset)
Alek Du8bf02612009-09-22 16:46:36 -0700140{
David Cohenf89a7682013-10-04 13:01:42 -0700141 struct intel_mid_gpio *priv = to_intel_gpio_priv(chip);
Alek Du8081c842010-05-26 14:42:25 -0700142 void __iomem *gpdr = gpio_reg(chip, offset, GPDR);
Alek Du8bf02612009-09-22 16:46:36 -0700143 u32 value;
144 unsigned long flags;
Alek Du8bf02612009-09-22 16:46:36 -0700145
David Cohenf89a7682013-10-04 13:01:42 -0700146 if (priv->pdev)
147 pm_runtime_get(&priv->pdev->dev);
Kristen Carlson Accardi78128032011-05-10 14:23:45 +0100148
David Cohenf89a7682013-10-04 13:01:42 -0700149 spin_lock_irqsave(&priv->lock, flags);
Alek Du8bf02612009-09-22 16:46:36 -0700150 value = readl(gpdr);
151 value &= ~BIT(offset % 32);
152 writel(value, gpdr);
David Cohenf89a7682013-10-04 13:01:42 -0700153 spin_unlock_irqrestore(&priv->lock, flags);
Kristen Carlson Accardi78128032011-05-10 14:23:45 +0100154
David Cohenf89a7682013-10-04 13:01:42 -0700155 if (priv->pdev)
156 pm_runtime_put(&priv->pdev->dev);
Kristen Carlson Accardi78128032011-05-10 14:23:45 +0100157
Alek Du8bf02612009-09-22 16:46:36 -0700158 return 0;
159}
160
David Cohenf89a7682013-10-04 13:01:42 -0700161static int intel_gpio_direction_output(struct gpio_chip *chip,
Alek Du8bf02612009-09-22 16:46:36 -0700162 unsigned offset, int value)
163{
David Cohenf89a7682013-10-04 13:01:42 -0700164 struct intel_mid_gpio *priv = to_intel_gpio_priv(chip);
Alek Du8081c842010-05-26 14:42:25 -0700165 void __iomem *gpdr = gpio_reg(chip, offset, GPDR);
Alek Du8bf02612009-09-22 16:46:36 -0700166 unsigned long flags;
Alek Du8bf02612009-09-22 16:46:36 -0700167
David Cohenf89a7682013-10-04 13:01:42 -0700168 intel_gpio_set(chip, offset, value);
Kristen Carlson Accardi78128032011-05-10 14:23:45 +0100169
David Cohenf89a7682013-10-04 13:01:42 -0700170 if (priv->pdev)
171 pm_runtime_get(&priv->pdev->dev);
Kristen Carlson Accardi78128032011-05-10 14:23:45 +0100172
David Cohenf89a7682013-10-04 13:01:42 -0700173 spin_lock_irqsave(&priv->lock, flags);
Alek Du8bf02612009-09-22 16:46:36 -0700174 value = readl(gpdr);
Justin P. Mattock6eab04a2011-04-08 19:49:08 -0700175 value |= BIT(offset % 32);
Alek Du8bf02612009-09-22 16:46:36 -0700176 writel(value, gpdr);
David Cohenf89a7682013-10-04 13:01:42 -0700177 spin_unlock_irqrestore(&priv->lock, flags);
Kristen Carlson Accardi78128032011-05-10 14:23:45 +0100178
David Cohenf89a7682013-10-04 13:01:42 -0700179 if (priv->pdev)
180 pm_runtime_put(&priv->pdev->dev);
Kristen Carlson Accardi78128032011-05-10 14:23:45 +0100181
Alek Du8bf02612009-09-22 16:46:36 -0700182 return 0;
183}
184
David Cohenf89a7682013-10-04 13:01:42 -0700185static int intel_gpio_to_irq(struct gpio_chip *chip, unsigned offset)
Alek Du8bf02612009-09-22 16:46:36 -0700186{
David Cohenf89a7682013-10-04 13:01:42 -0700187 struct intel_mid_gpio *priv = to_intel_gpio_priv(chip);
188 return irq_create_mapping(priv->domain, offset);
Alek Du8bf02612009-09-22 16:46:36 -0700189}
190
David Cohenf89a7682013-10-04 13:01:42 -0700191static int intel_mid_irq_type(struct irq_data *d, unsigned type)
Alek Du8bf02612009-09-22 16:46:36 -0700192{
David Cohenf89a7682013-10-04 13:01:42 -0700193 struct intel_mid_gpio *priv = irq_data_get_irq_chip_data(d);
Mika Westerberg465f2bd2012-05-02 11:15:50 +0300194 u32 gpio = irqd_to_hwirq(d);
Alek Du8bf02612009-09-22 16:46:36 -0700195 unsigned long flags;
196 u32 value;
David Cohenf89a7682013-10-04 13:01:42 -0700197 void __iomem *grer = gpio_reg(&priv->chip, gpio, GRER);
198 void __iomem *gfer = gpio_reg(&priv->chip, gpio, GFER);
Alek Du8bf02612009-09-22 16:46:36 -0700199
David Cohenf89a7682013-10-04 13:01:42 -0700200 if (gpio >= priv->chip.ngpio)
Alek Du8bf02612009-09-22 16:46:36 -0700201 return -EINVAL;
Kristen Carlson Accardi78128032011-05-10 14:23:45 +0100202
David Cohenf89a7682013-10-04 13:01:42 -0700203 if (priv->pdev)
204 pm_runtime_get(&priv->pdev->dev);
Kristen Carlson Accardi78128032011-05-10 14:23:45 +0100205
David Cohenf89a7682013-10-04 13:01:42 -0700206 spin_lock_irqsave(&priv->lock, flags);
Alek Du8bf02612009-09-22 16:46:36 -0700207 if (type & IRQ_TYPE_EDGE_RISING)
208 value = readl(grer) | BIT(gpio % 32);
209 else
210 value = readl(grer) & (~BIT(gpio % 32));
211 writel(value, grer);
212
213 if (type & IRQ_TYPE_EDGE_FALLING)
214 value = readl(gfer) | BIT(gpio % 32);
215 else
216 value = readl(gfer) & (~BIT(gpio % 32));
217 writel(value, gfer);
David Cohenf89a7682013-10-04 13:01:42 -0700218 spin_unlock_irqrestore(&priv->lock, flags);
Alek Du8bf02612009-09-22 16:46:36 -0700219
David Cohenf89a7682013-10-04 13:01:42 -0700220 if (priv->pdev)
221 pm_runtime_put(&priv->pdev->dev);
Kristen Carlson Accardi78128032011-05-10 14:23:45 +0100222
Alek Du8bf02612009-09-22 16:46:36 -0700223 return 0;
Andrew Mortonfd0574c2010-10-27 15:33:22 -0700224}
Alek Du8bf02612009-09-22 16:46:36 -0700225
David Cohenf89a7682013-10-04 13:01:42 -0700226static void intel_mid_irq_unmask(struct irq_data *d)
Alek Du8bf02612009-09-22 16:46:36 -0700227{
Andrew Mortonfd0574c2010-10-27 15:33:22 -0700228}
Alek Du8bf02612009-09-22 16:46:36 -0700229
David Cohenf89a7682013-10-04 13:01:42 -0700230static void intel_mid_irq_mask(struct irq_data *d)
Alek Du8bf02612009-09-22 16:46:36 -0700231{
Andrew Mortonfd0574c2010-10-27 15:33:22 -0700232}
Alek Du8bf02612009-09-22 16:46:36 -0700233
Linus Walleij57ef0422014-03-14 18:16:20 +0100234static int intel_mid_irq_reqres(struct irq_data *d)
Linus Walleijaa6baa72013-11-20 15:24:32 +0100235{
236 struct intel_mid_gpio *priv = irq_data_get_irq_chip_data(d);
237
Linus Walleij57ef0422014-03-14 18:16:20 +0100238 if (gpio_lock_as_irq(&priv->chip, irqd_to_hwirq(d))) {
Linus Walleijaa6baa72013-11-20 15:24:32 +0100239 dev_err(priv->chip.dev,
240 "unable to lock HW IRQ %lu for IRQ\n",
241 irqd_to_hwirq(d));
Linus Walleij57ef0422014-03-14 18:16:20 +0100242 return -EINVAL;
243 }
Linus Walleijaa6baa72013-11-20 15:24:32 +0100244 return 0;
245}
246
Linus Walleij57ef0422014-03-14 18:16:20 +0100247static void intel_mid_irq_relres(struct irq_data *d)
Linus Walleijaa6baa72013-11-20 15:24:32 +0100248{
249 struct intel_mid_gpio *priv = irq_data_get_irq_chip_data(d);
250
Linus Walleijaa6baa72013-11-20 15:24:32 +0100251 gpio_unlock_as_irq(&priv->chip, irqd_to_hwirq(d));
252}
253
David Cohenf89a7682013-10-04 13:01:42 -0700254static struct irq_chip intel_mid_irqchip = {
255 .name = "INTEL_MID-GPIO",
256 .irq_mask = intel_mid_irq_mask,
257 .irq_unmask = intel_mid_irq_unmask,
258 .irq_set_type = intel_mid_irq_type,
Linus Walleij57ef0422014-03-14 18:16:20 +0100259 .irq_request_resources = intel_mid_irq_reqres,
260 .irq_release_resources = intel_mid_irq_relres,
Alek Du8bf02612009-09-22 16:46:36 -0700261};
262
David Cohenf89a7682013-10-04 13:01:42 -0700263static const struct intel_mid_gpio_ddata gpio_lincroft = {
David Cohend56d6b32013-10-04 13:01:40 -0700264 .ngpio = 64,
265};
266
David Cohenf89a7682013-10-04 13:01:42 -0700267static const struct intel_mid_gpio_ddata gpio_penwell_aon = {
David Cohend56d6b32013-10-04 13:01:40 -0700268 .ngpio = 96,
David Cohenf89a7682013-10-04 13:01:42 -0700269 .chip_irq_type = INTEL_MID_IRQ_TYPE_EDGE,
David Cohend56d6b32013-10-04 13:01:40 -0700270};
271
David Cohenf89a7682013-10-04 13:01:42 -0700272static const struct intel_mid_gpio_ddata gpio_penwell_core = {
David Cohend56d6b32013-10-04 13:01:40 -0700273 .ngpio = 96,
David Cohenf89a7682013-10-04 13:01:42 -0700274 .chip_irq_type = INTEL_MID_IRQ_TYPE_EDGE,
David Cohend56d6b32013-10-04 13:01:40 -0700275};
276
David Cohenf89a7682013-10-04 13:01:42 -0700277static const struct intel_mid_gpio_ddata gpio_cloverview_aon = {
David Cohend56d6b32013-10-04 13:01:40 -0700278 .ngpio = 96,
David Cohenf89a7682013-10-04 13:01:42 -0700279 .chip_irq_type = INTEL_MID_IRQ_TYPE_EDGE | INTEL_MID_IRQ_TYPE_LEVEL,
David Cohend56d6b32013-10-04 13:01:40 -0700280};
281
David Cohenf89a7682013-10-04 13:01:42 -0700282static const struct intel_mid_gpio_ddata gpio_cloverview_core = {
David Cohend56d6b32013-10-04 13:01:40 -0700283 .ngpio = 96,
David Cohenf89a7682013-10-04 13:01:42 -0700284 .chip_irq_type = INTEL_MID_IRQ_TYPE_EDGE,
David Cohend56d6b32013-10-04 13:01:40 -0700285};
286
David Cohenf89a7682013-10-04 13:01:42 -0700287static const struct intel_mid_gpio_ddata gpio_tangier = {
David Cohend56d6b32013-10-04 13:01:40 -0700288 .ngpio = 192,
289 .gplr_offset = 4,
290 .flis_base = 0xff0c0000,
291 .flis_len = 0x8000,
292 .get_flis_offset = NULL,
David Cohenf89a7682013-10-04 13:01:42 -0700293 .chip_irq_type = INTEL_MID_IRQ_TYPE_EDGE,
David Cohend56d6b32013-10-04 13:01:40 -0700294};
295
Jingoo Han14f4a882013-12-03 08:08:45 +0900296static const struct pci_device_id intel_gpio_ids[] = {
David Cohend56d6b32013-10-04 13:01:40 -0700297 {
298 /* Lincroft */
299 PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x080f),
300 .driver_data = (kernel_ulong_t)&gpio_lincroft,
301 },
302 {
303 /* Penwell AON */
304 PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x081f),
305 .driver_data = (kernel_ulong_t)&gpio_penwell_aon,
306 },
307 {
308 /* Penwell Core */
309 PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x081a),
310 .driver_data = (kernel_ulong_t)&gpio_penwell_core,
311 },
312 {
313 /* Cloverview Aon */
314 PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x08eb),
315 .driver_data = (kernel_ulong_t)&gpio_cloverview_aon,
316 },
317 {
318 /* Cloverview Core */
319 PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x08f7),
320 .driver_data = (kernel_ulong_t)&gpio_cloverview_core,
321 },
322 {
323 /* Tangier */
324 PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x1199),
325 .driver_data = (kernel_ulong_t)&gpio_tangier,
326 },
327 { 0 }
Alek Du8bf02612009-09-22 16:46:36 -0700328};
David Cohenf89a7682013-10-04 13:01:42 -0700329MODULE_DEVICE_TABLE(pci, intel_gpio_ids);
Alek Du8bf02612009-09-22 16:46:36 -0700330
David Cohenf89a7682013-10-04 13:01:42 -0700331static void intel_mid_irq_handler(unsigned irq, struct irq_desc *desc)
Alek Du8bf02612009-09-22 16:46:36 -0700332{
Thomas Gleixner20e2aa92011-03-17 19:32:49 +0000333 struct irq_data *data = irq_desc_get_irq_data(desc);
David Cohenf89a7682013-10-04 13:01:42 -0700334 struct intel_mid_gpio *priv = irq_data_get_irq_handler_data(data);
Thomas Gleixner20e2aa92011-03-17 19:32:49 +0000335 struct irq_chip *chip = irq_data_get_irq_chip(data);
Thomas Gleixner84bead62011-03-17 19:32:58 +0000336 u32 base, gpio, mask;
Thomas Gleixner732063b2011-03-17 19:32:55 +0000337 unsigned long pending;
Alek Du8bf02612009-09-22 16:46:36 -0700338 void __iomem *gedr;
Alek Du8bf02612009-09-22 16:46:36 -0700339
340 /* check GPIO controller to check which pin triggered the interrupt */
David Cohenf89a7682013-10-04 13:01:42 -0700341 for (base = 0; base < priv->chip.ngpio; base += 32) {
342 gedr = gpio_reg(&priv->chip, base, GEDR);
Mika Westerbergc8f925b2012-05-10 13:01:22 +0300343 while ((pending = readl(gedr))) {
Mathias Nyman2345b202011-07-08 10:02:18 +0100344 gpio = __ffs(pending);
Thomas Gleixner84bead62011-03-17 19:32:58 +0000345 mask = BIT(gpio);
Thomas Gleixner84bead62011-03-17 19:32:58 +0000346 /* Clear before handling so we can't lose an edge */
347 writel(mask, gedr);
David Cohenf89a7682013-10-04 13:01:42 -0700348 generic_handle_irq(irq_find_mapping(priv->domain,
Mika Westerberg465f2bd2012-05-02 11:15:50 +0300349 base + gpio));
Thomas Gleixner732063b2011-03-17 19:32:55 +0000350 }
Alek Du8bf02612009-09-22 16:46:36 -0700351 }
Feng Tang0766d202011-01-25 15:07:15 -0800352
Thomas Gleixner20e2aa92011-03-17 19:32:49 +0000353 chip->irq_eoi(data);
Alek Du8bf02612009-09-22 16:46:36 -0700354}
355
David Cohenf89a7682013-10-04 13:01:42 -0700356static void intel_mid_irq_init_hw(struct intel_mid_gpio *priv)
Mika Westerbergf5f93112012-04-05 12:15:17 +0300357{
358 void __iomem *reg;
359 unsigned base;
360
David Cohenf89a7682013-10-04 13:01:42 -0700361 for (base = 0; base < priv->chip.ngpio; base += 32) {
Mika Westerbergf5f93112012-04-05 12:15:17 +0300362 /* Clear the rising-edge detect register */
David Cohenf89a7682013-10-04 13:01:42 -0700363 reg = gpio_reg(&priv->chip, base, GRER);
Mika Westerbergf5f93112012-04-05 12:15:17 +0300364 writel(0, reg);
365 /* Clear the falling-edge detect register */
David Cohenf89a7682013-10-04 13:01:42 -0700366 reg = gpio_reg(&priv->chip, base, GFER);
Mika Westerbergf5f93112012-04-05 12:15:17 +0300367 writel(0, reg);
368 /* Clear the edge detect status register */
David Cohenf89a7682013-10-04 13:01:42 -0700369 reg = gpio_reg(&priv->chip, base, GEDR);
Mika Westerbergf5f93112012-04-05 12:15:17 +0300370 writel(~0, reg);
371 }
372}
373
Linus Walleijba519dd2013-10-11 19:27:02 +0200374static int intel_gpio_irq_map(struct irq_domain *d, unsigned int irq,
375 irq_hw_number_t hwirq)
Mika Westerberg465f2bd2012-05-02 11:15:50 +0300376{
David Cohenf89a7682013-10-04 13:01:42 -0700377 struct intel_mid_gpio *priv = d->host_data;
Mika Westerberg465f2bd2012-05-02 11:15:50 +0300378
Linus Walleije5428a62013-11-26 14:28:32 +0100379 irq_set_chip_and_handler(irq, &intel_mid_irqchip, handle_simple_irq);
Linus Walleijba519dd2013-10-11 19:27:02 +0200380 irq_set_chip_data(irq, priv);
381 irq_set_irq_type(irq, IRQ_TYPE_NONE);
Mika Westerberg465f2bd2012-05-02 11:15:50 +0300382
383 return 0;
384}
385
David Cohenf89a7682013-10-04 13:01:42 -0700386static const struct irq_domain_ops intel_gpio_irq_ops = {
387 .map = intel_gpio_irq_map,
Mika Westerberg465f2bd2012-05-02 11:15:50 +0300388 .xlate = irq_domain_xlate_twocell,
389};
390
David Cohenf89a7682013-10-04 13:01:42 -0700391static int intel_gpio_runtime_idle(struct device *dev)
Kristen Carlson Accardi78128032011-05-10 14:23:45 +0100392{
xinhui.pan84a34572014-01-31 13:08:01 -0800393 int err = pm_schedule_suspend(dev, 500);
394 return err ?: -EBUSY;
Kristen Carlson Accardi78128032011-05-10 14:23:45 +0100395}
396
David Cohenf89a7682013-10-04 13:01:42 -0700397static const struct dev_pm_ops intel_gpio_pm_ops = {
398 SET_RUNTIME_PM_OPS(NULL, NULL, intel_gpio_runtime_idle)
Kristen Carlson Accardi78128032011-05-10 14:23:45 +0100399};
400
David Cohenf89a7682013-10-04 13:01:42 -0700401static int intel_gpio_probe(struct pci_dev *pdev,
Andy Shevchenko64c8cbc2013-05-22 13:20:11 +0300402 const struct pci_device_id *id)
Alek Du8bf02612009-09-22 16:46:36 -0700403{
Andy Shevchenko64c8cbc2013-05-22 13:20:11 +0300404 void __iomem *base;
David Cohenf89a7682013-10-04 13:01:42 -0700405 struct intel_mid_gpio *priv;
Alek Du8bf02612009-09-22 16:46:36 -0700406 u32 gpio_base;
David Cohen2519f9a2013-05-06 16:11:03 -0700407 u32 irq_base;
Julia Lawalld6a2b7b2012-08-05 11:52:34 +0200408 int retval;
David Cohenf89a7682013-10-04 13:01:42 -0700409 struct intel_mid_gpio_ddata *ddata =
410 (struct intel_mid_gpio_ddata *)id->driver_data;
Alek Du8bf02612009-09-22 16:46:36 -0700411
Andy Shevchenko786e07e2013-05-22 13:20:12 +0300412 retval = pcim_enable_device(pdev);
Alek Du8bf02612009-09-22 16:46:36 -0700413 if (retval)
Mika Westerberg8302c742012-04-05 12:15:15 +0300414 return retval;
Alek Du8bf02612009-09-22 16:46:36 -0700415
Andy Shevchenko786e07e2013-05-22 13:20:12 +0300416 retval = pcim_iomap_regions(pdev, 1 << 0 | 1 << 1, pci_name(pdev));
Alek Du8bf02612009-09-22 16:46:36 -0700417 if (retval) {
Andy Shevchenko786e07e2013-05-22 13:20:12 +0300418 dev_err(&pdev->dev, "I/O memory mapping error\n");
419 return retval;
Alek Du8bf02612009-09-22 16:46:36 -0700420 }
Andy Shevchenko786e07e2013-05-22 13:20:12 +0300421
422 base = pcim_iomap_table(pdev)[1];
Andy Shevchenko64c8cbc2013-05-22 13:20:11 +0300423
424 irq_base = readl(base);
425 gpio_base = readl(sizeof(u32) + base);
426
Alek Du8bf02612009-09-22 16:46:36 -0700427 /* release the IO mapping, since we already get the info from bar1 */
Andy Shevchenko786e07e2013-05-22 13:20:12 +0300428 pcim_iounmap_regions(pdev, 1 << 1);
Alek Du8bf02612009-09-22 16:46:36 -0700429
David Cohenf89a7682013-10-04 13:01:42 -0700430 priv = devm_kzalloc(&pdev->dev, sizeof(*priv), GFP_KERNEL);
431 if (!priv) {
Andy Shevchenko8aca1192013-05-22 13:20:13 +0300432 dev_err(&pdev->dev, "can't allocate chip data\n");
Andy Shevchenko786e07e2013-05-22 13:20:12 +0300433 return -ENOMEM;
Alek Du8bf02612009-09-22 16:46:36 -0700434 }
Mika Westerbergb3e35af2012-04-05 12:15:16 +0300435
David Cohenf89a7682013-10-04 13:01:42 -0700436 priv->reg_base = pcim_iomap_table(pdev)[0];
437 priv->chip.label = dev_name(&pdev->dev);
Linus Walleijaa6baa72013-11-20 15:24:32 +0100438 priv->chip.dev = &pdev->dev;
David Cohenf89a7682013-10-04 13:01:42 -0700439 priv->chip.request = intel_gpio_request;
440 priv->chip.direction_input = intel_gpio_direction_input;
441 priv->chip.direction_output = intel_gpio_direction_output;
442 priv->chip.get = intel_gpio_get;
443 priv->chip.set = intel_gpio_set;
444 priv->chip.to_irq = intel_gpio_to_irq;
445 priv->chip.base = gpio_base;
446 priv->chip.ngpio = ddata->ngpio;
Linus Walleij9fb1f392013-12-04 14:42:46 +0100447 priv->chip.can_sleep = false;
David Cohenf89a7682013-10-04 13:01:42 -0700448 priv->pdev = pdev;
David Cohen2519f9a2013-05-06 16:11:03 -0700449
David Cohenf89a7682013-10-04 13:01:42 -0700450 spin_lock_init(&priv->lock);
Andy Shevchenkoaeb168f2013-05-22 13:20:10 +0300451
David Cohenf89a7682013-10-04 13:01:42 -0700452 priv->domain = irq_domain_add_simple(pdev->dev.of_node, ddata->ngpio,
453 irq_base, &intel_gpio_irq_ops, priv);
454 if (!priv->domain)
Andy Shevchenko786e07e2013-05-22 13:20:12 +0300455 return -ENOMEM;
David Cohen2519f9a2013-05-06 16:11:03 -0700456
David Cohenf89a7682013-10-04 13:01:42 -0700457 pci_set_drvdata(pdev, priv);
458 retval = gpiochip_add(&priv->chip);
Alek Du8bf02612009-09-22 16:46:36 -0700459 if (retval) {
Andy Shevchenko8aca1192013-05-22 13:20:13 +0300460 dev_err(&pdev->dev, "gpiochip_add error %d\n", retval);
Andy Shevchenko786e07e2013-05-22 13:20:12 +0300461 return retval;
Alek Du8bf02612009-09-22 16:46:36 -0700462 }
Mika Westerbergf5f93112012-04-05 12:15:17 +0300463
David Cohenf89a7682013-10-04 13:01:42 -0700464 intel_mid_irq_init_hw(priv);
Mika Westerbergf5f93112012-04-05 12:15:17 +0300465
David Cohenf89a7682013-10-04 13:01:42 -0700466 irq_set_handler_data(pdev->irq, priv);
467 irq_set_chained_handler(pdev->irq, intel_mid_irq_handler);
Alek Du8bf02612009-09-22 16:46:36 -0700468
Kristen Carlson Accardi78128032011-05-10 14:23:45 +0100469 pm_runtime_put_noidle(&pdev->dev);
470 pm_runtime_allow(&pdev->dev);
471
Mika Westerberg8302c742012-04-05 12:15:15 +0300472 return 0;
Alek Du8bf02612009-09-22 16:46:36 -0700473}
474
David Cohenf89a7682013-10-04 13:01:42 -0700475static struct pci_driver intel_gpio_driver = {
476 .name = "intel_mid_gpio",
477 .id_table = intel_gpio_ids,
478 .probe = intel_gpio_probe,
Kristen Carlson Accardi78128032011-05-10 14:23:45 +0100479 .driver = {
David Cohenf89a7682013-10-04 13:01:42 -0700480 .pm = &intel_gpio_pm_ops,
Kristen Carlson Accardi78128032011-05-10 14:23:45 +0100481 },
Alek Du8bf02612009-09-22 16:46:36 -0700482};
483
David Cohenf89a7682013-10-04 13:01:42 -0700484static int __init intel_gpio_init(void)
Alek Du8bf02612009-09-22 16:46:36 -0700485{
David Cohenf89a7682013-10-04 13:01:42 -0700486 return pci_register_driver(&intel_gpio_driver);
Alek Du8bf02612009-09-22 16:46:36 -0700487}
488
David Cohenf89a7682013-10-04 13:01:42 -0700489device_initcall(intel_gpio_init);