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Thomas Petazzoni9ae6f742012-06-13 19:01:28 +02001/*
2 * Marvell Armada 370 and Armada XP SoC IRQ handling
3 *
4 * Copyright (C) 2012 Marvell
5 *
6 * Lior Amsalem <alior@marvell.com>
7 * Gregory CLEMENT <gregory.clement@free-electrons.com>
8 * Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
9 * Ben Dooks <ben.dooks@codethink.co.uk>
10 *
11 * This file is licensed under the terms of the GNU General Public
12 * License version 2. This program is licensed "as is" without any
13 * warranty of any kind, whether express or implied.
14 */
15
16#include <linux/kernel.h>
17#include <linux/module.h>
18#include <linux/init.h>
19#include <linux/irq.h>
20#include <linux/interrupt.h>
Joel Porquet41a83e02015-07-07 17:11:46 -040021#include <linux/irqchip.h>
Ezequiel Garciabc69b8a2014-02-10 17:00:02 -030022#include <linux/irqchip/chained_irq.h>
Thomas Petazzonid7df84b2014-04-14 15:54:02 +020023#include <linux/cpu.h>
Thomas Petazzoni9ae6f742012-06-13 19:01:28 +020024#include <linux/io.h>
25#include <linux/of_address.h>
26#include <linux/of_irq.h>
Thomas Petazzoni31f614e2013-08-09 22:27:11 +020027#include <linux/of_pci.h>
Thomas Petazzoni9ae6f742012-06-13 19:01:28 +020028#include <linux/irqdomain.h>
Thomas Petazzoni31f614e2013-08-09 22:27:11 +020029#include <linux/slab.h>
Thomas Petazzoni0f077eb2014-11-21 17:00:00 +010030#include <linux/syscore_ops.h>
Thomas Petazzoni31f614e2013-08-09 22:27:11 +020031#include <linux/msi.h>
Thomas Petazzoni9ae6f742012-06-13 19:01:28 +020032#include <asm/mach/arch.h>
33#include <asm/exception.h>
Gregory CLEMENT344e8732012-08-02 11:19:12 +030034#include <asm/smp_plat.h>
Thomas Petazzoni9339d432013-04-09 23:26:15 +020035#include <asm/mach/irq.h>
36
Thomas Petazzoni9ae6f742012-06-13 19:01:28 +020037/* Interrupt Controller Registers Map */
38#define ARMADA_370_XP_INT_SET_MASK_OFFS (0x48)
39#define ARMADA_370_XP_INT_CLEAR_MASK_OFFS (0x4C)
Maxime Ripard28da06d2015-03-03 11:43:16 +010040#define ARMADA_370_XP_INT_FABRIC_MASK_OFFS (0x54)
41#define ARMADA_370_XP_INT_CAUSE_PERF(cpu) (1 << cpu)
Thomas Petazzoni9ae6f742012-06-13 19:01:28 +020042
Ben Dooksf3e16cc2012-06-04 18:50:12 +020043#define ARMADA_370_XP_INT_CONTROL (0x00)
Thomas Petazzoni9ae6f742012-06-13 19:01:28 +020044#define ARMADA_370_XP_INT_SET_ENABLE_OFFS (0x30)
45#define ARMADA_370_XP_INT_CLEAR_ENABLE_OFFS (0x34)
Gregory CLEMENT3202bf02012-12-05 21:43:23 +010046#define ARMADA_370_XP_INT_SOURCE_CTL(irq) (0x100 + irq*4)
Thomas Gleixner8cc3cfc2014-03-04 20:43:41 +000047#define ARMADA_370_XP_INT_SOURCE_CPU_MASK 0xF
Grzegorz Jaszczyk758e8362014-09-25 13:17:19 +020048#define ARMADA_370_XP_INT_IRQ_FIQ_MASK(cpuid) ((BIT(0) | BIT(8)) << cpuid)
Thomas Petazzoni9ae6f742012-06-13 19:01:28 +020049
50#define ARMADA_370_XP_CPU_INTACK_OFFS (0x44)
Ezequiel Garciabc69b8a2014-02-10 17:00:02 -030051#define ARMADA_375_PPI_CAUSE (0x10)
Thomas Petazzoni9ae6f742012-06-13 19:01:28 +020052
Gregory CLEMENT344e8732012-08-02 11:19:12 +030053#define ARMADA_370_XP_SW_TRIG_INT_OFFS (0x4)
54#define ARMADA_370_XP_IN_DRBEL_MSK_OFFS (0xc)
55#define ARMADA_370_XP_IN_DRBEL_CAUSE_OFFS (0x8)
56
Gregory CLEMENT3202bf02012-12-05 21:43:23 +010057#define ARMADA_370_XP_MAX_PER_CPU_IRQS (28)
58
Thomas Petazzoni5ec69012013-04-09 23:26:17 +020059#define IPI_DOORBELL_START (0)
60#define IPI_DOORBELL_END (8)
61#define IPI_DOORBELL_MASK 0xFF
Thomas Petazzoni31f614e2013-08-09 22:27:11 +020062#define PCI_MSI_DOORBELL_START (16)
63#define PCI_MSI_DOORBELL_NR (16)
64#define PCI_MSI_DOORBELL_END (32)
65#define PCI_MSI_DOORBELL_MASK 0xFFFF0000
Gregory CLEMENT344e8732012-08-02 11:19:12 +030066
Thomas Petazzoni9ae6f742012-06-13 19:01:28 +020067static void __iomem *per_cpu_int_base;
68static void __iomem *main_int_base;
69static struct irq_domain *armada_370_xp_mpic_domain;
Thomas Petazzoni0f077eb2014-11-21 17:00:00 +010070static u32 doorbell_mask_reg;
Maxime Ripard5724be82015-03-03 11:27:23 +010071static int parent_irq;
Thomas Petazzoni31f614e2013-08-09 22:27:11 +020072#ifdef CONFIG_PCI_MSI
73static struct irq_domain *armada_370_xp_msi_domain;
Thomas Petazzonifcc392d2016-02-10 15:46:57 +010074static struct irq_domain *armada_370_xp_msi_inner_domain;
Thomas Petazzoni31f614e2013-08-09 22:27:11 +020075static DECLARE_BITMAP(msi_used, PCI_MSI_DOORBELL_NR);
76static DEFINE_MUTEX(msi_used_lock);
77static phys_addr_t msi_doorbell_addr;
78#endif
Thomas Petazzoni9ae6f742012-06-13 19:01:28 +020079
Ezequiel Garcia2c299de2015-03-03 11:43:15 +010080static inline bool is_percpu_irq(irq_hw_number_t irq)
81{
Maxime Ripard080481f92015-09-25 18:09:34 +020082 if (irq <= ARMADA_370_XP_MAX_PER_CPU_IRQS)
Ezequiel Garcia2c299de2015-03-03 11:43:15 +010083 return true;
Maxime Ripard080481f92015-09-25 18:09:34 +020084
85 return false;
Ezequiel Garcia2c299de2015-03-03 11:43:15 +010086}
87
Gregory CLEMENT3202bf02012-12-05 21:43:23 +010088/*
89 * In SMP mode:
90 * For shared global interrupts, mask/unmask global enable bit
Marek Belisko097ef182013-03-15 23:34:04 +010091 * For CPU interrupts, mask/unmask the calling CPU's bit
Gregory CLEMENT3202bf02012-12-05 21:43:23 +010092 */
Thomas Petazzoni9ae6f742012-06-13 19:01:28 +020093static void armada_370_xp_irq_mask(struct irq_data *d)
94{
Gregory CLEMENT3202bf02012-12-05 21:43:23 +010095 irq_hw_number_t hwirq = irqd_to_hwirq(d);
96
Ezequiel Garcia2c299de2015-03-03 11:43:15 +010097 if (!is_percpu_irq(hwirq))
Gregory CLEMENT3202bf02012-12-05 21:43:23 +010098 writel(hwirq, main_int_base +
99 ARMADA_370_XP_INT_CLEAR_ENABLE_OFFS);
100 else
101 writel(hwirq, per_cpu_int_base +
102 ARMADA_370_XP_INT_SET_MASK_OFFS);
Thomas Petazzoni9ae6f742012-06-13 19:01:28 +0200103}
104
105static void armada_370_xp_irq_unmask(struct irq_data *d)
106{
Gregory CLEMENT3202bf02012-12-05 21:43:23 +0100107 irq_hw_number_t hwirq = irqd_to_hwirq(d);
108
Ezequiel Garcia2c299de2015-03-03 11:43:15 +0100109 if (!is_percpu_irq(hwirq))
Gregory CLEMENT3202bf02012-12-05 21:43:23 +0100110 writel(hwirq, main_int_base +
111 ARMADA_370_XP_INT_SET_ENABLE_OFFS);
112 else
113 writel(hwirq, per_cpu_int_base +
114 ARMADA_370_XP_INT_CLEAR_MASK_OFFS);
Thomas Petazzoni9ae6f742012-06-13 19:01:28 +0200115}
116
Thomas Petazzoni31f614e2013-08-09 22:27:11 +0200117#ifdef CONFIG_PCI_MSI
118
Thomas Petazzonifcc392d2016-02-10 15:46:57 +0100119static struct irq_chip armada_370_xp_msi_irq_chip = {
Thomas Petazzonif692a172016-02-10 15:46:59 +0100120 .name = "MPIC MSI",
Thomas Petazzonifcc392d2016-02-10 15:46:57 +0100121 .irq_mask = pci_msi_mask_irq,
122 .irq_unmask = pci_msi_unmask_irq,
123};
124
125static struct msi_domain_info armada_370_xp_msi_domain_info = {
Thomas Petazzonia71b9412016-02-10 15:47:00 +0100126 .flags = (MSI_FLAG_USE_DEF_DOM_OPS | MSI_FLAG_USE_DEF_CHIP_OPS |
127 MSI_FLAG_MULTI_PCI_MSI),
Thomas Petazzonifcc392d2016-02-10 15:46:57 +0100128 .chip = &armada_370_xp_msi_irq_chip,
129};
130
131static void armada_370_xp_compose_msi_msg(struct irq_data *data, struct msi_msg *msg)
132{
133 msg->address_lo = lower_32_bits(msi_doorbell_addr);
134 msg->address_hi = upper_32_bits(msi_doorbell_addr);
135 msg->data = 0xf00 | (data->hwirq + PCI_MSI_DOORBELL_START);
136}
137
138static int armada_370_xp_msi_set_affinity(struct irq_data *irq_data,
139 const struct cpumask *mask, bool force)
140{
141 return -EINVAL;
142}
143
144static struct irq_chip armada_370_xp_msi_bottom_irq_chip = {
Thomas Petazzonif692a172016-02-10 15:46:59 +0100145 .name = "MPIC MSI",
Thomas Petazzonifcc392d2016-02-10 15:46:57 +0100146 .irq_compose_msi_msg = armada_370_xp_compose_msi_msg,
147 .irq_set_affinity = armada_370_xp_msi_set_affinity,
148};
149
150static int armada_370_xp_msi_alloc(struct irq_domain *domain, unsigned int virq,
151 unsigned int nr_irqs, void *args)
Thomas Petazzoni31f614e2013-08-09 22:27:11 +0200152{
Thomas Petazzonia71b9412016-02-10 15:47:00 +0100153 int hwirq, i;
Thomas Petazzoni31f614e2013-08-09 22:27:11 +0200154
155 mutex_lock(&msi_used_lock);
Thomas Petazzonia71b9412016-02-10 15:47:00 +0100156
157 hwirq = bitmap_find_next_zero_area(msi_used, PCI_MSI_DOORBELL_NR,
158 0, nr_irqs, 0);
Thomas Petazzonifcc392d2016-02-10 15:46:57 +0100159 if (hwirq >= PCI_MSI_DOORBELL_NR) {
160 mutex_unlock(&msi_used_lock);
161 return -ENOSPC;
162 }
163
Thomas Petazzonia71b9412016-02-10 15:47:00 +0100164 bitmap_set(msi_used, hwirq, nr_irqs);
Thomas Petazzoni31f614e2013-08-09 22:27:11 +0200165 mutex_unlock(&msi_used_lock);
166
Thomas Petazzonia71b9412016-02-10 15:47:00 +0100167 for (i = 0; i < nr_irqs; i++) {
168 irq_domain_set_info(domain, virq + i, hwirq + i,
169 &armada_370_xp_msi_bottom_irq_chip,
170 domain->host_data, handle_simple_irq,
171 NULL, NULL);
172 }
Thomas Petazzonifcc392d2016-02-10 15:46:57 +0100173
Thomas Petazzoni31f614e2013-08-09 22:27:11 +0200174 return hwirq;
175}
176
Thomas Petazzonifcc392d2016-02-10 15:46:57 +0100177static void armada_370_xp_msi_free(struct irq_domain *domain,
178 unsigned int virq, unsigned int nr_irqs)
Thomas Petazzoni31f614e2013-08-09 22:27:11 +0200179{
Thomas Petazzonifcc392d2016-02-10 15:46:57 +0100180 struct irq_data *d = irq_domain_get_irq_data(domain, virq);
181
Thomas Petazzoni31f614e2013-08-09 22:27:11 +0200182 mutex_lock(&msi_used_lock);
Thomas Petazzonia71b9412016-02-10 15:47:00 +0100183 bitmap_clear(msi_used, d->hwirq, nr_irqs);
Thomas Petazzoni31f614e2013-08-09 22:27:11 +0200184 mutex_unlock(&msi_used_lock);
185}
186
Thomas Petazzonifcc392d2016-02-10 15:46:57 +0100187static const struct irq_domain_ops armada_370_xp_msi_domain_ops = {
188 .alloc = armada_370_xp_msi_alloc,
189 .free = armada_370_xp_msi_free,
Thomas Petazzoni31f614e2013-08-09 22:27:11 +0200190};
191
192static int armada_370_xp_msi_init(struct device_node *node,
193 phys_addr_t main_int_phys_base)
194{
Thomas Petazzoni31f614e2013-08-09 22:27:11 +0200195 u32 reg;
Thomas Petazzoni31f614e2013-08-09 22:27:11 +0200196
197 msi_doorbell_addr = main_int_phys_base +
198 ARMADA_370_XP_SW_TRIG_INT_OFFS;
199
Thomas Petazzonifcc392d2016-02-10 15:46:57 +0100200 armada_370_xp_msi_inner_domain =
201 irq_domain_add_linear(NULL, PCI_MSI_DOORBELL_NR,
202 &armada_370_xp_msi_domain_ops, NULL);
203 if (!armada_370_xp_msi_inner_domain)
Thomas Petazzoni31f614e2013-08-09 22:27:11 +0200204 return -ENOMEM;
205
Thomas Petazzoni31f614e2013-08-09 22:27:11 +0200206 armada_370_xp_msi_domain =
Thomas Petazzonifcc392d2016-02-10 15:46:57 +0100207 pci_msi_create_irq_domain(of_node_to_fwnode(node),
208 &armada_370_xp_msi_domain_info,
209 armada_370_xp_msi_inner_domain);
Thomas Petazzoni31f614e2013-08-09 22:27:11 +0200210 if (!armada_370_xp_msi_domain) {
Thomas Petazzonifcc392d2016-02-10 15:46:57 +0100211 irq_domain_remove(armada_370_xp_msi_inner_domain);
Thomas Petazzoni31f614e2013-08-09 22:27:11 +0200212 return -ENOMEM;
213 }
214
Thomas Petazzoni31f614e2013-08-09 22:27:11 +0200215 reg = readl(per_cpu_int_base + ARMADA_370_XP_IN_DRBEL_MSK_OFFS)
216 | PCI_MSI_DOORBELL_MASK;
217
218 writel(reg, per_cpu_int_base +
219 ARMADA_370_XP_IN_DRBEL_MSK_OFFS);
220
221 /* Unmask IPI interrupt */
222 writel(1, per_cpu_int_base + ARMADA_370_XP_INT_CLEAR_MASK_OFFS);
223
224 return 0;
225}
226#else
227static inline int armada_370_xp_msi_init(struct device_node *node,
228 phys_addr_t main_int_phys_base)
229{
230 return 0;
231}
232#endif
233
Gregory CLEMENT344e8732012-08-02 11:19:12 +0300234#ifdef CONFIG_SMP
Arnaud Ebalard19e61d42014-01-20 22:52:05 +0100235static DEFINE_RAW_SPINLOCK(irq_controller_lock);
236
Gregory CLEMENT344e8732012-08-02 11:19:12 +0300237static int armada_xp_set_affinity(struct irq_data *d,
238 const struct cpumask *mask_val, bool force)
239{
Gregory CLEMENT3202bf02012-12-05 21:43:23 +0100240 irq_hw_number_t hwirq = irqd_to_hwirq(d);
Thomas Gleixner8cc3cfc2014-03-04 20:43:41 +0000241 unsigned long reg, mask;
Gregory CLEMENT3202bf02012-12-05 21:43:23 +0100242 int cpu;
243
Thomas Gleixner8cc3cfc2014-03-04 20:43:41 +0000244 /* Select a single core from the affinity mask which is online */
245 cpu = cpumask_any_and(mask_val, cpu_online_mask);
246 mask = 1UL << cpu_logical_map(cpu);
Gregory CLEMENT3202bf02012-12-05 21:43:23 +0100247
248 raw_spin_lock(&irq_controller_lock);
Gregory CLEMENT3202bf02012-12-05 21:43:23 +0100249 reg = readl(main_int_base + ARMADA_370_XP_INT_SOURCE_CTL(hwirq));
Thomas Gleixner8cc3cfc2014-03-04 20:43:41 +0000250 reg = (reg & (~ARMADA_370_XP_INT_SOURCE_CPU_MASK)) | mask;
Gregory CLEMENT3202bf02012-12-05 21:43:23 +0100251 writel(reg, main_int_base + ARMADA_370_XP_INT_SOURCE_CTL(hwirq));
Gregory CLEMENT3202bf02012-12-05 21:43:23 +0100252 raw_spin_unlock(&irq_controller_lock);
253
Thomas Petazzoni1dacf192014-10-24 13:59:16 +0200254 return IRQ_SET_MASK_OK;
Gregory CLEMENT344e8732012-08-02 11:19:12 +0300255}
256#endif
257
Thomas Petazzoni9ae6f742012-06-13 19:01:28 +0200258static struct irq_chip armada_370_xp_irq_chip = {
Thomas Petazzonif692a172016-02-10 15:46:59 +0100259 .name = "MPIC",
Thomas Petazzoni9ae6f742012-06-13 19:01:28 +0200260 .irq_mask = armada_370_xp_irq_mask,
261 .irq_mask_ack = armada_370_xp_irq_mask,
262 .irq_unmask = armada_370_xp_irq_unmask,
Gregory CLEMENT344e8732012-08-02 11:19:12 +0300263#ifdef CONFIG_SMP
264 .irq_set_affinity = armada_xp_set_affinity,
265#endif
Gregory CLEMENT0d8e1d82015-03-30 16:04:37 +0200266 .flags = IRQCHIP_SKIP_SET_WAKE | IRQCHIP_MASK_ON_SUSPEND,
Thomas Petazzoni9ae6f742012-06-13 19:01:28 +0200267};
268
269static int armada_370_xp_mpic_irq_map(struct irq_domain *h,
270 unsigned int virq, irq_hw_number_t hw)
271{
272 armada_370_xp_irq_mask(irq_get_irq_data(virq));
Ezequiel Garcia2c299de2015-03-03 11:43:15 +0100273 if (!is_percpu_irq(hw))
Gregory CLEMENT600468d2013-04-05 14:32:52 +0200274 writel(hw, per_cpu_int_base +
275 ARMADA_370_XP_INT_CLEAR_MASK_OFFS);
276 else
277 writel(hw, main_int_base + ARMADA_370_XP_INT_SET_ENABLE_OFFS);
Thomas Petazzoni9ae6f742012-06-13 19:01:28 +0200278 irq_set_status_flags(virq, IRQ_LEVEL);
Gregory CLEMENT3a6f08a2013-01-25 18:32:41 +0100279
Ezequiel Garcia2c299de2015-03-03 11:43:15 +0100280 if (is_percpu_irq(hw)) {
Gregory CLEMENT3a6f08a2013-01-25 18:32:41 +0100281 irq_set_percpu_devid(virq);
282 irq_set_chip_and_handler(virq, &armada_370_xp_irq_chip,
283 handle_percpu_devid_irq);
284
285 } else {
286 irq_set_chip_and_handler(virq, &armada_370_xp_irq_chip,
287 handle_level_irq);
288 }
Rob Herringd17cab42015-08-29 18:01:22 -0500289 irq_set_probe(virq);
Thomas Petazzoni353d6d62015-10-21 15:48:15 +0200290 irq_clear_status_flags(virq, IRQ_NOAUTOEN);
Thomas Petazzoni9ae6f742012-06-13 19:01:28 +0200291
292 return 0;
293}
294
Thomas Petazzonid7df84b2014-04-14 15:54:02 +0200295static void armada_xp_mpic_smp_cpu_init(void)
Gregory CLEMENT344e8732012-08-02 11:19:12 +0300296{
Thomas Petazzonib73842b2014-05-30 22:18:18 +0200297 u32 control;
298 int nr_irqs, i;
299
300 control = readl(main_int_base + ARMADA_370_XP_INT_CONTROL);
301 nr_irqs = (control >> 2) & 0x3ff;
302
303 for (i = 0; i < nr_irqs; i++)
304 writel(i, per_cpu_int_base + ARMADA_370_XP_INT_SET_MASK_OFFS);
305
Gregory CLEMENT344e8732012-08-02 11:19:12 +0300306 /* Clear pending IPIs */
307 writel(0, per_cpu_int_base + ARMADA_370_XP_IN_DRBEL_CAUSE_OFFS);
308
309 /* Enable first 8 IPIs */
Thomas Petazzoni5ec69012013-04-09 23:26:17 +0200310 writel(IPI_DOORBELL_MASK, per_cpu_int_base +
Gregory CLEMENT344e8732012-08-02 11:19:12 +0300311 ARMADA_370_XP_IN_DRBEL_MSK_OFFS);
312
313 /* Unmask IPI interrupt */
314 writel(0, per_cpu_int_base + ARMADA_370_XP_INT_CLEAR_MASK_OFFS);
315}
Thomas Petazzonid7df84b2014-04-14 15:54:02 +0200316
Maxime Ripard28da06d2015-03-03 11:43:16 +0100317static void armada_xp_mpic_perf_init(void)
318{
319 unsigned long cpuid = cpu_logical_map(smp_processor_id());
320
321 /* Enable Performance Counter Overflow interrupts */
322 writel(ARMADA_370_XP_INT_CAUSE_PERF(cpuid),
323 per_cpu_int_base + ARMADA_370_XP_INT_FABRIC_MASK_OFFS);
324}
325
Ezequiel Garcia933a24b2015-03-03 11:43:14 +0100326#ifdef CONFIG_SMP
327static void armada_mpic_send_doorbell(const struct cpumask *mask,
328 unsigned int irq)
329{
330 int cpu;
331 unsigned long map = 0;
332
333 /* Convert our logical CPU mask into a physical one. */
334 for_each_cpu(cpu, mask)
335 map |= 1 << cpu_logical_map(cpu);
336
337 /*
338 * Ensure that stores to Normal memory are visible to the
339 * other CPUs before issuing the IPI.
340 */
341 dsb();
342
343 /* submit softirq */
344 writel((map << 8) | irq, main_int_base +
345 ARMADA_370_XP_SW_TRIG_INT_OFFS);
346}
347
Richard Cochrancb5ff2d2016-07-13 17:16:07 +0000348static int armada_xp_mpic_starting_cpu(unsigned int cpu)
Thomas Petazzonid7df84b2014-04-14 15:54:02 +0200349{
Richard Cochrancb5ff2d2016-07-13 17:16:07 +0000350 armada_xp_mpic_perf_init();
351 armada_xp_mpic_smp_cpu_init();
352 return 0;
Thomas Petazzonid7df84b2014-04-14 15:54:02 +0200353}
354
Richard Cochrancb5ff2d2016-07-13 17:16:07 +0000355static int mpic_cascaded_starting_cpu(unsigned int cpu)
Maxime Ripard5724be82015-03-03 11:27:23 +0100356{
Richard Cochrancb5ff2d2016-07-13 17:16:07 +0000357 armada_xp_mpic_perf_init();
358 enable_percpu_irq(parent_irq, IRQ_TYPE_NONE);
359 return 0;
Maxime Ripard5724be82015-03-03 11:27:23 +0100360}
Arnd Bergmannc76c15e2016-07-18 18:03:21 +0200361#endif
Gregory CLEMENT344e8732012-08-02 11:19:12 +0300362
Krzysztof Kozlowski96009732015-04-27 21:54:24 +0900363static const struct irq_domain_ops armada_370_xp_mpic_irq_ops = {
Thomas Petazzoni9ae6f742012-06-13 19:01:28 +0200364 .map = armada_370_xp_mpic_irq_map,
365 .xlate = irq_domain_xlate_onecell,
366};
367
Ezequiel Garcia9b8cf772014-02-10 17:00:01 -0300368#ifdef CONFIG_PCI_MSI
Ezequiel Garciabc69b8a2014-02-10 17:00:02 -0300369static void armada_370_xp_handle_msi_irq(struct pt_regs *regs, bool is_chained)
Ezequiel Garcia9b8cf772014-02-10 17:00:01 -0300370{
371 u32 msimask, msinr;
372
373 msimask = readl_relaxed(per_cpu_int_base +
374 ARMADA_370_XP_IN_DRBEL_CAUSE_OFFS)
375 & PCI_MSI_DOORBELL_MASK;
376
377 writel(~msimask, per_cpu_int_base +
378 ARMADA_370_XP_IN_DRBEL_CAUSE_OFFS);
379
380 for (msinr = PCI_MSI_DOORBELL_START;
381 msinr < PCI_MSI_DOORBELL_END; msinr++) {
382 int irq;
383
384 if (!(msimask & BIT(msinr)))
385 continue;
386
Marc Zyngiere89c6a02014-08-26 11:03:21 +0100387 if (is_chained) {
Thomas Petazzonifcc392d2016-02-10 15:46:57 +0100388 irq = irq_find_mapping(armada_370_xp_msi_inner_domain,
Thomas Petazzoni0636bab2016-02-10 15:46:58 +0100389 msinr - PCI_MSI_DOORBELL_START);
Ezequiel Garciabc69b8a2014-02-10 17:00:02 -0300390 generic_handle_irq(irq);
Marc Zyngiere89c6a02014-08-26 11:03:21 +0100391 } else {
Thomas Petazzoni0636bab2016-02-10 15:46:58 +0100392 irq = msinr - PCI_MSI_DOORBELL_START;
Thomas Petazzonifcc392d2016-02-10 15:46:57 +0100393 handle_domain_irq(armada_370_xp_msi_inner_domain,
Marc Zyngiere89c6a02014-08-26 11:03:21 +0100394 irq, regs);
395 }
Ezequiel Garcia9b8cf772014-02-10 17:00:01 -0300396 }
397}
398#else
Ezequiel Garciabc69b8a2014-02-10 17:00:02 -0300399static void armada_370_xp_handle_msi_irq(struct pt_regs *r, bool b) {}
Ezequiel Garcia9b8cf772014-02-10 17:00:01 -0300400#endif
401
Thomas Gleixnerbd0b9ac2015-09-14 10:42:37 +0200402static void armada_370_xp_mpic_handle_cascade_irq(struct irq_desc *desc)
Ezequiel Garciabc69b8a2014-02-10 17:00:02 -0300403{
Jiang Liu5b292642015-06-04 12:13:20 +0800404 struct irq_chip *chip = irq_desc_get_chip(desc);
Grzegorz Jaszczyk758e8362014-09-25 13:17:19 +0200405 unsigned long irqmap, irqn, irqsrc, cpuid;
Ezequiel Garciabc69b8a2014-02-10 17:00:02 -0300406 unsigned int cascade_irq;
407
408 chained_irq_enter(chip, desc);
409
410 irqmap = readl_relaxed(per_cpu_int_base + ARMADA_375_PPI_CAUSE);
Grzegorz Jaszczyk758e8362014-09-25 13:17:19 +0200411 cpuid = cpu_logical_map(smp_processor_id());
Ezequiel Garciabc69b8a2014-02-10 17:00:02 -0300412
413 for_each_set_bit(irqn, &irqmap, BITS_PER_LONG) {
Grzegorz Jaszczyk758e8362014-09-25 13:17:19 +0200414 irqsrc = readl_relaxed(main_int_base +
415 ARMADA_370_XP_INT_SOURCE_CTL(irqn));
416
417 /* Check if the interrupt is not masked on current CPU.
418 * Test IRQ (0-1) and FIQ (8-9) mask bits.
419 */
420 if (!(irqsrc & ARMADA_370_XP_INT_IRQ_FIQ_MASK(cpuid)))
421 continue;
422
423 if (irqn == 1) {
424 armada_370_xp_handle_msi_irq(NULL, true);
425 continue;
426 }
427
Ezequiel Garciabc69b8a2014-02-10 17:00:02 -0300428 cascade_irq = irq_find_mapping(armada_370_xp_mpic_domain, irqn);
429 generic_handle_irq(cascade_irq);
430 }
431
432 chained_irq_exit(chip, desc);
433}
434
Stephen Boyd8783dd32014-03-04 16:40:30 -0800435static void __exception_irq_entry
Thomas Petazzoni9339d432013-04-09 23:26:15 +0200436armada_370_xp_handle_irq(struct pt_regs *regs)
Thomas Petazzoni9ae6f742012-06-13 19:01:28 +0200437{
438 u32 irqstat, irqnr;
439
440 do {
441 irqstat = readl_relaxed(per_cpu_int_base +
442 ARMADA_370_XP_CPU_INTACK_OFFS);
443 irqnr = irqstat & 0x3FF;
444
Gregory CLEMENT344e8732012-08-02 11:19:12 +0300445 if (irqnr > 1022)
446 break;
447
Thomas Petazzoni31f614e2013-08-09 22:27:11 +0200448 if (irqnr > 1) {
Marc Zyngiere89c6a02014-08-26 11:03:21 +0100449 handle_domain_irq(armada_370_xp_mpic_domain,
450 irqnr, regs);
Thomas Petazzoni9ae6f742012-06-13 19:01:28 +0200451 continue;
452 }
Thomas Petazzoni31f614e2013-08-09 22:27:11 +0200453
Thomas Petazzoni31f614e2013-08-09 22:27:11 +0200454 /* MSI handling */
Ezequiel Garcia9b8cf772014-02-10 17:00:01 -0300455 if (irqnr == 1)
Ezequiel Garciabc69b8a2014-02-10 17:00:02 -0300456 armada_370_xp_handle_msi_irq(regs, false);
Thomas Petazzoni31f614e2013-08-09 22:27:11 +0200457
Gregory CLEMENT344e8732012-08-02 11:19:12 +0300458#ifdef CONFIG_SMP
459 /* IPI Handling */
460 if (irqnr == 0) {
461 u32 ipimask, ipinr;
Thomas Petazzoni9ae6f742012-06-13 19:01:28 +0200462
Gregory CLEMENT344e8732012-08-02 11:19:12 +0300463 ipimask = readl_relaxed(per_cpu_int_base +
464 ARMADA_370_XP_IN_DRBEL_CAUSE_OFFS)
Thomas Petazzoni5ec69012013-04-09 23:26:17 +0200465 & IPI_DOORBELL_MASK;
Gregory CLEMENT344e8732012-08-02 11:19:12 +0300466
Lior Amsalema6f089e2013-11-25 17:26:44 +0100467 writel(~ipimask, per_cpu_int_base +
Gregory CLEMENT344e8732012-08-02 11:19:12 +0300468 ARMADA_370_XP_IN_DRBEL_CAUSE_OFFS);
469
470 /* Handle all pending doorbells */
Thomas Petazzoni5ec69012013-04-09 23:26:17 +0200471 for (ipinr = IPI_DOORBELL_START;
472 ipinr < IPI_DOORBELL_END; ipinr++) {
Gregory CLEMENT344e8732012-08-02 11:19:12 +0300473 if (ipimask & (0x1 << ipinr))
474 handle_IPI(ipinr, regs);
475 }
476 continue;
477 }
478#endif
479
Thomas Petazzoni9ae6f742012-06-13 19:01:28 +0200480 } while (1);
481}
482
Thomas Petazzoni0f077eb2014-11-21 17:00:00 +0100483static int armada_370_xp_mpic_suspend(void)
484{
485 doorbell_mask_reg = readl(per_cpu_int_base +
486 ARMADA_370_XP_IN_DRBEL_MSK_OFFS);
487 return 0;
488}
489
490static void armada_370_xp_mpic_resume(void)
491{
492 int nirqs;
493 irq_hw_number_t irq;
494
495 /* Re-enable interrupts */
496 nirqs = (readl(main_int_base + ARMADA_370_XP_INT_CONTROL) >> 2) & 0x3ff;
497 for (irq = 0; irq < nirqs; irq++) {
498 struct irq_data *data;
499 int virq;
500
501 virq = irq_linear_revmap(armada_370_xp_mpic_domain, irq);
502 if (virq == 0)
503 continue;
504
Maxime Ripard080481f92015-09-25 18:09:34 +0200505 if (!is_percpu_irq(irq))
Thomas Petazzoni0f077eb2014-11-21 17:00:00 +0100506 writel(irq, per_cpu_int_base +
507 ARMADA_370_XP_INT_CLEAR_MASK_OFFS);
508 else
509 writel(irq, main_int_base +
510 ARMADA_370_XP_INT_SET_ENABLE_OFFS);
511
512 data = irq_get_irq_data(virq);
513 if (!irqd_irq_disabled(data))
514 armada_370_xp_irq_unmask(data);
515 }
516
517 /* Reconfigure doorbells for IPIs and MSIs */
518 writel(doorbell_mask_reg,
519 per_cpu_int_base + ARMADA_370_XP_IN_DRBEL_MSK_OFFS);
520 if (doorbell_mask_reg & IPI_DOORBELL_MASK)
521 writel(0, per_cpu_int_base + ARMADA_370_XP_INT_CLEAR_MASK_OFFS);
522 if (doorbell_mask_reg & PCI_MSI_DOORBELL_MASK)
523 writel(1, per_cpu_int_base + ARMADA_370_XP_INT_CLEAR_MASK_OFFS);
524}
525
Ben Dooks6c880902016-06-08 18:55:33 +0100526static struct syscore_ops armada_370_xp_mpic_syscore_ops = {
Thomas Petazzoni0f077eb2014-11-21 17:00:00 +0100527 .suspend = armada_370_xp_mpic_suspend,
528 .resume = armada_370_xp_mpic_resume,
529};
530
Thomas Petazzoni9ae6f742012-06-13 19:01:28 +0200531static int __init armada_370_xp_mpic_of_init(struct device_node *node,
532 struct device_node *parent)
533{
Thomas Petazzoni627dfcc2013-08-09 22:27:10 +0200534 struct resource main_int_res, per_cpu_int_res;
Maxime Ripard5724be82015-03-03 11:27:23 +0100535 int nr_irqs, i;
Thomas Petazzoni9ae6f742012-06-13 19:01:28 +0200536 u32 control;
537
Thomas Petazzoni627dfcc2013-08-09 22:27:10 +0200538 BUG_ON(of_address_to_resource(node, 0, &main_int_res));
539 BUG_ON(of_address_to_resource(node, 1, &per_cpu_int_res));
Thomas Petazzoni9ae6f742012-06-13 19:01:28 +0200540
Thomas Petazzoni627dfcc2013-08-09 22:27:10 +0200541 BUG_ON(!request_mem_region(main_int_res.start,
542 resource_size(&main_int_res),
543 node->full_name));
544 BUG_ON(!request_mem_region(per_cpu_int_res.start,
545 resource_size(&per_cpu_int_res),
546 node->full_name));
547
548 main_int_base = ioremap(main_int_res.start,
549 resource_size(&main_int_res));
Thomas Petazzoni9ae6f742012-06-13 19:01:28 +0200550 BUG_ON(!main_int_base);
Thomas Petazzoni627dfcc2013-08-09 22:27:10 +0200551
552 per_cpu_int_base = ioremap(per_cpu_int_res.start,
553 resource_size(&per_cpu_int_res));
Thomas Petazzoni9ae6f742012-06-13 19:01:28 +0200554 BUG_ON(!per_cpu_int_base);
Gregory CLEMENTd792b1e2012-09-26 18:02:48 +0200555
556 control = readl(main_int_base + ARMADA_370_XP_INT_CONTROL);
Thomas Petazzonib73842b2014-05-30 22:18:18 +0200557 nr_irqs = (control >> 2) & 0x3ff;
558
559 for (i = 0; i < nr_irqs; i++)
560 writel(i, main_int_base + ARMADA_370_XP_INT_CLEAR_ENABLE_OFFS);
Gregory CLEMENTd792b1e2012-09-26 18:02:48 +0200561
Thomas Petazzoni9ae6f742012-06-13 19:01:28 +0200562 armada_370_xp_mpic_domain =
Thomas Petazzonib73842b2014-05-30 22:18:18 +0200563 irq_domain_add_linear(node, nr_irqs,
Thomas Petazzoni9ae6f742012-06-13 19:01:28 +0200564 &armada_370_xp_mpic_irq_ops, NULL);
Thomas Petazzoni627dfcc2013-08-09 22:27:10 +0200565 BUG_ON(!armada_370_xp_mpic_domain);
Thomas Petazzonifcc392d2016-02-10 15:46:57 +0100566 armada_370_xp_mpic_domain->bus_token = DOMAIN_BUS_WIRED;
Thomas Petazzoni9ae6f742012-06-13 19:01:28 +0200567
Ezequiel Garcia933a24b2015-03-03 11:43:14 +0100568 /* Setup for the boot CPU */
Maxime Ripard28da06d2015-03-03 11:43:16 +0100569 armada_xp_mpic_perf_init();
Thomas Petazzoni9ae6f742012-06-13 19:01:28 +0200570 armada_xp_mpic_smp_cpu_init();
Thomas Petazzoni9ae6f742012-06-13 19:01:28 +0200571
Thomas Petazzoni31f614e2013-08-09 22:27:11 +0200572 armada_370_xp_msi_init(node, main_int_res.start);
573
Ezequiel Garciabc69b8a2014-02-10 17:00:02 -0300574 parent_irq = irq_of_parse_and_map(node, 0);
575 if (parent_irq <= 0) {
576 irq_set_default_host(armada_370_xp_mpic_domain);
577 set_handle_irq(armada_370_xp_handle_irq);
Thomas Petazzonief37d332014-04-14 15:54:01 +0200578#ifdef CONFIG_SMP
579 set_smp_cross_call(armada_mpic_send_doorbell);
Richard Cochrancb5ff2d2016-07-13 17:16:07 +0000580 cpuhp_setup_state_nocalls(CPUHP_AP_IRQ_ARMADA_XP_STARTING,
581 "AP_IRQ_ARMADA_XP_STARTING",
582 armada_xp_mpic_starting_cpu, NULL);
Thomas Petazzonief37d332014-04-14 15:54:01 +0200583#endif
Ezequiel Garciabc69b8a2014-02-10 17:00:02 -0300584 } else {
Maxime Ripard5724be82015-03-03 11:27:23 +0100585#ifdef CONFIG_SMP
Richard Cochrancb5ff2d2016-07-13 17:16:07 +0000586 cpuhp_setup_state_nocalls(CPUHP_AP_IRQ_ARMADA_CASC_STARTING,
587 "AP_IRQ_ARMADA_CASC_STARTING",
588 mpic_cascaded_starting_cpu, NULL);
Maxime Ripard5724be82015-03-03 11:27:23 +0100589#endif
Ezequiel Garciabc69b8a2014-02-10 17:00:02 -0300590 irq_set_chained_handler(parent_irq,
591 armada_370_xp_mpic_handle_cascade_irq);
592 }
Thomas Petazzonib313ada2013-04-09 23:26:16 +0200593
Thomas Petazzoni0f077eb2014-11-21 17:00:00 +0100594 register_syscore_ops(&armada_370_xp_mpic_syscore_ops);
595
Thomas Petazzoni9ae6f742012-06-13 19:01:28 +0200596 return 0;
597}
598
Thomas Petazzoni9339d432013-04-09 23:26:15 +0200599IRQCHIP_DECLARE(armada_370_xp_mpic, "marvell,mpic", armada_370_xp_mpic_of_init);