yanyang1 | c82baa2 | 2015-08-18 15:28:32 +0800 | [diff] [blame] | 1 | /* |
| 2 | * Copyright 2015 Advanced Micro Devices, Inc. |
| 3 | * |
| 4 | * Permission is hereby granted, free of charge, to any person obtaining a |
| 5 | * copy of this software and associated documentation files (the "Software"), |
| 6 | * to deal in the Software without restriction, including without limitation |
| 7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, |
| 8 | * and/or sell copies of the Software, and to permit persons to whom the |
| 9 | * Software is furnished to do so, subject to the following conditions: |
| 10 | * |
| 11 | * The above copyright notice and this permission notice shall be included in |
| 12 | * all copies or substantial portions of the Software. |
| 13 | * |
| 14 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
| 15 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
| 16 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
| 17 | * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR |
| 18 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, |
| 19 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR |
| 20 | * OTHER DEALINGS IN THE SOFTWARE. |
| 21 | * |
| 22 | */ |
| 23 | #include <linux/module.h> |
| 24 | #include <linux/slab.h> |
yanyang1 | c82baa2 | 2015-08-18 15:28:32 +0800 | [diff] [blame] | 25 | #include "linux/delay.h" |
| 26 | #include "pp_acpi.h" |
| 27 | #include "hwmgr.h" |
| 28 | #include <atombios.h> |
| 29 | #include "tonga_hwmgr.h" |
| 30 | #include "pptable.h" |
| 31 | #include "processpptables.h" |
| 32 | #include "tonga_processpptables.h" |
| 33 | #include "tonga_pptable.h" |
| 34 | #include "pp_debug.h" |
| 35 | #include "tonga_ppsmc.h" |
| 36 | #include "cgs_common.h" |
| 37 | #include "pppcielanes.h" |
| 38 | #include "tonga_dyn_defaults.h" |
| 39 | #include "smumgr.h" |
| 40 | #include "tonga_smumgr.h" |
Rex Zhu | 0859ed3 | 2015-10-15 21:12:58 +0800 | [diff] [blame] | 41 | #include "tonga_clockpowergating.h" |
Rex Zhu | 1e4854e | 2015-10-20 18:06:23 +0800 | [diff] [blame] | 42 | #include "tonga_thermal.h" |
yanyang1 | c82baa2 | 2015-08-18 15:28:32 +0800 | [diff] [blame] | 43 | |
| 44 | #include "smu/smu_7_1_2_d.h" |
| 45 | #include "smu/smu_7_1_2_sh_mask.h" |
| 46 | |
| 47 | #include "gmc/gmc_8_1_d.h" |
| 48 | #include "gmc/gmc_8_1_sh_mask.h" |
| 49 | |
| 50 | #include "bif/bif_5_0_d.h" |
| 51 | #include "bif/bif_5_0_sh_mask.h" |
| 52 | |
Alex Deucher | 7e8d1fb | 2016-04-08 16:42:38 -0400 | [diff] [blame] | 53 | #include "dce/dce_10_0_d.h" |
| 54 | #include "dce/dce_10_0_sh_mask.h" |
| 55 | |
Rex Zhu | 1e4854e | 2015-10-20 18:06:23 +0800 | [diff] [blame] | 56 | #include "cgs_linux.h" |
| 57 | #include "eventmgr.h" |
Alex Deucher | 16881da | 2015-11-11 20:18:52 -0500 | [diff] [blame] | 58 | #include "amd_pcie_helpers.h" |
Rex Zhu | 1e4854e | 2015-10-20 18:06:23 +0800 | [diff] [blame] | 59 | |
yanyang1 | c82baa2 | 2015-08-18 15:28:32 +0800 | [diff] [blame] | 60 | #define MC_CG_ARB_FREQ_F0 0x0a |
| 61 | #define MC_CG_ARB_FREQ_F1 0x0b |
| 62 | #define MC_CG_ARB_FREQ_F2 0x0c |
| 63 | #define MC_CG_ARB_FREQ_F3 0x0d |
| 64 | |
| 65 | #define MC_CG_SEQ_DRAMCONF_S0 0x05 |
| 66 | #define MC_CG_SEQ_DRAMCONF_S1 0x06 |
| 67 | #define MC_CG_SEQ_YCLK_SUSPEND 0x04 |
| 68 | #define MC_CG_SEQ_YCLK_RESUME 0x0a |
| 69 | |
| 70 | #define PCIE_BUS_CLK 10000 |
| 71 | #define TCLK (PCIE_BUS_CLK / 10) |
| 72 | |
| 73 | #define SMC_RAM_END 0x40000 |
| 74 | #define SMC_CG_IND_START 0xc0030000 |
| 75 | #define SMC_CG_IND_END 0xc0040000 /* First byte after SMC_CG_IND*/ |
| 76 | |
| 77 | #define VOLTAGE_SCALE 4 |
| 78 | #define VOLTAGE_VID_OFFSET_SCALE1 625 |
| 79 | #define VOLTAGE_VID_OFFSET_SCALE2 100 |
| 80 | |
| 81 | #define VDDC_VDDCI_DELTA 200 |
| 82 | #define VDDC_VDDGFX_DELTA 300 |
| 83 | |
| 84 | #define MC_SEQ_MISC0_GDDR5_SHIFT 28 |
| 85 | #define MC_SEQ_MISC0_GDDR5_MASK 0xf0000000 |
| 86 | #define MC_SEQ_MISC0_GDDR5_VALUE 5 |
| 87 | |
| 88 | typedef uint32_t PECI_RegistryValue; |
| 89 | |
| 90 | /* [2.5%,~2.5%] Clock stretched is multiple of 2.5% vs not and [Fmin, Fmax, LDO_REFSEL, USE_FOR_LOW_FREQ] */ |
Nils Wallménius | f498d9e | 2016-04-10 16:29:59 +0200 | [diff] [blame] | 91 | static const uint16_t PP_ClockStretcherLookupTable[2][4] = { |
yanyang1 | c82baa2 | 2015-08-18 15:28:32 +0800 | [diff] [blame] | 92 | {600, 1050, 3, 0}, |
| 93 | {600, 1050, 6, 1} }; |
| 94 | |
| 95 | /* [FF, SS] type, [] 4 voltage ranges, and [Floor Freq, Boundary Freq, VID min , VID max] */ |
Nils Wallménius | f498d9e | 2016-04-10 16:29:59 +0200 | [diff] [blame] | 96 | static const uint32_t PP_ClockStretcherDDTTable[2][4][4] = { |
yanyang1 | c82baa2 | 2015-08-18 15:28:32 +0800 | [diff] [blame] | 97 | { {265, 529, 120, 128}, {325, 650, 96, 119}, {430, 860, 32, 95}, {0, 0, 0, 31} }, |
| 98 | { {275, 550, 104, 112}, {319, 638, 96, 103}, {360, 720, 64, 95}, {384, 768, 32, 63} } }; |
| 99 | |
| 100 | /* [Use_For_Low_freq] value, [0%, 5%, 10%, 7.14%, 14.28%, 20%] (coming from PWR_CKS_CNTL.stretch_amount reg spec) */ |
Nils Wallménius | f498d9e | 2016-04-10 16:29:59 +0200 | [diff] [blame] | 101 | static const uint8_t PP_ClockStretchAmountConversion[2][6] = { |
yanyang1 | c82baa2 | 2015-08-18 15:28:32 +0800 | [diff] [blame] | 102 | {0, 1, 3, 2, 4, 5}, |
| 103 | {0, 2, 4, 5, 6, 5} }; |
| 104 | |
| 105 | /* Values for the CG_THERMAL_CTRL::DPM_EVENT_SRC field. */ |
| 106 | enum DPM_EVENT_SRC { |
| 107 | DPM_EVENT_SRC_ANALOG = 0, /* Internal analog trip point */ |
| 108 | DPM_EVENT_SRC_EXTERNAL = 1, /* External (GPIO 17) signal */ |
| 109 | DPM_EVENT_SRC_DIGITAL = 2, /* Internal digital trip point (DIG_THERM_DPM) */ |
| 110 | DPM_EVENT_SRC_ANALOG_OR_EXTERNAL = 3, /* Internal analog or external */ |
| 111 | DPM_EVENT_SRC_DIGITAL_OR_EXTERNAL = 4 /* Internal digital or external */ |
| 112 | }; |
| 113 | typedef enum DPM_EVENT_SRC DPM_EVENT_SRC; |
| 114 | |
Nils Wallménius | f498d9e | 2016-04-10 16:29:59 +0200 | [diff] [blame] | 115 | static const unsigned long PhwTonga_Magic = (unsigned long)(PHM_VIslands_Magic); |
yanyang1 | c82baa2 | 2015-08-18 15:28:32 +0800 | [diff] [blame] | 116 | |
| 117 | struct tonga_power_state *cast_phw_tonga_power_state( |
| 118 | struct pp_hw_power_state *hw_ps) |
| 119 | { |
Rex Zhu | c15c8d7 | 2016-01-06 16:48:38 +0800 | [diff] [blame] | 120 | if (hw_ps == NULL) |
| 121 | return NULL; |
| 122 | |
yanyang1 | c82baa2 | 2015-08-18 15:28:32 +0800 | [diff] [blame] | 123 | PP_ASSERT_WITH_CODE((PhwTonga_Magic == hw_ps->magic), |
| 124 | "Invalid Powerstate Type!", |
Rex Zhu | c15c8d7 | 2016-01-06 16:48:38 +0800 | [diff] [blame] | 125 | return NULL); |
yanyang1 | c82baa2 | 2015-08-18 15:28:32 +0800 | [diff] [blame] | 126 | |
| 127 | return (struct tonga_power_state *)hw_ps; |
| 128 | } |
| 129 | |
| 130 | const struct tonga_power_state *cast_const_phw_tonga_power_state( |
| 131 | const struct pp_hw_power_state *hw_ps) |
| 132 | { |
Rex Zhu | c15c8d7 | 2016-01-06 16:48:38 +0800 | [diff] [blame] | 133 | if (hw_ps == NULL) |
| 134 | return NULL; |
| 135 | |
yanyang1 | c82baa2 | 2015-08-18 15:28:32 +0800 | [diff] [blame] | 136 | PP_ASSERT_WITH_CODE((PhwTonga_Magic == hw_ps->magic), |
| 137 | "Invalid Powerstate Type!", |
Rex Zhu | c15c8d7 | 2016-01-06 16:48:38 +0800 | [diff] [blame] | 138 | return NULL); |
yanyang1 | c82baa2 | 2015-08-18 15:28:32 +0800 | [diff] [blame] | 139 | |
| 140 | return (const struct tonga_power_state *)hw_ps; |
| 141 | } |
| 142 | |
| 143 | int tonga_add_voltage(struct pp_hwmgr *hwmgr, |
| 144 | phm_ppt_v1_voltage_lookup_table *look_up_table, |
| 145 | phm_ppt_v1_voltage_lookup_record *record) |
| 146 | { |
| 147 | uint32_t i; |
| 148 | PP_ASSERT_WITH_CODE((NULL != look_up_table), |
| 149 | "Lookup Table empty.", return -1;); |
| 150 | PP_ASSERT_WITH_CODE((0 != look_up_table->count), |
| 151 | "Lookup Table empty.", return -1;); |
| 152 | PP_ASSERT_WITH_CODE((SMU72_MAX_LEVELS_VDDGFX >= look_up_table->count), |
| 153 | "Lookup Table is full.", return -1;); |
| 154 | |
| 155 | /* This is to avoid entering duplicate calculated records. */ |
| 156 | for (i = 0; i < look_up_table->count; i++) { |
| 157 | if (look_up_table->entries[i].us_vdd == record->us_vdd) { |
| 158 | if (look_up_table->entries[i].us_calculated == 1) |
| 159 | return 0; |
| 160 | else |
| 161 | break; |
| 162 | } |
| 163 | } |
| 164 | |
| 165 | look_up_table->entries[i].us_calculated = 1; |
| 166 | look_up_table->entries[i].us_vdd = record->us_vdd; |
| 167 | look_up_table->entries[i].us_cac_low = record->us_cac_low; |
| 168 | look_up_table->entries[i].us_cac_mid = record->us_cac_mid; |
| 169 | look_up_table->entries[i].us_cac_high = record->us_cac_high; |
| 170 | /* Only increment the count when we're appending, not replacing duplicate entry. */ |
| 171 | if (i == look_up_table->count) |
| 172 | look_up_table->count++; |
| 173 | |
| 174 | return 0; |
| 175 | } |
| 176 | |
Rex Zhu | bbb207f | 2015-10-16 15:02:04 +0800 | [diff] [blame] | 177 | int tonga_notify_smc_display_change(struct pp_hwmgr *hwmgr, bool has_display) |
| 178 | { |
| 179 | PPSMC_Msg msg = has_display? (PPSMC_Msg)PPSMC_HasDisplay : (PPSMC_Msg)PPSMC_NoDisplay; |
| 180 | |
| 181 | return (smum_send_msg_to_smc(hwmgr->smumgr, msg) == 0) ? 0 : -1; |
| 182 | } |
| 183 | |
yanyang1 | c82baa2 | 2015-08-18 15:28:32 +0800 | [diff] [blame] | 184 | uint8_t tonga_get_voltage_id(pp_atomctrl_voltage_table *voltage_table, |
| 185 | uint32_t voltage) |
| 186 | { |
| 187 | uint8_t count = (uint8_t) (voltage_table->count); |
| 188 | uint8_t i = 0; |
| 189 | |
| 190 | PP_ASSERT_WITH_CODE((NULL != voltage_table), |
| 191 | "Voltage Table empty.", return 0;); |
| 192 | PP_ASSERT_WITH_CODE((0 != count), |
| 193 | "Voltage Table empty.", return 0;); |
| 194 | |
| 195 | for (i = 0; i < count; i++) { |
| 196 | /* find first voltage bigger than requested */ |
| 197 | if (voltage_table->entries[i].value >= voltage) |
| 198 | return i; |
| 199 | } |
| 200 | |
| 201 | /* voltage is bigger than max voltage in the table */ |
| 202 | return i - 1; |
| 203 | } |
| 204 | |
| 205 | /** |
| 206 | * @brief PhwTonga_GetVoltageOrder |
| 207 | * Returns index of requested voltage record in lookup(table) |
| 208 | * @param hwmgr - pointer to hardware manager |
| 209 | * @param lookupTable - lookup list to search in |
| 210 | * @param voltage - voltage to look for |
| 211 | * @return 0 on success |
| 212 | */ |
| 213 | uint8_t tonga_get_voltage_index(phm_ppt_v1_voltage_lookup_table *look_up_table, |
| 214 | uint16_t voltage) |
| 215 | { |
| 216 | uint8_t count = (uint8_t) (look_up_table->count); |
| 217 | uint8_t i; |
| 218 | |
| 219 | PP_ASSERT_WITH_CODE((NULL != look_up_table), "Lookup Table empty.", return 0;); |
| 220 | PP_ASSERT_WITH_CODE((0 != count), "Lookup Table empty.", return 0;); |
| 221 | |
| 222 | for (i = 0; i < count; i++) { |
| 223 | /* find first voltage equal or bigger than requested */ |
| 224 | if (look_up_table->entries[i].us_vdd >= voltage) |
| 225 | return i; |
| 226 | } |
| 227 | |
| 228 | /* voltage is bigger than max voltage in the table */ |
| 229 | return i-1; |
| 230 | } |
| 231 | |
| 232 | bool tonga_is_dpm_running(struct pp_hwmgr *hwmgr) |
| 233 | { |
| 234 | /* |
| 235 | * We return the status of Voltage Control instead of checking SCLK/MCLK DPM |
| 236 | * because we may have test scenarios that need us intentionly disable SCLK/MCLK DPM, |
| 237 | * whereas voltage control is a fundemental change that will not be disabled |
| 238 | */ |
| 239 | |
| 240 | return (0 == PHM_READ_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, |
| 241 | FEATURE_STATUS, VOLTAGE_CONTROLLER_ON) ? 1 : 0); |
| 242 | } |
| 243 | |
| 244 | /** |
| 245 | * Re-generate the DPM level mask value |
| 246 | * @param hwmgr the address of the hardware manager |
| 247 | */ |
| 248 | static uint32_t tonga_get_dpm_level_enable_mask_value( |
| 249 | struct tonga_single_dpm_table * dpm_table) |
| 250 | { |
| 251 | uint32_t i; |
| 252 | uint32_t mask_value = 0; |
| 253 | |
| 254 | for (i = dpm_table->count; i > 0; i--) { |
| 255 | mask_value = mask_value << 1; |
| 256 | |
| 257 | if (dpm_table->dpm_levels[i-1].enabled) |
| 258 | mask_value |= 0x1; |
| 259 | else |
| 260 | mask_value &= 0xFFFFFFFE; |
| 261 | } |
| 262 | return mask_value; |
| 263 | } |
| 264 | |
| 265 | /** |
| 266 | * Retrieve DPM default values from registry (if available) |
| 267 | * |
| 268 | * @param hwmgr the address of the powerplay hardware manager. |
| 269 | */ |
| 270 | void tonga_initialize_dpm_defaults(struct pp_hwmgr *hwmgr) |
| 271 | { |
| 272 | tonga_hwmgr *data = (tonga_hwmgr *)(hwmgr->backend); |
| 273 | phw_tonga_ulv_parm *ulv = &(data->ulv); |
| 274 | uint32_t tmp; |
| 275 | |
| 276 | ulv->ch_ulv_parameter = PPTONGA_CGULVPARAMETER_DFLT; |
| 277 | data->voting_rights_clients0 = PPTONGA_VOTINGRIGHTSCLIENTS_DFLT0; |
| 278 | data->voting_rights_clients1 = PPTONGA_VOTINGRIGHTSCLIENTS_DFLT1; |
| 279 | data->voting_rights_clients2 = PPTONGA_VOTINGRIGHTSCLIENTS_DFLT2; |
| 280 | data->voting_rights_clients3 = PPTONGA_VOTINGRIGHTSCLIENTS_DFLT3; |
| 281 | data->voting_rights_clients4 = PPTONGA_VOTINGRIGHTSCLIENTS_DFLT4; |
| 282 | data->voting_rights_clients5 = PPTONGA_VOTINGRIGHTSCLIENTS_DFLT5; |
| 283 | data->voting_rights_clients6 = PPTONGA_VOTINGRIGHTSCLIENTS_DFLT6; |
| 284 | data->voting_rights_clients7 = PPTONGA_VOTINGRIGHTSCLIENTS_DFLT7; |
| 285 | |
| 286 | data->static_screen_threshold_unit = PPTONGA_STATICSCREENTHRESHOLDUNIT_DFLT; |
| 287 | data->static_screen_threshold = PPTONGA_STATICSCREENTHRESHOLD_DFLT; |
| 288 | |
| 289 | phm_cap_unset(hwmgr->platform_descriptor.platformCaps, |
| 290 | PHM_PlatformCaps_ABM); |
| 291 | phm_cap_set(hwmgr->platform_descriptor.platformCaps, |
| 292 | PHM_PlatformCaps_NonABMSupportInPPLib); |
| 293 | |
| 294 | tmp = 0; |
| 295 | if (tmp == 0) |
| 296 | phm_cap_set(hwmgr->platform_descriptor.platformCaps, |
| 297 | PHM_PlatformCaps_DynamicACTiming); |
| 298 | |
| 299 | tmp = 0; |
| 300 | if (0 != tmp) |
| 301 | phm_cap_set(hwmgr->platform_descriptor.platformCaps, |
| 302 | PHM_PlatformCaps_DisableMemoryTransition); |
| 303 | |
| 304 | data->mclk_strobe_mode_threshold = 40000; |
| 305 | data->mclk_stutter_mode_threshold = 30000; |
| 306 | data->mclk_edc_enable_threshold = 40000; |
| 307 | data->mclk_edc_wr_enable_threshold = 40000; |
| 308 | |
| 309 | tmp = 0; |
| 310 | if (tmp != 0) |
| 311 | phm_cap_set(hwmgr->platform_descriptor.platformCaps, |
| 312 | PHM_PlatformCaps_DisableMCLS); |
| 313 | |
| 314 | data->pcie_gen_performance.max = PP_PCIEGen1; |
| 315 | data->pcie_gen_performance.min = PP_PCIEGen3; |
| 316 | data->pcie_gen_power_saving.max = PP_PCIEGen1; |
| 317 | data->pcie_gen_power_saving.min = PP_PCIEGen3; |
| 318 | |
| 319 | data->pcie_lane_performance.max = 0; |
| 320 | data->pcie_lane_performance.min = 16; |
| 321 | data->pcie_lane_power_saving.max = 0; |
| 322 | data->pcie_lane_power_saving.min = 16; |
| 323 | |
| 324 | tmp = 0; |
| 325 | |
| 326 | if (tmp) |
| 327 | phm_cap_set(hwmgr->platform_descriptor.platformCaps, |
| 328 | PHM_PlatformCaps_SclkThrottleLowNotification); |
| 329 | |
| 330 | phm_cap_set(hwmgr->platform_descriptor.platformCaps, |
| 331 | PHM_PlatformCaps_DynamicUVDState); |
| 332 | |
| 333 | } |
| 334 | |
| 335 | int tonga_update_sclk_threshold(struct pp_hwmgr *hwmgr) |
| 336 | { |
| 337 | tonga_hwmgr *data = (tonga_hwmgr *)(hwmgr->backend); |
| 338 | |
| 339 | int result = 0; |
| 340 | uint32_t low_sclk_interrupt_threshold = 0; |
| 341 | |
| 342 | if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, |
| 343 | PHM_PlatformCaps_SclkThrottleLowNotification) |
| 344 | && (hwmgr->gfx_arbiter.sclk_threshold != data->low_sclk_interrupt_threshold)) { |
| 345 | data->low_sclk_interrupt_threshold = hwmgr->gfx_arbiter.sclk_threshold; |
| 346 | low_sclk_interrupt_threshold = data->low_sclk_interrupt_threshold; |
| 347 | |
| 348 | CONVERT_FROM_HOST_TO_SMC_UL(low_sclk_interrupt_threshold); |
| 349 | |
| 350 | result = tonga_copy_bytes_to_smc( |
| 351 | hwmgr->smumgr, |
| 352 | data->dpm_table_start + offsetof(SMU72_Discrete_DpmTable, |
| 353 | LowSclkInterruptThreshold), |
| 354 | (uint8_t *)&low_sclk_interrupt_threshold, |
| 355 | sizeof(uint32_t), |
| 356 | data->sram_end |
| 357 | ); |
| 358 | } |
| 359 | |
| 360 | return result; |
| 361 | } |
| 362 | |
| 363 | /** |
| 364 | * Find SCLK value that is associated with specified virtual_voltage_Id. |
| 365 | * |
| 366 | * @param hwmgr the address of the powerplay hardware manager. |
| 367 | * @param virtual_voltage_Id voltageId to look for. |
| 368 | * @param sclk output value . |
| 369 | * @return always 0 if success and 2 if association not found |
| 370 | */ |
| 371 | static int tonga_get_sclk_for_voltage_evv(struct pp_hwmgr *hwmgr, |
| 372 | phm_ppt_v1_voltage_lookup_table *lookup_table, |
| 373 | uint16_t virtual_voltage_id, uint32_t *sclk) |
| 374 | { |
| 375 | uint8_t entryId; |
| 376 | uint8_t voltageId; |
| 377 | struct phm_ppt_v1_information *pptable_info = |
| 378 | (struct phm_ppt_v1_information *)(hwmgr->pptable); |
| 379 | |
| 380 | PP_ASSERT_WITH_CODE(lookup_table->count != 0, "Lookup table is empty", return -1); |
| 381 | |
| 382 | /* search for leakage voltage ID 0xff01 ~ 0xff08 and sckl */ |
| 383 | for (entryId = 0; entryId < pptable_info->vdd_dep_on_sclk->count; entryId++) { |
| 384 | voltageId = pptable_info->vdd_dep_on_sclk->entries[entryId].vddInd; |
| 385 | if (lookup_table->entries[voltageId].us_vdd == virtual_voltage_id) |
| 386 | break; |
| 387 | } |
| 388 | |
| 389 | PP_ASSERT_WITH_CODE(entryId < pptable_info->vdd_dep_on_sclk->count, |
| 390 | "Can't find requested voltage id in vdd_dep_on_sclk table!", |
| 391 | return -1; |
| 392 | ); |
| 393 | |
| 394 | *sclk = pptable_info->vdd_dep_on_sclk->entries[entryId].clk; |
| 395 | |
| 396 | return 0; |
| 397 | } |
| 398 | |
| 399 | /** |
| 400 | * Get Leakage VDDC based on leakage ID. |
| 401 | * |
| 402 | * @param hwmgr the address of the powerplay hardware manager. |
| 403 | * @return 2 if vddgfx returned is greater than 2V or if BIOS |
| 404 | */ |
| 405 | int tonga_get_evv_voltage(struct pp_hwmgr *hwmgr) |
| 406 | { |
| 407 | tonga_hwmgr *data = (tonga_hwmgr *)(hwmgr->backend); |
| 408 | struct phm_ppt_v1_information *pptable_info = (struct phm_ppt_v1_information *)(hwmgr->pptable); |
| 409 | phm_ppt_v1_clock_voltage_dependency_table *sclk_table = pptable_info->vdd_dep_on_sclk; |
| 410 | uint16_t virtual_voltage_id; |
| 411 | uint16_t vddc = 0; |
| 412 | uint16_t vddgfx = 0; |
| 413 | uint16_t i, j; |
| 414 | uint32_t sclk = 0; |
| 415 | |
| 416 | /* retrieve voltage for leakage ID (0xff01 + i) */ |
| 417 | for (i = 0; i < TONGA_MAX_LEAKAGE_COUNT; i++) { |
| 418 | virtual_voltage_id = ATOM_VIRTUAL_VOLTAGE_ID0 + i; |
| 419 | |
| 420 | /* in split mode we should have only vddgfx EVV leakages */ |
| 421 | if (data->vdd_gfx_control == TONGA_VOLTAGE_CONTROL_BY_SVID2) { |
| 422 | if (0 == tonga_get_sclk_for_voltage_evv(hwmgr, |
| 423 | pptable_info->vddgfx_lookup_table, virtual_voltage_id, &sclk)) { |
| 424 | if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, |
| 425 | PHM_PlatformCaps_ClockStretcher)) { |
| 426 | for (j = 1; j < sclk_table->count; j++) { |
| 427 | if (sclk_table->entries[j].clk == sclk && |
| 428 | sclk_table->entries[j].cks_enable == 0) { |
| 429 | sclk += 5000; |
| 430 | break; |
| 431 | } |
| 432 | } |
| 433 | } |
Moritz Kühner | ac0cc35 | 2016-04-17 16:15:24 +0200 | [diff] [blame] | 434 | if (0 == atomctrl_get_voltage_evv_on_sclk |
| 435 | (hwmgr, VOLTAGE_TYPE_VDDGFX, sclk, |
| 436 | virtual_voltage_id, &vddgfx)) { |
| 437 | /* need to make sure vddgfx is less than 2v or else, it could burn the ASIC. */ |
| 438 | PP_ASSERT_WITH_CODE((vddgfx < 2000 && vddgfx != 0), "Invalid VDDGFX value!", return -1); |
yanyang1 | c82baa2 | 2015-08-18 15:28:32 +0800 | [diff] [blame] | 439 | |
Moritz Kühner | ac0cc35 | 2016-04-17 16:15:24 +0200 | [diff] [blame] | 440 | /* the voltage should not be zero nor equal to leakage ID */ |
| 441 | if (vddgfx != 0 && vddgfx != virtual_voltage_id) { |
| 442 | data->vddcgfx_leakage.actual_voltage[data->vddcgfx_leakage.count] = vddgfx; |
| 443 | data->vddcgfx_leakage.leakage_id[data->vddcgfx_leakage.count] = virtual_voltage_id; |
| 444 | data->vddcgfx_leakage.count++; |
| 445 | } |
| 446 | } else { |
| 447 | printk("Error retrieving EVV voltage value!\n"); |
yanyang1 | c82baa2 | 2015-08-18 15:28:32 +0800 | [diff] [blame] | 448 | } |
| 449 | } |
| 450 | } else { |
| 451 | /* in merged mode we have only vddc EVV leakages */ |
| 452 | if (0 == tonga_get_sclk_for_voltage_evv(hwmgr, |
| 453 | pptable_info->vddc_lookup_table, |
| 454 | virtual_voltage_id, &sclk)) { |
Moritz Kühner | ac0cc35 | 2016-04-17 16:15:24 +0200 | [diff] [blame] | 455 | if (0 == atomctrl_get_voltage_evv_on_sclk |
| 456 | (hwmgr, VOLTAGE_TYPE_VDDC, sclk, |
| 457 | virtual_voltage_id, &vddc)) { |
| 458 | /* need to make sure vddc is less than 2v or else, it could burn the ASIC. */ |
| 459 | PP_ASSERT_WITH_CODE(vddc < 2000, "Invalid VDDC value!", return -1); |
yanyang1 | c82baa2 | 2015-08-18 15:28:32 +0800 | [diff] [blame] | 460 | |
Moritz Kühner | ac0cc35 | 2016-04-17 16:15:24 +0200 | [diff] [blame] | 461 | /* the voltage should not be zero nor equal to leakage ID */ |
| 462 | if (vddc != 0 && vddc != virtual_voltage_id) { |
| 463 | data->vddc_leakage.actual_voltage[data->vddc_leakage.count] = vddc; |
| 464 | data->vddc_leakage.leakage_id[data->vddc_leakage.count] = virtual_voltage_id; |
| 465 | data->vddc_leakage.count++; |
| 466 | } |
| 467 | } else { |
| 468 | printk("Error retrieving EVV voltage value!\n"); |
yanyang1 | c82baa2 | 2015-08-18 15:28:32 +0800 | [diff] [blame] | 469 | } |
| 470 | } |
| 471 | } |
| 472 | } |
| 473 | |
| 474 | return 0; |
| 475 | } |
| 476 | |
| 477 | int tonga_enable_sclk_mclk_dpm(struct pp_hwmgr *hwmgr) |
| 478 | { |
| 479 | tonga_hwmgr *data = (tonga_hwmgr *)(hwmgr->backend); |
| 480 | |
| 481 | /* enable SCLK dpm */ |
| 482 | if (0 == data->sclk_dpm_key_disabled) { |
| 483 | PP_ASSERT_WITH_CODE( |
| 484 | (0 == smum_send_msg_to_smc(hwmgr->smumgr, |
| 485 | PPSMC_MSG_DPM_Enable)), |
| 486 | "Failed to enable SCLK DPM during DPM Start Function!", |
| 487 | return -1); |
| 488 | } |
| 489 | |
| 490 | /* enable MCLK dpm */ |
| 491 | if (0 == data->mclk_dpm_key_disabled) { |
| 492 | PP_ASSERT_WITH_CODE( |
| 493 | (0 == smum_send_msg_to_smc(hwmgr->smumgr, |
| 494 | PPSMC_MSG_MCLKDPM_Enable)), |
| 495 | "Failed to enable MCLK DPM during DPM Start Function!", |
| 496 | return -1); |
| 497 | |
| 498 | PHM_WRITE_FIELD(hwmgr->device, MC_SEQ_CNTL_3, CAC_EN, 0x1); |
| 499 | |
| 500 | cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, |
| 501 | ixLCAC_MC0_CNTL, 0x05);/* CH0,1 read */ |
| 502 | cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, |
| 503 | ixLCAC_MC1_CNTL, 0x05);/* CH2,3 read */ |
| 504 | cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, |
| 505 | ixLCAC_CPL_CNTL, 0x100005);/*Read */ |
| 506 | |
| 507 | udelay(10); |
| 508 | |
| 509 | cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, |
| 510 | ixLCAC_MC0_CNTL, 0x400005);/* CH0,1 write */ |
| 511 | cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, |
| 512 | ixLCAC_MC1_CNTL, 0x400005);/* CH2,3 write */ |
| 513 | cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, |
| 514 | ixLCAC_CPL_CNTL, 0x500005);/* write */ |
| 515 | |
| 516 | } |
| 517 | |
| 518 | return 0; |
| 519 | } |
| 520 | |
| 521 | int tonga_start_dpm(struct pp_hwmgr *hwmgr) |
| 522 | { |
| 523 | tonga_hwmgr *data = (tonga_hwmgr *)(hwmgr->backend); |
| 524 | |
| 525 | /* enable general power management */ |
| 526 | PHM_WRITE_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, GENERAL_PWRMGT, GLOBAL_PWRMGT_EN, 1); |
| 527 | /* enable sclk deep sleep */ |
| 528 | PHM_WRITE_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, SCLK_PWRMGT_CNTL, DYNAMIC_PM_EN, 1); |
| 529 | |
| 530 | /* prepare for PCIE DPM */ |
| 531 | cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, data->soft_regs_start + |
| 532 | offsetof(SMU72_SoftRegisters, VoltageChangeTimeout), 0x1000); |
| 533 | |
| 534 | PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__PCIE, SWRST_COMMAND_1, RESETLC, 0x0); |
| 535 | |
| 536 | PP_ASSERT_WITH_CODE( |
| 537 | (0 == smum_send_msg_to_smc(hwmgr->smumgr, |
| 538 | PPSMC_MSG_Voltage_Cntl_Enable)), |
| 539 | "Failed to enable voltage DPM during DPM Start Function!", |
| 540 | return -1); |
| 541 | |
| 542 | if (0 != tonga_enable_sclk_mclk_dpm(hwmgr)) { |
| 543 | PP_ASSERT_WITH_CODE(0, "Failed to enable Sclk DPM and Mclk DPM!", return -1); |
| 544 | } |
| 545 | |
| 546 | /* enable PCIE dpm */ |
| 547 | if (0 == data->pcie_dpm_key_disabled) { |
| 548 | PP_ASSERT_WITH_CODE( |
| 549 | (0 == smum_send_msg_to_smc(hwmgr->smumgr, |
| 550 | PPSMC_MSG_PCIeDPM_Enable)), |
| 551 | "Failed to enable pcie DPM during DPM Start Function!", |
| 552 | return -1 |
| 553 | ); |
| 554 | } |
| 555 | |
| 556 | if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, |
| 557 | PHM_PlatformCaps_Falcon_QuickTransition)) { |
| 558 | smum_send_msg_to_smc(hwmgr->smumgr, |
| 559 | PPSMC_MSG_EnableACDCGPIOInterrupt); |
| 560 | } |
| 561 | |
| 562 | return 0; |
| 563 | } |
| 564 | |
| 565 | int tonga_disable_sclk_mclk_dpm(struct pp_hwmgr *hwmgr) |
| 566 | { |
| 567 | tonga_hwmgr *data = (tonga_hwmgr *)(hwmgr->backend); |
| 568 | |
| 569 | /* disable SCLK dpm */ |
| 570 | if (0 == data->sclk_dpm_key_disabled) { |
| 571 | /* Checking if DPM is running. If we discover hang because of this, we should skip this message.*/ |
| 572 | PP_ASSERT_WITH_CODE( |
Edward O'Callaghan | 4ba27f9 | 2016-07-12 10:17:56 +1000 | [diff] [blame] | 573 | !tonga_is_dpm_running(hwmgr), |
yanyang1 | c82baa2 | 2015-08-18 15:28:32 +0800 | [diff] [blame] | 574 | "Trying to Disable SCLK DPM when DPM is disabled", |
| 575 | return -1 |
| 576 | ); |
| 577 | |
| 578 | PP_ASSERT_WITH_CODE( |
| 579 | (0 == smum_send_msg_to_smc(hwmgr->smumgr, |
| 580 | PPSMC_MSG_DPM_Disable)), |
| 581 | "Failed to disable SCLK DPM during DPM stop Function!", |
| 582 | return -1); |
| 583 | } |
| 584 | |
| 585 | /* disable MCLK dpm */ |
| 586 | if (0 == data->mclk_dpm_key_disabled) { |
| 587 | /* Checking if DPM is running. If we discover hang because of this, we should skip this message. */ |
| 588 | PP_ASSERT_WITH_CODE( |
Edward O'Callaghan | 4ba27f9 | 2016-07-12 10:17:56 +1000 | [diff] [blame] | 589 | !tonga_is_dpm_running(hwmgr), |
yanyang1 | c82baa2 | 2015-08-18 15:28:32 +0800 | [diff] [blame] | 590 | "Trying to Disable MCLK DPM when DPM is disabled", |
| 591 | return -1 |
| 592 | ); |
| 593 | |
| 594 | PP_ASSERT_WITH_CODE( |
| 595 | (0 == smum_send_msg_to_smc(hwmgr->smumgr, |
| 596 | PPSMC_MSG_MCLKDPM_Disable)), |
| 597 | "Failed to Disable MCLK DPM during DPM stop Function!", |
| 598 | return -1); |
| 599 | } |
| 600 | |
| 601 | return 0; |
| 602 | } |
| 603 | |
| 604 | int tonga_stop_dpm(struct pp_hwmgr *hwmgr) |
| 605 | { |
| 606 | tonga_hwmgr *data = (tonga_hwmgr *)(hwmgr->backend); |
| 607 | |
| 608 | PHM_WRITE_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, GENERAL_PWRMGT, GLOBAL_PWRMGT_EN, 0); |
| 609 | /* disable sclk deep sleep*/ |
| 610 | PHM_WRITE_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, SCLK_PWRMGT_CNTL, DYNAMIC_PM_EN, 0); |
| 611 | |
| 612 | /* disable PCIE dpm */ |
| 613 | if (0 == data->pcie_dpm_key_disabled) { |
| 614 | /* Checking if DPM is running. If we discover hang because of this, we should skip this message.*/ |
| 615 | PP_ASSERT_WITH_CODE( |
Edward O'Callaghan | 4ba27f9 | 2016-07-12 10:17:56 +1000 | [diff] [blame] | 616 | !tonga_is_dpm_running(hwmgr), |
yanyang1 | c82baa2 | 2015-08-18 15:28:32 +0800 | [diff] [blame] | 617 | "Trying to Disable PCIE DPM when DPM is disabled", |
| 618 | return -1 |
| 619 | ); |
| 620 | PP_ASSERT_WITH_CODE( |
| 621 | (0 == smum_send_msg_to_smc(hwmgr->smumgr, |
| 622 | PPSMC_MSG_PCIeDPM_Disable)), |
| 623 | "Failed to disable pcie DPM during DPM stop Function!", |
| 624 | return -1); |
| 625 | } |
| 626 | |
| 627 | if (0 != tonga_disable_sclk_mclk_dpm(hwmgr)) |
| 628 | PP_ASSERT_WITH_CODE(0, "Failed to disable Sclk DPM and Mclk DPM!", return -1); |
| 629 | |
| 630 | /* Checking if DPM is running. If we discover hang because of this, we should skip this message.*/ |
| 631 | PP_ASSERT_WITH_CODE( |
Edward O'Callaghan | 4ba27f9 | 2016-07-12 10:17:56 +1000 | [diff] [blame] | 632 | !tonga_is_dpm_running(hwmgr), |
yanyang1 | c82baa2 | 2015-08-18 15:28:32 +0800 | [diff] [blame] | 633 | "Trying to Disable Voltage CNTL when DPM is disabled", |
| 634 | return -1 |
| 635 | ); |
| 636 | |
| 637 | PP_ASSERT_WITH_CODE( |
| 638 | (0 == smum_send_msg_to_smc(hwmgr->smumgr, |
| 639 | PPSMC_MSG_Voltage_Cntl_Disable)), |
| 640 | "Failed to disable voltage DPM during DPM stop Function!", |
| 641 | return -1); |
| 642 | |
| 643 | return 0; |
| 644 | } |
| 645 | |
| 646 | int tonga_enable_sclk_control(struct pp_hwmgr *hwmgr) |
| 647 | { |
| 648 | PHM_WRITE_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, SCLK_PWRMGT_CNTL, SCLK_PWRMGT_OFF, 0); |
| 649 | |
| 650 | return 0; |
| 651 | } |
| 652 | |
| 653 | /** |
| 654 | * Send a message to the SMC and return a parameter |
| 655 | * |
| 656 | * @param hwmgr: the address of the powerplay hardware manager. |
| 657 | * @param msg: the message to send. |
| 658 | * @param parameter: pointer to the received parameter |
| 659 | * @return The response that came from the SMC. |
| 660 | */ |
| 661 | PPSMC_Result tonga_send_msg_to_smc_return_parameter( |
| 662 | struct pp_hwmgr *hwmgr, |
| 663 | PPSMC_Msg msg, |
| 664 | uint32_t *parameter) |
| 665 | { |
| 666 | int result; |
| 667 | |
| 668 | result = smum_send_msg_to_smc(hwmgr->smumgr, msg); |
| 669 | |
| 670 | if ((0 == result) && parameter) { |
| 671 | *parameter = cgs_read_register(hwmgr->device, mmSMC_MSG_ARG_0); |
| 672 | } |
| 673 | |
| 674 | return result; |
| 675 | } |
| 676 | |
| 677 | /** |
| 678 | * force DPM power State |
| 679 | * |
| 680 | * @param hwmgr: the address of the powerplay hardware manager. |
| 681 | * @param n : DPM level |
| 682 | * @return The response that came from the SMC. |
| 683 | */ |
| 684 | int tonga_dpm_force_state(struct pp_hwmgr *hwmgr, uint32_t n) |
| 685 | { |
| 686 | tonga_hwmgr *data = (tonga_hwmgr *)(hwmgr->backend); |
| 687 | uint32_t level_mask = 1 << n; |
| 688 | |
| 689 | /* Checking if DPM is running. If we discover hang because of this, we should skip this message. */ |
Edward O'Callaghan | 4ba27f9 | 2016-07-12 10:17:56 +1000 | [diff] [blame] | 690 | PP_ASSERT_WITH_CODE(!tonga_is_dpm_running(hwmgr), |
| 691 | "Trying to force SCLK when DPM is disabled", |
| 692 | return -1;); |
yanyang1 | c82baa2 | 2015-08-18 15:28:32 +0800 | [diff] [blame] | 693 | if (0 == data->sclk_dpm_key_disabled) |
| 694 | return (0 == smum_send_msg_to_smc_with_parameter( |
| 695 | hwmgr->smumgr, |
| 696 | (PPSMC_Msg)(PPSMC_MSG_SCLKDPM_SetEnabledMask), |
| 697 | level_mask) ? 0 : 1); |
| 698 | |
| 699 | return 0; |
| 700 | } |
| 701 | |
| 702 | /** |
| 703 | * force DPM power State |
| 704 | * |
| 705 | * @param hwmgr: the address of the powerplay hardware manager. |
| 706 | * @param n : DPM level |
| 707 | * @return The response that came from the SMC. |
| 708 | */ |
| 709 | int tonga_dpm_force_state_mclk(struct pp_hwmgr *hwmgr, uint32_t n) |
| 710 | { |
| 711 | tonga_hwmgr *data = (tonga_hwmgr *)(hwmgr->backend); |
| 712 | uint32_t level_mask = 1 << n; |
| 713 | |
| 714 | /* Checking if DPM is running. If we discover hang because of this, we should skip this message. */ |
Edward O'Callaghan | 4ba27f9 | 2016-07-12 10:17:56 +1000 | [diff] [blame] | 715 | PP_ASSERT_WITH_CODE(!tonga_is_dpm_running(hwmgr), |
| 716 | "Trying to Force MCLK when DPM is disabled", |
| 717 | return -1;); |
yanyang1 | c82baa2 | 2015-08-18 15:28:32 +0800 | [diff] [blame] | 718 | if (0 == data->mclk_dpm_key_disabled) |
| 719 | return (0 == smum_send_msg_to_smc_with_parameter( |
| 720 | hwmgr->smumgr, |
| 721 | (PPSMC_Msg)(PPSMC_MSG_MCLKDPM_SetEnabledMask), |
| 722 | level_mask) ? 0 : 1); |
| 723 | |
| 724 | return 0; |
| 725 | } |
| 726 | |
| 727 | /** |
| 728 | * force DPM power State |
| 729 | * |
| 730 | * @param hwmgr: the address of the powerplay hardware manager. |
| 731 | * @param n : DPM level |
| 732 | * @return The response that came from the SMC. |
| 733 | */ |
| 734 | int tonga_dpm_force_state_pcie(struct pp_hwmgr *hwmgr, uint32_t n) |
| 735 | { |
| 736 | tonga_hwmgr *data = (tonga_hwmgr *)(hwmgr->backend); |
| 737 | |
| 738 | /* Checking if DPM is running. If we discover hang because of this, we should skip this message.*/ |
Edward O'Callaghan | 4ba27f9 | 2016-07-12 10:17:56 +1000 | [diff] [blame] | 739 | PP_ASSERT_WITH_CODE(!tonga_is_dpm_running(hwmgr), |
| 740 | "Trying to Force PCIE level when DPM is disabled", |
| 741 | return -1;); |
yanyang1 | c82baa2 | 2015-08-18 15:28:32 +0800 | [diff] [blame] | 742 | if (0 == data->pcie_dpm_key_disabled) |
| 743 | return (0 == smum_send_msg_to_smc_with_parameter( |
| 744 | hwmgr->smumgr, |
| 745 | (PPSMC_Msg)(PPSMC_MSG_PCIeDPM_ForceLevel), |
| 746 | n) ? 0 : 1); |
| 747 | |
| 748 | return 0; |
| 749 | } |
| 750 | |
| 751 | /** |
| 752 | * Set the initial state by calling SMC to switch to this state directly |
| 753 | * |
| 754 | * @param hwmgr the address of the powerplay hardware manager. |
| 755 | * @return always 0 |
| 756 | */ |
| 757 | int tonga_set_boot_state(struct pp_hwmgr *hwmgr) |
| 758 | { |
| 759 | /* |
| 760 | * SMC only stores one state that SW will ask to switch too, |
| 761 | * so we switch the the just uploaded one |
| 762 | */ |
| 763 | return (0 == tonga_disable_sclk_mclk_dpm(hwmgr)) ? 0 : 1; |
| 764 | } |
| 765 | |
| 766 | /** |
| 767 | * Get the location of various tables inside the FW image. |
| 768 | * |
| 769 | * @param hwmgr the address of the powerplay hardware manager. |
| 770 | * @return always 0 |
| 771 | */ |
| 772 | int tonga_process_firmware_header(struct pp_hwmgr *hwmgr) |
| 773 | { |
| 774 | tonga_hwmgr *data = (tonga_hwmgr *)(hwmgr->backend); |
| 775 | struct tonga_smumgr *tonga_smu = (struct tonga_smumgr *)(hwmgr->smumgr->backend); |
| 776 | |
| 777 | uint32_t tmp; |
| 778 | int result; |
Edward O'Callaghan | ed5121a | 2016-07-12 10:17:52 +1000 | [diff] [blame] | 779 | bool error = false; |
yanyang1 | c82baa2 | 2015-08-18 15:28:32 +0800 | [diff] [blame] | 780 | |
| 781 | result = tonga_read_smc_sram_dword(hwmgr->smumgr, |
| 782 | SMU72_FIRMWARE_HEADER_LOCATION + |
| 783 | offsetof(SMU72_Firmware_Header, DpmTable), |
| 784 | &tmp, data->sram_end); |
| 785 | |
| 786 | if (0 == result) { |
| 787 | data->dpm_table_start = tmp; |
| 788 | } |
| 789 | |
| 790 | error |= (0 != result); |
| 791 | |
| 792 | result = tonga_read_smc_sram_dword(hwmgr->smumgr, |
| 793 | SMU72_FIRMWARE_HEADER_LOCATION + |
| 794 | offsetof(SMU72_Firmware_Header, SoftRegisters), |
| 795 | &tmp, data->sram_end); |
| 796 | |
| 797 | if (0 == result) { |
| 798 | data->soft_regs_start = tmp; |
| 799 | tonga_smu->ulSoftRegsStart = tmp; |
| 800 | } |
| 801 | |
| 802 | error |= (0 != result); |
| 803 | |
| 804 | |
| 805 | result = tonga_read_smc_sram_dword(hwmgr->smumgr, |
| 806 | SMU72_FIRMWARE_HEADER_LOCATION + |
| 807 | offsetof(SMU72_Firmware_Header, mcRegisterTable), |
| 808 | &tmp, data->sram_end); |
| 809 | |
| 810 | if (0 == result) { |
| 811 | data->mc_reg_table_start = tmp; |
| 812 | } |
| 813 | |
| 814 | result = tonga_read_smc_sram_dword(hwmgr->smumgr, |
| 815 | SMU72_FIRMWARE_HEADER_LOCATION + |
| 816 | offsetof(SMU72_Firmware_Header, FanTable), |
| 817 | &tmp, data->sram_end); |
| 818 | |
| 819 | if (0 == result) { |
| 820 | data->fan_table_start = tmp; |
| 821 | } |
| 822 | |
| 823 | error |= (0 != result); |
| 824 | |
| 825 | result = tonga_read_smc_sram_dword(hwmgr->smumgr, |
| 826 | SMU72_FIRMWARE_HEADER_LOCATION + |
| 827 | offsetof(SMU72_Firmware_Header, mcArbDramTimingTable), |
| 828 | &tmp, data->sram_end); |
| 829 | |
| 830 | if (0 == result) { |
| 831 | data->arb_table_start = tmp; |
| 832 | } |
| 833 | |
| 834 | error |= (0 != result); |
| 835 | |
| 836 | |
| 837 | result = tonga_read_smc_sram_dword(hwmgr->smumgr, |
| 838 | SMU72_FIRMWARE_HEADER_LOCATION + |
| 839 | offsetof(SMU72_Firmware_Header, Version), |
| 840 | &tmp, data->sram_end); |
| 841 | |
| 842 | if (0 == result) { |
| 843 | hwmgr->microcode_version_info.SMC = tmp; |
| 844 | } |
| 845 | |
| 846 | error |= (0 != result); |
| 847 | |
| 848 | return error ? 1 : 0; |
| 849 | } |
| 850 | |
| 851 | /** |
| 852 | * Read clock related registers. |
| 853 | * |
| 854 | * @param hwmgr the address of the powerplay hardware manager. |
| 855 | * @return always 0 |
| 856 | */ |
| 857 | int tonga_read_clock_registers(struct pp_hwmgr *hwmgr) |
| 858 | { |
| 859 | tonga_hwmgr *data = (tonga_hwmgr *)(hwmgr->backend); |
| 860 | |
| 861 | data->clock_registers.vCG_SPLL_FUNC_CNTL = |
| 862 | cgs_read_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixCG_SPLL_FUNC_CNTL); |
| 863 | data->clock_registers.vCG_SPLL_FUNC_CNTL_2 = |
| 864 | cgs_read_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixCG_SPLL_FUNC_CNTL_2); |
| 865 | data->clock_registers.vCG_SPLL_FUNC_CNTL_3 = |
| 866 | cgs_read_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixCG_SPLL_FUNC_CNTL_3); |
| 867 | data->clock_registers.vCG_SPLL_FUNC_CNTL_4 = |
| 868 | cgs_read_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixCG_SPLL_FUNC_CNTL_4); |
| 869 | data->clock_registers.vCG_SPLL_SPREAD_SPECTRUM = |
| 870 | cgs_read_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixCG_SPLL_SPREAD_SPECTRUM); |
| 871 | data->clock_registers.vCG_SPLL_SPREAD_SPECTRUM_2 = |
| 872 | cgs_read_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixCG_SPLL_SPREAD_SPECTRUM_2); |
| 873 | data->clock_registers.vDLL_CNTL = |
| 874 | cgs_read_register(hwmgr->device, mmDLL_CNTL); |
| 875 | data->clock_registers.vMCLK_PWRMGT_CNTL = |
| 876 | cgs_read_register(hwmgr->device, mmMCLK_PWRMGT_CNTL); |
| 877 | data->clock_registers.vMPLL_AD_FUNC_CNTL = |
| 878 | cgs_read_register(hwmgr->device, mmMPLL_AD_FUNC_CNTL); |
| 879 | data->clock_registers.vMPLL_DQ_FUNC_CNTL = |
| 880 | cgs_read_register(hwmgr->device, mmMPLL_DQ_FUNC_CNTL); |
| 881 | data->clock_registers.vMPLL_FUNC_CNTL = |
| 882 | cgs_read_register(hwmgr->device, mmMPLL_FUNC_CNTL); |
| 883 | data->clock_registers.vMPLL_FUNC_CNTL_1 = |
| 884 | cgs_read_register(hwmgr->device, mmMPLL_FUNC_CNTL_1); |
| 885 | data->clock_registers.vMPLL_FUNC_CNTL_2 = |
| 886 | cgs_read_register(hwmgr->device, mmMPLL_FUNC_CNTL_2); |
| 887 | data->clock_registers.vMPLL_SS1 = |
| 888 | cgs_read_register(hwmgr->device, mmMPLL_SS1); |
| 889 | data->clock_registers.vMPLL_SS2 = |
| 890 | cgs_read_register(hwmgr->device, mmMPLL_SS2); |
| 891 | |
| 892 | return 0; |
| 893 | } |
| 894 | |
| 895 | /** |
| 896 | * Find out if memory is GDDR5. |
| 897 | * |
| 898 | * @param hwmgr the address of the powerplay hardware manager. |
| 899 | * @return always 0 |
| 900 | */ |
| 901 | int tonga_get_memory_type(struct pp_hwmgr *hwmgr) |
| 902 | { |
| 903 | tonga_hwmgr *data = (tonga_hwmgr *)(hwmgr->backend); |
| 904 | uint32_t temp; |
| 905 | |
| 906 | temp = cgs_read_register(hwmgr->device, mmMC_SEQ_MISC0); |
| 907 | |
| 908 | data->is_memory_GDDR5 = (MC_SEQ_MISC0_GDDR5_VALUE == |
| 909 | ((temp & MC_SEQ_MISC0_GDDR5_MASK) >> |
| 910 | MC_SEQ_MISC0_GDDR5_SHIFT)); |
| 911 | |
| 912 | return 0; |
| 913 | } |
| 914 | |
| 915 | /** |
| 916 | * Enables Dynamic Power Management by SMC |
| 917 | * |
| 918 | * @param hwmgr the address of the powerplay hardware manager. |
| 919 | * @return always 0 |
| 920 | */ |
| 921 | int tonga_enable_acpi_power_management(struct pp_hwmgr *hwmgr) |
| 922 | { |
| 923 | PHM_WRITE_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, GENERAL_PWRMGT, STATIC_PM_EN, 1); |
| 924 | |
| 925 | return 0; |
| 926 | } |
| 927 | |
| 928 | /** |
| 929 | * Initialize PowerGating States for different engines |
| 930 | * |
| 931 | * @param hwmgr the address of the powerplay hardware manager. |
| 932 | * @return always 0 |
| 933 | */ |
| 934 | int tonga_init_power_gate_state(struct pp_hwmgr *hwmgr) |
| 935 | { |
| 936 | tonga_hwmgr *data = (tonga_hwmgr *)(hwmgr->backend); |
| 937 | |
Edward O'Callaghan | ed5121a | 2016-07-12 10:17:52 +1000 | [diff] [blame] | 938 | data->uvd_power_gated = false; |
| 939 | data->vce_power_gated = false; |
| 940 | data->samu_power_gated = false; |
| 941 | data->acp_power_gated = false; |
| 942 | data->pg_acp_init = true; |
yanyang1 | c82baa2 | 2015-08-18 15:28:32 +0800 | [diff] [blame] | 943 | |
| 944 | return 0; |
| 945 | } |
| 946 | |
| 947 | /** |
| 948 | * Checks if DPM is enabled |
| 949 | * |
| 950 | * @param hwmgr the address of the powerplay hardware manager. |
| 951 | * @return always 0 |
| 952 | */ |
| 953 | int tonga_check_for_dpm_running(struct pp_hwmgr *hwmgr) |
| 954 | { |
| 955 | /* |
| 956 | * We return the status of Voltage Control instead of checking SCLK/MCLK DPM |
| 957 | * because we may have test scenarios that need us intentionly disable SCLK/MCLK DPM, |
| 958 | * whereas voltage control is a fundemental change that will not be disabled |
| 959 | */ |
Edward O'Callaghan | 4ba27f9 | 2016-07-12 10:17:56 +1000 | [diff] [blame] | 960 | return (!tonga_is_dpm_running(hwmgr) ? 0 : 1); |
yanyang1 | c82baa2 | 2015-08-18 15:28:32 +0800 | [diff] [blame] | 961 | } |
| 962 | |
| 963 | /** |
| 964 | * Checks if DPM is stopped |
| 965 | * |
| 966 | * @param hwmgr the address of the powerplay hardware manager. |
| 967 | * @return always 0 |
| 968 | */ |
| 969 | int tonga_check_for_dpm_stopped(struct pp_hwmgr *hwmgr) |
| 970 | { |
| 971 | tonga_hwmgr *data = (tonga_hwmgr *)(hwmgr->backend); |
| 972 | |
Edward O'Callaghan | 4ba27f9 | 2016-07-12 10:17:56 +1000 | [diff] [blame] | 973 | if (tonga_is_dpm_running(hwmgr)) { |
yanyang1 | c82baa2 | 2015-08-18 15:28:32 +0800 | [diff] [blame] | 974 | /* If HW Virtualization is enabled, dpm_table_start will not have a valid value */ |
| 975 | if (!data->dpm_table_start) { |
| 976 | return 1; |
| 977 | } |
| 978 | } |
| 979 | |
| 980 | return 0; |
| 981 | } |
| 982 | |
| 983 | /** |
| 984 | * Remove repeated voltage values and create table with unique values. |
| 985 | * |
| 986 | * @param hwmgr the address of the powerplay hardware manager. |
| 987 | * @param voltage_table the pointer to changing voltage table |
| 988 | * @return 1 in success |
| 989 | */ |
| 990 | |
| 991 | static int tonga_trim_voltage_table(struct pp_hwmgr *hwmgr, |
| 992 | pp_atomctrl_voltage_table *voltage_table) |
| 993 | { |
| 994 | uint32_t table_size, i, j; |
| 995 | uint16_t vvalue; |
Edward O'Callaghan | ed5121a | 2016-07-12 10:17:52 +1000 | [diff] [blame] | 996 | bool bVoltageFound = false; |
yanyang1 | c82baa2 | 2015-08-18 15:28:32 +0800 | [diff] [blame] | 997 | pp_atomctrl_voltage_table *table; |
| 998 | |
| 999 | PP_ASSERT_WITH_CODE((NULL != voltage_table), "Voltage Table empty.", return -1;); |
| 1000 | table_size = sizeof(pp_atomctrl_voltage_table); |
| 1001 | table = kzalloc(table_size, GFP_KERNEL); |
| 1002 | |
| 1003 | if (NULL == table) |
| 1004 | return -ENOMEM; |
| 1005 | |
| 1006 | memset(table, 0x00, table_size); |
| 1007 | table->mask_low = voltage_table->mask_low; |
| 1008 | table->phase_delay = voltage_table->phase_delay; |
| 1009 | |
| 1010 | for (i = 0; i < voltage_table->count; i++) { |
| 1011 | vvalue = voltage_table->entries[i].value; |
Edward O'Callaghan | ed5121a | 2016-07-12 10:17:52 +1000 | [diff] [blame] | 1012 | bVoltageFound = false; |
yanyang1 | c82baa2 | 2015-08-18 15:28:32 +0800 | [diff] [blame] | 1013 | |
| 1014 | for (j = 0; j < table->count; j++) { |
| 1015 | if (vvalue == table->entries[j].value) { |
Edward O'Callaghan | ed5121a | 2016-07-12 10:17:52 +1000 | [diff] [blame] | 1016 | bVoltageFound = true; |
yanyang1 | c82baa2 | 2015-08-18 15:28:32 +0800 | [diff] [blame] | 1017 | break; |
| 1018 | } |
| 1019 | } |
| 1020 | |
| 1021 | if (!bVoltageFound) { |
| 1022 | table->entries[table->count].value = vvalue; |
| 1023 | table->entries[table->count].smio_low = |
| 1024 | voltage_table->entries[i].smio_low; |
| 1025 | table->count++; |
| 1026 | } |
| 1027 | } |
| 1028 | |
| 1029 | memcpy(table, voltage_table, sizeof(pp_atomctrl_voltage_table)); |
| 1030 | |
| 1031 | kfree(table); |
| 1032 | |
| 1033 | return 0; |
| 1034 | } |
| 1035 | |
| 1036 | static int tonga_get_svi2_vdd_ci_voltage_table( |
| 1037 | struct pp_hwmgr *hwmgr, |
| 1038 | phm_ppt_v1_clock_voltage_dependency_table *voltage_dependency_table) |
| 1039 | { |
| 1040 | uint32_t i; |
| 1041 | int result; |
| 1042 | tonga_hwmgr *data = (tonga_hwmgr *)(hwmgr->backend); |
| 1043 | pp_atomctrl_voltage_table *vddci_voltage_table = &(data->vddci_voltage_table); |
| 1044 | |
| 1045 | PP_ASSERT_WITH_CODE((0 != voltage_dependency_table->count), |
| 1046 | "Voltage Dependency Table empty.", return -1;); |
| 1047 | |
| 1048 | vddci_voltage_table->mask_low = 0; |
| 1049 | vddci_voltage_table->phase_delay = 0; |
| 1050 | vddci_voltage_table->count = voltage_dependency_table->count; |
| 1051 | |
| 1052 | for (i = 0; i < voltage_dependency_table->count; i++) { |
| 1053 | vddci_voltage_table->entries[i].value = |
| 1054 | voltage_dependency_table->entries[i].vddci; |
| 1055 | vddci_voltage_table->entries[i].smio_low = 0; |
| 1056 | } |
| 1057 | |
| 1058 | result = tonga_trim_voltage_table(hwmgr, vddci_voltage_table); |
| 1059 | PP_ASSERT_WITH_CODE((0 == result), |
| 1060 | "Failed to trim VDDCI table.", return result;); |
| 1061 | |
| 1062 | return 0; |
| 1063 | } |
| 1064 | |
| 1065 | |
| 1066 | |
| 1067 | static int tonga_get_svi2_vdd_voltage_table( |
| 1068 | struct pp_hwmgr *hwmgr, |
| 1069 | phm_ppt_v1_voltage_lookup_table *look_up_table, |
| 1070 | pp_atomctrl_voltage_table *voltage_table) |
| 1071 | { |
| 1072 | uint8_t i = 0; |
| 1073 | |
| 1074 | PP_ASSERT_WITH_CODE((0 != look_up_table->count), |
| 1075 | "Voltage Lookup Table empty.", return -1;); |
| 1076 | |
| 1077 | voltage_table->mask_low = 0; |
| 1078 | voltage_table->phase_delay = 0; |
| 1079 | |
| 1080 | voltage_table->count = look_up_table->count; |
| 1081 | |
| 1082 | for (i = 0; i < voltage_table->count; i++) { |
| 1083 | voltage_table->entries[i].value = look_up_table->entries[i].us_vdd; |
| 1084 | voltage_table->entries[i].smio_low = 0; |
| 1085 | } |
| 1086 | |
| 1087 | return 0; |
| 1088 | } |
| 1089 | |
| 1090 | /* |
| 1091 | * -------------------------------------------------------- Voltage Tables -------------------------------------------------------------------------- |
| 1092 | * If the voltage table would be bigger than what will fit into the state table on the SMC keep only the higher entries. |
| 1093 | */ |
| 1094 | |
| 1095 | static void tonga_trim_voltage_table_to_fit_state_table( |
| 1096 | struct pp_hwmgr *hwmgr, |
| 1097 | uint32_t max_voltage_steps, |
| 1098 | pp_atomctrl_voltage_table *voltage_table) |
| 1099 | { |
| 1100 | unsigned int i, diff; |
| 1101 | |
| 1102 | if (voltage_table->count <= max_voltage_steps) { |
| 1103 | return; |
| 1104 | } |
| 1105 | |
| 1106 | diff = voltage_table->count - max_voltage_steps; |
| 1107 | |
| 1108 | for (i = 0; i < max_voltage_steps; i++) { |
| 1109 | voltage_table->entries[i] = voltage_table->entries[i + diff]; |
| 1110 | } |
| 1111 | |
| 1112 | voltage_table->count = max_voltage_steps; |
| 1113 | |
| 1114 | return; |
| 1115 | } |
| 1116 | |
| 1117 | /** |
| 1118 | * Create Voltage Tables. |
| 1119 | * |
| 1120 | * @param hwmgr the address of the powerplay hardware manager. |
| 1121 | * @return always 0 |
| 1122 | */ |
| 1123 | int tonga_construct_voltage_tables(struct pp_hwmgr *hwmgr) |
| 1124 | { |
| 1125 | tonga_hwmgr *data = (tonga_hwmgr *)(hwmgr->backend); |
| 1126 | struct phm_ppt_v1_information *pptable_info = (struct phm_ppt_v1_information *)(hwmgr->pptable); |
| 1127 | int result; |
| 1128 | |
| 1129 | /* MVDD has only GPIO voltage control */ |
| 1130 | if (TONGA_VOLTAGE_CONTROL_BY_GPIO == data->mvdd_control) { |
| 1131 | result = atomctrl_get_voltage_table_v3(hwmgr, |
| 1132 | VOLTAGE_TYPE_MVDDC, VOLTAGE_OBJ_GPIO_LUT, &(data->mvdd_voltage_table)); |
| 1133 | PP_ASSERT_WITH_CODE((0 == result), |
| 1134 | "Failed to retrieve MVDD table.", return result;); |
| 1135 | } |
| 1136 | |
| 1137 | if (TONGA_VOLTAGE_CONTROL_BY_GPIO == data->vdd_ci_control) { |
| 1138 | /* GPIO voltage */ |
| 1139 | result = atomctrl_get_voltage_table_v3(hwmgr, |
| 1140 | VOLTAGE_TYPE_VDDCI, VOLTAGE_OBJ_GPIO_LUT, &(data->vddci_voltage_table)); |
| 1141 | PP_ASSERT_WITH_CODE((0 == result), |
| 1142 | "Failed to retrieve VDDCI table.", return result;); |
| 1143 | } else if (TONGA_VOLTAGE_CONTROL_BY_SVID2 == data->vdd_ci_control) { |
| 1144 | /* SVI2 voltage */ |
| 1145 | result = tonga_get_svi2_vdd_ci_voltage_table(hwmgr, |
| 1146 | pptable_info->vdd_dep_on_mclk); |
| 1147 | PP_ASSERT_WITH_CODE((0 == result), |
| 1148 | "Failed to retrieve SVI2 VDDCI table from dependancy table.", return result;); |
| 1149 | } |
| 1150 | |
| 1151 | if (TONGA_VOLTAGE_CONTROL_BY_SVID2 == data->vdd_gfx_control) { |
| 1152 | /* VDDGFX has only SVI2 voltage control */ |
| 1153 | result = tonga_get_svi2_vdd_voltage_table(hwmgr, |
| 1154 | pptable_info->vddgfx_lookup_table, &(data->vddgfx_voltage_table)); |
| 1155 | PP_ASSERT_WITH_CODE((0 == result), |
| 1156 | "Failed to retrieve SVI2 VDDGFX table from lookup table.", return result;); |
| 1157 | } |
| 1158 | |
| 1159 | if (TONGA_VOLTAGE_CONTROL_BY_SVID2 == data->voltage_control) { |
| 1160 | /* VDDC has only SVI2 voltage control */ |
| 1161 | result = tonga_get_svi2_vdd_voltage_table(hwmgr, |
| 1162 | pptable_info->vddc_lookup_table, &(data->vddc_voltage_table)); |
| 1163 | PP_ASSERT_WITH_CODE((0 == result), |
| 1164 | "Failed to retrieve SVI2 VDDC table from lookup table.", return result;); |
| 1165 | } |
| 1166 | |
| 1167 | PP_ASSERT_WITH_CODE( |
| 1168 | (data->vddc_voltage_table.count <= (SMU72_MAX_LEVELS_VDDC)), |
| 1169 | "Too many voltage values for VDDC. Trimming to fit state table.", |
| 1170 | tonga_trim_voltage_table_to_fit_state_table(hwmgr, |
| 1171 | SMU72_MAX_LEVELS_VDDC, &(data->vddc_voltage_table)); |
| 1172 | ); |
| 1173 | |
| 1174 | PP_ASSERT_WITH_CODE( |
| 1175 | (data->vddgfx_voltage_table.count <= (SMU72_MAX_LEVELS_VDDGFX)), |
| 1176 | "Too many voltage values for VDDGFX. Trimming to fit state table.", |
| 1177 | tonga_trim_voltage_table_to_fit_state_table(hwmgr, |
| 1178 | SMU72_MAX_LEVELS_VDDGFX, &(data->vddgfx_voltage_table)); |
| 1179 | ); |
| 1180 | |
| 1181 | PP_ASSERT_WITH_CODE( |
| 1182 | (data->vddci_voltage_table.count <= (SMU72_MAX_LEVELS_VDDCI)), |
| 1183 | "Too many voltage values for VDDCI. Trimming to fit state table.", |
| 1184 | tonga_trim_voltage_table_to_fit_state_table(hwmgr, |
| 1185 | SMU72_MAX_LEVELS_VDDCI, &(data->vddci_voltage_table)); |
| 1186 | ); |
| 1187 | |
| 1188 | PP_ASSERT_WITH_CODE( |
| 1189 | (data->mvdd_voltage_table.count <= (SMU72_MAX_LEVELS_MVDD)), |
| 1190 | "Too many voltage values for MVDD. Trimming to fit state table.", |
| 1191 | tonga_trim_voltage_table_to_fit_state_table(hwmgr, |
| 1192 | SMU72_MAX_LEVELS_MVDD, &(data->mvdd_voltage_table)); |
| 1193 | ); |
| 1194 | |
| 1195 | return 0; |
| 1196 | } |
| 1197 | |
| 1198 | /** |
| 1199 | * Vddc table preparation for SMC. |
| 1200 | * |
| 1201 | * @param hwmgr the address of the hardware manager |
| 1202 | * @param table the SMC DPM table structure to be populated |
| 1203 | * @return always 0 |
| 1204 | */ |
| 1205 | static int tonga_populate_smc_vddc_table(struct pp_hwmgr *hwmgr, |
| 1206 | SMU72_Discrete_DpmTable *table) |
| 1207 | { |
| 1208 | unsigned int count; |
| 1209 | tonga_hwmgr *data = (tonga_hwmgr *)(hwmgr->backend); |
| 1210 | |
| 1211 | if (TONGA_VOLTAGE_CONTROL_BY_SVID2 == data->voltage_control) { |
| 1212 | table->VddcLevelCount = data->vddc_voltage_table.count; |
| 1213 | for (count = 0; count < table->VddcLevelCount; count++) { |
| 1214 | table->VddcTable[count] = |
| 1215 | PP_HOST_TO_SMC_US(data->vddc_voltage_table.entries[count].value * VOLTAGE_SCALE); |
| 1216 | } |
| 1217 | CONVERT_FROM_HOST_TO_SMC_UL(table->VddcLevelCount); |
| 1218 | } |
| 1219 | return 0; |
| 1220 | } |
| 1221 | |
| 1222 | /** |
| 1223 | * VddGfx table preparation for SMC. |
| 1224 | * |
| 1225 | * @param hwmgr the address of the hardware manager |
| 1226 | * @param table the SMC DPM table structure to be populated |
| 1227 | * @return always 0 |
| 1228 | */ |
| 1229 | static int tonga_populate_smc_vdd_gfx_table(struct pp_hwmgr *hwmgr, |
| 1230 | SMU72_Discrete_DpmTable *table) |
| 1231 | { |
| 1232 | unsigned int count; |
| 1233 | tonga_hwmgr *data = (tonga_hwmgr *)(hwmgr->backend); |
| 1234 | |
| 1235 | if (TONGA_VOLTAGE_CONTROL_BY_SVID2 == data->vdd_gfx_control) { |
| 1236 | table->VddGfxLevelCount = data->vddgfx_voltage_table.count; |
| 1237 | for (count = 0; count < data->vddgfx_voltage_table.count; count++) { |
| 1238 | table->VddGfxTable[count] = |
| 1239 | PP_HOST_TO_SMC_US(data->vddgfx_voltage_table.entries[count].value * VOLTAGE_SCALE); |
| 1240 | } |
| 1241 | CONVERT_FROM_HOST_TO_SMC_UL(table->VddGfxLevelCount); |
| 1242 | } |
| 1243 | return 0; |
| 1244 | } |
| 1245 | |
| 1246 | /** |
| 1247 | * Vddci table preparation for SMC. |
| 1248 | * |
| 1249 | * @param *hwmgr The address of the hardware manager. |
| 1250 | * @param *table The SMC DPM table structure to be populated. |
| 1251 | * @return 0 |
| 1252 | */ |
| 1253 | static int tonga_populate_smc_vdd_ci_table(struct pp_hwmgr *hwmgr, |
| 1254 | SMU72_Discrete_DpmTable *table) |
| 1255 | { |
| 1256 | tonga_hwmgr *data = (tonga_hwmgr *)(hwmgr->backend); |
| 1257 | uint32_t count; |
| 1258 | |
| 1259 | table->VddciLevelCount = data->vddci_voltage_table.count; |
| 1260 | for (count = 0; count < table->VddciLevelCount; count++) { |
| 1261 | if (TONGA_VOLTAGE_CONTROL_BY_SVID2 == data->vdd_ci_control) { |
| 1262 | table->VddciTable[count] = |
| 1263 | PP_HOST_TO_SMC_US(data->vddci_voltage_table.entries[count].value * VOLTAGE_SCALE); |
| 1264 | } else if (TONGA_VOLTAGE_CONTROL_BY_GPIO == data->vdd_ci_control) { |
| 1265 | table->SmioTable1.Pattern[count].Voltage = |
| 1266 | PP_HOST_TO_SMC_US(data->vddci_voltage_table.entries[count].value * VOLTAGE_SCALE); |
| 1267 | /* Index into DpmTable.Smio. Drive bits from Smio entry to get this voltage level. */ |
| 1268 | table->SmioTable1.Pattern[count].Smio = |
| 1269 | (uint8_t) count; |
| 1270 | table->Smio[count] |= |
| 1271 | data->vddci_voltage_table.entries[count].smio_low; |
| 1272 | table->VddciTable[count] = |
| 1273 | PP_HOST_TO_SMC_US(data->vddci_voltage_table.entries[count].value * VOLTAGE_SCALE); |
| 1274 | } |
| 1275 | } |
| 1276 | |
| 1277 | table->SmioMask1 = data->vddci_voltage_table.mask_low; |
| 1278 | CONVERT_FROM_HOST_TO_SMC_UL(table->VddciLevelCount); |
| 1279 | |
| 1280 | return 0; |
| 1281 | } |
| 1282 | |
| 1283 | /** |
| 1284 | * Mvdd table preparation for SMC. |
| 1285 | * |
| 1286 | * @param *hwmgr The address of the hardware manager. |
| 1287 | * @param *table The SMC DPM table structure to be populated. |
| 1288 | * @return 0 |
| 1289 | */ |
| 1290 | static int tonga_populate_smc_mvdd_table(struct pp_hwmgr *hwmgr, |
| 1291 | SMU72_Discrete_DpmTable *table) |
| 1292 | { |
| 1293 | tonga_hwmgr *data = (tonga_hwmgr *)(hwmgr->backend); |
| 1294 | uint32_t count; |
| 1295 | |
| 1296 | if (TONGA_VOLTAGE_CONTROL_BY_GPIO == data->mvdd_control) { |
| 1297 | table->MvddLevelCount = data->mvdd_voltage_table.count; |
| 1298 | for (count = 0; count < table->MvddLevelCount; count++) { |
| 1299 | table->SmioTable2.Pattern[count].Voltage = |
| 1300 | PP_HOST_TO_SMC_US(data->mvdd_voltage_table.entries[count].value * VOLTAGE_SCALE); |
| 1301 | /* Index into DpmTable.Smio. Drive bits from Smio entry to get this voltage level.*/ |
| 1302 | table->SmioTable2.Pattern[count].Smio = |
| 1303 | (uint8_t) count; |
| 1304 | table->Smio[count] |= |
| 1305 | data->mvdd_voltage_table.entries[count].smio_low; |
| 1306 | } |
Huang Rui | 1dfefee | 2016-07-06 09:32:24 +0800 | [diff] [blame] | 1307 | table->SmioMask2 = data->mvdd_voltage_table.mask_low; |
yanyang1 | c82baa2 | 2015-08-18 15:28:32 +0800 | [diff] [blame] | 1308 | |
| 1309 | CONVERT_FROM_HOST_TO_SMC_UL(table->MvddLevelCount); |
| 1310 | } |
| 1311 | |
| 1312 | return 0; |
| 1313 | } |
| 1314 | |
| 1315 | /** |
| 1316 | * Convert a voltage value in mv unit to VID number required by SMU firmware |
| 1317 | */ |
| 1318 | static uint8_t convert_to_vid(uint16_t vddc) |
| 1319 | { |
| 1320 | return (uint8_t) ((6200 - (vddc * VOLTAGE_SCALE)) / 25); |
| 1321 | } |
| 1322 | |
| 1323 | |
| 1324 | /** |
| 1325 | * Preparation of vddc and vddgfx CAC tables for SMC. |
| 1326 | * |
| 1327 | * @param hwmgr the address of the hardware manager |
| 1328 | * @param table the SMC DPM table structure to be populated |
| 1329 | * @return always 0 |
| 1330 | */ |
| 1331 | static int tonga_populate_cac_tables(struct pp_hwmgr *hwmgr, |
| 1332 | SMU72_Discrete_DpmTable *table) |
| 1333 | { |
| 1334 | uint32_t count; |
| 1335 | uint8_t index; |
yanyang1 | c82baa2 | 2015-08-18 15:28:32 +0800 | [diff] [blame] | 1336 | tonga_hwmgr *data = (tonga_hwmgr *)(hwmgr->backend); |
| 1337 | struct phm_ppt_v1_information *pptable_info = (struct phm_ppt_v1_information *)(hwmgr->pptable); |
| 1338 | struct phm_ppt_v1_voltage_lookup_table *vddgfx_lookup_table = pptable_info->vddgfx_lookup_table; |
| 1339 | struct phm_ppt_v1_voltage_lookup_table *vddc_lookup_table = pptable_info->vddc_lookup_table; |
| 1340 | |
| 1341 | /* pTables is already swapped, so in order to use the value from it, we need to swap it back. */ |
| 1342 | uint32_t vddcLevelCount = PP_SMC_TO_HOST_UL(table->VddcLevelCount); |
| 1343 | uint32_t vddgfxLevelCount = PP_SMC_TO_HOST_UL(table->VddGfxLevelCount); |
| 1344 | |
| 1345 | for (count = 0; count < vddcLevelCount; count++) { |
| 1346 | /* We are populating vddc CAC data to BapmVddc table in split and merged mode */ |
| 1347 | index = tonga_get_voltage_index(vddc_lookup_table, |
| 1348 | data->vddc_voltage_table.entries[count].value); |
| 1349 | table->BapmVddcVidLoSidd[count] = |
| 1350 | convert_to_vid(vddc_lookup_table->entries[index].us_cac_low); |
| 1351 | table->BapmVddcVidHiSidd[count] = |
| 1352 | convert_to_vid(vddc_lookup_table->entries[index].us_cac_mid); |
| 1353 | table->BapmVddcVidHiSidd2[count] = |
| 1354 | convert_to_vid(vddc_lookup_table->entries[index].us_cac_high); |
| 1355 | } |
| 1356 | |
| 1357 | if ((data->vdd_gfx_control == TONGA_VOLTAGE_CONTROL_BY_SVID2)) { |
| 1358 | /* We are populating vddgfx CAC data to BapmVddgfx table in split mode */ |
| 1359 | for (count = 0; count < vddgfxLevelCount; count++) { |
| 1360 | index = tonga_get_voltage_index(vddgfx_lookup_table, |
| 1361 | data->vddgfx_voltage_table.entries[count].value); |
| 1362 | table->BapmVddGfxVidLoSidd[count] = |
| 1363 | convert_to_vid(vddgfx_lookup_table->entries[index].us_cac_low); |
| 1364 | table->BapmVddGfxVidHiSidd[count] = |
| 1365 | convert_to_vid(vddgfx_lookup_table->entries[index].us_cac_mid); |
| 1366 | table->BapmVddGfxVidHiSidd2[count] = |
| 1367 | convert_to_vid(vddgfx_lookup_table->entries[index].us_cac_high); |
| 1368 | } |
| 1369 | } else { |
| 1370 | for (count = 0; count < vddcLevelCount; count++) { |
| 1371 | index = tonga_get_voltage_index(vddc_lookup_table, |
| 1372 | data->vddc_voltage_table.entries[count].value); |
| 1373 | table->BapmVddGfxVidLoSidd[count] = |
| 1374 | convert_to_vid(vddc_lookup_table->entries[index].us_cac_low); |
| 1375 | table->BapmVddGfxVidHiSidd[count] = |
| 1376 | convert_to_vid(vddc_lookup_table->entries[index].us_cac_mid); |
| 1377 | table->BapmVddGfxVidHiSidd2[count] = |
| 1378 | convert_to_vid(vddc_lookup_table->entries[index].us_cac_high); |
| 1379 | } |
| 1380 | } |
| 1381 | |
Edward O'Callaghan | 538f1ef | 2016-07-12 10:17:57 +1000 | [diff] [blame] | 1382 | return 0; |
yanyang1 | c82baa2 | 2015-08-18 15:28:32 +0800 | [diff] [blame] | 1383 | } |
| 1384 | |
| 1385 | |
| 1386 | /** |
| 1387 | * Preparation of voltage tables for SMC. |
| 1388 | * |
| 1389 | * @param hwmgr the address of the hardware manager |
| 1390 | * @param table the SMC DPM table structure to be populated |
| 1391 | * @return always 0 |
| 1392 | */ |
| 1393 | |
| 1394 | int tonga_populate_smc_voltage_tables(struct pp_hwmgr *hwmgr, |
| 1395 | SMU72_Discrete_DpmTable *table) |
| 1396 | { |
| 1397 | int result; |
| 1398 | |
| 1399 | result = tonga_populate_smc_vddc_table(hwmgr, table); |
| 1400 | PP_ASSERT_WITH_CODE(0 == result, |
| 1401 | "can not populate VDDC voltage table to SMC", return -1); |
| 1402 | |
| 1403 | result = tonga_populate_smc_vdd_ci_table(hwmgr, table); |
| 1404 | PP_ASSERT_WITH_CODE(0 == result, |
| 1405 | "can not populate VDDCI voltage table to SMC", return -1); |
| 1406 | |
| 1407 | result = tonga_populate_smc_vdd_gfx_table(hwmgr, table); |
| 1408 | PP_ASSERT_WITH_CODE(0 == result, |
| 1409 | "can not populate VDDGFX voltage table to SMC", return -1); |
| 1410 | |
| 1411 | result = tonga_populate_smc_mvdd_table(hwmgr, table); |
| 1412 | PP_ASSERT_WITH_CODE(0 == result, |
| 1413 | "can not populate MVDD voltage table to SMC", return -1); |
| 1414 | |
| 1415 | result = tonga_populate_cac_tables(hwmgr, table); |
| 1416 | PP_ASSERT_WITH_CODE(0 == result, |
| 1417 | "can not populate CAC voltage tables to SMC", return -1); |
| 1418 | |
| 1419 | return 0; |
| 1420 | } |
| 1421 | |
| 1422 | /** |
| 1423 | * Populates the SMC VRConfig field in DPM table. |
| 1424 | * |
| 1425 | * @param hwmgr the address of the hardware manager |
| 1426 | * @param table the SMC DPM table structure to be populated |
| 1427 | * @return always 0 |
| 1428 | */ |
| 1429 | static int tonga_populate_vr_config(struct pp_hwmgr *hwmgr, |
| 1430 | SMU72_Discrete_DpmTable *table) |
| 1431 | { |
| 1432 | tonga_hwmgr *data = (tonga_hwmgr *)(hwmgr->backend); |
| 1433 | uint16_t config; |
| 1434 | |
| 1435 | if (TONGA_VOLTAGE_CONTROL_BY_SVID2 == data->vdd_gfx_control) { |
| 1436 | /* Splitted mode */ |
| 1437 | config = VR_SVI2_PLANE_1; |
| 1438 | table->VRConfig |= (config<<VRCONF_VDDGFX_SHIFT); |
| 1439 | |
| 1440 | if (TONGA_VOLTAGE_CONTROL_BY_SVID2 == data->voltage_control) { |
| 1441 | config = VR_SVI2_PLANE_2; |
| 1442 | table->VRConfig |= config; |
| 1443 | } else { |
| 1444 | printk(KERN_ERR "[ powerplay ] VDDC and VDDGFX should be both on SVI2 control in splitted mode! \n"); |
| 1445 | } |
| 1446 | } else { |
| 1447 | /* Merged mode */ |
| 1448 | config = VR_MERGED_WITH_VDDC; |
| 1449 | table->VRConfig |= (config<<VRCONF_VDDGFX_SHIFT); |
| 1450 | |
| 1451 | /* Set Vddc Voltage Controller */ |
| 1452 | if (TONGA_VOLTAGE_CONTROL_BY_SVID2 == data->voltage_control) { |
| 1453 | config = VR_SVI2_PLANE_1; |
| 1454 | table->VRConfig |= config; |
| 1455 | } else { |
| 1456 | printk(KERN_ERR "[ powerplay ] VDDC should be on SVI2 control in merged mode! \n"); |
| 1457 | } |
| 1458 | } |
| 1459 | |
| 1460 | /* Set Vddci Voltage Controller */ |
| 1461 | if (TONGA_VOLTAGE_CONTROL_BY_SVID2 == data->vdd_ci_control) { |
| 1462 | config = VR_SVI2_PLANE_2; /* only in merged mode */ |
| 1463 | table->VRConfig |= (config<<VRCONF_VDDCI_SHIFT); |
| 1464 | } else if (TONGA_VOLTAGE_CONTROL_BY_GPIO == data->vdd_ci_control) { |
| 1465 | config = VR_SMIO_PATTERN_1; |
| 1466 | table->VRConfig |= (config<<VRCONF_VDDCI_SHIFT); |
| 1467 | } |
| 1468 | |
| 1469 | /* Set Mvdd Voltage Controller */ |
| 1470 | if (TONGA_VOLTAGE_CONTROL_BY_GPIO == data->mvdd_control) { |
| 1471 | config = VR_SMIO_PATTERN_2; |
| 1472 | table->VRConfig |= (config<<VRCONF_MVDD_SHIFT); |
| 1473 | } |
| 1474 | |
| 1475 | return 0; |
| 1476 | } |
| 1477 | |
| 1478 | static int tonga_get_dependecy_volt_by_clk(struct pp_hwmgr *hwmgr, |
| 1479 | phm_ppt_v1_clock_voltage_dependency_table *allowed_clock_voltage_table, |
| 1480 | uint32_t clock, SMU_VoltageLevel *voltage, uint32_t *mvdd) |
| 1481 | { |
| 1482 | uint32_t i = 0; |
| 1483 | tonga_hwmgr *data = (tonga_hwmgr *)(hwmgr->backend); |
| 1484 | struct phm_ppt_v1_information *pptable_info = (struct phm_ppt_v1_information *)(hwmgr->pptable); |
| 1485 | |
| 1486 | /* clock - voltage dependency table is empty table */ |
| 1487 | if (allowed_clock_voltage_table->count == 0) |
| 1488 | return -1; |
| 1489 | |
| 1490 | for (i = 0; i < allowed_clock_voltage_table->count; i++) { |
| 1491 | /* find first sclk bigger than request */ |
| 1492 | if (allowed_clock_voltage_table->entries[i].clk >= clock) { |
| 1493 | voltage->VddGfx = tonga_get_voltage_index(pptable_info->vddgfx_lookup_table, |
| 1494 | allowed_clock_voltage_table->entries[i].vddgfx); |
| 1495 | |
| 1496 | voltage->Vddc = tonga_get_voltage_index(pptable_info->vddc_lookup_table, |
| 1497 | allowed_clock_voltage_table->entries[i].vddc); |
| 1498 | |
| 1499 | if (allowed_clock_voltage_table->entries[i].vddci) { |
| 1500 | voltage->Vddci = tonga_get_voltage_id(&data->vddci_voltage_table, |
| 1501 | allowed_clock_voltage_table->entries[i].vddci); |
| 1502 | } else { |
| 1503 | voltage->Vddci = tonga_get_voltage_id(&data->vddci_voltage_table, |
| 1504 | allowed_clock_voltage_table->entries[i].vddc - data->vddc_vddci_delta); |
| 1505 | } |
| 1506 | |
| 1507 | if (allowed_clock_voltage_table->entries[i].mvdd) { |
| 1508 | *mvdd = (uint32_t) allowed_clock_voltage_table->entries[i].mvdd; |
| 1509 | } |
| 1510 | |
| 1511 | voltage->Phases = 1; |
| 1512 | return 0; |
| 1513 | } |
| 1514 | } |
| 1515 | |
| 1516 | /* sclk is bigger than max sclk in the dependence table */ |
| 1517 | voltage->VddGfx = tonga_get_voltage_index(pptable_info->vddgfx_lookup_table, |
| 1518 | allowed_clock_voltage_table->entries[i-1].vddgfx); |
| 1519 | voltage->Vddc = tonga_get_voltage_index(pptable_info->vddc_lookup_table, |
| 1520 | allowed_clock_voltage_table->entries[i-1].vddc); |
| 1521 | |
| 1522 | if (allowed_clock_voltage_table->entries[i-1].vddci) { |
| 1523 | voltage->Vddci = tonga_get_voltage_id(&data->vddci_voltage_table, |
| 1524 | allowed_clock_voltage_table->entries[i-1].vddci); |
| 1525 | } |
| 1526 | if (allowed_clock_voltage_table->entries[i-1].mvdd) { |
| 1527 | *mvdd = (uint32_t) allowed_clock_voltage_table->entries[i-1].mvdd; |
| 1528 | } |
| 1529 | |
| 1530 | return 0; |
| 1531 | } |
| 1532 | |
| 1533 | /** |
| 1534 | * Call SMC to reset S0/S1 to S1 and Reset SMIO to initial value |
| 1535 | * |
| 1536 | * @param hwmgr the address of the powerplay hardware manager. |
| 1537 | * @return always 0 |
| 1538 | */ |
| 1539 | int tonga_reset_to_default(struct pp_hwmgr *hwmgr) |
| 1540 | { |
| 1541 | return (smum_send_msg_to_smc(hwmgr->smumgr, PPSMC_MSG_ResetToDefaults) == 0) ? 0 : 1; |
| 1542 | } |
| 1543 | |
| 1544 | int tonga_populate_memory_timing_parameters( |
| 1545 | struct pp_hwmgr *hwmgr, |
| 1546 | uint32_t engine_clock, |
| 1547 | uint32_t memory_clock, |
| 1548 | struct SMU72_Discrete_MCArbDramTimingTableEntry *arb_regs |
| 1549 | ) |
| 1550 | { |
| 1551 | uint32_t dramTiming; |
| 1552 | uint32_t dramTiming2; |
| 1553 | uint32_t burstTime; |
| 1554 | int result; |
| 1555 | |
| 1556 | result = atomctrl_set_engine_dram_timings_rv770(hwmgr, |
| 1557 | engine_clock, memory_clock); |
| 1558 | |
| 1559 | PP_ASSERT_WITH_CODE(result == 0, |
| 1560 | "Error calling VBIOS to set DRAM_TIMING.", return result); |
| 1561 | |
| 1562 | dramTiming = cgs_read_register(hwmgr->device, mmMC_ARB_DRAM_TIMING); |
| 1563 | dramTiming2 = cgs_read_register(hwmgr->device, mmMC_ARB_DRAM_TIMING2); |
| 1564 | burstTime = PHM_READ_FIELD(hwmgr->device, MC_ARB_BURST_TIME, STATE0); |
| 1565 | |
| 1566 | arb_regs->McArbDramTiming = PP_HOST_TO_SMC_UL(dramTiming); |
| 1567 | arb_regs->McArbDramTiming2 = PP_HOST_TO_SMC_UL(dramTiming2); |
| 1568 | arb_regs->McArbBurstTime = (uint8_t)burstTime; |
| 1569 | |
| 1570 | return 0; |
| 1571 | } |
| 1572 | |
| 1573 | /** |
| 1574 | * Setup parameters for the MC ARB. |
| 1575 | * |
| 1576 | * @param hwmgr the address of the powerplay hardware manager. |
| 1577 | * @return always 0 |
| 1578 | * This function is to be called from the SetPowerState table. |
| 1579 | */ |
| 1580 | int tonga_program_memory_timing_parameters(struct pp_hwmgr *hwmgr) |
| 1581 | { |
| 1582 | tonga_hwmgr *data = (tonga_hwmgr *)(hwmgr->backend); |
| 1583 | int result = 0; |
| 1584 | SMU72_Discrete_MCArbDramTimingTable arb_regs; |
| 1585 | uint32_t i, j; |
| 1586 | |
| 1587 | memset(&arb_regs, 0x00, sizeof(SMU72_Discrete_MCArbDramTimingTable)); |
| 1588 | |
| 1589 | for (i = 0; i < data->dpm_table.sclk_table.count; i++) { |
| 1590 | for (j = 0; j < data->dpm_table.mclk_table.count; j++) { |
| 1591 | result = tonga_populate_memory_timing_parameters |
| 1592 | (hwmgr, data->dpm_table.sclk_table.dpm_levels[i].value, |
| 1593 | data->dpm_table.mclk_table.dpm_levels[j].value, |
| 1594 | &arb_regs.entries[i][j]); |
| 1595 | |
| 1596 | if (0 != result) { |
| 1597 | break; |
| 1598 | } |
| 1599 | } |
| 1600 | } |
| 1601 | |
| 1602 | if (0 == result) { |
| 1603 | result = tonga_copy_bytes_to_smc( |
| 1604 | hwmgr->smumgr, |
| 1605 | data->arb_table_start, |
| 1606 | (uint8_t *)&arb_regs, |
| 1607 | sizeof(SMU72_Discrete_MCArbDramTimingTable), |
| 1608 | data->sram_end |
| 1609 | ); |
| 1610 | } |
| 1611 | |
| 1612 | return result; |
| 1613 | } |
| 1614 | |
| 1615 | static int tonga_populate_smc_link_level(struct pp_hwmgr *hwmgr, SMU72_Discrete_DpmTable *table) |
| 1616 | { |
| 1617 | tonga_hwmgr *data = (tonga_hwmgr *)(hwmgr->backend); |
| 1618 | struct tonga_dpm_table *dpm_table = &data->dpm_table; |
| 1619 | uint32_t i; |
| 1620 | |
| 1621 | /* Index (dpm_table->pcie_speed_table.count) is reserved for PCIE boot level. */ |
| 1622 | for (i = 0; i <= dpm_table->pcie_speed_table.count; i++) { |
| 1623 | table->LinkLevel[i].PcieGenSpeed = |
| 1624 | (uint8_t)dpm_table->pcie_speed_table.dpm_levels[i].value; |
| 1625 | table->LinkLevel[i].PcieLaneCount = |
| 1626 | (uint8_t)encode_pcie_lane_width(dpm_table->pcie_speed_table.dpm_levels[i].param1); |
| 1627 | table->LinkLevel[i].EnabledForActivity = |
| 1628 | 1; |
| 1629 | table->LinkLevel[i].SPC = |
| 1630 | (uint8_t)(data->pcie_spc_cap & 0xff); |
| 1631 | table->LinkLevel[i].DownThreshold = |
| 1632 | PP_HOST_TO_SMC_UL(5); |
| 1633 | table->LinkLevel[i].UpThreshold = |
| 1634 | PP_HOST_TO_SMC_UL(30); |
| 1635 | } |
| 1636 | |
| 1637 | data->smc_state_table.LinkLevelCount = |
| 1638 | (uint8_t)dpm_table->pcie_speed_table.count; |
| 1639 | data->dpm_level_enable_mask.pcie_dpm_enable_mask = |
| 1640 | tonga_get_dpm_level_enable_mask_value(&dpm_table->pcie_speed_table); |
| 1641 | |
| 1642 | return 0; |
| 1643 | } |
| 1644 | |
Alex Deucher | 0104aa2 | 2015-11-13 10:46:30 -0500 | [diff] [blame] | 1645 | static int tonga_populate_smc_uvd_level(struct pp_hwmgr *hwmgr, |
| 1646 | SMU72_Discrete_DpmTable *table) |
| 1647 | { |
| 1648 | int result = 0; |
| 1649 | |
| 1650 | uint8_t count; |
| 1651 | pp_atomctrl_clock_dividers_vi dividers; |
| 1652 | tonga_hwmgr *data = (tonga_hwmgr *)(hwmgr->backend); |
| 1653 | struct phm_ppt_v1_information *pptable_info = (struct phm_ppt_v1_information *)(hwmgr->pptable); |
| 1654 | phm_ppt_v1_mm_clock_voltage_dependency_table *mm_table = pptable_info->mm_dep_table; |
| 1655 | |
| 1656 | table->UvdLevelCount = (uint8_t) (mm_table->count); |
| 1657 | table->UvdBootLevel = 0; |
| 1658 | |
| 1659 | for (count = 0; count < table->UvdLevelCount; count++) { |
| 1660 | table->UvdLevel[count].VclkFrequency = mm_table->entries[count].vclk; |
| 1661 | table->UvdLevel[count].DclkFrequency = mm_table->entries[count].dclk; |
| 1662 | table->UvdLevel[count].MinVoltage.Vddc = |
| 1663 | tonga_get_voltage_index(pptable_info->vddc_lookup_table, |
| 1664 | mm_table->entries[count].vddc); |
| 1665 | table->UvdLevel[count].MinVoltage.VddGfx = |
| 1666 | (data->vdd_gfx_control == TONGA_VOLTAGE_CONTROL_BY_SVID2) ? |
| 1667 | tonga_get_voltage_index(pptable_info->vddgfx_lookup_table, |
| 1668 | mm_table->entries[count].vddgfx) : 0; |
| 1669 | table->UvdLevel[count].MinVoltage.Vddci = |
| 1670 | tonga_get_voltage_id(&data->vddci_voltage_table, |
| 1671 | mm_table->entries[count].vddc - data->vddc_vddci_delta); |
| 1672 | table->UvdLevel[count].MinVoltage.Phases = 1; |
| 1673 | |
| 1674 | /* retrieve divider value for VBIOS */ |
| 1675 | result = atomctrl_get_dfs_pll_dividers_vi(hwmgr, |
| 1676 | table->UvdLevel[count].VclkFrequency, ÷rs); |
| 1677 | PP_ASSERT_WITH_CODE((0 == result), |
| 1678 | "can not find divide id for Vclk clock", return result); |
| 1679 | |
| 1680 | table->UvdLevel[count].VclkDivider = (uint8_t)dividers.pll_post_divider; |
| 1681 | |
| 1682 | result = atomctrl_get_dfs_pll_dividers_vi(hwmgr, |
| 1683 | table->UvdLevel[count].DclkFrequency, ÷rs); |
| 1684 | PP_ASSERT_WITH_CODE((0 == result), |
| 1685 | "can not find divide id for Dclk clock", return result); |
| 1686 | |
| 1687 | table->UvdLevel[count].DclkDivider = (uint8_t)dividers.pll_post_divider; |
| 1688 | |
| 1689 | CONVERT_FROM_HOST_TO_SMC_UL(table->UvdLevel[count].VclkFrequency); |
| 1690 | CONVERT_FROM_HOST_TO_SMC_UL(table->UvdLevel[count].DclkFrequency); |
| 1691 | //CONVERT_FROM_HOST_TO_SMC_UL((uint32_t)table->UvdLevel[count].MinVoltage); |
Rex Zhu | c15c8d7 | 2016-01-06 16:48:38 +0800 | [diff] [blame] | 1692 | } |
Alex Deucher | 0104aa2 | 2015-11-13 10:46:30 -0500 | [diff] [blame] | 1693 | |
Rex Zhu | c15c8d7 | 2016-01-06 16:48:38 +0800 | [diff] [blame] | 1694 | return result; |
Alex Deucher | 0104aa2 | 2015-11-13 10:46:30 -0500 | [diff] [blame] | 1695 | |
| 1696 | } |
yanyang1 | c82baa2 | 2015-08-18 15:28:32 +0800 | [diff] [blame] | 1697 | |
| 1698 | static int tonga_populate_smc_vce_level(struct pp_hwmgr *hwmgr, |
| 1699 | SMU72_Discrete_DpmTable *table) |
| 1700 | { |
| 1701 | int result = 0; |
| 1702 | |
| 1703 | uint8_t count; |
| 1704 | pp_atomctrl_clock_dividers_vi dividers; |
| 1705 | tonga_hwmgr *data = (tonga_hwmgr *)(hwmgr->backend); |
| 1706 | struct phm_ppt_v1_information *pptable_info = (struct phm_ppt_v1_information *)(hwmgr->pptable); |
| 1707 | phm_ppt_v1_mm_clock_voltage_dependency_table *mm_table = pptable_info->mm_dep_table; |
| 1708 | |
| 1709 | table->VceLevelCount = (uint8_t) (mm_table->count); |
| 1710 | table->VceBootLevel = 0; |
| 1711 | |
| 1712 | for (count = 0; count < table->VceLevelCount; count++) { |
| 1713 | table->VceLevel[count].Frequency = |
| 1714 | mm_table->entries[count].eclk; |
| 1715 | table->VceLevel[count].MinVoltage.Vddc = |
| 1716 | tonga_get_voltage_index(pptable_info->vddc_lookup_table, |
| 1717 | mm_table->entries[count].vddc); |
| 1718 | table->VceLevel[count].MinVoltage.VddGfx = |
| 1719 | (data->vdd_gfx_control == TONGA_VOLTAGE_CONTROL_BY_SVID2) ? |
| 1720 | tonga_get_voltage_index(pptable_info->vddgfx_lookup_table, |
| 1721 | mm_table->entries[count].vddgfx) : 0; |
| 1722 | table->VceLevel[count].MinVoltage.Vddci = |
| 1723 | tonga_get_voltage_id(&data->vddci_voltage_table, |
| 1724 | mm_table->entries[count].vddc - data->vddc_vddci_delta); |
| 1725 | table->VceLevel[count].MinVoltage.Phases = 1; |
| 1726 | |
| 1727 | /* retrieve divider value for VBIOS */ |
| 1728 | result = atomctrl_get_dfs_pll_dividers_vi(hwmgr, |
| 1729 | table->VceLevel[count].Frequency, ÷rs); |
| 1730 | PP_ASSERT_WITH_CODE((0 == result), |
| 1731 | "can not find divide id for VCE engine clock", return result); |
| 1732 | |
Rex Zhu | c15c8d7 | 2016-01-06 16:48:38 +0800 | [diff] [blame] | 1733 | table->VceLevel[count].Divider = (uint8_t)dividers.pll_post_divider; |
yanyang1 | c82baa2 | 2015-08-18 15:28:32 +0800 | [diff] [blame] | 1734 | |
| 1735 | CONVERT_FROM_HOST_TO_SMC_UL(table->VceLevel[count].Frequency); |
| 1736 | } |
| 1737 | |
| 1738 | return result; |
| 1739 | } |
| 1740 | |
| 1741 | static int tonga_populate_smc_acp_level(struct pp_hwmgr *hwmgr, |
| 1742 | SMU72_Discrete_DpmTable *table) |
| 1743 | { |
| 1744 | int result = 0; |
| 1745 | uint8_t count; |
| 1746 | pp_atomctrl_clock_dividers_vi dividers; |
| 1747 | tonga_hwmgr *data = (tonga_hwmgr *)(hwmgr->backend); |
| 1748 | struct phm_ppt_v1_information *pptable_info = (struct phm_ppt_v1_information *)(hwmgr->pptable); |
| 1749 | phm_ppt_v1_mm_clock_voltage_dependency_table *mm_table = pptable_info->mm_dep_table; |
| 1750 | |
| 1751 | table->AcpLevelCount = (uint8_t) (mm_table->count); |
| 1752 | table->AcpBootLevel = 0; |
| 1753 | |
| 1754 | for (count = 0; count < table->AcpLevelCount; count++) { |
| 1755 | table->AcpLevel[count].Frequency = |
| 1756 | pptable_info->mm_dep_table->entries[count].aclk; |
| 1757 | table->AcpLevel[count].MinVoltage.Vddc = |
| 1758 | tonga_get_voltage_index(pptable_info->vddc_lookup_table, |
| 1759 | mm_table->entries[count].vddc); |
| 1760 | table->AcpLevel[count].MinVoltage.VddGfx = |
| 1761 | (data->vdd_gfx_control == TONGA_VOLTAGE_CONTROL_BY_SVID2) ? |
| 1762 | tonga_get_voltage_index(pptable_info->vddgfx_lookup_table, |
| 1763 | mm_table->entries[count].vddgfx) : 0; |
| 1764 | table->AcpLevel[count].MinVoltage.Vddci = |
| 1765 | tonga_get_voltage_id(&data->vddci_voltage_table, |
| 1766 | mm_table->entries[count].vddc - data->vddc_vddci_delta); |
| 1767 | table->AcpLevel[count].MinVoltage.Phases = 1; |
| 1768 | |
| 1769 | /* retrieve divider value for VBIOS */ |
| 1770 | result = atomctrl_get_dfs_pll_dividers_vi(hwmgr, |
| 1771 | table->AcpLevel[count].Frequency, ÷rs); |
| 1772 | PP_ASSERT_WITH_CODE((0 == result), |
| 1773 | "can not find divide id for engine clock", return result); |
| 1774 | |
| 1775 | table->AcpLevel[count].Divider = (uint8_t)dividers.pll_post_divider; |
| 1776 | |
| 1777 | CONVERT_FROM_HOST_TO_SMC_UL(table->AcpLevel[count].Frequency); |
| 1778 | } |
| 1779 | |
| 1780 | return result; |
| 1781 | } |
| 1782 | |
| 1783 | static int tonga_populate_smc_samu_level(struct pp_hwmgr *hwmgr, |
| 1784 | SMU72_Discrete_DpmTable *table) |
| 1785 | { |
| 1786 | int result = 0; |
| 1787 | uint8_t count; |
| 1788 | pp_atomctrl_clock_dividers_vi dividers; |
| 1789 | tonga_hwmgr *data = (tonga_hwmgr *)(hwmgr->backend); |
| 1790 | struct phm_ppt_v1_information *pptable_info = (struct phm_ppt_v1_information *)(hwmgr->pptable); |
| 1791 | phm_ppt_v1_mm_clock_voltage_dependency_table *mm_table = pptable_info->mm_dep_table; |
| 1792 | |
| 1793 | table->SamuBootLevel = 0; |
| 1794 | table->SamuLevelCount = (uint8_t) (mm_table->count); |
| 1795 | |
| 1796 | for (count = 0; count < table->SamuLevelCount; count++) { |
| 1797 | /* not sure whether we need evclk or not */ |
| 1798 | table->SamuLevel[count].Frequency = |
| 1799 | pptable_info->mm_dep_table->entries[count].samclock; |
| 1800 | table->SamuLevel[count].MinVoltage.Vddc = |
| 1801 | tonga_get_voltage_index(pptable_info->vddc_lookup_table, |
| 1802 | mm_table->entries[count].vddc); |
| 1803 | table->SamuLevel[count].MinVoltage.VddGfx = |
| 1804 | (data->vdd_gfx_control == TONGA_VOLTAGE_CONTROL_BY_SVID2) ? |
| 1805 | tonga_get_voltage_index(pptable_info->vddgfx_lookup_table, |
| 1806 | mm_table->entries[count].vddgfx) : 0; |
| 1807 | table->SamuLevel[count].MinVoltage.Vddci = |
| 1808 | tonga_get_voltage_id(&data->vddci_voltage_table, |
| 1809 | mm_table->entries[count].vddc - data->vddc_vddci_delta); |
| 1810 | table->SamuLevel[count].MinVoltage.Phases = 1; |
| 1811 | |
| 1812 | /* retrieve divider value for VBIOS */ |
| 1813 | result = atomctrl_get_dfs_pll_dividers_vi(hwmgr, |
| 1814 | table->SamuLevel[count].Frequency, ÷rs); |
| 1815 | PP_ASSERT_WITH_CODE((0 == result), |
| 1816 | "can not find divide id for samu clock", return result); |
| 1817 | |
Rex Zhu | c15c8d7 | 2016-01-06 16:48:38 +0800 | [diff] [blame] | 1818 | table->SamuLevel[count].Divider = (uint8_t)dividers.pll_post_divider; |
yanyang1 | c82baa2 | 2015-08-18 15:28:32 +0800 | [diff] [blame] | 1819 | |
| 1820 | CONVERT_FROM_HOST_TO_SMC_UL(table->SamuLevel[count].Frequency); |
| 1821 | } |
| 1822 | |
| 1823 | return result; |
| 1824 | } |
| 1825 | |
| 1826 | /** |
| 1827 | * Populates the SMC MCLK structure using the provided memory clock |
| 1828 | * |
| 1829 | * @param hwmgr the address of the hardware manager |
| 1830 | * @param memory_clock the memory clock to use to populate the structure |
| 1831 | * @param sclk the SMC SCLK structure to be populated |
| 1832 | */ |
| 1833 | static int tonga_calculate_mclk_params( |
| 1834 | struct pp_hwmgr *hwmgr, |
| 1835 | uint32_t memory_clock, |
| 1836 | SMU72_Discrete_MemoryLevel *mclk, |
| 1837 | bool strobe_mode, |
| 1838 | bool dllStateOn |
| 1839 | ) |
| 1840 | { |
| 1841 | const tonga_hwmgr *data = (tonga_hwmgr *)(hwmgr->backend); |
| 1842 | uint32_t dll_cntl = data->clock_registers.vDLL_CNTL; |
| 1843 | uint32_t mclk_pwrmgt_cntl = data->clock_registers.vMCLK_PWRMGT_CNTL; |
| 1844 | uint32_t mpll_ad_func_cntl = data->clock_registers.vMPLL_AD_FUNC_CNTL; |
| 1845 | uint32_t mpll_dq_func_cntl = data->clock_registers.vMPLL_DQ_FUNC_CNTL; |
| 1846 | uint32_t mpll_func_cntl = data->clock_registers.vMPLL_FUNC_CNTL; |
| 1847 | uint32_t mpll_func_cntl_1 = data->clock_registers.vMPLL_FUNC_CNTL_1; |
| 1848 | uint32_t mpll_func_cntl_2 = data->clock_registers.vMPLL_FUNC_CNTL_2; |
| 1849 | uint32_t mpll_ss1 = data->clock_registers.vMPLL_SS1; |
| 1850 | uint32_t mpll_ss2 = data->clock_registers.vMPLL_SS2; |
| 1851 | |
| 1852 | pp_atomctrl_memory_clock_param mpll_param; |
| 1853 | int result; |
| 1854 | |
| 1855 | result = atomctrl_get_memory_pll_dividers_si(hwmgr, |
| 1856 | memory_clock, &mpll_param, strobe_mode); |
| 1857 | PP_ASSERT_WITH_CODE(0 == result, |
| 1858 | "Error retrieving Memory Clock Parameters from VBIOS.", return result); |
| 1859 | |
| 1860 | /* MPLL_FUNC_CNTL setup*/ |
Rex Zhu | c15c8d7 | 2016-01-06 16:48:38 +0800 | [diff] [blame] | 1861 | mpll_func_cntl = PHM_SET_FIELD(mpll_func_cntl, MPLL_FUNC_CNTL, BWCTRL, mpll_param.bw_ctrl); |
yanyang1 | c82baa2 | 2015-08-18 15:28:32 +0800 | [diff] [blame] | 1862 | |
| 1863 | /* MPLL_FUNC_CNTL_1 setup*/ |
| 1864 | mpll_func_cntl_1 = PHM_SET_FIELD(mpll_func_cntl_1, |
| 1865 | MPLL_FUNC_CNTL_1, CLKF, mpll_param.mpll_fb_divider.cl_kf); |
| 1866 | mpll_func_cntl_1 = PHM_SET_FIELD(mpll_func_cntl_1, |
| 1867 | MPLL_FUNC_CNTL_1, CLKFRAC, mpll_param.mpll_fb_divider.clk_frac); |
| 1868 | mpll_func_cntl_1 = PHM_SET_FIELD(mpll_func_cntl_1, |
| 1869 | MPLL_FUNC_CNTL_1, VCO_MODE, mpll_param.vco_mode); |
| 1870 | |
| 1871 | /* MPLL_AD_FUNC_CNTL setup*/ |
| 1872 | mpll_ad_func_cntl = PHM_SET_FIELD(mpll_ad_func_cntl, |
| 1873 | MPLL_AD_FUNC_CNTL, YCLK_POST_DIV, mpll_param.mpll_post_divider); |
| 1874 | |
| 1875 | if (data->is_memory_GDDR5) { |
| 1876 | /* MPLL_DQ_FUNC_CNTL setup*/ |
| 1877 | mpll_dq_func_cntl = PHM_SET_FIELD(mpll_dq_func_cntl, |
| 1878 | MPLL_DQ_FUNC_CNTL, YCLK_SEL, mpll_param.yclk_sel); |
| 1879 | mpll_dq_func_cntl = PHM_SET_FIELD(mpll_dq_func_cntl, |
| 1880 | MPLL_DQ_FUNC_CNTL, YCLK_POST_DIV, mpll_param.mpll_post_divider); |
| 1881 | } |
| 1882 | |
| 1883 | if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, |
| 1884 | PHM_PlatformCaps_MemorySpreadSpectrumSupport)) { |
| 1885 | /* |
| 1886 | ************************************ |
| 1887 | Fref = Reference Frequency |
| 1888 | NF = Feedback divider ratio |
| 1889 | NR = Reference divider ratio |
| 1890 | Fnom = Nominal VCO output frequency = Fref * NF / NR |
| 1891 | Fs = Spreading Rate |
| 1892 | D = Percentage down-spread / 2 |
| 1893 | Fint = Reference input frequency to PFD = Fref / NR |
| 1894 | NS = Spreading rate divider ratio = int(Fint / (2 * Fs)) |
| 1895 | CLKS = NS - 1 = ISS_STEP_NUM[11:0] |
| 1896 | NV = D * Fs / Fnom * 4 * ((Fnom/Fref * NR) ^ 2) |
| 1897 | CLKV = 65536 * NV = ISS_STEP_SIZE[25:0] |
| 1898 | ************************************* |
| 1899 | */ |
| 1900 | pp_atomctrl_internal_ss_info ss_info; |
| 1901 | uint32_t freq_nom; |
| 1902 | uint32_t tmp; |
| 1903 | uint32_t reference_clock = atomctrl_get_mpll_reference_clock(hwmgr); |
| 1904 | |
| 1905 | /* for GDDR5 for all modes and DDR3 */ |
| 1906 | if (1 == mpll_param.qdr) |
| 1907 | freq_nom = memory_clock * 4 * (1 << mpll_param.mpll_post_divider); |
| 1908 | else |
| 1909 | freq_nom = memory_clock * 2 * (1 << mpll_param.mpll_post_divider); |
| 1910 | |
| 1911 | /* tmp = (freq_nom / reference_clock * reference_divider) ^ 2 Note: S.I. reference_divider = 1*/ |
| 1912 | tmp = (freq_nom / reference_clock); |
| 1913 | tmp = tmp * tmp; |
| 1914 | |
| 1915 | if (0 == atomctrl_get_memory_clock_spread_spectrum(hwmgr, freq_nom, &ss_info)) { |
| 1916 | /* ss_info.speed_spectrum_percentage -- in unit of 0.01% */ |
| 1917 | /* ss.Info.speed_spectrum_rate -- in unit of khz */ |
| 1918 | /* CLKS = reference_clock / (2 * speed_spectrum_rate * reference_divider) * 10 */ |
| 1919 | /* = reference_clock * 5 / speed_spectrum_rate */ |
| 1920 | uint32_t clks = reference_clock * 5 / ss_info.speed_spectrum_rate; |
| 1921 | |
| 1922 | /* CLKV = 65536 * speed_spectrum_percentage / 2 * spreadSpecrumRate / freq_nom * 4 / 100000 * ((freq_nom / reference_clock) ^ 2) */ |
| 1923 | /* = 131 * speed_spectrum_percentage * speed_spectrum_rate / 100 * ((freq_nom / reference_clock) ^ 2) / freq_nom */ |
| 1924 | uint32_t clkv = |
| 1925 | (uint32_t)((((131 * ss_info.speed_spectrum_percentage * |
| 1926 | ss_info.speed_spectrum_rate) / 100) * tmp) / freq_nom); |
| 1927 | |
| 1928 | mpll_ss1 = PHM_SET_FIELD(mpll_ss1, MPLL_SS1, CLKV, clkv); |
| 1929 | mpll_ss2 = PHM_SET_FIELD(mpll_ss2, MPLL_SS2, CLKS, clks); |
| 1930 | } |
| 1931 | } |
| 1932 | |
| 1933 | /* MCLK_PWRMGT_CNTL setup */ |
| 1934 | mclk_pwrmgt_cntl = PHM_SET_FIELD(mclk_pwrmgt_cntl, |
| 1935 | MCLK_PWRMGT_CNTL, DLL_SPEED, mpll_param.dll_speed); |
| 1936 | mclk_pwrmgt_cntl = PHM_SET_FIELD(mclk_pwrmgt_cntl, |
| 1937 | MCLK_PWRMGT_CNTL, MRDCK0_PDNB, dllStateOn); |
| 1938 | mclk_pwrmgt_cntl = PHM_SET_FIELD(mclk_pwrmgt_cntl, |
| 1939 | MCLK_PWRMGT_CNTL, MRDCK1_PDNB, dllStateOn); |
| 1940 | |
| 1941 | |
| 1942 | /* Save the result data to outpupt memory level structure */ |
| 1943 | mclk->MclkFrequency = memory_clock; |
| 1944 | mclk->MpllFuncCntl = mpll_func_cntl; |
| 1945 | mclk->MpllFuncCntl_1 = mpll_func_cntl_1; |
| 1946 | mclk->MpllFuncCntl_2 = mpll_func_cntl_2; |
| 1947 | mclk->MpllAdFuncCntl = mpll_ad_func_cntl; |
| 1948 | mclk->MpllDqFuncCntl = mpll_dq_func_cntl; |
| 1949 | mclk->MclkPwrmgtCntl = mclk_pwrmgt_cntl; |
| 1950 | mclk->DllCntl = dll_cntl; |
| 1951 | mclk->MpllSs1 = mpll_ss1; |
| 1952 | mclk->MpllSs2 = mpll_ss2; |
| 1953 | |
| 1954 | return 0; |
| 1955 | } |
| 1956 | |
| 1957 | static uint8_t tonga_get_mclk_frequency_ratio(uint32_t memory_clock, |
| 1958 | bool strobe_mode) |
| 1959 | { |
| 1960 | uint8_t mc_para_index; |
| 1961 | |
| 1962 | if (strobe_mode) { |
| 1963 | if (memory_clock < 12500) { |
| 1964 | mc_para_index = 0x00; |
| 1965 | } else if (memory_clock > 47500) { |
| 1966 | mc_para_index = 0x0f; |
| 1967 | } else { |
| 1968 | mc_para_index = (uint8_t)((memory_clock - 10000) / 2500); |
| 1969 | } |
| 1970 | } else { |
| 1971 | if (memory_clock < 65000) { |
| 1972 | mc_para_index = 0x00; |
| 1973 | } else if (memory_clock > 135000) { |
| 1974 | mc_para_index = 0x0f; |
| 1975 | } else { |
| 1976 | mc_para_index = (uint8_t)((memory_clock - 60000) / 5000); |
| 1977 | } |
| 1978 | } |
| 1979 | |
| 1980 | return mc_para_index; |
| 1981 | } |
| 1982 | |
| 1983 | static uint8_t tonga_get_ddr3_mclk_frequency_ratio(uint32_t memory_clock) |
| 1984 | { |
| 1985 | uint8_t mc_para_index; |
| 1986 | |
| 1987 | if (memory_clock < 10000) { |
| 1988 | mc_para_index = 0; |
| 1989 | } else if (memory_clock >= 80000) { |
| 1990 | mc_para_index = 0x0f; |
| 1991 | } else { |
| 1992 | mc_para_index = (uint8_t)((memory_clock - 10000) / 5000 + 1); |
| 1993 | } |
| 1994 | |
| 1995 | return mc_para_index; |
| 1996 | } |
| 1997 | |
| 1998 | static int tonga_populate_single_memory_level( |
| 1999 | struct pp_hwmgr *hwmgr, |
| 2000 | uint32_t memory_clock, |
| 2001 | SMU72_Discrete_MemoryLevel *memory_level |
| 2002 | ) |
| 2003 | { |
| 2004 | uint32_t minMvdd = 0; |
| 2005 | tonga_hwmgr *data = (tonga_hwmgr *)(hwmgr->backend); |
| 2006 | struct phm_ppt_v1_information *pptable_info = (struct phm_ppt_v1_information *)(hwmgr->pptable); |
| 2007 | int result = 0; |
| 2008 | bool dllStateOn; |
| 2009 | struct cgs_display_info info = {0}; |
| 2010 | |
| 2011 | |
| 2012 | if (NULL != pptable_info->vdd_dep_on_mclk) { |
| 2013 | result = tonga_get_dependecy_volt_by_clk(hwmgr, |
| 2014 | pptable_info->vdd_dep_on_mclk, memory_clock, &memory_level->MinVoltage, &minMvdd); |
| 2015 | PP_ASSERT_WITH_CODE((0 == result), |
| 2016 | "can not find MinVddc voltage value from memory VDDC voltage dependency table", return result); |
| 2017 | } |
| 2018 | |
| 2019 | if (data->mvdd_control == TONGA_VOLTAGE_CONTROL_NONE) { |
| 2020 | memory_level->MinMvdd = data->vbios_boot_state.mvdd_bootup_value; |
| 2021 | } else { |
| 2022 | memory_level->MinMvdd = minMvdd; |
| 2023 | } |
| 2024 | memory_level->EnabledForThrottle = 1; |
| 2025 | memory_level->EnabledForActivity = 0; |
| 2026 | memory_level->UpHyst = 0; |
| 2027 | memory_level->DownHyst = 100; |
| 2028 | memory_level->VoltageDownHyst = 0; |
| 2029 | |
| 2030 | /* Indicates maximum activity level for this performance level.*/ |
| 2031 | memory_level->ActivityLevel = (uint16_t)data->mclk_activity_target; |
| 2032 | memory_level->StutterEnable = 0; |
| 2033 | memory_level->StrobeEnable = 0; |
| 2034 | memory_level->EdcReadEnable = 0; |
| 2035 | memory_level->EdcWriteEnable = 0; |
| 2036 | memory_level->RttEnable = 0; |
| 2037 | |
| 2038 | /* default set to low watermark. Highest level will be set to high later.*/ |
| 2039 | memory_level->DisplayWatermark = PPSMC_DISPLAY_WATERMARK_LOW; |
| 2040 | |
| 2041 | cgs_get_active_displays_info(hwmgr->device, &info); |
| 2042 | data->display_timing.num_existing_displays = info.display_count; |
| 2043 | |
| 2044 | if ((data->mclk_stutter_mode_threshold != 0) && |
Alex Deucher | 7e8d1fb | 2016-04-08 16:42:38 -0400 | [diff] [blame] | 2045 | (memory_clock <= data->mclk_stutter_mode_threshold) && |
Edward O'Callaghan | 4ba27f9 | 2016-07-12 10:17:56 +1000 | [diff] [blame] | 2046 | (!data->is_uvd_enabled) |
Alex Deucher | 7e8d1fb | 2016-04-08 16:42:38 -0400 | [diff] [blame] | 2047 | && (PHM_READ_FIELD(hwmgr->device, DPG_PIPE_STUTTER_CONTROL, STUTTER_ENABLE) & 0x1) |
| 2048 | && (data->display_timing.num_existing_displays <= 2) |
| 2049 | && (data->display_timing.num_existing_displays != 0)) |
yanyang1 | c82baa2 | 2015-08-18 15:28:32 +0800 | [diff] [blame] | 2050 | memory_level->StutterEnable = 1; |
| 2051 | |
| 2052 | /* decide strobe mode*/ |
| 2053 | memory_level->StrobeEnable = (data->mclk_strobe_mode_threshold != 0) && |
| 2054 | (memory_clock <= data->mclk_strobe_mode_threshold); |
| 2055 | |
| 2056 | /* decide EDC mode and memory clock ratio*/ |
| 2057 | if (data->is_memory_GDDR5) { |
| 2058 | memory_level->StrobeRatio = tonga_get_mclk_frequency_ratio(memory_clock, |
| 2059 | memory_level->StrobeEnable); |
| 2060 | |
| 2061 | if ((data->mclk_edc_enable_threshold != 0) && |
| 2062 | (memory_clock > data->mclk_edc_enable_threshold)) { |
| 2063 | memory_level->EdcReadEnable = 1; |
| 2064 | } |
| 2065 | |
| 2066 | if ((data->mclk_edc_wr_enable_threshold != 0) && |
| 2067 | (memory_clock > data->mclk_edc_wr_enable_threshold)) { |
| 2068 | memory_level->EdcWriteEnable = 1; |
| 2069 | } |
| 2070 | |
| 2071 | if (memory_level->StrobeEnable) { |
| 2072 | if (tonga_get_mclk_frequency_ratio(memory_clock, 1) >= |
| 2073 | ((cgs_read_register(hwmgr->device, mmMC_SEQ_MISC7) >> 16) & 0xf)) { |
| 2074 | dllStateOn = ((cgs_read_register(hwmgr->device, mmMC_SEQ_MISC5) >> 1) & 0x1) ? 1 : 0; |
| 2075 | } else { |
| 2076 | dllStateOn = ((cgs_read_register(hwmgr->device, mmMC_SEQ_MISC6) >> 1) & 0x1) ? 1 : 0; |
| 2077 | } |
| 2078 | |
| 2079 | } else { |
| 2080 | dllStateOn = data->dll_defaule_on; |
| 2081 | } |
| 2082 | } else { |
| 2083 | memory_level->StrobeRatio = |
| 2084 | tonga_get_ddr3_mclk_frequency_ratio(memory_clock); |
| 2085 | dllStateOn = ((cgs_read_register(hwmgr->device, mmMC_SEQ_MISC5) >> 1) & 0x1) ? 1 : 0; |
| 2086 | } |
| 2087 | |
| 2088 | result = tonga_calculate_mclk_params(hwmgr, |
| 2089 | memory_clock, memory_level, memory_level->StrobeEnable, dllStateOn); |
| 2090 | |
| 2091 | if (0 == result) { |
| 2092 | CONVERT_FROM_HOST_TO_SMC_UL(memory_level->MinMvdd); |
| 2093 | /* MCLK frequency in units of 10KHz*/ |
| 2094 | CONVERT_FROM_HOST_TO_SMC_UL(memory_level->MclkFrequency); |
| 2095 | /* Indicates maximum activity level for this performance level.*/ |
| 2096 | CONVERT_FROM_HOST_TO_SMC_US(memory_level->ActivityLevel); |
| 2097 | CONVERT_FROM_HOST_TO_SMC_UL(memory_level->MpllFuncCntl); |
| 2098 | CONVERT_FROM_HOST_TO_SMC_UL(memory_level->MpllFuncCntl_1); |
| 2099 | CONVERT_FROM_HOST_TO_SMC_UL(memory_level->MpllFuncCntl_2); |
| 2100 | CONVERT_FROM_HOST_TO_SMC_UL(memory_level->MpllAdFuncCntl); |
| 2101 | CONVERT_FROM_HOST_TO_SMC_UL(memory_level->MpllDqFuncCntl); |
| 2102 | CONVERT_FROM_HOST_TO_SMC_UL(memory_level->MclkPwrmgtCntl); |
| 2103 | CONVERT_FROM_HOST_TO_SMC_UL(memory_level->DllCntl); |
| 2104 | CONVERT_FROM_HOST_TO_SMC_UL(memory_level->MpllSs1); |
| 2105 | CONVERT_FROM_HOST_TO_SMC_UL(memory_level->MpllSs2); |
| 2106 | } |
| 2107 | |
| 2108 | return result; |
| 2109 | } |
| 2110 | |
| 2111 | /** |
| 2112 | * Populates the SMC MVDD structure using the provided memory clock. |
| 2113 | * |
| 2114 | * @param hwmgr the address of the hardware manager |
| 2115 | * @param mclk the MCLK value to be used in the decision if MVDD should be high or low. |
| 2116 | * @param voltage the SMC VOLTAGE structure to be populated |
| 2117 | */ |
| 2118 | int tonga_populate_mvdd_value(struct pp_hwmgr *hwmgr, uint32_t mclk, SMIO_Pattern *smio_pattern) |
| 2119 | { |
| 2120 | const tonga_hwmgr *data = (tonga_hwmgr *)(hwmgr->backend); |
| 2121 | struct phm_ppt_v1_information *pptable_info = (struct phm_ppt_v1_information *)(hwmgr->pptable); |
| 2122 | uint32_t i = 0; |
| 2123 | |
| 2124 | if (TONGA_VOLTAGE_CONTROL_NONE != data->mvdd_control) { |
| 2125 | /* find mvdd value which clock is more than request */ |
| 2126 | for (i = 0; i < pptable_info->vdd_dep_on_mclk->count; i++) { |
| 2127 | if (mclk <= pptable_info->vdd_dep_on_mclk->entries[i].clk) { |
| 2128 | /* Always round to higher voltage. */ |
| 2129 | smio_pattern->Voltage = data->mvdd_voltage_table.entries[i].value; |
| 2130 | break; |
| 2131 | } |
| 2132 | } |
| 2133 | |
| 2134 | PP_ASSERT_WITH_CODE(i < pptable_info->vdd_dep_on_mclk->count, |
| 2135 | "MVDD Voltage is outside the supported range.", return -1); |
| 2136 | |
| 2137 | } else { |
| 2138 | return -1; |
| 2139 | } |
| 2140 | |
| 2141 | return 0; |
| 2142 | } |
| 2143 | |
| 2144 | |
| 2145 | static int tonga_populate_smv_acpi_level(struct pp_hwmgr *hwmgr, |
| 2146 | SMU72_Discrete_DpmTable *table) |
| 2147 | { |
| 2148 | int result = 0; |
| 2149 | const tonga_hwmgr *data = (tonga_hwmgr *)(hwmgr->backend); |
| 2150 | pp_atomctrl_clock_dividers_vi dividers; |
| 2151 | SMIO_Pattern voltage_level; |
| 2152 | uint32_t spll_func_cntl = data->clock_registers.vCG_SPLL_FUNC_CNTL; |
| 2153 | uint32_t spll_func_cntl_2 = data->clock_registers.vCG_SPLL_FUNC_CNTL_2; |
| 2154 | uint32_t dll_cntl = data->clock_registers.vDLL_CNTL; |
| 2155 | uint32_t mclk_pwrmgt_cntl = data->clock_registers.vMCLK_PWRMGT_CNTL; |
| 2156 | |
| 2157 | /* The ACPI state should not do DPM on DC (or ever).*/ |
| 2158 | table->ACPILevel.Flags &= ~PPSMC_SWSTATE_FLAG_DC; |
| 2159 | |
| 2160 | table->ACPILevel.MinVoltage = data->smc_state_table.GraphicsLevel[0].MinVoltage; |
| 2161 | |
| 2162 | /* assign zero for now*/ |
| 2163 | table->ACPILevel.SclkFrequency = atomctrl_get_reference_clock(hwmgr); |
| 2164 | |
| 2165 | /* get the engine clock dividers for this clock value*/ |
| 2166 | result = atomctrl_get_engine_pll_dividers_vi(hwmgr, |
| 2167 | table->ACPILevel.SclkFrequency, ÷rs); |
| 2168 | |
| 2169 | PP_ASSERT_WITH_CODE(result == 0, |
| 2170 | "Error retrieving Engine Clock dividers from VBIOS.", return result); |
| 2171 | |
| 2172 | /* divider ID for required SCLK*/ |
| 2173 | table->ACPILevel.SclkDid = (uint8_t)dividers.pll_post_divider; |
| 2174 | table->ACPILevel.DisplayWatermark = PPSMC_DISPLAY_WATERMARK_LOW; |
| 2175 | table->ACPILevel.DeepSleepDivId = 0; |
| 2176 | |
| 2177 | spll_func_cntl = PHM_SET_FIELD(spll_func_cntl, |
| 2178 | CG_SPLL_FUNC_CNTL, SPLL_PWRON, 0); |
| 2179 | spll_func_cntl = PHM_SET_FIELD(spll_func_cntl, |
| 2180 | CG_SPLL_FUNC_CNTL, SPLL_RESET, 1); |
| 2181 | spll_func_cntl_2 = PHM_SET_FIELD(spll_func_cntl_2, |
| 2182 | CG_SPLL_FUNC_CNTL_2, SCLK_MUX_SEL, 4); |
| 2183 | |
| 2184 | table->ACPILevel.CgSpllFuncCntl = spll_func_cntl; |
| 2185 | table->ACPILevel.CgSpllFuncCntl2 = spll_func_cntl_2; |
| 2186 | table->ACPILevel.CgSpllFuncCntl3 = data->clock_registers.vCG_SPLL_FUNC_CNTL_3; |
| 2187 | table->ACPILevel.CgSpllFuncCntl4 = data->clock_registers.vCG_SPLL_FUNC_CNTL_4; |
| 2188 | table->ACPILevel.SpllSpreadSpectrum = data->clock_registers.vCG_SPLL_SPREAD_SPECTRUM; |
| 2189 | table->ACPILevel.SpllSpreadSpectrum2 = data->clock_registers.vCG_SPLL_SPREAD_SPECTRUM_2; |
| 2190 | table->ACPILevel.CcPwrDynRm = 0; |
| 2191 | table->ACPILevel.CcPwrDynRm1 = 0; |
| 2192 | |
| 2193 | |
| 2194 | /* For various features to be enabled/disabled while this level is active.*/ |
| 2195 | CONVERT_FROM_HOST_TO_SMC_UL(table->ACPILevel.Flags); |
| 2196 | /* SCLK frequency in units of 10KHz*/ |
| 2197 | CONVERT_FROM_HOST_TO_SMC_UL(table->ACPILevel.SclkFrequency); |
| 2198 | CONVERT_FROM_HOST_TO_SMC_UL(table->ACPILevel.CgSpllFuncCntl); |
| 2199 | CONVERT_FROM_HOST_TO_SMC_UL(table->ACPILevel.CgSpllFuncCntl2); |
| 2200 | CONVERT_FROM_HOST_TO_SMC_UL(table->ACPILevel.CgSpllFuncCntl3); |
| 2201 | CONVERT_FROM_HOST_TO_SMC_UL(table->ACPILevel.CgSpllFuncCntl4); |
| 2202 | CONVERT_FROM_HOST_TO_SMC_UL(table->ACPILevel.SpllSpreadSpectrum); |
| 2203 | CONVERT_FROM_HOST_TO_SMC_UL(table->ACPILevel.SpllSpreadSpectrum2); |
| 2204 | CONVERT_FROM_HOST_TO_SMC_UL(table->ACPILevel.CcPwrDynRm); |
| 2205 | CONVERT_FROM_HOST_TO_SMC_UL(table->ACPILevel.CcPwrDynRm1); |
| 2206 | |
| 2207 | /* table->MemoryACPILevel.MinVddcPhases = table->ACPILevel.MinVddcPhases;*/ |
| 2208 | table->MemoryACPILevel.MinVoltage = data->smc_state_table.MemoryLevel[0].MinVoltage; |
| 2209 | |
| 2210 | /* CONVERT_FROM_HOST_TO_SMC_UL(table->MemoryACPILevel.MinVoltage);*/ |
| 2211 | |
| 2212 | if (0 == tonga_populate_mvdd_value(hwmgr, 0, &voltage_level)) |
| 2213 | table->MemoryACPILevel.MinMvdd = |
| 2214 | PP_HOST_TO_SMC_UL(voltage_level.Voltage * VOLTAGE_SCALE); |
| 2215 | else |
| 2216 | table->MemoryACPILevel.MinMvdd = 0; |
| 2217 | |
| 2218 | /* Force reset on DLL*/ |
| 2219 | mclk_pwrmgt_cntl = PHM_SET_FIELD(mclk_pwrmgt_cntl, |
| 2220 | MCLK_PWRMGT_CNTL, MRDCK0_RESET, 0x1); |
| 2221 | mclk_pwrmgt_cntl = PHM_SET_FIELD(mclk_pwrmgt_cntl, |
| 2222 | MCLK_PWRMGT_CNTL, MRDCK1_RESET, 0x1); |
| 2223 | |
| 2224 | /* Disable DLL in ACPIState*/ |
| 2225 | mclk_pwrmgt_cntl = PHM_SET_FIELD(mclk_pwrmgt_cntl, |
| 2226 | MCLK_PWRMGT_CNTL, MRDCK0_PDNB, 0); |
| 2227 | mclk_pwrmgt_cntl = PHM_SET_FIELD(mclk_pwrmgt_cntl, |
| 2228 | MCLK_PWRMGT_CNTL, MRDCK1_PDNB, 0); |
| 2229 | |
| 2230 | /* Enable DLL bypass signal*/ |
| 2231 | dll_cntl = PHM_SET_FIELD(dll_cntl, |
| 2232 | DLL_CNTL, MRDCK0_BYPASS, 0); |
| 2233 | dll_cntl = PHM_SET_FIELD(dll_cntl, |
| 2234 | DLL_CNTL, MRDCK1_BYPASS, 0); |
| 2235 | |
| 2236 | table->MemoryACPILevel.DllCntl = |
| 2237 | PP_HOST_TO_SMC_UL(dll_cntl); |
| 2238 | table->MemoryACPILevel.MclkPwrmgtCntl = |
| 2239 | PP_HOST_TO_SMC_UL(mclk_pwrmgt_cntl); |
| 2240 | table->MemoryACPILevel.MpllAdFuncCntl = |
| 2241 | PP_HOST_TO_SMC_UL(data->clock_registers.vMPLL_AD_FUNC_CNTL); |
| 2242 | table->MemoryACPILevel.MpllDqFuncCntl = |
| 2243 | PP_HOST_TO_SMC_UL(data->clock_registers.vMPLL_DQ_FUNC_CNTL); |
| 2244 | table->MemoryACPILevel.MpllFuncCntl = |
| 2245 | PP_HOST_TO_SMC_UL(data->clock_registers.vMPLL_FUNC_CNTL); |
| 2246 | table->MemoryACPILevel.MpllFuncCntl_1 = |
| 2247 | PP_HOST_TO_SMC_UL(data->clock_registers.vMPLL_FUNC_CNTL_1); |
| 2248 | table->MemoryACPILevel.MpllFuncCntl_2 = |
| 2249 | PP_HOST_TO_SMC_UL(data->clock_registers.vMPLL_FUNC_CNTL_2); |
| 2250 | table->MemoryACPILevel.MpllSs1 = |
| 2251 | PP_HOST_TO_SMC_UL(data->clock_registers.vMPLL_SS1); |
| 2252 | table->MemoryACPILevel.MpllSs2 = |
| 2253 | PP_HOST_TO_SMC_UL(data->clock_registers.vMPLL_SS2); |
| 2254 | |
| 2255 | table->MemoryACPILevel.EnabledForThrottle = 0; |
| 2256 | table->MemoryACPILevel.EnabledForActivity = 0; |
| 2257 | table->MemoryACPILevel.UpHyst = 0; |
| 2258 | table->MemoryACPILevel.DownHyst = 100; |
| 2259 | table->MemoryACPILevel.VoltageDownHyst = 0; |
| 2260 | /* Indicates maximum activity level for this performance level.*/ |
| 2261 | table->MemoryACPILevel.ActivityLevel = PP_HOST_TO_SMC_US((uint16_t)data->mclk_activity_target); |
| 2262 | |
| 2263 | table->MemoryACPILevel.StutterEnable = 0; |
| 2264 | table->MemoryACPILevel.StrobeEnable = 0; |
| 2265 | table->MemoryACPILevel.EdcReadEnable = 0; |
| 2266 | table->MemoryACPILevel.EdcWriteEnable = 0; |
| 2267 | table->MemoryACPILevel.RttEnable = 0; |
| 2268 | |
| 2269 | return result; |
| 2270 | } |
| 2271 | |
| 2272 | static int tonga_find_boot_level(struct tonga_single_dpm_table *table, uint32_t value, uint32_t *boot_level) |
| 2273 | { |
| 2274 | int result = 0; |
| 2275 | uint32_t i; |
| 2276 | |
| 2277 | for (i = 0; i < table->count; i++) { |
| 2278 | if (value == table->dpm_levels[i].value) { |
| 2279 | *boot_level = i; |
| 2280 | result = 0; |
| 2281 | } |
| 2282 | } |
| 2283 | return result; |
| 2284 | } |
| 2285 | |
| 2286 | static int tonga_populate_smc_boot_level(struct pp_hwmgr *hwmgr, |
| 2287 | SMU72_Discrete_DpmTable *table) |
| 2288 | { |
| 2289 | int result = 0; |
| 2290 | tonga_hwmgr *data = (tonga_hwmgr *)(hwmgr->backend); |
| 2291 | |
| 2292 | table->GraphicsBootLevel = 0; /* 0 == DPM[0] (low), etc. */ |
| 2293 | table->MemoryBootLevel = 0; /* 0 == DPM[0] (low), etc. */ |
| 2294 | |
| 2295 | /* find boot level from dpm table*/ |
| 2296 | result = tonga_find_boot_level(&(data->dpm_table.sclk_table), |
| 2297 | data->vbios_boot_state.sclk_bootup_value, |
| 2298 | (uint32_t *)&(data->smc_state_table.GraphicsBootLevel)); |
| 2299 | |
| 2300 | if (0 != result) { |
| 2301 | data->smc_state_table.GraphicsBootLevel = 0; |
| 2302 | printk(KERN_ERR "[ powerplay ] VBIOS did not find boot engine clock value \ |
| 2303 | in dependency table. Using Graphics DPM level 0!"); |
| 2304 | result = 0; |
| 2305 | } |
| 2306 | |
| 2307 | result = tonga_find_boot_level(&(data->dpm_table.mclk_table), |
| 2308 | data->vbios_boot_state.mclk_bootup_value, |
| 2309 | (uint32_t *)&(data->smc_state_table.MemoryBootLevel)); |
| 2310 | |
| 2311 | if (0 != result) { |
| 2312 | data->smc_state_table.MemoryBootLevel = 0; |
| 2313 | printk(KERN_ERR "[ powerplay ] VBIOS did not find boot engine clock value \ |
| 2314 | in dependency table. Using Memory DPM level 0!"); |
| 2315 | result = 0; |
| 2316 | } |
| 2317 | |
| 2318 | table->BootVoltage.Vddc = |
| 2319 | tonga_get_voltage_id(&(data->vddc_voltage_table), |
| 2320 | data->vbios_boot_state.vddc_bootup_value); |
| 2321 | table->BootVoltage.VddGfx = |
| 2322 | tonga_get_voltage_id(&(data->vddgfx_voltage_table), |
| 2323 | data->vbios_boot_state.vddgfx_bootup_value); |
| 2324 | table->BootVoltage.Vddci = |
| 2325 | tonga_get_voltage_id(&(data->vddci_voltage_table), |
| 2326 | data->vbios_boot_state.vddci_bootup_value); |
| 2327 | table->BootMVdd = data->vbios_boot_state.mvdd_bootup_value; |
| 2328 | |
| 2329 | CONVERT_FROM_HOST_TO_SMC_US(table->BootMVdd); |
| 2330 | |
| 2331 | return result; |
| 2332 | } |
| 2333 | |
| 2334 | |
| 2335 | /** |
| 2336 | * Calculates the SCLK dividers using the provided engine clock |
| 2337 | * |
| 2338 | * @param hwmgr the address of the hardware manager |
| 2339 | * @param engine_clock the engine clock to use to populate the structure |
| 2340 | * @param sclk the SMC SCLK structure to be populated |
| 2341 | */ |
| 2342 | int tonga_calculate_sclk_params(struct pp_hwmgr *hwmgr, |
| 2343 | uint32_t engine_clock, SMU72_Discrete_GraphicsLevel *sclk) |
| 2344 | { |
| 2345 | const tonga_hwmgr *data = (tonga_hwmgr *)(hwmgr->backend); |
| 2346 | pp_atomctrl_clock_dividers_vi dividers; |
| 2347 | uint32_t spll_func_cntl = data->clock_registers.vCG_SPLL_FUNC_CNTL; |
| 2348 | uint32_t spll_func_cntl_3 = data->clock_registers.vCG_SPLL_FUNC_CNTL_3; |
| 2349 | uint32_t spll_func_cntl_4 = data->clock_registers.vCG_SPLL_FUNC_CNTL_4; |
| 2350 | uint32_t cg_spll_spread_spectrum = data->clock_registers.vCG_SPLL_SPREAD_SPECTRUM; |
| 2351 | uint32_t cg_spll_spread_spectrum_2 = data->clock_registers.vCG_SPLL_SPREAD_SPECTRUM_2; |
| 2352 | uint32_t reference_clock; |
| 2353 | uint32_t reference_divider; |
| 2354 | uint32_t fbdiv; |
| 2355 | int result; |
| 2356 | |
| 2357 | /* get the engine clock dividers for this clock value*/ |
| 2358 | result = atomctrl_get_engine_pll_dividers_vi(hwmgr, engine_clock, ÷rs); |
| 2359 | |
| 2360 | PP_ASSERT_WITH_CODE(result == 0, |
| 2361 | "Error retrieving Engine Clock dividers from VBIOS.", return result); |
| 2362 | |
| 2363 | /* To get FBDIV we need to multiply this by 16384 and divide it by Fref.*/ |
| 2364 | reference_clock = atomctrl_get_reference_clock(hwmgr); |
| 2365 | |
| 2366 | reference_divider = 1 + dividers.uc_pll_ref_div; |
| 2367 | |
| 2368 | /* low 14 bits is fraction and high 12 bits is divider*/ |
| 2369 | fbdiv = dividers.ul_fb_div.ul_fb_divider & 0x3FFFFFF; |
| 2370 | |
| 2371 | /* SPLL_FUNC_CNTL setup*/ |
| 2372 | spll_func_cntl = PHM_SET_FIELD(spll_func_cntl, |
| 2373 | CG_SPLL_FUNC_CNTL, SPLL_REF_DIV, dividers.uc_pll_ref_div); |
| 2374 | spll_func_cntl = PHM_SET_FIELD(spll_func_cntl, |
| 2375 | CG_SPLL_FUNC_CNTL, SPLL_PDIV_A, dividers.uc_pll_post_div); |
| 2376 | |
| 2377 | /* SPLL_FUNC_CNTL_3 setup*/ |
| 2378 | spll_func_cntl_3 = PHM_SET_FIELD(spll_func_cntl_3, |
| 2379 | CG_SPLL_FUNC_CNTL_3, SPLL_FB_DIV, fbdiv); |
| 2380 | |
| 2381 | /* set to use fractional accumulation*/ |
| 2382 | spll_func_cntl_3 = PHM_SET_FIELD(spll_func_cntl_3, |
| 2383 | CG_SPLL_FUNC_CNTL_3, SPLL_DITHEN, 1); |
| 2384 | |
| 2385 | if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, |
| 2386 | PHM_PlatformCaps_EngineSpreadSpectrumSupport)) { |
| 2387 | pp_atomctrl_internal_ss_info ss_info; |
| 2388 | |
| 2389 | uint32_t vcoFreq = engine_clock * dividers.uc_pll_post_div; |
| 2390 | if (0 == atomctrl_get_engine_clock_spread_spectrum(hwmgr, vcoFreq, &ss_info)) { |
| 2391 | /* |
| 2392 | * ss_info.speed_spectrum_percentage -- in unit of 0.01% |
| 2393 | * ss_info.speed_spectrum_rate -- in unit of khz |
| 2394 | */ |
| 2395 | /* clks = reference_clock * 10 / (REFDIV + 1) / speed_spectrum_rate / 2 */ |
| 2396 | uint32_t clkS = reference_clock * 5 / (reference_divider * ss_info.speed_spectrum_rate); |
| 2397 | |
| 2398 | /* clkv = 2 * D * fbdiv / NS */ |
| 2399 | uint32_t clkV = 4 * ss_info.speed_spectrum_percentage * fbdiv / (clkS * 10000); |
| 2400 | |
| 2401 | cg_spll_spread_spectrum = |
| 2402 | PHM_SET_FIELD(cg_spll_spread_spectrum, CG_SPLL_SPREAD_SPECTRUM, CLKS, clkS); |
| 2403 | cg_spll_spread_spectrum = |
| 2404 | PHM_SET_FIELD(cg_spll_spread_spectrum, CG_SPLL_SPREAD_SPECTRUM, SSEN, 1); |
| 2405 | cg_spll_spread_spectrum_2 = |
| 2406 | PHM_SET_FIELD(cg_spll_spread_spectrum_2, CG_SPLL_SPREAD_SPECTRUM_2, CLKV, clkV); |
| 2407 | } |
| 2408 | } |
| 2409 | |
| 2410 | sclk->SclkFrequency = engine_clock; |
| 2411 | sclk->CgSpllFuncCntl3 = spll_func_cntl_3; |
| 2412 | sclk->CgSpllFuncCntl4 = spll_func_cntl_4; |
| 2413 | sclk->SpllSpreadSpectrum = cg_spll_spread_spectrum; |
| 2414 | sclk->SpllSpreadSpectrum2 = cg_spll_spread_spectrum_2; |
| 2415 | sclk->SclkDid = (uint8_t)dividers.pll_post_divider; |
| 2416 | |
| 2417 | return 0; |
| 2418 | } |
| 2419 | |
Nils Wallménius | 438498a | 2016-05-05 09:07:48 +0200 | [diff] [blame] | 2420 | static uint8_t tonga_get_sleep_divider_id_from_clock(uint32_t engine_clock, |
| 2421 | uint32_t min_engine_clock_in_sr) |
Eric Huang | a4333b4 | 2016-03-30 16:30:12 -0400 | [diff] [blame] | 2422 | { |
| 2423 | uint32_t i, temp; |
Nils Wallménius | 9887e42 | 2016-05-05 09:07:46 +0200 | [diff] [blame] | 2424 | uint32_t min = max(min_engine_clock_in_sr, (uint32_t)TONGA_MINIMUM_ENGINE_CLOCK); |
Eric Huang | a4333b4 | 2016-03-30 16:30:12 -0400 | [diff] [blame] | 2425 | |
| 2426 | PP_ASSERT_WITH_CODE((engine_clock >= min), |
| 2427 | "Engine clock can't satisfy stutter requirement!", return 0); |
| 2428 | |
| 2429 | for (i = TONGA_MAX_DEEPSLEEP_DIVIDER_ID;; i--) { |
Nils Wallménius | 354ef92 | 2016-05-05 09:07:47 +0200 | [diff] [blame] | 2430 | temp = engine_clock >> i; |
Eric Huang | a4333b4 | 2016-03-30 16:30:12 -0400 | [diff] [blame] | 2431 | |
| 2432 | if(temp >= min || i == 0) |
| 2433 | break; |
| 2434 | } |
| 2435 | return (uint8_t)i; |
| 2436 | } |
| 2437 | |
yanyang1 | c82baa2 | 2015-08-18 15:28:32 +0800 | [diff] [blame] | 2438 | /** |
| 2439 | * Populates single SMC SCLK structure using the provided engine clock |
| 2440 | * |
| 2441 | * @param hwmgr the address of the hardware manager |
| 2442 | * @param engine_clock the engine clock to use to populate the structure |
| 2443 | * @param sclk the SMC SCLK structure to be populated |
| 2444 | */ |
| 2445 | static int tonga_populate_single_graphic_level(struct pp_hwmgr *hwmgr, uint32_t engine_clock, uint16_t sclk_activity_level_threshold, SMU72_Discrete_GraphicsLevel *graphic_level) |
| 2446 | { |
| 2447 | int result; |
| 2448 | uint32_t threshold; |
| 2449 | uint32_t mvdd; |
| 2450 | tonga_hwmgr *data = (tonga_hwmgr *)(hwmgr->backend); |
| 2451 | struct phm_ppt_v1_information *pptable_info = (struct phm_ppt_v1_information *)(hwmgr->pptable); |
| 2452 | |
| 2453 | result = tonga_calculate_sclk_params(hwmgr, engine_clock, graphic_level); |
| 2454 | |
| 2455 | |
| 2456 | /* populate graphics levels*/ |
| 2457 | result = tonga_get_dependecy_volt_by_clk(hwmgr, |
| 2458 | pptable_info->vdd_dep_on_sclk, engine_clock, |
| 2459 | &graphic_level->MinVoltage, &mvdd); |
| 2460 | PP_ASSERT_WITH_CODE((0 == result), |
| 2461 | "can not find VDDC voltage value for VDDC \ |
| 2462 | engine clock dependency table", return result); |
| 2463 | |
| 2464 | /* SCLK frequency in units of 10KHz*/ |
| 2465 | graphic_level->SclkFrequency = engine_clock; |
| 2466 | |
| 2467 | /* Indicates maximum activity level for this performance level. 50% for now*/ |
| 2468 | graphic_level->ActivityLevel = sclk_activity_level_threshold; |
| 2469 | |
| 2470 | graphic_level->CcPwrDynRm = 0; |
| 2471 | graphic_level->CcPwrDynRm1 = 0; |
| 2472 | /* this level can be used if activity is high enough.*/ |
| 2473 | graphic_level->EnabledForActivity = 0; |
| 2474 | /* this level can be used for throttling.*/ |
| 2475 | graphic_level->EnabledForThrottle = 1; |
| 2476 | graphic_level->UpHyst = 0; |
| 2477 | graphic_level->DownHyst = 0; |
| 2478 | graphic_level->VoltageDownHyst = 0; |
| 2479 | graphic_level->PowerThrottle = 0; |
| 2480 | |
| 2481 | threshold = engine_clock * data->fast_watemark_threshold / 100; |
| 2482 | /* |
| 2483 | *get the DAL clock. do it in funture. |
| 2484 | PECI_GetMinClockSettings(hwmgr->peci, &minClocks); |
| 2485 | data->display_timing.min_clock_insr = minClocks.engineClockInSR; |
yanyang1 | c82baa2 | 2015-08-18 15:28:32 +0800 | [diff] [blame] | 2486 | */ |
Eric Huang | a4333b4 | 2016-03-30 16:30:12 -0400 | [diff] [blame] | 2487 | if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, |
| 2488 | PHM_PlatformCaps_SclkDeepSleep)) |
| 2489 | graphic_level->DeepSleepDivId = |
Nils Wallménius | 438498a | 2016-05-05 09:07:48 +0200 | [diff] [blame] | 2490 | tonga_get_sleep_divider_id_from_clock(engine_clock, |
Eric Huang | a4333b4 | 2016-03-30 16:30:12 -0400 | [diff] [blame] | 2491 | data->display_timing.min_clock_insr); |
yanyang1 | c82baa2 | 2015-08-18 15:28:32 +0800 | [diff] [blame] | 2492 | |
| 2493 | /* Default to slow, highest DPM level will be set to PPSMC_DISPLAY_WATERMARK_LOW later.*/ |
| 2494 | graphic_level->DisplayWatermark = PPSMC_DISPLAY_WATERMARK_LOW; |
| 2495 | |
| 2496 | if (0 == result) { |
| 2497 | /* CONVERT_FROM_HOST_TO_SMC_UL(graphic_level->MinVoltage);*/ |
| 2498 | /* CONVERT_FROM_HOST_TO_SMC_UL(graphic_level->MinVddcPhases);*/ |
| 2499 | CONVERT_FROM_HOST_TO_SMC_UL(graphic_level->SclkFrequency); |
| 2500 | CONVERT_FROM_HOST_TO_SMC_US(graphic_level->ActivityLevel); |
| 2501 | CONVERT_FROM_HOST_TO_SMC_UL(graphic_level->CgSpllFuncCntl3); |
| 2502 | CONVERT_FROM_HOST_TO_SMC_UL(graphic_level->CgSpllFuncCntl4); |
| 2503 | CONVERT_FROM_HOST_TO_SMC_UL(graphic_level->SpllSpreadSpectrum); |
| 2504 | CONVERT_FROM_HOST_TO_SMC_UL(graphic_level->SpllSpreadSpectrum2); |
| 2505 | CONVERT_FROM_HOST_TO_SMC_UL(graphic_level->CcPwrDynRm); |
| 2506 | CONVERT_FROM_HOST_TO_SMC_UL(graphic_level->CcPwrDynRm1); |
| 2507 | } |
| 2508 | |
| 2509 | return result; |
| 2510 | } |
| 2511 | |
| 2512 | /** |
| 2513 | * Populates all SMC SCLK levels' structure based on the trimmed allowed dpm engine clock states |
| 2514 | * |
| 2515 | * @param hwmgr the address of the hardware manager |
| 2516 | */ |
| 2517 | static int tonga_populate_all_graphic_levels(struct pp_hwmgr *hwmgr) |
| 2518 | { |
| 2519 | tonga_hwmgr *data = (tonga_hwmgr *)(hwmgr->backend); |
| 2520 | struct phm_ppt_v1_information *pptable_info = (struct phm_ppt_v1_information *)(hwmgr->pptable); |
| 2521 | struct tonga_dpm_table *dpm_table = &data->dpm_table; |
| 2522 | phm_ppt_v1_pcie_table *pcie_table = pptable_info->pcie_table; |
| 2523 | uint8_t pcie_entry_count = (uint8_t) data->dpm_table.pcie_speed_table.count; |
| 2524 | int result = 0; |
| 2525 | uint32_t level_array_adress = data->dpm_table_start + |
| 2526 | offsetof(SMU72_Discrete_DpmTable, GraphicsLevel); |
| 2527 | uint32_t level_array_size = sizeof(SMU72_Discrete_GraphicsLevel) * |
| 2528 | SMU72_MAX_LEVELS_GRAPHICS; /* 64 -> long; 32 -> int*/ |
| 2529 | SMU72_Discrete_GraphicsLevel *levels = data->smc_state_table.GraphicsLevel; |
| 2530 | uint32_t i, maxEntry; |
| 2531 | uint8_t highest_pcie_level_enabled = 0, lowest_pcie_level_enabled = 0, mid_pcie_level_enabled = 0, count = 0; |
| 2532 | PECI_RegistryValue reg_value; |
| 2533 | memset(levels, 0x00, level_array_size); |
| 2534 | |
| 2535 | for (i = 0; i < dpm_table->sclk_table.count; i++) { |
| 2536 | result = tonga_populate_single_graphic_level(hwmgr, |
| 2537 | dpm_table->sclk_table.dpm_levels[i].value, |
| 2538 | (uint16_t)data->activity_target[i], |
| 2539 | &(data->smc_state_table.GraphicsLevel[i])); |
| 2540 | |
| 2541 | if (0 != result) |
| 2542 | return result; |
| 2543 | |
| 2544 | /* Making sure only DPM level 0-1 have Deep Sleep Div ID populated. */ |
| 2545 | if (i > 1) |
| 2546 | data->smc_state_table.GraphicsLevel[i].DeepSleepDivId = 0; |
| 2547 | |
| 2548 | if (0 == i) { |
| 2549 | reg_value = 0; |
| 2550 | if (reg_value != 0) |
| 2551 | data->smc_state_table.GraphicsLevel[0].UpHyst = (uint8_t)reg_value; |
| 2552 | } |
| 2553 | |
| 2554 | if (1 == i) { |
| 2555 | reg_value = 0; |
| 2556 | if (reg_value != 0) |
| 2557 | data->smc_state_table.GraphicsLevel[1].UpHyst = (uint8_t)reg_value; |
| 2558 | } |
| 2559 | } |
| 2560 | |
| 2561 | /* Only enable level 0 for now. */ |
| 2562 | data->smc_state_table.GraphicsLevel[0].EnabledForActivity = 1; |
| 2563 | |
| 2564 | /* set highest level watermark to high */ |
| 2565 | if (dpm_table->sclk_table.count > 1) |
| 2566 | data->smc_state_table.GraphicsLevel[dpm_table->sclk_table.count-1].DisplayWatermark = |
| 2567 | PPSMC_DISPLAY_WATERMARK_HIGH; |
| 2568 | |
| 2569 | data->smc_state_table.GraphicsDpmLevelCount = |
| 2570 | (uint8_t)dpm_table->sclk_table.count; |
| 2571 | data->dpm_level_enable_mask.sclk_dpm_enable_mask = |
| 2572 | tonga_get_dpm_level_enable_mask_value(&dpm_table->sclk_table); |
| 2573 | |
| 2574 | if (pcie_table != NULL) { |
| 2575 | PP_ASSERT_WITH_CODE((pcie_entry_count >= 1), |
| 2576 | "There must be 1 or more PCIE levels defined in PPTable.", return -1); |
| 2577 | maxEntry = pcie_entry_count - 1; /* for indexing, we need to decrement by 1.*/ |
| 2578 | for (i = 0; i < dpm_table->sclk_table.count; i++) { |
| 2579 | data->smc_state_table.GraphicsLevel[i].pcieDpmLevel = |
| 2580 | (uint8_t) ((i < maxEntry) ? i : maxEntry); |
| 2581 | } |
| 2582 | } else { |
| 2583 | if (0 == data->dpm_level_enable_mask.pcie_dpm_enable_mask) |
| 2584 | printk(KERN_ERR "[ powerplay ] Pcie Dpm Enablemask is 0!"); |
| 2585 | |
| 2586 | while (data->dpm_level_enable_mask.pcie_dpm_enable_mask && |
| 2587 | ((data->dpm_level_enable_mask.pcie_dpm_enable_mask & |
| 2588 | (1<<(highest_pcie_level_enabled+1))) != 0)) { |
| 2589 | highest_pcie_level_enabled++; |
| 2590 | } |
| 2591 | |
| 2592 | while (data->dpm_level_enable_mask.pcie_dpm_enable_mask && |
| 2593 | ((data->dpm_level_enable_mask.pcie_dpm_enable_mask & |
| 2594 | (1<<lowest_pcie_level_enabled)) == 0)) { |
| 2595 | lowest_pcie_level_enabled++; |
| 2596 | } |
| 2597 | |
| 2598 | while ((count < highest_pcie_level_enabled) && |
| 2599 | ((data->dpm_level_enable_mask.pcie_dpm_enable_mask & |
| 2600 | (1<<(lowest_pcie_level_enabled+1+count))) == 0)) { |
| 2601 | count++; |
| 2602 | } |
| 2603 | mid_pcie_level_enabled = (lowest_pcie_level_enabled+1+count) < highest_pcie_level_enabled ? |
| 2604 | (lowest_pcie_level_enabled+1+count) : highest_pcie_level_enabled; |
| 2605 | |
| 2606 | |
| 2607 | /* set pcieDpmLevel to highest_pcie_level_enabled*/ |
| 2608 | for (i = 2; i < dpm_table->sclk_table.count; i++) { |
| 2609 | data->smc_state_table.GraphicsLevel[i].pcieDpmLevel = highest_pcie_level_enabled; |
| 2610 | } |
| 2611 | |
| 2612 | /* set pcieDpmLevel to lowest_pcie_level_enabled*/ |
| 2613 | data->smc_state_table.GraphicsLevel[0].pcieDpmLevel = lowest_pcie_level_enabled; |
| 2614 | |
| 2615 | /* set pcieDpmLevel to mid_pcie_level_enabled*/ |
| 2616 | data->smc_state_table.GraphicsLevel[1].pcieDpmLevel = mid_pcie_level_enabled; |
| 2617 | } |
| 2618 | /* level count will send to smc once at init smc table and never change*/ |
| 2619 | result = tonga_copy_bytes_to_smc(hwmgr->smumgr, level_array_adress, (uint8_t *)levels, (uint32_t)level_array_size, data->sram_end); |
| 2620 | |
| 2621 | if (0 != result) |
| 2622 | return result; |
| 2623 | |
| 2624 | return 0; |
| 2625 | } |
| 2626 | |
| 2627 | /** |
| 2628 | * Populates all SMC MCLK levels' structure based on the trimmed allowed dpm memory clock states |
| 2629 | * |
| 2630 | * @param hwmgr the address of the hardware manager |
| 2631 | */ |
| 2632 | |
| 2633 | static int tonga_populate_all_memory_levels(struct pp_hwmgr *hwmgr) |
| 2634 | { |
| 2635 | tonga_hwmgr *data = (tonga_hwmgr *)(hwmgr->backend); |
| 2636 | struct tonga_dpm_table *dpm_table = &data->dpm_table; |
| 2637 | int result; |
| 2638 | /* populate MCLK dpm table to SMU7 */ |
| 2639 | uint32_t level_array_adress = data->dpm_table_start + offsetof(SMU72_Discrete_DpmTable, MemoryLevel); |
| 2640 | uint32_t level_array_size = sizeof(SMU72_Discrete_MemoryLevel) * SMU72_MAX_LEVELS_MEMORY; |
| 2641 | SMU72_Discrete_MemoryLevel *levels = data->smc_state_table.MemoryLevel; |
| 2642 | uint32_t i; |
| 2643 | |
| 2644 | memset(levels, 0x00, level_array_size); |
| 2645 | |
| 2646 | for (i = 0; i < dpm_table->mclk_table.count; i++) { |
| 2647 | PP_ASSERT_WITH_CODE((0 != dpm_table->mclk_table.dpm_levels[i].value), |
| 2648 | "can not populate memory level as memory clock is zero", return -1); |
| 2649 | result = tonga_populate_single_memory_level(hwmgr, dpm_table->mclk_table.dpm_levels[i].value, |
| 2650 | &(data->smc_state_table.MemoryLevel[i])); |
| 2651 | if (0 != result) { |
| 2652 | return result; |
| 2653 | } |
| 2654 | } |
| 2655 | |
| 2656 | /* Only enable level 0 for now.*/ |
| 2657 | data->smc_state_table.MemoryLevel[0].EnabledForActivity = 1; |
| 2658 | |
| 2659 | /* |
| 2660 | * in order to prevent MC activity from stutter mode to push DPM up. |
| 2661 | * the UVD change complements this by putting the MCLK in a higher state |
| 2662 | * by default such that we are not effected by up threshold or and MCLK DPM latency. |
| 2663 | */ |
| 2664 | data->smc_state_table.MemoryLevel[0].ActivityLevel = 0x1F; |
| 2665 | CONVERT_FROM_HOST_TO_SMC_US(data->smc_state_table.MemoryLevel[0].ActivityLevel); |
| 2666 | |
| 2667 | data->smc_state_table.MemoryDpmLevelCount = (uint8_t)dpm_table->mclk_table.count; |
| 2668 | data->dpm_level_enable_mask.mclk_dpm_enable_mask = tonga_get_dpm_level_enable_mask_value(&dpm_table->mclk_table); |
| 2669 | /* set highest level watermark to high*/ |
| 2670 | data->smc_state_table.MemoryLevel[dpm_table->mclk_table.count-1].DisplayWatermark = PPSMC_DISPLAY_WATERMARK_HIGH; |
| 2671 | |
| 2672 | /* level count will send to smc once at init smc table and never change*/ |
| 2673 | result = tonga_copy_bytes_to_smc(hwmgr->smumgr, |
| 2674 | level_array_adress, (uint8_t *)levels, (uint32_t)level_array_size, data->sram_end); |
| 2675 | |
| 2676 | if (0 != result) { |
| 2677 | return result; |
| 2678 | } |
| 2679 | |
| 2680 | return 0; |
| 2681 | } |
| 2682 | |
| 2683 | struct TONGA_DLL_SPEED_SETTING { |
| 2684 | uint16_t Min; /* Minimum Data Rate*/ |
| 2685 | uint16_t Max; /* Maximum Data Rate*/ |
Christian König | edf600d | 2016-05-03 15:54:54 +0200 | [diff] [blame] | 2686 | uint32_t dll_speed; /* The desired DLL_SPEED setting*/ |
yanyang1 | c82baa2 | 2015-08-18 15:28:32 +0800 | [diff] [blame] | 2687 | }; |
| 2688 | |
| 2689 | static int tonga_populate_clock_stretcher_data_table(struct pp_hwmgr *hwmgr) |
| 2690 | { |
| 2691 | return 0; |
| 2692 | } |
| 2693 | |
| 2694 | /* ---------------------------------------- ULV related functions ----------------------------------------------------*/ |
| 2695 | |
| 2696 | |
| 2697 | static int tonga_reset_single_dpm_table( |
| 2698 | struct pp_hwmgr *hwmgr, |
| 2699 | struct tonga_single_dpm_table *dpm_table, |
| 2700 | uint32_t count) |
| 2701 | { |
| 2702 | uint32_t i; |
| 2703 | if (!(count <= MAX_REGULAR_DPM_NUMBER)) |
| 2704 | printk(KERN_ERR "[ powerplay ] Fatal error, can not set up single DPM \ |
| 2705 | table entries to exceed max number! \n"); |
| 2706 | |
| 2707 | dpm_table->count = count; |
| 2708 | for (i = 0; i < MAX_REGULAR_DPM_NUMBER; i++) { |
Edward O'Callaghan | ed5121a | 2016-07-12 10:17:52 +1000 | [diff] [blame] | 2709 | dpm_table->dpm_levels[i].enabled = false; |
yanyang1 | c82baa2 | 2015-08-18 15:28:32 +0800 | [diff] [blame] | 2710 | } |
| 2711 | |
| 2712 | return 0; |
| 2713 | } |
| 2714 | |
| 2715 | static void tonga_setup_pcie_table_entry( |
| 2716 | struct tonga_single_dpm_table *dpm_table, |
| 2717 | uint32_t index, uint32_t pcie_gen, |
| 2718 | uint32_t pcie_lanes) |
| 2719 | { |
| 2720 | dpm_table->dpm_levels[index].value = pcie_gen; |
| 2721 | dpm_table->dpm_levels[index].param1 = pcie_lanes; |
Edward O'Callaghan | ed5121a | 2016-07-12 10:17:52 +1000 | [diff] [blame] | 2722 | dpm_table->dpm_levels[index].enabled = true; |
yanyang1 | c82baa2 | 2015-08-18 15:28:32 +0800 | [diff] [blame] | 2723 | } |
| 2724 | |
yanyang1 | c82baa2 | 2015-08-18 15:28:32 +0800 | [diff] [blame] | 2725 | static int tonga_setup_default_pcie_tables(struct pp_hwmgr *hwmgr) |
| 2726 | { |
| 2727 | tonga_hwmgr *data = (tonga_hwmgr *)(hwmgr->backend); |
| 2728 | struct phm_ppt_v1_information *pptable_info = (struct phm_ppt_v1_information *)(hwmgr->pptable); |
| 2729 | phm_ppt_v1_pcie_table *pcie_table = pptable_info->pcie_table; |
| 2730 | uint32_t i, maxEntry; |
| 2731 | |
| 2732 | if (data->use_pcie_performance_levels && !data->use_pcie_power_saving_levels) { |
| 2733 | data->pcie_gen_power_saving = data->pcie_gen_performance; |
| 2734 | data->pcie_lane_power_saving = data->pcie_lane_performance; |
| 2735 | } else if (!data->use_pcie_performance_levels && data->use_pcie_power_saving_levels) { |
| 2736 | data->pcie_gen_performance = data->pcie_gen_power_saving; |
| 2737 | data->pcie_lane_performance = data->pcie_lane_power_saving; |
| 2738 | } |
| 2739 | |
| 2740 | tonga_reset_single_dpm_table(hwmgr, &data->dpm_table.pcie_speed_table, SMU72_MAX_LEVELS_LINK); |
| 2741 | |
| 2742 | if (pcie_table != NULL) { |
| 2743 | /* |
| 2744 | * maxEntry is used to make sure we reserve one PCIE level for boot level (fix for A+A PSPP issue). |
| 2745 | * If PCIE table from PPTable have ULV entry + 8 entries, then ignore the last entry. |
| 2746 | */ |
| 2747 | maxEntry = (SMU72_MAX_LEVELS_LINK < pcie_table->count) ? |
| 2748 | SMU72_MAX_LEVELS_LINK : pcie_table->count; |
| 2749 | for (i = 1; i < maxEntry; i++) { |
| 2750 | tonga_setup_pcie_table_entry(&data->dpm_table.pcie_speed_table, i-1, |
| 2751 | get_pcie_gen_support(data->pcie_gen_cap, pcie_table->entries[i].gen_speed), |
| 2752 | get_pcie_lane_support(data->pcie_lane_cap, PP_Max_PCIELane)); |
| 2753 | } |
| 2754 | data->dpm_table.pcie_speed_table.count = maxEntry - 1; |
| 2755 | } else { |
| 2756 | /* Hardcode Pcie Table */ |
| 2757 | tonga_setup_pcie_table_entry(&data->dpm_table.pcie_speed_table, 0, |
| 2758 | get_pcie_gen_support(data->pcie_gen_cap, PP_Min_PCIEGen), |
| 2759 | get_pcie_lane_support(data->pcie_lane_cap, PP_Max_PCIELane)); |
| 2760 | tonga_setup_pcie_table_entry(&data->dpm_table.pcie_speed_table, 1, |
| 2761 | get_pcie_gen_support(data->pcie_gen_cap, PP_Min_PCIEGen), |
| 2762 | get_pcie_lane_support(data->pcie_lane_cap, PP_Max_PCIELane)); |
| 2763 | tonga_setup_pcie_table_entry(&data->dpm_table.pcie_speed_table, 2, |
| 2764 | get_pcie_gen_support(data->pcie_gen_cap, PP_Max_PCIEGen), |
| 2765 | get_pcie_lane_support(data->pcie_lane_cap, PP_Max_PCIELane)); |
| 2766 | tonga_setup_pcie_table_entry(&data->dpm_table.pcie_speed_table, 3, |
| 2767 | get_pcie_gen_support(data->pcie_gen_cap, PP_Max_PCIEGen), |
| 2768 | get_pcie_lane_support(data->pcie_lane_cap, PP_Max_PCIELane)); |
| 2769 | tonga_setup_pcie_table_entry(&data->dpm_table.pcie_speed_table, 4, |
| 2770 | get_pcie_gen_support(data->pcie_gen_cap, PP_Max_PCIEGen), |
| 2771 | get_pcie_lane_support(data->pcie_lane_cap, PP_Max_PCIELane)); |
| 2772 | tonga_setup_pcie_table_entry(&data->dpm_table.pcie_speed_table, 5, |
| 2773 | get_pcie_gen_support(data->pcie_gen_cap, PP_Max_PCIEGen), |
| 2774 | get_pcie_lane_support(data->pcie_lane_cap, PP_Max_PCIELane)); |
| 2775 | data->dpm_table.pcie_speed_table.count = 6; |
| 2776 | } |
| 2777 | /* Populate last level for boot PCIE level, but do not increment count. */ |
| 2778 | tonga_setup_pcie_table_entry(&data->dpm_table.pcie_speed_table, |
| 2779 | data->dpm_table.pcie_speed_table.count, |
| 2780 | get_pcie_gen_support(data->pcie_gen_cap, PP_Min_PCIEGen), |
| 2781 | get_pcie_lane_support(data->pcie_lane_cap, PP_Max_PCIELane)); |
| 2782 | |
| 2783 | return 0; |
| 2784 | |
| 2785 | } |
| 2786 | |
| 2787 | /* |
| 2788 | * This function is to initalize all DPM state tables for SMU7 based on the dependency table. |
| 2789 | * Dynamic state patching function will then trim these state tables to the allowed range based |
| 2790 | * on the power policy or external client requests, such as UVD request, etc. |
| 2791 | */ |
| 2792 | static int tonga_setup_default_dpm_tables(struct pp_hwmgr *hwmgr) |
| 2793 | { |
| 2794 | tonga_hwmgr *data = (tonga_hwmgr *)(hwmgr->backend); |
| 2795 | struct phm_ppt_v1_information *pptable_info = (struct phm_ppt_v1_information *)(hwmgr->pptable); |
| 2796 | uint32_t i; |
| 2797 | |
| 2798 | phm_ppt_v1_clock_voltage_dependency_table *allowed_vdd_sclk_table = |
| 2799 | pptable_info->vdd_dep_on_sclk; |
| 2800 | phm_ppt_v1_clock_voltage_dependency_table *allowed_vdd_mclk_table = |
| 2801 | pptable_info->vdd_dep_on_mclk; |
| 2802 | |
| 2803 | PP_ASSERT_WITH_CODE(allowed_vdd_sclk_table != NULL, |
| 2804 | "SCLK dependency table is missing. This table is mandatory", return -1); |
| 2805 | PP_ASSERT_WITH_CODE(allowed_vdd_sclk_table->count >= 1, |
| 2806 | "SCLK dependency table has to have is missing. This table is mandatory", return -1); |
| 2807 | |
| 2808 | PP_ASSERT_WITH_CODE(allowed_vdd_mclk_table != NULL, |
| 2809 | "MCLK dependency table is missing. This table is mandatory", return -1); |
| 2810 | PP_ASSERT_WITH_CODE(allowed_vdd_mclk_table->count >= 1, |
| 2811 | "VMCLK dependency table has to have is missing. This table is mandatory", return -1); |
| 2812 | |
| 2813 | /* clear the state table to reset everything to default */ |
| 2814 | memset(&(data->dpm_table), 0x00, sizeof(data->dpm_table)); |
| 2815 | tonga_reset_single_dpm_table(hwmgr, &data->dpm_table.sclk_table, SMU72_MAX_LEVELS_GRAPHICS); |
| 2816 | tonga_reset_single_dpm_table(hwmgr, &data->dpm_table.mclk_table, SMU72_MAX_LEVELS_MEMORY); |
| 2817 | /* tonga_reset_single_dpm_table(hwmgr, &tonga_hwmgr->dpm_table.VddcTable, SMU72_MAX_LEVELS_VDDC); */ |
| 2818 | /* tonga_reset_single_dpm_table(hwmgr, &tonga_hwmgr->dpm_table.vdd_gfx_table, SMU72_MAX_LEVELS_VDDGFX);*/ |
| 2819 | /* tonga_reset_single_dpm_table(hwmgr, &tonga_hwmgr->dpm_table.vdd_ci_table, SMU72_MAX_LEVELS_VDDCI);*/ |
| 2820 | /* tonga_reset_single_dpm_table(hwmgr, &tonga_hwmgr->dpm_table.mvdd_table, SMU72_MAX_LEVELS_MVDD);*/ |
| 2821 | |
| 2822 | PP_ASSERT_WITH_CODE(allowed_vdd_sclk_table != NULL, |
| 2823 | "SCLK dependency table is missing. This table is mandatory", return -1); |
| 2824 | /* Initialize Sclk DPM table based on allow Sclk values*/ |
| 2825 | data->dpm_table.sclk_table.count = 0; |
| 2826 | |
| 2827 | for (i = 0; i < allowed_vdd_sclk_table->count; i++) { |
| 2828 | if (i == 0 || data->dpm_table.sclk_table.dpm_levels[data->dpm_table.sclk_table.count-1].value != |
| 2829 | allowed_vdd_sclk_table->entries[i].clk) { |
| 2830 | data->dpm_table.sclk_table.dpm_levels[data->dpm_table.sclk_table.count].value = |
| 2831 | allowed_vdd_sclk_table->entries[i].clk; |
Edward O'Callaghan | ed5121a | 2016-07-12 10:17:52 +1000 | [diff] [blame] | 2832 | data->dpm_table.sclk_table.dpm_levels[data->dpm_table.sclk_table.count].enabled = true; /*(i==0) ? 1 : 0; to do */ |
yanyang1 | c82baa2 | 2015-08-18 15:28:32 +0800 | [diff] [blame] | 2833 | data->dpm_table.sclk_table.count++; |
| 2834 | } |
| 2835 | } |
| 2836 | |
| 2837 | PP_ASSERT_WITH_CODE(allowed_vdd_mclk_table != NULL, |
| 2838 | "MCLK dependency table is missing. This table is mandatory", return -1); |
| 2839 | /* Initialize Mclk DPM table based on allow Mclk values */ |
| 2840 | data->dpm_table.mclk_table.count = 0; |
| 2841 | for (i = 0; i < allowed_vdd_mclk_table->count; i++) { |
| 2842 | if (i == 0 || data->dpm_table.mclk_table.dpm_levels[data->dpm_table.mclk_table.count-1].value != |
| 2843 | allowed_vdd_mclk_table->entries[i].clk) { |
| 2844 | data->dpm_table.mclk_table.dpm_levels[data->dpm_table.mclk_table.count].value = |
| 2845 | allowed_vdd_mclk_table->entries[i].clk; |
Edward O'Callaghan | ed5121a | 2016-07-12 10:17:52 +1000 | [diff] [blame] | 2846 | data->dpm_table.mclk_table.dpm_levels[data->dpm_table.mclk_table.count].enabled = true; /*(i==0) ? 1 : 0; */ |
yanyang1 | c82baa2 | 2015-08-18 15:28:32 +0800 | [diff] [blame] | 2847 | data->dpm_table.mclk_table.count++; |
| 2848 | } |
| 2849 | } |
| 2850 | |
yanyang1 | c82baa2 | 2015-08-18 15:28:32 +0800 | [diff] [blame] | 2851 | /* setup PCIE gen speed levels*/ |
| 2852 | tonga_setup_default_pcie_tables(hwmgr); |
| 2853 | |
| 2854 | /* save a copy of the default DPM table*/ |
| 2855 | memcpy(&(data->golden_dpm_table), &(data->dpm_table), sizeof(struct tonga_dpm_table)); |
| 2856 | |
| 2857 | return 0; |
| 2858 | } |
| 2859 | |
| 2860 | int tonga_populate_smc_initial_state(struct pp_hwmgr *hwmgr, |
| 2861 | const struct tonga_power_state *bootState) |
| 2862 | { |
| 2863 | tonga_hwmgr *data = (tonga_hwmgr *)(hwmgr->backend); |
| 2864 | struct phm_ppt_v1_information *pptable_info = (struct phm_ppt_v1_information *)(hwmgr->pptable); |
| 2865 | uint8_t count, level; |
| 2866 | |
| 2867 | count = (uint8_t) (pptable_info->vdd_dep_on_sclk->count); |
| 2868 | for (level = 0; level < count; level++) { |
| 2869 | if (pptable_info->vdd_dep_on_sclk->entries[level].clk >= |
| 2870 | bootState->performance_levels[0].engine_clock) { |
| 2871 | data->smc_state_table.GraphicsBootLevel = level; |
| 2872 | break; |
| 2873 | } |
| 2874 | } |
| 2875 | |
| 2876 | count = (uint8_t) (pptable_info->vdd_dep_on_mclk->count); |
| 2877 | for (level = 0; level < count; level++) { |
| 2878 | if (pptable_info->vdd_dep_on_mclk->entries[level].clk >= |
| 2879 | bootState->performance_levels[0].memory_clock) { |
| 2880 | data->smc_state_table.MemoryBootLevel = level; |
| 2881 | break; |
| 2882 | } |
| 2883 | } |
| 2884 | |
| 2885 | return 0; |
| 2886 | } |
| 2887 | |
| 2888 | /** |
| 2889 | * Initializes the SMC table and uploads it |
| 2890 | * |
| 2891 | * @param hwmgr the address of the powerplay hardware manager. |
| 2892 | * @param pInput the pointer to input data (PowerState) |
| 2893 | * @return always 0 |
| 2894 | */ |
| 2895 | int tonga_init_smc_table(struct pp_hwmgr *hwmgr) |
| 2896 | { |
| 2897 | int result; |
| 2898 | tonga_hwmgr *data = (tonga_hwmgr *)(hwmgr->backend); |
| 2899 | struct phm_ppt_v1_information *pptable_info = (struct phm_ppt_v1_information *)(hwmgr->pptable); |
| 2900 | SMU72_Discrete_DpmTable *table = &(data->smc_state_table); |
| 2901 | const phw_tonga_ulv_parm *ulv = &(data->ulv); |
| 2902 | uint8_t i; |
| 2903 | PECI_RegistryValue reg_value; |
| 2904 | pp_atomctrl_gpio_pin_assignment gpio_pin_assignment; |
| 2905 | |
| 2906 | result = tonga_setup_default_dpm_tables(hwmgr); |
| 2907 | PP_ASSERT_WITH_CODE(0 == result, |
| 2908 | "Failed to setup default DPM tables!", return result;); |
| 2909 | memset(&(data->smc_state_table), 0x00, sizeof(data->smc_state_table)); |
| 2910 | if (TONGA_VOLTAGE_CONTROL_NONE != data->voltage_control) { |
| 2911 | tonga_populate_smc_voltage_tables(hwmgr, table); |
| 2912 | } |
| 2913 | |
| 2914 | if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, |
| 2915 | PHM_PlatformCaps_AutomaticDCTransition)) { |
| 2916 | table->SystemFlags |= PPSMC_SYSTEMFLAG_GPIO_DC; |
| 2917 | } |
| 2918 | |
| 2919 | if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, |
| 2920 | PHM_PlatformCaps_StepVddc)) { |
| 2921 | table->SystemFlags |= PPSMC_SYSTEMFLAG_STEPVDDC; |
| 2922 | } |
| 2923 | |
| 2924 | if (data->is_memory_GDDR5) { |
| 2925 | table->SystemFlags |= PPSMC_SYSTEMFLAG_GDDR5; |
| 2926 | } |
| 2927 | |
| 2928 | i = PHM_READ_FIELD(hwmgr->device, CC_MC_MAX_CHANNEL, NOOFCHAN); |
| 2929 | |
| 2930 | if (i == 1 || i == 0) { |
| 2931 | table->SystemFlags |= PPSMC_SYSTEMFLAG_12CHANNEL; |
| 2932 | } |
| 2933 | |
| 2934 | if (ulv->ulv_supported && pptable_info->us_ulv_voltage_offset) { |
| 2935 | PP_ASSERT_WITH_CODE(0 == result, |
| 2936 | "Failed to initialize ULV state!", return result;); |
| 2937 | |
| 2938 | cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, |
| 2939 | ixCG_ULV_PARAMETER, ulv->ch_ulv_parameter); |
| 2940 | } |
| 2941 | |
| 2942 | result = tonga_populate_smc_link_level(hwmgr, table); |
| 2943 | PP_ASSERT_WITH_CODE(0 == result, |
| 2944 | "Failed to initialize Link Level!", return result;); |
| 2945 | |
| 2946 | result = tonga_populate_all_graphic_levels(hwmgr); |
| 2947 | PP_ASSERT_WITH_CODE(0 == result, |
| 2948 | "Failed to initialize Graphics Level!", return result;); |
| 2949 | |
| 2950 | result = tonga_populate_all_memory_levels(hwmgr); |
| 2951 | PP_ASSERT_WITH_CODE(0 == result, |
| 2952 | "Failed to initialize Memory Level!", return result;); |
| 2953 | |
| 2954 | result = tonga_populate_smv_acpi_level(hwmgr, table); |
| 2955 | PP_ASSERT_WITH_CODE(0 == result, |
| 2956 | "Failed to initialize ACPI Level!", return result;); |
| 2957 | |
| 2958 | result = tonga_populate_smc_vce_level(hwmgr, table); |
| 2959 | PP_ASSERT_WITH_CODE(0 == result, |
| 2960 | "Failed to initialize VCE Level!", return result;); |
| 2961 | |
| 2962 | result = tonga_populate_smc_acp_level(hwmgr, table); |
| 2963 | PP_ASSERT_WITH_CODE(0 == result, |
| 2964 | "Failed to initialize ACP Level!", return result;); |
| 2965 | |
| 2966 | result = tonga_populate_smc_samu_level(hwmgr, table); |
| 2967 | PP_ASSERT_WITH_CODE(0 == result, |
| 2968 | "Failed to initialize SAMU Level!", return result;); |
| 2969 | |
| 2970 | /* Since only the initial state is completely set up at this point (the other states are just copies of the boot state) we only */ |
| 2971 | /* need to populate the ARB settings for the initial state. */ |
| 2972 | result = tonga_program_memory_timing_parameters(hwmgr); |
| 2973 | PP_ASSERT_WITH_CODE(0 == result, |
| 2974 | "Failed to Write ARB settings for the initial state.", return result;); |
| 2975 | |
Alex Deucher | 0104aa2 | 2015-11-13 10:46:30 -0500 | [diff] [blame] | 2976 | result = tonga_populate_smc_uvd_level(hwmgr, table); |
| 2977 | PP_ASSERT_WITH_CODE(0 == result, |
| 2978 | "Failed to initialize UVD Level!", return result;); |
| 2979 | |
yanyang1 | c82baa2 | 2015-08-18 15:28:32 +0800 | [diff] [blame] | 2980 | result = tonga_populate_smc_boot_level(hwmgr, table); |
| 2981 | PP_ASSERT_WITH_CODE(0 == result, |
| 2982 | "Failed to initialize Boot Level!", return result;); |
| 2983 | |
| 2984 | if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, |
| 2985 | PHM_PlatformCaps_ClockStretcher)) { |
| 2986 | result = tonga_populate_clock_stretcher_data_table(hwmgr); |
| 2987 | PP_ASSERT_WITH_CODE(0 == result, |
| 2988 | "Failed to populate Clock Stretcher Data Table!", return result;); |
| 2989 | } |
| 2990 | table->GraphicsVoltageChangeEnable = 1; |
| 2991 | table->GraphicsThermThrottleEnable = 1; |
| 2992 | table->GraphicsInterval = 1; |
| 2993 | table->VoltageInterval = 1; |
| 2994 | table->ThermalInterval = 1; |
| 2995 | table->TemperatureLimitHigh = |
| 2996 | pptable_info->cac_dtp_table->usTargetOperatingTemp * |
| 2997 | TONGA_Q88_FORMAT_CONVERSION_UNIT; |
| 2998 | table->TemperatureLimitLow = |
| 2999 | (pptable_info->cac_dtp_table->usTargetOperatingTemp - 1) * |
| 3000 | TONGA_Q88_FORMAT_CONVERSION_UNIT; |
| 3001 | table->MemoryVoltageChangeEnable = 1; |
| 3002 | table->MemoryInterval = 1; |
| 3003 | table->VoltageResponseTime = 0; |
| 3004 | table->PhaseResponseTime = 0; |
| 3005 | table->MemoryThermThrottleEnable = 1; |
| 3006 | |
| 3007 | /* |
| 3008 | * Cail reads current link status and reports it as cap (we cannot change this due to some previous issues we had) |
| 3009 | * SMC drops the link status to lowest level after enabling DPM by PowerPlay. After pnp or toggling CF, driver gets reloaded again |
| 3010 | * but this time Cail reads current link status which was set to low by SMC and reports it as cap to powerplay |
| 3011 | * To avoid it, we set PCIeBootLinkLevel to highest dpm level |
| 3012 | */ |
| 3013 | PP_ASSERT_WITH_CODE((1 <= data->dpm_table.pcie_speed_table.count), |
| 3014 | "There must be 1 or more PCIE levels defined in PPTable.", |
| 3015 | return -1); |
| 3016 | |
| 3017 | table->PCIeBootLinkLevel = (uint8_t) (data->dpm_table.pcie_speed_table.count); |
| 3018 | |
| 3019 | table->PCIeGenInterval = 1; |
| 3020 | |
| 3021 | result = tonga_populate_vr_config(hwmgr, table); |
| 3022 | PP_ASSERT_WITH_CODE(0 == result, |
| 3023 | "Failed to populate VRConfig setting!", return result); |
| 3024 | |
| 3025 | table->ThermGpio = 17; |
| 3026 | table->SclkStepSize = 0x4000; |
| 3027 | |
| 3028 | reg_value = 0; |
| 3029 | if ((0 == reg_value) && |
Rex Zhu | e013c91 | 2016-06-29 19:48:58 +0800 | [diff] [blame] | 3030 | (atomctrl_get_pp_assign_pin(hwmgr, VDDC_VRHOT_GPIO_PINID, |
| 3031 | &gpio_pin_assignment))) { |
yanyang1 | c82baa2 | 2015-08-18 15:28:32 +0800 | [diff] [blame] | 3032 | table->VRHotGpio = gpio_pin_assignment.uc_gpio_pin_bit_shift; |
| 3033 | phm_cap_set(hwmgr->platform_descriptor.platformCaps, |
| 3034 | PHM_PlatformCaps_RegulatorHot); |
| 3035 | } else { |
| 3036 | table->VRHotGpio = TONGA_UNUSED_GPIO_PIN; |
| 3037 | phm_cap_unset(hwmgr->platform_descriptor.platformCaps, |
| 3038 | PHM_PlatformCaps_RegulatorHot); |
| 3039 | } |
| 3040 | |
| 3041 | /* ACDC Switch GPIO */ |
| 3042 | reg_value = 0; |
| 3043 | if ((0 == reg_value) && |
Rex Zhu | e013c91 | 2016-06-29 19:48:58 +0800 | [diff] [blame] | 3044 | (atomctrl_get_pp_assign_pin(hwmgr, PP_AC_DC_SWITCH_GPIO_PINID, |
| 3045 | &gpio_pin_assignment))) { |
yanyang1 | c82baa2 | 2015-08-18 15:28:32 +0800 | [diff] [blame] | 3046 | table->AcDcGpio = gpio_pin_assignment.uc_gpio_pin_bit_shift; |
| 3047 | phm_cap_set(hwmgr->platform_descriptor.platformCaps, |
| 3048 | PHM_PlatformCaps_AutomaticDCTransition); |
| 3049 | } else { |
| 3050 | table->AcDcGpio = TONGA_UNUSED_GPIO_PIN; |
| 3051 | phm_cap_unset(hwmgr->platform_descriptor.platformCaps, |
| 3052 | PHM_PlatformCaps_AutomaticDCTransition); |
| 3053 | } |
| 3054 | |
| 3055 | phm_cap_unset(hwmgr->platform_descriptor.platformCaps, |
| 3056 | PHM_PlatformCaps_Falcon_QuickTransition); |
| 3057 | |
| 3058 | reg_value = 0; |
| 3059 | if (1 == reg_value) { |
| 3060 | phm_cap_unset(hwmgr->platform_descriptor.platformCaps, |
| 3061 | PHM_PlatformCaps_AutomaticDCTransition); |
| 3062 | phm_cap_set(hwmgr->platform_descriptor.platformCaps, |
| 3063 | PHM_PlatformCaps_Falcon_QuickTransition); |
| 3064 | } |
| 3065 | |
| 3066 | reg_value = 0; |
Rex Zhu | e013c91 | 2016-06-29 19:48:58 +0800 | [diff] [blame] | 3067 | if ((0 == reg_value) && (atomctrl_get_pp_assign_pin(hwmgr, |
yanyang1 | c82baa2 | 2015-08-18 15:28:32 +0800 | [diff] [blame] | 3068 | THERMAL_INT_OUTPUT_GPIO_PINID, &gpio_pin_assignment))) { |
| 3069 | phm_cap_set(hwmgr->platform_descriptor.platformCaps, |
| 3070 | PHM_PlatformCaps_ThermalOutGPIO); |
| 3071 | |
| 3072 | table->ThermOutGpio = gpio_pin_assignment.uc_gpio_pin_bit_shift; |
| 3073 | |
| 3074 | table->ThermOutPolarity = |
| 3075 | (0 == (cgs_read_register(hwmgr->device, mmGPIOPAD_A) & |
| 3076 | (1 << gpio_pin_assignment.uc_gpio_pin_bit_shift))) ? 1:0; |
| 3077 | |
| 3078 | table->ThermOutMode = SMU7_THERM_OUT_MODE_THERM_ONLY; |
| 3079 | |
| 3080 | /* if required, combine VRHot/PCC with thermal out GPIO*/ |
| 3081 | if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, |
| 3082 | PHM_PlatformCaps_RegulatorHot) && |
| 3083 | phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, |
| 3084 | PHM_PlatformCaps_CombinePCCWithThermalSignal)){ |
| 3085 | table->ThermOutMode = SMU7_THERM_OUT_MODE_THERM_VRHOT; |
| 3086 | } |
| 3087 | } else { |
| 3088 | phm_cap_unset(hwmgr->platform_descriptor.platformCaps, |
| 3089 | PHM_PlatformCaps_ThermalOutGPIO); |
| 3090 | |
| 3091 | table->ThermOutGpio = 17; |
| 3092 | table->ThermOutPolarity = 1; |
| 3093 | table->ThermOutMode = SMU7_THERM_OUT_MODE_DISABLE; |
| 3094 | } |
| 3095 | |
| 3096 | for (i = 0; i < SMU72_MAX_ENTRIES_SMIO; i++) { |
| 3097 | table->Smio[i] = PP_HOST_TO_SMC_UL(table->Smio[i]); |
| 3098 | } |
| 3099 | CONVERT_FROM_HOST_TO_SMC_UL(table->SystemFlags); |
| 3100 | CONVERT_FROM_HOST_TO_SMC_UL(table->VRConfig); |
| 3101 | CONVERT_FROM_HOST_TO_SMC_UL(table->SmioMask1); |
| 3102 | CONVERT_FROM_HOST_TO_SMC_UL(table->SmioMask2); |
| 3103 | CONVERT_FROM_HOST_TO_SMC_UL(table->SclkStepSize); |
| 3104 | CONVERT_FROM_HOST_TO_SMC_US(table->TemperatureLimitHigh); |
| 3105 | CONVERT_FROM_HOST_TO_SMC_US(table->TemperatureLimitLow); |
| 3106 | CONVERT_FROM_HOST_TO_SMC_US(table->VoltageResponseTime); |
| 3107 | CONVERT_FROM_HOST_TO_SMC_US(table->PhaseResponseTime); |
| 3108 | |
| 3109 | /* Upload all dpm data to SMC memory.(dpm level, dpm level count etc) */ |
| 3110 | result = tonga_copy_bytes_to_smc(hwmgr->smumgr, data->dpm_table_start + |
| 3111 | offsetof(SMU72_Discrete_DpmTable, SystemFlags), |
| 3112 | (uint8_t *)&(table->SystemFlags), |
| 3113 | sizeof(SMU72_Discrete_DpmTable)-3 * sizeof(SMU72_PIDController), |
| 3114 | data->sram_end); |
| 3115 | |
| 3116 | PP_ASSERT_WITH_CODE(0 == result, |
| 3117 | "Failed to upload dpm data to SMC memory!", return result;); |
| 3118 | |
| 3119 | return result; |
| 3120 | } |
| 3121 | |
| 3122 | /* Look up the voltaged based on DAL's requested level. and then send the requested VDDC voltage to SMC*/ |
| 3123 | static void tonga_apply_dal_minimum_voltage_request(struct pp_hwmgr *hwmgr) |
| 3124 | { |
| 3125 | return; |
| 3126 | } |
| 3127 | |
| 3128 | int tonga_upload_dpm_level_enable_mask(struct pp_hwmgr *hwmgr) |
| 3129 | { |
| 3130 | PPSMC_Result result; |
| 3131 | tonga_hwmgr *data = (tonga_hwmgr *)(hwmgr->backend); |
| 3132 | |
| 3133 | /* Apply minimum voltage based on DAL's request level */ |
| 3134 | tonga_apply_dal_minimum_voltage_request(hwmgr); |
| 3135 | |
| 3136 | if (0 == data->sclk_dpm_key_disabled) { |
| 3137 | /* Checking if DPM is running. If we discover hang because of this, we should skip this message.*/ |
Edward O'Callaghan | 4ba27f9 | 2016-07-12 10:17:56 +1000 | [diff] [blame] | 3138 | if (tonga_is_dpm_running(hwmgr)) |
yanyang1 | c82baa2 | 2015-08-18 15:28:32 +0800 | [diff] [blame] | 3139 | printk(KERN_ERR "[ powerplay ] Trying to set Enable Mask when DPM is disabled \n"); |
| 3140 | |
| 3141 | if (0 != data->dpm_level_enable_mask.sclk_dpm_enable_mask) { |
| 3142 | result = smum_send_msg_to_smc_with_parameter( |
| 3143 | hwmgr->smumgr, |
| 3144 | (PPSMC_Msg)PPSMC_MSG_SCLKDPM_SetEnabledMask, |
| 3145 | data->dpm_level_enable_mask.sclk_dpm_enable_mask); |
| 3146 | PP_ASSERT_WITH_CODE((0 == result), |
| 3147 | "Set Sclk Dpm enable Mask failed", return -1); |
| 3148 | } |
| 3149 | } |
| 3150 | |
| 3151 | if (0 == data->mclk_dpm_key_disabled) { |
| 3152 | /* Checking if DPM is running. If we discover hang because of this, we should skip this message.*/ |
Edward O'Callaghan | 4ba27f9 | 2016-07-12 10:17:56 +1000 | [diff] [blame] | 3153 | if (tonga_is_dpm_running(hwmgr)) |
yanyang1 | c82baa2 | 2015-08-18 15:28:32 +0800 | [diff] [blame] | 3154 | printk(KERN_ERR "[ powerplay ] Trying to set Enable Mask when DPM is disabled \n"); |
| 3155 | |
| 3156 | if (0 != data->dpm_level_enable_mask.mclk_dpm_enable_mask) { |
| 3157 | result = smum_send_msg_to_smc_with_parameter( |
| 3158 | hwmgr->smumgr, |
| 3159 | (PPSMC_Msg)PPSMC_MSG_MCLKDPM_SetEnabledMask, |
| 3160 | data->dpm_level_enable_mask.mclk_dpm_enable_mask); |
| 3161 | PP_ASSERT_WITH_CODE((0 == result), |
| 3162 | "Set Mclk Dpm enable Mask failed", return -1); |
| 3163 | } |
| 3164 | } |
| 3165 | |
| 3166 | return 0; |
| 3167 | } |
| 3168 | |
| 3169 | |
| 3170 | int tonga_force_dpm_highest(struct pp_hwmgr *hwmgr) |
| 3171 | { |
| 3172 | uint32_t level, tmp; |
| 3173 | tonga_hwmgr *data = (tonga_hwmgr *)(hwmgr->backend); |
| 3174 | |
| 3175 | if (0 == data->pcie_dpm_key_disabled) { |
| 3176 | /* PCIE */ |
| 3177 | if (data->dpm_level_enable_mask.pcie_dpm_enable_mask != 0) { |
| 3178 | level = 0; |
| 3179 | tmp = data->dpm_level_enable_mask.pcie_dpm_enable_mask; |
| 3180 | while (tmp >>= 1) |
| 3181 | level++ ; |
| 3182 | |
| 3183 | if (0 != level) { |
| 3184 | PP_ASSERT_WITH_CODE((0 == tonga_dpm_force_state_pcie(hwmgr, level)), |
| 3185 | "force highest pcie dpm state failed!", return -1); |
| 3186 | } |
| 3187 | } |
| 3188 | } |
| 3189 | |
| 3190 | if (0 == data->sclk_dpm_key_disabled) { |
| 3191 | /* SCLK */ |
| 3192 | if (data->dpm_level_enable_mask.sclk_dpm_enable_mask != 0) { |
| 3193 | level = 0; |
| 3194 | tmp = data->dpm_level_enable_mask.sclk_dpm_enable_mask; |
| 3195 | while (tmp >>= 1) |
| 3196 | level++ ; |
| 3197 | |
| 3198 | if (0 != level) { |
| 3199 | PP_ASSERT_WITH_CODE((0 == tonga_dpm_force_state(hwmgr, level)), |
| 3200 | "force highest sclk dpm state failed!", return -1); |
| 3201 | if (PHM_READ_VFPF_INDIRECT_FIELD(hwmgr->device, |
| 3202 | CGS_IND_REG__SMC, TARGET_AND_CURRENT_PROFILE_INDEX, CURR_SCLK_INDEX) != level) |
| 3203 | printk(KERN_ERR "[ powerplay ] Target_and_current_Profile_Index. \ |
| 3204 | Curr_Sclk_Index does not match the level \n"); |
| 3205 | |
| 3206 | } |
| 3207 | } |
| 3208 | } |
| 3209 | |
| 3210 | if (0 == data->mclk_dpm_key_disabled) { |
| 3211 | /* MCLK */ |
| 3212 | if (data->dpm_level_enable_mask.mclk_dpm_enable_mask != 0) { |
| 3213 | level = 0; |
| 3214 | tmp = data->dpm_level_enable_mask.mclk_dpm_enable_mask; |
| 3215 | while (tmp >>= 1) |
| 3216 | level++ ; |
| 3217 | |
| 3218 | if (0 != level) { |
| 3219 | PP_ASSERT_WITH_CODE((0 == tonga_dpm_force_state_mclk(hwmgr, level)), |
| 3220 | "force highest mclk dpm state failed!", return -1); |
| 3221 | if (PHM_READ_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, |
| 3222 | TARGET_AND_CURRENT_PROFILE_INDEX, CURR_MCLK_INDEX) != level) |
| 3223 | printk(KERN_ERR "[ powerplay ] Target_and_current_Profile_Index. \ |
Alex Deucher | 9fe1837 | 2015-11-11 00:23:57 -0500 | [diff] [blame] | 3224 | Curr_Mclk_Index does not match the level \n"); |
yanyang1 | c82baa2 | 2015-08-18 15:28:32 +0800 | [diff] [blame] | 3225 | } |
| 3226 | } |
| 3227 | } |
| 3228 | |
| 3229 | return 0; |
| 3230 | } |
| 3231 | |
| 3232 | /** |
| 3233 | * Find the MC microcode version and store it in the HwMgr struct |
| 3234 | * |
| 3235 | * @param hwmgr the address of the powerplay hardware manager. |
| 3236 | * @return always 0 |
| 3237 | */ |
| 3238 | int tonga_get_mc_microcode_version (struct pp_hwmgr *hwmgr) |
| 3239 | { |
| 3240 | cgs_write_register(hwmgr->device, mmMC_SEQ_IO_DEBUG_INDEX, 0x9F); |
| 3241 | |
| 3242 | hwmgr->microcode_version_info.MC = cgs_read_register(hwmgr->device, mmMC_SEQ_IO_DEBUG_DATA); |
| 3243 | |
| 3244 | return 0; |
| 3245 | } |
| 3246 | |
| 3247 | /** |
| 3248 | * Initialize Dynamic State Adjustment Rule Settings |
| 3249 | * |
| 3250 | * @param hwmgr the address of the powerplay hardware manager. |
| 3251 | */ |
| 3252 | int tonga_initializa_dynamic_state_adjustment_rule_settings(struct pp_hwmgr *hwmgr) |
| 3253 | { |
| 3254 | uint32_t table_size; |
| 3255 | struct phm_clock_voltage_dependency_table *table_clk_vlt; |
| 3256 | struct phm_ppt_v1_information *pptable_info = (struct phm_ppt_v1_information *)(hwmgr->pptable); |
| 3257 | |
| 3258 | hwmgr->dyn_state.mclk_sclk_ratio = 4; |
| 3259 | hwmgr->dyn_state.sclk_mclk_delta = 15000; /* 150 MHz */ |
| 3260 | hwmgr->dyn_state.vddc_vddci_delta = 200; /* 200mV */ |
| 3261 | |
| 3262 | /* initialize vddc_dep_on_dal_pwrl table */ |
| 3263 | table_size = sizeof(uint32_t) + 4 * sizeof(struct phm_clock_voltage_dependency_record); |
Edward O'Callaghan | 5969a8c | 2016-07-12 10:17:55 +1000 | [diff] [blame] | 3264 | table_clk_vlt = kzalloc(table_size, GFP_KERNEL); |
yanyang1 | c82baa2 | 2015-08-18 15:28:32 +0800 | [diff] [blame] | 3265 | |
| 3266 | if (NULL == table_clk_vlt) { |
| 3267 | printk(KERN_ERR "[ powerplay ] Can not allocate space for vddc_dep_on_dal_pwrl! \n"); |
| 3268 | return -ENOMEM; |
| 3269 | } else { |
| 3270 | table_clk_vlt->count = 4; |
| 3271 | table_clk_vlt->entries[0].clk = PP_DAL_POWERLEVEL_ULTRALOW; |
| 3272 | table_clk_vlt->entries[0].v = 0; |
| 3273 | table_clk_vlt->entries[1].clk = PP_DAL_POWERLEVEL_LOW; |
| 3274 | table_clk_vlt->entries[1].v = 720; |
| 3275 | table_clk_vlt->entries[2].clk = PP_DAL_POWERLEVEL_NOMINAL; |
| 3276 | table_clk_vlt->entries[2].v = 810; |
| 3277 | table_clk_vlt->entries[3].clk = PP_DAL_POWERLEVEL_PERFORMANCE; |
| 3278 | table_clk_vlt->entries[3].v = 900; |
| 3279 | pptable_info->vddc_dep_on_dal_pwrl = table_clk_vlt; |
| 3280 | hwmgr->dyn_state.vddc_dep_on_dal_pwrl = table_clk_vlt; |
| 3281 | } |
| 3282 | |
| 3283 | return 0; |
| 3284 | } |
| 3285 | |
| 3286 | static int tonga_set_private_var_based_on_pptale(struct pp_hwmgr *hwmgr) |
| 3287 | { |
| 3288 | tonga_hwmgr *data = (tonga_hwmgr *)(hwmgr->backend); |
| 3289 | struct phm_ppt_v1_information *pptable_info = (struct phm_ppt_v1_information *)(hwmgr->pptable); |
| 3290 | |
| 3291 | phm_ppt_v1_clock_voltage_dependency_table *allowed_sclk_vdd_table = |
| 3292 | pptable_info->vdd_dep_on_sclk; |
| 3293 | phm_ppt_v1_clock_voltage_dependency_table *allowed_mclk_vdd_table = |
| 3294 | pptable_info->vdd_dep_on_mclk; |
| 3295 | |
| 3296 | PP_ASSERT_WITH_CODE(allowed_sclk_vdd_table != NULL, |
Christian König | edf600d | 2016-05-03 15:54:54 +0200 | [diff] [blame] | 3297 | "VDD dependency on SCLK table is missing. \ |
yanyang1 | c82baa2 | 2015-08-18 15:28:32 +0800 | [diff] [blame] | 3298 | This table is mandatory", return -1); |
| 3299 | PP_ASSERT_WITH_CODE(allowed_sclk_vdd_table->count >= 1, |
Christian König | edf600d | 2016-05-03 15:54:54 +0200 | [diff] [blame] | 3300 | "VDD dependency on SCLK table has to have is missing. \ |
yanyang1 | c82baa2 | 2015-08-18 15:28:32 +0800 | [diff] [blame] | 3301 | This table is mandatory", return -1); |
| 3302 | |
| 3303 | PP_ASSERT_WITH_CODE(allowed_mclk_vdd_table != NULL, |
Christian König | edf600d | 2016-05-03 15:54:54 +0200 | [diff] [blame] | 3304 | "VDD dependency on MCLK table is missing. \ |
yanyang1 | c82baa2 | 2015-08-18 15:28:32 +0800 | [diff] [blame] | 3305 | This table is mandatory", return -1); |
| 3306 | PP_ASSERT_WITH_CODE(allowed_mclk_vdd_table->count >= 1, |
| 3307 | "VDD dependency on MCLK table has to have is missing. \ |
| 3308 | This table is mandatory", return -1); |
| 3309 | |
| 3310 | data->min_vddc_in_pp_table = (uint16_t)allowed_sclk_vdd_table->entries[0].vddc; |
| 3311 | data->max_vddc_in_pp_table = (uint16_t)allowed_sclk_vdd_table->entries[allowed_sclk_vdd_table->count - 1].vddc; |
| 3312 | |
| 3313 | pptable_info->max_clock_voltage_on_ac.sclk = |
| 3314 | allowed_sclk_vdd_table->entries[allowed_sclk_vdd_table->count - 1].clk; |
| 3315 | pptable_info->max_clock_voltage_on_ac.mclk = |
| 3316 | allowed_mclk_vdd_table->entries[allowed_mclk_vdd_table->count - 1].clk; |
| 3317 | pptable_info->max_clock_voltage_on_ac.vddc = |
| 3318 | allowed_sclk_vdd_table->entries[allowed_sclk_vdd_table->count - 1].vddc; |
| 3319 | pptable_info->max_clock_voltage_on_ac.vddci = |
| 3320 | allowed_mclk_vdd_table->entries[allowed_mclk_vdd_table->count - 1].vddci; |
| 3321 | |
| 3322 | hwmgr->dyn_state.max_clock_voltage_on_ac.sclk = |
| 3323 | pptable_info->max_clock_voltage_on_ac.sclk; |
| 3324 | hwmgr->dyn_state.max_clock_voltage_on_ac.mclk = |
| 3325 | pptable_info->max_clock_voltage_on_ac.mclk; |
| 3326 | hwmgr->dyn_state.max_clock_voltage_on_ac.vddc = |
| 3327 | pptable_info->max_clock_voltage_on_ac.vddc; |
| 3328 | hwmgr->dyn_state.max_clock_voltage_on_ac.vddci = |
| 3329 | pptable_info->max_clock_voltage_on_ac.vddci; |
| 3330 | |
| 3331 | return 0; |
| 3332 | } |
| 3333 | |
| 3334 | int tonga_unforce_dpm_levels(struct pp_hwmgr *hwmgr) |
| 3335 | { |
| 3336 | tonga_hwmgr *data = (tonga_hwmgr *)(hwmgr->backend); |
| 3337 | int result = 1; |
| 3338 | |
Edward O'Callaghan | 4ba27f9 | 2016-07-12 10:17:56 +1000 | [diff] [blame] | 3339 | PP_ASSERT_WITH_CODE (!tonga_is_dpm_running(hwmgr), |
| 3340 | "Trying to Unforce DPM when DPM is disabled. Returning without sending SMC message.", |
| 3341 | return result); |
yanyang1 | c82baa2 | 2015-08-18 15:28:32 +0800 | [diff] [blame] | 3342 | |
| 3343 | if (0 == data->pcie_dpm_key_disabled) { |
| 3344 | PP_ASSERT_WITH_CODE((0 == smum_send_msg_to_smc( |
| 3345 | hwmgr->smumgr, |
| 3346 | PPSMC_MSG_PCIeDPM_UnForceLevel)), |
| 3347 | "unforce pcie level failed!", |
| 3348 | return -1); |
| 3349 | } |
| 3350 | |
| 3351 | result = tonga_upload_dpm_level_enable_mask(hwmgr); |
| 3352 | |
| 3353 | return result; |
| 3354 | } |
| 3355 | |
| 3356 | static uint32_t tonga_get_lowest_enable_level( |
| 3357 | struct pp_hwmgr *hwmgr, uint32_t level_mask) |
| 3358 | { |
| 3359 | uint32_t level = 0; |
| 3360 | |
| 3361 | while (0 == (level_mask & (1 << level))) |
| 3362 | level++; |
| 3363 | |
| 3364 | return level; |
| 3365 | } |
| 3366 | |
| 3367 | static int tonga_force_dpm_lowest(struct pp_hwmgr *hwmgr) |
| 3368 | { |
Alex Deucher | 9fe1837 | 2015-11-11 00:23:57 -0500 | [diff] [blame] | 3369 | uint32_t level; |
yanyang1 | c82baa2 | 2015-08-18 15:28:32 +0800 | [diff] [blame] | 3370 | tonga_hwmgr *data = (tonga_hwmgr *)(hwmgr->backend); |
| 3371 | |
Alex Deucher | 9fe1837 | 2015-11-11 00:23:57 -0500 | [diff] [blame] | 3372 | if (0 == data->pcie_dpm_key_disabled) { |
| 3373 | /* PCIE */ |
| 3374 | if (data->dpm_level_enable_mask.pcie_dpm_enable_mask != 0) { |
| 3375 | level = tonga_get_lowest_enable_level(hwmgr, |
| 3376 | data->dpm_level_enable_mask.pcie_dpm_enable_mask); |
| 3377 | PP_ASSERT_WITH_CODE((0 == tonga_dpm_force_state_pcie(hwmgr, level)), |
| 3378 | "force lowest pcie dpm state failed!", return -1); |
| 3379 | } |
| 3380 | } |
yanyang1 | c82baa2 | 2015-08-18 15:28:32 +0800 | [diff] [blame] | 3381 | |
Alex Deucher | 9fe1837 | 2015-11-11 00:23:57 -0500 | [diff] [blame] | 3382 | if (0 == data->sclk_dpm_key_disabled) { |
| 3383 | /* SCLK */ |
| 3384 | if (0 != data->dpm_level_enable_mask.sclk_dpm_enable_mask) { |
| 3385 | level = tonga_get_lowest_enable_level(hwmgr, |
| 3386 | data->dpm_level_enable_mask.sclk_dpm_enable_mask); |
yanyang1 | c82baa2 | 2015-08-18 15:28:32 +0800 | [diff] [blame] | 3387 | |
Alex Deucher | 9fe1837 | 2015-11-11 00:23:57 -0500 | [diff] [blame] | 3388 | PP_ASSERT_WITH_CODE((0 == tonga_dpm_force_state(hwmgr, level)), |
| 3389 | "force sclk dpm state failed!", return -1); |
| 3390 | |
| 3391 | if (PHM_READ_VFPF_INDIRECT_FIELD(hwmgr->device, |
| 3392 | CGS_IND_REG__SMC, TARGET_AND_CURRENT_PROFILE_INDEX, CURR_SCLK_INDEX) != level) |
| 3393 | printk(KERN_ERR "[ powerplay ] Target_and_current_Profile_Index. \ |
yanyang1 | c82baa2 | 2015-08-18 15:28:32 +0800 | [diff] [blame] | 3394 | Curr_Sclk_Index does not match the level \n"); |
Alex Deucher | 9fe1837 | 2015-11-11 00:23:57 -0500 | [diff] [blame] | 3395 | } |
| 3396 | } |
| 3397 | |
| 3398 | if (0 == data->mclk_dpm_key_disabled) { |
| 3399 | /* MCLK */ |
| 3400 | if (data->dpm_level_enable_mask.mclk_dpm_enable_mask != 0) { |
| 3401 | level = tonga_get_lowest_enable_level(hwmgr, |
| 3402 | data->dpm_level_enable_mask.mclk_dpm_enable_mask); |
| 3403 | PP_ASSERT_WITH_CODE((0 == tonga_dpm_force_state_mclk(hwmgr, level)), |
| 3404 | "force lowest mclk dpm state failed!", return -1); |
| 3405 | if (PHM_READ_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, |
| 3406 | TARGET_AND_CURRENT_PROFILE_INDEX, CURR_MCLK_INDEX) != level) |
| 3407 | printk(KERN_ERR "[ powerplay ] Target_and_current_Profile_Index. \ |
| 3408 | Curr_Mclk_Index does not match the level \n"); |
| 3409 | } |
yanyang1 | c82baa2 | 2015-08-18 15:28:32 +0800 | [diff] [blame] | 3410 | } |
| 3411 | |
| 3412 | return 0; |
| 3413 | } |
| 3414 | |
| 3415 | static int tonga_patch_voltage_dependency_tables_with_lookup_table(struct pp_hwmgr *hwmgr) |
| 3416 | { |
| 3417 | uint8_t entryId; |
| 3418 | uint8_t voltageId; |
| 3419 | tonga_hwmgr *data = (tonga_hwmgr *)(hwmgr->backend); |
| 3420 | struct phm_ppt_v1_information *pptable_info = (struct phm_ppt_v1_information *)(hwmgr->pptable); |
| 3421 | |
| 3422 | phm_ppt_v1_clock_voltage_dependency_table *sclk_table = pptable_info->vdd_dep_on_sclk; |
| 3423 | phm_ppt_v1_clock_voltage_dependency_table *mclk_table = pptable_info->vdd_dep_on_mclk; |
| 3424 | phm_ppt_v1_mm_clock_voltage_dependency_table *mm_table = pptable_info->mm_dep_table; |
| 3425 | |
| 3426 | if (data->vdd_gfx_control == TONGA_VOLTAGE_CONTROL_BY_SVID2) { |
| 3427 | for (entryId = 0; entryId < sclk_table->count; ++entryId) { |
| 3428 | voltageId = sclk_table->entries[entryId].vddInd; |
| 3429 | sclk_table->entries[entryId].vddgfx = |
| 3430 | pptable_info->vddgfx_lookup_table->entries[voltageId].us_vdd; |
| 3431 | } |
| 3432 | } else { |
| 3433 | for (entryId = 0; entryId < sclk_table->count; ++entryId) { |
| 3434 | voltageId = sclk_table->entries[entryId].vddInd; |
| 3435 | sclk_table->entries[entryId].vddc = |
| 3436 | pptable_info->vddc_lookup_table->entries[voltageId].us_vdd; |
| 3437 | } |
| 3438 | } |
| 3439 | |
| 3440 | for (entryId = 0; entryId < mclk_table->count; ++entryId) { |
| 3441 | voltageId = mclk_table->entries[entryId].vddInd; |
| 3442 | mclk_table->entries[entryId].vddc = |
| 3443 | pptable_info->vddc_lookup_table->entries[voltageId].us_vdd; |
| 3444 | } |
| 3445 | |
| 3446 | for (entryId = 0; entryId < mm_table->count; ++entryId) { |
| 3447 | voltageId = mm_table->entries[entryId].vddcInd; |
| 3448 | mm_table->entries[entryId].vddc = |
| 3449 | pptable_info->vddc_lookup_table->entries[voltageId].us_vdd; |
| 3450 | } |
| 3451 | |
| 3452 | return 0; |
| 3453 | |
| 3454 | } |
| 3455 | |
| 3456 | static int tonga_calc_voltage_dependency_tables(struct pp_hwmgr *hwmgr) |
| 3457 | { |
| 3458 | uint8_t entryId; |
| 3459 | phm_ppt_v1_voltage_lookup_record v_record; |
| 3460 | tonga_hwmgr *data = (tonga_hwmgr *)(hwmgr->backend); |
| 3461 | struct phm_ppt_v1_information *pptable_info = (struct phm_ppt_v1_information *)(hwmgr->pptable); |
| 3462 | |
| 3463 | phm_ppt_v1_clock_voltage_dependency_table *sclk_table = pptable_info->vdd_dep_on_sclk; |
| 3464 | phm_ppt_v1_clock_voltage_dependency_table *mclk_table = pptable_info->vdd_dep_on_mclk; |
| 3465 | |
| 3466 | if (data->vdd_gfx_control == TONGA_VOLTAGE_CONTROL_BY_SVID2) { |
| 3467 | for (entryId = 0; entryId < sclk_table->count; ++entryId) { |
| 3468 | if (sclk_table->entries[entryId].vdd_offset & (1 << 15)) |
| 3469 | v_record.us_vdd = sclk_table->entries[entryId].vddgfx + |
| 3470 | sclk_table->entries[entryId].vdd_offset - 0xFFFF; |
| 3471 | else |
| 3472 | v_record.us_vdd = sclk_table->entries[entryId].vddgfx + |
| 3473 | sclk_table->entries[entryId].vdd_offset; |
| 3474 | |
| 3475 | sclk_table->entries[entryId].vddc = |
| 3476 | v_record.us_cac_low = v_record.us_cac_mid = |
| 3477 | v_record.us_cac_high = v_record.us_vdd; |
| 3478 | |
| 3479 | tonga_add_voltage(hwmgr, pptable_info->vddc_lookup_table, &v_record); |
| 3480 | } |
| 3481 | |
| 3482 | for (entryId = 0; entryId < mclk_table->count; ++entryId) { |
| 3483 | if (mclk_table->entries[entryId].vdd_offset & (1 << 15)) |
| 3484 | v_record.us_vdd = mclk_table->entries[entryId].vddc + |
| 3485 | mclk_table->entries[entryId].vdd_offset - 0xFFFF; |
| 3486 | else |
| 3487 | v_record.us_vdd = mclk_table->entries[entryId].vddc + |
| 3488 | mclk_table->entries[entryId].vdd_offset; |
| 3489 | |
| 3490 | mclk_table->entries[entryId].vddgfx = v_record.us_cac_low = |
| 3491 | v_record.us_cac_mid = v_record.us_cac_high = v_record.us_vdd; |
| 3492 | tonga_add_voltage(hwmgr, pptable_info->vddgfx_lookup_table, &v_record); |
| 3493 | } |
| 3494 | } |
| 3495 | |
| 3496 | return 0; |
| 3497 | |
| 3498 | } |
| 3499 | |
| 3500 | static int tonga_calc_mm_voltage_dependency_table(struct pp_hwmgr *hwmgr) |
| 3501 | { |
| 3502 | uint32_t entryId; |
| 3503 | phm_ppt_v1_voltage_lookup_record v_record; |
| 3504 | tonga_hwmgr *data = (tonga_hwmgr *)(hwmgr->backend); |
| 3505 | struct phm_ppt_v1_information *pptable_info = (struct phm_ppt_v1_information *)(hwmgr->pptable); |
| 3506 | phm_ppt_v1_mm_clock_voltage_dependency_table *mm_table = pptable_info->mm_dep_table; |
| 3507 | |
| 3508 | if (data->vdd_gfx_control == TONGA_VOLTAGE_CONTROL_BY_SVID2) { |
| 3509 | for (entryId = 0; entryId < mm_table->count; entryId++) { |
| 3510 | if (mm_table->entries[entryId].vddgfx_offset & (1 << 15)) |
| 3511 | v_record.us_vdd = mm_table->entries[entryId].vddc + |
| 3512 | mm_table->entries[entryId].vddgfx_offset - 0xFFFF; |
| 3513 | else |
| 3514 | v_record.us_vdd = mm_table->entries[entryId].vddc + |
| 3515 | mm_table->entries[entryId].vddgfx_offset; |
| 3516 | |
| 3517 | /* Add the calculated VDDGFX to the VDDGFX lookup table */ |
| 3518 | mm_table->entries[entryId].vddgfx = v_record.us_cac_low = |
| 3519 | v_record.us_cac_mid = v_record.us_cac_high = v_record.us_vdd; |
| 3520 | tonga_add_voltage(hwmgr, pptable_info->vddgfx_lookup_table, &v_record); |
| 3521 | } |
| 3522 | } |
| 3523 | return 0; |
| 3524 | } |
| 3525 | |
| 3526 | |
| 3527 | /** |
| 3528 | * Change virtual leakage voltage to actual value. |
| 3529 | * |
| 3530 | * @param hwmgr the address of the powerplay hardware manager. |
| 3531 | * @param pointer to changing voltage |
| 3532 | * @param pointer to leakage table |
| 3533 | */ |
| 3534 | static void tonga_patch_with_vdd_leakage(struct pp_hwmgr *hwmgr, |
| 3535 | uint16_t *voltage, phw_tonga_leakage_voltage *pLeakageTable) |
| 3536 | { |
| 3537 | uint32_t leakage_index; |
| 3538 | |
| 3539 | /* search for leakage voltage ID 0xff01 ~ 0xff08 */ |
| 3540 | for (leakage_index = 0; leakage_index < pLeakageTable->count; leakage_index++) { |
| 3541 | /* if this voltage matches a leakage voltage ID */ |
| 3542 | /* patch with actual leakage voltage */ |
| 3543 | if (pLeakageTable->leakage_id[leakage_index] == *voltage) { |
| 3544 | *voltage = pLeakageTable->actual_voltage[leakage_index]; |
| 3545 | break; |
| 3546 | } |
| 3547 | } |
| 3548 | |
| 3549 | if (*voltage > ATOM_VIRTUAL_VOLTAGE_ID0) |
| 3550 | printk(KERN_ERR "[ powerplay ] Voltage value looks like a Leakage ID but it's not patched \n"); |
| 3551 | } |
| 3552 | |
| 3553 | /** |
| 3554 | * Patch voltage lookup table by EVV leakages. |
| 3555 | * |
| 3556 | * @param hwmgr the address of the powerplay hardware manager. |
| 3557 | * @param pointer to voltage lookup table |
| 3558 | * @param pointer to leakage table |
| 3559 | * @return always 0 |
| 3560 | */ |
| 3561 | static int tonga_patch_lookup_table_with_leakage(struct pp_hwmgr *hwmgr, |
| 3562 | phm_ppt_v1_voltage_lookup_table *lookup_table, |
| 3563 | phw_tonga_leakage_voltage *pLeakageTable) |
| 3564 | { |
| 3565 | uint32_t i; |
| 3566 | |
| 3567 | for (i = 0; i < lookup_table->count; i++) { |
| 3568 | tonga_patch_with_vdd_leakage(hwmgr, |
| 3569 | &lookup_table->entries[i].us_vdd, pLeakageTable); |
| 3570 | } |
| 3571 | |
| 3572 | return 0; |
| 3573 | } |
| 3574 | |
| 3575 | static int tonga_patch_clock_voltage_lomits_with_vddc_leakage(struct pp_hwmgr *hwmgr, |
| 3576 | phw_tonga_leakage_voltage *pLeakageTable, uint16_t *Vddc) |
| 3577 | { |
| 3578 | struct phm_ppt_v1_information *pptable_info = (struct phm_ppt_v1_information *)(hwmgr->pptable); |
| 3579 | |
| 3580 | tonga_patch_with_vdd_leakage(hwmgr, (uint16_t *)Vddc, pLeakageTable); |
| 3581 | hwmgr->dyn_state.max_clock_voltage_on_dc.vddc = |
| 3582 | pptable_info->max_clock_voltage_on_dc.vddc; |
| 3583 | |
| 3584 | return 0; |
| 3585 | } |
| 3586 | |
| 3587 | static int tonga_patch_clock_voltage_limits_with_vddgfx_leakage( |
| 3588 | struct pp_hwmgr *hwmgr, phw_tonga_leakage_voltage *pLeakageTable, |
| 3589 | uint16_t *Vddgfx) |
| 3590 | { |
| 3591 | tonga_patch_with_vdd_leakage(hwmgr, (uint16_t *)Vddgfx, pLeakageTable); |
| 3592 | return 0; |
| 3593 | } |
| 3594 | |
| 3595 | int tonga_sort_lookup_table(struct pp_hwmgr *hwmgr, |
| 3596 | phm_ppt_v1_voltage_lookup_table *lookup_table) |
| 3597 | { |
| 3598 | uint32_t table_size, i, j; |
| 3599 | phm_ppt_v1_voltage_lookup_record tmp_voltage_lookup_record; |
| 3600 | table_size = lookup_table->count; |
| 3601 | |
| 3602 | PP_ASSERT_WITH_CODE(0 != lookup_table->count, |
| 3603 | "Lookup table is empty", return -1); |
| 3604 | |
| 3605 | /* Sorting voltages */ |
| 3606 | for (i = 0; i < table_size - 1; i++) { |
| 3607 | for (j = i + 1; j > 0; j--) { |
| 3608 | if (lookup_table->entries[j].us_vdd < lookup_table->entries[j-1].us_vdd) { |
| 3609 | tmp_voltage_lookup_record = lookup_table->entries[j-1]; |
| 3610 | lookup_table->entries[j-1] = lookup_table->entries[j]; |
| 3611 | lookup_table->entries[j] = tmp_voltage_lookup_record; |
| 3612 | } |
| 3613 | } |
| 3614 | } |
| 3615 | |
| 3616 | return 0; |
| 3617 | } |
| 3618 | |
| 3619 | static int tonga_complete_dependency_tables(struct pp_hwmgr *hwmgr) |
| 3620 | { |
| 3621 | int result = 0; |
| 3622 | int tmp_result; |
| 3623 | tonga_hwmgr *data = (struct tonga_hwmgr *)(hwmgr->backend); |
| 3624 | struct phm_ppt_v1_information *pptable_info = (struct phm_ppt_v1_information *)(hwmgr->pptable); |
| 3625 | |
| 3626 | if (data->vdd_gfx_control == TONGA_VOLTAGE_CONTROL_BY_SVID2) { |
| 3627 | tmp_result = tonga_patch_lookup_table_with_leakage(hwmgr, |
| 3628 | pptable_info->vddgfx_lookup_table, &(data->vddcgfx_leakage)); |
| 3629 | if (tmp_result != 0) |
| 3630 | result = tmp_result; |
| 3631 | |
| 3632 | tmp_result = tonga_patch_clock_voltage_limits_with_vddgfx_leakage(hwmgr, |
| 3633 | &(data->vddcgfx_leakage), &pptable_info->max_clock_voltage_on_dc.vddgfx); |
| 3634 | if (tmp_result != 0) |
| 3635 | result = tmp_result; |
| 3636 | } else { |
| 3637 | tmp_result = tonga_patch_lookup_table_with_leakage(hwmgr, |
| 3638 | pptable_info->vddc_lookup_table, &(data->vddc_leakage)); |
| 3639 | if (tmp_result != 0) |
| 3640 | result = tmp_result; |
| 3641 | |
| 3642 | tmp_result = tonga_patch_clock_voltage_lomits_with_vddc_leakage(hwmgr, |
| 3643 | &(data->vddc_leakage), &pptable_info->max_clock_voltage_on_dc.vddc); |
| 3644 | if (tmp_result != 0) |
| 3645 | result = tmp_result; |
| 3646 | } |
| 3647 | |
| 3648 | tmp_result = tonga_patch_voltage_dependency_tables_with_lookup_table(hwmgr); |
| 3649 | if (tmp_result != 0) |
| 3650 | result = tmp_result; |
| 3651 | |
| 3652 | tmp_result = tonga_calc_voltage_dependency_tables(hwmgr); |
| 3653 | if (tmp_result != 0) |
| 3654 | result = tmp_result; |
| 3655 | |
| 3656 | tmp_result = tonga_calc_mm_voltage_dependency_table(hwmgr); |
| 3657 | if (tmp_result != 0) |
| 3658 | result = tmp_result; |
| 3659 | |
| 3660 | tmp_result = tonga_sort_lookup_table(hwmgr, pptable_info->vddgfx_lookup_table); |
| 3661 | if (tmp_result != 0) |
| 3662 | result = tmp_result; |
| 3663 | |
| 3664 | tmp_result = tonga_sort_lookup_table(hwmgr, pptable_info->vddc_lookup_table); |
| 3665 | if (tmp_result != 0) |
| 3666 | result = tmp_result; |
| 3667 | |
| 3668 | return result; |
| 3669 | } |
| 3670 | |
| 3671 | int tonga_init_sclk_threshold(struct pp_hwmgr *hwmgr) |
| 3672 | { |
| 3673 | tonga_hwmgr *data = (tonga_hwmgr *)(hwmgr->backend); |
| 3674 | data->low_sclk_interrupt_threshold = 0; |
| 3675 | |
| 3676 | return 0; |
| 3677 | } |
| 3678 | |
| 3679 | int tonga_setup_asic_task(struct pp_hwmgr *hwmgr) |
| 3680 | { |
| 3681 | int tmp_result, result = 0; |
| 3682 | |
| 3683 | tmp_result = tonga_read_clock_registers(hwmgr); |
| 3684 | PP_ASSERT_WITH_CODE((0 == tmp_result), |
| 3685 | "Failed to read clock registers!", result = tmp_result); |
| 3686 | |
| 3687 | tmp_result = tonga_get_memory_type(hwmgr); |
| 3688 | PP_ASSERT_WITH_CODE((0 == tmp_result), |
| 3689 | "Failed to get memory type!", result = tmp_result); |
| 3690 | |
| 3691 | tmp_result = tonga_enable_acpi_power_management(hwmgr); |
| 3692 | PP_ASSERT_WITH_CODE((0 == tmp_result), |
| 3693 | "Failed to enable ACPI power management!", result = tmp_result); |
| 3694 | |
| 3695 | tmp_result = tonga_init_power_gate_state(hwmgr); |
| 3696 | PP_ASSERT_WITH_CODE((0 == tmp_result), |
| 3697 | "Failed to init power gate state!", result = tmp_result); |
| 3698 | |
| 3699 | tmp_result = tonga_get_mc_microcode_version(hwmgr); |
| 3700 | PP_ASSERT_WITH_CODE((0 == tmp_result), |
| 3701 | "Failed to get MC microcode version!", result = tmp_result); |
| 3702 | |
| 3703 | tmp_result = tonga_init_sclk_threshold(hwmgr); |
| 3704 | PP_ASSERT_WITH_CODE((0 == tmp_result), |
| 3705 | "Failed to init sclk threshold!", result = tmp_result); |
| 3706 | |
| 3707 | return result; |
| 3708 | } |
| 3709 | |
| 3710 | /** |
| 3711 | * Enable voltage control |
| 3712 | * |
| 3713 | * @param hwmgr the address of the powerplay hardware manager. |
| 3714 | * @return always 0 |
| 3715 | */ |
| 3716 | int tonga_enable_voltage_control(struct pp_hwmgr *hwmgr) |
| 3717 | { |
| 3718 | /* enable voltage control */ |
| 3719 | PHM_WRITE_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, GENERAL_PWRMGT, VOLT_PWRMGT_EN, 1); |
| 3720 | |
| 3721 | return 0; |
| 3722 | } |
| 3723 | |
| 3724 | /** |
| 3725 | * Checks if we want to support voltage control |
| 3726 | * |
| 3727 | * @param hwmgr the address of the powerplay hardware manager. |
| 3728 | */ |
| 3729 | bool cf_tonga_voltage_control(const struct pp_hwmgr *hwmgr) |
| 3730 | { |
| 3731 | const struct tonga_hwmgr *data = (struct tonga_hwmgr *)(hwmgr->backend); |
| 3732 | |
| 3733 | return(TONGA_VOLTAGE_CONTROL_NONE != data->voltage_control); |
| 3734 | } |
| 3735 | |
| 3736 | /*---------------------------MC----------------------------*/ |
| 3737 | |
| 3738 | uint8_t tonga_get_memory_modile_index(struct pp_hwmgr *hwmgr) |
| 3739 | { |
| 3740 | return (uint8_t) (0xFF & (cgs_read_register(hwmgr->device, mmBIOS_SCRATCH_4) >> 16)); |
| 3741 | } |
| 3742 | |
| 3743 | bool tonga_check_s0_mc_reg_index(uint16_t inReg, uint16_t *outReg) |
| 3744 | { |
Edward O'Callaghan | ed5121a | 2016-07-12 10:17:52 +1000 | [diff] [blame] | 3745 | bool result = true; |
yanyang1 | c82baa2 | 2015-08-18 15:28:32 +0800 | [diff] [blame] | 3746 | |
| 3747 | switch (inReg) { |
| 3748 | case mmMC_SEQ_RAS_TIMING: |
| 3749 | *outReg = mmMC_SEQ_RAS_TIMING_LP; |
| 3750 | break; |
| 3751 | |
| 3752 | case mmMC_SEQ_DLL_STBY: |
| 3753 | *outReg = mmMC_SEQ_DLL_STBY_LP; |
| 3754 | break; |
| 3755 | |
| 3756 | case mmMC_SEQ_G5PDX_CMD0: |
| 3757 | *outReg = mmMC_SEQ_G5PDX_CMD0_LP; |
| 3758 | break; |
| 3759 | |
| 3760 | case mmMC_SEQ_G5PDX_CMD1: |
| 3761 | *outReg = mmMC_SEQ_G5PDX_CMD1_LP; |
| 3762 | break; |
| 3763 | |
| 3764 | case mmMC_SEQ_G5PDX_CTRL: |
| 3765 | *outReg = mmMC_SEQ_G5PDX_CTRL_LP; |
| 3766 | break; |
| 3767 | |
| 3768 | case mmMC_SEQ_CAS_TIMING: |
| 3769 | *outReg = mmMC_SEQ_CAS_TIMING_LP; |
| 3770 | break; |
| 3771 | |
| 3772 | case mmMC_SEQ_MISC_TIMING: |
| 3773 | *outReg = mmMC_SEQ_MISC_TIMING_LP; |
| 3774 | break; |
| 3775 | |
| 3776 | case mmMC_SEQ_MISC_TIMING2: |
| 3777 | *outReg = mmMC_SEQ_MISC_TIMING2_LP; |
| 3778 | break; |
| 3779 | |
| 3780 | case mmMC_SEQ_PMG_DVS_CMD: |
| 3781 | *outReg = mmMC_SEQ_PMG_DVS_CMD_LP; |
| 3782 | break; |
| 3783 | |
| 3784 | case mmMC_SEQ_PMG_DVS_CTL: |
| 3785 | *outReg = mmMC_SEQ_PMG_DVS_CTL_LP; |
| 3786 | break; |
| 3787 | |
| 3788 | case mmMC_SEQ_RD_CTL_D0: |
| 3789 | *outReg = mmMC_SEQ_RD_CTL_D0_LP; |
| 3790 | break; |
| 3791 | |
| 3792 | case mmMC_SEQ_RD_CTL_D1: |
| 3793 | *outReg = mmMC_SEQ_RD_CTL_D1_LP; |
| 3794 | break; |
| 3795 | |
| 3796 | case mmMC_SEQ_WR_CTL_D0: |
| 3797 | *outReg = mmMC_SEQ_WR_CTL_D0_LP; |
| 3798 | break; |
| 3799 | |
| 3800 | case mmMC_SEQ_WR_CTL_D1: |
| 3801 | *outReg = mmMC_SEQ_WR_CTL_D1_LP; |
| 3802 | break; |
| 3803 | |
| 3804 | case mmMC_PMG_CMD_EMRS: |
| 3805 | *outReg = mmMC_SEQ_PMG_CMD_EMRS_LP; |
| 3806 | break; |
| 3807 | |
| 3808 | case mmMC_PMG_CMD_MRS: |
| 3809 | *outReg = mmMC_SEQ_PMG_CMD_MRS_LP; |
| 3810 | break; |
| 3811 | |
| 3812 | case mmMC_PMG_CMD_MRS1: |
| 3813 | *outReg = mmMC_SEQ_PMG_CMD_MRS1_LP; |
| 3814 | break; |
| 3815 | |
| 3816 | case mmMC_SEQ_PMG_TIMING: |
| 3817 | *outReg = mmMC_SEQ_PMG_TIMING_LP; |
| 3818 | break; |
| 3819 | |
| 3820 | case mmMC_PMG_CMD_MRS2: |
| 3821 | *outReg = mmMC_SEQ_PMG_CMD_MRS2_LP; |
| 3822 | break; |
| 3823 | |
| 3824 | case mmMC_SEQ_WR_CTL_2: |
| 3825 | *outReg = mmMC_SEQ_WR_CTL_2_LP; |
| 3826 | break; |
| 3827 | |
| 3828 | default: |
Edward O'Callaghan | ed5121a | 2016-07-12 10:17:52 +1000 | [diff] [blame] | 3829 | result = false; |
yanyang1 | c82baa2 | 2015-08-18 15:28:32 +0800 | [diff] [blame] | 3830 | break; |
| 3831 | } |
| 3832 | |
| 3833 | return result; |
| 3834 | } |
| 3835 | |
| 3836 | int tonga_set_s0_mc_reg_index(phw_tonga_mc_reg_table *table) |
| 3837 | { |
| 3838 | uint32_t i; |
| 3839 | uint16_t address; |
| 3840 | |
| 3841 | for (i = 0; i < table->last; i++) { |
| 3842 | table->mc_reg_address[i].s0 = |
| 3843 | tonga_check_s0_mc_reg_index(table->mc_reg_address[i].s1, &address) |
| 3844 | ? address : table->mc_reg_address[i].s1; |
| 3845 | } |
| 3846 | return 0; |
| 3847 | } |
| 3848 | |
| 3849 | int tonga_copy_vbios_smc_reg_table(const pp_atomctrl_mc_reg_table *table, phw_tonga_mc_reg_table *ni_table) |
| 3850 | { |
| 3851 | uint8_t i, j; |
| 3852 | |
| 3853 | PP_ASSERT_WITH_CODE((table->last <= SMU72_DISCRETE_MC_REGISTER_ARRAY_SIZE), |
| 3854 | "Invalid VramInfo table.", return -1); |
| 3855 | PP_ASSERT_WITH_CODE((table->num_entries <= MAX_AC_TIMING_ENTRIES), |
| 3856 | "Invalid VramInfo table.", return -1); |
| 3857 | |
| 3858 | for (i = 0; i < table->last; i++) { |
| 3859 | ni_table->mc_reg_address[i].s1 = table->mc_reg_address[i].s1; |
| 3860 | } |
| 3861 | ni_table->last = table->last; |
| 3862 | |
| 3863 | for (i = 0; i < table->num_entries; i++) { |
| 3864 | ni_table->mc_reg_table_entry[i].mclk_max = |
| 3865 | table->mc_reg_table_entry[i].mclk_max; |
| 3866 | for (j = 0; j < table->last; j++) { |
| 3867 | ni_table->mc_reg_table_entry[i].mc_data[j] = |
| 3868 | table->mc_reg_table_entry[i].mc_data[j]; |
| 3869 | } |
| 3870 | } |
Rex Zhu | c15c8d7 | 2016-01-06 16:48:38 +0800 | [diff] [blame] | 3871 | |
yanyang1 | c82baa2 | 2015-08-18 15:28:32 +0800 | [diff] [blame] | 3872 | ni_table->num_entries = table->num_entries; |
| 3873 | |
| 3874 | return 0; |
| 3875 | } |
| 3876 | |
| 3877 | /** |
| 3878 | * VBIOS omits some information to reduce size, we need to recover them here. |
| 3879 | * 1. when we see mmMC_SEQ_MISC1, bit[31:16] EMRS1, need to be write to mmMC_PMG_CMD_EMRS /_LP[15:0]. |
| 3880 | * Bit[15:0] MRS, need to be update mmMC_PMG_CMD_MRS/_LP[15:0] |
| 3881 | * 2. when we see mmMC_SEQ_RESERVE_M, bit[15:0] EMRS2, need to be write to mmMC_PMG_CMD_MRS1/_LP[15:0]. |
| 3882 | * 3. need to set these data for each clock range |
| 3883 | * |
| 3884 | * @param hwmgr the address of the powerplay hardware manager. |
| 3885 | * @param table the address of MCRegTable |
| 3886 | * @return always 0 |
| 3887 | */ |
| 3888 | int tonga_set_mc_special_registers(struct pp_hwmgr *hwmgr, phw_tonga_mc_reg_table *table) |
| 3889 | { |
| 3890 | uint8_t i, j, k; |
| 3891 | uint32_t temp_reg; |
| 3892 | const tonga_hwmgr *data = (struct tonga_hwmgr *)(hwmgr->backend); |
| 3893 | |
| 3894 | for (i = 0, j = table->last; i < table->last; i++) { |
| 3895 | PP_ASSERT_WITH_CODE((j < SMU72_DISCRETE_MC_REGISTER_ARRAY_SIZE), |
| 3896 | "Invalid VramInfo table.", return -1); |
| 3897 | switch (table->mc_reg_address[i].s1) { |
| 3898 | /* |
| 3899 | * mmMC_SEQ_MISC1, bit[31:16] EMRS1, need to be write to mmMC_PMG_CMD_EMRS /_LP[15:0]. |
| 3900 | * Bit[15:0] MRS, need to be update mmMC_PMG_CMD_MRS/_LP[15:0] |
| 3901 | */ |
| 3902 | case mmMC_SEQ_MISC1: |
| 3903 | temp_reg = cgs_read_register(hwmgr->device, mmMC_PMG_CMD_EMRS); |
| 3904 | table->mc_reg_address[j].s1 = mmMC_PMG_CMD_EMRS; |
| 3905 | table->mc_reg_address[j].s0 = mmMC_SEQ_PMG_CMD_EMRS_LP; |
| 3906 | for (k = 0; k < table->num_entries; k++) { |
| 3907 | table->mc_reg_table_entry[k].mc_data[j] = |
| 3908 | ((temp_reg & 0xffff0000)) | |
| 3909 | ((table->mc_reg_table_entry[k].mc_data[i] & 0xffff0000) >> 16); |
| 3910 | } |
| 3911 | j++; |
| 3912 | PP_ASSERT_WITH_CODE((j < SMU72_DISCRETE_MC_REGISTER_ARRAY_SIZE), |
| 3913 | "Invalid VramInfo table.", return -1); |
| 3914 | |
| 3915 | temp_reg = cgs_read_register(hwmgr->device, mmMC_PMG_CMD_MRS); |
| 3916 | table->mc_reg_address[j].s1 = mmMC_PMG_CMD_MRS; |
| 3917 | table->mc_reg_address[j].s0 = mmMC_SEQ_PMG_CMD_MRS_LP; |
| 3918 | for (k = 0; k < table->num_entries; k++) { |
| 3919 | table->mc_reg_table_entry[k].mc_data[j] = |
| 3920 | (temp_reg & 0xffff0000) | |
| 3921 | (table->mc_reg_table_entry[k].mc_data[i] & 0x0000ffff); |
| 3922 | |
| 3923 | if (!data->is_memory_GDDR5) { |
| 3924 | table->mc_reg_table_entry[k].mc_data[j] |= 0x100; |
| 3925 | } |
| 3926 | } |
| 3927 | j++; |
| 3928 | PP_ASSERT_WITH_CODE((j <= SMU72_DISCRETE_MC_REGISTER_ARRAY_SIZE), |
| 3929 | "Invalid VramInfo table.", return -1); |
| 3930 | |
| 3931 | if (!data->is_memory_GDDR5) { |
| 3932 | table->mc_reg_address[j].s1 = mmMC_PMG_AUTO_CMD; |
| 3933 | table->mc_reg_address[j].s0 = mmMC_PMG_AUTO_CMD; |
| 3934 | for (k = 0; k < table->num_entries; k++) { |
| 3935 | table->mc_reg_table_entry[k].mc_data[j] = |
| 3936 | (table->mc_reg_table_entry[k].mc_data[i] & 0xffff0000) >> 16; |
| 3937 | } |
| 3938 | j++; |
| 3939 | PP_ASSERT_WITH_CODE((j <= SMU72_DISCRETE_MC_REGISTER_ARRAY_SIZE), |
| 3940 | "Invalid VramInfo table.", return -1); |
| 3941 | } |
| 3942 | |
| 3943 | break; |
| 3944 | |
| 3945 | case mmMC_SEQ_RESERVE_M: |
| 3946 | temp_reg = cgs_read_register(hwmgr->device, mmMC_PMG_CMD_MRS1); |
| 3947 | table->mc_reg_address[j].s1 = mmMC_PMG_CMD_MRS1; |
| 3948 | table->mc_reg_address[j].s0 = mmMC_SEQ_PMG_CMD_MRS1_LP; |
| 3949 | for (k = 0; k < table->num_entries; k++) { |
| 3950 | table->mc_reg_table_entry[k].mc_data[j] = |
| 3951 | (temp_reg & 0xffff0000) | |
| 3952 | (table->mc_reg_table_entry[k].mc_data[i] & 0x0000ffff); |
| 3953 | } |
| 3954 | j++; |
| 3955 | PP_ASSERT_WITH_CODE((j <= SMU72_DISCRETE_MC_REGISTER_ARRAY_SIZE), |
| 3956 | "Invalid VramInfo table.", return -1); |
| 3957 | break; |
| 3958 | |
| 3959 | default: |
| 3960 | break; |
| 3961 | } |
| 3962 | |
| 3963 | } |
| 3964 | |
| 3965 | table->last = j; |
| 3966 | |
| 3967 | return 0; |
| 3968 | } |
| 3969 | |
| 3970 | int tonga_set_valid_flag(phw_tonga_mc_reg_table *table) |
| 3971 | { |
| 3972 | uint8_t i, j; |
| 3973 | for (i = 0; i < table->last; i++) { |
| 3974 | for (j = 1; j < table->num_entries; j++) { |
| 3975 | if (table->mc_reg_table_entry[j-1].mc_data[i] != |
| 3976 | table->mc_reg_table_entry[j].mc_data[i]) { |
| 3977 | table->validflag |= (1<<i); |
| 3978 | break; |
| 3979 | } |
| 3980 | } |
| 3981 | } |
| 3982 | |
| 3983 | return 0; |
| 3984 | } |
| 3985 | |
| 3986 | int tonga_initialize_mc_reg_table(struct pp_hwmgr *hwmgr) |
| 3987 | { |
| 3988 | int result; |
| 3989 | tonga_hwmgr *data = (tonga_hwmgr *)(hwmgr->backend); |
| 3990 | pp_atomctrl_mc_reg_table *table; |
| 3991 | phw_tonga_mc_reg_table *ni_table = &data->tonga_mc_reg_table; |
| 3992 | uint8_t module_index = tonga_get_memory_modile_index(hwmgr); |
| 3993 | |
| 3994 | table = kzalloc(sizeof(pp_atomctrl_mc_reg_table), GFP_KERNEL); |
| 3995 | |
| 3996 | if (NULL == table) |
Rex Zhu | c15c8d7 | 2016-01-06 16:48:38 +0800 | [diff] [blame] | 3997 | return -ENOMEM; |
yanyang1 | c82baa2 | 2015-08-18 15:28:32 +0800 | [diff] [blame] | 3998 | |
| 3999 | /* Program additional LP registers that are no longer programmed by VBIOS */ |
| 4000 | cgs_write_register(hwmgr->device, mmMC_SEQ_RAS_TIMING_LP, cgs_read_register(hwmgr->device, mmMC_SEQ_RAS_TIMING)); |
| 4001 | cgs_write_register(hwmgr->device, mmMC_SEQ_CAS_TIMING_LP, cgs_read_register(hwmgr->device, mmMC_SEQ_CAS_TIMING)); |
| 4002 | cgs_write_register(hwmgr->device, mmMC_SEQ_DLL_STBY_LP, cgs_read_register(hwmgr->device, mmMC_SEQ_DLL_STBY)); |
| 4003 | cgs_write_register(hwmgr->device, mmMC_SEQ_G5PDX_CMD0_LP, cgs_read_register(hwmgr->device, mmMC_SEQ_G5PDX_CMD0)); |
| 4004 | cgs_write_register(hwmgr->device, mmMC_SEQ_G5PDX_CMD1_LP, cgs_read_register(hwmgr->device, mmMC_SEQ_G5PDX_CMD1)); |
| 4005 | cgs_write_register(hwmgr->device, mmMC_SEQ_G5PDX_CTRL_LP, cgs_read_register(hwmgr->device, mmMC_SEQ_G5PDX_CTRL)); |
| 4006 | cgs_write_register(hwmgr->device, mmMC_SEQ_PMG_DVS_CMD_LP, cgs_read_register(hwmgr->device, mmMC_SEQ_PMG_DVS_CMD)); |
| 4007 | cgs_write_register(hwmgr->device, mmMC_SEQ_PMG_DVS_CTL_LP, cgs_read_register(hwmgr->device, mmMC_SEQ_PMG_DVS_CTL)); |
| 4008 | cgs_write_register(hwmgr->device, mmMC_SEQ_MISC_TIMING_LP, cgs_read_register(hwmgr->device, mmMC_SEQ_MISC_TIMING)); |
| 4009 | cgs_write_register(hwmgr->device, mmMC_SEQ_MISC_TIMING2_LP, cgs_read_register(hwmgr->device, mmMC_SEQ_MISC_TIMING2)); |
| 4010 | cgs_write_register(hwmgr->device, mmMC_SEQ_PMG_CMD_EMRS_LP, cgs_read_register(hwmgr->device, mmMC_PMG_CMD_EMRS)); |
| 4011 | cgs_write_register(hwmgr->device, mmMC_SEQ_PMG_CMD_MRS_LP, cgs_read_register(hwmgr->device, mmMC_PMG_CMD_MRS)); |
| 4012 | cgs_write_register(hwmgr->device, mmMC_SEQ_PMG_CMD_MRS1_LP, cgs_read_register(hwmgr->device, mmMC_PMG_CMD_MRS1)); |
| 4013 | cgs_write_register(hwmgr->device, mmMC_SEQ_WR_CTL_D0_LP, cgs_read_register(hwmgr->device, mmMC_SEQ_WR_CTL_D0)); |
| 4014 | cgs_write_register(hwmgr->device, mmMC_SEQ_WR_CTL_D1_LP, cgs_read_register(hwmgr->device, mmMC_SEQ_WR_CTL_D1)); |
| 4015 | cgs_write_register(hwmgr->device, mmMC_SEQ_RD_CTL_D0_LP, cgs_read_register(hwmgr->device, mmMC_SEQ_RD_CTL_D0)); |
| 4016 | cgs_write_register(hwmgr->device, mmMC_SEQ_RD_CTL_D1_LP, cgs_read_register(hwmgr->device, mmMC_SEQ_RD_CTL_D1)); |
| 4017 | cgs_write_register(hwmgr->device, mmMC_SEQ_PMG_TIMING_LP, cgs_read_register(hwmgr->device, mmMC_SEQ_PMG_TIMING)); |
| 4018 | cgs_write_register(hwmgr->device, mmMC_SEQ_PMG_CMD_MRS2_LP, cgs_read_register(hwmgr->device, mmMC_PMG_CMD_MRS2)); |
| 4019 | cgs_write_register(hwmgr->device, mmMC_SEQ_WR_CTL_2_LP, cgs_read_register(hwmgr->device, mmMC_SEQ_WR_CTL_2)); |
| 4020 | |
| 4021 | memset(table, 0x00, sizeof(pp_atomctrl_mc_reg_table)); |
| 4022 | |
| 4023 | result = atomctrl_initialize_mc_reg_table(hwmgr, module_index, table); |
| 4024 | |
| 4025 | if (0 == result) |
| 4026 | result = tonga_copy_vbios_smc_reg_table(table, ni_table); |
| 4027 | |
| 4028 | if (0 == result) { |
| 4029 | tonga_set_s0_mc_reg_index(ni_table); |
| 4030 | result = tonga_set_mc_special_registers(hwmgr, ni_table); |
| 4031 | } |
| 4032 | |
| 4033 | if (0 == result) |
| 4034 | tonga_set_valid_flag(ni_table); |
| 4035 | |
| 4036 | kfree(table); |
| 4037 | return result; |
| 4038 | } |
| 4039 | |
| 4040 | /* |
| 4041 | * Copy one arb setting to another and then switch the active set. |
| 4042 | * arbFreqSrc and arbFreqDest is one of the MC_CG_ARB_FREQ_Fx constants. |
| 4043 | */ |
| 4044 | int tonga_copy_and_switch_arb_sets(struct pp_hwmgr *hwmgr, |
| 4045 | uint32_t arbFreqSrc, uint32_t arbFreqDest) |
| 4046 | { |
| 4047 | uint32_t mc_arb_dram_timing; |
| 4048 | uint32_t mc_arb_dram_timing2; |
| 4049 | uint32_t burst_time; |
| 4050 | uint32_t mc_cg_config; |
| 4051 | |
| 4052 | switch (arbFreqSrc) { |
| 4053 | case MC_CG_ARB_FREQ_F0: |
| 4054 | mc_arb_dram_timing = cgs_read_register(hwmgr->device, mmMC_ARB_DRAM_TIMING); |
| 4055 | mc_arb_dram_timing2 = cgs_read_register(hwmgr->device, mmMC_ARB_DRAM_TIMING2); |
| 4056 | burst_time = PHM_READ_FIELD(hwmgr->device, MC_ARB_BURST_TIME, STATE0); |
| 4057 | break; |
| 4058 | |
| 4059 | case MC_CG_ARB_FREQ_F1: |
| 4060 | mc_arb_dram_timing = cgs_read_register(hwmgr->device, mmMC_ARB_DRAM_TIMING_1); |
| 4061 | mc_arb_dram_timing2 = cgs_read_register(hwmgr->device, mmMC_ARB_DRAM_TIMING2_1); |
| 4062 | burst_time = PHM_READ_FIELD(hwmgr->device, MC_ARB_BURST_TIME, STATE1); |
| 4063 | break; |
| 4064 | |
| 4065 | default: |
| 4066 | return -1; |
| 4067 | } |
| 4068 | |
| 4069 | switch (arbFreqDest) { |
| 4070 | case MC_CG_ARB_FREQ_F0: |
| 4071 | cgs_write_register(hwmgr->device, mmMC_ARB_DRAM_TIMING, mc_arb_dram_timing); |
| 4072 | cgs_write_register(hwmgr->device, mmMC_ARB_DRAM_TIMING2, mc_arb_dram_timing2); |
| 4073 | PHM_WRITE_FIELD(hwmgr->device, MC_ARB_BURST_TIME, STATE0, burst_time); |
| 4074 | break; |
| 4075 | |
| 4076 | case MC_CG_ARB_FREQ_F1: |
| 4077 | cgs_write_register(hwmgr->device, mmMC_ARB_DRAM_TIMING_1, mc_arb_dram_timing); |
| 4078 | cgs_write_register(hwmgr->device, mmMC_ARB_DRAM_TIMING2_1, mc_arb_dram_timing2); |
| 4079 | PHM_WRITE_FIELD(hwmgr->device, MC_ARB_BURST_TIME, STATE1, burst_time); |
| 4080 | break; |
| 4081 | |
| 4082 | default: |
| 4083 | return -1; |
| 4084 | } |
| 4085 | |
| 4086 | mc_cg_config = cgs_read_register(hwmgr->device, mmMC_CG_CONFIG); |
| 4087 | mc_cg_config |= 0x0000000F; |
| 4088 | cgs_write_register(hwmgr->device, mmMC_CG_CONFIG, mc_cg_config); |
| 4089 | PHM_WRITE_FIELD(hwmgr->device, MC_ARB_CG, CG_ARB_REQ, arbFreqDest); |
| 4090 | |
| 4091 | return 0; |
| 4092 | } |
| 4093 | |
| 4094 | /** |
| 4095 | * Initial switch from ARB F0->F1 |
| 4096 | * |
| 4097 | * @param hwmgr the address of the powerplay hardware manager. |
| 4098 | * @return always 0 |
| 4099 | * This function is to be called from the SetPowerState table. |
| 4100 | */ |
| 4101 | int tonga_initial_switch_from_arb_f0_to_f1(struct pp_hwmgr *hwmgr) |
| 4102 | { |
| 4103 | return tonga_copy_and_switch_arb_sets(hwmgr, MC_CG_ARB_FREQ_F0, MC_CG_ARB_FREQ_F1); |
| 4104 | } |
| 4105 | |
| 4106 | /** |
| 4107 | * Initialize the ARB DRAM timing table's index field. |
| 4108 | * |
| 4109 | * @param hwmgr the address of the powerplay hardware manager. |
| 4110 | * @return always 0 |
| 4111 | */ |
| 4112 | int tonga_init_arb_table_index(struct pp_hwmgr *hwmgr) |
| 4113 | { |
| 4114 | const tonga_hwmgr *data = (struct tonga_hwmgr *)(hwmgr->backend); |
| 4115 | uint32_t tmp; |
| 4116 | int result; |
| 4117 | |
| 4118 | /* |
| 4119 | * This is a read-modify-write on the first byte of the ARB table. |
| 4120 | * The first byte in the SMU72_Discrete_MCArbDramTimingTable structure is the field 'current'. |
| 4121 | * This solution is ugly, but we never write the whole table only individual fields in it. |
| 4122 | * In reality this field should not be in that structure but in a soft register. |
| 4123 | */ |
| 4124 | result = tonga_read_smc_sram_dword(hwmgr->smumgr, |
| 4125 | data->arb_table_start, &tmp, data->sram_end); |
| 4126 | |
| 4127 | if (0 != result) |
| 4128 | return result; |
| 4129 | |
| 4130 | tmp &= 0x00FFFFFF; |
| 4131 | tmp |= ((uint32_t)MC_CG_ARB_FREQ_F1) << 24; |
| 4132 | |
| 4133 | return tonga_write_smc_sram_dword(hwmgr->smumgr, |
| 4134 | data->arb_table_start, tmp, data->sram_end); |
| 4135 | } |
| 4136 | |
| 4137 | int tonga_populate_mc_reg_address(struct pp_hwmgr *hwmgr, SMU72_Discrete_MCRegisters *mc_reg_table) |
| 4138 | { |
| 4139 | const struct tonga_hwmgr *data = (struct tonga_hwmgr *)(hwmgr->backend); |
| 4140 | |
| 4141 | uint32_t i, j; |
| 4142 | |
| 4143 | for (i = 0, j = 0; j < data->tonga_mc_reg_table.last; j++) { |
| 4144 | if (data->tonga_mc_reg_table.validflag & 1<<j) { |
| 4145 | PP_ASSERT_WITH_CODE(i < SMU72_DISCRETE_MC_REGISTER_ARRAY_SIZE, |
| 4146 | "Index of mc_reg_table->address[] array out of boundary", return -1); |
| 4147 | mc_reg_table->address[i].s0 = |
| 4148 | PP_HOST_TO_SMC_US(data->tonga_mc_reg_table.mc_reg_address[j].s0); |
| 4149 | mc_reg_table->address[i].s1 = |
| 4150 | PP_HOST_TO_SMC_US(data->tonga_mc_reg_table.mc_reg_address[j].s1); |
| 4151 | i++; |
| 4152 | } |
| 4153 | } |
| 4154 | |
| 4155 | mc_reg_table->last = (uint8_t)i; |
| 4156 | |
| 4157 | return 0; |
| 4158 | } |
| 4159 | |
| 4160 | /*convert register values from driver to SMC format */ |
| 4161 | void tonga_convert_mc_registers( |
| 4162 | const phw_tonga_mc_reg_entry * pEntry, |
| 4163 | SMU72_Discrete_MCRegisterSet *pData, |
| 4164 | uint32_t numEntries, uint32_t validflag) |
| 4165 | { |
| 4166 | uint32_t i, j; |
| 4167 | |
| 4168 | for (i = 0, j = 0; j < numEntries; j++) { |
| 4169 | if (validflag & 1<<j) { |
| 4170 | pData->value[i] = PP_HOST_TO_SMC_UL(pEntry->mc_data[j]); |
| 4171 | i++; |
| 4172 | } |
| 4173 | } |
| 4174 | } |
| 4175 | |
| 4176 | /* find the entry in the memory range table, then populate the value to SMC's tonga_mc_reg_table */ |
| 4177 | int tonga_convert_mc_reg_table_entry_to_smc( |
| 4178 | struct pp_hwmgr *hwmgr, |
| 4179 | const uint32_t memory_clock, |
| 4180 | SMU72_Discrete_MCRegisterSet *mc_reg_table_data |
| 4181 | ) |
| 4182 | { |
| 4183 | const tonga_hwmgr *data = (struct tonga_hwmgr *)(hwmgr->backend); |
| 4184 | uint32_t i = 0; |
| 4185 | |
| 4186 | for (i = 0; i < data->tonga_mc_reg_table.num_entries; i++) { |
| 4187 | if (memory_clock <= |
| 4188 | data->tonga_mc_reg_table.mc_reg_table_entry[i].mclk_max) { |
| 4189 | break; |
| 4190 | } |
| 4191 | } |
| 4192 | |
| 4193 | if ((i == data->tonga_mc_reg_table.num_entries) && (i > 0)) |
| 4194 | --i; |
| 4195 | |
| 4196 | tonga_convert_mc_registers(&data->tonga_mc_reg_table.mc_reg_table_entry[i], |
| 4197 | mc_reg_table_data, data->tonga_mc_reg_table.last, data->tonga_mc_reg_table.validflag); |
| 4198 | |
| 4199 | return 0; |
| 4200 | } |
| 4201 | |
| 4202 | int tonga_convert_mc_reg_table_to_smc(struct pp_hwmgr *hwmgr, |
| 4203 | SMU72_Discrete_MCRegisters *mc_reg_table) |
| 4204 | { |
| 4205 | int result = 0; |
| 4206 | tonga_hwmgr *data = (struct tonga_hwmgr *)(hwmgr->backend); |
| 4207 | int res; |
| 4208 | uint32_t i; |
| 4209 | |
| 4210 | for (i = 0; i < data->dpm_table.mclk_table.count; i++) { |
| 4211 | res = tonga_convert_mc_reg_table_entry_to_smc( |
| 4212 | hwmgr, |
| 4213 | data->dpm_table.mclk_table.dpm_levels[i].value, |
| 4214 | &mc_reg_table->data[i] |
| 4215 | ); |
| 4216 | |
| 4217 | if (0 != res) |
| 4218 | result = res; |
| 4219 | } |
| 4220 | |
| 4221 | return result; |
| 4222 | } |
| 4223 | |
| 4224 | int tonga_populate_initial_mc_reg_table(struct pp_hwmgr *hwmgr) |
| 4225 | { |
| 4226 | int result; |
| 4227 | struct tonga_hwmgr *data = (struct tonga_hwmgr *)(hwmgr->backend); |
| 4228 | |
| 4229 | memset(&data->mc_reg_table, 0x00, sizeof(SMU72_Discrete_MCRegisters)); |
| 4230 | result = tonga_populate_mc_reg_address(hwmgr, &(data->mc_reg_table)); |
| 4231 | PP_ASSERT_WITH_CODE(0 == result, |
| 4232 | "Failed to initialize MCRegTable for the MC register addresses!", return result;); |
| 4233 | |
| 4234 | result = tonga_convert_mc_reg_table_to_smc(hwmgr, &data->mc_reg_table); |
| 4235 | PP_ASSERT_WITH_CODE(0 == result, |
| 4236 | "Failed to initialize MCRegTable for driver state!", return result;); |
| 4237 | |
| 4238 | return tonga_copy_bytes_to_smc(hwmgr->smumgr, data->mc_reg_table_start, |
| 4239 | (uint8_t *)&data->mc_reg_table, sizeof(SMU72_Discrete_MCRegisters), data->sram_end); |
| 4240 | } |
| 4241 | |
| 4242 | /** |
| 4243 | * Programs static screed detection parameters |
| 4244 | * |
| 4245 | * @param hwmgr the address of the powerplay hardware manager. |
| 4246 | * @return always 0 |
| 4247 | */ |
| 4248 | int tonga_program_static_screen_threshold_parameters(struct pp_hwmgr *hwmgr) |
| 4249 | { |
| 4250 | tonga_hwmgr *data = (tonga_hwmgr *)(hwmgr->backend); |
| 4251 | |
| 4252 | /* Set static screen threshold unit*/ |
| 4253 | PHM_WRITE_VFPF_INDIRECT_FIELD(hwmgr->device, |
| 4254 | CGS_IND_REG__SMC, CG_STATIC_SCREEN_PARAMETER, STATIC_SCREEN_THRESHOLD_UNIT, |
| 4255 | data->static_screen_threshold_unit); |
| 4256 | /* Set static screen threshold*/ |
| 4257 | PHM_WRITE_VFPF_INDIRECT_FIELD(hwmgr->device, |
| 4258 | CGS_IND_REG__SMC, CG_STATIC_SCREEN_PARAMETER, STATIC_SCREEN_THRESHOLD, |
| 4259 | data->static_screen_threshold); |
| 4260 | |
| 4261 | return 0; |
| 4262 | } |
| 4263 | |
| 4264 | /** |
| 4265 | * Setup display gap for glitch free memory clock switching. |
| 4266 | * |
| 4267 | * @param hwmgr the address of the powerplay hardware manager. |
| 4268 | * @return always 0 |
| 4269 | */ |
| 4270 | int tonga_enable_display_gap(struct pp_hwmgr *hwmgr) |
| 4271 | { |
| 4272 | uint32_t display_gap = cgs_read_ind_register(hwmgr->device, |
| 4273 | CGS_IND_REG__SMC, ixCG_DISPLAY_GAP_CNTL); |
| 4274 | |
| 4275 | display_gap = PHM_SET_FIELD(display_gap, |
| 4276 | CG_DISPLAY_GAP_CNTL, DISP_GAP, DISPLAY_GAP_IGNORE); |
| 4277 | |
| 4278 | display_gap = PHM_SET_FIELD(display_gap, |
| 4279 | CG_DISPLAY_GAP_CNTL, DISP_GAP_MCHG, DISPLAY_GAP_VBLANK); |
| 4280 | |
| 4281 | cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, |
| 4282 | ixCG_DISPLAY_GAP_CNTL, display_gap); |
| 4283 | |
| 4284 | return 0; |
| 4285 | } |
| 4286 | |
| 4287 | /** |
| 4288 | * Programs activity state transition voting clients |
| 4289 | * |
| 4290 | * @param hwmgr the address of the powerplay hardware manager. |
| 4291 | * @return always 0 |
| 4292 | */ |
| 4293 | int tonga_program_voting_clients(struct pp_hwmgr *hwmgr) |
| 4294 | { |
| 4295 | tonga_hwmgr *data = (tonga_hwmgr *)(hwmgr->backend); |
| 4296 | |
| 4297 | /* Clear reset for voting clients before enabling DPM */ |
| 4298 | PHM_WRITE_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, |
| 4299 | SCLK_PWRMGT_CNTL, RESET_SCLK_CNT, 0); |
| 4300 | PHM_WRITE_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, |
| 4301 | SCLK_PWRMGT_CNTL, RESET_BUSY_CNT, 0); |
| 4302 | |
| 4303 | cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, |
| 4304 | ixCG_FREQ_TRAN_VOTING_0, data->voting_rights_clients0); |
| 4305 | cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, |
| 4306 | ixCG_FREQ_TRAN_VOTING_1, data->voting_rights_clients1); |
| 4307 | cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, |
| 4308 | ixCG_FREQ_TRAN_VOTING_2, data->voting_rights_clients2); |
| 4309 | cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, |
| 4310 | ixCG_FREQ_TRAN_VOTING_3, data->voting_rights_clients3); |
| 4311 | cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, |
| 4312 | ixCG_FREQ_TRAN_VOTING_4, data->voting_rights_clients4); |
| 4313 | cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, |
| 4314 | ixCG_FREQ_TRAN_VOTING_5, data->voting_rights_clients5); |
| 4315 | cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, |
| 4316 | ixCG_FREQ_TRAN_VOTING_6, data->voting_rights_clients6); |
| 4317 | cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, |
| 4318 | ixCG_FREQ_TRAN_VOTING_7, data->voting_rights_clients7); |
| 4319 | |
| 4320 | return 0; |
| 4321 | } |
| 4322 | |
| 4323 | |
| 4324 | int tonga_enable_dpm_tasks(struct pp_hwmgr *hwmgr) |
| 4325 | { |
| 4326 | int tmp_result, result = 0; |
| 4327 | |
| 4328 | tmp_result = tonga_check_for_dpm_stopped(hwmgr); |
| 4329 | |
| 4330 | if (cf_tonga_voltage_control(hwmgr)) { |
| 4331 | tmp_result = tonga_enable_voltage_control(hwmgr); |
| 4332 | PP_ASSERT_WITH_CODE((0 == tmp_result), |
| 4333 | "Failed to enable voltage control!", result = tmp_result); |
| 4334 | |
| 4335 | tmp_result = tonga_construct_voltage_tables(hwmgr); |
| 4336 | PP_ASSERT_WITH_CODE((0 == tmp_result), |
| 4337 | "Failed to contruct voltage tables!", result = tmp_result); |
| 4338 | } |
| 4339 | |
| 4340 | tmp_result = tonga_initialize_mc_reg_table(hwmgr); |
| 4341 | PP_ASSERT_WITH_CODE((0 == tmp_result), |
| 4342 | "Failed to initialize MC reg table!", result = tmp_result); |
| 4343 | |
| 4344 | tmp_result = tonga_program_static_screen_threshold_parameters(hwmgr); |
| 4345 | PP_ASSERT_WITH_CODE((0 == tmp_result), |
| 4346 | "Failed to program static screen threshold parameters!", result = tmp_result); |
| 4347 | |
| 4348 | tmp_result = tonga_enable_display_gap(hwmgr); |
| 4349 | PP_ASSERT_WITH_CODE((0 == tmp_result), |
| 4350 | "Failed to enable display gap!", result = tmp_result); |
| 4351 | |
| 4352 | tmp_result = tonga_program_voting_clients(hwmgr); |
| 4353 | PP_ASSERT_WITH_CODE((0 == tmp_result), |
| 4354 | "Failed to program voting clients!", result = tmp_result); |
| 4355 | |
| 4356 | tmp_result = tonga_process_firmware_header(hwmgr); |
| 4357 | PP_ASSERT_WITH_CODE((0 == tmp_result), |
| 4358 | "Failed to process firmware header!", result = tmp_result); |
| 4359 | |
| 4360 | tmp_result = tonga_initial_switch_from_arb_f0_to_f1(hwmgr); |
| 4361 | PP_ASSERT_WITH_CODE((0 == tmp_result), |
| 4362 | "Failed to initialize switch from ArbF0 to F1!", result = tmp_result); |
| 4363 | |
| 4364 | tmp_result = tonga_init_smc_table(hwmgr); |
| 4365 | PP_ASSERT_WITH_CODE((0 == tmp_result), |
| 4366 | "Failed to initialize SMC table!", result = tmp_result); |
| 4367 | |
| 4368 | tmp_result = tonga_init_arb_table_index(hwmgr); |
| 4369 | PP_ASSERT_WITH_CODE((0 == tmp_result), |
| 4370 | "Failed to initialize ARB table index!", result = tmp_result); |
| 4371 | |
| 4372 | tmp_result = tonga_populate_initial_mc_reg_table(hwmgr); |
| 4373 | PP_ASSERT_WITH_CODE((0 == tmp_result), |
| 4374 | "Failed to populate initialize MC Reg table!", result = tmp_result); |
| 4375 | |
Rex Zhu | bbb207f | 2015-10-16 15:02:04 +0800 | [diff] [blame] | 4376 | tmp_result = tonga_notify_smc_display_change(hwmgr, false); |
| 4377 | PP_ASSERT_WITH_CODE((0 == tmp_result), |
| 4378 | "Failed to notify no display!", result = tmp_result); |
| 4379 | |
yanyang1 | c82baa2 | 2015-08-18 15:28:32 +0800 | [diff] [blame] | 4380 | /* enable SCLK control */ |
| 4381 | tmp_result = tonga_enable_sclk_control(hwmgr); |
| 4382 | PP_ASSERT_WITH_CODE((0 == tmp_result), |
| 4383 | "Failed to enable SCLK control!", result = tmp_result); |
| 4384 | |
| 4385 | /* enable DPM */ |
| 4386 | tmp_result = tonga_start_dpm(hwmgr); |
| 4387 | PP_ASSERT_WITH_CODE((0 == tmp_result), |
| 4388 | "Failed to start DPM!", result = tmp_result); |
| 4389 | |
| 4390 | return result; |
| 4391 | } |
| 4392 | |
| 4393 | int tonga_disable_dpm_tasks(struct pp_hwmgr *hwmgr) |
| 4394 | { |
| 4395 | int tmp_result, result = 0; |
| 4396 | |
| 4397 | tmp_result = tonga_check_for_dpm_running(hwmgr); |
| 4398 | PP_ASSERT_WITH_CODE((0 == tmp_result), |
| 4399 | "SMC is still running!", return 0); |
| 4400 | |
| 4401 | tmp_result = tonga_stop_dpm(hwmgr); |
| 4402 | PP_ASSERT_WITH_CODE((0 == tmp_result), |
| 4403 | "Failed to stop DPM!", result = tmp_result); |
| 4404 | |
| 4405 | tmp_result = tonga_reset_to_default(hwmgr); |
| 4406 | PP_ASSERT_WITH_CODE((0 == tmp_result), |
| 4407 | "Failed to reset to default!", result = tmp_result); |
| 4408 | |
| 4409 | return result; |
| 4410 | } |
| 4411 | |
| 4412 | int tonga_reset_asic_tasks(struct pp_hwmgr *hwmgr) |
| 4413 | { |
| 4414 | int result; |
| 4415 | |
| 4416 | result = tonga_set_boot_state(hwmgr); |
| 4417 | if (0 != result) |
| 4418 | printk(KERN_ERR "[ powerplay ] Failed to reset asic via set boot state! \n"); |
| 4419 | |
| 4420 | return result; |
| 4421 | } |
| 4422 | |
| 4423 | int tonga_hwmgr_backend_fini(struct pp_hwmgr *hwmgr) |
| 4424 | { |
Eric Huang | 92dea67 | 2016-04-15 17:14:53 -0400 | [diff] [blame] | 4425 | return phm_hwmgr_backend_fini(hwmgr); |
yanyang1 | c82baa2 | 2015-08-18 15:28:32 +0800 | [diff] [blame] | 4426 | } |
| 4427 | |
| 4428 | /** |
| 4429 | * Initializes the Volcanic Islands Hardware Manager |
| 4430 | * |
| 4431 | * @param hwmgr the address of the powerplay hardware manager. |
| 4432 | * @return 1 if success; otherwise appropriate error code. |
| 4433 | */ |
| 4434 | int tonga_hwmgr_backend_init(struct pp_hwmgr *hwmgr) |
| 4435 | { |
| 4436 | int result = 0; |
| 4437 | SMU72_Discrete_DpmTable *table = NULL; |
Eric Huang | 76ad42c | 2016-06-02 16:15:59 -0400 | [diff] [blame] | 4438 | tonga_hwmgr *data; |
yanyang1 | c82baa2 | 2015-08-18 15:28:32 +0800 | [diff] [blame] | 4439 | pp_atomctrl_gpio_pin_assignment gpio_pin_assignment; |
| 4440 | struct phm_ppt_v1_information *pptable_info = (struct phm_ppt_v1_information *)(hwmgr->pptable); |
| 4441 | phw_tonga_ulv_parm *ulv; |
Alex Deucher | 52b52a8 | 2016-02-05 11:11:51 -0500 | [diff] [blame] | 4442 | struct cgs_system_info sys_info = {0}; |
yanyang1 | c82baa2 | 2015-08-18 15:28:32 +0800 | [diff] [blame] | 4443 | |
| 4444 | PP_ASSERT_WITH_CODE((NULL != hwmgr), |
| 4445 | "Invalid Parameter!", return -1;); |
| 4446 | |
Eric Huang | 76ad42c | 2016-06-02 16:15:59 -0400 | [diff] [blame] | 4447 | data = kzalloc(sizeof(struct tonga_hwmgr), GFP_KERNEL); |
| 4448 | if (data == NULL) |
| 4449 | return -ENOMEM; |
| 4450 | |
| 4451 | hwmgr->backend = data; |
| 4452 | |
Edward O'Callaghan | ed5121a | 2016-07-12 10:17:52 +1000 | [diff] [blame] | 4453 | data->dll_defaule_on = false; |
yanyang1 | c82baa2 | 2015-08-18 15:28:32 +0800 | [diff] [blame] | 4454 | data->sram_end = SMC_RAM_END; |
| 4455 | |
| 4456 | data->activity_target[0] = PPTONGA_TARGETACTIVITY_DFLT; |
| 4457 | data->activity_target[1] = PPTONGA_TARGETACTIVITY_DFLT; |
| 4458 | data->activity_target[2] = PPTONGA_TARGETACTIVITY_DFLT; |
| 4459 | data->activity_target[3] = PPTONGA_TARGETACTIVITY_DFLT; |
| 4460 | data->activity_target[4] = PPTONGA_TARGETACTIVITY_DFLT; |
| 4461 | data->activity_target[5] = PPTONGA_TARGETACTIVITY_DFLT; |
| 4462 | data->activity_target[6] = PPTONGA_TARGETACTIVITY_DFLT; |
| 4463 | data->activity_target[7] = PPTONGA_TARGETACTIVITY_DFLT; |
| 4464 | |
| 4465 | data->vddc_vddci_delta = VDDC_VDDCI_DELTA; |
| 4466 | data->vddc_vddgfx_delta = VDDC_VDDGFX_DELTA; |
| 4467 | data->mclk_activity_target = PPTONGA_MCLK_TARGETACTIVITY_DFLT; |
| 4468 | |
| 4469 | phm_cap_set(hwmgr->platform_descriptor.platformCaps, |
| 4470 | PHM_PlatformCaps_DisableVoltageIsland); |
| 4471 | |
| 4472 | data->sclk_dpm_key_disabled = 0; |
| 4473 | data->mclk_dpm_key_disabled = 0; |
| 4474 | data->pcie_dpm_key_disabled = 0; |
| 4475 | data->pcc_monitor_enabled = 0; |
| 4476 | |
| 4477 | phm_cap_set(hwmgr->platform_descriptor.platformCaps, |
| 4478 | PHM_PlatformCaps_UnTabledHardwareInterface); |
| 4479 | |
| 4480 | data->gpio_debug = 0; |
| 4481 | data->engine_clock_data = 0; |
| 4482 | data->memory_clock_data = 0; |
| 4483 | phm_cap_set(hwmgr->platform_descriptor.platformCaps, |
| 4484 | PHM_PlatformCaps_DynamicPatchPowerState); |
| 4485 | |
| 4486 | /* need to set voltage control types before EVV patching*/ |
| 4487 | data->voltage_control = TONGA_VOLTAGE_CONTROL_NONE; |
| 4488 | data->vdd_ci_control = TONGA_VOLTAGE_CONTROL_NONE; |
| 4489 | data->vdd_gfx_control = TONGA_VOLTAGE_CONTROL_NONE; |
| 4490 | data->mvdd_control = TONGA_VOLTAGE_CONTROL_NONE; |
Rex Zhu | a2fb493 | 2016-06-13 17:46:31 +0800 | [diff] [blame] | 4491 | data->force_pcie_gen = PP_PCIEGenInvalid; |
yanyang1 | c82baa2 | 2015-08-18 15:28:32 +0800 | [diff] [blame] | 4492 | |
Eric Huang | 3ec2cdb | 2015-11-09 17:35:45 -0500 | [diff] [blame] | 4493 | if (atomctrl_is_voltage_controled_by_gpio_v3(hwmgr, |
yanyang1 | c82baa2 | 2015-08-18 15:28:32 +0800 | [diff] [blame] | 4494 | VOLTAGE_TYPE_VDDC, VOLTAGE_OBJ_SVID2)) { |
| 4495 | data->voltage_control = TONGA_VOLTAGE_CONTROL_BY_SVID2; |
| 4496 | } |
| 4497 | |
| 4498 | if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, |
| 4499 | PHM_PlatformCaps_ControlVDDGFX)) { |
Eric Huang | 3ec2cdb | 2015-11-09 17:35:45 -0500 | [diff] [blame] | 4500 | if (atomctrl_is_voltage_controled_by_gpio_v3(hwmgr, |
yanyang1 | c82baa2 | 2015-08-18 15:28:32 +0800 | [diff] [blame] | 4501 | VOLTAGE_TYPE_VDDGFX, VOLTAGE_OBJ_SVID2)) { |
| 4502 | data->vdd_gfx_control = TONGA_VOLTAGE_CONTROL_BY_SVID2; |
| 4503 | } |
| 4504 | } |
| 4505 | |
| 4506 | if (TONGA_VOLTAGE_CONTROL_NONE == data->vdd_gfx_control) { |
| 4507 | phm_cap_unset(hwmgr->platform_descriptor.platformCaps, |
| 4508 | PHM_PlatformCaps_ControlVDDGFX); |
| 4509 | } |
| 4510 | |
| 4511 | if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, |
| 4512 | PHM_PlatformCaps_EnableMVDDControl)) { |
Eric Huang | 3ec2cdb | 2015-11-09 17:35:45 -0500 | [diff] [blame] | 4513 | if (atomctrl_is_voltage_controled_by_gpio_v3(hwmgr, |
yanyang1 | c82baa2 | 2015-08-18 15:28:32 +0800 | [diff] [blame] | 4514 | VOLTAGE_TYPE_MVDDC, VOLTAGE_OBJ_GPIO_LUT)) { |
| 4515 | data->mvdd_control = TONGA_VOLTAGE_CONTROL_BY_GPIO; |
| 4516 | } |
| 4517 | } |
| 4518 | |
| 4519 | if (TONGA_VOLTAGE_CONTROL_NONE == data->mvdd_control) { |
| 4520 | phm_cap_unset(hwmgr->platform_descriptor.platformCaps, |
| 4521 | PHM_PlatformCaps_EnableMVDDControl); |
| 4522 | } |
| 4523 | |
| 4524 | if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, |
| 4525 | PHM_PlatformCaps_ControlVDDCI)) { |
Eric Huang | 3ec2cdb | 2015-11-09 17:35:45 -0500 | [diff] [blame] | 4526 | if (atomctrl_is_voltage_controled_by_gpio_v3(hwmgr, |
yanyang1 | c82baa2 | 2015-08-18 15:28:32 +0800 | [diff] [blame] | 4527 | VOLTAGE_TYPE_VDDCI, VOLTAGE_OBJ_GPIO_LUT)) |
| 4528 | data->vdd_ci_control = TONGA_VOLTAGE_CONTROL_BY_GPIO; |
Eric Huang | 3ec2cdb | 2015-11-09 17:35:45 -0500 | [diff] [blame] | 4529 | else if (atomctrl_is_voltage_controled_by_gpio_v3(hwmgr, |
yanyang1 | c82baa2 | 2015-08-18 15:28:32 +0800 | [diff] [blame] | 4530 | VOLTAGE_TYPE_VDDCI, VOLTAGE_OBJ_SVID2)) |
| 4531 | data->vdd_ci_control = TONGA_VOLTAGE_CONTROL_BY_SVID2; |
| 4532 | } |
| 4533 | |
| 4534 | if (TONGA_VOLTAGE_CONTROL_NONE == data->vdd_ci_control) |
| 4535 | phm_cap_unset(hwmgr->platform_descriptor.platformCaps, |
| 4536 | PHM_PlatformCaps_ControlVDDCI); |
| 4537 | |
| 4538 | phm_cap_set(hwmgr->platform_descriptor.platformCaps, |
| 4539 | PHM_PlatformCaps_TablelessHardwareInterface); |
| 4540 | |
| 4541 | if (pptable_info->cac_dtp_table->usClockStretchAmount != 0) |
| 4542 | phm_cap_set(hwmgr->platform_descriptor.platformCaps, |
| 4543 | PHM_PlatformCaps_ClockStretcher); |
| 4544 | |
| 4545 | /* Initializes DPM default values*/ |
| 4546 | tonga_initialize_dpm_defaults(hwmgr); |
| 4547 | |
| 4548 | /* Get leakage voltage based on leakage ID.*/ |
| 4549 | PP_ASSERT_WITH_CODE((0 == tonga_get_evv_voltage(hwmgr)), |
| 4550 | "Get EVV Voltage Failed. Abort Driver loading!", return -1); |
| 4551 | |
| 4552 | tonga_complete_dependency_tables(hwmgr); |
| 4553 | |
| 4554 | /* Parse pptable data read from VBIOS*/ |
| 4555 | tonga_set_private_var_based_on_pptale(hwmgr); |
| 4556 | |
| 4557 | /* ULV Support*/ |
| 4558 | ulv = &(data->ulv); |
Edward O'Callaghan | ed5121a | 2016-07-12 10:17:52 +1000 | [diff] [blame] | 4559 | ulv->ulv_supported = false; |
yanyang1 | c82baa2 | 2015-08-18 15:28:32 +0800 | [diff] [blame] | 4560 | |
| 4561 | /* Initalize Dynamic State Adjustment Rule Settings*/ |
| 4562 | result = tonga_initializa_dynamic_state_adjustment_rule_settings(hwmgr); |
Alex Deucher | aa22ae4 | 2015-12-11 12:39:01 -0500 | [diff] [blame] | 4563 | if (result) |
| 4564 | printk(KERN_ERR "[ powerplay ] tonga_initializa_dynamic_state_adjustment_rule_settings failed!\n"); |
Edward O'Callaghan | ed5121a | 2016-07-12 10:17:52 +1000 | [diff] [blame] | 4565 | data->uvd_enabled = false; |
yanyang1 | c82baa2 | 2015-08-18 15:28:32 +0800 | [diff] [blame] | 4566 | |
| 4567 | table = &(data->smc_state_table); |
| 4568 | |
| 4569 | /* |
| 4570 | * if ucGPIO_ID=VDDC_PCC_GPIO_PINID in GPIO_LUTable, |
| 4571 | * Peak Current Control feature is enabled and we should program PCC HW register |
| 4572 | */ |
Rex Zhu | e013c91 | 2016-06-29 19:48:58 +0800 | [diff] [blame] | 4573 | if (atomctrl_get_pp_assign_pin(hwmgr, VDDC_PCC_GPIO_PINID, &gpio_pin_assignment)) { |
yanyang1 | c82baa2 | 2015-08-18 15:28:32 +0800 | [diff] [blame] | 4574 | uint32_t temp_reg = cgs_read_ind_register(hwmgr->device, |
| 4575 | CGS_IND_REG__SMC, ixCNB_PWRMGT_CNTL); |
| 4576 | |
| 4577 | switch (gpio_pin_assignment.uc_gpio_pin_bit_shift) { |
| 4578 | case 0: |
| 4579 | temp_reg = PHM_SET_FIELD(temp_reg, |
| 4580 | CNB_PWRMGT_CNTL, GNB_SLOW_MODE, 0x1); |
| 4581 | break; |
| 4582 | case 1: |
| 4583 | temp_reg = PHM_SET_FIELD(temp_reg, |
| 4584 | CNB_PWRMGT_CNTL, GNB_SLOW_MODE, 0x2); |
| 4585 | break; |
| 4586 | case 2: |
| 4587 | temp_reg = PHM_SET_FIELD(temp_reg, |
| 4588 | CNB_PWRMGT_CNTL, GNB_SLOW, 0x1); |
| 4589 | break; |
| 4590 | case 3: |
| 4591 | temp_reg = PHM_SET_FIELD(temp_reg, |
| 4592 | CNB_PWRMGT_CNTL, FORCE_NB_PS1, 0x1); |
| 4593 | break; |
| 4594 | case 4: |
| 4595 | temp_reg = PHM_SET_FIELD(temp_reg, |
| 4596 | CNB_PWRMGT_CNTL, DPM_ENABLED, 0x1); |
| 4597 | break; |
| 4598 | default: |
| 4599 | printk(KERN_ERR "[ powerplay ] Failed to setup PCC HW register! \ |
| 4600 | Wrong GPIO assigned for VDDC_PCC_GPIO_PINID! \n"); |
| 4601 | break; |
| 4602 | } |
| 4603 | cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, |
| 4604 | ixCNB_PWRMGT_CNTL, temp_reg); |
| 4605 | } |
| 4606 | |
| 4607 | phm_cap_set(hwmgr->platform_descriptor.platformCaps, |
| 4608 | PHM_PlatformCaps_EnableSMU7ThermalManagement); |
| 4609 | phm_cap_set(hwmgr->platform_descriptor.platformCaps, |
| 4610 | PHM_PlatformCaps_SMU7); |
| 4611 | |
Edward O'Callaghan | ed5121a | 2016-07-12 10:17:52 +1000 | [diff] [blame] | 4612 | data->vddc_phase_shed_control = false; |
yanyang1 | c82baa2 | 2015-08-18 15:28:32 +0800 | [diff] [blame] | 4613 | |
Alex Deucher | 3d5afb4 | 2016-02-04 23:47:38 -0500 | [diff] [blame] | 4614 | phm_cap_unset(hwmgr->platform_descriptor.platformCaps, |
| 4615 | PHM_PlatformCaps_UVDPowerGating); |
Alex Deucher | f997e6f | 2016-02-04 23:48:51 -0500 | [diff] [blame] | 4616 | phm_cap_unset(hwmgr->platform_descriptor.platformCaps, |
| 4617 | PHM_PlatformCaps_VCEPowerGating); |
Alex Deucher | 52b52a8 | 2016-02-05 11:11:51 -0500 | [diff] [blame] | 4618 | sys_info.size = sizeof(struct cgs_system_info); |
| 4619 | sys_info.info_id = CGS_SYSTEM_INFO_PG_FLAGS; |
| 4620 | result = cgs_query_system_info(hwmgr->device, &sys_info); |
| 4621 | if (!result) { |
| 4622 | if (sys_info.value & AMD_PG_SUPPORT_UVD) |
| 4623 | phm_cap_set(hwmgr->platform_descriptor.platformCaps, |
| 4624 | PHM_PlatformCaps_UVDPowerGating); |
| 4625 | if (sys_info.value & AMD_PG_SUPPORT_VCE) |
| 4626 | phm_cap_set(hwmgr->platform_descriptor.platformCaps, |
| 4627 | PHM_PlatformCaps_VCEPowerGating); |
| 4628 | } |
Alex Deucher | 834b694 | 2015-11-11 20:58:55 -0500 | [diff] [blame] | 4629 | |
yanyang1 | c82baa2 | 2015-08-18 15:28:32 +0800 | [diff] [blame] | 4630 | if (0 == result) { |
Edward O'Callaghan | ed5121a | 2016-07-12 10:17:52 +1000 | [diff] [blame] | 4631 | data->is_tlu_enabled = false; |
yanyang1 | c82baa2 | 2015-08-18 15:28:32 +0800 | [diff] [blame] | 4632 | hwmgr->platform_descriptor.hardwareActivityPerformanceLevels = |
| 4633 | TONGA_MAX_HARDWARE_POWERLEVELS; |
| 4634 | hwmgr->platform_descriptor.hardwarePerformanceLevels = 2; |
| 4635 | hwmgr->platform_descriptor.minimumClocksReductionPercentage = 50; |
| 4636 | |
Alex Deucher | 834b694 | 2015-11-11 20:58:55 -0500 | [diff] [blame] | 4637 | sys_info.size = sizeof(struct cgs_system_info); |
| 4638 | sys_info.info_id = CGS_SYSTEM_INFO_PCIE_GEN_INFO; |
| 4639 | result = cgs_query_system_info(hwmgr->device, &sys_info); |
| 4640 | if (result) |
Huang Rui | d1371f8 | 2016-06-22 13:49:48 +0800 | [diff] [blame] | 4641 | data->pcie_gen_cap = AMDGPU_DEFAULT_PCIE_GEN_MASK; |
Alex Deucher | 834b694 | 2015-11-11 20:58:55 -0500 | [diff] [blame] | 4642 | else |
| 4643 | data->pcie_gen_cap = (uint32_t)sys_info.value; |
| 4644 | if (data->pcie_gen_cap & CAIL_PCIE_LINK_SPEED_SUPPORT_GEN3) |
| 4645 | data->pcie_spc_cap = 20; |
| 4646 | sys_info.size = sizeof(struct cgs_system_info); |
| 4647 | sys_info.info_id = CGS_SYSTEM_INFO_PCIE_MLW; |
| 4648 | result = cgs_query_system_info(hwmgr->device, &sys_info); |
| 4649 | if (result) |
Huang Rui | d1371f8 | 2016-06-22 13:49:48 +0800 | [diff] [blame] | 4650 | data->pcie_lane_cap = AMDGPU_DEFAULT_PCIE_MLW_MASK; |
Alex Deucher | 834b694 | 2015-11-11 20:58:55 -0500 | [diff] [blame] | 4651 | else |
| 4652 | data->pcie_lane_cap = (uint32_t)sys_info.value; |
yanyang1 | c82baa2 | 2015-08-18 15:28:32 +0800 | [diff] [blame] | 4653 | } else { |
| 4654 | /* Ignore return value in here, we are cleaning up a mess. */ |
| 4655 | tonga_hwmgr_backend_fini(hwmgr); |
| 4656 | } |
| 4657 | |
| 4658 | return result; |
| 4659 | } |
| 4660 | |
| 4661 | static int tonga_force_dpm_level(struct pp_hwmgr *hwmgr, |
| 4662 | enum amd_dpm_forced_level level) |
| 4663 | { |
| 4664 | int ret = 0; |
| 4665 | |
| 4666 | switch (level) { |
| 4667 | case AMD_DPM_FORCED_LEVEL_HIGH: |
| 4668 | ret = tonga_force_dpm_highest(hwmgr); |
| 4669 | if (ret) |
| 4670 | return ret; |
| 4671 | break; |
| 4672 | case AMD_DPM_FORCED_LEVEL_LOW: |
| 4673 | ret = tonga_force_dpm_lowest(hwmgr); |
| 4674 | if (ret) |
| 4675 | return ret; |
| 4676 | break; |
| 4677 | case AMD_DPM_FORCED_LEVEL_AUTO: |
| 4678 | ret = tonga_unforce_dpm_levels(hwmgr); |
| 4679 | if (ret) |
| 4680 | return ret; |
| 4681 | break; |
| 4682 | default: |
| 4683 | break; |
| 4684 | } |
| 4685 | |
| 4686 | hwmgr->dpm_level = level; |
| 4687 | return ret; |
| 4688 | } |
| 4689 | |
| 4690 | static int tonga_apply_state_adjust_rules(struct pp_hwmgr *hwmgr, |
| 4691 | struct pp_power_state *prequest_ps, |
| 4692 | const struct pp_power_state *pcurrent_ps) |
| 4693 | { |
| 4694 | struct tonga_power_state *tonga_ps = |
| 4695 | cast_phw_tonga_power_state(&prequest_ps->hardware); |
| 4696 | |
| 4697 | uint32_t sclk; |
| 4698 | uint32_t mclk; |
| 4699 | struct PP_Clocks minimum_clocks = {0}; |
| 4700 | bool disable_mclk_switching; |
| 4701 | bool disable_mclk_switching_for_frame_lock; |
| 4702 | struct cgs_display_info info = {0}; |
| 4703 | const struct phm_clock_and_voltage_limits *max_limits; |
| 4704 | uint32_t i; |
| 4705 | tonga_hwmgr *data = (struct tonga_hwmgr *)(hwmgr->backend); |
| 4706 | struct phm_ppt_v1_information *pptable_info = (struct phm_ppt_v1_information *)(hwmgr->pptable); |
| 4707 | |
| 4708 | int32_t count; |
| 4709 | int32_t stable_pstate_sclk = 0, stable_pstate_mclk = 0; |
| 4710 | |
| 4711 | data->battery_state = (PP_StateUILabel_Battery == prequest_ps->classification.ui_label); |
| 4712 | |
| 4713 | PP_ASSERT_WITH_CODE(tonga_ps->performance_level_count == 2, |
| 4714 | "VI should always have 2 performance levels", |
| 4715 | ); |
| 4716 | |
| 4717 | max_limits = (PP_PowerSource_AC == hwmgr->power_source) ? |
| 4718 | &(hwmgr->dyn_state.max_clock_voltage_on_ac) : |
| 4719 | &(hwmgr->dyn_state.max_clock_voltage_on_dc); |
| 4720 | |
| 4721 | if (PP_PowerSource_DC == hwmgr->power_source) { |
| 4722 | for (i = 0; i < tonga_ps->performance_level_count; i++) { |
| 4723 | if (tonga_ps->performance_levels[i].memory_clock > max_limits->mclk) |
| 4724 | tonga_ps->performance_levels[i].memory_clock = max_limits->mclk; |
| 4725 | if (tonga_ps->performance_levels[i].engine_clock > max_limits->sclk) |
| 4726 | tonga_ps->performance_levels[i].engine_clock = max_limits->sclk; |
| 4727 | } |
| 4728 | } |
| 4729 | |
| 4730 | tonga_ps->vce_clocks.EVCLK = hwmgr->vce_arbiter.evclk; |
| 4731 | tonga_ps->vce_clocks.ECCLK = hwmgr->vce_arbiter.ecclk; |
| 4732 | |
| 4733 | tonga_ps->acp_clk = hwmgr->acp_arbiter.acpclk; |
| 4734 | |
| 4735 | cgs_get_active_displays_info(hwmgr->device, &info); |
| 4736 | |
| 4737 | /*TO DO result = PHM_CheckVBlankTime(hwmgr, &vblankTooShort);*/ |
| 4738 | |
| 4739 | /* TO DO GetMinClockSettings(hwmgr->pPECI, &minimum_clocks); */ |
| 4740 | |
| 4741 | if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_StablePState)) { |
| 4742 | |
| 4743 | max_limits = &(hwmgr->dyn_state.max_clock_voltage_on_ac); |
| 4744 | stable_pstate_sclk = (max_limits->sclk * 75) / 100; |
| 4745 | |
| 4746 | for (count = pptable_info->vdd_dep_on_sclk->count-1; count >= 0; count--) { |
| 4747 | if (stable_pstate_sclk >= pptable_info->vdd_dep_on_sclk->entries[count].clk) { |
| 4748 | stable_pstate_sclk = pptable_info->vdd_dep_on_sclk->entries[count].clk; |
| 4749 | break; |
| 4750 | } |
| 4751 | } |
| 4752 | |
| 4753 | if (count < 0) |
| 4754 | stable_pstate_sclk = pptable_info->vdd_dep_on_sclk->entries[0].clk; |
| 4755 | |
| 4756 | stable_pstate_mclk = max_limits->mclk; |
| 4757 | |
| 4758 | minimum_clocks.engineClock = stable_pstate_sclk; |
| 4759 | minimum_clocks.memoryClock = stable_pstate_mclk; |
| 4760 | } |
| 4761 | |
| 4762 | if (minimum_clocks.engineClock < hwmgr->gfx_arbiter.sclk) |
| 4763 | minimum_clocks.engineClock = hwmgr->gfx_arbiter.sclk; |
| 4764 | |
| 4765 | if (minimum_clocks.memoryClock < hwmgr->gfx_arbiter.mclk) |
| 4766 | minimum_clocks.memoryClock = hwmgr->gfx_arbiter.mclk; |
| 4767 | |
| 4768 | tonga_ps->sclk_threshold = hwmgr->gfx_arbiter.sclk_threshold; |
| 4769 | |
| 4770 | if (0 != hwmgr->gfx_arbiter.sclk_over_drive) { |
| 4771 | PP_ASSERT_WITH_CODE((hwmgr->gfx_arbiter.sclk_over_drive <= hwmgr->platform_descriptor.overdriveLimit.engineClock), |
| 4772 | "Overdrive sclk exceeds limit", |
| 4773 | hwmgr->gfx_arbiter.sclk_over_drive = hwmgr->platform_descriptor.overdriveLimit.engineClock); |
| 4774 | |
| 4775 | if (hwmgr->gfx_arbiter.sclk_over_drive >= hwmgr->gfx_arbiter.sclk) |
| 4776 | tonga_ps->performance_levels[1].engine_clock = hwmgr->gfx_arbiter.sclk_over_drive; |
| 4777 | } |
| 4778 | |
| 4779 | if (0 != hwmgr->gfx_arbiter.mclk_over_drive) { |
| 4780 | PP_ASSERT_WITH_CODE((hwmgr->gfx_arbiter.mclk_over_drive <= hwmgr->platform_descriptor.overdriveLimit.memoryClock), |
| 4781 | "Overdrive mclk exceeds limit", |
| 4782 | hwmgr->gfx_arbiter.mclk_over_drive = hwmgr->platform_descriptor.overdriveLimit.memoryClock); |
| 4783 | |
| 4784 | if (hwmgr->gfx_arbiter.mclk_over_drive >= hwmgr->gfx_arbiter.mclk) |
| 4785 | tonga_ps->performance_levels[1].memory_clock = hwmgr->gfx_arbiter.mclk_over_drive; |
| 4786 | } |
| 4787 | |
| 4788 | disable_mclk_switching_for_frame_lock = phm_cap_enabled( |
| 4789 | hwmgr->platform_descriptor.platformCaps, |
| 4790 | PHM_PlatformCaps_DisableMclkSwitchingForFrameLock); |
| 4791 | |
| 4792 | disable_mclk_switching = (1 < info.display_count) || |
| 4793 | disable_mclk_switching_for_frame_lock; |
| 4794 | |
| 4795 | sclk = tonga_ps->performance_levels[0].engine_clock; |
| 4796 | mclk = tonga_ps->performance_levels[0].memory_clock; |
| 4797 | |
| 4798 | if (disable_mclk_switching) |
| 4799 | mclk = tonga_ps->performance_levels[tonga_ps->performance_level_count - 1].memory_clock; |
| 4800 | |
| 4801 | if (sclk < minimum_clocks.engineClock) |
| 4802 | sclk = (minimum_clocks.engineClock > max_limits->sclk) ? max_limits->sclk : minimum_clocks.engineClock; |
| 4803 | |
| 4804 | if (mclk < minimum_clocks.memoryClock) |
| 4805 | mclk = (minimum_clocks.memoryClock > max_limits->mclk) ? max_limits->mclk : minimum_clocks.memoryClock; |
| 4806 | |
| 4807 | tonga_ps->performance_levels[0].engine_clock = sclk; |
| 4808 | tonga_ps->performance_levels[0].memory_clock = mclk; |
| 4809 | |
| 4810 | tonga_ps->performance_levels[1].engine_clock = |
| 4811 | (tonga_ps->performance_levels[1].engine_clock >= tonga_ps->performance_levels[0].engine_clock) ? |
| 4812 | tonga_ps->performance_levels[1].engine_clock : |
| 4813 | tonga_ps->performance_levels[0].engine_clock; |
| 4814 | |
| 4815 | if (disable_mclk_switching) { |
| 4816 | if (mclk < tonga_ps->performance_levels[1].memory_clock) |
| 4817 | mclk = tonga_ps->performance_levels[1].memory_clock; |
| 4818 | |
| 4819 | tonga_ps->performance_levels[0].memory_clock = mclk; |
| 4820 | tonga_ps->performance_levels[1].memory_clock = mclk; |
| 4821 | } else { |
| 4822 | if (tonga_ps->performance_levels[1].memory_clock < tonga_ps->performance_levels[0].memory_clock) |
| 4823 | tonga_ps->performance_levels[1].memory_clock = tonga_ps->performance_levels[0].memory_clock; |
| 4824 | } |
| 4825 | |
| 4826 | if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_StablePState)) { |
| 4827 | for (i=0; i < tonga_ps->performance_level_count; i++) { |
| 4828 | tonga_ps->performance_levels[i].engine_clock = stable_pstate_sclk; |
| 4829 | tonga_ps->performance_levels[i].memory_clock = stable_pstate_mclk; |
| 4830 | tonga_ps->performance_levels[i].pcie_gen = data->pcie_gen_performance.max; |
| 4831 | tonga_ps->performance_levels[i].pcie_lane = data->pcie_gen_performance.max; |
| 4832 | } |
| 4833 | } |
| 4834 | |
| 4835 | return 0; |
| 4836 | } |
| 4837 | |
| 4838 | int tonga_get_power_state_size(struct pp_hwmgr *hwmgr) |
| 4839 | { |
| 4840 | return sizeof(struct tonga_power_state); |
| 4841 | } |
| 4842 | |
| 4843 | static int tonga_dpm_get_mclk(struct pp_hwmgr *hwmgr, bool low) |
| 4844 | { |
| 4845 | struct pp_power_state *ps; |
| 4846 | struct tonga_power_state *tonga_ps; |
| 4847 | |
| 4848 | if (hwmgr == NULL) |
| 4849 | return -EINVAL; |
| 4850 | |
| 4851 | ps = hwmgr->request_ps; |
| 4852 | |
| 4853 | if (ps == NULL) |
| 4854 | return -EINVAL; |
| 4855 | |
| 4856 | tonga_ps = cast_phw_tonga_power_state(&ps->hardware); |
| 4857 | |
| 4858 | if (low) |
| 4859 | return tonga_ps->performance_levels[0].memory_clock; |
| 4860 | else |
| 4861 | return tonga_ps->performance_levels[tonga_ps->performance_level_count-1].memory_clock; |
| 4862 | } |
| 4863 | |
| 4864 | static int tonga_dpm_get_sclk(struct pp_hwmgr *hwmgr, bool low) |
| 4865 | { |
| 4866 | struct pp_power_state *ps; |
| 4867 | struct tonga_power_state *tonga_ps; |
| 4868 | |
| 4869 | if (hwmgr == NULL) |
| 4870 | return -EINVAL; |
| 4871 | |
| 4872 | ps = hwmgr->request_ps; |
| 4873 | |
| 4874 | if (ps == NULL) |
| 4875 | return -EINVAL; |
| 4876 | |
| 4877 | tonga_ps = cast_phw_tonga_power_state(&ps->hardware); |
| 4878 | |
| 4879 | if (low) |
| 4880 | return tonga_ps->performance_levels[0].engine_clock; |
| 4881 | else |
| 4882 | return tonga_ps->performance_levels[tonga_ps->performance_level_count-1].engine_clock; |
| 4883 | } |
| 4884 | |
| 4885 | static uint16_t tonga_get_current_pcie_speed( |
| 4886 | struct pp_hwmgr *hwmgr) |
| 4887 | { |
| 4888 | uint32_t speed_cntl = 0; |
| 4889 | |
| 4890 | speed_cntl = cgs_read_ind_register(hwmgr->device, |
| 4891 | CGS_IND_REG__PCIE, |
| 4892 | ixPCIE_LC_SPEED_CNTL); |
| 4893 | return((uint16_t)PHM_GET_FIELD(speed_cntl, |
| 4894 | PCIE_LC_SPEED_CNTL, LC_CURRENT_DATA_RATE)); |
| 4895 | } |
| 4896 | |
| 4897 | static int tonga_get_current_pcie_lane_number( |
| 4898 | struct pp_hwmgr *hwmgr) |
| 4899 | { |
| 4900 | uint32_t link_width; |
| 4901 | |
| 4902 | link_width = PHM_READ_INDIRECT_FIELD(hwmgr->device, |
| 4903 | CGS_IND_REG__PCIE, |
| 4904 | PCIE_LC_LINK_WIDTH_CNTL, |
| 4905 | LC_LINK_WIDTH_RD); |
| 4906 | |
| 4907 | PP_ASSERT_WITH_CODE((7 >= link_width), |
| 4908 | "Invalid PCIe lane width!", return 0); |
| 4909 | |
| 4910 | return decode_pcie_lane_width(link_width); |
| 4911 | } |
| 4912 | |
| 4913 | static int tonga_dpm_patch_boot_state(struct pp_hwmgr *hwmgr, |
| 4914 | struct pp_hw_power_state *hw_ps) |
| 4915 | { |
| 4916 | struct tonga_hwmgr *data = (struct tonga_hwmgr *)(hwmgr->backend); |
| 4917 | struct tonga_power_state *ps = (struct tonga_power_state *)hw_ps; |
| 4918 | ATOM_FIRMWARE_INFO_V2_2 *fw_info; |
| 4919 | uint16_t size; |
| 4920 | uint8_t frev, crev; |
| 4921 | int index = GetIndexIntoMasterTable(DATA, FirmwareInfo); |
| 4922 | |
| 4923 | /* First retrieve the Boot clocks and VDDC from the firmware info table. |
| 4924 | * We assume here that fw_info is unchanged if this call fails. |
| 4925 | */ |
| 4926 | fw_info = (ATOM_FIRMWARE_INFO_V2_2 *)cgs_atom_get_data_table( |
| 4927 | hwmgr->device, index, |
| 4928 | &size, &frev, &crev); |
| 4929 | if (!fw_info) |
| 4930 | /* During a test, there is no firmware info table. */ |
| 4931 | return 0; |
| 4932 | |
| 4933 | /* Patch the state. */ |
| 4934 | data->vbios_boot_state.sclk_bootup_value = le32_to_cpu(fw_info->ulDefaultEngineClock); |
| 4935 | data->vbios_boot_state.mclk_bootup_value = le32_to_cpu(fw_info->ulDefaultMemoryClock); |
| 4936 | data->vbios_boot_state.mvdd_bootup_value = le16_to_cpu(fw_info->usBootUpMVDDCVoltage); |
| 4937 | data->vbios_boot_state.vddc_bootup_value = le16_to_cpu(fw_info->usBootUpVDDCVoltage); |
| 4938 | data->vbios_boot_state.vddci_bootup_value = le16_to_cpu(fw_info->usBootUpVDDCIVoltage); |
| 4939 | data->vbios_boot_state.pcie_gen_bootup_value = tonga_get_current_pcie_speed(hwmgr); |
| 4940 | data->vbios_boot_state.pcie_lane_bootup_value = |
| 4941 | (uint16_t)tonga_get_current_pcie_lane_number(hwmgr); |
| 4942 | |
| 4943 | /* set boot power state */ |
| 4944 | ps->performance_levels[0].memory_clock = data->vbios_boot_state.mclk_bootup_value; |
| 4945 | ps->performance_levels[0].engine_clock = data->vbios_boot_state.sclk_bootup_value; |
| 4946 | ps->performance_levels[0].pcie_gen = data->vbios_boot_state.pcie_gen_bootup_value; |
| 4947 | ps->performance_levels[0].pcie_lane = data->vbios_boot_state.pcie_lane_bootup_value; |
| 4948 | |
| 4949 | return 0; |
| 4950 | } |
| 4951 | |
| 4952 | static int tonga_get_pp_table_entry_callback_func(struct pp_hwmgr *hwmgr, |
| 4953 | void *state, struct pp_power_state *power_state, |
| 4954 | void *pp_table, uint32_t classification_flag) |
| 4955 | { |
| 4956 | struct tonga_hwmgr *data = (struct tonga_hwmgr *)(hwmgr->backend); |
| 4957 | |
| 4958 | struct tonga_power_state *tonga_ps = |
| 4959 | (struct tonga_power_state *)(&(power_state->hardware)); |
| 4960 | |
| 4961 | struct tonga_performance_level *performance_level; |
| 4962 | |
| 4963 | ATOM_Tonga_State *state_entry = (ATOM_Tonga_State *)state; |
| 4964 | |
| 4965 | ATOM_Tonga_POWERPLAYTABLE *powerplay_table = |
| 4966 | (ATOM_Tonga_POWERPLAYTABLE *)pp_table; |
| 4967 | |
| 4968 | ATOM_Tonga_SCLK_Dependency_Table *sclk_dep_table = |
| 4969 | (ATOM_Tonga_SCLK_Dependency_Table *) |
Rex Zhu | c9fe74e | 2015-11-16 11:24:35 +0800 | [diff] [blame] | 4970 | (((unsigned long)powerplay_table) + |
yanyang1 | c82baa2 | 2015-08-18 15:28:32 +0800 | [diff] [blame] | 4971 | le16_to_cpu(powerplay_table->usSclkDependencyTableOffset)); |
| 4972 | |
| 4973 | ATOM_Tonga_MCLK_Dependency_Table *mclk_dep_table = |
| 4974 | (ATOM_Tonga_MCLK_Dependency_Table *) |
Rex Zhu | c9fe74e | 2015-11-16 11:24:35 +0800 | [diff] [blame] | 4975 | (((unsigned long)powerplay_table) + |
yanyang1 | c82baa2 | 2015-08-18 15:28:32 +0800 | [diff] [blame] | 4976 | le16_to_cpu(powerplay_table->usMclkDependencyTableOffset)); |
| 4977 | |
| 4978 | /* The following fields are not initialized here: id orderedList allStatesList */ |
| 4979 | power_state->classification.ui_label = |
| 4980 | (le16_to_cpu(state_entry->usClassification) & |
| 4981 | ATOM_PPLIB_CLASSIFICATION_UI_MASK) >> |
| 4982 | ATOM_PPLIB_CLASSIFICATION_UI_SHIFT; |
| 4983 | power_state->classification.flags = classification_flag; |
| 4984 | /* NOTE: There is a classification2 flag in BIOS that is not being used right now */ |
| 4985 | |
| 4986 | power_state->classification.temporary_state = false; |
| 4987 | power_state->classification.to_be_deleted = false; |
| 4988 | |
| 4989 | power_state->validation.disallowOnDC = |
| 4990 | (0 != (le32_to_cpu(state_entry->ulCapsAndSettings) & ATOM_Tonga_DISALLOW_ON_DC)); |
| 4991 | |
| 4992 | power_state->pcie.lanes = 0; |
| 4993 | |
| 4994 | power_state->display.disableFrameModulation = false; |
| 4995 | power_state->display.limitRefreshrate = false; |
| 4996 | power_state->display.enableVariBright = |
| 4997 | (0 != (le32_to_cpu(state_entry->ulCapsAndSettings) & ATOM_Tonga_ENABLE_VARIBRIGHT)); |
| 4998 | |
| 4999 | power_state->validation.supportedPowerLevels = 0; |
| 5000 | power_state->uvd_clocks.VCLK = 0; |
| 5001 | power_state->uvd_clocks.DCLK = 0; |
| 5002 | power_state->temperatures.min = 0; |
| 5003 | power_state->temperatures.max = 0; |
| 5004 | |
| 5005 | performance_level = &(tonga_ps->performance_levels |
| 5006 | [tonga_ps->performance_level_count++]); |
| 5007 | |
| 5008 | PP_ASSERT_WITH_CODE( |
| 5009 | (tonga_ps->performance_level_count < SMU72_MAX_LEVELS_GRAPHICS), |
| 5010 | "Performance levels exceeds SMC limit!", |
| 5011 | return -1); |
| 5012 | |
| 5013 | PP_ASSERT_WITH_CODE( |
| 5014 | (tonga_ps->performance_level_count <= |
| 5015 | hwmgr->platform_descriptor.hardwareActivityPerformanceLevels), |
| 5016 | "Performance levels exceeds Driver limit!", |
| 5017 | return -1); |
| 5018 | |
| 5019 | /* Performance levels are arranged from low to high. */ |
| 5020 | performance_level->memory_clock = |
| 5021 | le32_to_cpu(mclk_dep_table->entries[state_entry->ucMemoryClockIndexLow].ulMclk); |
| 5022 | |
| 5023 | performance_level->engine_clock = |
| 5024 | le32_to_cpu(sclk_dep_table->entries[state_entry->ucEngineClockIndexLow].ulSclk); |
| 5025 | |
| 5026 | performance_level->pcie_gen = get_pcie_gen_support( |
| 5027 | data->pcie_gen_cap, |
| 5028 | state_entry->ucPCIEGenLow); |
| 5029 | |
| 5030 | performance_level->pcie_lane = get_pcie_lane_support( |
| 5031 | data->pcie_lane_cap, |
| 5032 | state_entry->ucPCIELaneHigh); |
| 5033 | |
| 5034 | performance_level = |
| 5035 | &(tonga_ps->performance_levels[tonga_ps->performance_level_count++]); |
| 5036 | |
| 5037 | performance_level->memory_clock = |
| 5038 | le32_to_cpu(mclk_dep_table->entries[state_entry->ucMemoryClockIndexHigh].ulMclk); |
| 5039 | |
| 5040 | performance_level->engine_clock = |
| 5041 | le32_to_cpu(sclk_dep_table->entries[state_entry->ucEngineClockIndexHigh].ulSclk); |
| 5042 | |
| 5043 | performance_level->pcie_gen = get_pcie_gen_support( |
| 5044 | data->pcie_gen_cap, |
| 5045 | state_entry->ucPCIEGenHigh); |
| 5046 | |
| 5047 | performance_level->pcie_lane = get_pcie_lane_support( |
| 5048 | data->pcie_lane_cap, |
| 5049 | state_entry->ucPCIELaneHigh); |
| 5050 | |
| 5051 | return 0; |
| 5052 | } |
| 5053 | |
| 5054 | static int tonga_get_pp_table_entry(struct pp_hwmgr *hwmgr, |
| 5055 | unsigned long entry_index, struct pp_power_state *ps) |
| 5056 | { |
| 5057 | int result; |
| 5058 | struct tonga_power_state *tonga_ps; |
| 5059 | struct tonga_hwmgr *data = (struct tonga_hwmgr *)(hwmgr->backend); |
| 5060 | |
| 5061 | struct phm_ppt_v1_information *table_info = |
| 5062 | (struct phm_ppt_v1_information *)(hwmgr->pptable); |
| 5063 | |
| 5064 | struct phm_ppt_v1_clock_voltage_dependency_table *dep_mclk_table = |
| 5065 | table_info->vdd_dep_on_mclk; |
| 5066 | |
| 5067 | ps->hardware.magic = PhwTonga_Magic; |
| 5068 | |
| 5069 | tonga_ps = cast_phw_tonga_power_state(&(ps->hardware)); |
| 5070 | |
| 5071 | result = tonga_get_powerplay_table_entry(hwmgr, entry_index, ps, |
| 5072 | tonga_get_pp_table_entry_callback_func); |
| 5073 | |
| 5074 | /* This is the earliest time we have all the dependency table and the VBIOS boot state |
| 5075 | * as PP_Tables_GetPowerPlayTableEntry retrieves the VBIOS boot state |
| 5076 | * if there is only one VDDCI/MCLK level, check if it's the same as VBIOS boot state |
| 5077 | */ |
| 5078 | if (dep_mclk_table != NULL && dep_mclk_table->count == 1) { |
| 5079 | if (dep_mclk_table->entries[0].clk != |
| 5080 | data->vbios_boot_state.mclk_bootup_value) |
| 5081 | printk(KERN_ERR "Single MCLK entry VDDCI/MCLK dependency table " |
| 5082 | "does not match VBIOS boot MCLK level"); |
| 5083 | if (dep_mclk_table->entries[0].vddci != |
| 5084 | data->vbios_boot_state.vddci_bootup_value) |
| 5085 | printk(KERN_ERR "Single VDDCI entry VDDCI/MCLK dependency table " |
| 5086 | "does not match VBIOS boot VDDCI level"); |
| 5087 | } |
| 5088 | |
| 5089 | /* set DC compatible flag if this state supports DC */ |
| 5090 | if (!ps->validation.disallowOnDC) |
| 5091 | tonga_ps->dc_compatible = true; |
| 5092 | |
| 5093 | if (ps->classification.flags & PP_StateClassificationFlag_ACPI) |
| 5094 | data->acpi_pcie_gen = tonga_ps->performance_levels[0].pcie_gen; |
| 5095 | else if (ps->classification.flags & PP_StateClassificationFlag_Boot) { |
| 5096 | if (data->bacos.best_match == 0xffff) { |
| 5097 | /* For V.I. use boot state as base BACO state */ |
| 5098 | data->bacos.best_match = PP_StateClassificationFlag_Boot; |
| 5099 | data->bacos.performance_level = tonga_ps->performance_levels[0]; |
| 5100 | } |
| 5101 | } |
| 5102 | |
| 5103 | tonga_ps->uvd_clocks.VCLK = ps->uvd_clocks.VCLK; |
| 5104 | tonga_ps->uvd_clocks.DCLK = ps->uvd_clocks.DCLK; |
| 5105 | |
| 5106 | if (!result) { |
| 5107 | uint32_t i; |
| 5108 | |
| 5109 | switch (ps->classification.ui_label) { |
| 5110 | case PP_StateUILabel_Performance: |
| 5111 | data->use_pcie_performance_levels = true; |
| 5112 | |
| 5113 | for (i = 0; i < tonga_ps->performance_level_count; i++) { |
| 5114 | if (data->pcie_gen_performance.max < |
| 5115 | tonga_ps->performance_levels[i].pcie_gen) |
| 5116 | data->pcie_gen_performance.max = |
| 5117 | tonga_ps->performance_levels[i].pcie_gen; |
| 5118 | |
| 5119 | if (data->pcie_gen_performance.min > |
| 5120 | tonga_ps->performance_levels[i].pcie_gen) |
| 5121 | data->pcie_gen_performance.min = |
| 5122 | tonga_ps->performance_levels[i].pcie_gen; |
| 5123 | |
| 5124 | if (data->pcie_lane_performance.max < |
| 5125 | tonga_ps->performance_levels[i].pcie_lane) |
| 5126 | data->pcie_lane_performance.max = |
| 5127 | tonga_ps->performance_levels[i].pcie_lane; |
| 5128 | |
| 5129 | if (data->pcie_lane_performance.min > |
| 5130 | tonga_ps->performance_levels[i].pcie_lane) |
| 5131 | data->pcie_lane_performance.min = |
| 5132 | tonga_ps->performance_levels[i].pcie_lane; |
| 5133 | } |
| 5134 | break; |
| 5135 | case PP_StateUILabel_Battery: |
| 5136 | data->use_pcie_power_saving_levels = true; |
| 5137 | |
| 5138 | for (i = 0; i < tonga_ps->performance_level_count; i++) { |
| 5139 | if (data->pcie_gen_power_saving.max < |
| 5140 | tonga_ps->performance_levels[i].pcie_gen) |
| 5141 | data->pcie_gen_power_saving.max = |
| 5142 | tonga_ps->performance_levels[i].pcie_gen; |
| 5143 | |
| 5144 | if (data->pcie_gen_power_saving.min > |
| 5145 | tonga_ps->performance_levels[i].pcie_gen) |
| 5146 | data->pcie_gen_power_saving.min = |
| 5147 | tonga_ps->performance_levels[i].pcie_gen; |
| 5148 | |
| 5149 | if (data->pcie_lane_power_saving.max < |
| 5150 | tonga_ps->performance_levels[i].pcie_lane) |
| 5151 | data->pcie_lane_power_saving.max = |
| 5152 | tonga_ps->performance_levels[i].pcie_lane; |
| 5153 | |
| 5154 | if (data->pcie_lane_power_saving.min > |
| 5155 | tonga_ps->performance_levels[i].pcie_lane) |
| 5156 | data->pcie_lane_power_saving.min = |
| 5157 | tonga_ps->performance_levels[i].pcie_lane; |
| 5158 | } |
| 5159 | break; |
| 5160 | default: |
| 5161 | break; |
| 5162 | } |
| 5163 | } |
| 5164 | return 0; |
| 5165 | } |
| 5166 | |
| 5167 | static void |
| 5168 | tonga_print_current_perforce_level(struct pp_hwmgr *hwmgr, struct seq_file *m) |
| 5169 | { |
Rex Zhu | ab4f4b1 | 2016-01-06 17:17:53 +0800 | [diff] [blame] | 5170 | uint32_t sclk, mclk, activity_percent; |
Rex Zhu | 9c5f8de | 2015-12-08 14:31:13 +0800 | [diff] [blame] | 5171 | uint32_t offset; |
| 5172 | struct tonga_hwmgr *data = (struct tonga_hwmgr *)(hwmgr->backend); |
yanyang1 | c82baa2 | 2015-08-18 15:28:32 +0800 | [diff] [blame] | 5173 | |
| 5174 | smum_send_msg_to_smc(hwmgr->smumgr, (PPSMC_Msg)(PPSMC_MSG_API_GetSclkFrequency)); |
| 5175 | |
| 5176 | sclk = cgs_read_register(hwmgr->device, mmSMC_MSG_ARG_0); |
| 5177 | |
| 5178 | smum_send_msg_to_smc(hwmgr->smumgr, (PPSMC_Msg)(PPSMC_MSG_API_GetMclkFrequency)); |
| 5179 | |
| 5180 | mclk = cgs_read_register(hwmgr->device, mmSMC_MSG_ARG_0); |
| 5181 | seq_printf(m, "\n [ mclk ]: %u MHz\n\n [ sclk ]: %u MHz\n", mclk/100, sclk/100); |
Rex Zhu | 9c5f8de | 2015-12-08 14:31:13 +0800 | [diff] [blame] | 5182 | |
Rex Zhu | 9c5f8de | 2015-12-08 14:31:13 +0800 | [diff] [blame] | 5183 | offset = data->soft_regs_start + offsetof(SMU72_SoftRegisters, AverageGraphicsActivity); |
Rex Zhu | ab4f4b1 | 2016-01-06 17:17:53 +0800 | [diff] [blame] | 5184 | activity_percent = cgs_read_ind_register(hwmgr->device, CGS_IND_REG__SMC, offset); |
| 5185 | activity_percent += 0x80; |
| 5186 | activity_percent >>= 8; |
Rex Zhu | 9c5f8de | 2015-12-08 14:31:13 +0800 | [diff] [blame] | 5187 | |
Rex Zhu | ab4f4b1 | 2016-01-06 17:17:53 +0800 | [diff] [blame] | 5188 | seq_printf(m, "\n [GPU load]: %u%%\n\n", activity_percent > 100 ? 100 : activity_percent); |
Rex Zhu | 9c5f8de | 2015-12-08 14:31:13 +0800 | [diff] [blame] | 5189 | |
Rex Zhu | d27d494 | 2016-03-01 17:04:12 +0800 | [diff] [blame] | 5190 | seq_printf(m, "uvd %sabled\n", data->uvd_power_gated ? "dis" : "en"); |
| 5191 | |
| 5192 | seq_printf(m, "vce %sabled\n", data->vce_power_gated ? "dis" : "en"); |
yanyang1 | c82baa2 | 2015-08-18 15:28:32 +0800 | [diff] [blame] | 5193 | } |
| 5194 | |
| 5195 | static int tonga_find_dpm_states_clocks_in_dpm_table(struct pp_hwmgr *hwmgr, const void *input) |
| 5196 | { |
| 5197 | const struct phm_set_power_state_input *states = (const struct phm_set_power_state_input *)input; |
| 5198 | const struct tonga_power_state *tonga_ps = cast_const_phw_tonga_power_state(states->pnew_state); |
| 5199 | struct tonga_hwmgr *data = (struct tonga_hwmgr *)(hwmgr->backend); |
| 5200 | struct tonga_single_dpm_table *psclk_table = &(data->dpm_table.sclk_table); |
| 5201 | uint32_t sclk = tonga_ps->performance_levels[tonga_ps->performance_level_count-1].engine_clock; |
| 5202 | struct tonga_single_dpm_table *pmclk_table = &(data->dpm_table.mclk_table); |
| 5203 | uint32_t mclk = tonga_ps->performance_levels[tonga_ps->performance_level_count-1].memory_clock; |
| 5204 | struct PP_Clocks min_clocks = {0}; |
| 5205 | uint32_t i; |
| 5206 | struct cgs_display_info info = {0}; |
| 5207 | |
| 5208 | data->need_update_smu7_dpm_table = 0; |
| 5209 | |
| 5210 | for (i = 0; i < psclk_table->count; i++) { |
| 5211 | if (sclk == psclk_table->dpm_levels[i].value) |
| 5212 | break; |
| 5213 | } |
| 5214 | |
| 5215 | if (i >= psclk_table->count) |
| 5216 | data->need_update_smu7_dpm_table |= DPMTABLE_OD_UPDATE_SCLK; |
| 5217 | else { |
| 5218 | /* TODO: Check SCLK in DAL's minimum clocks in case DeepSleep divider update is required.*/ |
| 5219 | if(data->display_timing.min_clock_insr != min_clocks.engineClockInSR) |
| 5220 | data->need_update_smu7_dpm_table |= DPMTABLE_UPDATE_SCLK; |
| 5221 | } |
| 5222 | |
| 5223 | for (i=0; i < pmclk_table->count; i++) { |
| 5224 | if (mclk == pmclk_table->dpm_levels[i].value) |
| 5225 | break; |
| 5226 | } |
| 5227 | |
| 5228 | if (i >= pmclk_table->count) |
| 5229 | data->need_update_smu7_dpm_table |= DPMTABLE_OD_UPDATE_MCLK; |
| 5230 | |
| 5231 | cgs_get_active_displays_info(hwmgr->device, &info); |
| 5232 | |
| 5233 | if (data->display_timing.num_existing_displays != info.display_count) |
| 5234 | data->need_update_smu7_dpm_table |= DPMTABLE_UPDATE_MCLK; |
| 5235 | |
| 5236 | return 0; |
| 5237 | } |
| 5238 | |
| 5239 | static uint16_t tonga_get_maximum_link_speed(struct pp_hwmgr *hwmgr, const struct tonga_power_state *hw_ps) |
| 5240 | { |
| 5241 | uint32_t i; |
| 5242 | uint32_t sclk, max_sclk = 0; |
| 5243 | struct tonga_hwmgr *data = (struct tonga_hwmgr *)(hwmgr->backend); |
| 5244 | struct tonga_dpm_table *pdpm_table = &data->dpm_table; |
| 5245 | |
| 5246 | for (i = 0; i < hw_ps->performance_level_count; i++) { |
| 5247 | sclk = hw_ps->performance_levels[i].engine_clock; |
| 5248 | if (max_sclk < sclk) |
| 5249 | max_sclk = sclk; |
| 5250 | } |
| 5251 | |
| 5252 | for (i = 0; i < pdpm_table->sclk_table.count; i++) { |
| 5253 | if (pdpm_table->sclk_table.dpm_levels[i].value == max_sclk) |
| 5254 | return (uint16_t) ((i >= pdpm_table->pcie_speed_table.count) ? |
| 5255 | pdpm_table->pcie_speed_table.dpm_levels[pdpm_table->pcie_speed_table.count-1].value : |
| 5256 | pdpm_table->pcie_speed_table.dpm_levels[i].value); |
| 5257 | } |
| 5258 | |
| 5259 | return 0; |
| 5260 | } |
| 5261 | |
| 5262 | static int tonga_request_link_speed_change_before_state_change(struct pp_hwmgr *hwmgr, const void *input) |
| 5263 | { |
| 5264 | const struct phm_set_power_state_input *states = (const struct phm_set_power_state_input *)input; |
| 5265 | struct tonga_hwmgr *data = (struct tonga_hwmgr *)(hwmgr->backend); |
| 5266 | const struct tonga_power_state *tonga_nps = cast_const_phw_tonga_power_state(states->pnew_state); |
| 5267 | const struct tonga_power_state *tonga_cps = cast_const_phw_tonga_power_state(states->pcurrent_state); |
| 5268 | |
| 5269 | uint16_t target_link_speed = tonga_get_maximum_link_speed(hwmgr, tonga_nps); |
| 5270 | uint16_t current_link_speed; |
| 5271 | |
| 5272 | if (data->force_pcie_gen == PP_PCIEGenInvalid) |
| 5273 | current_link_speed = tonga_get_maximum_link_speed(hwmgr, tonga_cps); |
| 5274 | else |
| 5275 | current_link_speed = data->force_pcie_gen; |
| 5276 | |
| 5277 | data->force_pcie_gen = PP_PCIEGenInvalid; |
| 5278 | data->pspp_notify_required = false; |
| 5279 | if (target_link_speed > current_link_speed) { |
| 5280 | switch(target_link_speed) { |
| 5281 | case PP_PCIEGen3: |
| 5282 | if (0 == acpi_pcie_perf_request(hwmgr->device, PCIE_PERF_REQ_GEN3, false)) |
| 5283 | break; |
| 5284 | data->force_pcie_gen = PP_PCIEGen2; |
| 5285 | if (current_link_speed == PP_PCIEGen2) |
| 5286 | break; |
| 5287 | case PP_PCIEGen2: |
| 5288 | if (0 == acpi_pcie_perf_request(hwmgr->device, PCIE_PERF_REQ_GEN2, false)) |
| 5289 | break; |
| 5290 | default: |
| 5291 | data->force_pcie_gen = tonga_get_current_pcie_speed(hwmgr); |
| 5292 | break; |
| 5293 | } |
| 5294 | } else { |
| 5295 | if (target_link_speed < current_link_speed) |
| 5296 | data->pspp_notify_required = true; |
| 5297 | } |
| 5298 | |
| 5299 | return 0; |
| 5300 | } |
| 5301 | |
| 5302 | static int tonga_freeze_sclk_mclk_dpm(struct pp_hwmgr *hwmgr) |
| 5303 | { |
| 5304 | struct tonga_hwmgr *data = (struct tonga_hwmgr *)(hwmgr->backend); |
| 5305 | |
| 5306 | if (0 == data->need_update_smu7_dpm_table) |
| 5307 | return 0; |
| 5308 | |
| 5309 | if ((0 == data->sclk_dpm_key_disabled) && |
| 5310 | (data->need_update_smu7_dpm_table & |
| 5311 | (DPMTABLE_OD_UPDATE_SCLK + DPMTABLE_UPDATE_SCLK))) { |
Edward O'Callaghan | 4ba27f9 | 2016-07-12 10:17:56 +1000 | [diff] [blame] | 5312 | PP_ASSERT_WITH_CODE(!tonga_is_dpm_running(hwmgr), |
| 5313 | "Trying to freeze SCLK DPM when DPM is disabled", |
yanyang1 | c82baa2 | 2015-08-18 15:28:32 +0800 | [diff] [blame] | 5314 | ); |
| 5315 | PP_ASSERT_WITH_CODE( |
| 5316 | 0 == smum_send_msg_to_smc(hwmgr->smumgr, |
| 5317 | PPSMC_MSG_SCLKDPM_FreezeLevel), |
| 5318 | "Failed to freeze SCLK DPM during FreezeSclkMclkDPM Function!", |
| 5319 | return -1); |
| 5320 | } |
| 5321 | |
| 5322 | if ((0 == data->mclk_dpm_key_disabled) && |
| 5323 | (data->need_update_smu7_dpm_table & |
| 5324 | DPMTABLE_OD_UPDATE_MCLK)) { |
Edward O'Callaghan | 4ba27f9 | 2016-07-12 10:17:56 +1000 | [diff] [blame] | 5325 | PP_ASSERT_WITH_CODE(!tonga_is_dpm_running(hwmgr), |
| 5326 | "Trying to freeze MCLK DPM when DPM is disabled", |
yanyang1 | c82baa2 | 2015-08-18 15:28:32 +0800 | [diff] [blame] | 5327 | ); |
| 5328 | PP_ASSERT_WITH_CODE( |
| 5329 | 0 == smum_send_msg_to_smc(hwmgr->smumgr, |
| 5330 | PPSMC_MSG_MCLKDPM_FreezeLevel), |
| 5331 | "Failed to freeze MCLK DPM during FreezeSclkMclkDPM Function!", |
| 5332 | return -1); |
| 5333 | } |
| 5334 | |
| 5335 | return 0; |
| 5336 | } |
| 5337 | |
| 5338 | static int tonga_populate_and_upload_sclk_mclk_dpm_levels(struct pp_hwmgr *hwmgr, const void *input) |
| 5339 | { |
| 5340 | int result = 0; |
| 5341 | |
| 5342 | const struct phm_set_power_state_input *states = (const struct phm_set_power_state_input *)input; |
| 5343 | const struct tonga_power_state *tonga_ps = cast_const_phw_tonga_power_state(states->pnew_state); |
| 5344 | struct tonga_hwmgr *data = (struct tonga_hwmgr *)(hwmgr->backend); |
| 5345 | uint32_t sclk = tonga_ps->performance_levels[tonga_ps->performance_level_count-1].engine_clock; |
| 5346 | uint32_t mclk = tonga_ps->performance_levels[tonga_ps->performance_level_count-1].memory_clock; |
| 5347 | struct tonga_dpm_table *pdpm_table = &data->dpm_table; |
| 5348 | |
| 5349 | struct tonga_dpm_table *pgolden_dpm_table = &data->golden_dpm_table; |
| 5350 | uint32_t dpm_count, clock_percent; |
| 5351 | uint32_t i; |
| 5352 | |
| 5353 | if (0 == data->need_update_smu7_dpm_table) |
| 5354 | return 0; |
| 5355 | |
| 5356 | if (data->need_update_smu7_dpm_table & DPMTABLE_OD_UPDATE_SCLK) { |
| 5357 | pdpm_table->sclk_table.dpm_levels[pdpm_table->sclk_table.count-1].value = sclk; |
| 5358 | |
| 5359 | if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_OD6PlusinACSupport) || |
| 5360 | phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_OD6PlusinDCSupport)) { |
| 5361 | /* Need to do calculation based on the golden DPM table |
| 5362 | * as the Heatmap GPU Clock axis is also based on the default values |
| 5363 | */ |
| 5364 | PP_ASSERT_WITH_CODE( |
| 5365 | (pgolden_dpm_table->sclk_table.dpm_levels[pgolden_dpm_table->sclk_table.count-1].value != 0), |
| 5366 | "Divide by 0!", |
| 5367 | return -1); |
| 5368 | dpm_count = pdpm_table->sclk_table.count < 2 ? 0 : pdpm_table->sclk_table.count-2; |
| 5369 | for (i = dpm_count; i > 1; i--) { |
| 5370 | if (sclk > pgolden_dpm_table->sclk_table.dpm_levels[pgolden_dpm_table->sclk_table.count-1].value) { |
| 5371 | clock_percent = ((sclk - pgolden_dpm_table->sclk_table.dpm_levels[pgolden_dpm_table->sclk_table.count-1].value)*100) / |
| 5372 | pgolden_dpm_table->sclk_table.dpm_levels[pgolden_dpm_table->sclk_table.count-1].value; |
| 5373 | |
| 5374 | pdpm_table->sclk_table.dpm_levels[i].value = |
| 5375 | pgolden_dpm_table->sclk_table.dpm_levels[i].value + |
| 5376 | (pgolden_dpm_table->sclk_table.dpm_levels[i].value * clock_percent)/100; |
| 5377 | |
| 5378 | } else if (pgolden_dpm_table->sclk_table.dpm_levels[pdpm_table->sclk_table.count-1].value > sclk) { |
| 5379 | clock_percent = ((pgolden_dpm_table->sclk_table.dpm_levels[pgolden_dpm_table->sclk_table.count-1].value - sclk)*100) / |
| 5380 | pgolden_dpm_table->sclk_table.dpm_levels[pgolden_dpm_table->sclk_table.count-1].value; |
| 5381 | |
| 5382 | pdpm_table->sclk_table.dpm_levels[i].value = |
| 5383 | pgolden_dpm_table->sclk_table.dpm_levels[i].value - |
| 5384 | (pgolden_dpm_table->sclk_table.dpm_levels[i].value * clock_percent)/100; |
| 5385 | } else |
| 5386 | pdpm_table->sclk_table.dpm_levels[i].value = |
| 5387 | pgolden_dpm_table->sclk_table.dpm_levels[i].value; |
| 5388 | } |
| 5389 | } |
| 5390 | } |
| 5391 | |
| 5392 | if (data->need_update_smu7_dpm_table & DPMTABLE_OD_UPDATE_MCLK) { |
| 5393 | pdpm_table->mclk_table.dpm_levels[pdpm_table->mclk_table.count-1].value = mclk; |
| 5394 | |
| 5395 | if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_OD6PlusinACSupport) || |
| 5396 | phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_OD6PlusinDCSupport)) { |
| 5397 | |
| 5398 | PP_ASSERT_WITH_CODE( |
| 5399 | (pgolden_dpm_table->mclk_table.dpm_levels[pgolden_dpm_table->mclk_table.count-1].value != 0), |
| 5400 | "Divide by 0!", |
| 5401 | return -1); |
| 5402 | dpm_count = pdpm_table->mclk_table.count < 2? 0 : pdpm_table->mclk_table.count-2; |
| 5403 | for (i = dpm_count; i > 1; i--) { |
| 5404 | if (mclk > pgolden_dpm_table->mclk_table.dpm_levels[pgolden_dpm_table->mclk_table.count-1].value) { |
| 5405 | clock_percent = ((mclk - pgolden_dpm_table->mclk_table.dpm_levels[pgolden_dpm_table->mclk_table.count-1].value)*100) / |
| 5406 | pgolden_dpm_table->mclk_table.dpm_levels[pgolden_dpm_table->mclk_table.count-1].value; |
| 5407 | |
| 5408 | pdpm_table->mclk_table.dpm_levels[i].value = |
| 5409 | pgolden_dpm_table->mclk_table.dpm_levels[i].value + |
| 5410 | (pgolden_dpm_table->mclk_table.dpm_levels[i].value * clock_percent)/100; |
| 5411 | |
| 5412 | } else if (pgolden_dpm_table->mclk_table.dpm_levels[pdpm_table->mclk_table.count-1].value > mclk) { |
| 5413 | clock_percent = ((pgolden_dpm_table->mclk_table.dpm_levels[pgolden_dpm_table->mclk_table.count-1].value - mclk)*100) / |
| 5414 | pgolden_dpm_table->mclk_table.dpm_levels[pgolden_dpm_table->mclk_table.count-1].value; |
| 5415 | |
| 5416 | pdpm_table->mclk_table.dpm_levels[i].value = |
| 5417 | pgolden_dpm_table->mclk_table.dpm_levels[i].value - |
| 5418 | (pgolden_dpm_table->mclk_table.dpm_levels[i].value * clock_percent)/100; |
| 5419 | } else |
| 5420 | pdpm_table->mclk_table.dpm_levels[i].value = pgolden_dpm_table->mclk_table.dpm_levels[i].value; |
| 5421 | } |
| 5422 | } |
| 5423 | } |
| 5424 | |
| 5425 | if (data->need_update_smu7_dpm_table & (DPMTABLE_OD_UPDATE_SCLK + DPMTABLE_UPDATE_SCLK)) { |
Eric Huang | e2ed8a1 | 2016-05-12 14:41:04 -0400 | [diff] [blame] | 5426 | result = tonga_populate_all_graphic_levels(hwmgr); |
yanyang1 | c82baa2 | 2015-08-18 15:28:32 +0800 | [diff] [blame] | 5427 | PP_ASSERT_WITH_CODE((0 == result), |
| 5428 | "Failed to populate SCLK during PopulateNewDPMClocksStates Function!", |
| 5429 | return result); |
| 5430 | } |
| 5431 | |
| 5432 | if (data->need_update_smu7_dpm_table & (DPMTABLE_OD_UPDATE_MCLK + DPMTABLE_UPDATE_MCLK)) { |
| 5433 | /*populate MCLK dpm table to SMU7 */ |
| 5434 | result = tonga_populate_all_memory_levels(hwmgr); |
| 5435 | PP_ASSERT_WITH_CODE((0 == result), |
| 5436 | "Failed to populate MCLK during PopulateNewDPMClocksStates Function!", |
| 5437 | return result); |
| 5438 | } |
| 5439 | |
| 5440 | return result; |
| 5441 | } |
| 5442 | |
| 5443 | static int tonga_trim_single_dpm_states(struct pp_hwmgr *hwmgr, |
| 5444 | struct tonga_single_dpm_table * pdpm_table, |
| 5445 | uint32_t low_limit, uint32_t high_limit) |
| 5446 | { |
| 5447 | uint32_t i; |
| 5448 | |
| 5449 | for (i = 0; i < pdpm_table->count; i++) { |
| 5450 | if ((pdpm_table->dpm_levels[i].value < low_limit) || |
| 5451 | (pdpm_table->dpm_levels[i].value > high_limit)) |
| 5452 | pdpm_table->dpm_levels[i].enabled = false; |
| 5453 | else |
| 5454 | pdpm_table->dpm_levels[i].enabled = true; |
| 5455 | } |
| 5456 | return 0; |
| 5457 | } |
| 5458 | |
| 5459 | static int tonga_trim_dpm_states(struct pp_hwmgr *hwmgr, const struct tonga_power_state *hw_state) |
| 5460 | { |
yanyang1 | c82baa2 | 2015-08-18 15:28:32 +0800 | [diff] [blame] | 5461 | struct tonga_hwmgr *data = (struct tonga_hwmgr *)(hwmgr->backend); |
| 5462 | uint32_t high_limit_count; |
| 5463 | |
| 5464 | PP_ASSERT_WITH_CODE((hw_state->performance_level_count >= 1), |
| 5465 | "power state did not have any performance level", |
| 5466 | return -1); |
| 5467 | |
| 5468 | high_limit_count = (1 == hw_state->performance_level_count) ? 0: 1; |
| 5469 | |
| 5470 | tonga_trim_single_dpm_states(hwmgr, |
| 5471 | &(data->dpm_table.sclk_table), |
| 5472 | hw_state->performance_levels[0].engine_clock, |
| 5473 | hw_state->performance_levels[high_limit_count].engine_clock); |
| 5474 | |
| 5475 | tonga_trim_single_dpm_states(hwmgr, |
| 5476 | &(data->dpm_table.mclk_table), |
| 5477 | hw_state->performance_levels[0].memory_clock, |
| 5478 | hw_state->performance_levels[high_limit_count].memory_clock); |
| 5479 | |
Edward O'Callaghan | 538f1ef | 2016-07-12 10:17:57 +1000 | [diff] [blame] | 5480 | return 0; |
yanyang1 | c82baa2 | 2015-08-18 15:28:32 +0800 | [diff] [blame] | 5481 | } |
| 5482 | |
| 5483 | static int tonga_generate_dpm_level_enable_mask(struct pp_hwmgr *hwmgr, const void *input) |
| 5484 | { |
| 5485 | int result; |
| 5486 | const struct phm_set_power_state_input *states = (const struct phm_set_power_state_input *)input; |
| 5487 | struct tonga_hwmgr *data = (struct tonga_hwmgr *)(hwmgr->backend); |
| 5488 | const struct tonga_power_state *tonga_ps = cast_const_phw_tonga_power_state(states->pnew_state); |
| 5489 | |
yanyang1 | c82baa2 | 2015-08-18 15:28:32 +0800 | [diff] [blame] | 5490 | result = tonga_trim_dpm_states(hwmgr, tonga_ps); |
| 5491 | if (0 != result) |
| 5492 | return result; |
| 5493 | |
| 5494 | data->dpm_level_enable_mask.sclk_dpm_enable_mask = tonga_get_dpm_level_enable_mask_value(&data->dpm_table.sclk_table); |
| 5495 | data->dpm_level_enable_mask.mclk_dpm_enable_mask = tonga_get_dpm_level_enable_mask_value(&data->dpm_table.mclk_table); |
| 5496 | data->last_mclk_dpm_enable_mask = data->dpm_level_enable_mask.mclk_dpm_enable_mask; |
| 5497 | if (data->uvd_enabled) |
| 5498 | data->dpm_level_enable_mask.mclk_dpm_enable_mask &= 0xFFFFFFFE; |
| 5499 | |
| 5500 | data->dpm_level_enable_mask.pcie_dpm_enable_mask = tonga_get_dpm_level_enable_mask_value(&data->dpm_table.pcie_speed_table); |
| 5501 | |
| 5502 | return 0; |
| 5503 | } |
| 5504 | |
Rex Zhu | 0859ed3 | 2015-10-15 21:12:58 +0800 | [diff] [blame] | 5505 | int tonga_enable_disable_vce_dpm(struct pp_hwmgr *hwmgr, bool enable) |
yanyang1 | c82baa2 | 2015-08-18 15:28:32 +0800 | [diff] [blame] | 5506 | { |
Rex Zhu | 0859ed3 | 2015-10-15 21:12:58 +0800 | [diff] [blame] | 5507 | return smum_send_msg_to_smc(hwmgr->smumgr, enable ? |
yanyang1 | c82baa2 | 2015-08-18 15:28:32 +0800 | [diff] [blame] | 5508 | (PPSMC_Msg)PPSMC_MSG_VCEDPM_Enable : |
| 5509 | (PPSMC_Msg)PPSMC_MSG_VCEDPM_Disable); |
| 5510 | } |
| 5511 | |
Rex Zhu | 0859ed3 | 2015-10-15 21:12:58 +0800 | [diff] [blame] | 5512 | int tonga_enable_disable_uvd_dpm(struct pp_hwmgr *hwmgr, bool enable) |
| 5513 | { |
| 5514 | return smum_send_msg_to_smc(hwmgr->smumgr, enable ? |
| 5515 | (PPSMC_Msg)PPSMC_MSG_UVDDPM_Enable : |
| 5516 | (PPSMC_Msg)PPSMC_MSG_UVDDPM_Disable); |
| 5517 | } |
| 5518 | |
| 5519 | int tonga_update_uvd_dpm(struct pp_hwmgr *hwmgr, bool bgate) |
| 5520 | { |
| 5521 | struct tonga_hwmgr *data = (struct tonga_hwmgr *)(hwmgr->backend); |
| 5522 | uint32_t mm_boot_level_offset, mm_boot_level_value; |
| 5523 | struct phm_ppt_v1_information *ptable_information = (struct phm_ppt_v1_information *)(hwmgr->pptable); |
| 5524 | |
| 5525 | if (!bgate) { |
| 5526 | data->smc_state_table.UvdBootLevel = (uint8_t) (ptable_information->mm_dep_table->count - 1); |
| 5527 | mm_boot_level_offset = data->dpm_table_start + offsetof(SMU72_Discrete_DpmTable, UvdBootLevel); |
| 5528 | mm_boot_level_offset /= 4; |
| 5529 | mm_boot_level_offset *= 4; |
| 5530 | mm_boot_level_value = cgs_read_ind_register(hwmgr->device, CGS_IND_REG__SMC, mm_boot_level_offset); |
| 5531 | mm_boot_level_value &= 0x00FFFFFF; |
| 5532 | mm_boot_level_value |= data->smc_state_table.UvdBootLevel << 24; |
| 5533 | cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, mm_boot_level_offset, mm_boot_level_value); |
| 5534 | |
| 5535 | if (!phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_UVDDPM) || |
| 5536 | phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_StablePState)) |
| 5537 | smum_send_msg_to_smc_with_parameter(hwmgr->smumgr, |
| 5538 | PPSMC_MSG_UVDDPM_SetEnabledMask, |
| 5539 | (uint32_t)(1 << data->smc_state_table.UvdBootLevel)); |
| 5540 | } |
| 5541 | |
| 5542 | return tonga_enable_disable_uvd_dpm(hwmgr, !bgate); |
| 5543 | } |
| 5544 | |
| 5545 | int tonga_update_vce_dpm(struct pp_hwmgr *hwmgr, const void *input) |
yanyang1 | c82baa2 | 2015-08-18 15:28:32 +0800 | [diff] [blame] | 5546 | { |
| 5547 | const struct phm_set_power_state_input *states = (const struct phm_set_power_state_input *)input; |
| 5548 | struct tonga_hwmgr *data = (struct tonga_hwmgr *)(hwmgr->backend); |
| 5549 | const struct tonga_power_state *tonga_nps = cast_const_phw_tonga_power_state(states->pnew_state); |
| 5550 | const struct tonga_power_state *tonga_cps = cast_const_phw_tonga_power_state(states->pcurrent_state); |
| 5551 | |
| 5552 | uint32_t mm_boot_level_offset, mm_boot_level_value; |
| 5553 | struct phm_ppt_v1_information *pptable_info = (struct phm_ppt_v1_information *)(hwmgr->pptable); |
| 5554 | |
Rex Zhu | 0859ed3 | 2015-10-15 21:12:58 +0800 | [diff] [blame] | 5555 | if (tonga_nps->vce_clocks.EVCLK > 0 && (tonga_cps == NULL || tonga_cps->vce_clocks.EVCLK == 0)) { |
yanyang1 | c82baa2 | 2015-08-18 15:28:32 +0800 | [diff] [blame] | 5556 | data->smc_state_table.VceBootLevel = (uint8_t) (pptable_info->mm_dep_table->count - 1); |
| 5557 | |
| 5558 | mm_boot_level_offset = data->dpm_table_start + offsetof(SMU72_Discrete_DpmTable, VceBootLevel); |
| 5559 | mm_boot_level_offset /= 4; |
| 5560 | mm_boot_level_offset *= 4; |
| 5561 | mm_boot_level_value = cgs_read_ind_register(hwmgr->device, CGS_IND_REG__SMC, mm_boot_level_offset); |
| 5562 | mm_boot_level_value &= 0xFF00FFFF; |
| 5563 | mm_boot_level_value |= data->smc_state_table.VceBootLevel << 16; |
| 5564 | cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, mm_boot_level_offset, mm_boot_level_value); |
| 5565 | |
Rex Zhu | 0859ed3 | 2015-10-15 21:12:58 +0800 | [diff] [blame] | 5566 | if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_StablePState)) |
| 5567 | smum_send_msg_to_smc_with_parameter(hwmgr->smumgr, |
| 5568 | PPSMC_MSG_VCEDPM_SetEnabledMask, |
| 5569 | (uint32_t)(1 << data->smc_state_table.VceBootLevel)); |
yanyang1 | c82baa2 | 2015-08-18 15:28:32 +0800 | [diff] [blame] | 5570 | |
Rex Zhu | 0859ed3 | 2015-10-15 21:12:58 +0800 | [diff] [blame] | 5571 | tonga_enable_disable_vce_dpm(hwmgr, true); |
| 5572 | } else if (tonga_nps->vce_clocks.EVCLK == 0 && tonga_cps != NULL && tonga_cps->vce_clocks.EVCLK > 0) |
| 5573 | tonga_enable_disable_vce_dpm(hwmgr, false); |
yanyang1 | c82baa2 | 2015-08-18 15:28:32 +0800 | [diff] [blame] | 5574 | |
| 5575 | return 0; |
| 5576 | } |
| 5577 | |
| 5578 | static int tonga_update_and_upload_mc_reg_table(struct pp_hwmgr *hwmgr) |
| 5579 | { |
| 5580 | struct tonga_hwmgr *data = (struct tonga_hwmgr *)(hwmgr->backend); |
| 5581 | |
| 5582 | uint32_t address; |
| 5583 | int32_t result; |
| 5584 | |
| 5585 | if (0 == (data->need_update_smu7_dpm_table & DPMTABLE_OD_UPDATE_MCLK)) |
| 5586 | return 0; |
| 5587 | |
| 5588 | |
| 5589 | memset(&data->mc_reg_table, 0, sizeof(SMU72_Discrete_MCRegisters)); |
| 5590 | |
| 5591 | result = tonga_convert_mc_reg_table_to_smc(hwmgr, &(data->mc_reg_table)); |
| 5592 | |
| 5593 | if(result != 0) |
| 5594 | return result; |
| 5595 | |
| 5596 | |
| 5597 | address = data->mc_reg_table_start + (uint32_t)offsetof(SMU72_Discrete_MCRegisters, data[0]); |
| 5598 | |
| 5599 | return tonga_copy_bytes_to_smc(hwmgr->smumgr, address, |
| 5600 | (uint8_t *)&data->mc_reg_table.data[0], |
| 5601 | sizeof(SMU72_Discrete_MCRegisterSet) * data->dpm_table.mclk_table.count, |
| 5602 | data->sram_end); |
| 5603 | } |
| 5604 | |
| 5605 | static int tonga_program_memory_timing_parameters_conditionally(struct pp_hwmgr *hwmgr) |
| 5606 | { |
| 5607 | struct tonga_hwmgr *data = (struct tonga_hwmgr *)(hwmgr->backend); |
| 5608 | |
| 5609 | if (data->need_update_smu7_dpm_table & |
| 5610 | (DPMTABLE_OD_UPDATE_SCLK + DPMTABLE_OD_UPDATE_MCLK)) |
| 5611 | return tonga_program_memory_timing_parameters(hwmgr); |
| 5612 | |
| 5613 | return 0; |
| 5614 | } |
| 5615 | |
| 5616 | static int tonga_unfreeze_sclk_mclk_dpm(struct pp_hwmgr *hwmgr) |
| 5617 | { |
| 5618 | struct tonga_hwmgr *data = (struct tonga_hwmgr *)(hwmgr->backend); |
| 5619 | |
| 5620 | if (0 == data->need_update_smu7_dpm_table) |
| 5621 | return 0; |
| 5622 | |
| 5623 | if ((0 == data->sclk_dpm_key_disabled) && |
| 5624 | (data->need_update_smu7_dpm_table & |
| 5625 | (DPMTABLE_OD_UPDATE_SCLK + DPMTABLE_UPDATE_SCLK))) { |
| 5626 | |
Edward O'Callaghan | 4ba27f9 | 2016-07-12 10:17:56 +1000 | [diff] [blame] | 5627 | PP_ASSERT_WITH_CODE(!tonga_is_dpm_running(hwmgr), |
| 5628 | "Trying to Unfreeze SCLK DPM when DPM is disabled", |
yanyang1 | c82baa2 | 2015-08-18 15:28:32 +0800 | [diff] [blame] | 5629 | ); |
| 5630 | PP_ASSERT_WITH_CODE( |
| 5631 | 0 == smum_send_msg_to_smc(hwmgr->smumgr, |
| 5632 | PPSMC_MSG_SCLKDPM_UnfreezeLevel), |
| 5633 | "Failed to unfreeze SCLK DPM during UnFreezeSclkMclkDPM Function!", |
| 5634 | return -1); |
| 5635 | } |
| 5636 | |
| 5637 | if ((0 == data->mclk_dpm_key_disabled) && |
| 5638 | (data->need_update_smu7_dpm_table & DPMTABLE_OD_UPDATE_MCLK)) { |
| 5639 | |
Edward O'Callaghan | 4ba27f9 | 2016-07-12 10:17:56 +1000 | [diff] [blame] | 5640 | PP_ASSERT_WITH_CODE(!tonga_is_dpm_running(hwmgr), |
| 5641 | "Trying to Unfreeze MCLK DPM when DPM is disabled", |
yanyang1 | c82baa2 | 2015-08-18 15:28:32 +0800 | [diff] [blame] | 5642 | ); |
| 5643 | PP_ASSERT_WITH_CODE( |
| 5644 | 0 == smum_send_msg_to_smc(hwmgr->smumgr, |
| 5645 | PPSMC_MSG_SCLKDPM_UnfreezeLevel), |
| 5646 | "Failed to unfreeze MCLK DPM during UnFreezeSclkMclkDPM Function!", |
| 5647 | return -1); |
| 5648 | } |
| 5649 | |
| 5650 | data->need_update_smu7_dpm_table = 0; |
| 5651 | |
| 5652 | return 0; |
| 5653 | } |
| 5654 | |
| 5655 | static int tonga_notify_link_speed_change_after_state_change(struct pp_hwmgr *hwmgr, const void *input) |
| 5656 | { |
| 5657 | const struct phm_set_power_state_input *states = (const struct phm_set_power_state_input *)input; |
| 5658 | struct tonga_hwmgr *data = (struct tonga_hwmgr *)(hwmgr->backend); |
| 5659 | const struct tonga_power_state *tonga_ps = cast_const_phw_tonga_power_state(states->pnew_state); |
| 5660 | uint16_t target_link_speed = tonga_get_maximum_link_speed(hwmgr, tonga_ps); |
| 5661 | uint8_t request; |
| 5662 | |
| 5663 | if (data->pspp_notify_required || |
| 5664 | data->pcie_performance_request) { |
| 5665 | if (target_link_speed == PP_PCIEGen3) |
| 5666 | request = PCIE_PERF_REQ_GEN3; |
| 5667 | else if (target_link_speed == PP_PCIEGen2) |
| 5668 | request = PCIE_PERF_REQ_GEN2; |
| 5669 | else |
| 5670 | request = PCIE_PERF_REQ_GEN1; |
| 5671 | |
| 5672 | if(request == PCIE_PERF_REQ_GEN1 && tonga_get_current_pcie_speed(hwmgr) > 0) { |
| 5673 | data->pcie_performance_request = false; |
| 5674 | return 0; |
| 5675 | } |
| 5676 | |
| 5677 | if (0 != acpi_pcie_perf_request(hwmgr->device, request, false)) { |
| 5678 | if (PP_PCIEGen2 == target_link_speed) |
| 5679 | printk("PSPP request to switch to Gen2 from Gen3 Failed!"); |
| 5680 | else |
| 5681 | printk("PSPP request to switch to Gen1 from Gen2 Failed!"); |
| 5682 | } |
| 5683 | } |
| 5684 | |
| 5685 | data->pcie_performance_request = false; |
| 5686 | return 0; |
| 5687 | } |
| 5688 | |
| 5689 | static int tonga_set_power_state_tasks(struct pp_hwmgr *hwmgr, const void *input) |
| 5690 | { |
| 5691 | int tmp_result, result = 0; |
| 5692 | |
| 5693 | tmp_result = tonga_find_dpm_states_clocks_in_dpm_table(hwmgr, input); |
| 5694 | PP_ASSERT_WITH_CODE((0 == tmp_result), "Failed to find DPM states clocks in DPM table!", result = tmp_result); |
| 5695 | |
| 5696 | if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_PCIEPerformanceRequest)) { |
| 5697 | tmp_result = tonga_request_link_speed_change_before_state_change(hwmgr, input); |
| 5698 | PP_ASSERT_WITH_CODE((0 == tmp_result), "Failed to request link speed change before state change!", result = tmp_result); |
| 5699 | } |
| 5700 | |
| 5701 | tmp_result = tonga_freeze_sclk_mclk_dpm(hwmgr); |
| 5702 | PP_ASSERT_WITH_CODE((0 == tmp_result), "Failed to freeze SCLK MCLK DPM!", result = tmp_result); |
| 5703 | |
| 5704 | tmp_result = tonga_populate_and_upload_sclk_mclk_dpm_levels(hwmgr, input); |
| 5705 | PP_ASSERT_WITH_CODE((0 == tmp_result), "Failed to populate and upload SCLK MCLK DPM levels!", result = tmp_result); |
| 5706 | |
| 5707 | tmp_result = tonga_generate_dpm_level_enable_mask(hwmgr, input); |
| 5708 | PP_ASSERT_WITH_CODE((0 == tmp_result), "Failed to generate DPM level enabled mask!", result = tmp_result); |
| 5709 | |
| 5710 | tmp_result = tonga_update_vce_dpm(hwmgr, input); |
| 5711 | PP_ASSERT_WITH_CODE((0 == tmp_result), "Failed to update VCE DPM!", result = tmp_result); |
| 5712 | |
| 5713 | tmp_result = tonga_update_sclk_threshold(hwmgr); |
| 5714 | PP_ASSERT_WITH_CODE((0 == tmp_result), "Failed to update SCLK threshold!", result = tmp_result); |
| 5715 | |
| 5716 | tmp_result = tonga_update_and_upload_mc_reg_table(hwmgr); |
| 5717 | PP_ASSERT_WITH_CODE((0 == tmp_result), "Failed to upload MC reg table!", result = tmp_result); |
| 5718 | |
| 5719 | tmp_result = tonga_program_memory_timing_parameters_conditionally(hwmgr); |
| 5720 | PP_ASSERT_WITH_CODE((0 == tmp_result), "Failed to program memory timing parameters!", result = tmp_result); |
| 5721 | |
| 5722 | tmp_result = tonga_unfreeze_sclk_mclk_dpm(hwmgr); |
| 5723 | PP_ASSERT_WITH_CODE((0 == tmp_result), "Failed to unfreeze SCLK MCLK DPM!", result = tmp_result); |
| 5724 | |
| 5725 | tmp_result = tonga_upload_dpm_level_enable_mask(hwmgr); |
| 5726 | PP_ASSERT_WITH_CODE((0 == tmp_result), "Failed to upload DPM level enabled mask!", result = tmp_result); |
| 5727 | |
| 5728 | if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_PCIEPerformanceRequest)) { |
| 5729 | tmp_result = tonga_notify_link_speed_change_after_state_change(hwmgr, input); |
| 5730 | PP_ASSERT_WITH_CODE((0 == tmp_result), "Failed to notify link speed change after state change!", result = tmp_result); |
| 5731 | } |
| 5732 | |
| 5733 | return result; |
| 5734 | } |
| 5735 | |
Rex Zhu | 1e4854e | 2015-10-20 18:06:23 +0800 | [diff] [blame] | 5736 | /** |
| 5737 | * Set maximum target operating fan output PWM |
| 5738 | * |
| 5739 | * @param pHwMgr: the address of the powerplay hardware manager. |
| 5740 | * @param usMaxFanPwm: max operating fan PWM in percents |
| 5741 | * @return The response that came from the SMC. |
| 5742 | */ |
| 5743 | static int tonga_set_max_fan_pwm_output(struct pp_hwmgr *hwmgr, uint16_t us_max_fan_pwm) |
| 5744 | { |
| 5745 | hwmgr->thermal_controller.advanceFanControlParameters.usMaxFanPWM = us_max_fan_pwm; |
| 5746 | |
| 5747 | if (phm_is_hw_access_blocked(hwmgr)) |
| 5748 | return 0; |
| 5749 | |
Rex Zhu | c15c8d7 | 2016-01-06 16:48:38 +0800 | [diff] [blame] | 5750 | return (0 == smum_send_msg_to_smc_with_parameter(hwmgr->smumgr, PPSMC_MSG_SetFanPwmMax, us_max_fan_pwm) ? 0 : -1); |
Rex Zhu | 1e4854e | 2015-10-20 18:06:23 +0800 | [diff] [blame] | 5751 | } |
Rex Zhu | bbb207f | 2015-10-16 15:02:04 +0800 | [diff] [blame] | 5752 | |
| 5753 | int tonga_notify_smc_display_config_after_ps_adjustment(struct pp_hwmgr *hwmgr) |
| 5754 | { |
| 5755 | uint32_t num_active_displays = 0; |
| 5756 | struct cgs_display_info info = {0}; |
| 5757 | info.mode_info = NULL; |
| 5758 | |
| 5759 | cgs_get_active_displays_info(hwmgr->device, &info); |
| 5760 | |
| 5761 | num_active_displays = info.display_count; |
| 5762 | |
| 5763 | if (num_active_displays > 1) /* to do && (pHwMgr->pPECI->displayConfiguration.bMultiMonitorInSync != TRUE)) */ |
| 5764 | tonga_notify_smc_display_change(hwmgr, false); |
| 5765 | else |
| 5766 | tonga_notify_smc_display_change(hwmgr, true); |
| 5767 | |
| 5768 | return 0; |
| 5769 | } |
| 5770 | |
| 5771 | /** |
| 5772 | * Programs the display gap |
| 5773 | * |
| 5774 | * @param hwmgr the address of the powerplay hardware manager. |
| 5775 | * @return always OK |
| 5776 | */ |
| 5777 | int tonga_program_display_gap(struct pp_hwmgr *hwmgr) |
| 5778 | { |
| 5779 | struct tonga_hwmgr *data = (struct tonga_hwmgr *)(hwmgr->backend); |
| 5780 | uint32_t num_active_displays = 0; |
| 5781 | uint32_t display_gap = cgs_read_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixCG_DISPLAY_GAP_CNTL); |
| 5782 | uint32_t display_gap2; |
| 5783 | uint32_t pre_vbi_time_in_us; |
| 5784 | uint32_t frame_time_in_us; |
| 5785 | uint32_t ref_clock; |
| 5786 | uint32_t refresh_rate = 0; |
| 5787 | struct cgs_display_info info = {0}; |
| 5788 | struct cgs_mode_info mode_info; |
| 5789 | |
| 5790 | info.mode_info = &mode_info; |
| 5791 | |
| 5792 | cgs_get_active_displays_info(hwmgr->device, &info); |
| 5793 | num_active_displays = info.display_count; |
| 5794 | |
| 5795 | display_gap = PHM_SET_FIELD(display_gap, CG_DISPLAY_GAP_CNTL, DISP_GAP, (num_active_displays > 0)? DISPLAY_GAP_VBLANK_OR_WM : DISPLAY_GAP_IGNORE); |
| 5796 | cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixCG_DISPLAY_GAP_CNTL, display_gap); |
| 5797 | |
| 5798 | ref_clock = mode_info.ref_clock; |
| 5799 | refresh_rate = mode_info.refresh_rate; |
| 5800 | |
| 5801 | if(0 == refresh_rate) |
| 5802 | refresh_rate = 60; |
| 5803 | |
| 5804 | frame_time_in_us = 1000000 / refresh_rate; |
| 5805 | |
| 5806 | pre_vbi_time_in_us = frame_time_in_us - 200 - mode_info.vblank_time_us; |
| 5807 | display_gap2 = pre_vbi_time_in_us * (ref_clock / 100); |
| 5808 | |
| 5809 | cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixCG_DISPLAY_GAP_CNTL2, display_gap2); |
| 5810 | |
| 5811 | cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, data->soft_regs_start + offsetof(SMU72_SoftRegisters, PreVBlankGap), 0x64); |
| 5812 | |
| 5813 | cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, data->soft_regs_start + offsetof(SMU72_SoftRegisters, VBlankTimeout), (frame_time_in_us - pre_vbi_time_in_us)); |
| 5814 | |
| 5815 | if (num_active_displays == 1) |
| 5816 | tonga_notify_smc_display_change(hwmgr, true); |
| 5817 | |
| 5818 | return 0; |
| 5819 | } |
| 5820 | |
| 5821 | int tonga_display_configuration_changed_task(struct pp_hwmgr *hwmgr) |
| 5822 | { |
| 5823 | |
| 5824 | tonga_program_display_gap(hwmgr); |
| 5825 | |
| 5826 | /* to do PhwTonga_CacUpdateDisplayConfiguration(pHwMgr); */ |
| 5827 | return 0; |
| 5828 | } |
| 5829 | |
Rex Zhu | 1e4854e | 2015-10-20 18:06:23 +0800 | [diff] [blame] | 5830 | /** |
| 5831 | * Set maximum target operating fan output RPM |
| 5832 | * |
| 5833 | * @param pHwMgr: the address of the powerplay hardware manager. |
| 5834 | * @param usMaxFanRpm: max operating fan RPM value. |
| 5835 | * @return The response that came from the SMC. |
| 5836 | */ |
| 5837 | static int tonga_set_max_fan_rpm_output(struct pp_hwmgr *hwmgr, uint16_t us_max_fan_pwm) |
| 5838 | { |
| 5839 | hwmgr->thermal_controller.advanceFanControlParameters.usMaxFanRPM = us_max_fan_pwm; |
| 5840 | |
| 5841 | if (phm_is_hw_access_blocked(hwmgr)) |
| 5842 | return 0; |
| 5843 | |
Rex Zhu | c15c8d7 | 2016-01-06 16:48:38 +0800 | [diff] [blame] | 5844 | return (0 == smum_send_msg_to_smc_with_parameter(hwmgr->smumgr, PPSMC_MSG_SetFanRpmMax, us_max_fan_pwm) ? 0 : -1); |
Rex Zhu | 1e4854e | 2015-10-20 18:06:23 +0800 | [diff] [blame] | 5845 | } |
| 5846 | |
| 5847 | uint32_t tonga_get_xclk(struct pp_hwmgr *hwmgr) |
| 5848 | { |
| 5849 | uint32_t reference_clock; |
| 5850 | uint32_t tc; |
| 5851 | uint32_t divide; |
| 5852 | |
| 5853 | ATOM_FIRMWARE_INFO *fw_info; |
| 5854 | uint16_t size; |
| 5855 | uint8_t frev, crev; |
| 5856 | int index = GetIndexIntoMasterTable(DATA, FirmwareInfo); |
| 5857 | |
| 5858 | tc = PHM_READ_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, CG_CLKPIN_CNTL_2, MUX_TCLK_TO_XCLK); |
| 5859 | |
| 5860 | if (tc) |
| 5861 | return TCLK; |
| 5862 | |
| 5863 | fw_info = (ATOM_FIRMWARE_INFO *)cgs_atom_get_data_table(hwmgr->device, index, |
| 5864 | &size, &frev, &crev); |
| 5865 | |
| 5866 | if (!fw_info) |
| 5867 | return 0; |
| 5868 | |
Rex Zhu | dcf799e | 2016-03-23 15:12:48 +0800 | [diff] [blame] | 5869 | reference_clock = le16_to_cpu(fw_info->usReferenceClock); |
Rex Zhu | 1e4854e | 2015-10-20 18:06:23 +0800 | [diff] [blame] | 5870 | |
| 5871 | divide = PHM_READ_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, CG_CLKPIN_CNTL, XTALIN_DIVIDE); |
| 5872 | |
| 5873 | if (0 != divide) |
| 5874 | return reference_clock / 4; |
| 5875 | |
| 5876 | return reference_clock; |
| 5877 | } |
| 5878 | |
| 5879 | int tonga_dpm_set_interrupt_state(void *private_data, |
| 5880 | unsigned src_id, unsigned type, |
| 5881 | int enabled) |
| 5882 | { |
| 5883 | uint32_t cg_thermal_int; |
| 5884 | struct pp_hwmgr *hwmgr = ((struct pp_eventmgr *)private_data)->hwmgr; |
| 5885 | |
| 5886 | if (hwmgr == NULL) |
| 5887 | return -EINVAL; |
| 5888 | |
| 5889 | switch (type) { |
| 5890 | case AMD_THERMAL_IRQ_LOW_TO_HIGH: |
| 5891 | if (enabled) { |
| 5892 | cg_thermal_int = cgs_read_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixCG_THERMAL_INT); |
| 5893 | cg_thermal_int |= CG_THERMAL_INT_CTRL__THERM_INTH_MASK_MASK; |
| 5894 | cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixCG_THERMAL_INT, cg_thermal_int); |
| 5895 | } else { |
| 5896 | cg_thermal_int = cgs_read_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixCG_THERMAL_INT); |
| 5897 | cg_thermal_int &= ~CG_THERMAL_INT_CTRL__THERM_INTH_MASK_MASK; |
| 5898 | cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixCG_THERMAL_INT, cg_thermal_int); |
| 5899 | } |
| 5900 | break; |
| 5901 | |
| 5902 | case AMD_THERMAL_IRQ_HIGH_TO_LOW: |
| 5903 | if (enabled) { |
| 5904 | cg_thermal_int = cgs_read_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixCG_THERMAL_INT); |
| 5905 | cg_thermal_int |= CG_THERMAL_INT_CTRL__THERM_INTL_MASK_MASK; |
| 5906 | cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixCG_THERMAL_INT, cg_thermal_int); |
| 5907 | } else { |
| 5908 | cg_thermal_int = cgs_read_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixCG_THERMAL_INT); |
| 5909 | cg_thermal_int &= ~CG_THERMAL_INT_CTRL__THERM_INTL_MASK_MASK; |
| 5910 | cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixCG_THERMAL_INT, cg_thermal_int); |
| 5911 | } |
| 5912 | break; |
| 5913 | default: |
| 5914 | break; |
| 5915 | } |
| 5916 | return 0; |
| 5917 | } |
| 5918 | |
| 5919 | int tonga_register_internal_thermal_interrupt(struct pp_hwmgr *hwmgr, |
| 5920 | const void *thermal_interrupt_info) |
| 5921 | { |
| 5922 | int result; |
| 5923 | const struct pp_interrupt_registration_info *info = |
| 5924 | (const struct pp_interrupt_registration_info *)thermal_interrupt_info; |
| 5925 | |
| 5926 | if (info == NULL) |
| 5927 | return -EINVAL; |
| 5928 | |
| 5929 | result = cgs_add_irq_source(hwmgr->device, 230, AMD_THERMAL_IRQ_LAST, |
| 5930 | tonga_dpm_set_interrupt_state, |
| 5931 | info->call_back, info->context); |
| 5932 | |
| 5933 | if (result) |
| 5934 | return -EINVAL; |
| 5935 | |
| 5936 | result = cgs_add_irq_source(hwmgr->device, 231, AMD_THERMAL_IRQ_LAST, |
| 5937 | tonga_dpm_set_interrupt_state, |
| 5938 | info->call_back, info->context); |
| 5939 | |
| 5940 | if (result) |
| 5941 | return -EINVAL; |
| 5942 | |
| 5943 | return 0; |
| 5944 | } |
| 5945 | |
Rex Zhu | e829ecd | 2015-11-04 11:21:35 +0800 | [diff] [blame] | 5946 | bool tonga_check_smc_update_required_for_display_configuration(struct pp_hwmgr *hwmgr) |
| 5947 | { |
| 5948 | struct tonga_hwmgr *data = (struct tonga_hwmgr *)(hwmgr->backend); |
| 5949 | bool is_update_required = false; |
| 5950 | struct cgs_display_info info = {0,0,NULL}; |
| 5951 | |
| 5952 | cgs_get_active_displays_info(hwmgr->device, &info); |
| 5953 | |
| 5954 | if (data->display_timing.num_existing_displays != info.display_count) |
| 5955 | is_update_required = true; |
| 5956 | /* TO DO NEED TO GET DEEP SLEEP CLOCK FROM DAL |
| 5957 | if (phm_cap_enabled(hwmgr->hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_SclkDeepSleep)) { |
| 5958 | cgs_get_min_clock_settings(hwmgr->device, &min_clocks); |
| 5959 | if(min_clocks.engineClockInSR != data->display_timing.minClockInSR) |
| 5960 | is_update_required = true; |
| 5961 | */ |
| 5962 | return is_update_required; |
| 5963 | } |
| 5964 | |
| 5965 | static inline bool tonga_are_power_levels_equal(const struct tonga_performance_level *pl1, |
| 5966 | const struct tonga_performance_level *pl2) |
| 5967 | { |
| 5968 | return ((pl1->memory_clock == pl2->memory_clock) && |
| 5969 | (pl1->engine_clock == pl2->engine_clock) && |
| 5970 | (pl1->pcie_gen == pl2->pcie_gen) && |
| 5971 | (pl1->pcie_lane == pl2->pcie_lane)); |
| 5972 | } |
| 5973 | |
| 5974 | int tonga_check_states_equal(struct pp_hwmgr *hwmgr, const struct pp_hw_power_state *pstate1, const struct pp_hw_power_state *pstate2, bool *equal) |
| 5975 | { |
| 5976 | const struct tonga_power_state *psa = cast_const_phw_tonga_power_state(pstate1); |
| 5977 | const struct tonga_power_state *psb = cast_const_phw_tonga_power_state(pstate2); |
| 5978 | int i; |
| 5979 | |
Rex Zhu | c15c8d7 | 2016-01-06 16:48:38 +0800 | [diff] [blame] | 5980 | if (equal == NULL || psa == NULL || psb == NULL) |
Rex Zhu | e829ecd | 2015-11-04 11:21:35 +0800 | [diff] [blame] | 5981 | return -EINVAL; |
| 5982 | |
| 5983 | /* If the two states don't even have the same number of performance levels they cannot be the same state. */ |
| 5984 | if (psa->performance_level_count != psb->performance_level_count) { |
| 5985 | *equal = false; |
| 5986 | return 0; |
| 5987 | } |
| 5988 | |
| 5989 | for (i = 0; i < psa->performance_level_count; i++) { |
| 5990 | if (!tonga_are_power_levels_equal(&(psa->performance_levels[i]), &(psb->performance_levels[i]))) { |
| 5991 | /* If we have found even one performance level pair that is different the states are different. */ |
| 5992 | *equal = false; |
| 5993 | return 0; |
| 5994 | } |
| 5995 | } |
| 5996 | |
| 5997 | /* If all performance levels are the same try to use the UVD clocks to break the tie.*/ |
| 5998 | *equal = ((psa->uvd_clocks.VCLK == psb->uvd_clocks.VCLK) && (psa->uvd_clocks.DCLK == psb->uvd_clocks.DCLK)); |
| 5999 | *equal &= ((psa->vce_clocks.EVCLK == psb->vce_clocks.EVCLK) && (psa->vce_clocks.ECCLK == psb->vce_clocks.ECCLK)); |
| 6000 | *equal &= (psa->sclk_threshold == psb->sclk_threshold); |
| 6001 | *equal &= (psa->acp_clk == psb->acp_clk); |
| 6002 | |
| 6003 | return 0; |
| 6004 | } |
| 6005 | |
Eric Huang | 9dcfc19 | 2015-12-04 10:57:22 -0500 | [diff] [blame] | 6006 | static int tonga_set_fan_control_mode(struct pp_hwmgr *hwmgr, uint32_t mode) |
| 6007 | { |
| 6008 | if (mode) { |
| 6009 | /* stop auto-manage */ |
| 6010 | if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, |
| 6011 | PHM_PlatformCaps_MicrocodeFanControl)) |
| 6012 | tonga_fan_ctrl_stop_smc_fan_control(hwmgr); |
| 6013 | tonga_fan_ctrl_set_static_mode(hwmgr, mode); |
| 6014 | } else |
| 6015 | /* restart auto-manage */ |
| 6016 | tonga_fan_ctrl_reset_fan_speed_to_default(hwmgr); |
| 6017 | |
| 6018 | return 0; |
| 6019 | } |
| 6020 | |
| 6021 | static int tonga_get_fan_control_mode(struct pp_hwmgr *hwmgr) |
| 6022 | { |
| 6023 | if (hwmgr->fan_ctrl_is_in_default_mode) |
| 6024 | return hwmgr->fan_ctrl_default_mode; |
| 6025 | else |
| 6026 | return PHM_READ_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, |
| 6027 | CG_FDO_CTRL2, FDO_PWM_MODE); |
| 6028 | } |
| 6029 | |
Eric Huang | 5d37a63 | 2016-01-22 14:32:41 -0500 | [diff] [blame] | 6030 | static int tonga_force_clock_level(struct pp_hwmgr *hwmgr, |
Eric Huang | 5632708 | 2016-04-12 14:57:23 -0400 | [diff] [blame] | 6031 | enum pp_clock_type type, uint32_t mask) |
Eric Huang | 5d37a63 | 2016-01-22 14:32:41 -0500 | [diff] [blame] | 6032 | { |
| 6033 | struct tonga_hwmgr *data = (struct tonga_hwmgr *)(hwmgr->backend); |
| 6034 | |
| 6035 | if (hwmgr->dpm_level != AMD_DPM_FORCED_LEVEL_MANUAL) |
| 6036 | return -EINVAL; |
| 6037 | |
| 6038 | switch (type) { |
| 6039 | case PP_SCLK: |
| 6040 | if (!data->sclk_dpm_key_disabled) |
| 6041 | smum_send_msg_to_smc_with_parameter(hwmgr->smumgr, |
| 6042 | PPSMC_MSG_SCLKDPM_SetEnabledMask, |
Eric Huang | 5632708 | 2016-04-12 14:57:23 -0400 | [diff] [blame] | 6043 | data->dpm_level_enable_mask.sclk_dpm_enable_mask & mask); |
Eric Huang | 5d37a63 | 2016-01-22 14:32:41 -0500 | [diff] [blame] | 6044 | break; |
| 6045 | case PP_MCLK: |
| 6046 | if (!data->mclk_dpm_key_disabled) |
| 6047 | smum_send_msg_to_smc_with_parameter(hwmgr->smumgr, |
| 6048 | PPSMC_MSG_MCLKDPM_SetEnabledMask, |
Eric Huang | 5632708 | 2016-04-12 14:57:23 -0400 | [diff] [blame] | 6049 | data->dpm_level_enable_mask.mclk_dpm_enable_mask & mask); |
Eric Huang | 5d37a63 | 2016-01-22 14:32:41 -0500 | [diff] [blame] | 6050 | break; |
| 6051 | case PP_PCIE: |
Eric Huang | 5632708 | 2016-04-12 14:57:23 -0400 | [diff] [blame] | 6052 | { |
| 6053 | uint32_t tmp = mask & data->dpm_level_enable_mask.pcie_dpm_enable_mask; |
| 6054 | uint32_t level = 0; |
| 6055 | |
| 6056 | while (tmp >>= 1) |
| 6057 | level++; |
| 6058 | |
Eric Huang | 5d37a63 | 2016-01-22 14:32:41 -0500 | [diff] [blame] | 6059 | if (!data->pcie_dpm_key_disabled) |
| 6060 | smum_send_msg_to_smc_with_parameter(hwmgr->smumgr, |
| 6061 | PPSMC_MSG_PCIeDPM_ForceLevel, |
Eric Huang | 5632708 | 2016-04-12 14:57:23 -0400 | [diff] [blame] | 6062 | level); |
Eric Huang | 5d37a63 | 2016-01-22 14:32:41 -0500 | [diff] [blame] | 6063 | break; |
Eric Huang | 5632708 | 2016-04-12 14:57:23 -0400 | [diff] [blame] | 6064 | } |
Eric Huang | 5d37a63 | 2016-01-22 14:32:41 -0500 | [diff] [blame] | 6065 | default: |
| 6066 | break; |
| 6067 | } |
| 6068 | |
| 6069 | return 0; |
| 6070 | } |
| 6071 | |
| 6072 | static int tonga_print_clock_levels(struct pp_hwmgr *hwmgr, |
| 6073 | enum pp_clock_type type, char *buf) |
| 6074 | { |
| 6075 | struct tonga_hwmgr *data = (struct tonga_hwmgr *)(hwmgr->backend); |
| 6076 | struct tonga_single_dpm_table *sclk_table = &(data->dpm_table.sclk_table); |
| 6077 | struct tonga_single_dpm_table *mclk_table = &(data->dpm_table.mclk_table); |
| 6078 | struct tonga_single_dpm_table *pcie_table = &(data->dpm_table.pcie_speed_table); |
| 6079 | int i, now, size = 0; |
| 6080 | uint32_t clock, pcie_speed; |
| 6081 | |
| 6082 | switch (type) { |
| 6083 | case PP_SCLK: |
| 6084 | smum_send_msg_to_smc(hwmgr->smumgr, PPSMC_MSG_API_GetSclkFrequency); |
| 6085 | clock = cgs_read_register(hwmgr->device, mmSMC_MSG_ARG_0); |
| 6086 | |
| 6087 | for (i = 0; i < sclk_table->count; i++) { |
| 6088 | if (clock > sclk_table->dpm_levels[i].value) |
| 6089 | continue; |
| 6090 | break; |
| 6091 | } |
| 6092 | now = i; |
| 6093 | |
| 6094 | for (i = 0; i < sclk_table->count; i++) |
| 6095 | size += sprintf(buf + size, "%d: %uMhz %s\n", |
| 6096 | i, sclk_table->dpm_levels[i].value / 100, |
| 6097 | (i == now) ? "*" : ""); |
| 6098 | break; |
| 6099 | case PP_MCLK: |
| 6100 | smum_send_msg_to_smc(hwmgr->smumgr, PPSMC_MSG_API_GetMclkFrequency); |
| 6101 | clock = cgs_read_register(hwmgr->device, mmSMC_MSG_ARG_0); |
| 6102 | |
| 6103 | for (i = 0; i < mclk_table->count; i++) { |
| 6104 | if (clock > mclk_table->dpm_levels[i].value) |
| 6105 | continue; |
| 6106 | break; |
| 6107 | } |
| 6108 | now = i; |
| 6109 | |
| 6110 | for (i = 0; i < mclk_table->count; i++) |
| 6111 | size += sprintf(buf + size, "%d: %uMhz %s\n", |
| 6112 | i, mclk_table->dpm_levels[i].value / 100, |
| 6113 | (i == now) ? "*" : ""); |
| 6114 | break; |
| 6115 | case PP_PCIE: |
| 6116 | pcie_speed = tonga_get_current_pcie_speed(hwmgr); |
| 6117 | for (i = 0; i < pcie_table->count; i++) { |
| 6118 | if (pcie_speed != pcie_table->dpm_levels[i].value) |
| 6119 | continue; |
| 6120 | break; |
| 6121 | } |
| 6122 | now = i; |
| 6123 | |
| 6124 | for (i = 0; i < pcie_table->count; i++) |
| 6125 | size += sprintf(buf + size, "%d: %s %s\n", i, |
| 6126 | (pcie_table->dpm_levels[i].value == 0) ? "2.5GB, x8" : |
| 6127 | (pcie_table->dpm_levels[i].value == 1) ? "5.0GB, x16" : |
| 6128 | (pcie_table->dpm_levels[i].value == 2) ? "8.0GB, x16" : "", |
| 6129 | (i == now) ? "*" : ""); |
| 6130 | break; |
| 6131 | default: |
| 6132 | break; |
| 6133 | } |
| 6134 | return size; |
| 6135 | } |
| 6136 | |
Eric Huang | 9ccd4e1 | 2016-05-12 15:10:49 -0400 | [diff] [blame] | 6137 | static int tonga_get_sclk_od(struct pp_hwmgr *hwmgr) |
| 6138 | { |
| 6139 | struct tonga_hwmgr *data = (struct tonga_hwmgr *)(hwmgr->backend); |
| 6140 | struct tonga_single_dpm_table *sclk_table = &(data->dpm_table.sclk_table); |
| 6141 | struct tonga_single_dpm_table *golden_sclk_table = |
| 6142 | &(data->golden_dpm_table.sclk_table); |
| 6143 | int value; |
| 6144 | |
| 6145 | value = (sclk_table->dpm_levels[sclk_table->count - 1].value - |
| 6146 | golden_sclk_table->dpm_levels[golden_sclk_table->count - 1].value) * |
| 6147 | 100 / |
| 6148 | golden_sclk_table->dpm_levels[golden_sclk_table->count - 1].value; |
| 6149 | |
| 6150 | return value; |
| 6151 | } |
| 6152 | |
| 6153 | static int tonga_set_sclk_od(struct pp_hwmgr *hwmgr, uint32_t value) |
| 6154 | { |
| 6155 | struct tonga_hwmgr *data = (struct tonga_hwmgr *)(hwmgr->backend); |
| 6156 | struct tonga_single_dpm_table *golden_sclk_table = |
| 6157 | &(data->golden_dpm_table.sclk_table); |
| 6158 | struct pp_power_state *ps; |
| 6159 | struct tonga_power_state *tonga_ps; |
| 6160 | |
| 6161 | if (value > 20) |
| 6162 | value = 20; |
| 6163 | |
| 6164 | ps = hwmgr->request_ps; |
| 6165 | |
| 6166 | if (ps == NULL) |
| 6167 | return -EINVAL; |
| 6168 | |
| 6169 | tonga_ps = cast_phw_tonga_power_state(&ps->hardware); |
| 6170 | |
| 6171 | tonga_ps->performance_levels[tonga_ps->performance_level_count - 1].engine_clock = |
| 6172 | golden_sclk_table->dpm_levels[golden_sclk_table->count - 1].value * |
| 6173 | value / 100 + |
| 6174 | golden_sclk_table->dpm_levels[golden_sclk_table->count - 1].value; |
| 6175 | |
| 6176 | return 0; |
| 6177 | } |
| 6178 | |
Eric Huang | f715d5b | 2016-05-24 16:13:25 -0400 | [diff] [blame] | 6179 | static int tonga_get_mclk_od(struct pp_hwmgr *hwmgr) |
| 6180 | { |
| 6181 | struct tonga_hwmgr *data = (struct tonga_hwmgr *)(hwmgr->backend); |
| 6182 | struct tonga_single_dpm_table *mclk_table = &(data->dpm_table.mclk_table); |
| 6183 | struct tonga_single_dpm_table *golden_mclk_table = |
| 6184 | &(data->golden_dpm_table.mclk_table); |
| 6185 | int value; |
| 6186 | |
| 6187 | value = (mclk_table->dpm_levels[mclk_table->count - 1].value - |
| 6188 | golden_mclk_table->dpm_levels[golden_mclk_table->count - 1].value) * |
| 6189 | 100 / |
| 6190 | golden_mclk_table->dpm_levels[golden_mclk_table->count - 1].value; |
| 6191 | |
| 6192 | return value; |
| 6193 | } |
| 6194 | |
| 6195 | static int tonga_set_mclk_od(struct pp_hwmgr *hwmgr, uint32_t value) |
| 6196 | { |
| 6197 | struct tonga_hwmgr *data = (struct tonga_hwmgr *)(hwmgr->backend); |
| 6198 | struct tonga_single_dpm_table *golden_mclk_table = |
| 6199 | &(data->golden_dpm_table.mclk_table); |
| 6200 | struct pp_power_state *ps; |
| 6201 | struct tonga_power_state *tonga_ps; |
| 6202 | |
| 6203 | if (value > 20) |
| 6204 | value = 20; |
| 6205 | |
| 6206 | ps = hwmgr->request_ps; |
| 6207 | |
| 6208 | if (ps == NULL) |
| 6209 | return -EINVAL; |
| 6210 | |
| 6211 | tonga_ps = cast_phw_tonga_power_state(&ps->hardware); |
| 6212 | |
| 6213 | tonga_ps->performance_levels[tonga_ps->performance_level_count - 1].memory_clock = |
| 6214 | golden_mclk_table->dpm_levels[golden_mclk_table->count - 1].value * |
| 6215 | value / 100 + |
| 6216 | golden_mclk_table->dpm_levels[golden_mclk_table->count - 1].value; |
| 6217 | |
| 6218 | return 0; |
| 6219 | } |
| 6220 | |
yanyang1 | c82baa2 | 2015-08-18 15:28:32 +0800 | [diff] [blame] | 6221 | static const struct pp_hwmgr_func tonga_hwmgr_funcs = { |
| 6222 | .backend_init = &tonga_hwmgr_backend_init, |
| 6223 | .backend_fini = &tonga_hwmgr_backend_fini, |
| 6224 | .asic_setup = &tonga_setup_asic_task, |
| 6225 | .dynamic_state_management_enable = &tonga_enable_dpm_tasks, |
Eric Huang | 57461af | 2016-06-06 15:36:42 -0400 | [diff] [blame] | 6226 | .dynamic_state_management_disable = &tonga_disable_dpm_tasks, |
yanyang1 | c82baa2 | 2015-08-18 15:28:32 +0800 | [diff] [blame] | 6227 | .apply_state_adjust_rules = tonga_apply_state_adjust_rules, |
| 6228 | .force_dpm_level = &tonga_force_dpm_level, |
| 6229 | .power_state_set = tonga_set_power_state_tasks, |
| 6230 | .get_power_state_size = tonga_get_power_state_size, |
| 6231 | .get_mclk = tonga_dpm_get_mclk, |
| 6232 | .get_sclk = tonga_dpm_get_sclk, |
| 6233 | .patch_boot_state = tonga_dpm_patch_boot_state, |
| 6234 | .get_pp_table_entry = tonga_get_pp_table_entry, |
| 6235 | .get_num_of_pp_table_entries = tonga_get_number_of_powerplay_table_entries, |
| 6236 | .print_current_perforce_level = tonga_print_current_perforce_level, |
Rex Zhu | 0859ed3 | 2015-10-15 21:12:58 +0800 | [diff] [blame] | 6237 | .powerdown_uvd = tonga_phm_powerdown_uvd, |
| 6238 | .powergate_uvd = tonga_phm_powergate_uvd, |
| 6239 | .powergate_vce = tonga_phm_powergate_vce, |
| 6240 | .disable_clock_power_gating = tonga_phm_disable_clock_power_gating, |
Alex Deucher | ce90dbd | 2016-04-28 17:19:41 -0400 | [diff] [blame] | 6241 | .update_clock_gatings = tonga_phm_update_clock_gatings, |
Rex Zhu | bbb207f | 2015-10-16 15:02:04 +0800 | [diff] [blame] | 6242 | .notify_smc_display_config_after_ps_adjustment = tonga_notify_smc_display_config_after_ps_adjustment, |
| 6243 | .display_config_changed = tonga_display_configuration_changed_task, |
Rex Zhu | 1e4854e | 2015-10-20 18:06:23 +0800 | [diff] [blame] | 6244 | .set_max_fan_pwm_output = tonga_set_max_fan_pwm_output, |
| 6245 | .set_max_fan_rpm_output = tonga_set_max_fan_rpm_output, |
| 6246 | .get_temperature = tonga_thermal_get_temperature, |
| 6247 | .stop_thermal_controller = tonga_thermal_stop_thermal_controller, |
| 6248 | .get_fan_speed_info = tonga_fan_ctrl_get_fan_speed_info, |
| 6249 | .get_fan_speed_percent = tonga_fan_ctrl_get_fan_speed_percent, |
| 6250 | .set_fan_speed_percent = tonga_fan_ctrl_set_fan_speed_percent, |
| 6251 | .reset_fan_speed_to_default = tonga_fan_ctrl_reset_fan_speed_to_default, |
| 6252 | .get_fan_speed_rpm = tonga_fan_ctrl_get_fan_speed_rpm, |
| 6253 | .set_fan_speed_rpm = tonga_fan_ctrl_set_fan_speed_rpm, |
| 6254 | .uninitialize_thermal_controller = tonga_thermal_ctrl_uninitialize_thermal_controller, |
| 6255 | .register_internal_thermal_interrupt = tonga_register_internal_thermal_interrupt, |
Rex Zhu | e829ecd | 2015-11-04 11:21:35 +0800 | [diff] [blame] | 6256 | .check_smc_update_required_for_display_configuration = tonga_check_smc_update_required_for_display_configuration, |
| 6257 | .check_states_equal = tonga_check_states_equal, |
Eric Huang | 9dcfc19 | 2015-12-04 10:57:22 -0500 | [diff] [blame] | 6258 | .set_fan_control_mode = tonga_set_fan_control_mode, |
| 6259 | .get_fan_control_mode = tonga_get_fan_control_mode, |
Eric Huang | 5d37a63 | 2016-01-22 14:32:41 -0500 | [diff] [blame] | 6260 | .force_clock_level = tonga_force_clock_level, |
| 6261 | .print_clock_levels = tonga_print_clock_levels, |
Eric Huang | 9ccd4e1 | 2016-05-12 15:10:49 -0400 | [diff] [blame] | 6262 | .get_sclk_od = tonga_get_sclk_od, |
| 6263 | .set_sclk_od = tonga_set_sclk_od, |
Eric Huang | f715d5b | 2016-05-24 16:13:25 -0400 | [diff] [blame] | 6264 | .get_mclk_od = tonga_get_mclk_od, |
| 6265 | .set_mclk_od = tonga_set_mclk_od, |
yanyang1 | c82baa2 | 2015-08-18 15:28:32 +0800 | [diff] [blame] | 6266 | }; |
| 6267 | |
| 6268 | int tonga_hwmgr_init(struct pp_hwmgr *hwmgr) |
| 6269 | { |
yanyang1 | c82baa2 | 2015-08-18 15:28:32 +0800 | [diff] [blame] | 6270 | hwmgr->hwmgr_func = &tonga_hwmgr_funcs; |
| 6271 | hwmgr->pptable_func = &tonga_pptable_funcs; |
Rex Zhu | 1e4854e | 2015-10-20 18:06:23 +0800 | [diff] [blame] | 6272 | pp_tonga_thermal_initialize(hwmgr); |
yanyang1 | c82baa2 | 2015-08-18 15:28:32 +0800 | [diff] [blame] | 6273 | return 0; |
| 6274 | } |
| 6275 | |