Sandeep Paulraj | 358934a | 2009-12-16 22:02:18 +0000 | [diff] [blame] | 1 | /* |
| 2 | * Copyright (C) 2009 Texas Instruments. |
Brian Niebuhr | 43abb11 | 2010-10-06 18:34:47 +0530 | [diff] [blame] | 3 | * Copyright (C) 2010 EF Johnson Technologies |
Sandeep Paulraj | 358934a | 2009-12-16 22:02:18 +0000 | [diff] [blame] | 4 | * |
| 5 | * This program is free software; you can redistribute it and/or modify |
| 6 | * it under the terms of the GNU General Public License as published by |
| 7 | * the Free Software Foundation; either version 2 of the License, or |
| 8 | * (at your option) any later version. |
| 9 | * |
| 10 | * This program is distributed in the hope that it will be useful, |
| 11 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 12 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 13 | * GNU General Public License for more details. |
| 14 | * |
| 15 | * You should have received a copy of the GNU General Public License |
| 16 | * along with this program; if not, write to the Free Software |
| 17 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA |
| 18 | */ |
| 19 | |
| 20 | #include <linux/interrupt.h> |
| 21 | #include <linux/io.h> |
| 22 | #include <linux/gpio.h> |
| 23 | #include <linux/module.h> |
| 24 | #include <linux/delay.h> |
| 25 | #include <linux/platform_device.h> |
| 26 | #include <linux/err.h> |
| 27 | #include <linux/clk.h> |
| 28 | #include <linux/dma-mapping.h> |
| 29 | #include <linux/spi/spi.h> |
| 30 | #include <linux/spi/spi_bitbang.h> |
Tejun Heo | 5a0e3ad | 2010-03-24 17:04:11 +0900 | [diff] [blame] | 31 | #include <linux/slab.h> |
Sandeep Paulraj | 358934a | 2009-12-16 22:02:18 +0000 | [diff] [blame] | 32 | |
| 33 | #include <mach/spi.h> |
| 34 | #include <mach/edma.h> |
| 35 | |
| 36 | #define SPI_NO_RESOURCE ((resource_size_t)-1) |
| 37 | |
| 38 | #define SPI_MAX_CHIPSELECT 2 |
| 39 | |
| 40 | #define CS_DEFAULT 0xFF |
| 41 | |
Sandeep Paulraj | 358934a | 2009-12-16 22:02:18 +0000 | [diff] [blame] | 42 | #define SPIFMT_PHASE_MASK BIT(16) |
| 43 | #define SPIFMT_POLARITY_MASK BIT(17) |
| 44 | #define SPIFMT_DISTIMER_MASK BIT(18) |
| 45 | #define SPIFMT_SHIFTDIR_MASK BIT(20) |
| 46 | #define SPIFMT_WAITENA_MASK BIT(21) |
| 47 | #define SPIFMT_PARITYENA_MASK BIT(22) |
| 48 | #define SPIFMT_ODD_PARITY_MASK BIT(23) |
| 49 | #define SPIFMT_WDELAY_MASK 0x3f000000u |
| 50 | #define SPIFMT_WDELAY_SHIFT 24 |
Brian Niebuhr | 7fe0092 | 2010-08-13 13:27:23 +0530 | [diff] [blame] | 51 | #define SPIFMT_PRESCALE_SHIFT 8 |
Sandeep Paulraj | 358934a | 2009-12-16 22:02:18 +0000 | [diff] [blame] | 52 | |
Sandeep Paulraj | 358934a | 2009-12-16 22:02:18 +0000 | [diff] [blame] | 53 | /* SPIPC0 */ |
| 54 | #define SPIPC0_DIFUN_MASK BIT(11) /* MISO */ |
| 55 | #define SPIPC0_DOFUN_MASK BIT(10) /* MOSI */ |
| 56 | #define SPIPC0_CLKFUN_MASK BIT(9) /* CLK */ |
| 57 | #define SPIPC0_SPIENA_MASK BIT(8) /* nREADY */ |
Sandeep Paulraj | 358934a | 2009-12-16 22:02:18 +0000 | [diff] [blame] | 58 | |
| 59 | #define SPIINT_MASKALL 0x0101035F |
Brian Niebuhr | e0d205e | 2010-09-02 16:52:06 +0530 | [diff] [blame] | 60 | #define SPIINT_MASKINT 0x0000015F |
| 61 | #define SPI_INTLVL_1 0x000001FF |
| 62 | #define SPI_INTLVL_0 0x00000000 |
Sandeep Paulraj | 358934a | 2009-12-16 22:02:18 +0000 | [diff] [blame] | 63 | |
Brian Niebuhr | cfbc5d1 | 2010-08-12 12:27:33 +0530 | [diff] [blame] | 64 | /* SPIDAT1 (upper 16 bit defines) */ |
| 65 | #define SPIDAT1_CSHOLD_MASK BIT(12) |
| 66 | |
| 67 | /* SPIGCR1 */ |
Sandeep Paulraj | 358934a | 2009-12-16 22:02:18 +0000 | [diff] [blame] | 68 | #define SPIGCR1_CLKMOD_MASK BIT(1) |
| 69 | #define SPIGCR1_MASTER_MASK BIT(0) |
Brian Niebuhr | 3f27b57 | 2010-10-06 18:25:43 +0530 | [diff] [blame] | 70 | #define SPIGCR1_POWERDOWN_MASK BIT(8) |
Sandeep Paulraj | 358934a | 2009-12-16 22:02:18 +0000 | [diff] [blame] | 71 | #define SPIGCR1_LOOPBACK_MASK BIT(16) |
Sekhar Nori | 8e206f1 | 2010-08-20 16:20:49 +0530 | [diff] [blame] | 72 | #define SPIGCR1_SPIENA_MASK BIT(24) |
Sandeep Paulraj | 358934a | 2009-12-16 22:02:18 +0000 | [diff] [blame] | 73 | |
| 74 | /* SPIBUF */ |
| 75 | #define SPIBUF_TXFULL_MASK BIT(29) |
| 76 | #define SPIBUF_RXEMPTY_MASK BIT(31) |
| 77 | |
Brian Niebuhr | 7abbf23 | 2010-08-19 15:07:38 +0530 | [diff] [blame] | 78 | /* SPIDELAY */ |
| 79 | #define SPIDELAY_C2TDELAY_SHIFT 24 |
| 80 | #define SPIDELAY_C2TDELAY_MASK (0xFF << SPIDELAY_C2TDELAY_SHIFT) |
| 81 | #define SPIDELAY_T2CDELAY_SHIFT 16 |
| 82 | #define SPIDELAY_T2CDELAY_MASK (0xFF << SPIDELAY_T2CDELAY_SHIFT) |
| 83 | #define SPIDELAY_T2EDELAY_SHIFT 8 |
| 84 | #define SPIDELAY_T2EDELAY_MASK (0xFF << SPIDELAY_T2EDELAY_SHIFT) |
| 85 | #define SPIDELAY_C2EDELAY_SHIFT 0 |
| 86 | #define SPIDELAY_C2EDELAY_MASK 0xFF |
| 87 | |
Sandeep Paulraj | 358934a | 2009-12-16 22:02:18 +0000 | [diff] [blame] | 88 | /* Error Masks */ |
| 89 | #define SPIFLG_DLEN_ERR_MASK BIT(0) |
| 90 | #define SPIFLG_TIMEOUT_MASK BIT(1) |
| 91 | #define SPIFLG_PARERR_MASK BIT(2) |
| 92 | #define SPIFLG_DESYNC_MASK BIT(3) |
| 93 | #define SPIFLG_BITERR_MASK BIT(4) |
| 94 | #define SPIFLG_OVRRUN_MASK BIT(6) |
Sandeep Paulraj | 358934a | 2009-12-16 22:02:18 +0000 | [diff] [blame] | 95 | #define SPIFLG_BUF_INIT_ACTIVE_MASK BIT(24) |
Brian Niebuhr | 839c996 | 2010-08-23 16:39:19 +0530 | [diff] [blame] | 96 | #define SPIFLG_ERROR_MASK (SPIFLG_DLEN_ERR_MASK \ |
| 97 | | SPIFLG_TIMEOUT_MASK | SPIFLG_PARERR_MASK \ |
| 98 | | SPIFLG_DESYNC_MASK | SPIFLG_BITERR_MASK \ |
| 99 | | SPIFLG_OVRRUN_MASK) |
Sandeep Paulraj | 358934a | 2009-12-16 22:02:18 +0000 | [diff] [blame] | 100 | |
Sandeep Paulraj | 358934a | 2009-12-16 22:02:18 +0000 | [diff] [blame] | 101 | #define SPIINT_DMA_REQ_EN BIT(16) |
Sandeep Paulraj | 358934a | 2009-12-16 22:02:18 +0000 | [diff] [blame] | 102 | |
Sandeep Paulraj | 358934a | 2009-12-16 22:02:18 +0000 | [diff] [blame] | 103 | /* SPI Controller registers */ |
| 104 | #define SPIGCR0 0x00 |
| 105 | #define SPIGCR1 0x04 |
| 106 | #define SPIINT 0x08 |
| 107 | #define SPILVL 0x0c |
| 108 | #define SPIFLG 0x10 |
| 109 | #define SPIPC0 0x14 |
Sandeep Paulraj | 358934a | 2009-12-16 22:02:18 +0000 | [diff] [blame] | 110 | #define SPIDAT1 0x3c |
| 111 | #define SPIBUF 0x40 |
Sandeep Paulraj | 358934a | 2009-12-16 22:02:18 +0000 | [diff] [blame] | 112 | #define SPIDELAY 0x48 |
| 113 | #define SPIDEF 0x4c |
| 114 | #define SPIFMT0 0x50 |
Sandeep Paulraj | 358934a | 2009-12-16 22:02:18 +0000 | [diff] [blame] | 115 | |
Sandeep Paulraj | 358934a | 2009-12-16 22:02:18 +0000 | [diff] [blame] | 116 | /* We have 2 DMA channels per CS, one for RX and one for TX */ |
| 117 | struct davinci_spi_dma { |
Sekhar Nori | 212d4b6 | 2010-10-11 10:41:39 +0530 | [diff] [blame] | 118 | int tx_channel; |
| 119 | int rx_channel; |
Brian Niebuhr | 523c37e | 2010-10-04 17:35:34 +0530 | [diff] [blame] | 120 | int dummy_param_slot; |
Sandeep Paulraj | 358934a | 2009-12-16 22:02:18 +0000 | [diff] [blame] | 121 | enum dma_event_q eventq; |
Sandeep Paulraj | 358934a | 2009-12-16 22:02:18 +0000 | [diff] [blame] | 122 | }; |
| 123 | |
| 124 | /* SPI Controller driver's private data. */ |
| 125 | struct davinci_spi { |
| 126 | struct spi_bitbang bitbang; |
| 127 | struct clk *clk; |
| 128 | |
| 129 | u8 version; |
| 130 | resource_size_t pbase; |
| 131 | void __iomem *base; |
Brian Niebuhr | e0d205e | 2010-09-02 16:52:06 +0530 | [diff] [blame] | 132 | u32 irq; |
| 133 | struct completion done; |
Sandeep Paulraj | 358934a | 2009-12-16 22:02:18 +0000 | [diff] [blame] | 134 | |
| 135 | const void *tx; |
| 136 | void *rx; |
Brian Niebuhr | e91c659 | 2010-10-01 10:29:29 +0530 | [diff] [blame] | 137 | #define SPI_TMP_BUFSZ (SMP_CACHE_BYTES + 1) |
| 138 | u8 rx_tmp_buf[SPI_TMP_BUFSZ]; |
Brian Niebuhr | e0d205e | 2010-09-02 16:52:06 +0530 | [diff] [blame] | 139 | int rcount; |
| 140 | int wcount; |
Sekhar Nori | 212d4b6 | 2010-10-11 10:41:39 +0530 | [diff] [blame] | 141 | struct davinci_spi_dma dma; |
Brian Niebuhr | 778e261 | 2010-09-03 15:15:06 +0530 | [diff] [blame] | 142 | struct davinci_spi_platform_data *pdata; |
Sandeep Paulraj | 358934a | 2009-12-16 22:02:18 +0000 | [diff] [blame] | 143 | |
| 144 | void (*get_rx)(u32 rx_data, struct davinci_spi *); |
| 145 | u32 (*get_tx)(struct davinci_spi *); |
| 146 | |
Brian Niebuhr | cda987e | 2010-08-19 16:16:28 +0530 | [diff] [blame] | 147 | u8 bytes_per_word[SPI_MAX_CHIPSELECT]; |
Sandeep Paulraj | 358934a | 2009-12-16 22:02:18 +0000 | [diff] [blame] | 148 | }; |
| 149 | |
Brian Niebuhr | 53a31b0 | 2010-08-16 15:05:51 +0530 | [diff] [blame] | 150 | static struct davinci_spi_config davinci_spi_default_cfg; |
| 151 | |
Sekhar Nori | 212d4b6 | 2010-10-11 10:41:39 +0530 | [diff] [blame] | 152 | static void davinci_spi_rx_buf_u8(u32 data, struct davinci_spi *dspi) |
Sandeep Paulraj | 358934a | 2009-12-16 22:02:18 +0000 | [diff] [blame] | 153 | { |
Sekhar Nori | 212d4b6 | 2010-10-11 10:41:39 +0530 | [diff] [blame] | 154 | if (dspi->rx) { |
| 155 | u8 *rx = dspi->rx; |
Brian Niebuhr | 53d454a | 2010-08-19 17:04:25 +0530 | [diff] [blame] | 156 | *rx++ = (u8)data; |
Sekhar Nori | 212d4b6 | 2010-10-11 10:41:39 +0530 | [diff] [blame] | 157 | dspi->rx = rx; |
Brian Niebuhr | 53d454a | 2010-08-19 17:04:25 +0530 | [diff] [blame] | 158 | } |
Sandeep Paulraj | 358934a | 2009-12-16 22:02:18 +0000 | [diff] [blame] | 159 | } |
| 160 | |
Sekhar Nori | 212d4b6 | 2010-10-11 10:41:39 +0530 | [diff] [blame] | 161 | static void davinci_spi_rx_buf_u16(u32 data, struct davinci_spi *dspi) |
Sandeep Paulraj | 358934a | 2009-12-16 22:02:18 +0000 | [diff] [blame] | 162 | { |
Sekhar Nori | 212d4b6 | 2010-10-11 10:41:39 +0530 | [diff] [blame] | 163 | if (dspi->rx) { |
| 164 | u16 *rx = dspi->rx; |
Brian Niebuhr | 53d454a | 2010-08-19 17:04:25 +0530 | [diff] [blame] | 165 | *rx++ = (u16)data; |
Sekhar Nori | 212d4b6 | 2010-10-11 10:41:39 +0530 | [diff] [blame] | 166 | dspi->rx = rx; |
Brian Niebuhr | 53d454a | 2010-08-19 17:04:25 +0530 | [diff] [blame] | 167 | } |
Sandeep Paulraj | 358934a | 2009-12-16 22:02:18 +0000 | [diff] [blame] | 168 | } |
| 169 | |
Sekhar Nori | 212d4b6 | 2010-10-11 10:41:39 +0530 | [diff] [blame] | 170 | static u32 davinci_spi_tx_buf_u8(struct davinci_spi *dspi) |
Sandeep Paulraj | 358934a | 2009-12-16 22:02:18 +0000 | [diff] [blame] | 171 | { |
Brian Niebuhr | 53d454a | 2010-08-19 17:04:25 +0530 | [diff] [blame] | 172 | u32 data = 0; |
Sekhar Nori | 212d4b6 | 2010-10-11 10:41:39 +0530 | [diff] [blame] | 173 | if (dspi->tx) { |
| 174 | const u8 *tx = dspi->tx; |
Brian Niebuhr | 53d454a | 2010-08-19 17:04:25 +0530 | [diff] [blame] | 175 | data = *tx++; |
Sekhar Nori | 212d4b6 | 2010-10-11 10:41:39 +0530 | [diff] [blame] | 176 | dspi->tx = tx; |
Brian Niebuhr | 53d454a | 2010-08-19 17:04:25 +0530 | [diff] [blame] | 177 | } |
Sandeep Paulraj | 358934a | 2009-12-16 22:02:18 +0000 | [diff] [blame] | 178 | return data; |
| 179 | } |
| 180 | |
Sekhar Nori | 212d4b6 | 2010-10-11 10:41:39 +0530 | [diff] [blame] | 181 | static u32 davinci_spi_tx_buf_u16(struct davinci_spi *dspi) |
Sandeep Paulraj | 358934a | 2009-12-16 22:02:18 +0000 | [diff] [blame] | 182 | { |
Brian Niebuhr | 53d454a | 2010-08-19 17:04:25 +0530 | [diff] [blame] | 183 | u32 data = 0; |
Sekhar Nori | 212d4b6 | 2010-10-11 10:41:39 +0530 | [diff] [blame] | 184 | if (dspi->tx) { |
| 185 | const u16 *tx = dspi->tx; |
Brian Niebuhr | 53d454a | 2010-08-19 17:04:25 +0530 | [diff] [blame] | 186 | data = *tx++; |
Sekhar Nori | 212d4b6 | 2010-10-11 10:41:39 +0530 | [diff] [blame] | 187 | dspi->tx = tx; |
Brian Niebuhr | 53d454a | 2010-08-19 17:04:25 +0530 | [diff] [blame] | 188 | } |
Sandeep Paulraj | 358934a | 2009-12-16 22:02:18 +0000 | [diff] [blame] | 189 | return data; |
| 190 | } |
| 191 | |
| 192 | static inline void set_io_bits(void __iomem *addr, u32 bits) |
| 193 | { |
| 194 | u32 v = ioread32(addr); |
| 195 | |
| 196 | v |= bits; |
| 197 | iowrite32(v, addr); |
| 198 | } |
| 199 | |
| 200 | static inline void clear_io_bits(void __iomem *addr, u32 bits) |
| 201 | { |
| 202 | u32 v = ioread32(addr); |
| 203 | |
| 204 | v &= ~bits; |
| 205 | iowrite32(v, addr); |
| 206 | } |
| 207 | |
Sandeep Paulraj | 358934a | 2009-12-16 22:02:18 +0000 | [diff] [blame] | 208 | /* |
| 209 | * Interface to control the chip select signal |
| 210 | */ |
| 211 | static void davinci_spi_chipselect(struct spi_device *spi, int value) |
| 212 | { |
Sekhar Nori | 212d4b6 | 2010-10-11 10:41:39 +0530 | [diff] [blame] | 213 | struct davinci_spi *dspi; |
Sandeep Paulraj | 358934a | 2009-12-16 22:02:18 +0000 | [diff] [blame] | 214 | struct davinci_spi_platform_data *pdata; |
Brian Niebuhr | 7978b8c | 2010-08-13 10:11:03 +0530 | [diff] [blame] | 215 | u8 chip_sel = spi->chip_select; |
Sekhar Nori | 212d4b6 | 2010-10-11 10:41:39 +0530 | [diff] [blame] | 216 | u16 spidat1 = CS_DEFAULT; |
Brian Niebuhr | 2385397 | 2010-08-13 10:57:44 +0530 | [diff] [blame] | 217 | bool gpio_chipsel = false; |
Sandeep Paulraj | 358934a | 2009-12-16 22:02:18 +0000 | [diff] [blame] | 218 | |
Sekhar Nori | 212d4b6 | 2010-10-11 10:41:39 +0530 | [diff] [blame] | 219 | dspi = spi_master_get_devdata(spi->master); |
| 220 | pdata = dspi->pdata; |
Sandeep Paulraj | 358934a | 2009-12-16 22:02:18 +0000 | [diff] [blame] | 221 | |
Brian Niebuhr | 2385397 | 2010-08-13 10:57:44 +0530 | [diff] [blame] | 222 | if (pdata->chip_sel && chip_sel < pdata->num_chipselect && |
| 223 | pdata->chip_sel[chip_sel] != SPI_INTERN_CS) |
| 224 | gpio_chipsel = true; |
| 225 | |
Sandeep Paulraj | 358934a | 2009-12-16 22:02:18 +0000 | [diff] [blame] | 226 | /* |
| 227 | * Board specific chip select logic decides the polarity and cs |
| 228 | * line for the controller |
| 229 | */ |
Brian Niebuhr | 2385397 | 2010-08-13 10:57:44 +0530 | [diff] [blame] | 230 | if (gpio_chipsel) { |
| 231 | if (value == BITBANG_CS_ACTIVE) |
| 232 | gpio_set_value(pdata->chip_sel[chip_sel], 0); |
| 233 | else |
| 234 | gpio_set_value(pdata->chip_sel[chip_sel], 1); |
| 235 | } else { |
| 236 | if (value == BITBANG_CS_ACTIVE) { |
Sekhar Nori | 212d4b6 | 2010-10-11 10:41:39 +0530 | [diff] [blame] | 237 | spidat1 |= SPIDAT1_CSHOLD_MASK; |
| 238 | spidat1 &= ~(0x1 << chip_sel); |
Brian Niebuhr | 2385397 | 2010-08-13 10:57:44 +0530 | [diff] [blame] | 239 | } |
Brian Niebuhr | 7978b8c | 2010-08-13 10:11:03 +0530 | [diff] [blame] | 240 | |
Sekhar Nori | 212d4b6 | 2010-10-11 10:41:39 +0530 | [diff] [blame] | 241 | iowrite16(spidat1, dspi->base + SPIDAT1 + 2); |
Brian Niebuhr | 2385397 | 2010-08-13 10:57:44 +0530 | [diff] [blame] | 242 | } |
Sandeep Paulraj | 358934a | 2009-12-16 22:02:18 +0000 | [diff] [blame] | 243 | } |
| 244 | |
| 245 | /** |
Brian Niebuhr | 7fe0092 | 2010-08-13 13:27:23 +0530 | [diff] [blame] | 246 | * davinci_spi_get_prescale - Calculates the correct prescale value |
| 247 | * @maxspeed_hz: the maximum rate the SPI clock can run at |
| 248 | * |
| 249 | * This function calculates the prescale value that generates a clock rate |
| 250 | * less than or equal to the specified maximum. |
| 251 | * |
| 252 | * Returns: calculated prescale - 1 for easy programming into SPI registers |
| 253 | * or negative error number if valid prescalar cannot be updated. |
| 254 | */ |
Sekhar Nori | 212d4b6 | 2010-10-11 10:41:39 +0530 | [diff] [blame] | 255 | static inline int davinci_spi_get_prescale(struct davinci_spi *dspi, |
Brian Niebuhr | 7fe0092 | 2010-08-13 13:27:23 +0530 | [diff] [blame] | 256 | u32 max_speed_hz) |
| 257 | { |
| 258 | int ret; |
| 259 | |
Sekhar Nori | 212d4b6 | 2010-10-11 10:41:39 +0530 | [diff] [blame] | 260 | ret = DIV_ROUND_UP(clk_get_rate(dspi->clk), max_speed_hz); |
Brian Niebuhr | 7fe0092 | 2010-08-13 13:27:23 +0530 | [diff] [blame] | 261 | |
| 262 | if (ret < 3 || ret > 256) |
| 263 | return -EINVAL; |
| 264 | |
| 265 | return ret - 1; |
| 266 | } |
| 267 | |
| 268 | /** |
Sandeep Paulraj | 358934a | 2009-12-16 22:02:18 +0000 | [diff] [blame] | 269 | * davinci_spi_setup_transfer - This functions will determine transfer method |
| 270 | * @spi: spi device on which data transfer to be done |
| 271 | * @t: spi transfer in which transfer info is filled |
| 272 | * |
| 273 | * This function determines data transfer method (8/16/32 bit transfer). |
| 274 | * It will also set the SPI Clock Control register according to |
| 275 | * SPI slave device freq. |
| 276 | */ |
| 277 | static int davinci_spi_setup_transfer(struct spi_device *spi, |
| 278 | struct spi_transfer *t) |
| 279 | { |
| 280 | |
Sekhar Nori | 212d4b6 | 2010-10-11 10:41:39 +0530 | [diff] [blame] | 281 | struct davinci_spi *dspi; |
Brian Niebuhr | 25f3351 | 2010-08-19 12:15:22 +0530 | [diff] [blame] | 282 | struct davinci_spi_config *spicfg; |
Sandeep Paulraj | 358934a | 2009-12-16 22:02:18 +0000 | [diff] [blame] | 283 | u8 bits_per_word = 0; |
Brian Niebuhr | 25f3351 | 2010-08-19 12:15:22 +0530 | [diff] [blame] | 284 | u32 hz = 0, spifmt = 0, prescale = 0; |
Sandeep Paulraj | 358934a | 2009-12-16 22:02:18 +0000 | [diff] [blame] | 285 | |
Sekhar Nori | 212d4b6 | 2010-10-11 10:41:39 +0530 | [diff] [blame] | 286 | dspi = spi_master_get_devdata(spi->master); |
Brian Niebuhr | 25f3351 | 2010-08-19 12:15:22 +0530 | [diff] [blame] | 287 | spicfg = (struct davinci_spi_config *)spi->controller_data; |
| 288 | if (!spicfg) |
| 289 | spicfg = &davinci_spi_default_cfg; |
Sandeep Paulraj | 358934a | 2009-12-16 22:02:18 +0000 | [diff] [blame] | 290 | |
| 291 | if (t) { |
| 292 | bits_per_word = t->bits_per_word; |
| 293 | hz = t->speed_hz; |
| 294 | } |
| 295 | |
| 296 | /* if bits_per_word is not set then set it default */ |
| 297 | if (!bits_per_word) |
| 298 | bits_per_word = spi->bits_per_word; |
| 299 | |
| 300 | /* |
| 301 | * Assign function pointer to appropriate transfer method |
| 302 | * 8bit, 16bit or 32bit transfer |
| 303 | */ |
| 304 | if (bits_per_word <= 8 && bits_per_word >= 2) { |
Sekhar Nori | 212d4b6 | 2010-10-11 10:41:39 +0530 | [diff] [blame] | 305 | dspi->get_rx = davinci_spi_rx_buf_u8; |
| 306 | dspi->get_tx = davinci_spi_tx_buf_u8; |
| 307 | dspi->bytes_per_word[spi->chip_select] = 1; |
Sandeep Paulraj | 358934a | 2009-12-16 22:02:18 +0000 | [diff] [blame] | 308 | } else if (bits_per_word <= 16 && bits_per_word >= 2) { |
Sekhar Nori | 212d4b6 | 2010-10-11 10:41:39 +0530 | [diff] [blame] | 309 | dspi->get_rx = davinci_spi_rx_buf_u16; |
| 310 | dspi->get_tx = davinci_spi_tx_buf_u16; |
| 311 | dspi->bytes_per_word[spi->chip_select] = 2; |
Sandeep Paulraj | 358934a | 2009-12-16 22:02:18 +0000 | [diff] [blame] | 312 | } else |
| 313 | return -EINVAL; |
| 314 | |
| 315 | if (!hz) |
| 316 | hz = spi->max_speed_hz; |
| 317 | |
Brian Niebuhr | 25f3351 | 2010-08-19 12:15:22 +0530 | [diff] [blame] | 318 | /* Set up SPIFMTn register, unique to this chipselect. */ |
| 319 | |
Sekhar Nori | 212d4b6 | 2010-10-11 10:41:39 +0530 | [diff] [blame] | 320 | prescale = davinci_spi_get_prescale(dspi, hz); |
Brian Niebuhr | 7fe0092 | 2010-08-13 13:27:23 +0530 | [diff] [blame] | 321 | if (prescale < 0) |
| 322 | return prescale; |
| 323 | |
Brian Niebuhr | 25f3351 | 2010-08-19 12:15:22 +0530 | [diff] [blame] | 324 | spifmt = (prescale << SPIFMT_PRESCALE_SHIFT) | (bits_per_word & 0x1f); |
Sandeep Paulraj | 358934a | 2009-12-16 22:02:18 +0000 | [diff] [blame] | 325 | |
Brian Niebuhr | 25f3351 | 2010-08-19 12:15:22 +0530 | [diff] [blame] | 326 | if (spi->mode & SPI_LSB_FIRST) |
| 327 | spifmt |= SPIFMT_SHIFTDIR_MASK; |
| 328 | |
| 329 | if (spi->mode & SPI_CPOL) |
| 330 | spifmt |= SPIFMT_POLARITY_MASK; |
| 331 | |
| 332 | if (!(spi->mode & SPI_CPHA)) |
| 333 | spifmt |= SPIFMT_PHASE_MASK; |
| 334 | |
| 335 | /* |
| 336 | * Version 1 hardware supports two basic SPI modes: |
| 337 | * - Standard SPI mode uses 4 pins, with chipselect |
| 338 | * - 3 pin SPI is a 4 pin variant without CS (SPI_NO_CS) |
| 339 | * (distinct from SPI_3WIRE, with just one data wire; |
| 340 | * or similar variants without MOSI or without MISO) |
| 341 | * |
| 342 | * Version 2 hardware supports an optional handshaking signal, |
| 343 | * so it can support two more modes: |
| 344 | * - 5 pin SPI variant is standard SPI plus SPI_READY |
| 345 | * - 4 pin with enable is (SPI_READY | SPI_NO_CS) |
| 346 | */ |
| 347 | |
Sekhar Nori | 212d4b6 | 2010-10-11 10:41:39 +0530 | [diff] [blame] | 348 | if (dspi->version == SPI_VERSION_2) { |
Brian Niebuhr | 25f3351 | 2010-08-19 12:15:22 +0530 | [diff] [blame] | 349 | |
Brian Niebuhr | 7abbf23 | 2010-08-19 15:07:38 +0530 | [diff] [blame] | 350 | u32 delay = 0; |
| 351 | |
Brian Niebuhr | 25f3351 | 2010-08-19 12:15:22 +0530 | [diff] [blame] | 352 | spifmt |= ((spicfg->wdelay << SPIFMT_WDELAY_SHIFT) |
| 353 | & SPIFMT_WDELAY_MASK); |
| 354 | |
| 355 | if (spicfg->odd_parity) |
| 356 | spifmt |= SPIFMT_ODD_PARITY_MASK; |
| 357 | |
| 358 | if (spicfg->parity_enable) |
| 359 | spifmt |= SPIFMT_PARITYENA_MASK; |
| 360 | |
Brian Niebuhr | 7abbf23 | 2010-08-19 15:07:38 +0530 | [diff] [blame] | 361 | if (spicfg->timer_disable) { |
Brian Niebuhr | 25f3351 | 2010-08-19 12:15:22 +0530 | [diff] [blame] | 362 | spifmt |= SPIFMT_DISTIMER_MASK; |
Brian Niebuhr | 7abbf23 | 2010-08-19 15:07:38 +0530 | [diff] [blame] | 363 | } else { |
| 364 | delay |= (spicfg->c2tdelay << SPIDELAY_C2TDELAY_SHIFT) |
| 365 | & SPIDELAY_C2TDELAY_MASK; |
| 366 | delay |= (spicfg->t2cdelay << SPIDELAY_T2CDELAY_SHIFT) |
| 367 | & SPIDELAY_T2CDELAY_MASK; |
| 368 | } |
Brian Niebuhr | 25f3351 | 2010-08-19 12:15:22 +0530 | [diff] [blame] | 369 | |
Brian Niebuhr | 7abbf23 | 2010-08-19 15:07:38 +0530 | [diff] [blame] | 370 | if (spi->mode & SPI_READY) { |
Brian Niebuhr | 25f3351 | 2010-08-19 12:15:22 +0530 | [diff] [blame] | 371 | spifmt |= SPIFMT_WAITENA_MASK; |
Brian Niebuhr | 7abbf23 | 2010-08-19 15:07:38 +0530 | [diff] [blame] | 372 | delay |= (spicfg->t2edelay << SPIDELAY_T2EDELAY_SHIFT) |
| 373 | & SPIDELAY_T2EDELAY_MASK; |
| 374 | delay |= (spicfg->c2edelay << SPIDELAY_C2EDELAY_SHIFT) |
| 375 | & SPIDELAY_C2EDELAY_MASK; |
| 376 | } |
| 377 | |
Sekhar Nori | 212d4b6 | 2010-10-11 10:41:39 +0530 | [diff] [blame] | 378 | iowrite32(delay, dspi->base + SPIDELAY); |
Brian Niebuhr | 25f3351 | 2010-08-19 12:15:22 +0530 | [diff] [blame] | 379 | } |
| 380 | |
Sekhar Nori | 212d4b6 | 2010-10-11 10:41:39 +0530 | [diff] [blame] | 381 | iowrite32(spifmt, dspi->base + SPIFMT0); |
Sandeep Paulraj | 358934a | 2009-12-16 22:02:18 +0000 | [diff] [blame] | 382 | |
| 383 | return 0; |
| 384 | } |
| 385 | |
Sandeep Paulraj | 358934a | 2009-12-16 22:02:18 +0000 | [diff] [blame] | 386 | /** |
| 387 | * davinci_spi_setup - This functions will set default transfer method |
| 388 | * @spi: spi device on which data transfer to be done |
| 389 | * |
| 390 | * This functions sets the default transfer method. |
| 391 | */ |
Sandeep Paulraj | 358934a | 2009-12-16 22:02:18 +0000 | [diff] [blame] | 392 | static int davinci_spi_setup(struct spi_device *spi) |
| 393 | { |
Brian Niebuhr | b23a5d4 | 2010-09-24 18:53:32 +0530 | [diff] [blame] | 394 | int retval = 0; |
Sekhar Nori | 212d4b6 | 2010-10-11 10:41:39 +0530 | [diff] [blame] | 395 | struct davinci_spi *dspi; |
Brian Niebuhr | be88471 | 2010-09-03 12:15:28 +0530 | [diff] [blame] | 396 | struct davinci_spi_platform_data *pdata; |
Sandeep Paulraj | 358934a | 2009-12-16 22:02:18 +0000 | [diff] [blame] | 397 | |
Sekhar Nori | 212d4b6 | 2010-10-11 10:41:39 +0530 | [diff] [blame] | 398 | dspi = spi_master_get_devdata(spi->master); |
| 399 | pdata = dspi->pdata; |
Sandeep Paulraj | 358934a | 2009-12-16 22:02:18 +0000 | [diff] [blame] | 400 | |
| 401 | /* if bits per word length is zero then set it default 8 */ |
| 402 | if (!spi->bits_per_word) |
| 403 | spi->bits_per_word = 8; |
| 404 | |
Brian Niebuhr | be88471 | 2010-09-03 12:15:28 +0530 | [diff] [blame] | 405 | if (!(spi->mode & SPI_NO_CS)) { |
| 406 | if ((pdata->chip_sel == NULL) || |
| 407 | (pdata->chip_sel[spi->chip_select] == SPI_INTERN_CS)) |
Sekhar Nori | 212d4b6 | 2010-10-11 10:41:39 +0530 | [diff] [blame] | 408 | set_io_bits(dspi->base + SPIPC0, 1 << spi->chip_select); |
Brian Niebuhr | be88471 | 2010-09-03 12:15:28 +0530 | [diff] [blame] | 409 | |
| 410 | } |
| 411 | |
| 412 | if (spi->mode & SPI_READY) |
Sekhar Nori | 212d4b6 | 2010-10-11 10:41:39 +0530 | [diff] [blame] | 413 | set_io_bits(dspi->base + SPIPC0, SPIPC0_SPIENA_MASK); |
Brian Niebuhr | be88471 | 2010-09-03 12:15:28 +0530 | [diff] [blame] | 414 | |
| 415 | if (spi->mode & SPI_LOOP) |
Sekhar Nori | 212d4b6 | 2010-10-11 10:41:39 +0530 | [diff] [blame] | 416 | set_io_bits(dspi->base + SPIGCR1, SPIGCR1_LOOPBACK_MASK); |
Brian Niebuhr | be88471 | 2010-09-03 12:15:28 +0530 | [diff] [blame] | 417 | else |
Sekhar Nori | 212d4b6 | 2010-10-11 10:41:39 +0530 | [diff] [blame] | 418 | clear_io_bits(dspi->base + SPIGCR1, SPIGCR1_LOOPBACK_MASK); |
Brian Niebuhr | be88471 | 2010-09-03 12:15:28 +0530 | [diff] [blame] | 419 | |
Sandeep Paulraj | 358934a | 2009-12-16 22:02:18 +0000 | [diff] [blame] | 420 | return retval; |
| 421 | } |
| 422 | |
Sekhar Nori | 212d4b6 | 2010-10-11 10:41:39 +0530 | [diff] [blame] | 423 | static int davinci_spi_check_error(struct davinci_spi *dspi, int int_status) |
Sandeep Paulraj | 358934a | 2009-12-16 22:02:18 +0000 | [diff] [blame] | 424 | { |
Sekhar Nori | 212d4b6 | 2010-10-11 10:41:39 +0530 | [diff] [blame] | 425 | struct device *sdev = dspi->bitbang.master->dev.parent; |
Sandeep Paulraj | 358934a | 2009-12-16 22:02:18 +0000 | [diff] [blame] | 426 | |
| 427 | if (int_status & SPIFLG_TIMEOUT_MASK) { |
| 428 | dev_dbg(sdev, "SPI Time-out Error\n"); |
| 429 | return -ETIMEDOUT; |
| 430 | } |
| 431 | if (int_status & SPIFLG_DESYNC_MASK) { |
| 432 | dev_dbg(sdev, "SPI Desynchronization Error\n"); |
| 433 | return -EIO; |
| 434 | } |
| 435 | if (int_status & SPIFLG_BITERR_MASK) { |
| 436 | dev_dbg(sdev, "SPI Bit error\n"); |
| 437 | return -EIO; |
| 438 | } |
| 439 | |
Sekhar Nori | 212d4b6 | 2010-10-11 10:41:39 +0530 | [diff] [blame] | 440 | if (dspi->version == SPI_VERSION_2) { |
Sandeep Paulraj | 358934a | 2009-12-16 22:02:18 +0000 | [diff] [blame] | 441 | if (int_status & SPIFLG_DLEN_ERR_MASK) { |
| 442 | dev_dbg(sdev, "SPI Data Length Error\n"); |
| 443 | return -EIO; |
| 444 | } |
| 445 | if (int_status & SPIFLG_PARERR_MASK) { |
| 446 | dev_dbg(sdev, "SPI Parity Error\n"); |
| 447 | return -EIO; |
| 448 | } |
| 449 | if (int_status & SPIFLG_OVRRUN_MASK) { |
| 450 | dev_dbg(sdev, "SPI Data Overrun error\n"); |
| 451 | return -EIO; |
| 452 | } |
Sandeep Paulraj | 358934a | 2009-12-16 22:02:18 +0000 | [diff] [blame] | 453 | if (int_status & SPIFLG_BUF_INIT_ACTIVE_MASK) { |
| 454 | dev_dbg(sdev, "SPI Buffer Init Active\n"); |
| 455 | return -EBUSY; |
| 456 | } |
| 457 | } |
| 458 | |
| 459 | return 0; |
| 460 | } |
| 461 | |
| 462 | /** |
Brian Niebuhr | e0d205e | 2010-09-02 16:52:06 +0530 | [diff] [blame] | 463 | * davinci_spi_process_events - check for and handle any SPI controller events |
Sekhar Nori | 212d4b6 | 2010-10-11 10:41:39 +0530 | [diff] [blame] | 464 | * @dspi: the controller data |
Brian Niebuhr | e0d205e | 2010-09-02 16:52:06 +0530 | [diff] [blame] | 465 | * |
| 466 | * This function will check the SPIFLG register and handle any events that are |
| 467 | * detected there |
| 468 | */ |
Sekhar Nori | 212d4b6 | 2010-10-11 10:41:39 +0530 | [diff] [blame] | 469 | static int davinci_spi_process_events(struct davinci_spi *dspi) |
Brian Niebuhr | e0d205e | 2010-09-02 16:52:06 +0530 | [diff] [blame] | 470 | { |
Sekhar Nori | 212d4b6 | 2010-10-11 10:41:39 +0530 | [diff] [blame] | 471 | u32 buf, status, errors = 0, spidat1; |
Brian Niebuhr | e0d205e | 2010-09-02 16:52:06 +0530 | [diff] [blame] | 472 | |
Sekhar Nori | 212d4b6 | 2010-10-11 10:41:39 +0530 | [diff] [blame] | 473 | buf = ioread32(dspi->base + SPIBUF); |
Brian Niebuhr | e0d205e | 2010-09-02 16:52:06 +0530 | [diff] [blame] | 474 | |
Sekhar Nori | 212d4b6 | 2010-10-11 10:41:39 +0530 | [diff] [blame] | 475 | if (dspi->rcount > 0 && !(buf & SPIBUF_RXEMPTY_MASK)) { |
| 476 | dspi->get_rx(buf & 0xFFFF, dspi); |
| 477 | dspi->rcount--; |
Brian Niebuhr | e0d205e | 2010-09-02 16:52:06 +0530 | [diff] [blame] | 478 | } |
| 479 | |
Sekhar Nori | 212d4b6 | 2010-10-11 10:41:39 +0530 | [diff] [blame] | 480 | status = ioread32(dspi->base + SPIFLG); |
Brian Niebuhr | e0d205e | 2010-09-02 16:52:06 +0530 | [diff] [blame] | 481 | |
| 482 | if (unlikely(status & SPIFLG_ERROR_MASK)) { |
| 483 | errors = status & SPIFLG_ERROR_MASK; |
| 484 | goto out; |
| 485 | } |
| 486 | |
Sekhar Nori | 212d4b6 | 2010-10-11 10:41:39 +0530 | [diff] [blame] | 487 | if (dspi->wcount > 0 && !(buf & SPIBUF_TXFULL_MASK)) { |
| 488 | spidat1 = ioread32(dspi->base + SPIDAT1); |
| 489 | dspi->wcount--; |
| 490 | spidat1 &= ~0xFFFF; |
| 491 | spidat1 |= 0xFFFF & dspi->get_tx(dspi); |
| 492 | iowrite32(spidat1, dspi->base + SPIDAT1); |
Brian Niebuhr | e0d205e | 2010-09-02 16:52:06 +0530 | [diff] [blame] | 493 | } |
| 494 | |
| 495 | out: |
| 496 | return errors; |
| 497 | } |
| 498 | |
Brian Niebuhr | 87467bd | 2010-10-06 17:03:10 +0530 | [diff] [blame] | 499 | static void davinci_spi_dma_callback(unsigned lch, u16 status, void *data) |
| 500 | { |
Sekhar Nori | 212d4b6 | 2010-10-11 10:41:39 +0530 | [diff] [blame] | 501 | struct davinci_spi *dspi = data; |
| 502 | struct davinci_spi_dma *dma = &dspi->dma; |
Brian Niebuhr | 87467bd | 2010-10-06 17:03:10 +0530 | [diff] [blame] | 503 | |
| 504 | edma_stop(lch); |
| 505 | |
| 506 | if (status == DMA_COMPLETE) { |
Sekhar Nori | 212d4b6 | 2010-10-11 10:41:39 +0530 | [diff] [blame] | 507 | if (lch == dma->rx_channel) |
| 508 | dspi->rcount = 0; |
| 509 | if (lch == dma->tx_channel) |
| 510 | dspi->wcount = 0; |
Brian Niebuhr | 87467bd | 2010-10-06 17:03:10 +0530 | [diff] [blame] | 511 | } |
| 512 | |
Sekhar Nori | 212d4b6 | 2010-10-11 10:41:39 +0530 | [diff] [blame] | 513 | if ((!dspi->wcount && !dspi->rcount) || (status != DMA_COMPLETE)) |
| 514 | complete(&dspi->done); |
Brian Niebuhr | 87467bd | 2010-10-06 17:03:10 +0530 | [diff] [blame] | 515 | } |
| 516 | |
Brian Niebuhr | e0d205e | 2010-09-02 16:52:06 +0530 | [diff] [blame] | 517 | /** |
Sandeep Paulraj | 358934a | 2009-12-16 22:02:18 +0000 | [diff] [blame] | 518 | * davinci_spi_bufs - functions which will handle transfer data |
| 519 | * @spi: spi device on which data transfer to be done |
| 520 | * @t: spi transfer in which transfer info is filled |
| 521 | * |
| 522 | * This function will put data to be transferred into data register |
| 523 | * of SPI controller and then wait until the completion will be marked |
| 524 | * by the IRQ Handler. |
| 525 | */ |
Brian Niebuhr | 87467bd | 2010-10-06 17:03:10 +0530 | [diff] [blame] | 526 | static int davinci_spi_bufs(struct spi_device *spi, struct spi_transfer *t) |
Sandeep Paulraj | 358934a | 2009-12-16 22:02:18 +0000 | [diff] [blame] | 527 | { |
Sekhar Nori | 212d4b6 | 2010-10-11 10:41:39 +0530 | [diff] [blame] | 528 | struct davinci_spi *dspi; |
Brian Niebuhr | 87467bd | 2010-10-06 17:03:10 +0530 | [diff] [blame] | 529 | int data_type, ret; |
Sekhar Nori | 212d4b6 | 2010-10-11 10:41:39 +0530 | [diff] [blame] | 530 | u32 tx_data, spidat1; |
Brian Niebuhr | 839c996 | 2010-08-23 16:39:19 +0530 | [diff] [blame] | 531 | u32 errors = 0; |
Brian Niebuhr | e0d205e | 2010-09-02 16:52:06 +0530 | [diff] [blame] | 532 | struct davinci_spi_config *spicfg; |
Sandeep Paulraj | 358934a | 2009-12-16 22:02:18 +0000 | [diff] [blame] | 533 | struct davinci_spi_platform_data *pdata; |
Brian Niebuhr | 87467bd | 2010-10-06 17:03:10 +0530 | [diff] [blame] | 534 | unsigned uninitialized_var(rx_buf_count); |
| 535 | struct device *sdev; |
Sandeep Paulraj | 358934a | 2009-12-16 22:02:18 +0000 | [diff] [blame] | 536 | |
Sekhar Nori | 212d4b6 | 2010-10-11 10:41:39 +0530 | [diff] [blame] | 537 | dspi = spi_master_get_devdata(spi->master); |
| 538 | pdata = dspi->pdata; |
Brian Niebuhr | e0d205e | 2010-09-02 16:52:06 +0530 | [diff] [blame] | 539 | spicfg = (struct davinci_spi_config *)spi->controller_data; |
| 540 | if (!spicfg) |
| 541 | spicfg = &davinci_spi_default_cfg; |
Sekhar Nori | 212d4b6 | 2010-10-11 10:41:39 +0530 | [diff] [blame] | 542 | sdev = dspi->bitbang.master->dev.parent; |
Brian Niebuhr | 87467bd | 2010-10-06 17:03:10 +0530 | [diff] [blame] | 543 | |
| 544 | /* convert len to words based on bits_per_word */ |
Sekhar Nori | 212d4b6 | 2010-10-11 10:41:39 +0530 | [diff] [blame] | 545 | data_type = dspi->bytes_per_word[spi->chip_select]; |
Sandeep Paulraj | 358934a | 2009-12-16 22:02:18 +0000 | [diff] [blame] | 546 | |
Sekhar Nori | 212d4b6 | 2010-10-11 10:41:39 +0530 | [diff] [blame] | 547 | dspi->tx = t->tx_buf; |
| 548 | dspi->rx = t->rx_buf; |
| 549 | dspi->wcount = t->len / data_type; |
| 550 | dspi->rcount = dspi->wcount; |
Brian Niebuhr | 7978b8c | 2010-08-13 10:11:03 +0530 | [diff] [blame] | 551 | |
Sekhar Nori | 212d4b6 | 2010-10-11 10:41:39 +0530 | [diff] [blame] | 552 | spidat1 = ioread32(dspi->base + SPIDAT1); |
Brian Niebuhr | 839c996 | 2010-08-23 16:39:19 +0530 | [diff] [blame] | 553 | |
Sekhar Nori | 212d4b6 | 2010-10-11 10:41:39 +0530 | [diff] [blame] | 554 | clear_io_bits(dspi->base + SPIGCR1, SPIGCR1_POWERDOWN_MASK); |
| 555 | set_io_bits(dspi->base + SPIGCR1, SPIGCR1_SPIENA_MASK); |
Sandeep Paulraj | 358934a | 2009-12-16 22:02:18 +0000 | [diff] [blame] | 556 | |
Sekhar Nori | 212d4b6 | 2010-10-11 10:41:39 +0530 | [diff] [blame] | 557 | INIT_COMPLETION(dspi->done); |
Brian Niebuhr | 87467bd | 2010-10-06 17:03:10 +0530 | [diff] [blame] | 558 | |
| 559 | if (spicfg->io_type == SPI_IO_TYPE_INTR) |
Sekhar Nori | 212d4b6 | 2010-10-11 10:41:39 +0530 | [diff] [blame] | 560 | set_io_bits(dspi->base + SPIINT, SPIINT_MASKINT); |
Brian Niebuhr | 87467bd | 2010-10-06 17:03:10 +0530 | [diff] [blame] | 561 | |
| 562 | if (spicfg->io_type != SPI_IO_TYPE_DMA) { |
| 563 | /* start the transfer */ |
Sekhar Nori | 212d4b6 | 2010-10-11 10:41:39 +0530 | [diff] [blame] | 564 | dspi->wcount--; |
| 565 | tx_data = dspi->get_tx(dspi); |
| 566 | spidat1 &= 0xFFFF0000; |
| 567 | spidat1 |= tx_data & 0xFFFF; |
| 568 | iowrite32(spidat1, dspi->base + SPIDAT1); |
Brian Niebuhr | 87467bd | 2010-10-06 17:03:10 +0530 | [diff] [blame] | 569 | } else { |
Sekhar Nori | 212d4b6 | 2010-10-11 10:41:39 +0530 | [diff] [blame] | 570 | struct davinci_spi_dma *dma; |
Brian Niebuhr | 87467bd | 2010-10-06 17:03:10 +0530 | [diff] [blame] | 571 | unsigned long tx_reg, rx_reg; |
| 572 | struct edmacc_param param; |
| 573 | void *rx_buf; |
Michael Williamson | b1178b2 | 2011-03-14 11:49:02 -0400 | [diff] [blame^] | 574 | int b, c; |
Brian Niebuhr | 87467bd | 2010-10-06 17:03:10 +0530 | [diff] [blame] | 575 | |
Sekhar Nori | 212d4b6 | 2010-10-11 10:41:39 +0530 | [diff] [blame] | 576 | dma = &dspi->dma; |
Brian Niebuhr | 87467bd | 2010-10-06 17:03:10 +0530 | [diff] [blame] | 577 | |
Sekhar Nori | 212d4b6 | 2010-10-11 10:41:39 +0530 | [diff] [blame] | 578 | tx_reg = (unsigned long)dspi->pbase + SPIDAT1; |
| 579 | rx_reg = (unsigned long)dspi->pbase + SPIBUF; |
Brian Niebuhr | 87467bd | 2010-10-06 17:03:10 +0530 | [diff] [blame] | 580 | |
| 581 | /* |
| 582 | * Transmit DMA setup |
| 583 | * |
| 584 | * If there is transmit data, map the transmit buffer, set it |
| 585 | * as the source of data and set the source B index to data |
| 586 | * size. If there is no transmit data, set the transmit register |
| 587 | * as the source of data, and set the source B index to zero. |
| 588 | * |
| 589 | * The destination is always the transmit register itself. And |
| 590 | * the destination never increments. |
| 591 | */ |
| 592 | |
| 593 | if (t->tx_buf) { |
| 594 | t->tx_dma = dma_map_single(&spi->dev, (void *)t->tx_buf, |
Michael Williamson | d09519e | 2011-03-13 10:34:21 -0400 | [diff] [blame] | 595 | t->len, DMA_TO_DEVICE); |
Brian Niebuhr | 87467bd | 2010-10-06 17:03:10 +0530 | [diff] [blame] | 596 | if (dma_mapping_error(&spi->dev, t->tx_dma)) { |
| 597 | dev_dbg(sdev, "Unable to DMA map %d bytes" |
Michael Williamson | d09519e | 2011-03-13 10:34:21 -0400 | [diff] [blame] | 598 | "TX buffer\n", t->len); |
Brian Niebuhr | 87467bd | 2010-10-06 17:03:10 +0530 | [diff] [blame] | 599 | return -ENOMEM; |
| 600 | } |
| 601 | } |
| 602 | |
Michael Williamson | b1178b2 | 2011-03-14 11:49:02 -0400 | [diff] [blame^] | 603 | /* |
| 604 | * If number of words is greater than 65535, then we need |
| 605 | * to configure a 3 dimension transfer. Use the BCNTRLD |
| 606 | * feature to allow for transfers that aren't even multiples |
| 607 | * of 65535 (or any other possible b size) by first transferring |
| 608 | * the remainder amount then grabbing the next N blocks of |
| 609 | * 65535 words. |
| 610 | */ |
| 611 | |
| 612 | c = dspi->wcount / (SZ_64K - 1); /* N 65535 Blocks */ |
| 613 | b = dspi->wcount - c * (SZ_64K - 1); /* Remainder */ |
| 614 | if (b) |
| 615 | c++; |
| 616 | else |
| 617 | b = SZ_64K - 1; |
| 618 | |
Sekhar Nori | 212d4b6 | 2010-10-11 10:41:39 +0530 | [diff] [blame] | 619 | param.opt = TCINTEN | EDMA_TCC(dma->tx_channel); |
Brian Niebuhr | 87467bd | 2010-10-06 17:03:10 +0530 | [diff] [blame] | 620 | param.src = t->tx_buf ? t->tx_dma : tx_reg; |
Michael Williamson | b1178b2 | 2011-03-14 11:49:02 -0400 | [diff] [blame^] | 621 | param.a_b_cnt = b << 16 | data_type; |
Brian Niebuhr | 87467bd | 2010-10-06 17:03:10 +0530 | [diff] [blame] | 622 | param.dst = tx_reg; |
| 623 | param.src_dst_bidx = t->tx_buf ? data_type : 0; |
Michael Williamson | b1178b2 | 2011-03-14 11:49:02 -0400 | [diff] [blame^] | 624 | param.link_bcntrld = 0xffffffff; |
| 625 | param.src_dst_cidx = t->tx_buf ? data_type : 0; |
| 626 | param.ccnt = c; |
Sekhar Nori | 212d4b6 | 2010-10-11 10:41:39 +0530 | [diff] [blame] | 627 | edma_write_slot(dma->tx_channel, ¶m); |
| 628 | edma_link(dma->tx_channel, dma->dummy_param_slot); |
Brian Niebuhr | 87467bd | 2010-10-06 17:03:10 +0530 | [diff] [blame] | 629 | |
| 630 | /* |
| 631 | * Receive DMA setup |
| 632 | * |
| 633 | * If there is receive buffer, use it to receive data. If there |
| 634 | * is none provided, use a temporary receive buffer. Set the |
| 635 | * destination B index to 0 so effectively only one byte is used |
| 636 | * in the temporary buffer (address does not increment). |
| 637 | * |
| 638 | * The source of receive data is the receive data register. The |
| 639 | * source address never increments. |
| 640 | */ |
| 641 | |
| 642 | if (t->rx_buf) { |
| 643 | rx_buf = t->rx_buf; |
Michael Williamson | d09519e | 2011-03-13 10:34:21 -0400 | [diff] [blame] | 644 | rx_buf_count = t->len; |
Brian Niebuhr | 87467bd | 2010-10-06 17:03:10 +0530 | [diff] [blame] | 645 | } else { |
Sekhar Nori | 212d4b6 | 2010-10-11 10:41:39 +0530 | [diff] [blame] | 646 | rx_buf = dspi->rx_tmp_buf; |
| 647 | rx_buf_count = sizeof(dspi->rx_tmp_buf); |
Brian Niebuhr | 87467bd | 2010-10-06 17:03:10 +0530 | [diff] [blame] | 648 | } |
| 649 | |
| 650 | t->rx_dma = dma_map_single(&spi->dev, rx_buf, rx_buf_count, |
| 651 | DMA_FROM_DEVICE); |
| 652 | if (dma_mapping_error(&spi->dev, t->rx_dma)) { |
| 653 | dev_dbg(sdev, "Couldn't DMA map a %d bytes RX buffer\n", |
| 654 | rx_buf_count); |
| 655 | if (t->tx_buf) |
Michael Williamson | d09519e | 2011-03-13 10:34:21 -0400 | [diff] [blame] | 656 | dma_unmap_single(NULL, t->tx_dma, t->len, |
Sekhar Nori | 212d4b6 | 2010-10-11 10:41:39 +0530 | [diff] [blame] | 657 | DMA_TO_DEVICE); |
Brian Niebuhr | 87467bd | 2010-10-06 17:03:10 +0530 | [diff] [blame] | 658 | return -ENOMEM; |
| 659 | } |
| 660 | |
Sekhar Nori | 212d4b6 | 2010-10-11 10:41:39 +0530 | [diff] [blame] | 661 | param.opt = TCINTEN | EDMA_TCC(dma->rx_channel); |
Brian Niebuhr | 87467bd | 2010-10-06 17:03:10 +0530 | [diff] [blame] | 662 | param.src = rx_reg; |
Michael Williamson | b1178b2 | 2011-03-14 11:49:02 -0400 | [diff] [blame^] | 663 | param.a_b_cnt = b << 16 | data_type; |
Brian Niebuhr | 87467bd | 2010-10-06 17:03:10 +0530 | [diff] [blame] | 664 | param.dst = t->rx_dma; |
| 665 | param.src_dst_bidx = (t->rx_buf ? data_type : 0) << 16; |
Michael Williamson | b1178b2 | 2011-03-14 11:49:02 -0400 | [diff] [blame^] | 666 | param.link_bcntrld = 0xffffffff; |
| 667 | param.src_dst_cidx = (t->rx_buf ? data_type : 0) << 16; |
| 668 | param.ccnt = c; |
Sekhar Nori | 212d4b6 | 2010-10-11 10:41:39 +0530 | [diff] [blame] | 669 | edma_write_slot(dma->rx_channel, ¶m); |
Brian Niebuhr | 87467bd | 2010-10-06 17:03:10 +0530 | [diff] [blame] | 670 | |
| 671 | if (pdata->cshold_bug) |
Sekhar Nori | 212d4b6 | 2010-10-11 10:41:39 +0530 | [diff] [blame] | 672 | iowrite16(spidat1 >> 16, dspi->base + SPIDAT1 + 2); |
Brian Niebuhr | 87467bd | 2010-10-06 17:03:10 +0530 | [diff] [blame] | 673 | |
Sekhar Nori | 212d4b6 | 2010-10-11 10:41:39 +0530 | [diff] [blame] | 674 | edma_start(dma->rx_channel); |
| 675 | edma_start(dma->tx_channel); |
| 676 | set_io_bits(dspi->base + SPIINT, SPIINT_DMA_REQ_EN); |
Brian Niebuhr | e0d205e | 2010-09-02 16:52:06 +0530 | [diff] [blame] | 677 | } |
Brian Niebuhr | cf90fe7 | 2010-08-20 17:02:49 +0530 | [diff] [blame] | 678 | |
Brian Niebuhr | e0d205e | 2010-09-02 16:52:06 +0530 | [diff] [blame] | 679 | /* Wait for the transfer to complete */ |
Brian Niebuhr | 87467bd | 2010-10-06 17:03:10 +0530 | [diff] [blame] | 680 | if (spicfg->io_type != SPI_IO_TYPE_POLL) { |
Sekhar Nori | 212d4b6 | 2010-10-11 10:41:39 +0530 | [diff] [blame] | 681 | wait_for_completion_interruptible(&(dspi->done)); |
Brian Niebuhr | e0d205e | 2010-09-02 16:52:06 +0530 | [diff] [blame] | 682 | } else { |
Sekhar Nori | 212d4b6 | 2010-10-11 10:41:39 +0530 | [diff] [blame] | 683 | while (dspi->rcount > 0 || dspi->wcount > 0) { |
| 684 | errors = davinci_spi_process_events(dspi); |
Brian Niebuhr | e0d205e | 2010-09-02 16:52:06 +0530 | [diff] [blame] | 685 | if (errors) |
| 686 | break; |
| 687 | cpu_relax(); |
Sandeep Paulraj | 358934a | 2009-12-16 22:02:18 +0000 | [diff] [blame] | 688 | } |
| 689 | } |
| 690 | |
Sekhar Nori | 212d4b6 | 2010-10-11 10:41:39 +0530 | [diff] [blame] | 691 | clear_io_bits(dspi->base + SPIINT, SPIINT_MASKALL); |
Brian Niebuhr | 87467bd | 2010-10-06 17:03:10 +0530 | [diff] [blame] | 692 | if (spicfg->io_type == SPI_IO_TYPE_DMA) { |
| 693 | |
| 694 | if (t->tx_buf) |
Michael Williamson | d09519e | 2011-03-13 10:34:21 -0400 | [diff] [blame] | 695 | dma_unmap_single(NULL, t->tx_dma, t->len, |
Brian Niebuhr | 87467bd | 2010-10-06 17:03:10 +0530 | [diff] [blame] | 696 | DMA_TO_DEVICE); |
| 697 | |
| 698 | dma_unmap_single(NULL, t->rx_dma, rx_buf_count, |
| 699 | DMA_FROM_DEVICE); |
| 700 | |
Sekhar Nori | 212d4b6 | 2010-10-11 10:41:39 +0530 | [diff] [blame] | 701 | clear_io_bits(dspi->base + SPIINT, SPIINT_DMA_REQ_EN); |
Brian Niebuhr | 87467bd | 2010-10-06 17:03:10 +0530 | [diff] [blame] | 702 | } |
Brian Niebuhr | e0d205e | 2010-09-02 16:52:06 +0530 | [diff] [blame] | 703 | |
Sekhar Nori | 212d4b6 | 2010-10-11 10:41:39 +0530 | [diff] [blame] | 704 | clear_io_bits(dspi->base + SPIGCR1, SPIGCR1_SPIENA_MASK); |
| 705 | set_io_bits(dspi->base + SPIGCR1, SPIGCR1_POWERDOWN_MASK); |
Brian Niebuhr | 3f27b57 | 2010-10-06 18:25:43 +0530 | [diff] [blame] | 706 | |
Sandeep Paulraj | 358934a | 2009-12-16 22:02:18 +0000 | [diff] [blame] | 707 | /* |
| 708 | * Check for bit error, desync error,parity error,timeout error and |
| 709 | * receive overflow errors |
| 710 | */ |
Brian Niebuhr | 839c996 | 2010-08-23 16:39:19 +0530 | [diff] [blame] | 711 | if (errors) { |
Sekhar Nori | 212d4b6 | 2010-10-11 10:41:39 +0530 | [diff] [blame] | 712 | ret = davinci_spi_check_error(dspi, errors); |
Brian Niebuhr | 839c996 | 2010-08-23 16:39:19 +0530 | [diff] [blame] | 713 | WARN(!ret, "%s: error reported but no error found!\n", |
| 714 | dev_name(&spi->dev)); |
Sandeep Paulraj | 358934a | 2009-12-16 22:02:18 +0000 | [diff] [blame] | 715 | return ret; |
Brian Niebuhr | 839c996 | 2010-08-23 16:39:19 +0530 | [diff] [blame] | 716 | } |
Sandeep Paulraj | 358934a | 2009-12-16 22:02:18 +0000 | [diff] [blame] | 717 | |
Sekhar Nori | 212d4b6 | 2010-10-11 10:41:39 +0530 | [diff] [blame] | 718 | if (dspi->rcount != 0 || dspi->wcount != 0) { |
Brian Niebuhr | 87467bd | 2010-10-06 17:03:10 +0530 | [diff] [blame] | 719 | dev_err(sdev, "SPI data transfer error\n"); |
| 720 | return -EIO; |
| 721 | } |
| 722 | |
Sandeep Paulraj | 358934a | 2009-12-16 22:02:18 +0000 | [diff] [blame] | 723 | return t->len; |
| 724 | } |
| 725 | |
Brian Niebuhr | e0d205e | 2010-09-02 16:52:06 +0530 | [diff] [blame] | 726 | /** |
| 727 | * davinci_spi_irq - Interrupt handler for SPI Master Controller |
| 728 | * @irq: IRQ number for this SPI Master |
| 729 | * @context_data: structure for SPI Master controller davinci_spi |
| 730 | * |
| 731 | * ISR will determine that interrupt arrives either for READ or WRITE command. |
| 732 | * According to command it will do the appropriate action. It will check |
| 733 | * transfer length and if it is not zero then dispatch transfer command again. |
| 734 | * If transfer length is zero then it will indicate the COMPLETION so that |
| 735 | * davinci_spi_bufs function can go ahead. |
| 736 | */ |
Sekhar Nori | 212d4b6 | 2010-10-11 10:41:39 +0530 | [diff] [blame] | 737 | static irqreturn_t davinci_spi_irq(s32 irq, void *data) |
Brian Niebuhr | e0d205e | 2010-09-02 16:52:06 +0530 | [diff] [blame] | 738 | { |
Sekhar Nori | 212d4b6 | 2010-10-11 10:41:39 +0530 | [diff] [blame] | 739 | struct davinci_spi *dspi = data; |
Brian Niebuhr | e0d205e | 2010-09-02 16:52:06 +0530 | [diff] [blame] | 740 | int status; |
| 741 | |
Sekhar Nori | 212d4b6 | 2010-10-11 10:41:39 +0530 | [diff] [blame] | 742 | status = davinci_spi_process_events(dspi); |
Brian Niebuhr | e0d205e | 2010-09-02 16:52:06 +0530 | [diff] [blame] | 743 | if (unlikely(status != 0)) |
Sekhar Nori | 212d4b6 | 2010-10-11 10:41:39 +0530 | [diff] [blame] | 744 | clear_io_bits(dspi->base + SPIINT, SPIINT_MASKINT); |
Brian Niebuhr | e0d205e | 2010-09-02 16:52:06 +0530 | [diff] [blame] | 745 | |
Sekhar Nori | 212d4b6 | 2010-10-11 10:41:39 +0530 | [diff] [blame] | 746 | if ((!dspi->rcount && !dspi->wcount) || status) |
| 747 | complete(&dspi->done); |
Brian Niebuhr | e0d205e | 2010-09-02 16:52:06 +0530 | [diff] [blame] | 748 | |
| 749 | return IRQ_HANDLED; |
| 750 | } |
| 751 | |
Sekhar Nori | 212d4b6 | 2010-10-11 10:41:39 +0530 | [diff] [blame] | 752 | static int davinci_spi_request_dma(struct davinci_spi *dspi) |
Sekhar Nori | 903ca25 | 2010-10-01 14:51:40 +0530 | [diff] [blame] | 753 | { |
| 754 | int r; |
Sekhar Nori | 212d4b6 | 2010-10-11 10:41:39 +0530 | [diff] [blame] | 755 | struct davinci_spi_dma *dma = &dspi->dma; |
Sekhar Nori | 903ca25 | 2010-10-01 14:51:40 +0530 | [diff] [blame] | 756 | |
Sekhar Nori | 212d4b6 | 2010-10-11 10:41:39 +0530 | [diff] [blame] | 757 | r = edma_alloc_channel(dma->rx_channel, davinci_spi_dma_callback, dspi, |
| 758 | dma->eventq); |
Sekhar Nori | 903ca25 | 2010-10-01 14:51:40 +0530 | [diff] [blame] | 759 | if (r < 0) { |
| 760 | pr_err("Unable to request DMA channel for SPI RX\n"); |
Brian Niebuhr | 523c37e | 2010-10-04 17:35:34 +0530 | [diff] [blame] | 761 | r = -EAGAIN; |
| 762 | goto rx_dma_failed; |
Sekhar Nori | 903ca25 | 2010-10-01 14:51:40 +0530 | [diff] [blame] | 763 | } |
| 764 | |
Sekhar Nori | 212d4b6 | 2010-10-11 10:41:39 +0530 | [diff] [blame] | 765 | r = edma_alloc_channel(dma->tx_channel, davinci_spi_dma_callback, dspi, |
| 766 | dma->eventq); |
Sekhar Nori | 903ca25 | 2010-10-01 14:51:40 +0530 | [diff] [blame] | 767 | if (r < 0) { |
Sekhar Nori | 903ca25 | 2010-10-01 14:51:40 +0530 | [diff] [blame] | 768 | pr_err("Unable to request DMA channel for SPI TX\n"); |
Brian Niebuhr | 523c37e | 2010-10-04 17:35:34 +0530 | [diff] [blame] | 769 | r = -EAGAIN; |
| 770 | goto tx_dma_failed; |
Sekhar Nori | 903ca25 | 2010-10-01 14:51:40 +0530 | [diff] [blame] | 771 | } |
| 772 | |
Sekhar Nori | 212d4b6 | 2010-10-11 10:41:39 +0530 | [diff] [blame] | 773 | r = edma_alloc_slot(EDMA_CTLR(dma->tx_channel), EDMA_SLOT_ANY); |
Brian Niebuhr | 523c37e | 2010-10-04 17:35:34 +0530 | [diff] [blame] | 774 | if (r < 0) { |
| 775 | pr_err("Unable to request SPI TX DMA param slot\n"); |
| 776 | r = -EAGAIN; |
| 777 | goto param_failed; |
| 778 | } |
Sekhar Nori | 212d4b6 | 2010-10-11 10:41:39 +0530 | [diff] [blame] | 779 | dma->dummy_param_slot = r; |
| 780 | edma_link(dma->dummy_param_slot, dma->dummy_param_slot); |
Brian Niebuhr | 523c37e | 2010-10-04 17:35:34 +0530 | [diff] [blame] | 781 | |
Sekhar Nori | 903ca25 | 2010-10-01 14:51:40 +0530 | [diff] [blame] | 782 | return 0; |
Brian Niebuhr | 523c37e | 2010-10-04 17:35:34 +0530 | [diff] [blame] | 783 | param_failed: |
Sekhar Nori | 212d4b6 | 2010-10-11 10:41:39 +0530 | [diff] [blame] | 784 | edma_free_channel(dma->tx_channel); |
Brian Niebuhr | 523c37e | 2010-10-04 17:35:34 +0530 | [diff] [blame] | 785 | tx_dma_failed: |
Sekhar Nori | 212d4b6 | 2010-10-11 10:41:39 +0530 | [diff] [blame] | 786 | edma_free_channel(dma->rx_channel); |
Brian Niebuhr | 523c37e | 2010-10-04 17:35:34 +0530 | [diff] [blame] | 787 | rx_dma_failed: |
| 788 | return r; |
Sekhar Nori | 903ca25 | 2010-10-01 14:51:40 +0530 | [diff] [blame] | 789 | } |
| 790 | |
Sandeep Paulraj | 358934a | 2009-12-16 22:02:18 +0000 | [diff] [blame] | 791 | /** |
Sandeep Paulraj | 358934a | 2009-12-16 22:02:18 +0000 | [diff] [blame] | 792 | * davinci_spi_probe - probe function for SPI Master Controller |
| 793 | * @pdev: platform_device structure which contains plateform specific data |
Brian Niebuhr | 035540f | 2010-10-06 18:32:40 +0530 | [diff] [blame] | 794 | * |
| 795 | * According to Linux Device Model this function will be invoked by Linux |
| 796 | * with platform_device struct which contains the device specific info. |
| 797 | * This function will map the SPI controller's memory, register IRQ, |
| 798 | * Reset SPI controller and setting its registers to default value. |
| 799 | * It will invoke spi_bitbang_start to create work queue so that client driver |
| 800 | * can register transfer method to work queue. |
Sandeep Paulraj | 358934a | 2009-12-16 22:02:18 +0000 | [diff] [blame] | 801 | */ |
| 802 | static int davinci_spi_probe(struct platform_device *pdev) |
| 803 | { |
| 804 | struct spi_master *master; |
Sekhar Nori | 212d4b6 | 2010-10-11 10:41:39 +0530 | [diff] [blame] | 805 | struct davinci_spi *dspi; |
Sandeep Paulraj | 358934a | 2009-12-16 22:02:18 +0000 | [diff] [blame] | 806 | struct davinci_spi_platform_data *pdata; |
| 807 | struct resource *r, *mem; |
| 808 | resource_size_t dma_rx_chan = SPI_NO_RESOURCE; |
| 809 | resource_size_t dma_tx_chan = SPI_NO_RESOURCE; |
| 810 | resource_size_t dma_eventq = SPI_NO_RESOURCE; |
| 811 | int i = 0, ret = 0; |
Brian Niebuhr | f34bd4c | 2010-09-03 11:56:35 +0530 | [diff] [blame] | 812 | u32 spipc0; |
Sandeep Paulraj | 358934a | 2009-12-16 22:02:18 +0000 | [diff] [blame] | 813 | |
| 814 | pdata = pdev->dev.platform_data; |
| 815 | if (pdata == NULL) { |
| 816 | ret = -ENODEV; |
| 817 | goto err; |
| 818 | } |
| 819 | |
| 820 | master = spi_alloc_master(&pdev->dev, sizeof(struct davinci_spi)); |
| 821 | if (master == NULL) { |
| 822 | ret = -ENOMEM; |
| 823 | goto err; |
| 824 | } |
| 825 | |
| 826 | dev_set_drvdata(&pdev->dev, master); |
| 827 | |
Sekhar Nori | 212d4b6 | 2010-10-11 10:41:39 +0530 | [diff] [blame] | 828 | dspi = spi_master_get_devdata(master); |
| 829 | if (dspi == NULL) { |
Sandeep Paulraj | 358934a | 2009-12-16 22:02:18 +0000 | [diff] [blame] | 830 | ret = -ENOENT; |
| 831 | goto free_master; |
| 832 | } |
| 833 | |
| 834 | r = platform_get_resource(pdev, IORESOURCE_MEM, 0); |
| 835 | if (r == NULL) { |
| 836 | ret = -ENOENT; |
| 837 | goto free_master; |
| 838 | } |
| 839 | |
Sekhar Nori | 212d4b6 | 2010-10-11 10:41:39 +0530 | [diff] [blame] | 840 | dspi->pbase = r->start; |
| 841 | dspi->pdata = pdata; |
Sandeep Paulraj | 358934a | 2009-12-16 22:02:18 +0000 | [diff] [blame] | 842 | |
Sekhar Nori | 0e0eae4d1 | 2010-10-08 14:04:22 +0530 | [diff] [blame] | 843 | mem = request_mem_region(r->start, resource_size(r), pdev->name); |
Sandeep Paulraj | 358934a | 2009-12-16 22:02:18 +0000 | [diff] [blame] | 844 | if (mem == NULL) { |
| 845 | ret = -EBUSY; |
| 846 | goto free_master; |
| 847 | } |
| 848 | |
Sekhar Nori | 212d4b6 | 2010-10-11 10:41:39 +0530 | [diff] [blame] | 849 | dspi->base = ioremap(r->start, resource_size(r)); |
| 850 | if (dspi->base == NULL) { |
Sandeep Paulraj | 358934a | 2009-12-16 22:02:18 +0000 | [diff] [blame] | 851 | ret = -ENOMEM; |
| 852 | goto release_region; |
| 853 | } |
| 854 | |
Sekhar Nori | 212d4b6 | 2010-10-11 10:41:39 +0530 | [diff] [blame] | 855 | dspi->irq = platform_get_irq(pdev, 0); |
| 856 | if (dspi->irq <= 0) { |
Brian Niebuhr | e0d205e | 2010-09-02 16:52:06 +0530 | [diff] [blame] | 857 | ret = -EINVAL; |
| 858 | goto unmap_io; |
| 859 | } |
| 860 | |
Sekhar Nori | 212d4b6 | 2010-10-11 10:41:39 +0530 | [diff] [blame] | 861 | ret = request_irq(dspi->irq, davinci_spi_irq, 0, dev_name(&pdev->dev), |
| 862 | dspi); |
Brian Niebuhr | e0d205e | 2010-09-02 16:52:06 +0530 | [diff] [blame] | 863 | if (ret) |
| 864 | goto unmap_io; |
| 865 | |
Sekhar Nori | 212d4b6 | 2010-10-11 10:41:39 +0530 | [diff] [blame] | 866 | dspi->bitbang.master = spi_master_get(master); |
| 867 | if (dspi->bitbang.master == NULL) { |
Sandeep Paulraj | 358934a | 2009-12-16 22:02:18 +0000 | [diff] [blame] | 868 | ret = -ENODEV; |
Brian Niebuhr | d3f7141 | 2010-09-29 12:31:54 +0530 | [diff] [blame] | 869 | goto irq_free; |
Sandeep Paulraj | 358934a | 2009-12-16 22:02:18 +0000 | [diff] [blame] | 870 | } |
| 871 | |
Sekhar Nori | 212d4b6 | 2010-10-11 10:41:39 +0530 | [diff] [blame] | 872 | dspi->clk = clk_get(&pdev->dev, NULL); |
| 873 | if (IS_ERR(dspi->clk)) { |
Sandeep Paulraj | 358934a | 2009-12-16 22:02:18 +0000 | [diff] [blame] | 874 | ret = -ENODEV; |
| 875 | goto put_master; |
| 876 | } |
Sekhar Nori | 212d4b6 | 2010-10-11 10:41:39 +0530 | [diff] [blame] | 877 | clk_enable(dspi->clk); |
Sandeep Paulraj | 358934a | 2009-12-16 22:02:18 +0000 | [diff] [blame] | 878 | |
Sandeep Paulraj | 358934a | 2009-12-16 22:02:18 +0000 | [diff] [blame] | 879 | master->bus_num = pdev->id; |
| 880 | master->num_chipselect = pdata->num_chipselect; |
| 881 | master->setup = davinci_spi_setup; |
Sandeep Paulraj | 358934a | 2009-12-16 22:02:18 +0000 | [diff] [blame] | 882 | |
Sekhar Nori | 212d4b6 | 2010-10-11 10:41:39 +0530 | [diff] [blame] | 883 | dspi->bitbang.chipselect = davinci_spi_chipselect; |
| 884 | dspi->bitbang.setup_transfer = davinci_spi_setup_transfer; |
Sandeep Paulraj | 358934a | 2009-12-16 22:02:18 +0000 | [diff] [blame] | 885 | |
Sekhar Nori | 212d4b6 | 2010-10-11 10:41:39 +0530 | [diff] [blame] | 886 | dspi->version = pdata->version; |
Sandeep Paulraj | 358934a | 2009-12-16 22:02:18 +0000 | [diff] [blame] | 887 | |
Sekhar Nori | 212d4b6 | 2010-10-11 10:41:39 +0530 | [diff] [blame] | 888 | dspi->bitbang.flags = SPI_NO_CS | SPI_LSB_FIRST | SPI_LOOP; |
| 889 | if (dspi->version == SPI_VERSION_2) |
| 890 | dspi->bitbang.flags |= SPI_READY; |
Sandeep Paulraj | 358934a | 2009-12-16 22:02:18 +0000 | [diff] [blame] | 891 | |
Sekhar Nori | 903ca25 | 2010-10-01 14:51:40 +0530 | [diff] [blame] | 892 | r = platform_get_resource(pdev, IORESOURCE_DMA, 0); |
| 893 | if (r) |
| 894 | dma_rx_chan = r->start; |
| 895 | r = platform_get_resource(pdev, IORESOURCE_DMA, 1); |
| 896 | if (r) |
| 897 | dma_tx_chan = r->start; |
| 898 | r = platform_get_resource(pdev, IORESOURCE_DMA, 2); |
| 899 | if (r) |
| 900 | dma_eventq = r->start; |
Sandeep Paulraj | 358934a | 2009-12-16 22:02:18 +0000 | [diff] [blame] | 901 | |
Sekhar Nori | 212d4b6 | 2010-10-11 10:41:39 +0530 | [diff] [blame] | 902 | dspi->bitbang.txrx_bufs = davinci_spi_bufs; |
Sekhar Nori | 903ca25 | 2010-10-01 14:51:40 +0530 | [diff] [blame] | 903 | if (dma_rx_chan != SPI_NO_RESOURCE && |
| 904 | dma_tx_chan != SPI_NO_RESOURCE && |
| 905 | dma_eventq != SPI_NO_RESOURCE) { |
Sekhar Nori | 212d4b6 | 2010-10-11 10:41:39 +0530 | [diff] [blame] | 906 | dspi->dma.rx_channel = dma_rx_chan; |
| 907 | dspi->dma.tx_channel = dma_tx_chan; |
| 908 | dspi->dma.eventq = dma_eventq; |
Brian Niebuhr | 96fd881 | 2010-09-27 22:23:23 +0530 | [diff] [blame] | 909 | |
Sekhar Nori | 212d4b6 | 2010-10-11 10:41:39 +0530 | [diff] [blame] | 910 | ret = davinci_spi_request_dma(dspi); |
Sekhar Nori | 903ca25 | 2010-10-01 14:51:40 +0530 | [diff] [blame] | 911 | if (ret) |
| 912 | goto free_clk; |
| 913 | |
Brian Niebuhr | 87467bd | 2010-10-06 17:03:10 +0530 | [diff] [blame] | 914 | dev_info(&pdev->dev, "DMA: supported\n"); |
| 915 | dev_info(&pdev->dev, "DMA: RX channel: %d, TX channel: %d, " |
| 916 | "event queue: %d\n", dma_rx_chan, dma_tx_chan, |
Sandeep Paulraj | 358934a | 2009-12-16 22:02:18 +0000 | [diff] [blame] | 917 | dma_eventq); |
| 918 | } |
| 919 | |
Sekhar Nori | 212d4b6 | 2010-10-11 10:41:39 +0530 | [diff] [blame] | 920 | dspi->get_rx = davinci_spi_rx_buf_u8; |
| 921 | dspi->get_tx = davinci_spi_tx_buf_u8; |
Sandeep Paulraj | 358934a | 2009-12-16 22:02:18 +0000 | [diff] [blame] | 922 | |
Sekhar Nori | 212d4b6 | 2010-10-11 10:41:39 +0530 | [diff] [blame] | 923 | init_completion(&dspi->done); |
Brian Niebuhr | e0d205e | 2010-09-02 16:52:06 +0530 | [diff] [blame] | 924 | |
Sandeep Paulraj | 358934a | 2009-12-16 22:02:18 +0000 | [diff] [blame] | 925 | /* Reset In/OUT SPI module */ |
Sekhar Nori | 212d4b6 | 2010-10-11 10:41:39 +0530 | [diff] [blame] | 926 | iowrite32(0, dspi->base + SPIGCR0); |
Sandeep Paulraj | 358934a | 2009-12-16 22:02:18 +0000 | [diff] [blame] | 927 | udelay(100); |
Sekhar Nori | 212d4b6 | 2010-10-11 10:41:39 +0530 | [diff] [blame] | 928 | iowrite32(1, dspi->base + SPIGCR0); |
Sandeep Paulraj | 358934a | 2009-12-16 22:02:18 +0000 | [diff] [blame] | 929 | |
Brian Niebuhr | be88471 | 2010-09-03 12:15:28 +0530 | [diff] [blame] | 930 | /* Set up SPIPC0. CS and ENA init is done in davinci_spi_setup */ |
Brian Niebuhr | f34bd4c | 2010-09-03 11:56:35 +0530 | [diff] [blame] | 931 | spipc0 = SPIPC0_DIFUN_MASK | SPIPC0_DOFUN_MASK | SPIPC0_CLKFUN_MASK; |
Sekhar Nori | 212d4b6 | 2010-10-11 10:41:39 +0530 | [diff] [blame] | 932 | iowrite32(spipc0, dspi->base + SPIPC0); |
Brian Niebuhr | f34bd4c | 2010-09-03 11:56:35 +0530 | [diff] [blame] | 933 | |
Brian Niebuhr | 2385397 | 2010-08-13 10:57:44 +0530 | [diff] [blame] | 934 | /* initialize chip selects */ |
| 935 | if (pdata->chip_sel) { |
| 936 | for (i = 0; i < pdata->num_chipselect; i++) { |
| 937 | if (pdata->chip_sel[i] != SPI_INTERN_CS) |
| 938 | gpio_direction_output(pdata->chip_sel[i], 1); |
| 939 | } |
| 940 | } |
| 941 | |
Brian Niebuhr | e0d205e | 2010-09-02 16:52:06 +0530 | [diff] [blame] | 942 | if (pdata->intr_line) |
Sekhar Nori | 212d4b6 | 2010-10-11 10:41:39 +0530 | [diff] [blame] | 943 | iowrite32(SPI_INTLVL_1, dspi->base + SPILVL); |
Brian Niebuhr | e0d205e | 2010-09-02 16:52:06 +0530 | [diff] [blame] | 944 | else |
Sekhar Nori | 212d4b6 | 2010-10-11 10:41:39 +0530 | [diff] [blame] | 945 | iowrite32(SPI_INTLVL_0, dspi->base + SPILVL); |
Brian Niebuhr | e0d205e | 2010-09-02 16:52:06 +0530 | [diff] [blame] | 946 | |
Sekhar Nori | 212d4b6 | 2010-10-11 10:41:39 +0530 | [diff] [blame] | 947 | iowrite32(CS_DEFAULT, dspi->base + SPIDEF); |
Brian Niebuhr | 843a713 | 2010-08-12 12:49:05 +0530 | [diff] [blame] | 948 | |
Sandeep Paulraj | 358934a | 2009-12-16 22:02:18 +0000 | [diff] [blame] | 949 | /* master mode default */ |
Sekhar Nori | 212d4b6 | 2010-10-11 10:41:39 +0530 | [diff] [blame] | 950 | set_io_bits(dspi->base + SPIGCR1, SPIGCR1_CLKMOD_MASK); |
| 951 | set_io_bits(dspi->base + SPIGCR1, SPIGCR1_MASTER_MASK); |
| 952 | set_io_bits(dspi->base + SPIGCR1, SPIGCR1_POWERDOWN_MASK); |
Sandeep Paulraj | 358934a | 2009-12-16 22:02:18 +0000 | [diff] [blame] | 953 | |
Sekhar Nori | 212d4b6 | 2010-10-11 10:41:39 +0530 | [diff] [blame] | 954 | ret = spi_bitbang_start(&dspi->bitbang); |
Sandeep Paulraj | 358934a | 2009-12-16 22:02:18 +0000 | [diff] [blame] | 955 | if (ret) |
Sekhar Nori | 903ca25 | 2010-10-01 14:51:40 +0530 | [diff] [blame] | 956 | goto free_dma; |
Sandeep Paulraj | 358934a | 2009-12-16 22:02:18 +0000 | [diff] [blame] | 957 | |
Sekhar Nori | 212d4b6 | 2010-10-11 10:41:39 +0530 | [diff] [blame] | 958 | dev_info(&pdev->dev, "Controller at 0x%p\n", dspi->base); |
Sandeep Paulraj | 358934a | 2009-12-16 22:02:18 +0000 | [diff] [blame] | 959 | |
Sandeep Paulraj | 358934a | 2009-12-16 22:02:18 +0000 | [diff] [blame] | 960 | return ret; |
| 961 | |
Sekhar Nori | 903ca25 | 2010-10-01 14:51:40 +0530 | [diff] [blame] | 962 | free_dma: |
Sekhar Nori | 212d4b6 | 2010-10-11 10:41:39 +0530 | [diff] [blame] | 963 | edma_free_channel(dspi->dma.tx_channel); |
| 964 | edma_free_channel(dspi->dma.rx_channel); |
| 965 | edma_free_slot(dspi->dma.dummy_param_slot); |
Sandeep Paulraj | 358934a | 2009-12-16 22:02:18 +0000 | [diff] [blame] | 966 | free_clk: |
Sekhar Nori | 212d4b6 | 2010-10-11 10:41:39 +0530 | [diff] [blame] | 967 | clk_disable(dspi->clk); |
| 968 | clk_put(dspi->clk); |
Sandeep Paulraj | 358934a | 2009-12-16 22:02:18 +0000 | [diff] [blame] | 969 | put_master: |
| 970 | spi_master_put(master); |
Brian Niebuhr | e0d205e | 2010-09-02 16:52:06 +0530 | [diff] [blame] | 971 | irq_free: |
Sekhar Nori | 212d4b6 | 2010-10-11 10:41:39 +0530 | [diff] [blame] | 972 | free_irq(dspi->irq, dspi); |
Sandeep Paulraj | 358934a | 2009-12-16 22:02:18 +0000 | [diff] [blame] | 973 | unmap_io: |
Sekhar Nori | 212d4b6 | 2010-10-11 10:41:39 +0530 | [diff] [blame] | 974 | iounmap(dspi->base); |
Sandeep Paulraj | 358934a | 2009-12-16 22:02:18 +0000 | [diff] [blame] | 975 | release_region: |
Sekhar Nori | 212d4b6 | 2010-10-11 10:41:39 +0530 | [diff] [blame] | 976 | release_mem_region(dspi->pbase, resource_size(r)); |
Sandeep Paulraj | 358934a | 2009-12-16 22:02:18 +0000 | [diff] [blame] | 977 | free_master: |
| 978 | kfree(master); |
| 979 | err: |
| 980 | return ret; |
| 981 | } |
| 982 | |
| 983 | /** |
| 984 | * davinci_spi_remove - remove function for SPI Master Controller |
| 985 | * @pdev: platform_device structure which contains plateform specific data |
| 986 | * |
| 987 | * This function will do the reverse action of davinci_spi_probe function |
| 988 | * It will free the IRQ and SPI controller's memory region. |
| 989 | * It will also call spi_bitbang_stop to destroy the work queue which was |
| 990 | * created by spi_bitbang_start. |
| 991 | */ |
| 992 | static int __exit davinci_spi_remove(struct platform_device *pdev) |
| 993 | { |
Sekhar Nori | 212d4b6 | 2010-10-11 10:41:39 +0530 | [diff] [blame] | 994 | struct davinci_spi *dspi; |
Sandeep Paulraj | 358934a | 2009-12-16 22:02:18 +0000 | [diff] [blame] | 995 | struct spi_master *master; |
Sekhar Nori | 0e0eae4d1 | 2010-10-08 14:04:22 +0530 | [diff] [blame] | 996 | struct resource *r; |
Sandeep Paulraj | 358934a | 2009-12-16 22:02:18 +0000 | [diff] [blame] | 997 | |
| 998 | master = dev_get_drvdata(&pdev->dev); |
Sekhar Nori | 212d4b6 | 2010-10-11 10:41:39 +0530 | [diff] [blame] | 999 | dspi = spi_master_get_devdata(master); |
Sandeep Paulraj | 358934a | 2009-12-16 22:02:18 +0000 | [diff] [blame] | 1000 | |
Sekhar Nori | 212d4b6 | 2010-10-11 10:41:39 +0530 | [diff] [blame] | 1001 | spi_bitbang_stop(&dspi->bitbang); |
Sandeep Paulraj | 358934a | 2009-12-16 22:02:18 +0000 | [diff] [blame] | 1002 | |
Sekhar Nori | 212d4b6 | 2010-10-11 10:41:39 +0530 | [diff] [blame] | 1003 | clk_disable(dspi->clk); |
| 1004 | clk_put(dspi->clk); |
Sandeep Paulraj | 358934a | 2009-12-16 22:02:18 +0000 | [diff] [blame] | 1005 | spi_master_put(master); |
Sekhar Nori | 212d4b6 | 2010-10-11 10:41:39 +0530 | [diff] [blame] | 1006 | free_irq(dspi->irq, dspi); |
| 1007 | iounmap(dspi->base); |
Sekhar Nori | 0e0eae4d1 | 2010-10-08 14:04:22 +0530 | [diff] [blame] | 1008 | r = platform_get_resource(pdev, IORESOURCE_MEM, 0); |
Sekhar Nori | 212d4b6 | 2010-10-11 10:41:39 +0530 | [diff] [blame] | 1009 | release_mem_region(dspi->pbase, resource_size(r)); |
Sandeep Paulraj | 358934a | 2009-12-16 22:02:18 +0000 | [diff] [blame] | 1010 | |
| 1011 | return 0; |
| 1012 | } |
| 1013 | |
| 1014 | static struct platform_driver davinci_spi_driver = { |
Brian Niebuhr | d8c174c | 2010-10-06 18:47:16 +0530 | [diff] [blame] | 1015 | .driver = { |
| 1016 | .name = "spi_davinci", |
| 1017 | .owner = THIS_MODULE, |
| 1018 | }, |
Sandeep Paulraj | 358934a | 2009-12-16 22:02:18 +0000 | [diff] [blame] | 1019 | .remove = __exit_p(davinci_spi_remove), |
| 1020 | }; |
| 1021 | |
| 1022 | static int __init davinci_spi_init(void) |
| 1023 | { |
| 1024 | return platform_driver_probe(&davinci_spi_driver, davinci_spi_probe); |
| 1025 | } |
| 1026 | module_init(davinci_spi_init); |
| 1027 | |
| 1028 | static void __exit davinci_spi_exit(void) |
| 1029 | { |
| 1030 | platform_driver_unregister(&davinci_spi_driver); |
| 1031 | } |
| 1032 | module_exit(davinci_spi_exit); |
| 1033 | |
| 1034 | MODULE_DESCRIPTION("TI DaVinci SPI Master Controller Driver"); |
| 1035 | MODULE_LICENSE("GPL"); |