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gerrit-public.fairphone.software / kernel / msm-4.9 / b1ad487c42e982bb30f10bfb267f71c5daa3a0d5 / . / drivers / gpu / drm / radeon / radeon_asic.h
blob: ae637cfda783285a0f2638435e6620c6026fb534 [file] [log] [blame]
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200[diff] [blame]1/*
2 * Copyright 2008 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
4 * Copyright 2009 Jerome Glisse.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
23 *
24 * Authors: Dave Airlie
25 * Alex Deucher
26 * Jerome Glisse
27 */
28#ifndef __RADEON_ASIC_H__
29#define __RADEON_ASIC_H__
30
31/*
32 * common functions
33 */
Rafał Miłecki74338742009-11-03 00:53:02 +0100[diff] [blame]34uint32_t radeon_legacy_get_engine_clock(struct radeon_device *rdev);
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200[diff] [blame]35void radeon_legacy_set_engine_clock(struct radeon_device *rdev, uint32_t eng_clock);
Rafał Miłecki5ea597f2009-12-17 13:50:09 +0100[diff] [blame]36uint32_t radeon_legacy_get_memory_clock(struct radeon_device *rdev);
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200[diff] [blame]37void radeon_legacy_set_clock_gating(struct radeon_device *rdev, int enable);
38
Rafał Miłecki74338742009-11-03 00:53:02 +0100[diff] [blame]39uint32_t radeon_atom_get_engine_clock(struct radeon_device *rdev);
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200[diff] [blame]40void radeon_atom_set_engine_clock(struct radeon_device *rdev, uint32_t eng_clock);
Rafał Miłecki74338742009-11-03 00:53:02 +0100[diff] [blame]41uint32_t radeon_atom_get_memory_clock(struct radeon_device *rdev);
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200[diff] [blame]42void radeon_atom_set_memory_clock(struct radeon_device *rdev, uint32_t mem_clock);
43void radeon_atom_set_clock_gating(struct radeon_device *rdev, int enable);
44
Alex Deucher37e9b6a2012-08-03 11:39:43 -0400[diff] [blame]45void atombios_set_backlight_level(struct radeon_encoder *radeon_encoder, u8 level);
Alex Deucher6d92f812012-09-14 09:59:26 -0400[diff] [blame]46u8 atombios_get_backlight_level(struct radeon_encoder *radeon_encoder);
Alex Deucher37e9b6a2012-08-03 11:39:43 -0400[diff] [blame]47void radeon_legacy_set_backlight_level(struct radeon_encoder *radeon_encoder, u8 level);
Alex Deucher6d92f812012-09-14 09:59:26 -0400[diff] [blame]48u8 radeon_legacy_get_backlight_level(struct radeon_encoder *radeon_encoder);
Alex Deucher37e9b6a2012-08-03 11:39:43 -0400[diff] [blame]49
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200[diff] [blame]50/*
Pauli Nieminen44ca7472010-02-11 17:25:47 +0000[diff] [blame]51 * r100,rv100,rs100,rv200,rs200
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200[diff] [blame]52 */
Daniel Vetter2b497502010-03-11 21:19:18 +0000[diff] [blame]53struct r100_mc_save {
54 u32 GENMO_WT;
55 u32 CRTC_EXT_CNTL;
56 u32 CRTC_GEN_CNTL;
57 u32 CRTC2_GEN_CNTL;
58 u32 CUR_OFFSET;
59 u32 CUR2_OFFSET;
60};
61int r100_init(struct radeon_device *rdev);
62void r100_fini(struct radeon_device *rdev);
63int r100_suspend(struct radeon_device *rdev);
64int r100_resume(struct radeon_device *rdev);
Dave Airlie28d52042009-09-21 14:33:58 +1000[diff] [blame]65void r100_vga_set_state(struct radeon_device *rdev, bool state);
Christian Könige32eb502011-10-23 12:56:27 +0200[diff] [blame]66bool r100_gpu_is_lockup(struct radeon_device *rdev, struct radeon_ring *cp);
Jerome Glissea2d07b72010-03-09 14:45:11 +0000[diff] [blame]67int r100_asic_reset(struct radeon_device *rdev);
Michel Dänzer7ed220d2009-08-13 11:10:51 +0200[diff] [blame]68u32 r100_get_vblank_counter(struct radeon_device *rdev, int crtc);
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200[diff] [blame]69void r100_pci_gart_tlb_flush(struct radeon_device *rdev);
70int r100_pci_gart_set_page(struct radeon_device *rdev, int i, uint64_t addr);
Alex Deucherf7128122012-02-23 17:53:45 -0500[diff] [blame]71void r100_ring_start(struct radeon_device *rdev, struct radeon_ring *ring);
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200[diff] [blame]72int r100_irq_set(struct radeon_device *rdev);
73int r100_irq_process(struct radeon_device *rdev);
74void r100_fence_ring_emit(struct radeon_device *rdev,
75 struct radeon_fence *fence);
Christian König1654b812013-11-12 12:58:05 +0100[diff] [blame]76bool r100_semaphore_ring_emit(struct radeon_device *rdev,
Christian Könige32eb502011-10-23 12:56:27 +0200[diff] [blame]77 struct radeon_ring *cp,
Christian König15d33322011-09-15 19:02:22 +0200[diff] [blame]78 struct radeon_semaphore *semaphore,
Christian König7b1f2482011-09-23 15:11:23 +0200[diff] [blame]79 bool emit_wait);
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200[diff] [blame]80int r100_cs_parse(struct radeon_cs_parser *p);
81void r100_pll_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v);
82uint32_t r100_pll_rreg(struct radeon_device *rdev, uint32_t reg);
83int r100_copy_blit(struct radeon_device *rdev,
84 uint64_t src_offset,
85 uint64_t dst_offset,
Alex Deucher003cefe2011-09-16 12:04:08 -0400[diff] [blame]86 unsigned num_gpu_pages,
Christian König876dc9f2012-05-08 14:24:01 +0200[diff] [blame]87 struct radeon_fence **fence);
Dave Airliee024e112009-06-24 09:48:08 +1000[diff] [blame]88int r100_set_surface_reg(struct radeon_device *rdev, int reg,
89 uint32_t tiling_flags, uint32_t pitch,
90 uint32_t offset, uint32_t obj_size);
Daniel Vetter9479c542010-03-11 21:19:16 +0000[diff] [blame]91void r100_clear_surface_reg(struct radeon_device *rdev, int reg);
Jerome Glissec93bb852009-07-13 21:04:08 +0200[diff] [blame]92void r100_bandwidth_update(struct radeon_device *rdev);
Jerome Glisse3ce0a232009-09-08 10:10:24 +1000[diff] [blame]93void r100_ring_ib_execute(struct radeon_device *rdev, struct radeon_ib *ib);
Christian Könige32eb502011-10-23 12:56:27 +0200[diff] [blame]94int r100_ring_test(struct radeon_device *rdev, struct radeon_ring *cp);
Alex Deucher429770b2009-12-04 15:26:55 -0500[diff] [blame]95void r100_hpd_init(struct radeon_device *rdev);
96void r100_hpd_fini(struct radeon_device *rdev);
97bool r100_hpd_sense(struct radeon_device *rdev, enum radeon_hpd_id hpd);
98void r100_hpd_set_polarity(struct radeon_device *rdev,
99 enum radeon_hpd_id hpd);
Daniel Vetter2b497502010-03-11 21:19:18 +0000[diff] [blame]100int r100_debugfs_rbbm_init(struct radeon_device *rdev);
101int r100_debugfs_cp_init(struct radeon_device *rdev);
102void r100_cp_disable(struct radeon_device *rdev);
103int r100_cp_init(struct radeon_device *rdev, unsigned ring_size);
104void r100_cp_fini(struct radeon_device *rdev);
105int r100_pci_gart_init(struct radeon_device *rdev);
106void r100_pci_gart_fini(struct radeon_device *rdev);
107int r100_pci_gart_enable(struct radeon_device *rdev);
108void r100_pci_gart_disable(struct radeon_device *rdev);
109int r100_debugfs_mc_info_init(struct radeon_device *rdev);
110int r100_gui_wait_for_idle(struct radeon_device *rdev);
Alex Deucherf7128122012-02-23 17:53:45 -0500[diff] [blame]111int r100_ib_test(struct radeon_device *rdev, struct radeon_ring *ring);
Daniel Vetter2b497502010-03-11 21:19:18 +0000[diff] [blame]112void r100_irq_disable(struct radeon_device *rdev);
113void r100_mc_stop(struct radeon_device *rdev, struct r100_mc_save *save);
114void r100_mc_resume(struct radeon_device *rdev, struct r100_mc_save *save);
115void r100_vram_init_sizes(struct radeon_device *rdev);
Daniel Vetter2b497502010-03-11 21:19:18 +0000[diff] [blame]116int r100_cp_reset(struct radeon_device *rdev);
117void r100_vga_render_disable(struct radeon_device *rdev);
Dave Airlie4c712e62010-07-15 12:13:50 +1000[diff] [blame]118void r100_restore_sanity(struct radeon_device *rdev);
Daniel Vetter2b497502010-03-11 21:19:18 +0000[diff] [blame]119int r100_cs_track_check_pkt3_indx_buffer(struct radeon_cs_parser *p,
120 struct radeon_cs_packet *pkt,
121 struct radeon_bo *robj);
122int r100_cs_parse_packet0(struct radeon_cs_parser *p,
123 struct radeon_cs_packet *pkt,
124 const unsigned *auth, unsigned n,
125 radeon_packet0_check_t check);
126int r100_cs_packet_parse(struct radeon_cs_parser *p,
127 struct radeon_cs_packet *pkt,
128 unsigned idx);
129void r100_enable_bm(struct radeon_device *rdev);
130void r100_set_common_regs(struct radeon_device *rdev);
Jerome Glisse90aca4d2010-03-09 14:45:12 +0000[diff] [blame]131void r100_bm_disable(struct radeon_device *rdev);
Alex Deucherdef9ba92010-04-22 12:39:58 -0400[diff] [blame]132extern bool r100_gui_idle(struct radeon_device *rdev);
Alex Deucher49e02b72010-04-23 17:57:27 -0400[diff] [blame]133extern void r100_pm_misc(struct radeon_device *rdev);
134extern void r100_pm_prepare(struct radeon_device *rdev);
135extern void r100_pm_finish(struct radeon_device *rdev);
Alex Deucherce8f5372010-05-07 15:10:16 -0400[diff] [blame]136extern void r100_pm_init_profile(struct radeon_device *rdev);
137extern void r100_pm_get_dynpm_state(struct radeon_device *rdev);
Alex Deucher6f34be52010-11-21 10:59:01 -0500[diff] [blame]138extern void r100_pre_page_flip(struct radeon_device *rdev, int crtc);
139extern u32 r100_page_flip(struct radeon_device *rdev, int crtc, u64 crtc_base);
140extern void r100_post_page_flip(struct radeon_device *rdev, int crtc);
Alex Deucher3ae19b72012-02-23 17:53:37 -0500[diff] [blame]141extern void r100_wait_for_vblank(struct radeon_device *rdev, int crtc);
Alex Deucher89e51812012-02-23 17:53:38 -0500[diff] [blame]142extern int r100_mc_wait_for_idle(struct radeon_device *rdev);
Alex Deucherbae6b5622010-04-22 13:38:05 -0400[diff] [blame]143
Alex Deucherea31bf62013-12-09 19:44:30 -0500[diff] [blame]144u32 r100_gfx_get_rptr(struct radeon_device *rdev,
145 struct radeon_ring *ring);
146u32 r100_gfx_get_wptr(struct radeon_device *rdev,
147 struct radeon_ring *ring);
148void r100_gfx_set_wptr(struct radeon_device *rdev,
149 struct radeon_ring *ring);
150
Pauli Nieminen44ca7472010-02-11 17:25:47 +0000[diff] [blame]151/*
152 * r200,rv250,rs300,rv280
153 */
154extern int r200_copy_dma(struct radeon_device *rdev,
Daniel Vetter187f3da2010-11-28 19:06:09 +0100[diff] [blame]155 uint64_t src_offset,
156 uint64_t dst_offset,
Alex Deucher003cefe2011-09-16 12:04:08 -0400[diff] [blame]157 unsigned num_gpu_pages,
Christian König876dc9f2012-05-08 14:24:01 +0200[diff] [blame]158 struct radeon_fence **fence);
Daniel Vetter187f3da2010-11-28 19:06:09 +0100[diff] [blame]159void r200_set_safe_registers(struct radeon_device *rdev);
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200[diff] [blame]160
161/*
162 * r300,r350,rv350,rv380
163 */
Jerome Glisse207bf9e2009-09-30 15:35:32 +0200[diff] [blame]164extern int r300_init(struct radeon_device *rdev);
165extern void r300_fini(struct radeon_device *rdev);
166extern int r300_suspend(struct radeon_device *rdev);
167extern int r300_resume(struct radeon_device *rdev);
Jerome Glissea2d07b72010-03-09 14:45:11 +0000[diff] [blame]168extern int r300_asic_reset(struct radeon_device *rdev);
Alex Deucherf7128122012-02-23 17:53:45 -0500[diff] [blame]169extern void r300_ring_start(struct radeon_device *rdev, struct radeon_ring *ring);
Jerome Glisse207bf9e2009-09-30 15:35:32 +0200[diff] [blame]170extern void r300_fence_ring_emit(struct radeon_device *rdev,
171 struct radeon_fence *fence);
172extern int r300_cs_parse(struct radeon_cs_parser *p);
173extern void rv370_pcie_gart_tlb_flush(struct radeon_device *rdev);
174extern int rv370_pcie_gart_set_page(struct radeon_device *rdev, int i, uint64_t addr);
Jerome Glisse207bf9e2009-09-30 15:35:32 +0200[diff] [blame]175extern void rv370_set_pcie_lanes(struct radeon_device *rdev, int lanes);
Alex Deucherc836a412009-12-23 10:07:50 -0500[diff] [blame]176extern int rv370_get_pcie_lanes(struct radeon_device *rdev);
Daniel Vetter187f3da2010-11-28 19:06:09 +0100[diff] [blame]177extern void r300_set_reg_safe(struct radeon_device *rdev);
178extern void r300_mc_program(struct radeon_device *rdev);
179extern void r300_mc_init(struct radeon_device *rdev);
180extern void r300_clock_startup(struct radeon_device *rdev);
181extern int r300_mc_wait_for_idle(struct radeon_device *rdev);
182extern int rv370_pcie_gart_init(struct radeon_device *rdev);
183extern void rv370_pcie_gart_fini(struct radeon_device *rdev);
184extern int rv370_pcie_gart_enable(struct radeon_device *rdev);
185extern void rv370_pcie_gart_disable(struct radeon_device *rdev);
Alex Deucher89e51812012-02-23 17:53:38 -0500[diff] [blame]186extern int r300_mc_wait_for_idle(struct radeon_device *rdev);
Pauli Nieminen44ca7472010-02-11 17:25:47 +0000[diff] [blame]187
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200[diff] [blame]188/*
189 * r420,r423,rv410
190 */
Jerome Glisse9f022dd2009-09-11 15:35:22 +0200[diff] [blame]191extern int r420_init(struct radeon_device *rdev);
192extern void r420_fini(struct radeon_device *rdev);
193extern int r420_suspend(struct radeon_device *rdev);
194extern int r420_resume(struct radeon_device *rdev);
Alex Deucherce8f5372010-05-07 15:10:16 -0400[diff] [blame]195extern void r420_pm_init_profile(struct radeon_device *rdev);
Daniel Vetter187f3da2010-11-28 19:06:09 +0100[diff] [blame]196extern u32 r420_mc_rreg(struct radeon_device *rdev, u32 reg);
197extern void r420_mc_wreg(struct radeon_device *rdev, u32 reg, u32 v);
198extern int r420_debugfs_pipes_info_init(struct radeon_device *rdev);
199extern void r420_pipes_init(struct radeon_device *rdev);
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200[diff] [blame]200
201/*
202 * rs400,rs480
203 */
Jerome Glisseca6ffc62009-10-01 10:20:52 +0200[diff] [blame]204extern int rs400_init(struct radeon_device *rdev);
205extern void rs400_fini(struct radeon_device *rdev);
206extern int rs400_suspend(struct radeon_device *rdev);
207extern int rs400_resume(struct radeon_device *rdev);
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200[diff] [blame]208void rs400_gart_tlb_flush(struct radeon_device *rdev);
209int rs400_gart_set_page(struct radeon_device *rdev, int i, uint64_t addr);
210uint32_t rs400_mc_rreg(struct radeon_device *rdev, uint32_t reg);
211void rs400_mc_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v);
Daniel Vetter187f3da2010-11-28 19:06:09 +0100[diff] [blame]212int rs400_gart_init(struct radeon_device *rdev);
213int rs400_gart_enable(struct radeon_device *rdev);
214void rs400_gart_adjust_size(struct radeon_device *rdev);
215void rs400_gart_disable(struct radeon_device *rdev);
216void rs400_gart_fini(struct radeon_device *rdev);
Alex Deucher89e51812012-02-23 17:53:38 -0500[diff] [blame]217extern int rs400_mc_wait_for_idle(struct radeon_device *rdev);
Daniel Vetter187f3da2010-11-28 19:06:09 +0100[diff] [blame]218
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200[diff] [blame]219/*
220 * rs600.
221 */
Jerome Glisse90aca4d2010-03-09 14:45:12 +0000[diff] [blame]222extern int rs600_asic_reset(struct radeon_device *rdev);
Jerome Glissec010f802009-09-30 22:09:06 +0200[diff] [blame]223extern int rs600_init(struct radeon_device *rdev);
224extern void rs600_fini(struct radeon_device *rdev);
225extern int rs600_suspend(struct radeon_device *rdev);
226extern int rs600_resume(struct radeon_device *rdev);
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200[diff] [blame]227int rs600_irq_set(struct radeon_device *rdev);
Michel Dänzer7ed220d2009-08-13 11:10:51 +0200[diff] [blame]228int rs600_irq_process(struct radeon_device *rdev);
Daniel Vetter187f3da2010-11-28 19:06:09 +0100[diff] [blame]229void rs600_irq_disable(struct radeon_device *rdev);
Michel Dänzer7ed220d2009-08-13 11:10:51 +0200[diff] [blame]230u32 rs600_get_vblank_counter(struct radeon_device *rdev, int crtc);
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200[diff] [blame]231void rs600_gart_tlb_flush(struct radeon_device *rdev);
232int rs600_gart_set_page(struct radeon_device *rdev, int i, uint64_t addr);
233uint32_t rs600_mc_rreg(struct radeon_device *rdev, uint32_t reg);
234void rs600_mc_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v);
Jerome Glissec93bb852009-07-13 21:04:08 +0200[diff] [blame]235void rs600_bandwidth_update(struct radeon_device *rdev);
Alex Deucher429770b2009-12-04 15:26:55 -0500[diff] [blame]236void rs600_hpd_init(struct radeon_device *rdev);
237void rs600_hpd_fini(struct radeon_device *rdev);
238bool rs600_hpd_sense(struct radeon_device *rdev, enum radeon_hpd_id hpd);
239void rs600_hpd_set_polarity(struct radeon_device *rdev,
240 enum radeon_hpd_id hpd);
Alex Deucher49e02b72010-04-23 17:57:27 -0400[diff] [blame]241extern void rs600_pm_misc(struct radeon_device *rdev);
242extern void rs600_pm_prepare(struct radeon_device *rdev);
243extern void rs600_pm_finish(struct radeon_device *rdev);
Alex Deucher6f34be52010-11-21 10:59:01 -0500[diff] [blame]244extern void rs600_pre_page_flip(struct radeon_device *rdev, int crtc);
245extern u32 rs600_page_flip(struct radeon_device *rdev, int crtc, u64 crtc_base);
246extern void rs600_post_page_flip(struct radeon_device *rdev, int crtc);
Daniel Vetter187f3da2010-11-28 19:06:09 +0100[diff] [blame]247void rs600_set_safe_registers(struct radeon_device *rdev);
Alex Deucher3ae19b72012-02-23 17:53:37 -0500[diff] [blame]248extern void avivo_wait_for_vblank(struct radeon_device *rdev, int crtc);
Alex Deucher89e51812012-02-23 17:53:38 -0500[diff] [blame]249extern int rs600_mc_wait_for_idle(struct radeon_device *rdev);
Alex Deucher429770b2009-12-04 15:26:55 -0500[diff] [blame]250
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200[diff] [blame]251/*
252 * rs690,rs740
253 */
Jerome Glisse3bc68532009-10-01 09:39:24 +0200[diff] [blame]254int rs690_init(struct radeon_device *rdev);
255void rs690_fini(struct radeon_device *rdev);
256int rs690_resume(struct radeon_device *rdev);
257int rs690_suspend(struct radeon_device *rdev);
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200[diff] [blame]258uint32_t rs690_mc_rreg(struct radeon_device *rdev, uint32_t reg);
259void rs690_mc_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v);
Jerome Glissec93bb852009-07-13 21:04:08 +0200[diff] [blame]260void rs690_bandwidth_update(struct radeon_device *rdev);
Daniel Vetter187f3da2010-11-28 19:06:09 +0100[diff] [blame]261void rs690_line_buffer_adjust(struct radeon_device *rdev,
262 struct drm_display_mode *mode1,
263 struct drm_display_mode *mode2);
Alex Deucher89e51812012-02-23 17:53:38 -0500[diff] [blame]264extern int rs690_mc_wait_for_idle(struct radeon_device *rdev);
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200[diff] [blame]265
266/*
267 * rv515
268 */
Daniel Vetter187f3da2010-11-28 19:06:09 +0100[diff] [blame]269struct rv515_mc_save {
Daniel Vetter187f3da2010-11-28 19:06:09 +0100[diff] [blame]270 u32 vga_render_control;
271 u32 vga_hdp_control;
Alex Deucher6253e4c2012-12-12 14:30:32 -0500[diff] [blame]272 bool crtc_enabled[2];
Daniel Vetter187f3da2010-11-28 19:06:09 +0100[diff] [blame]273};
Jerome Glisse81ee8fb2012-07-27 16:32:24 -0400[diff] [blame]274
Jerome Glisse068a1172009-06-17 13:28:30 +0200[diff] [blame]275int rv515_init(struct radeon_device *rdev);
Jerome Glissed39c3b82009-09-28 18:34:43 +0200[diff] [blame]276void rv515_fini(struct radeon_device *rdev);
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200[diff] [blame]277uint32_t rv515_mc_rreg(struct radeon_device *rdev, uint32_t reg);
278void rv515_mc_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v);
Alex Deucherf7128122012-02-23 17:53:45 -0500[diff] [blame]279void rv515_ring_start(struct radeon_device *rdev, struct radeon_ring *ring);
Jerome Glissec93bb852009-07-13 21:04:08 +0200[diff] [blame]280void rv515_bandwidth_update(struct radeon_device *rdev);
Jerome Glissed39c3b82009-09-28 18:34:43 +0200[diff] [blame]281int rv515_resume(struct radeon_device *rdev);
282int rv515_suspend(struct radeon_device *rdev);
Daniel Vetter187f3da2010-11-28 19:06:09 +0100[diff] [blame]283void rv515_bandwidth_avivo_update(struct radeon_device *rdev);
284void rv515_vga_render_disable(struct radeon_device *rdev);
285void rv515_set_safe_registers(struct radeon_device *rdev);
286void rv515_mc_stop(struct radeon_device *rdev, struct rv515_mc_save *save);
287void rv515_mc_resume(struct radeon_device *rdev, struct rv515_mc_save *save);
288void rv515_clock_startup(struct radeon_device *rdev);
289void rv515_debugfs(struct radeon_device *rdev);
Alex Deucher89e51812012-02-23 17:53:38 -0500[diff] [blame]290int rv515_mc_wait_for_idle(struct radeon_device *rdev);
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200[diff] [blame]291
292/*
293 * r520,rv530,rv560,rv570,r580
294 */
Jerome Glissed39c3b82009-09-28 18:34:43 +0200[diff] [blame]295int r520_init(struct radeon_device *rdev);
Jerome Glissef0ed1f62009-09-28 20:39:19 +0200[diff] [blame]296int r520_resume(struct radeon_device *rdev);
Alex Deucher89e51812012-02-23 17:53:38 -0500[diff] [blame]297int r520_mc_wait_for_idle(struct radeon_device *rdev);
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200[diff] [blame]298
299/*
Jerome Glisse3ce0a232009-09-08 10:10:24 +1000[diff] [blame]300 * r600,rv610,rv630,rv620,rv635,rv670,rs780,rs880
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200[diff] [blame]301 */
Jerome Glisse3ce0a232009-09-08 10:10:24 +1000[diff] [blame]302int r600_init(struct radeon_device *rdev);
303void r600_fini(struct radeon_device *rdev);
304int r600_suspend(struct radeon_device *rdev);
305int r600_resume(struct radeon_device *rdev);
Dave Airlie28d52042009-09-21 14:33:58 +1000[diff] [blame]306void r600_vga_set_state(struct radeon_device *rdev, bool state);
Jerome Glisse3ce0a232009-09-08 10:10:24 +1000[diff] [blame]307int r600_wb_init(struct radeon_device *rdev);
308void r600_wb_fini(struct radeon_device *rdev);
Jerome Glisse3ce0a232009-09-08 10:10:24 +1000[diff] [blame]309void r600_pcie_gart_tlb_flush(struct radeon_device *rdev);
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200[diff] [blame]310uint32_t r600_pciep_rreg(struct radeon_device *rdev, uint32_t reg);
311void r600_pciep_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v);
Jerome Glisse3ce0a232009-09-08 10:10:24 +1000[diff] [blame]312int r600_cs_parse(struct radeon_cs_parser *p);
Alex Deuchercf4ccd02011-11-18 10:19:47 -0500[diff] [blame]313int r600_dma_cs_parse(struct radeon_cs_parser *p);
Jerome Glisse3ce0a232009-09-08 10:10:24 +1000[diff] [blame]314void r600_fence_ring_emit(struct radeon_device *rdev,
315 struct radeon_fence *fence);
Christian König1654b812013-11-12 12:58:05 +0100[diff] [blame]316bool r600_semaphore_ring_emit(struct radeon_device *rdev,
Christian Könige32eb502011-10-23 12:56:27 +0200[diff] [blame]317 struct radeon_ring *cp,
Christian König15d33322011-09-15 19:02:22 +0200[diff] [blame]318 struct radeon_semaphore *semaphore,
Christian König7b1f2482011-09-23 15:11:23 +0200[diff] [blame]319 bool emit_wait);
Alex Deucher4d756582012-09-27 15:08:35 -0400[diff] [blame]320void r600_dma_fence_ring_emit(struct radeon_device *rdev,
321 struct radeon_fence *fence);
Christian König1654b812013-11-12 12:58:05 +0100[diff] [blame]322bool r600_dma_semaphore_ring_emit(struct radeon_device *rdev,
Alex Deucher4d756582012-09-27 15:08:35 -0400[diff] [blame]323 struct radeon_ring *ring,
324 struct radeon_semaphore *semaphore,
325 bool emit_wait);
326void r600_dma_ring_ib_execute(struct radeon_device *rdev, struct radeon_ib *ib);
327bool r600_dma_is_lockup(struct radeon_device *rdev, struct radeon_ring *ring);
Alex Deucher123bc182013-01-24 11:37:19 -0500[diff] [blame]328bool r600_gfx_is_lockup(struct radeon_device *rdev, struct radeon_ring *cp);
Jerome Glissea2d07b72010-03-09 14:45:11 +0000[diff] [blame]329int r600_asic_reset(struct radeon_device *rdev);
Jerome Glisse3ce0a232009-09-08 10:10:24 +1000[diff] [blame]330int r600_set_surface_reg(struct radeon_device *rdev, int reg,
331 uint32_t tiling_flags, uint32_t pitch,
332 uint32_t offset, uint32_t obj_size);
Daniel Vetter9479c542010-03-11 21:19:16 +0000[diff] [blame]333void r600_clear_surface_reg(struct radeon_device *rdev, int reg);
Alex Deucherf7128122012-02-23 17:53:45 -0500[diff] [blame]334int r600_ib_test(struct radeon_device *rdev, struct radeon_ring *ring);
Alex Deucher4d756582012-09-27 15:08:35 -0400[diff] [blame]335int r600_dma_ib_test(struct radeon_device *rdev, struct radeon_ring *ring);
Jerome Glisse3ce0a232009-09-08 10:10:24 +1000[diff] [blame]336void r600_ring_ib_execute(struct radeon_device *rdev, struct radeon_ib *ib);
Christian Könige32eb502011-10-23 12:56:27 +0200[diff] [blame]337int r600_ring_test(struct radeon_device *rdev, struct radeon_ring *cp);
Alex Deucher4d756582012-09-27 15:08:35 -0400[diff] [blame]338int r600_dma_ring_test(struct radeon_device *rdev, struct radeon_ring *cp);
Alex Deucher072b5ac2013-07-11 14:48:05 -0400[diff] [blame]339int r600_copy_cpdma(struct radeon_device *rdev,
340 uint64_t src_offset, uint64_t dst_offset,
341 unsigned num_gpu_pages, struct radeon_fence **fence);
Alex Deucher4d756582012-09-27 15:08:35 -0400[diff] [blame]342int r600_copy_dma(struct radeon_device *rdev,
343 uint64_t src_offset, uint64_t dst_offset,
344 unsigned num_gpu_pages, struct radeon_fence **fence);
Alex Deucher429770b2009-12-04 15:26:55 -0500[diff] [blame]345void r600_hpd_init(struct radeon_device *rdev);
346void r600_hpd_fini(struct radeon_device *rdev);
347bool r600_hpd_sense(struct radeon_device *rdev, enum radeon_hpd_id hpd);
348void r600_hpd_set_polarity(struct radeon_device *rdev,
349 enum radeon_hpd_id hpd);
Jerome Glisse062b3892010-02-04 20:36:39 +0100[diff] [blame]350extern void r600_ioctl_wait_idle(struct radeon_device *rdev, struct radeon_bo *bo);
Alex Deucherdef9ba92010-04-22 12:39:58 -0400[diff] [blame]351extern bool r600_gui_idle(struct radeon_device *rdev);
Alex Deucher49e02b72010-04-23 17:57:27 -0400[diff] [blame]352extern void r600_pm_misc(struct radeon_device *rdev);
Alex Deucherce8f5372010-05-07 15:10:16 -0400[diff] [blame]353extern void r600_pm_init_profile(struct radeon_device *rdev);
354extern void rs780_pm_init_profile(struct radeon_device *rdev);
Samuel Li65337e62013-04-05 17:50:53 -0400[diff] [blame]355extern uint32_t rs780_mc_rreg(struct radeon_device *rdev, uint32_t reg);
356extern void rs780_mc_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v);
Alex Deucherce8f5372010-05-07 15:10:16 -0400[diff] [blame]357extern void r600_pm_get_dynpm_state(struct radeon_device *rdev);
Alex Deucher3313e3d2011-01-06 18:49:34 -0500[diff] [blame]358extern void r600_set_pcie_lanes(struct radeon_device *rdev, int lanes);
359extern int r600_get_pcie_lanes(struct radeon_device *rdev);
Daniel Vetter3574dda2011-02-18 17:59:19 +0100[diff] [blame]360bool r600_card_posted(struct radeon_device *rdev);
361void r600_cp_stop(struct radeon_device *rdev);
362int r600_cp_start(struct radeon_device *rdev);
Christian Könige32eb502011-10-23 12:56:27 +0200[diff] [blame]363void r600_ring_init(struct radeon_device *rdev, struct radeon_ring *cp, unsigned ring_size);
Daniel Vetter3574dda2011-02-18 17:59:19 +0100[diff] [blame]364int r600_cp_resume(struct radeon_device *rdev);
365void r600_cp_fini(struct radeon_device *rdev);
366int r600_count_pipe_bits(uint32_t val);
367int r600_mc_wait_for_idle(struct radeon_device *rdev);
368int r600_pcie_gart_init(struct radeon_device *rdev);
369void r600_scratch_init(struct radeon_device *rdev);
Daniel Vetter3574dda2011-02-18 17:59:19 +0100[diff] [blame]370int r600_init_microcode(struct radeon_device *rdev);
Alex Deucherea31bf62013-12-09 19:44:30 -0500[diff] [blame]371u32 r600_gfx_get_rptr(struct radeon_device *rdev,
372 struct radeon_ring *ring);
373u32 r600_gfx_get_wptr(struct radeon_device *rdev,
374 struct radeon_ring *ring);
375void r600_gfx_set_wptr(struct radeon_device *rdev,
376 struct radeon_ring *ring);
Daniel Vetter3574dda2011-02-18 17:59:19 +0100[diff] [blame]377/* r600 irq */
378int r600_irq_process(struct radeon_device *rdev);
379int r600_irq_init(struct radeon_device *rdev);
380void r600_irq_fini(struct radeon_device *rdev);
381void r600_ih_ring_init(struct radeon_device *rdev, unsigned ring_size);
382int r600_irq_set(struct radeon_device *rdev);
383void r600_irq_suspend(struct radeon_device *rdev);
384void r600_disable_interrupts(struct radeon_device *rdev);
385void r600_rlc_stop(struct radeon_device *rdev);
386/* r600 audio */
387int r600_audio_init(struct radeon_device *rdev);
Alex Deucherb5306022013-07-31 16:51:33 -0400[diff] [blame]388struct r600_audio_pin r600_audio_status(struct radeon_device *rdev);
Daniel Vetter3574dda2011-02-18 17:59:19 +0100[diff] [blame]389void r600_audio_fini(struct radeon_device *rdev);
Daniel Vetter3574dda2011-02-18 17:59:19 +0100[diff] [blame]390int r600_hdmi_buffer_status_changed(struct drm_encoder *encoder);
391void r600_hdmi_update_audio_settings(struct drm_encoder *encoder);
Alex Deuchera973bea2013-04-18 11:32:16 -0400[diff] [blame]392void r600_hdmi_enable(struct drm_encoder *encoder, bool enable);
393void r600_hdmi_setmode(struct drm_encoder *encoder, struct drm_display_mode *mode);
Alex Deucher89e51812012-02-23 17:53:38 -0500[diff] [blame]394int r600_mc_wait_for_idle(struct radeon_device *rdev);
Alex Deucher454d2e22013-02-14 10:04:02 -0500[diff] [blame]395u32 r600_get_xclk(struct radeon_device *rdev);
Alex Deucherd0418892013-01-24 10:35:23 -0500[diff] [blame]396uint64_t r600_get_gpu_clock_counter(struct radeon_device *rdev);
Alex Deucher6bd1c382013-06-21 14:38:03 -0400[diff] [blame]397int rv6xx_get_temp(struct radeon_device *rdev);
Alex Deucher1b9ba702013-09-05 09:52:37 -0400[diff] [blame]398int r600_set_uvd_clocks(struct radeon_device *rdev, u32 vclk, u32 dclk);
Alex Deucher98243912013-01-16 13:13:42 -0500[diff] [blame]399int r600_dpm_pre_set_power_state(struct radeon_device *rdev);
400void r600_dpm_post_set_power_state(struct radeon_device *rdev);
Alex Deuchera4643ba2013-12-19 12:18:13 -0500[diff] [blame]401int r600_dpm_late_enable(struct radeon_device *rdev);
Christian König2e1e6da2013-08-13 11:56:52 +0200[diff] [blame]402/* r600 dma */
403uint32_t r600_dma_get_rptr(struct radeon_device *rdev,
404 struct radeon_ring *ring);
405uint32_t r600_dma_get_wptr(struct radeon_device *rdev,
406 struct radeon_ring *ring);
407void r600_dma_set_wptr(struct radeon_device *rdev,
408 struct radeon_ring *ring);
Alex Deucher4a6369e2013-04-12 14:04:10 -0400[diff] [blame]409/* rv6xx dpm */
410int rv6xx_dpm_init(struct radeon_device *rdev);
411int rv6xx_dpm_enable(struct radeon_device *rdev);
412void rv6xx_dpm_disable(struct radeon_device *rdev);
413int rv6xx_dpm_set_power_state(struct radeon_device *rdev);
414void rv6xx_setup_asic(struct radeon_device *rdev);
415void rv6xx_dpm_display_configuration_changed(struct radeon_device *rdev);
416void rv6xx_dpm_fini(struct radeon_device *rdev);
417u32 rv6xx_dpm_get_sclk(struct radeon_device *rdev, bool low);
418u32 rv6xx_dpm_get_mclk(struct radeon_device *rdev, bool low);
419void rv6xx_dpm_print_power_state(struct radeon_device *rdev,
420 struct radeon_ps *ps);
Alex Deucher242916a2013-06-28 14:20:53 -0400[diff] [blame]421void rv6xx_dpm_debugfs_print_current_performance_level(struct radeon_device *rdev,
422 struct seq_file *m);
Alex Deucherf4f85a82013-07-25 20:07:25 -0400[diff] [blame]423int rv6xx_dpm_force_performance_level(struct radeon_device *rdev,
424 enum radeon_dpm_forced_level level);
Alex Deucher9d670062013-04-12 13:59:22 -0400[diff] [blame]425/* rs780 dpm */
426int rs780_dpm_init(struct radeon_device *rdev);
427int rs780_dpm_enable(struct radeon_device *rdev);
428void rs780_dpm_disable(struct radeon_device *rdev);
429int rs780_dpm_set_power_state(struct radeon_device *rdev);
430void rs780_dpm_setup_asic(struct radeon_device *rdev);
431void rs780_dpm_display_configuration_changed(struct radeon_device *rdev);
432void rs780_dpm_fini(struct radeon_device *rdev);
433u32 rs780_dpm_get_sclk(struct radeon_device *rdev, bool low);
434u32 rs780_dpm_get_mclk(struct radeon_device *rdev, bool low);
435void rs780_dpm_print_power_state(struct radeon_device *rdev,
436 struct radeon_ps *ps);
Alex Deucher444bddc2013-07-02 13:05:23 -0400[diff] [blame]437void rs780_dpm_debugfs_print_current_performance_level(struct radeon_device *rdev,
438 struct seq_file *m);
Anthoine Bourgeois63580c32013-09-03 13:52:19 -0400[diff] [blame]439int rs780_dpm_force_performance_level(struct radeon_device *rdev,
440 enum radeon_dpm_forced_level level);
Jerome Glisse3ce0a232009-09-08 10:10:24 +1000[diff] [blame]441
Jerome Glisse3ce0a232009-09-08 10:10:24 +1000[diff] [blame]442/*
443 * rv770,rv730,rv710,rv740
444 */
445int rv770_init(struct radeon_device *rdev);
446void rv770_fini(struct radeon_device *rdev);
447int rv770_suspend(struct radeon_device *rdev);
448int rv770_resume(struct radeon_device *rdev);
Daniel Vetter3574dda2011-02-18 17:59:19 +0100[diff] [blame]449void rv770_pm_misc(struct radeon_device *rdev);
450u32 rv770_page_flip(struct radeon_device *rdev, int crtc, u64 crtc_base);
451void r700_vram_gtt_location(struct radeon_device *rdev, struct radeon_mc *mc);
452void r700_cp_stop(struct radeon_device *rdev);
453void r700_cp_fini(struct radeon_device *rdev);
Alex Deucher43fb7782013-01-04 09:24:18 -0500[diff] [blame]454int rv770_copy_dma(struct radeon_device *rdev,
455 uint64_t src_offset, uint64_t dst_offset,
456 unsigned num_gpu_pages,
457 struct radeon_fence **fence);
Alex Deucher454d2e22013-02-14 10:04:02 -0500[diff] [blame]458u32 rv770_get_xclk(struct radeon_device *rdev);
Christian Königef0e6e62013-04-08 12:41:35 +0200[diff] [blame]459int rv770_set_uvd_clocks(struct radeon_device *rdev, u32 vclk, u32 dclk);
Alex Deucher6bd1c382013-06-21 14:38:03 -0400[diff] [blame]460int rv770_get_temp(struct radeon_device *rdev);
Alex Deucher66229b22013-06-26 00:11:19 -0400[diff] [blame]461/* rv7xx pm */
462int rv770_dpm_init(struct radeon_device *rdev);
463int rv770_dpm_enable(struct radeon_device *rdev);
Alex Deuchera3f11242013-12-19 13:48:36 -0500[diff] [blame]464int rv770_dpm_late_enable(struct radeon_device *rdev);
Alex Deucher66229b22013-06-26 00:11:19 -0400[diff] [blame]465void rv770_dpm_disable(struct radeon_device *rdev);
466int rv770_dpm_set_power_state(struct radeon_device *rdev);
467void rv770_dpm_setup_asic(struct radeon_device *rdev);
468void rv770_dpm_display_configuration_changed(struct radeon_device *rdev);
469void rv770_dpm_fini(struct radeon_device *rdev);
470u32 rv770_dpm_get_sclk(struct radeon_device *rdev, bool low);
471u32 rv770_dpm_get_mclk(struct radeon_device *rdev, bool low);
472void rv770_dpm_print_power_state(struct radeon_device *rdev,
473 struct radeon_ps *ps);
Alex Deucherbd210d12013-06-28 10:06:26 -0400[diff] [blame]474void rv770_dpm_debugfs_print_current_performance_level(struct radeon_device *rdev,
475 struct seq_file *m);
Alex Deucher8b5e6b72013-07-02 18:40:35 -0400[diff] [blame]476int rv770_dpm_force_performance_level(struct radeon_device *rdev,
477 enum radeon_dpm_forced_level level);
Alex Deucherb06195d2013-07-08 11:49:48 -0400[diff] [blame]478bool rv770_dpm_vblank_too_short(struct radeon_device *rdev);
Jerome Glisse3ce0a232009-09-08 10:10:24 +1000[diff] [blame]479
Alex Deucherbcc1c2a2010-01-12 17:54:34 -0500[diff] [blame]480/*
481 * evergreen
482 */
Daniel Vetter3574dda2011-02-18 17:59:19 +0100[diff] [blame]483struct evergreen_mc_save {
Daniel Vetter3574dda2011-02-18 17:59:19 +0100[diff] [blame]484 u32 vga_render_control;
485 u32 vga_hdp_control;
Alex Deucher62444b72012-08-15 17:18:42 -0400[diff] [blame]486 bool crtc_enabled[RADEON_MAX_CRTCS];
Daniel Vetter3574dda2011-02-18 17:59:19 +0100[diff] [blame]487};
Jerome Glisse81ee8fb2012-07-27 16:32:24 -0400[diff] [blame]488
Alex Deucher0fcdb612010-03-24 13:20:41 -0400[diff] [blame]489void evergreen_pcie_gart_tlb_flush(struct radeon_device *rdev);
Alex Deucherbcc1c2a2010-01-12 17:54:34 -0500[diff] [blame]490int evergreen_init(struct radeon_device *rdev);
491void evergreen_fini(struct radeon_device *rdev);
492int evergreen_suspend(struct radeon_device *rdev);
493int evergreen_resume(struct radeon_device *rdev);
Alex Deucher123bc182013-01-24 11:37:19 -0500[diff] [blame]494bool evergreen_gfx_is_lockup(struct radeon_device *rdev, struct radeon_ring *cp);
495bool evergreen_dma_is_lockup(struct radeon_device *rdev, struct radeon_ring *cp);
Jerome Glissea2d07b72010-03-09 14:45:11 +0000[diff] [blame]496int evergreen_asic_reset(struct radeon_device *rdev);
Alex Deucherbcc1c2a2010-01-12 17:54:34 -0500[diff] [blame]497void evergreen_bandwidth_update(struct radeon_device *rdev);
Alex Deucher12920592011-02-02 12:37:40 -0500[diff] [blame]498void evergreen_ring_ib_execute(struct radeon_device *rdev, struct radeon_ib *ib);
Alex Deucherbcc1c2a2010-01-12 17:54:34 -0500[diff] [blame]499void evergreen_hpd_init(struct radeon_device *rdev);
500void evergreen_hpd_fini(struct radeon_device *rdev);
501bool evergreen_hpd_sense(struct radeon_device *rdev, enum radeon_hpd_id hpd);
502void evergreen_hpd_set_polarity(struct radeon_device *rdev,
503 enum radeon_hpd_id hpd);
Alex Deucher45f9a392010-03-24 13:55:51 -0400[diff] [blame]504u32 evergreen_get_vblank_counter(struct radeon_device *rdev, int crtc);
505int evergreen_irq_set(struct radeon_device *rdev);
506int evergreen_irq_process(struct radeon_device *rdev);
Alex Deuchercb5fcbd2010-05-28 19:01:35 -0400[diff] [blame]507extern int evergreen_cs_parse(struct radeon_cs_parser *p);
Alex Deucherd2ead3e2012-12-13 09:55:45 -0500[diff] [blame]508extern int evergreen_dma_cs_parse(struct radeon_cs_parser *p);
Alex Deucher49e02b72010-04-23 17:57:27 -0400[diff] [blame]509extern void evergreen_pm_misc(struct radeon_device *rdev);
510extern void evergreen_pm_prepare(struct radeon_device *rdev);
511extern void evergreen_pm_finish(struct radeon_device *rdev);
Alex Deuchera4c9e2e2011-11-04 10:09:41 -0400[diff] [blame]512extern void sumo_pm_init_profile(struct radeon_device *rdev);
Alex Deucher27810fb2012-10-01 19:25:11 -0400[diff] [blame]513extern void btc_pm_init_profile(struct radeon_device *rdev);
Alex Deucher23d33ba2013-04-08 12:41:32 +0200[diff] [blame]514int sumo_set_uvd_clocks(struct radeon_device *rdev, u32 vclk, u32 dclk);
Alex Deuchera8b49252013-04-08 12:41:33 +0200[diff] [blame]515int evergreen_set_uvd_clocks(struct radeon_device *rdev, u32 vclk, u32 dclk);
Alex Deucher6f34be52010-11-21 10:59:01 -0500[diff] [blame]516extern void evergreen_pre_page_flip(struct radeon_device *rdev, int crtc);
517extern u32 evergreen_page_flip(struct radeon_device *rdev, int crtc, u64 crtc_base);
518extern void evergreen_post_page_flip(struct radeon_device *rdev, int crtc);
Alex Deucher3ae19b72012-02-23 17:53:37 -0500[diff] [blame]519extern void dce4_wait_for_vblank(struct radeon_device *rdev, int crtc);
Daniel Vetter3574dda2011-02-18 17:59:19 +0100[diff] [blame]520void evergreen_disable_interrupt_state(struct radeon_device *rdev);
Alex Deucher89e51812012-02-23 17:53:38 -0500[diff] [blame]521int evergreen_mc_wait_for_idle(struct radeon_device *rdev);
Alex Deucher233d1ad2012-12-04 15:25:59 -0500[diff] [blame]522void evergreen_dma_fence_ring_emit(struct radeon_device *rdev,
523 struct radeon_fence *fence);
524void evergreen_dma_ring_ib_execute(struct radeon_device *rdev,
525 struct radeon_ib *ib);
526int evergreen_copy_dma(struct radeon_device *rdev,
527 uint64_t src_offset, uint64_t dst_offset,
528 unsigned num_gpu_pages,
529 struct radeon_fence **fence);
Alex Deuchera973bea2013-04-18 11:32:16 -0400[diff] [blame]530void evergreen_hdmi_enable(struct drm_encoder *encoder, bool enable);
531void evergreen_hdmi_setmode(struct drm_encoder *encoder, struct drm_display_mode *mode);
Alex Deucher6bd1c382013-06-21 14:38:03 -0400[diff] [blame]532int evergreen_get_temp(struct radeon_device *rdev);
533int sumo_get_temp(struct radeon_device *rdev);
Alex Deucher29a15222012-12-14 11:57:36 -0500[diff] [blame]534int tn_get_temp(struct radeon_device *rdev);
Alex Deucherdc50ba72013-06-26 00:33:35 -0400[diff] [blame]535int cypress_dpm_init(struct radeon_device *rdev);
536void cypress_dpm_setup_asic(struct radeon_device *rdev);
537int cypress_dpm_enable(struct radeon_device *rdev);
538void cypress_dpm_disable(struct radeon_device *rdev);
539int cypress_dpm_set_power_state(struct radeon_device *rdev);
540void cypress_dpm_display_configuration_changed(struct radeon_device *rdev);
541void cypress_dpm_fini(struct radeon_device *rdev);
Alex Deucherd0b54bd2013-07-08 11:56:09 -0400[diff] [blame]542bool cypress_dpm_vblank_too_short(struct radeon_device *rdev);
Alex Deucher6596afd2013-06-26 00:15:24 -0400[diff] [blame]543int btc_dpm_init(struct radeon_device *rdev);
544void btc_dpm_setup_asic(struct radeon_device *rdev);
545int btc_dpm_enable(struct radeon_device *rdev);
546void btc_dpm_disable(struct radeon_device *rdev);
Alex Deuchere8a95392013-01-16 14:17:23 -0500[diff] [blame]547int btc_dpm_pre_set_power_state(struct radeon_device *rdev);
Alex Deucher6596afd2013-06-26 00:15:24 -0400[diff] [blame]548int btc_dpm_set_power_state(struct radeon_device *rdev);
Alex Deuchere8a95392013-01-16 14:17:23 -0500[diff] [blame]549void btc_dpm_post_set_power_state(struct radeon_device *rdev);
Alex Deucher6596afd2013-06-26 00:15:24 -0400[diff] [blame]550void btc_dpm_fini(struct radeon_device *rdev);
Alex Deuchere8a95392013-01-16 14:17:23 -0500[diff] [blame]551u32 btc_dpm_get_sclk(struct radeon_device *rdev, bool low);
552u32 btc_dpm_get_mclk(struct radeon_device *rdev, bool low);
Alex Deuchera84301c2013-07-08 12:03:55 -0400[diff] [blame]553bool btc_dpm_vblank_too_short(struct radeon_device *rdev);
Alex Deucher9f3f63f2014-01-30 11:19:22 -0500[diff] [blame]554void btc_dpm_debugfs_print_current_performance_level(struct radeon_device *rdev,
555 struct seq_file *m);
Alex Deucher80ea2c12013-04-12 14:56:21 -0400[diff] [blame]556int sumo_dpm_init(struct radeon_device *rdev);
557int sumo_dpm_enable(struct radeon_device *rdev);
Alex Deucher14ec9fa2013-12-19 11:56:52 -0500[diff] [blame]558int sumo_dpm_late_enable(struct radeon_device *rdev);
Alex Deucher80ea2c12013-04-12 14:56:21 -0400[diff] [blame]559void sumo_dpm_disable(struct radeon_device *rdev);
Alex Deucher422a56b2013-06-25 15:40:21 -0400[diff] [blame]560int sumo_dpm_pre_set_power_state(struct radeon_device *rdev);
Alex Deucher80ea2c12013-04-12 14:56:21 -0400[diff] [blame]561int sumo_dpm_set_power_state(struct radeon_device *rdev);
Alex Deucher422a56b2013-06-25 15:40:21 -0400[diff] [blame]562void sumo_dpm_post_set_power_state(struct radeon_device *rdev);
Alex Deucher80ea2c12013-04-12 14:56:21 -0400[diff] [blame]563void sumo_dpm_setup_asic(struct radeon_device *rdev);
564void sumo_dpm_display_configuration_changed(struct radeon_device *rdev);
565void sumo_dpm_fini(struct radeon_device *rdev);
566u32 sumo_dpm_get_sclk(struct radeon_device *rdev, bool low);
567u32 sumo_dpm_get_mclk(struct radeon_device *rdev, bool low);
568void sumo_dpm_print_power_state(struct radeon_device *rdev,
569 struct radeon_ps *ps);
Alex Deucherfb701602013-06-28 10:47:56 -0400[diff] [blame]570void sumo_dpm_debugfs_print_current_performance_level(struct radeon_device *rdev,
571 struct seq_file *m);
Alex Deucher5d5e5592013-07-02 18:50:09 -0400[diff] [blame]572int sumo_dpm_force_performance_level(struct radeon_device *rdev,
573 enum radeon_dpm_forced_level level);
Daniel Vetter4546b2c2011-02-18 17:59:21 +0100[diff] [blame]574
Alex Deuchere3487622011-03-02 20:07:36 -0500[diff] [blame]575/*
576 * cayman
577 */
Alex Deucherb40e7e12011-11-17 14:57:50 -0500[diff] [blame]578void cayman_fence_ring_emit(struct radeon_device *rdev,
579 struct radeon_fence *fence);
Alex Deuchere3487622011-03-02 20:07:36 -0500[diff] [blame]580void cayman_pcie_gart_tlb_flush(struct radeon_device *rdev);
581int cayman_init(struct radeon_device *rdev);
582void cayman_fini(struct radeon_device *rdev);
583int cayman_suspend(struct radeon_device *rdev);
584int cayman_resume(struct radeon_device *rdev);
Alex Deuchere3487622011-03-02 20:07:36 -0500[diff] [blame]585int cayman_asic_reset(struct radeon_device *rdev);
Jerome Glisse721604a2012-01-05 22:11:05 -0500[diff] [blame]586void cayman_ring_ib_execute(struct radeon_device *rdev, struct radeon_ib *ib);
587int cayman_vm_init(struct radeon_device *rdev);
588void cayman_vm_fini(struct radeon_device *rdev);
Alex Deucher498522b2012-10-02 14:43:38 -0400[diff] [blame]589void cayman_vm_flush(struct radeon_device *rdev, int ridx, struct radeon_vm *vm);
Christian König089a7862012-08-11 11:54:05 +0200[diff] [blame]590uint32_t cayman_vm_page_flags(struct radeon_device *rdev, uint32_t flags);
Jerome Glisse721604a2012-01-05 22:11:05 -0500[diff] [blame]591int evergreen_ib_parse(struct radeon_device *rdev, struct radeon_ib *ib);
Alex Deuchercd459e52012-12-13 12:17:38 -0500[diff] [blame]592int evergreen_dma_ib_parse(struct radeon_device *rdev, struct radeon_ib *ib);
Alex Deucherf60cbd12012-12-04 15:27:33 -0500[diff] [blame]593void cayman_dma_ring_ib_execute(struct radeon_device *rdev,
594 struct radeon_ib *ib);
Alex Deucher123bc182013-01-24 11:37:19 -0500[diff] [blame]595bool cayman_gfx_is_lockup(struct radeon_device *rdev, struct radeon_ring *ring);
Alex Deucherf60cbd12012-12-04 15:27:33 -0500[diff] [blame]596bool cayman_dma_is_lockup(struct radeon_device *rdev, struct radeon_ring *ring);
Christian König24c16432013-10-30 11:51:09 -0400[diff] [blame]597void cayman_dma_vm_set_page(struct radeon_device *rdev,
598 struct radeon_ib *ib,
599 uint64_t pe,
600 uint64_t addr, unsigned count,
601 uint32_t incr, uint32_t flags);
602
Alex Deucherf60cbd12012-12-04 15:27:33 -0500[diff] [blame]603void cayman_dma_vm_flush(struct radeon_device *rdev, int ridx, struct radeon_vm *vm);
Alex Deucher45f9a392010-03-24 13:55:51 -0400[diff] [blame]604
Alex Deucherea31bf62013-12-09 19:44:30 -0500[diff] [blame]605u32 cayman_gfx_get_rptr(struct radeon_device *rdev,
606 struct radeon_ring *ring);
607u32 cayman_gfx_get_wptr(struct radeon_device *rdev,
608 struct radeon_ring *ring);
609void cayman_gfx_set_wptr(struct radeon_device *rdev,
610 struct radeon_ring *ring);
611uint32_t cayman_dma_get_rptr(struct radeon_device *rdev,
612 struct radeon_ring *ring);
613uint32_t cayman_dma_get_wptr(struct radeon_device *rdev,
614 struct radeon_ring *ring);
615void cayman_dma_set_wptr(struct radeon_device *rdev,
616 struct radeon_ring *ring);
617
Alex Deucher69e0b572013-04-12 16:42:42 -0400[diff] [blame]618int ni_dpm_init(struct radeon_device *rdev);
619void ni_dpm_setup_asic(struct radeon_device *rdev);
620int ni_dpm_enable(struct radeon_device *rdev);
621void ni_dpm_disable(struct radeon_device *rdev);
Alex Deucherfee3d742013-01-16 14:35:39 -0500[diff] [blame]622int ni_dpm_pre_set_power_state(struct radeon_device *rdev);
Alex Deucher69e0b572013-04-12 16:42:42 -0400[diff] [blame]623int ni_dpm_set_power_state(struct radeon_device *rdev);
Alex Deucherfee3d742013-01-16 14:35:39 -0500[diff] [blame]624void ni_dpm_post_set_power_state(struct radeon_device *rdev);
Alex Deucher69e0b572013-04-12 16:42:42 -0400[diff] [blame]625void ni_dpm_fini(struct radeon_device *rdev);
626u32 ni_dpm_get_sclk(struct radeon_device *rdev, bool low);
627u32 ni_dpm_get_mclk(struct radeon_device *rdev, bool low);
628void ni_dpm_print_power_state(struct radeon_device *rdev,
629 struct radeon_ps *ps);
Alex Deucherbdf0c4f2013-06-28 17:49:02 -0400[diff] [blame]630void ni_dpm_debugfs_print_current_performance_level(struct radeon_device *rdev,
631 struct seq_file *m);
Alex Deucher170a47f2013-07-02 18:43:53 -0400[diff] [blame]632int ni_dpm_force_performance_level(struct radeon_device *rdev,
633 enum radeon_dpm_forced_level level);
Alex Deucher76ad73e2013-07-08 12:09:41 -0400[diff] [blame]634bool ni_dpm_vblank_too_short(struct radeon_device *rdev);
Alex Deucherd70229f2013-04-12 16:40:41 -0400[diff] [blame]635int trinity_dpm_init(struct radeon_device *rdev);
636int trinity_dpm_enable(struct radeon_device *rdev);
Alex Deucherbda44c12013-12-19 12:03:35 -0500[diff] [blame]637int trinity_dpm_late_enable(struct radeon_device *rdev);
Alex Deucherd70229f2013-04-12 16:40:41 -0400[diff] [blame]638void trinity_dpm_disable(struct radeon_device *rdev);
Alex Deuchera284c482013-01-16 13:53:40 -0500[diff] [blame]639int trinity_dpm_pre_set_power_state(struct radeon_device *rdev);
Alex Deucherd70229f2013-04-12 16:40:41 -0400[diff] [blame]640int trinity_dpm_set_power_state(struct radeon_device *rdev);
Alex Deuchera284c482013-01-16 13:53:40 -0500[diff] [blame]641void trinity_dpm_post_set_power_state(struct radeon_device *rdev);
Alex Deucherd70229f2013-04-12 16:40:41 -0400[diff] [blame]642void trinity_dpm_setup_asic(struct radeon_device *rdev);
643void trinity_dpm_display_configuration_changed(struct radeon_device *rdev);
644void trinity_dpm_fini(struct radeon_device *rdev);
645u32 trinity_dpm_get_sclk(struct radeon_device *rdev, bool low);
646u32 trinity_dpm_get_mclk(struct radeon_device *rdev, bool low);
647void trinity_dpm_print_power_state(struct radeon_device *rdev,
648 struct radeon_ps *ps);
Alex Deucher490ab932013-06-28 12:01:38 -0400[diff] [blame]649void trinity_dpm_debugfs_print_current_performance_level(struct radeon_device *rdev,
650 struct seq_file *m);
Alex Deucher9b5de592013-07-02 18:52:10 -0400[diff] [blame]651int trinity_dpm_force_performance_level(struct radeon_device *rdev,
652 enum radeon_dpm_forced_level level);
Alex Deucher11877062013-09-09 19:19:52 -0400[diff] [blame]653void trinity_dpm_enable_bapm(struct radeon_device *rdev, bool enable);
Alex Deucherd70229f2013-04-12 16:40:41 -0400[diff] [blame]654
Alex Deucher43b3cd92012-03-20 17:18:00 -0400[diff] [blame]655/* DCE6 - SI */
656void dce6_bandwidth_update(struct radeon_device *rdev);
Alex Deucherb5306022013-07-31 16:51:33 -0400[diff] [blame]657int dce6_audio_init(struct radeon_device *rdev);
658void dce6_audio_fini(struct radeon_device *rdev);
Alex Deucher43b3cd92012-03-20 17:18:00 -0400[diff] [blame]659
Alex Deucher02779c02012-03-20 17:18:25 -0400[diff] [blame]660/*
661 * si
662 */
663void si_fence_ring_emit(struct radeon_device *rdev,
664 struct radeon_fence *fence);
665void si_pcie_gart_tlb_flush(struct radeon_device *rdev);
666int si_init(struct radeon_device *rdev);
667void si_fini(struct radeon_device *rdev);
668int si_suspend(struct radeon_device *rdev);
669int si_resume(struct radeon_device *rdev);
Alex Deucher123bc182013-01-24 11:37:19 -0500[diff] [blame]670bool si_gfx_is_lockup(struct radeon_device *rdev, struct radeon_ring *cp);
671bool si_dma_is_lockup(struct radeon_device *rdev, struct radeon_ring *cp);
Alex Deucher02779c02012-03-20 17:18:25 -0400[diff] [blame]672int si_asic_reset(struct radeon_device *rdev);
673void si_ring_ib_execute(struct radeon_device *rdev, struct radeon_ib *ib);
674int si_irq_set(struct radeon_device *rdev);
675int si_irq_process(struct radeon_device *rdev);
676int si_vm_init(struct radeon_device *rdev);
677void si_vm_fini(struct radeon_device *rdev);
Alex Deucher498522b2012-10-02 14:43:38 -0400[diff] [blame]678void si_vm_flush(struct radeon_device *rdev, int ridx, struct radeon_vm *vm);
Alex Deucher02779c02012-03-20 17:18:25 -0400[diff] [blame]679int si_ib_parse(struct radeon_device *rdev, struct radeon_ib *ib);
Alex Deucher8c5fd7e2012-12-04 15:28:18 -0500[diff] [blame]680int si_copy_dma(struct radeon_device *rdev,
681 uint64_t src_offset, uint64_t dst_offset,
682 unsigned num_gpu_pages,
683 struct radeon_fence **fence);
Christian König24c16432013-10-30 11:51:09 -0400[diff] [blame]684void si_dma_vm_set_page(struct radeon_device *rdev,
685 struct radeon_ib *ib,
686 uint64_t pe,
687 uint64_t addr, unsigned count,
688 uint32_t incr, uint32_t flags);
Alex Deucher8c5fd7e2012-12-04 15:28:18 -0500[diff] [blame]689void si_dma_vm_flush(struct radeon_device *rdev, int ridx, struct radeon_vm *vm);
Alex Deucher454d2e22013-02-14 10:04:02 -0500[diff] [blame]690u32 si_get_xclk(struct radeon_device *rdev);
Alex Deucherd0418892013-01-24 10:35:23 -0500[diff] [blame]691uint64_t si_get_gpu_clock_counter(struct radeon_device *rdev);
Christian König2539eb02013-04-08 12:41:34 +0200[diff] [blame]692int si_set_uvd_clocks(struct radeon_device *rdev, u32 vclk, u32 dclk);
Alex Deucher6bd1c382013-06-21 14:38:03 -0400[diff] [blame]693int si_get_temp(struct radeon_device *rdev);
Alex Deuchera9e61412013-06-25 17:56:16 -0400[diff] [blame]694int si_dpm_init(struct radeon_device *rdev);
695void si_dpm_setup_asic(struct radeon_device *rdev);
696int si_dpm_enable(struct radeon_device *rdev);
Alex Deucher963c1152013-12-19 13:54:35 -0500[diff] [blame]697int si_dpm_late_enable(struct radeon_device *rdev);
Alex Deuchera9e61412013-06-25 17:56:16 -0400[diff] [blame]698void si_dpm_disable(struct radeon_device *rdev);
699int si_dpm_pre_set_power_state(struct radeon_device *rdev);
700int si_dpm_set_power_state(struct radeon_device *rdev);
701void si_dpm_post_set_power_state(struct radeon_device *rdev);
702void si_dpm_fini(struct radeon_device *rdev);
703void si_dpm_display_configuration_changed(struct radeon_device *rdev);
Alex Deucher79821282013-06-28 18:02:19 -0400[diff] [blame]704void si_dpm_debugfs_print_current_performance_level(struct radeon_device *rdev,
705 struct seq_file *m);
Alex Deuchera160a6a2013-07-02 18:46:28 -0400[diff] [blame]706int si_dpm_force_performance_level(struct radeon_device *rdev,
707 enum radeon_dpm_forced_level level);
Alex Deucher02779c02012-03-20 17:18:25 -0400[diff] [blame]708
Alex Deucher0672e272013-04-09 16:22:31 -0400[diff] [blame]709/* DCE8 - CIK */
710void dce8_bandwidth_update(struct radeon_device *rdev);
711
Alex Deucher44fa3462012-12-18 22:17:00 -0500[diff] [blame]712/*
713 * cik
714 */
715uint64_t cik_get_gpu_clock_counter(struct radeon_device *rdev);
Alex Deucher2c679122013-04-09 13:32:18 -0400[diff] [blame]716u32 cik_get_xclk(struct radeon_device *rdev);
Alex Deucher6e2c3c02013-04-03 19:28:32 -0400[diff] [blame]717uint32_t cik_pciep_rreg(struct radeon_device *rdev, uint32_t reg);
718void cik_pciep_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v);
Christian König87167bb2013-04-09 13:39:21 -0400[diff] [blame]719int cik_set_uvd_clocks(struct radeon_device *rdev, u32 vclk, u32 dclk);
Alex Deucher0672e272013-04-09 16:22:31 -0400[diff] [blame]720void cik_sdma_fence_ring_emit(struct radeon_device *rdev,
721 struct radeon_fence *fence);
Christian König1654b812013-11-12 12:58:05 +0100[diff] [blame]722bool cik_sdma_semaphore_ring_emit(struct radeon_device *rdev,
Alex Deucher0672e272013-04-09 16:22:31 -0400[diff] [blame]723 struct radeon_ring *ring,
724 struct radeon_semaphore *semaphore,
725 bool emit_wait);
726void cik_sdma_ring_ib_execute(struct radeon_device *rdev, struct radeon_ib *ib);
727int cik_copy_dma(struct radeon_device *rdev,
728 uint64_t src_offset, uint64_t dst_offset,
729 unsigned num_gpu_pages,
730 struct radeon_fence **fence);
Alex Deucherc9dbd702013-10-01 16:36:51 -0400[diff] [blame]731int cik_copy_cpdma(struct radeon_device *rdev,
732 uint64_t src_offset, uint64_t dst_offset,
733 unsigned num_gpu_pages,
734 struct radeon_fence **fence);
Alex Deucher0672e272013-04-09 16:22:31 -0400[diff] [blame]735int cik_sdma_ring_test(struct radeon_device *rdev, struct radeon_ring *ring);
736int cik_sdma_ib_test(struct radeon_device *rdev, struct radeon_ring *ring);
737bool cik_sdma_is_lockup(struct radeon_device *rdev, struct radeon_ring *ring);
738void cik_fence_gfx_ring_emit(struct radeon_device *rdev,
739 struct radeon_fence *fence);
740void cik_fence_compute_ring_emit(struct radeon_device *rdev,
741 struct radeon_fence *fence);
Christian König1654b812013-11-12 12:58:05 +0100[diff] [blame]742bool cik_semaphore_ring_emit(struct radeon_device *rdev,
Alex Deucher0672e272013-04-09 16:22:31 -0400[diff] [blame]743 struct radeon_ring *cp,
744 struct radeon_semaphore *semaphore,
745 bool emit_wait);
746void cik_pcie_gart_tlb_flush(struct radeon_device *rdev);
747int cik_init(struct radeon_device *rdev);
748void cik_fini(struct radeon_device *rdev);
749int cik_suspend(struct radeon_device *rdev);
750int cik_resume(struct radeon_device *rdev);
751bool cik_gfx_is_lockup(struct radeon_device *rdev, struct radeon_ring *cp);
752int cik_asic_reset(struct radeon_device *rdev);
753void cik_ring_ib_execute(struct radeon_device *rdev, struct radeon_ib *ib);
754int cik_ring_test(struct radeon_device *rdev, struct radeon_ring *ring);
755int cik_ib_test(struct radeon_device *rdev, struct radeon_ring *ring);
756int cik_irq_set(struct radeon_device *rdev);
757int cik_irq_process(struct radeon_device *rdev);
758int cik_vm_init(struct radeon_device *rdev);
759void cik_vm_fini(struct radeon_device *rdev);
760void cik_vm_flush(struct radeon_device *rdev, int ridx, struct radeon_vm *vm);
Christian König24c16432013-10-30 11:51:09 -0400[diff] [blame]761void cik_sdma_vm_set_page(struct radeon_device *rdev,
762 struct radeon_ib *ib,
763 uint64_t pe,
764 uint64_t addr, unsigned count,
765 uint32_t incr, uint32_t flags);
Alex Deucher0672e272013-04-09 16:22:31 -0400[diff] [blame]766void cik_dma_vm_flush(struct radeon_device *rdev, int ridx, struct radeon_vm *vm);
767int cik_ib_parse(struct radeon_device *rdev, struct radeon_ib *ib);
Alex Deucherea31bf62013-12-09 19:44:30 -0500[diff] [blame]768u32 cik_gfx_get_rptr(struct radeon_device *rdev,
769 struct radeon_ring *ring);
770u32 cik_gfx_get_wptr(struct radeon_device *rdev,
771 struct radeon_ring *ring);
772void cik_gfx_set_wptr(struct radeon_device *rdev,
773 struct radeon_ring *ring);
774u32 cik_compute_get_rptr(struct radeon_device *rdev,
775 struct radeon_ring *ring);
776u32 cik_compute_get_wptr(struct radeon_device *rdev,
777 struct radeon_ring *ring);
778void cik_compute_set_wptr(struct radeon_device *rdev,
779 struct radeon_ring *ring);
780u32 cik_sdma_get_rptr(struct radeon_device *rdev,
781 struct radeon_ring *ring);
782u32 cik_sdma_get_wptr(struct radeon_device *rdev,
783 struct radeon_ring *ring);
784void cik_sdma_set_wptr(struct radeon_device *rdev,
785 struct radeon_ring *ring);
Alex Deucher286d9cc2013-06-21 15:50:47 -0400[diff] [blame]786int ci_get_temp(struct radeon_device *rdev);
787int kv_get_temp(struct radeon_device *rdev);
Alex Deucher44fa3462012-12-18 22:17:00 -0500[diff] [blame]788
Alex Deuchercc8dbbb2013-08-14 01:03:41 -0400[diff] [blame]789int ci_dpm_init(struct radeon_device *rdev);
790int ci_dpm_enable(struct radeon_device *rdev);
Alex Deucher90208422013-12-19 13:59:46 -0500[diff] [blame]791int ci_dpm_late_enable(struct radeon_device *rdev);
Alex Deuchercc8dbbb2013-08-14 01:03:41 -0400[diff] [blame]792void ci_dpm_disable(struct radeon_device *rdev);
793int ci_dpm_pre_set_power_state(struct radeon_device *rdev);
794int ci_dpm_set_power_state(struct radeon_device *rdev);
795void ci_dpm_post_set_power_state(struct radeon_device *rdev);
796void ci_dpm_setup_asic(struct radeon_device *rdev);
797void ci_dpm_display_configuration_changed(struct radeon_device *rdev);
798void ci_dpm_fini(struct radeon_device *rdev);
799u32 ci_dpm_get_sclk(struct radeon_device *rdev, bool low);
800u32 ci_dpm_get_mclk(struct radeon_device *rdev, bool low);
801void ci_dpm_print_power_state(struct radeon_device *rdev,
802 struct radeon_ps *ps);
Alex Deucher94b4adc2013-07-15 17:34:33 -0400[diff] [blame]803void ci_dpm_debugfs_print_current_performance_level(struct radeon_device *rdev,
804 struct seq_file *m);
Alex Deucher89536fd2013-07-15 18:14:24 -0400[diff] [blame]805int ci_dpm_force_performance_level(struct radeon_device *rdev,
806 enum radeon_dpm_forced_level level);
Alex Deucher54961312013-07-15 18:24:31 -0400[diff] [blame]807bool ci_dpm_vblank_too_short(struct radeon_device *rdev);
Alex Deucher942bdf72013-08-09 10:05:24 -0400[diff] [blame]808void ci_dpm_powergate_uvd(struct radeon_device *rdev, bool gate);
Alex Deuchercc8dbbb2013-08-14 01:03:41 -0400[diff] [blame]809
Alex Deucher41a524a2013-08-14 01:01:40 -0400[diff] [blame]810int kv_dpm_init(struct radeon_device *rdev);
811int kv_dpm_enable(struct radeon_device *rdev);
Alex Deucherd8852c32013-12-19 14:03:36 -0500[diff] [blame]812int kv_dpm_late_enable(struct radeon_device *rdev);
Alex Deucher41a524a2013-08-14 01:01:40 -0400[diff] [blame]813void kv_dpm_disable(struct radeon_device *rdev);
814int kv_dpm_pre_set_power_state(struct radeon_device *rdev);
815int kv_dpm_set_power_state(struct radeon_device *rdev);
816void kv_dpm_post_set_power_state(struct radeon_device *rdev);
817void kv_dpm_setup_asic(struct radeon_device *rdev);
818void kv_dpm_display_configuration_changed(struct radeon_device *rdev);
819void kv_dpm_fini(struct radeon_device *rdev);
820u32 kv_dpm_get_sclk(struct radeon_device *rdev, bool low);
821u32 kv_dpm_get_mclk(struct radeon_device *rdev, bool low);
822void kv_dpm_print_power_state(struct radeon_device *rdev,
823 struct radeon_ps *ps);
Alex Deucherae3e40e2013-07-18 16:39:53 -0400[diff] [blame]824void kv_dpm_debugfs_print_current_performance_level(struct radeon_device *rdev,
825 struct seq_file *m);
Alex Deucher2b4c8022013-07-18 16:48:46 -0400[diff] [blame]826int kv_dpm_force_performance_level(struct radeon_device *rdev,
827 enum radeon_dpm_forced_level level);
Alex Deucher77df5082013-08-09 10:02:40 -0400[diff] [blame]828void kv_dpm_powergate_uvd(struct radeon_device *rdev, bool gate);
Alex Deucherb7a5ae92013-09-09 19:33:08 -0400[diff] [blame]829void kv_dpm_enable_bapm(struct radeon_device *rdev, bool enable);
Alex Deucher41a524a2013-08-14 01:01:40 -0400[diff] [blame]830
Christian Könige409b122013-08-13 11:56:53 +0200[diff] [blame]831/* uvd v1.0 */
832uint32_t uvd_v1_0_get_rptr(struct radeon_device *rdev,
833 struct radeon_ring *ring);
834uint32_t uvd_v1_0_get_wptr(struct radeon_device *rdev,
835 struct radeon_ring *ring);
836void uvd_v1_0_set_wptr(struct radeon_device *rdev,
837 struct radeon_ring *ring);
838
839int uvd_v1_0_init(struct radeon_device *rdev);
840void uvd_v1_0_fini(struct radeon_device *rdev);
841int uvd_v1_0_start(struct radeon_device *rdev);
842void uvd_v1_0_stop(struct radeon_device *rdev);
843
844int uvd_v1_0_ring_test(struct radeon_device *rdev, struct radeon_ring *ring);
845int uvd_v1_0_ib_test(struct radeon_device *rdev, struct radeon_ring *ring);
Christian König1654b812013-11-12 12:58:05 +0100[diff] [blame]846bool uvd_v1_0_semaphore_emit(struct radeon_device *rdev,
Christian Könige409b122013-08-13 11:56:53 +0200[diff] [blame]847 struct radeon_ring *ring,
848 struct radeon_semaphore *semaphore,
849 bool emit_wait);
850void uvd_v1_0_ib_execute(struct radeon_device *rdev, struct radeon_ib *ib);
851
852/* uvd v2.2 */
853int uvd_v2_2_resume(struct radeon_device *rdev);
854void uvd_v2_2_fence_emit(struct radeon_device *rdev,
855 struct radeon_fence *fence);
856
857/* uvd v3.1 */
Christian König1654b812013-11-12 12:58:05 +0100[diff] [blame]858bool uvd_v3_1_semaphore_emit(struct radeon_device *rdev,
Christian Könige409b122013-08-13 11:56:53 +0200[diff] [blame]859 struct radeon_ring *ring,
860 struct radeon_semaphore *semaphore,
861 bool emit_wait);
862
863/* uvd v4.2 */
864int uvd_v4_2_resume(struct radeon_device *rdev);
865
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200[diff] [blame]866#endif