Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1 | #ifndef CCISS_H |
| 2 | #define CCISS_H |
| 3 | |
| 4 | #include <linux/genhd.h> |
Andrew Patterson | b368c9d | 2009-09-17 13:46:58 -0500 | [diff] [blame] | 5 | #include <linux/mutex.h> |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 6 | |
| 7 | #include "cciss_cmd.h" |
| 8 | |
| 9 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 10 | #define NWD_SHIFT 4 |
| 11 | #define MAX_PART (1 << NWD_SHIFT) |
| 12 | |
| 13 | #define IO_OK 0 |
| 14 | #define IO_ERROR 1 |
scameron@beardog.cca.cpqcorp.net | 789a424 | 2009-06-08 16:05:56 -0500 | [diff] [blame] | 15 | #define IO_NEEDS_RETRY 3 |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 16 | |
Andrew Patterson | 7fe0632 | 2009-06-02 14:48:39 +0200 | [diff] [blame] | 17 | #define VENDOR_LEN 8 |
| 18 | #define MODEL_LEN 16 |
| 19 | #define REV_LEN 4 |
| 20 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 21 | struct ctlr_info; |
| 22 | typedef struct ctlr_info ctlr_info_t; |
| 23 | |
| 24 | struct access_method { |
| 25 | void (*submit_command)(ctlr_info_t *h, CommandList_struct *c); |
| 26 | void (*set_intr_mask)(ctlr_info_t *h, unsigned long val); |
| 27 | unsigned long (*fifo_full)(ctlr_info_t *h); |
| 28 | unsigned long (*intr_pending)(ctlr_info_t *h); |
| 29 | unsigned long (*command_completed)(ctlr_info_t *h); |
| 30 | }; |
| 31 | typedef struct _drive_info_struct |
| 32 | { |
Stephen M. Cameron | 39ccf9a | 2009-09-17 13:48:00 -0500 | [diff] [blame] | 33 | unsigned char LunID[8]; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 34 | int usage_count; |
Mike Miller | ad2b931 | 2005-07-28 01:07:31 -0700 | [diff] [blame] | 35 | struct request_queue *queue; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 36 | sector_t nr_blocks; |
| 37 | int block_size; |
| 38 | int heads; |
| 39 | int sectors; |
| 40 | int cylinders; |
Mike Miller | ddd4744 | 2005-09-13 01:25:22 -0700 | [diff] [blame] | 41 | int raid_level; /* set to -1 to indicate that |
| 42 | * the drive is not in use/configured |
Andrew Patterson | 7fe0632 | 2009-06-02 14:48:39 +0200 | [diff] [blame] | 43 | */ |
| 44 | int busy_configuring; /* This is set when a drive is being removed |
| 45 | * to prevent it from being opened or it's |
| 46 | * queue from being started. |
| 47 | */ |
Stephen M. Cameron | 9cef0d2 | 2009-09-17 13:48:31 -0500 | [diff] [blame] | 48 | struct device dev; |
Andrew Patterson | 7fe0632 | 2009-06-02 14:48:39 +0200 | [diff] [blame] | 49 | __u8 serial_no[16]; /* from inquiry page 0x83, |
| 50 | * not necc. null terminated. |
| 51 | */ |
| 52 | char vendor[VENDOR_LEN + 1]; /* SCSI vendor string */ |
| 53 | char model[MODEL_LEN + 1]; /* SCSI model string */ |
| 54 | char rev[REV_LEN + 1]; /* SCSI revision string */ |
Stephen M. Cameron | 9cef0d2 | 2009-09-17 13:48:31 -0500 | [diff] [blame] | 55 | char device_initialized; /* indicates whether dev is initialized */ |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 56 | } drive_info_struct; |
| 57 | |
| 58 | struct ctlr_info |
| 59 | { |
| 60 | int ctlr; |
| 61 | char devname[8]; |
| 62 | char *product_name; |
| 63 | char firm_ver[4]; // Firmware version |
| 64 | struct pci_dev *pdev; |
| 65 | __u32 board_id; |
| 66 | void __iomem *vaddr; |
| 67 | unsigned long paddr; |
Mike Miller | f880632 | 2006-12-06 20:35:01 -0800 | [diff] [blame] | 68 | int nr_cmds; /* Number of commands allowed on this controller */ |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 69 | CfgTable_struct __iomem *cfgtable; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 70 | int interrupts_enabled; |
| 71 | int major; |
| 72 | int max_commands; |
| 73 | int commands_outstanding; |
| 74 | int max_outstanding; /* Debug */ |
| 75 | int num_luns; |
| 76 | int highest_lun; |
| 77 | int usage_count; /* number of opens all all minor devices */ |
Mike Miller | fb86a35 | 2006-01-08 01:03:50 -0800 | [diff] [blame] | 78 | # define DOORBELL_INT 0 |
| 79 | # define PERF_MODE_INT 1 |
| 80 | # define SIMPLE_MODE_INT 2 |
| 81 | # define MEMQ_MODE_INT 3 |
| 82 | unsigned int intr[4]; |
| 83 | unsigned int msix_vector; |
| 84 | unsigned int msi_vector; |
Mike Miller | 92c4231a | 2006-12-06 20:35:06 -0800 | [diff] [blame] | 85 | int cciss_max_sectors; |
Mike Miller (OS Dev) | 00988a3 | 2006-09-30 23:27:23 -0700 | [diff] [blame] | 86 | BYTE cciss_read; |
| 87 | BYTE cciss_write; |
| 88 | BYTE cciss_read_capacity; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 89 | |
| 90 | // information about each logical volume |
Stephen M. Cameron | 9cef0d2 | 2009-09-17 13:48:31 -0500 | [diff] [blame] | 91 | drive_info_struct *drv[CISS_MAX_LUN]; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 92 | |
| 93 | struct access_method access; |
| 94 | |
| 95 | /* queue and queue Info */ |
Jens Axboe | 8a3173d | 2008-11-20 09:46:09 +0100 | [diff] [blame] | 96 | struct hlist_head reqQ; |
| 97 | struct hlist_head cmpQ; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 98 | unsigned int Qdepth; |
| 99 | unsigned int maxQsinceinit; |
| 100 | unsigned int maxSG; |
| 101 | spinlock_t lock; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 102 | |
| 103 | //* pointers to command and error info pool */ |
| 104 | CommandList_struct *cmd_pool; |
| 105 | dma_addr_t cmd_pool_dhandle; |
| 106 | ErrorInfo_struct *errinfo_pool; |
| 107 | dma_addr_t errinfo_pool_dhandle; |
| 108 | unsigned long *cmd_pool_bits; |
| 109 | int nr_allocs; |
| 110 | int nr_frees; |
| 111 | int busy_configuring; |
Mike Miller | 1f8ef38 | 2005-09-13 01:25:21 -0700 | [diff] [blame] | 112 | int busy_initializing; |
Andrew Patterson | b368c9d | 2009-09-17 13:46:58 -0500 | [diff] [blame] | 113 | int busy_scanning; |
| 114 | struct mutex busy_shutting_down; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 115 | |
| 116 | /* This element holds the zero based queue number of the last |
| 117 | * queue to be started. It is used for fairness. |
| 118 | */ |
| 119 | int next_to_run; |
| 120 | |
| 121 | // Disk structures we need to pass back |
Mike Miller | 799202c | 2006-12-06 20:35:12 -0800 | [diff] [blame] | 122 | struct gendisk *gendisk[CISS_MAX_LUN]; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 123 | #ifdef CONFIG_CISS_SCSI_TAPE |
| 124 | void *scsi_ctlr; /* ptr to structure containing scsi related stuff */ |
mike.miller@hp.com | 3da8b71 | 2005-11-04 12:30:37 -0600 | [diff] [blame] | 125 | /* list of block side commands the scsi error handling sucked up */ |
| 126 | /* and saved for later processing */ |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 127 | #endif |
Mike Miller | 33079b2 | 2005-09-13 01:25:22 -0700 | [diff] [blame] | 128 | unsigned char alive; |
Andrew Patterson | b368c9d | 2009-09-17 13:46:58 -0500 | [diff] [blame] | 129 | struct list_head scan_list; |
| 130 | struct completion scan_wait; |
Andrew Patterson | 7fe0632 | 2009-06-02 14:48:39 +0200 | [diff] [blame] | 131 | struct device dev; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 132 | }; |
| 133 | |
| 134 | /* Defining the diffent access_menthods */ |
| 135 | /* |
| 136 | * Memory mapped FIFO interface (SMART 53xx cards) |
| 137 | */ |
| 138 | #define SA5_DOORBELL 0x20 |
| 139 | #define SA5_REQUEST_PORT_OFFSET 0x40 |
| 140 | #define SA5_REPLY_INTR_MASK_OFFSET 0x34 |
| 141 | #define SA5_REPLY_PORT_OFFSET 0x44 |
| 142 | #define SA5_INTR_STATUS 0x30 |
| 143 | #define SA5_SCRATCHPAD_OFFSET 0xB0 |
| 144 | |
| 145 | #define SA5_CTCFG_OFFSET 0xB4 |
| 146 | #define SA5_CTMEM_OFFSET 0xB8 |
| 147 | |
| 148 | #define SA5_INTR_OFF 0x08 |
| 149 | #define SA5B_INTR_OFF 0x04 |
| 150 | #define SA5_INTR_PENDING 0x08 |
| 151 | #define SA5B_INTR_PENDING 0x04 |
| 152 | #define FIFO_EMPTY 0xffffffff |
| 153 | #define CCISS_FIRMWARE_READY 0xffff0000 /* value in scratchpad register */ |
| 154 | |
| 155 | #define CISS_ERROR_BIT 0x02 |
| 156 | |
| 157 | #define CCISS_INTR_ON 1 |
| 158 | #define CCISS_INTR_OFF 0 |
| 159 | /* |
| 160 | Send the command to the hardware |
| 161 | */ |
| 162 | static void SA5_submit_command( ctlr_info_t *h, CommandList_struct *c) |
| 163 | { |
| 164 | #ifdef CCISS_DEBUG |
| 165 | printk("Sending %x - down to controller\n", c->busaddr ); |
| 166 | #endif /* CCISS_DEBUG */ |
| 167 | writel(c->busaddr, h->vaddr + SA5_REQUEST_PORT_OFFSET); |
| 168 | h->commands_outstanding++; |
| 169 | if ( h->commands_outstanding > h->max_outstanding) |
| 170 | h->max_outstanding = h->commands_outstanding; |
| 171 | } |
| 172 | |
| 173 | /* |
| 174 | * This card is the opposite of the other cards. |
| 175 | * 0 turns interrupts on... |
| 176 | * 0x08 turns them off... |
| 177 | */ |
| 178 | static void SA5_intr_mask(ctlr_info_t *h, unsigned long val) |
| 179 | { |
| 180 | if (val) |
| 181 | { /* Turn interrupts on */ |
| 182 | h->interrupts_enabled = 1; |
| 183 | writel(0, h->vaddr + SA5_REPLY_INTR_MASK_OFFSET); |
| 184 | } else /* Turn them off */ |
| 185 | { |
| 186 | h->interrupts_enabled = 0; |
| 187 | writel( SA5_INTR_OFF, |
| 188 | h->vaddr + SA5_REPLY_INTR_MASK_OFFSET); |
| 189 | } |
| 190 | } |
| 191 | /* |
| 192 | * This card is the opposite of the other cards. |
| 193 | * 0 turns interrupts on... |
| 194 | * 0x04 turns them off... |
| 195 | */ |
| 196 | static void SA5B_intr_mask(ctlr_info_t *h, unsigned long val) |
| 197 | { |
| 198 | if (val) |
| 199 | { /* Turn interrupts on */ |
| 200 | h->interrupts_enabled = 1; |
| 201 | writel(0, h->vaddr + SA5_REPLY_INTR_MASK_OFFSET); |
| 202 | } else /* Turn them off */ |
| 203 | { |
| 204 | h->interrupts_enabled = 0; |
| 205 | writel( SA5B_INTR_OFF, |
| 206 | h->vaddr + SA5_REPLY_INTR_MASK_OFFSET); |
| 207 | } |
| 208 | } |
| 209 | /* |
| 210 | * Returns true if fifo is full. |
| 211 | * |
| 212 | */ |
| 213 | static unsigned long SA5_fifo_full(ctlr_info_t *h) |
| 214 | { |
| 215 | if( h->commands_outstanding >= h->max_commands) |
| 216 | return(1); |
| 217 | else |
| 218 | return(0); |
| 219 | |
| 220 | } |
| 221 | /* |
| 222 | * returns value read from hardware. |
| 223 | * returns FIFO_EMPTY if there is nothing to read |
| 224 | */ |
| 225 | static unsigned long SA5_completed(ctlr_info_t *h) |
| 226 | { |
| 227 | unsigned long register_value |
| 228 | = readl(h->vaddr + SA5_REPLY_PORT_OFFSET); |
| 229 | if(register_value != FIFO_EMPTY) |
| 230 | { |
| 231 | h->commands_outstanding--; |
| 232 | #ifdef CCISS_DEBUG |
| 233 | printk("cciss: Read %lx back from board\n", register_value); |
| 234 | #endif /* CCISS_DEBUG */ |
| 235 | } |
| 236 | #ifdef CCISS_DEBUG |
| 237 | else |
| 238 | { |
| 239 | printk("cciss: FIFO Empty read\n"); |
| 240 | } |
| 241 | #endif |
| 242 | return ( register_value); |
| 243 | |
| 244 | } |
| 245 | /* |
| 246 | * Returns true if an interrupt is pending.. |
| 247 | */ |
| 248 | static unsigned long SA5_intr_pending(ctlr_info_t *h) |
| 249 | { |
| 250 | unsigned long register_value = |
| 251 | readl(h->vaddr + SA5_INTR_STATUS); |
| 252 | #ifdef CCISS_DEBUG |
| 253 | printk("cciss: intr_pending %lx\n", register_value); |
| 254 | #endif /* CCISS_DEBUG */ |
| 255 | if( register_value & SA5_INTR_PENDING) |
| 256 | return 1; |
| 257 | return 0 ; |
| 258 | } |
| 259 | |
| 260 | /* |
| 261 | * Returns true if an interrupt is pending.. |
| 262 | */ |
| 263 | static unsigned long SA5B_intr_pending(ctlr_info_t *h) |
| 264 | { |
| 265 | unsigned long register_value = |
| 266 | readl(h->vaddr + SA5_INTR_STATUS); |
| 267 | #ifdef CCISS_DEBUG |
| 268 | printk("cciss: intr_pending %lx\n", register_value); |
| 269 | #endif /* CCISS_DEBUG */ |
| 270 | if( register_value & SA5B_INTR_PENDING) |
| 271 | return 1; |
| 272 | return 0 ; |
| 273 | } |
| 274 | |
| 275 | |
| 276 | static struct access_method SA5_access = { |
| 277 | SA5_submit_command, |
| 278 | SA5_intr_mask, |
| 279 | SA5_fifo_full, |
| 280 | SA5_intr_pending, |
| 281 | SA5_completed, |
| 282 | }; |
| 283 | |
| 284 | static struct access_method SA5B_access = { |
| 285 | SA5_submit_command, |
| 286 | SA5B_intr_mask, |
| 287 | SA5_fifo_full, |
| 288 | SA5B_intr_pending, |
| 289 | SA5_completed, |
| 290 | }; |
| 291 | |
| 292 | struct board_type { |
| 293 | __u32 board_id; |
| 294 | char *product_name; |
| 295 | struct access_method *access; |
Mike Miller | f880632 | 2006-12-06 20:35:01 -0800 | [diff] [blame] | 296 | int nr_cmds; /* Max cmds this kind of ctlr can handle. */ |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 297 | }; |
| 298 | |
Mike Miller | ad2b931 | 2005-07-28 01:07:31 -0700 | [diff] [blame] | 299 | #define CCISS_LOCK(i) (&hba[i]->lock) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 300 | |
| 301 | #endif /* CCISS_H */ |
| 302 | |