Guennadi Liakhovetski | 0d34e91 | 2010-01-27 18:56:23 +0100 | [diff] [blame] | 1 | /* |
| 2 | * wm8978.c -- WM8978 ALSA SoC Audio Codec driver |
| 3 | * |
| 4 | * Copyright (C) 2009-2010 Guennadi Liakhovetski <g.liakhovetski@gmx.de> |
| 5 | * Copyright (C) 2007 Carlos Munoz <carlos@kenati.com> |
| 6 | * Copyright 2006-2009 Wolfson Microelectronics PLC. |
| 7 | * Based on wm8974 and wm8990 by Liam Girdwood <lrg@slimlogic.co.uk> |
| 8 | * |
| 9 | * This program is free software; you can redistribute it and/or modify |
| 10 | * it under the terms of the GNU General Public License version 2 as |
| 11 | * published by the Free Software Foundation. |
| 12 | */ |
| 13 | |
| 14 | #include <linux/module.h> |
| 15 | #include <linux/moduleparam.h> |
| 16 | #include <linux/kernel.h> |
| 17 | #include <linux/init.h> |
| 18 | #include <linux/delay.h> |
| 19 | #include <linux/pm.h> |
| 20 | #include <linux/i2c.h> |
| 21 | #include <linux/platform_device.h> |
| 22 | #include <sound/core.h> |
| 23 | #include <sound/pcm.h> |
| 24 | #include <sound/pcm_params.h> |
| 25 | #include <sound/soc.h> |
| 26 | #include <sound/soc-dapm.h> |
| 27 | #include <sound/initval.h> |
| 28 | #include <sound/tlv.h> |
| 29 | #include <asm/div64.h> |
| 30 | |
| 31 | #include "wm8978.h" |
| 32 | |
| 33 | static struct snd_soc_codec *wm8978_codec; |
| 34 | |
| 35 | /* wm8978 register cache. Note that register 0 is not included in the cache. */ |
| 36 | static const u16 wm8978_reg[WM8978_CACHEREGNUM] = { |
| 37 | 0x0000, 0x0000, 0x0000, 0x0000, /* 0x00...0x03 */ |
| 38 | 0x0050, 0x0000, 0x0140, 0x0000, /* 0x04...0x07 */ |
| 39 | 0x0000, 0x0000, 0x0000, 0x00ff, /* 0x08...0x0b */ |
| 40 | 0x00ff, 0x0000, 0x0100, 0x00ff, /* 0x0c...0x0f */ |
| 41 | 0x00ff, 0x0000, 0x012c, 0x002c, /* 0x10...0x13 */ |
| 42 | 0x002c, 0x002c, 0x002c, 0x0000, /* 0x14...0x17 */ |
| 43 | 0x0032, 0x0000, 0x0000, 0x0000, /* 0x18...0x1b */ |
| 44 | 0x0000, 0x0000, 0x0000, 0x0000, /* 0x1c...0x1f */ |
| 45 | 0x0038, 0x000b, 0x0032, 0x0000, /* 0x20...0x23 */ |
| 46 | 0x0008, 0x000c, 0x0093, 0x00e9, /* 0x24...0x27 */ |
| 47 | 0x0000, 0x0000, 0x0000, 0x0000, /* 0x28...0x2b */ |
| 48 | 0x0033, 0x0010, 0x0010, 0x0100, /* 0x2c...0x2f */ |
| 49 | 0x0100, 0x0002, 0x0001, 0x0001, /* 0x30...0x33 */ |
| 50 | 0x0039, 0x0039, 0x0039, 0x0039, /* 0x34...0x37 */ |
| 51 | 0x0001, 0x0001, /* 0x38...0x3b */ |
| 52 | }; |
| 53 | |
| 54 | /* codec private data */ |
| 55 | struct wm8978_priv { |
| 56 | struct snd_soc_codec codec; |
| 57 | unsigned int f_pllout; |
| 58 | unsigned int f_mclk; |
| 59 | unsigned int f_256fs; |
| 60 | unsigned int f_opclk; |
| 61 | enum wm8978_sysclk_src sysclk; |
| 62 | u16 reg_cache[WM8978_CACHEREGNUM]; |
| 63 | }; |
| 64 | |
| 65 | static const char *wm8978_companding[] = {"Off", "NC", "u-law", "A-law"}; |
| 66 | static const char *wm8978_eqmode[] = {"Capture", "Playback"}; |
| 67 | static const char *wm8978_bw[] = {"Narrow", "Wide"}; |
| 68 | static const char *wm8978_eq1[] = {"80Hz", "105Hz", "135Hz", "175Hz"}; |
| 69 | static const char *wm8978_eq2[] = {"230Hz", "300Hz", "385Hz", "500Hz"}; |
| 70 | static const char *wm8978_eq3[] = {"650Hz", "850Hz", "1.1kHz", "1.4kHz"}; |
| 71 | static const char *wm8978_eq4[] = {"1.8kHz", "2.4kHz", "3.2kHz", "4.1kHz"}; |
| 72 | static const char *wm8978_eq5[] = {"5.3kHz", "6.9kHz", "9kHz", "11.7kHz"}; |
| 73 | static const char *wm8978_alc3[] = {"ALC", "Limiter"}; |
| 74 | static const char *wm8978_alc1[] = {"Off", "Right", "Left", "Both"}; |
| 75 | |
| 76 | static const SOC_ENUM_SINGLE_DECL(adc_compand, WM8978_COMPANDING_CONTROL, 1, |
| 77 | wm8978_companding); |
| 78 | static const SOC_ENUM_SINGLE_DECL(dac_compand, WM8978_COMPANDING_CONTROL, 3, |
| 79 | wm8978_companding); |
| 80 | static const SOC_ENUM_SINGLE_DECL(eqmode, WM8978_EQ1, 8, wm8978_eqmode); |
| 81 | static const SOC_ENUM_SINGLE_DECL(eq1, WM8978_EQ1, 5, wm8978_eq1); |
| 82 | static const SOC_ENUM_SINGLE_DECL(eq2bw, WM8978_EQ2, 8, wm8978_bw); |
| 83 | static const SOC_ENUM_SINGLE_DECL(eq2, WM8978_EQ2, 5, wm8978_eq2); |
| 84 | static const SOC_ENUM_SINGLE_DECL(eq3bw, WM8978_EQ3, 8, wm8978_bw); |
| 85 | static const SOC_ENUM_SINGLE_DECL(eq3, WM8978_EQ3, 5, wm8978_eq3); |
| 86 | static const SOC_ENUM_SINGLE_DECL(eq4bw, WM8978_EQ4, 8, wm8978_bw); |
| 87 | static const SOC_ENUM_SINGLE_DECL(eq4, WM8978_EQ4, 5, wm8978_eq4); |
| 88 | static const SOC_ENUM_SINGLE_DECL(eq5, WM8978_EQ5, 5, wm8978_eq5); |
| 89 | static const SOC_ENUM_SINGLE_DECL(alc3, WM8978_ALC_CONTROL_3, 8, wm8978_alc3); |
| 90 | static const SOC_ENUM_SINGLE_DECL(alc1, WM8978_ALC_CONTROL_1, 7, wm8978_alc1); |
| 91 | |
| 92 | static const DECLARE_TLV_DB_SCALE(digital_tlv, -12750, 50, 1); |
| 93 | static const DECLARE_TLV_DB_SCALE(eq_tlv, -1200, 100, 0); |
| 94 | static const DECLARE_TLV_DB_SCALE(inpga_tlv, -1200, 75, 0); |
| 95 | static const DECLARE_TLV_DB_SCALE(spk_tlv, -5700, 100, 0); |
| 96 | static const DECLARE_TLV_DB_SCALE(boost_tlv, -1500, 300, 1); |
| 97 | |
| 98 | static const struct snd_kcontrol_new wm8978_snd_controls[] = { |
| 99 | |
| 100 | SOC_SINGLE("Digital Loopback Switch", |
| 101 | WM8978_COMPANDING_CONTROL, 0, 1, 0), |
| 102 | |
| 103 | SOC_ENUM("ADC Companding", adc_compand), |
| 104 | SOC_ENUM("DAC Companding", dac_compand), |
| 105 | |
| 106 | SOC_DOUBLE("DAC Inversion Switch", WM8978_DAC_CONTROL, 0, 1, 1, 0), |
| 107 | |
| 108 | SOC_DOUBLE_R_TLV("PCM Volume", |
| 109 | WM8978_LEFT_DAC_DIGITAL_VOLUME, WM8978_RIGHT_DAC_DIGITAL_VOLUME, |
| 110 | 0, 255, 0, digital_tlv), |
| 111 | |
| 112 | SOC_SINGLE("High Pass Filter Switch", WM8978_ADC_CONTROL, 8, 1, 0), |
| 113 | SOC_SINGLE("High Pass Cut Off", WM8978_ADC_CONTROL, 4, 7, 0), |
| 114 | SOC_DOUBLE("ADC Inversion Switch", WM8978_ADC_CONTROL, 0, 1, 1, 0), |
| 115 | |
| 116 | SOC_DOUBLE_R_TLV("ADC Volume", |
| 117 | WM8978_LEFT_ADC_DIGITAL_VOLUME, WM8978_RIGHT_ADC_DIGITAL_VOLUME, |
| 118 | 0, 255, 0, digital_tlv), |
| 119 | |
| 120 | SOC_ENUM("Equaliser Function", eqmode), |
| 121 | SOC_ENUM("EQ1 Cut Off", eq1), |
| 122 | SOC_SINGLE_TLV("EQ1 Volume", WM8978_EQ1, 0, 24, 1, eq_tlv), |
| 123 | |
| 124 | SOC_ENUM("Equaliser EQ2 Bandwith", eq2bw), |
| 125 | SOC_ENUM("EQ2 Cut Off", eq2), |
| 126 | SOC_SINGLE_TLV("EQ2 Volume", WM8978_EQ2, 0, 24, 1, eq_tlv), |
| 127 | |
| 128 | SOC_ENUM("Equaliser EQ3 Bandwith", eq3bw), |
| 129 | SOC_ENUM("EQ3 Cut Off", eq3), |
| 130 | SOC_SINGLE_TLV("EQ3 Volume", WM8978_EQ3, 0, 24, 1, eq_tlv), |
| 131 | |
| 132 | SOC_ENUM("Equaliser EQ4 Bandwith", eq4bw), |
| 133 | SOC_ENUM("EQ4 Cut Off", eq4), |
| 134 | SOC_SINGLE_TLV("EQ4 Volume", WM8978_EQ4, 0, 24, 1, eq_tlv), |
| 135 | |
| 136 | SOC_ENUM("EQ5 Cut Off", eq5), |
| 137 | SOC_SINGLE_TLV("EQ5 Volume", WM8978_EQ5, 0, 24, 1, eq_tlv), |
| 138 | |
| 139 | SOC_SINGLE("DAC Playback Limiter Switch", |
| 140 | WM8978_DAC_LIMITER_1, 8, 1, 0), |
| 141 | SOC_SINGLE("DAC Playback Limiter Decay", |
| 142 | WM8978_DAC_LIMITER_1, 4, 15, 0), |
| 143 | SOC_SINGLE("DAC Playback Limiter Attack", |
| 144 | WM8978_DAC_LIMITER_1, 0, 15, 0), |
| 145 | |
| 146 | SOC_SINGLE("DAC Playback Limiter Threshold", |
| 147 | WM8978_DAC_LIMITER_2, 4, 7, 0), |
| 148 | SOC_SINGLE("DAC Playback Limiter Boost", |
| 149 | WM8978_DAC_LIMITER_2, 0, 15, 0), |
| 150 | |
| 151 | SOC_ENUM("ALC Enable Switch", alc1), |
| 152 | SOC_SINGLE("ALC Capture Min Gain", WM8978_ALC_CONTROL_1, 0, 7, 0), |
| 153 | SOC_SINGLE("ALC Capture Max Gain", WM8978_ALC_CONTROL_1, 3, 7, 0), |
| 154 | |
| 155 | SOC_SINGLE("ALC Capture Hold", WM8978_ALC_CONTROL_2, 4, 7, 0), |
| 156 | SOC_SINGLE("ALC Capture Target", WM8978_ALC_CONTROL_2, 0, 15, 0), |
| 157 | |
| 158 | SOC_ENUM("ALC Capture Mode", alc3), |
| 159 | SOC_SINGLE("ALC Capture Decay", WM8978_ALC_CONTROL_3, 4, 15, 0), |
| 160 | SOC_SINGLE("ALC Capture Attack", WM8978_ALC_CONTROL_3, 0, 15, 0), |
| 161 | |
| 162 | SOC_SINGLE("ALC Capture Noise Gate Switch", WM8978_NOISE_GATE, 3, 1, 0), |
| 163 | SOC_SINGLE("ALC Capture Noise Gate Threshold", |
| 164 | WM8978_NOISE_GATE, 0, 7, 0), |
| 165 | |
| 166 | SOC_DOUBLE_R("Capture PGA ZC Switch", |
| 167 | WM8978_LEFT_INP_PGA_CONTROL, WM8978_RIGHT_INP_PGA_CONTROL, |
| 168 | 7, 1, 0), |
| 169 | |
| 170 | /* OUT1 - Headphones */ |
| 171 | SOC_DOUBLE_R("Headphone Playback ZC Switch", |
| 172 | WM8978_LOUT1_HP_CONTROL, WM8978_ROUT1_HP_CONTROL, 7, 1, 0), |
| 173 | |
| 174 | SOC_DOUBLE_R_TLV("Headphone Playback Volume", |
| 175 | WM8978_LOUT1_HP_CONTROL, WM8978_ROUT1_HP_CONTROL, |
| 176 | 0, 63, 0, spk_tlv), |
| 177 | |
| 178 | /* OUT2 - Speakers */ |
| 179 | SOC_DOUBLE_R("Speaker Playback ZC Switch", |
| 180 | WM8978_LOUT2_SPK_CONTROL, WM8978_ROUT2_SPK_CONTROL, 7, 1, 0), |
| 181 | |
| 182 | SOC_DOUBLE_R_TLV("Speaker Playback Volume", |
| 183 | WM8978_LOUT2_SPK_CONTROL, WM8978_ROUT2_SPK_CONTROL, |
| 184 | 0, 63, 0, spk_tlv), |
| 185 | |
| 186 | /* OUT3/4 - Line Output */ |
| 187 | SOC_DOUBLE_R("Line Playback Switch", |
| 188 | WM8978_OUT3_MIXER_CONTROL, WM8978_OUT4_MIXER_CONTROL, 6, 1, 1), |
| 189 | |
| 190 | /* Mixer #3: Boost (Input) mixer */ |
| 191 | SOC_DOUBLE_R("PGA Boost (+20dB)", |
| 192 | WM8978_LEFT_ADC_BOOST_CONTROL, WM8978_RIGHT_ADC_BOOST_CONTROL, |
| 193 | 8, 1, 0), |
| 194 | SOC_DOUBLE_R_TLV("L2/R2 Boost Volume", |
| 195 | WM8978_LEFT_ADC_BOOST_CONTROL, WM8978_RIGHT_ADC_BOOST_CONTROL, |
| 196 | 4, 7, 0, boost_tlv), |
| 197 | SOC_DOUBLE_R_TLV("Aux Boost Volume", |
| 198 | WM8978_LEFT_ADC_BOOST_CONTROL, WM8978_RIGHT_ADC_BOOST_CONTROL, |
| 199 | 0, 7, 0, boost_tlv), |
| 200 | |
| 201 | /* Input PGA volume */ |
| 202 | SOC_DOUBLE_R_TLV("Input PGA Volume", |
| 203 | WM8978_LEFT_INP_PGA_CONTROL, WM8978_RIGHT_INP_PGA_CONTROL, |
| 204 | 0, 63, 0, inpga_tlv), |
| 205 | |
| 206 | /* Headphone */ |
| 207 | SOC_DOUBLE_R("Headphone Switch", |
| 208 | WM8978_LOUT1_HP_CONTROL, WM8978_ROUT1_HP_CONTROL, 6, 1, 1), |
| 209 | |
| 210 | /* Speaker */ |
| 211 | SOC_DOUBLE_R("Speaker Switch", |
| 212 | WM8978_LOUT2_SPK_CONTROL, WM8978_ROUT2_SPK_CONTROL, 6, 1, 1), |
Guennadi Liakhovetski | b2c3e92 | 2010-01-29 15:31:06 +0100 | [diff] [blame^] | 213 | |
| 214 | /* DAC / ADC oversampling */ |
| 215 | SOC_SINGLE("DAC 128x Oversampling Switch", WM8978_DAC_CONTROL, 8, 1, 0), |
| 216 | SOC_SINGLE("ADC 128x Oversampling Switch", WM8978_ADC_CONTROL, 8, 1, 0), |
Guennadi Liakhovetski | 0d34e91 | 2010-01-27 18:56:23 +0100 | [diff] [blame] | 217 | }; |
| 218 | |
| 219 | /* Mixer #1: Output (OUT1, OUT2) Mixer: mix AUX, Input mixer output and DAC */ |
| 220 | static const struct snd_kcontrol_new wm8978_left_out_mixer[] = { |
| 221 | SOC_DAPM_SINGLE("Line Bypass Switch", WM8978_LEFT_MIXER_CONTROL, 1, 1, 0), |
| 222 | SOC_DAPM_SINGLE("Aux Playback Switch", WM8978_LEFT_MIXER_CONTROL, 5, 1, 0), |
| 223 | SOC_DAPM_SINGLE("PCM Playback Switch", WM8978_LEFT_MIXER_CONTROL, 0, 1, 0), |
| 224 | }; |
| 225 | |
| 226 | static const struct snd_kcontrol_new wm8978_right_out_mixer[] = { |
| 227 | SOC_DAPM_SINGLE("Line Bypass Switch", WM8978_RIGHT_MIXER_CONTROL, 1, 1, 0), |
| 228 | SOC_DAPM_SINGLE("Aux Playback Switch", WM8978_RIGHT_MIXER_CONTROL, 5, 1, 0), |
| 229 | SOC_DAPM_SINGLE("PCM Playback Switch", WM8978_RIGHT_MIXER_CONTROL, 0, 1, 0), |
| 230 | }; |
| 231 | |
| 232 | /* OUT3/OUT4 Mixer not implemented */ |
| 233 | |
| 234 | /* Mixer #2: Input PGA Mute */ |
| 235 | static const struct snd_kcontrol_new wm8978_left_input_mixer[] = { |
| 236 | SOC_DAPM_SINGLE("L2 Switch", WM8978_INPUT_CONTROL, 2, 1, 0), |
| 237 | SOC_DAPM_SINGLE("MicN Switch", WM8978_INPUT_CONTROL, 1, 1, 0), |
| 238 | SOC_DAPM_SINGLE("MicP Switch", WM8978_INPUT_CONTROL, 0, 1, 0), |
| 239 | }; |
| 240 | static const struct snd_kcontrol_new wm8978_right_input_mixer[] = { |
| 241 | SOC_DAPM_SINGLE("R2 Switch", WM8978_INPUT_CONTROL, 6, 1, 0), |
| 242 | SOC_DAPM_SINGLE("MicN Switch", WM8978_INPUT_CONTROL, 5, 1, 0), |
| 243 | SOC_DAPM_SINGLE("MicP Switch", WM8978_INPUT_CONTROL, 4, 1, 0), |
| 244 | }; |
| 245 | |
| 246 | static const struct snd_soc_dapm_widget wm8978_dapm_widgets[] = { |
| 247 | SND_SOC_DAPM_DAC("Left DAC", "Left HiFi Playback", |
| 248 | WM8978_POWER_MANAGEMENT_3, 0, 0), |
| 249 | SND_SOC_DAPM_DAC("Right DAC", "Right HiFi Playback", |
| 250 | WM8978_POWER_MANAGEMENT_3, 1, 0), |
| 251 | SND_SOC_DAPM_ADC("Left ADC", "Left HiFi Capture", |
| 252 | WM8978_POWER_MANAGEMENT_2, 0, 0), |
| 253 | SND_SOC_DAPM_ADC("Right ADC", "Right HiFi Capture", |
| 254 | WM8978_POWER_MANAGEMENT_2, 1, 0), |
| 255 | |
| 256 | /* Mixer #1: OUT1,2 */ |
| 257 | SOC_MIXER_ARRAY("Left Output Mixer", WM8978_POWER_MANAGEMENT_3, |
| 258 | 2, 0, wm8978_left_out_mixer), |
| 259 | SOC_MIXER_ARRAY("Right Output Mixer", WM8978_POWER_MANAGEMENT_3, |
| 260 | 3, 0, wm8978_right_out_mixer), |
| 261 | |
| 262 | SOC_MIXER_ARRAY("Left Input Mixer", WM8978_POWER_MANAGEMENT_2, |
| 263 | 2, 0, wm8978_left_input_mixer), |
| 264 | SOC_MIXER_ARRAY("Right Input Mixer", WM8978_POWER_MANAGEMENT_2, |
| 265 | 3, 0, wm8978_right_input_mixer), |
| 266 | |
| 267 | SND_SOC_DAPM_PGA("Left Boost Mixer", WM8978_POWER_MANAGEMENT_2, |
| 268 | 4, 0, NULL, 0), |
| 269 | SND_SOC_DAPM_PGA("Right Boost Mixer", WM8978_POWER_MANAGEMENT_2, |
| 270 | 5, 0, NULL, 0), |
| 271 | |
| 272 | SND_SOC_DAPM_PGA("Left Capture PGA", WM8978_LEFT_INP_PGA_CONTROL, |
| 273 | 6, 1, NULL, 0), |
| 274 | SND_SOC_DAPM_PGA("Right Capture PGA", WM8978_RIGHT_INP_PGA_CONTROL, |
| 275 | 6, 1, NULL, 0), |
| 276 | |
| 277 | SND_SOC_DAPM_PGA("Left Headphone Out", WM8978_POWER_MANAGEMENT_2, |
| 278 | 7, 0, NULL, 0), |
| 279 | SND_SOC_DAPM_PGA("Right Headphone Out", WM8978_POWER_MANAGEMENT_2, |
| 280 | 8, 0, NULL, 0), |
| 281 | |
| 282 | SND_SOC_DAPM_PGA("Left Speaker Out", WM8978_POWER_MANAGEMENT_3, |
| 283 | 6, 0, NULL, 0), |
| 284 | SND_SOC_DAPM_PGA("Right Speaker Out", WM8978_POWER_MANAGEMENT_3, |
| 285 | 5, 0, NULL, 0), |
| 286 | |
| 287 | SND_SOC_DAPM_MIXER("OUT4 VMID", WM8978_POWER_MANAGEMENT_3, |
| 288 | 8, 0, NULL, 0), |
| 289 | |
| 290 | SND_SOC_DAPM_MICBIAS("Mic Bias", WM8978_POWER_MANAGEMENT_1, 4, 0), |
| 291 | |
| 292 | SND_SOC_DAPM_INPUT("LMICN"), |
| 293 | SND_SOC_DAPM_INPUT("LMICP"), |
| 294 | SND_SOC_DAPM_INPUT("RMICN"), |
| 295 | SND_SOC_DAPM_INPUT("RMICP"), |
| 296 | SND_SOC_DAPM_INPUT("LAUX"), |
| 297 | SND_SOC_DAPM_INPUT("RAUX"), |
| 298 | SND_SOC_DAPM_INPUT("L2"), |
| 299 | SND_SOC_DAPM_INPUT("R2"), |
| 300 | SND_SOC_DAPM_OUTPUT("LHP"), |
| 301 | SND_SOC_DAPM_OUTPUT("RHP"), |
| 302 | SND_SOC_DAPM_OUTPUT("LSPK"), |
| 303 | SND_SOC_DAPM_OUTPUT("RSPK"), |
| 304 | }; |
| 305 | |
| 306 | static const struct snd_soc_dapm_route audio_map[] = { |
| 307 | /* Output mixer */ |
| 308 | {"Right Output Mixer", "PCM Playback Switch", "Right DAC"}, |
| 309 | {"Right Output Mixer", "Aux Playback Switch", "RAUX"}, |
| 310 | {"Right Output Mixer", "Line Bypass Switch", "Right Boost Mixer"}, |
| 311 | |
| 312 | {"Left Output Mixer", "PCM Playback Switch", "Left DAC"}, |
| 313 | {"Left Output Mixer", "Aux Playback Switch", "LAUX"}, |
| 314 | {"Left Output Mixer", "Line Bypass Switch", "Left Boost Mixer"}, |
| 315 | |
| 316 | /* Outputs */ |
| 317 | {"Right Headphone Out", NULL, "Right Output Mixer"}, |
| 318 | {"RHP", NULL, "Right Headphone Out"}, |
| 319 | |
| 320 | {"Left Headphone Out", NULL, "Left Output Mixer"}, |
| 321 | {"LHP", NULL, "Left Headphone Out"}, |
| 322 | |
| 323 | {"Right Speaker Out", NULL, "Right Output Mixer"}, |
| 324 | {"RSPK", NULL, "Right Speaker Out"}, |
| 325 | |
| 326 | {"Left Speaker Out", NULL, "Left Output Mixer"}, |
| 327 | {"LSPK", NULL, "Left Speaker Out"}, |
| 328 | |
| 329 | /* Boost Mixer */ |
| 330 | {"Right ADC", NULL, "Right Boost Mixer"}, |
| 331 | |
| 332 | {"Right Boost Mixer", NULL, "RAUX"}, |
| 333 | {"Right Boost Mixer", NULL, "Right Capture PGA"}, |
| 334 | {"Right Boost Mixer", NULL, "R2"}, |
| 335 | |
| 336 | {"Left ADC", NULL, "Left Boost Mixer"}, |
| 337 | |
| 338 | {"Left Boost Mixer", NULL, "LAUX"}, |
| 339 | {"Left Boost Mixer", NULL, "Left Capture PGA"}, |
| 340 | {"Left Boost Mixer", NULL, "L2"}, |
| 341 | |
| 342 | /* Input PGA */ |
| 343 | {"Right Capture PGA", NULL, "Right Input Mixer"}, |
| 344 | {"Left Capture PGA", NULL, "Left Input Mixer"}, |
| 345 | |
| 346 | {"Right Input Mixer", "R2 Switch", "R2"}, |
| 347 | {"Right Input Mixer", "MicN Switch", "RMICN"}, |
| 348 | {"Right Input Mixer", "MicP Switch", "RMICP"}, |
| 349 | |
| 350 | {"Left Input Mixer", "L2 Switch", "L2"}, |
| 351 | {"Left Input Mixer", "MicN Switch", "LMICN"}, |
| 352 | {"Left Input Mixer", "MicP Switch", "LMICP"}, |
| 353 | }; |
| 354 | |
| 355 | static int wm8978_add_widgets(struct snd_soc_codec *codec) |
| 356 | { |
| 357 | snd_soc_dapm_new_controls(codec, wm8978_dapm_widgets, |
| 358 | ARRAY_SIZE(wm8978_dapm_widgets)); |
| 359 | |
| 360 | /* set up the WM8978 audio map */ |
| 361 | snd_soc_dapm_add_routes(codec, audio_map, ARRAY_SIZE(audio_map)); |
| 362 | |
| 363 | return 0; |
| 364 | } |
| 365 | |
| 366 | /* PLL divisors */ |
| 367 | struct wm8978_pll_div { |
| 368 | u32 k; |
| 369 | u8 n; |
| 370 | u8 div2; |
| 371 | }; |
| 372 | |
| 373 | #define FIXED_PLL_SIZE (1 << 24) |
| 374 | |
| 375 | static void pll_factors(struct wm8978_pll_div *pll_div, unsigned int target, |
| 376 | unsigned int source) |
| 377 | { |
| 378 | u64 k_part; |
| 379 | unsigned int k, n_div, n_mod; |
| 380 | |
| 381 | n_div = target / source; |
| 382 | if (n_div < 6) { |
| 383 | source >>= 1; |
| 384 | pll_div->div2 = 1; |
| 385 | n_div = target / source; |
| 386 | } else { |
| 387 | pll_div->div2 = 0; |
| 388 | } |
| 389 | |
| 390 | if (n_div < 6 || n_div > 12) |
| 391 | dev_warn(wm8978_codec->dev, |
| 392 | "WM8978 N value exceeds recommended range! N = %u\n", |
| 393 | n_div); |
| 394 | |
| 395 | pll_div->n = n_div; |
| 396 | n_mod = target - source * n_div; |
| 397 | k_part = FIXED_PLL_SIZE * (long long)n_mod + source / 2; |
| 398 | |
| 399 | do_div(k_part, source); |
| 400 | |
| 401 | k = k_part & 0xFFFFFFFF; |
| 402 | |
| 403 | pll_div->k = k; |
| 404 | } |
| 405 | /* |
| 406 | * Calculate internal frequencies and dividers, according to Figure 40 |
| 407 | * "PLL and Clock Select Circuit" in WM8978 datasheet Rev. 2.6 |
| 408 | */ |
| 409 | static int wm8978_configure_pll(struct snd_soc_codec *codec) |
| 410 | { |
| 411 | struct wm8978_priv *wm8978 = codec->private_data; |
| 412 | struct wm8978_pll_div pll_div; |
| 413 | unsigned int f_opclk = wm8978->f_opclk, f_mclk = wm8978->f_mclk, |
| 414 | f_256fs = wm8978->f_256fs; |
| 415 | unsigned int f2, opclk_div; |
| 416 | |
| 417 | if (!f_mclk) |
| 418 | return -EINVAL; |
| 419 | |
| 420 | if (f_opclk) { |
| 421 | /* |
| 422 | * The user needs OPCLK. Choose OPCLKDIV to put |
| 423 | * 6 <= R = f2 / f1 < 13, 1 <= OPCLKDIV <= 4. |
| 424 | * f_opclk = f_mclk * prescale * R / 4 / OPCLKDIV, where |
| 425 | * prescale = 1, or prescale = 2. Prescale is calculated inside |
| 426 | * pll_factors(). We have to select f_PLLOUT, such that |
| 427 | * f_mclk * 3 / 4 <= f_PLLOUT < f_mclk * 13 / 4. Must be |
| 428 | * f_mclk * 3 / 16 <= f_opclk < f_mclk * 13 / 4. |
| 429 | */ |
| 430 | if (16 * f_opclk < 3 * f_mclk || 4 * f_opclk >= 13 * f_mclk) |
| 431 | return -EINVAL; |
| 432 | |
| 433 | if (4 * f_opclk < 3 * f_mclk) |
| 434 | /* Have to use OPCLKDIV */ |
| 435 | opclk_div = (3 * f_mclk / 4 + f_opclk - 1) / f_opclk; |
| 436 | else |
| 437 | opclk_div = 1; |
| 438 | |
| 439 | dev_dbg(codec->dev, "%s: OPCLKDIV=%d\n", __func__, opclk_div); |
| 440 | |
| 441 | snd_soc_update_bits(codec, WM8978_GPIO_CONTROL, 0x30, |
| 442 | (opclk_div - 1) << 4); |
| 443 | |
| 444 | wm8978->f_pllout = f_opclk * opclk_div; |
| 445 | } else if (f_256fs) { |
| 446 | /* |
| 447 | * Not using OPCLK, choose R: |
| 448 | * 6 <= R = f2 / f1 < 13, to put 1 <= MCLKDIV <= 12. |
| 449 | * f_256fs = f_mclk * prescale * R / 4 / MCLKDIV, where |
| 450 | * prescale = 1, or prescale = 2. Prescale is calculated inside |
| 451 | * pll_factors(). We have to select f_PLLOUT, such that |
| 452 | * f_mclk * 3 / 4 <= f_PLLOUT < f_mclk * 13 / 4. Must be |
| 453 | * f_mclk * 3 / 48 <= f_256fs < f_mclk * 13 / 4. This means MCLK |
| 454 | * must be 3.781MHz <= f_MCLK <= 32.768MHz |
| 455 | */ |
| 456 | if (48 * f_256fs < 3 * f_mclk || 4 * f_256fs >= 13 * f_mclk) |
| 457 | return -EINVAL; |
| 458 | |
| 459 | /* |
| 460 | * MCLKDIV will be selected in .hw_params(), just choose a |
| 461 | * suitable f_PLLOUT |
| 462 | */ |
| 463 | if (4 * f_256fs < 3 * f_mclk) |
| 464 | /* Will have to use MCLKDIV */ |
| 465 | wm8978->f_pllout = wm8978->f_mclk * 3 / 4; |
| 466 | else |
| 467 | wm8978->f_pllout = f_256fs; |
| 468 | |
| 469 | /* GPIO1 into default mode as input - before configuring PLL */ |
| 470 | snd_soc_update_bits(codec, WM8978_GPIO_CONTROL, 7, 0); |
| 471 | } else { |
| 472 | return -EINVAL; |
| 473 | } |
| 474 | |
| 475 | f2 = wm8978->f_pllout * 4; |
| 476 | |
| 477 | dev_dbg(codec->dev, "%s: f_MCLK=%uHz, f_PLLOUT=%uHz\n", __func__, |
| 478 | wm8978->f_mclk, wm8978->f_pllout); |
| 479 | |
| 480 | pll_factors(&pll_div, f2, wm8978->f_mclk); |
| 481 | |
| 482 | dev_dbg(codec->dev, "%s: calculated PLL N=0x%x, K=0x%x, div2=%d\n", |
| 483 | __func__, pll_div.n, pll_div.k, pll_div.div2); |
| 484 | |
| 485 | /* Turn PLL off for configuration... */ |
| 486 | snd_soc_update_bits(codec, WM8978_POWER_MANAGEMENT_1, 0x20, 0); |
| 487 | |
| 488 | snd_soc_write(codec, WM8978_PLL_N, (pll_div.div2 << 4) | pll_div.n); |
| 489 | snd_soc_write(codec, WM8978_PLL_K1, pll_div.k >> 18); |
| 490 | snd_soc_write(codec, WM8978_PLL_K2, (pll_div.k >> 9) & 0x1ff); |
| 491 | snd_soc_write(codec, WM8978_PLL_K3, pll_div.k & 0x1ff); |
| 492 | |
| 493 | /* ...and on again */ |
| 494 | snd_soc_update_bits(codec, WM8978_POWER_MANAGEMENT_1, 0x20, 0x20); |
| 495 | |
| 496 | if (f_opclk) |
| 497 | /* Output PLL (OPCLK) to GPIO1 */ |
| 498 | snd_soc_update_bits(codec, WM8978_GPIO_CONTROL, 7, 4); |
| 499 | |
| 500 | return 0; |
| 501 | } |
| 502 | |
| 503 | /* |
| 504 | * Configure WM8978 clock dividers. |
| 505 | */ |
| 506 | static int wm8978_set_dai_clkdiv(struct snd_soc_dai *codec_dai, |
| 507 | int div_id, int div) |
| 508 | { |
| 509 | struct snd_soc_codec *codec = codec_dai->codec; |
| 510 | struct wm8978_priv *wm8978 = codec->private_data; |
| 511 | int ret = 0; |
| 512 | |
| 513 | switch (div_id) { |
| 514 | case WM8978_OPCLKRATE: |
| 515 | wm8978->f_opclk = div; |
| 516 | |
| 517 | if (wm8978->f_mclk) |
| 518 | ret = wm8978_configure_pll(codec); |
| 519 | break; |
Guennadi Liakhovetski | 0d34e91 | 2010-01-27 18:56:23 +0100 | [diff] [blame] | 520 | case WM8978_BCLKDIV: |
| 521 | if (div & ~0x1c) |
| 522 | return -EINVAL; |
| 523 | snd_soc_update_bits(codec, WM8978_CLOCKING, 0x1c, div); |
| 524 | break; |
| 525 | default: |
| 526 | return -EINVAL; |
| 527 | } |
| 528 | |
| 529 | dev_dbg(codec->dev, "%s: ID %d, value %u\n", __func__, div_id, div); |
| 530 | |
| 531 | return ret; |
| 532 | } |
| 533 | |
| 534 | /* |
| 535 | * @freq: when .set_pll() us not used, freq is codec MCLK input frequency |
| 536 | */ |
| 537 | static int wm8978_set_dai_sysclk(struct snd_soc_dai *codec_dai, int clk_id, |
| 538 | unsigned int freq, int dir) |
| 539 | { |
| 540 | struct snd_soc_codec *codec = codec_dai->codec; |
| 541 | struct wm8978_priv *wm8978 = codec->private_data; |
| 542 | int ret = 0; |
| 543 | |
| 544 | dev_dbg(codec->dev, "%s: ID %d, freq %u\n", __func__, clk_id, freq); |
| 545 | |
| 546 | if (freq) { |
| 547 | wm8978->f_mclk = freq; |
| 548 | |
| 549 | /* Even if MCLK is used for system clock, might have to drive OPCLK */ |
| 550 | if (wm8978->f_opclk) |
| 551 | ret = wm8978_configure_pll(codec); |
| 552 | |
| 553 | /* Our sysclk is fixed to 256 * fs, will configure in .hw_params() */ |
| 554 | |
| 555 | if (!ret) |
| 556 | wm8978->sysclk = clk_id; |
| 557 | } |
| 558 | |
| 559 | if (wm8978->sysclk == WM8978_PLL && (!freq || clk_id == WM8978_MCLK)) { |
| 560 | /* Clock CODEC directly from MCLK */ |
| 561 | snd_soc_update_bits(codec, WM8978_CLOCKING, 0x100, 0); |
| 562 | |
| 563 | /* GPIO1 into default mode as input - before configuring PLL */ |
| 564 | snd_soc_update_bits(codec, WM8978_GPIO_CONTROL, 7, 0); |
| 565 | |
| 566 | /* Turn off PLL */ |
| 567 | snd_soc_update_bits(codec, WM8978_POWER_MANAGEMENT_1, 0x20, 0); |
| 568 | wm8978->sysclk = WM8978_MCLK; |
| 569 | wm8978->f_pllout = 0; |
| 570 | wm8978->f_opclk = 0; |
| 571 | } |
| 572 | |
| 573 | return ret; |
| 574 | } |
| 575 | |
| 576 | /* |
| 577 | * Set ADC and Voice DAC format. |
| 578 | */ |
| 579 | static int wm8978_set_dai_fmt(struct snd_soc_dai *codec_dai, unsigned int fmt) |
| 580 | { |
| 581 | struct snd_soc_codec *codec = codec_dai->codec; |
| 582 | /* |
| 583 | * BCLK polarity mask = 0x100, LRC clock polarity mask = 0x80, |
| 584 | * Data Format mask = 0x18: all will be calculated anew |
| 585 | */ |
| 586 | u16 iface = snd_soc_read(codec, WM8978_AUDIO_INTERFACE) & ~0x198; |
| 587 | u16 clk = snd_soc_read(codec, WM8978_CLOCKING); |
| 588 | |
| 589 | dev_dbg(codec->dev, "%s\n", __func__); |
| 590 | |
| 591 | /* set master/slave audio interface */ |
| 592 | switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) { |
| 593 | case SND_SOC_DAIFMT_CBM_CFM: |
| 594 | clk |= 1; |
| 595 | break; |
| 596 | case SND_SOC_DAIFMT_CBS_CFS: |
| 597 | clk &= ~1; |
| 598 | break; |
| 599 | default: |
| 600 | return -EINVAL; |
| 601 | } |
| 602 | |
| 603 | /* interface format */ |
| 604 | switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) { |
| 605 | case SND_SOC_DAIFMT_I2S: |
| 606 | iface |= 0x10; |
| 607 | break; |
| 608 | case SND_SOC_DAIFMT_RIGHT_J: |
| 609 | break; |
| 610 | case SND_SOC_DAIFMT_LEFT_J: |
| 611 | iface |= 0x8; |
| 612 | break; |
| 613 | case SND_SOC_DAIFMT_DSP_A: |
| 614 | iface |= 0x18; |
| 615 | break; |
| 616 | default: |
| 617 | return -EINVAL; |
| 618 | } |
| 619 | |
| 620 | /* clock inversion */ |
| 621 | switch (fmt & SND_SOC_DAIFMT_INV_MASK) { |
| 622 | case SND_SOC_DAIFMT_NB_NF: |
| 623 | break; |
| 624 | case SND_SOC_DAIFMT_IB_IF: |
| 625 | iface |= 0x180; |
| 626 | break; |
| 627 | case SND_SOC_DAIFMT_IB_NF: |
| 628 | iface |= 0x100; |
| 629 | break; |
| 630 | case SND_SOC_DAIFMT_NB_IF: |
| 631 | iface |= 0x80; |
| 632 | break; |
| 633 | default: |
| 634 | return -EINVAL; |
| 635 | } |
| 636 | |
| 637 | snd_soc_write(codec, WM8978_AUDIO_INTERFACE, iface); |
| 638 | snd_soc_write(codec, WM8978_CLOCKING, clk); |
| 639 | |
| 640 | return 0; |
| 641 | } |
| 642 | |
| 643 | /* MCLK dividers */ |
| 644 | static const int mclk_numerator[] = {1, 3, 2, 3, 4, 6, 8, 12}; |
| 645 | static const int mclk_denominator[] = {1, 2, 1, 1, 1, 1, 1, 1}; |
| 646 | |
| 647 | /* |
| 648 | * Set PCM DAI bit size and sample rate. |
| 649 | */ |
| 650 | static int wm8978_hw_params(struct snd_pcm_substream *substream, |
| 651 | struct snd_pcm_hw_params *params, |
| 652 | struct snd_soc_dai *dai) |
| 653 | { |
| 654 | struct snd_soc_pcm_runtime *rtd = substream->private_data; |
| 655 | struct snd_soc_device *socdev = rtd->socdev; |
| 656 | struct snd_soc_codec *codec = socdev->card->codec; |
| 657 | struct wm8978_priv *wm8978 = codec->private_data; |
| 658 | /* Word length mask = 0x60 */ |
| 659 | u16 iface_ctl = snd_soc_read(codec, WM8978_AUDIO_INTERFACE) & ~0x60; |
| 660 | /* Sampling rate mask = 0xe (for filters) */ |
| 661 | u16 add_ctl = snd_soc_read(codec, WM8978_ADDITIONAL_CONTROL) & ~0xe; |
| 662 | u16 clking = snd_soc_read(codec, WM8978_CLOCKING); |
| 663 | enum wm8978_sysclk_src current_clk_id = clking & 0x100 ? |
| 664 | WM8978_PLL : WM8978_MCLK; |
| 665 | unsigned int f_sel, diff, diff_best = INT_MAX; |
| 666 | int i, best = 0; |
| 667 | |
| 668 | if (!wm8978->f_mclk) |
| 669 | return -EINVAL; |
| 670 | |
| 671 | /* bit size */ |
| 672 | switch (params_format(params)) { |
| 673 | case SNDRV_PCM_FORMAT_S16_LE: |
| 674 | break; |
| 675 | case SNDRV_PCM_FORMAT_S20_3LE: |
| 676 | iface_ctl |= 0x20; |
| 677 | break; |
| 678 | case SNDRV_PCM_FORMAT_S24_LE: |
| 679 | iface_ctl |= 0x40; |
| 680 | break; |
| 681 | case SNDRV_PCM_FORMAT_S32_LE: |
| 682 | iface_ctl |= 0x60; |
| 683 | break; |
| 684 | } |
| 685 | |
| 686 | /* filter coefficient */ |
| 687 | switch (params_rate(params)) { |
| 688 | case 8000: |
| 689 | add_ctl |= 0x5 << 1; |
| 690 | break; |
| 691 | case 11025: |
| 692 | add_ctl |= 0x4 << 1; |
| 693 | break; |
| 694 | case 16000: |
| 695 | add_ctl |= 0x3 << 1; |
| 696 | break; |
| 697 | case 22050: |
| 698 | add_ctl |= 0x2 << 1; |
| 699 | break; |
| 700 | case 32000: |
| 701 | add_ctl |= 0x1 << 1; |
| 702 | break; |
| 703 | case 44100: |
| 704 | case 48000: |
| 705 | break; |
| 706 | } |
| 707 | |
| 708 | /* Sampling rate is known now, can configure the MCLK divider */ |
| 709 | wm8978->f_256fs = params_rate(params) * 256; |
| 710 | |
| 711 | if (wm8978->sysclk == WM8978_MCLK) { |
| 712 | f_sel = wm8978->f_mclk; |
| 713 | } else { |
| 714 | if (!wm8978->f_pllout) { |
| 715 | int ret = wm8978_configure_pll(codec); |
| 716 | if (ret < 0) |
| 717 | return ret; |
| 718 | } |
| 719 | f_sel = wm8978->f_pllout; |
| 720 | } |
| 721 | |
| 722 | /* |
| 723 | * In some cases it is possible to reconfigure PLL to a higher frequency |
| 724 | * by raising OPCLKDIV, but normally OPCLK is configured to 256 * fs or |
| 725 | * 512 * fs, so, we should be fine. |
| 726 | */ |
| 727 | if (f_sel < wm8978->f_256fs || f_sel > 12 * wm8978->f_256fs) |
| 728 | return -EINVAL; |
| 729 | |
| 730 | for (i = 0; i < ARRAY_SIZE(mclk_numerator); i++) { |
| 731 | diff = abs(wm8978->f_256fs * 3 - |
| 732 | f_sel * 3 * mclk_denominator[i] / mclk_numerator[i]); |
| 733 | |
| 734 | if (diff < diff_best) { |
| 735 | diff_best = diff; |
| 736 | best = i; |
| 737 | } |
| 738 | |
| 739 | if (!diff) |
| 740 | break; |
| 741 | } |
| 742 | |
| 743 | if (diff) |
| 744 | dev_warn(codec->dev, "Imprecise clock: %u%s\n", |
| 745 | f_sel * mclk_denominator[best] / mclk_numerator[best], |
| 746 | wm8978->sysclk == WM8978_MCLK ? |
| 747 | ", consider using PLL" : ""); |
| 748 | |
| 749 | dev_dbg(codec->dev, "%s: fmt %d, rate %u, MCLK divisor #%d\n", __func__, |
| 750 | params_format(params), params_rate(params), best); |
| 751 | |
| 752 | /* MCLK divisor mask = 0xe0 */ |
| 753 | snd_soc_update_bits(codec, WM8978_CLOCKING, 0xe0, best << 5); |
| 754 | |
| 755 | snd_soc_write(codec, WM8978_AUDIO_INTERFACE, iface_ctl); |
| 756 | snd_soc_write(codec, WM8978_ADDITIONAL_CONTROL, add_ctl); |
| 757 | |
| 758 | if (wm8978->sysclk != current_clk_id) { |
| 759 | if (wm8978->sysclk == WM8978_PLL) |
| 760 | /* Run CODEC from PLL instead of MCLK */ |
| 761 | snd_soc_update_bits(codec, WM8978_CLOCKING, |
| 762 | 0x100, 0x100); |
| 763 | else |
| 764 | /* Clock CODEC directly from MCLK */ |
| 765 | snd_soc_update_bits(codec, WM8978_CLOCKING, 0x100, 0); |
| 766 | } |
| 767 | |
| 768 | return 0; |
| 769 | } |
| 770 | |
| 771 | static int wm8978_mute(struct snd_soc_dai *dai, int mute) |
| 772 | { |
| 773 | struct snd_soc_codec *codec = dai->codec; |
| 774 | |
| 775 | dev_dbg(codec->dev, "%s: %d\n", __func__, mute); |
| 776 | |
| 777 | if (mute) |
| 778 | snd_soc_update_bits(codec, WM8978_DAC_CONTROL, 0x40, 0x40); |
| 779 | else |
| 780 | snd_soc_update_bits(codec, WM8978_DAC_CONTROL, 0x40, 0); |
| 781 | |
| 782 | return 0; |
| 783 | } |
| 784 | |
| 785 | static int wm8978_set_bias_level(struct snd_soc_codec *codec, |
| 786 | enum snd_soc_bias_level level) |
| 787 | { |
| 788 | u16 power1 = snd_soc_read(codec, WM8978_POWER_MANAGEMENT_1) & ~3; |
| 789 | |
| 790 | switch (level) { |
| 791 | case SND_SOC_BIAS_ON: |
| 792 | case SND_SOC_BIAS_PREPARE: |
| 793 | power1 |= 1; /* VMID 75k */ |
| 794 | snd_soc_write(codec, WM8978_POWER_MANAGEMENT_1, power1); |
| 795 | break; |
| 796 | case SND_SOC_BIAS_STANDBY: |
| 797 | /* bit 3: enable bias, bit 2: enable I/O tie off buffer */ |
| 798 | power1 |= 0xc; |
| 799 | |
| 800 | if (codec->bias_level == SND_SOC_BIAS_OFF) { |
| 801 | /* Initial cap charge at VMID 5k */ |
| 802 | snd_soc_write(codec, WM8978_POWER_MANAGEMENT_1, |
| 803 | power1 | 0x3); |
| 804 | mdelay(100); |
| 805 | } |
| 806 | |
| 807 | power1 |= 0x2; /* VMID 500k */ |
| 808 | snd_soc_write(codec, WM8978_POWER_MANAGEMENT_1, power1); |
| 809 | break; |
| 810 | case SND_SOC_BIAS_OFF: |
| 811 | /* Preserve PLL - OPCLK may be used by someone */ |
| 812 | snd_soc_update_bits(codec, WM8978_POWER_MANAGEMENT_1, ~0x20, 0); |
| 813 | snd_soc_write(codec, WM8978_POWER_MANAGEMENT_2, 0); |
| 814 | snd_soc_write(codec, WM8978_POWER_MANAGEMENT_3, 0); |
| 815 | break; |
| 816 | } |
| 817 | |
| 818 | dev_dbg(codec->dev, "%s: %d, %x\n", __func__, level, power1); |
| 819 | |
| 820 | codec->bias_level = level; |
| 821 | return 0; |
| 822 | } |
| 823 | |
| 824 | #define WM8978_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE | \ |
| 825 | SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S32_LE) |
| 826 | |
| 827 | static struct snd_soc_dai_ops wm8978_dai_ops = { |
| 828 | .hw_params = wm8978_hw_params, |
| 829 | .digital_mute = wm8978_mute, |
| 830 | .set_fmt = wm8978_set_dai_fmt, |
| 831 | .set_clkdiv = wm8978_set_dai_clkdiv, |
| 832 | .set_sysclk = wm8978_set_dai_sysclk, |
| 833 | }; |
| 834 | |
| 835 | /* Also supports 12kHz */ |
| 836 | struct snd_soc_dai wm8978_dai = { |
| 837 | .name = "WM8978 HiFi", |
| 838 | .id = 1, |
| 839 | .playback = { |
| 840 | .stream_name = "Playback", |
| 841 | .channels_min = 1, |
| 842 | .channels_max = 2, |
| 843 | .rates = SNDRV_PCM_RATE_8000_48000, |
| 844 | .formats = WM8978_FORMATS, |
| 845 | }, |
| 846 | .capture = { |
| 847 | .stream_name = "Capture", |
| 848 | .channels_min = 1, |
| 849 | .channels_max = 2, |
| 850 | .rates = SNDRV_PCM_RATE_8000_48000, |
| 851 | .formats = WM8978_FORMATS, |
| 852 | }, |
| 853 | .ops = &wm8978_dai_ops, |
| 854 | }; |
| 855 | EXPORT_SYMBOL_GPL(wm8978_dai); |
| 856 | |
| 857 | static int wm8978_suspend(struct platform_device *pdev, pm_message_t state) |
| 858 | { |
| 859 | struct snd_soc_device *socdev = platform_get_drvdata(pdev); |
| 860 | struct snd_soc_codec *codec = socdev->card->codec; |
| 861 | |
| 862 | wm8978_set_bias_level(codec, SND_SOC_BIAS_OFF); |
| 863 | /* Also switch PLL off */ |
| 864 | snd_soc_write(codec, WM8978_POWER_MANAGEMENT_1, 0); |
Guennadi Liakhovetski | 0d34e91 | 2010-01-27 18:56:23 +0100 | [diff] [blame] | 865 | |
| 866 | return 0; |
| 867 | } |
| 868 | |
| 869 | static int wm8978_resume(struct platform_device *pdev) |
| 870 | { |
| 871 | struct snd_soc_device *socdev = platform_get_drvdata(pdev); |
| 872 | struct snd_soc_codec *codec = socdev->card->codec; |
| 873 | struct wm8978_priv *wm8978 = codec->private_data; |
| 874 | int i; |
| 875 | u16 *cache = codec->reg_cache; |
| 876 | |
Guennadi Liakhovetski | 0d34e91 | 2010-01-27 18:56:23 +0100 | [diff] [blame] | 877 | /* Sync reg_cache with the hardware */ |
| 878 | for (i = 0; i < ARRAY_SIZE(wm8978_reg); i++) { |
| 879 | if (i == WM8978_RESET) |
| 880 | continue; |
| 881 | if (cache[i] != wm8978_reg[i]) |
| 882 | snd_soc_write(codec, i, cache[i]); |
| 883 | } |
| 884 | |
| 885 | wm8978_set_bias_level(codec, SND_SOC_BIAS_STANDBY); |
| 886 | |
| 887 | if (wm8978->f_pllout) |
| 888 | /* Switch PLL on */ |
| 889 | snd_soc_update_bits(codec, WM8978_POWER_MANAGEMENT_1, 0x20, 0x20); |
| 890 | |
| 891 | return 0; |
| 892 | } |
| 893 | |
| 894 | static int wm8978_probe(struct platform_device *pdev) |
| 895 | { |
| 896 | struct snd_soc_device *socdev = platform_get_drvdata(pdev); |
| 897 | struct snd_soc_codec *codec; |
| 898 | int ret = 0; |
| 899 | |
| 900 | if (wm8978_codec == NULL) { |
| 901 | dev_err(&pdev->dev, "Codec device not registered\n"); |
| 902 | return -ENODEV; |
| 903 | } |
| 904 | |
| 905 | socdev->card->codec = wm8978_codec; |
| 906 | codec = wm8978_codec; |
| 907 | |
| 908 | /* register pcms */ |
| 909 | ret = snd_soc_new_pcms(socdev, SNDRV_DEFAULT_IDX1, SNDRV_DEFAULT_STR1); |
| 910 | if (ret < 0) { |
| 911 | dev_err(codec->dev, "failed to create pcms: %d\n", ret); |
| 912 | goto pcm_err; |
| 913 | } |
| 914 | |
| 915 | snd_soc_add_controls(codec, wm8978_snd_controls, |
| 916 | ARRAY_SIZE(wm8978_snd_controls)); |
| 917 | wm8978_add_widgets(codec); |
| 918 | |
| 919 | pcm_err: |
| 920 | return ret; |
| 921 | } |
| 922 | |
| 923 | /* power down chip */ |
| 924 | static int wm8978_remove(struct platform_device *pdev) |
| 925 | { |
| 926 | struct snd_soc_device *socdev = platform_get_drvdata(pdev); |
| 927 | |
| 928 | snd_soc_free_pcms(socdev); |
| 929 | snd_soc_dapm_free(socdev); |
| 930 | |
| 931 | return 0; |
| 932 | } |
| 933 | |
| 934 | struct snd_soc_codec_device soc_codec_dev_wm8978 = { |
| 935 | .probe = wm8978_probe, |
| 936 | .remove = wm8978_remove, |
| 937 | .suspend = wm8978_suspend, |
| 938 | .resume = wm8978_resume, |
| 939 | }; |
| 940 | EXPORT_SYMBOL_GPL(soc_codec_dev_wm8978); |
| 941 | |
| 942 | /* |
| 943 | * These registers contain an "update" bit - bit 8. This means, for example, |
| 944 | * that one can write new DAC digital volume for both channels, but only when |
| 945 | * the update bit is set, will also the volume be updated - simultaneously for |
| 946 | * both channels. |
| 947 | */ |
| 948 | static const int update_reg[] = { |
| 949 | WM8978_LEFT_DAC_DIGITAL_VOLUME, |
| 950 | WM8978_RIGHT_DAC_DIGITAL_VOLUME, |
| 951 | WM8978_LEFT_ADC_DIGITAL_VOLUME, |
| 952 | WM8978_RIGHT_ADC_DIGITAL_VOLUME, |
| 953 | WM8978_LEFT_INP_PGA_CONTROL, |
| 954 | WM8978_RIGHT_INP_PGA_CONTROL, |
| 955 | WM8978_LOUT1_HP_CONTROL, |
| 956 | WM8978_ROUT1_HP_CONTROL, |
| 957 | WM8978_LOUT2_SPK_CONTROL, |
| 958 | WM8978_ROUT2_SPK_CONTROL, |
| 959 | }; |
| 960 | |
| 961 | static __devinit int wm8978_register(struct wm8978_priv *wm8978) |
| 962 | { |
| 963 | int ret, i; |
| 964 | struct snd_soc_codec *codec = &wm8978->codec; |
| 965 | |
| 966 | if (wm8978_codec) { |
| 967 | dev_err(codec->dev, "Another WM8978 is registered\n"); |
| 968 | return -EINVAL; |
| 969 | } |
| 970 | |
| 971 | /* |
| 972 | * Set default system clock to PLL, it is more precise, this is also the |
| 973 | * default hardware setting |
| 974 | */ |
| 975 | wm8978->sysclk = WM8978_PLL; |
| 976 | |
| 977 | mutex_init(&codec->mutex); |
| 978 | INIT_LIST_HEAD(&codec->dapm_widgets); |
| 979 | INIT_LIST_HEAD(&codec->dapm_paths); |
| 980 | |
| 981 | codec->private_data = wm8978; |
| 982 | codec->name = "WM8978"; |
| 983 | codec->owner = THIS_MODULE; |
| 984 | codec->bias_level = SND_SOC_BIAS_OFF; |
| 985 | codec->set_bias_level = wm8978_set_bias_level; |
| 986 | codec->dai = &wm8978_dai; |
| 987 | codec->num_dai = 1; |
| 988 | codec->reg_cache_size = WM8978_CACHEREGNUM; |
| 989 | codec->reg_cache = &wm8978->reg_cache; |
| 990 | |
| 991 | ret = snd_soc_codec_set_cache_io(codec, 7, 9, SND_SOC_I2C); |
| 992 | if (ret < 0) { |
| 993 | dev_err(codec->dev, "Failed to set cache I/O: %d\n", ret); |
| 994 | goto err; |
| 995 | } |
| 996 | |
| 997 | memcpy(codec->reg_cache, wm8978_reg, sizeof(wm8978_reg)); |
| 998 | |
| 999 | /* |
| 1000 | * Set the update bit in all registers, that have one. This way all |
| 1001 | * writes to those registers will also cause the update bit to be |
| 1002 | * written. |
| 1003 | */ |
| 1004 | for (i = 0; i < ARRAY_SIZE(update_reg); i++) |
| 1005 | ((u16 *)codec->reg_cache)[update_reg[i]] |= 0x100; |
| 1006 | |
| 1007 | /* Reset the codec */ |
| 1008 | ret = snd_soc_write(codec, WM8978_RESET, 0); |
| 1009 | if (ret < 0) { |
| 1010 | dev_err(codec->dev, "Failed to issue reset\n"); |
| 1011 | goto err; |
| 1012 | } |
| 1013 | |
| 1014 | wm8978_dai.dev = codec->dev; |
| 1015 | |
| 1016 | wm8978_set_bias_level(codec, SND_SOC_BIAS_STANDBY); |
| 1017 | |
| 1018 | wm8978_codec = codec; |
| 1019 | |
| 1020 | ret = snd_soc_register_codec(codec); |
| 1021 | if (ret != 0) { |
| 1022 | dev_err(codec->dev, "Failed to register codec: %d\n", ret); |
| 1023 | goto err; |
| 1024 | } |
| 1025 | |
| 1026 | ret = snd_soc_register_dai(&wm8978_dai); |
| 1027 | if (ret != 0) { |
| 1028 | dev_err(codec->dev, "Failed to register DAI: %d\n", ret); |
| 1029 | goto err_codec; |
| 1030 | } |
| 1031 | |
| 1032 | return 0; |
| 1033 | |
| 1034 | err_codec: |
| 1035 | snd_soc_unregister_codec(codec); |
| 1036 | err: |
| 1037 | kfree(wm8978); |
| 1038 | return ret; |
| 1039 | } |
| 1040 | |
| 1041 | static __devexit void wm8978_unregister(struct wm8978_priv *wm8978) |
| 1042 | { |
| 1043 | wm8978_set_bias_level(&wm8978->codec, SND_SOC_BIAS_OFF); |
| 1044 | snd_soc_unregister_dai(&wm8978_dai); |
| 1045 | snd_soc_unregister_codec(&wm8978->codec); |
| 1046 | kfree(wm8978); |
| 1047 | wm8978_codec = NULL; |
| 1048 | } |
| 1049 | |
| 1050 | static __devinit int wm8978_i2c_probe(struct i2c_client *i2c, |
| 1051 | const struct i2c_device_id *id) |
| 1052 | { |
| 1053 | struct wm8978_priv *wm8978; |
| 1054 | struct snd_soc_codec *codec; |
| 1055 | |
| 1056 | wm8978 = kzalloc(sizeof(struct wm8978_priv), GFP_KERNEL); |
| 1057 | if (wm8978 == NULL) |
| 1058 | return -ENOMEM; |
| 1059 | |
| 1060 | codec = &wm8978->codec; |
| 1061 | codec->hw_write = (hw_write_t)i2c_master_send; |
| 1062 | |
| 1063 | i2c_set_clientdata(i2c, wm8978); |
| 1064 | codec->control_data = i2c; |
| 1065 | |
| 1066 | codec->dev = &i2c->dev; |
| 1067 | |
| 1068 | return wm8978_register(wm8978); |
| 1069 | } |
| 1070 | |
| 1071 | static __devexit int wm8978_i2c_remove(struct i2c_client *client) |
| 1072 | { |
| 1073 | struct wm8978_priv *wm8978 = i2c_get_clientdata(client); |
| 1074 | wm8978_unregister(wm8978); |
| 1075 | return 0; |
| 1076 | } |
| 1077 | |
| 1078 | static const struct i2c_device_id wm8978_i2c_id[] = { |
| 1079 | { "wm8978", 0 }, |
| 1080 | { } |
| 1081 | }; |
| 1082 | MODULE_DEVICE_TABLE(i2c, wm8978_i2c_id); |
| 1083 | |
| 1084 | static struct i2c_driver wm8978_i2c_driver = { |
| 1085 | .driver = { |
| 1086 | .name = "WM8978", |
| 1087 | .owner = THIS_MODULE, |
| 1088 | }, |
| 1089 | .probe = wm8978_i2c_probe, |
| 1090 | .remove = __devexit_p(wm8978_i2c_remove), |
| 1091 | .id_table = wm8978_i2c_id, |
| 1092 | }; |
| 1093 | |
| 1094 | static int __init wm8978_modinit(void) |
| 1095 | { |
| 1096 | return i2c_add_driver(&wm8978_i2c_driver); |
| 1097 | } |
| 1098 | module_init(wm8978_modinit); |
| 1099 | |
| 1100 | static void __exit wm8978_exit(void) |
| 1101 | { |
| 1102 | i2c_del_driver(&wm8978_i2c_driver); |
| 1103 | } |
| 1104 | module_exit(wm8978_exit); |
| 1105 | |
| 1106 | MODULE_DESCRIPTION("ASoC WM8978 codec driver"); |
| 1107 | MODULE_AUTHOR("Guennadi Liakhovetski <g.liakhovetski@gmx.de>"); |
| 1108 | MODULE_LICENSE("GPL"); |