Paul Walmsley | b045d08 | 2008-03-18 11:24:28 +0200 | [diff] [blame] | 1 | /* |
| 2 | * OMAP3 clock framework |
| 3 | * |
| 4 | * Copyright (C) 2007-2008 Texas Instruments, Inc. |
| 5 | * Copyright (C) 2007-2008 Nokia Corporation |
| 6 | * |
| 7 | * Written by Paul Walmsley |
Paul Walmsley | 542313c | 2008-07-03 12:24:45 +0300 | [diff] [blame] | 8 | * With many device clock fixes by Kevin Hilman and Jouni Högander |
| 9 | * DPLL bypass clock support added by Roman Tereshonkov |
| 10 | * |
| 11 | */ |
| 12 | |
| 13 | /* |
| 14 | * Virtual clocks are introduced as convenient tools. |
| 15 | * They are sources for other clocks and not supposed |
| 16 | * to be requested from drivers directly. |
Paul Walmsley | b045d08 | 2008-03-18 11:24:28 +0200 | [diff] [blame] | 17 | */ |
| 18 | |
| 19 | #ifndef __ARCH_ARM_MACH_OMAP2_CLOCK34XX_H |
| 20 | #define __ARCH_ARM_MACH_OMAP2_CLOCK34XX_H |
| 21 | |
Russell King | a09e64f | 2008-08-05 16:14:15 +0100 | [diff] [blame] | 22 | #include <mach/control.h> |
Paul Walmsley | b045d08 | 2008-03-18 11:24:28 +0200 | [diff] [blame] | 23 | |
| 24 | #include "clock.h" |
| 25 | #include "cm.h" |
| 26 | #include "cm-regbits-34xx.h" |
| 27 | #include "prm.h" |
| 28 | #include "prm-regbits-34xx.h" |
| 29 | |
| 30 | static void omap3_dpll_recalc(struct clk *clk); |
| 31 | static void omap3_clkoutx2_recalc(struct clk *clk); |
Paul Walmsley | 542313c | 2008-07-03 12:24:45 +0300 | [diff] [blame] | 32 | static void omap3_dpll_allow_idle(struct clk *clk); |
| 33 | static void omap3_dpll_deny_idle(struct clk *clk); |
| 34 | static u32 omap3_dpll_autoidle_read(struct clk *clk); |
Paul Walmsley | b045d08 | 2008-03-18 11:24:28 +0200 | [diff] [blame] | 35 | |
Paul Walmsley | 88b8ba9 | 2008-07-03 12:24:46 +0300 | [diff] [blame] | 36 | /* Maximum DPLL multiplier, divider values for OMAP3 */ |
| 37 | #define OMAP3_MAX_DPLL_MULT 2048 |
| 38 | #define OMAP3_MAX_DPLL_DIV 128 |
| 39 | |
Paul Walmsley | b045d08 | 2008-03-18 11:24:28 +0200 | [diff] [blame] | 40 | /* |
| 41 | * DPLL1 supplies clock to the MPU. |
| 42 | * DPLL2 supplies clock to the IVA2. |
| 43 | * DPLL3 supplies CORE domain clocks. |
| 44 | * DPLL4 supplies peripheral clocks. |
| 45 | * DPLL5 supplies other peripheral clocks (USBHOST, USIM). |
| 46 | */ |
| 47 | |
Paul Walmsley | 542313c | 2008-07-03 12:24:45 +0300 | [diff] [blame] | 48 | /* CM_CLKEN_PLL*.EN* bit values - not all are available for every DPLL */ |
| 49 | #define DPLL_LOW_POWER_STOP 0x1 |
| 50 | #define DPLL_LOW_POWER_BYPASS 0x5 |
| 51 | #define DPLL_LOCKED 0x7 |
| 52 | |
Paul Walmsley | b045d08 | 2008-03-18 11:24:28 +0200 | [diff] [blame] | 53 | /* PRM CLOCKS */ |
| 54 | |
| 55 | /* According to timer32k.c, this is a 32768Hz clock, not a 32000Hz clock. */ |
| 56 | static struct clk omap_32k_fck = { |
| 57 | .name = "omap_32k_fck", |
Russell King | 897dcde | 2008-11-04 16:35:03 +0000 | [diff] [blame] | 58 | .ops = &clkops_null, |
Paul Walmsley | b045d08 | 2008-03-18 11:24:28 +0200 | [diff] [blame] | 59 | .rate = 32768, |
Russell King | 897dcde | 2008-11-04 16:35:03 +0000 | [diff] [blame] | 60 | .flags = CLOCK_IN_OMAP343X | RATE_FIXED | RATE_PROPAGATES, |
Paul Walmsley | b045d08 | 2008-03-18 11:24:28 +0200 | [diff] [blame] | 61 | .recalc = &propagate_rate, |
| 62 | }; |
| 63 | |
| 64 | static struct clk secure_32k_fck = { |
| 65 | .name = "secure_32k_fck", |
Russell King | 897dcde | 2008-11-04 16:35:03 +0000 | [diff] [blame] | 66 | .ops = &clkops_null, |
Paul Walmsley | b045d08 | 2008-03-18 11:24:28 +0200 | [diff] [blame] | 67 | .rate = 32768, |
Russell King | 897dcde | 2008-11-04 16:35:03 +0000 | [diff] [blame] | 68 | .flags = CLOCK_IN_OMAP343X | RATE_FIXED | RATE_PROPAGATES, |
Paul Walmsley | b045d08 | 2008-03-18 11:24:28 +0200 | [diff] [blame] | 69 | .recalc = &propagate_rate, |
| 70 | }; |
| 71 | |
| 72 | /* Virtual source clocks for osc_sys_ck */ |
| 73 | static struct clk virt_12m_ck = { |
| 74 | .name = "virt_12m_ck", |
Russell King | 897dcde | 2008-11-04 16:35:03 +0000 | [diff] [blame] | 75 | .ops = &clkops_null, |
Paul Walmsley | b045d08 | 2008-03-18 11:24:28 +0200 | [diff] [blame] | 76 | .rate = 12000000, |
Russell King | 897dcde | 2008-11-04 16:35:03 +0000 | [diff] [blame] | 77 | .flags = CLOCK_IN_OMAP343X | RATE_FIXED | RATE_PROPAGATES, |
Paul Walmsley | b045d08 | 2008-03-18 11:24:28 +0200 | [diff] [blame] | 78 | .recalc = &propagate_rate, |
| 79 | }; |
| 80 | |
| 81 | static struct clk virt_13m_ck = { |
| 82 | .name = "virt_13m_ck", |
Russell King | 897dcde | 2008-11-04 16:35:03 +0000 | [diff] [blame] | 83 | .ops = &clkops_null, |
Paul Walmsley | b045d08 | 2008-03-18 11:24:28 +0200 | [diff] [blame] | 84 | .rate = 13000000, |
Russell King | 897dcde | 2008-11-04 16:35:03 +0000 | [diff] [blame] | 85 | .flags = CLOCK_IN_OMAP343X | RATE_FIXED | RATE_PROPAGATES, |
Paul Walmsley | b045d08 | 2008-03-18 11:24:28 +0200 | [diff] [blame] | 86 | .recalc = &propagate_rate, |
| 87 | }; |
| 88 | |
| 89 | static struct clk virt_16_8m_ck = { |
| 90 | .name = "virt_16_8m_ck", |
Russell King | 897dcde | 2008-11-04 16:35:03 +0000 | [diff] [blame] | 91 | .ops = &clkops_null, |
Paul Walmsley | b045d08 | 2008-03-18 11:24:28 +0200 | [diff] [blame] | 92 | .rate = 16800000, |
Russell King | 897dcde | 2008-11-04 16:35:03 +0000 | [diff] [blame] | 93 | .flags = CLOCK_IN_OMAP3430ES2 | RATE_FIXED | RATE_PROPAGATES, |
Paul Walmsley | b045d08 | 2008-03-18 11:24:28 +0200 | [diff] [blame] | 94 | .recalc = &propagate_rate, |
| 95 | }; |
| 96 | |
| 97 | static struct clk virt_19_2m_ck = { |
| 98 | .name = "virt_19_2m_ck", |
Russell King | 897dcde | 2008-11-04 16:35:03 +0000 | [diff] [blame] | 99 | .ops = &clkops_null, |
Paul Walmsley | b045d08 | 2008-03-18 11:24:28 +0200 | [diff] [blame] | 100 | .rate = 19200000, |
Russell King | 897dcde | 2008-11-04 16:35:03 +0000 | [diff] [blame] | 101 | .flags = CLOCK_IN_OMAP343X | RATE_FIXED | RATE_PROPAGATES, |
Paul Walmsley | b045d08 | 2008-03-18 11:24:28 +0200 | [diff] [blame] | 102 | .recalc = &propagate_rate, |
| 103 | }; |
| 104 | |
| 105 | static struct clk virt_26m_ck = { |
| 106 | .name = "virt_26m_ck", |
Russell King | 897dcde | 2008-11-04 16:35:03 +0000 | [diff] [blame] | 107 | .ops = &clkops_null, |
Paul Walmsley | b045d08 | 2008-03-18 11:24:28 +0200 | [diff] [blame] | 108 | .rate = 26000000, |
Russell King | 897dcde | 2008-11-04 16:35:03 +0000 | [diff] [blame] | 109 | .flags = CLOCK_IN_OMAP343X | RATE_FIXED | RATE_PROPAGATES, |
Paul Walmsley | b045d08 | 2008-03-18 11:24:28 +0200 | [diff] [blame] | 110 | .recalc = &propagate_rate, |
| 111 | }; |
| 112 | |
| 113 | static struct clk virt_38_4m_ck = { |
| 114 | .name = "virt_38_4m_ck", |
Russell King | 897dcde | 2008-11-04 16:35:03 +0000 | [diff] [blame] | 115 | .ops = &clkops_null, |
Paul Walmsley | b045d08 | 2008-03-18 11:24:28 +0200 | [diff] [blame] | 116 | .rate = 38400000, |
Russell King | 897dcde | 2008-11-04 16:35:03 +0000 | [diff] [blame] | 117 | .flags = CLOCK_IN_OMAP343X | RATE_FIXED | RATE_PROPAGATES, |
Paul Walmsley | b045d08 | 2008-03-18 11:24:28 +0200 | [diff] [blame] | 118 | .recalc = &propagate_rate, |
| 119 | }; |
| 120 | |
| 121 | static const struct clksel_rate osc_sys_12m_rates[] = { |
| 122 | { .div = 1, .val = 0, .flags = RATE_IN_343X | DEFAULT_RATE }, |
| 123 | { .div = 0 } |
| 124 | }; |
| 125 | |
| 126 | static const struct clksel_rate osc_sys_13m_rates[] = { |
| 127 | { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE }, |
| 128 | { .div = 0 } |
| 129 | }; |
| 130 | |
| 131 | static const struct clksel_rate osc_sys_16_8m_rates[] = { |
| 132 | { .div = 1, .val = 5, .flags = RATE_IN_3430ES2 | DEFAULT_RATE }, |
| 133 | { .div = 0 } |
| 134 | }; |
| 135 | |
| 136 | static const struct clksel_rate osc_sys_19_2m_rates[] = { |
| 137 | { .div = 1, .val = 2, .flags = RATE_IN_343X | DEFAULT_RATE }, |
| 138 | { .div = 0 } |
| 139 | }; |
| 140 | |
| 141 | static const struct clksel_rate osc_sys_26m_rates[] = { |
| 142 | { .div = 1, .val = 3, .flags = RATE_IN_343X | DEFAULT_RATE }, |
| 143 | { .div = 0 } |
| 144 | }; |
| 145 | |
| 146 | static const struct clksel_rate osc_sys_38_4m_rates[] = { |
| 147 | { .div = 1, .val = 4, .flags = RATE_IN_343X | DEFAULT_RATE }, |
| 148 | { .div = 0 } |
| 149 | }; |
| 150 | |
| 151 | static const struct clksel osc_sys_clksel[] = { |
| 152 | { .parent = &virt_12m_ck, .rates = osc_sys_12m_rates }, |
| 153 | { .parent = &virt_13m_ck, .rates = osc_sys_13m_rates }, |
| 154 | { .parent = &virt_16_8m_ck, .rates = osc_sys_16_8m_rates }, |
| 155 | { .parent = &virt_19_2m_ck, .rates = osc_sys_19_2m_rates }, |
| 156 | { .parent = &virt_26m_ck, .rates = osc_sys_26m_rates }, |
| 157 | { .parent = &virt_38_4m_ck, .rates = osc_sys_38_4m_rates }, |
| 158 | { .parent = NULL }, |
| 159 | }; |
| 160 | |
| 161 | /* Oscillator clock */ |
| 162 | /* 12, 13, 16.8, 19.2, 26, or 38.4 MHz */ |
| 163 | static struct clk osc_sys_ck = { |
| 164 | .name = "osc_sys_ck", |
Russell King | 897dcde | 2008-11-04 16:35:03 +0000 | [diff] [blame] | 165 | .ops = &clkops_null, |
Paul Walmsley | b045d08 | 2008-03-18 11:24:28 +0200 | [diff] [blame] | 166 | .init = &omap2_init_clksel_parent, |
| 167 | .clksel_reg = OMAP3430_PRM_CLKSEL, |
| 168 | .clksel_mask = OMAP3430_SYS_CLKIN_SEL_MASK, |
| 169 | .clksel = osc_sys_clksel, |
| 170 | /* REVISIT: deal with autoextclkmode? */ |
Russell King | 897dcde | 2008-11-04 16:35:03 +0000 | [diff] [blame] | 171 | .flags = CLOCK_IN_OMAP343X | RATE_FIXED | RATE_PROPAGATES, |
Paul Walmsley | b045d08 | 2008-03-18 11:24:28 +0200 | [diff] [blame] | 172 | .recalc = &omap2_clksel_recalc, |
| 173 | }; |
| 174 | |
| 175 | static const struct clksel_rate div2_rates[] = { |
| 176 | { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE }, |
| 177 | { .div = 2, .val = 2, .flags = RATE_IN_343X }, |
| 178 | { .div = 0 } |
| 179 | }; |
| 180 | |
| 181 | static const struct clksel sys_clksel[] = { |
| 182 | { .parent = &osc_sys_ck, .rates = div2_rates }, |
| 183 | { .parent = NULL } |
| 184 | }; |
| 185 | |
| 186 | /* Latency: this clock is only enabled after PRM_CLKSETUP.SETUP_TIME */ |
| 187 | /* Feeds DPLLs - divided first by PRM_CLKSRC_CTRL.SYSCLKDIV? */ |
| 188 | static struct clk sys_ck = { |
| 189 | .name = "sys_ck", |
Russell King | 897dcde | 2008-11-04 16:35:03 +0000 | [diff] [blame] | 190 | .ops = &clkops_null, |
Paul Walmsley | b045d08 | 2008-03-18 11:24:28 +0200 | [diff] [blame] | 191 | .parent = &osc_sys_ck, |
| 192 | .init = &omap2_init_clksel_parent, |
| 193 | .clksel_reg = OMAP3430_PRM_CLKSRC_CTRL, |
| 194 | .clksel_mask = OMAP_SYSCLKDIV_MASK, |
| 195 | .clksel = sys_clksel, |
Russell King | 897dcde | 2008-11-04 16:35:03 +0000 | [diff] [blame] | 196 | .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES, |
Paul Walmsley | b045d08 | 2008-03-18 11:24:28 +0200 | [diff] [blame] | 197 | .recalc = &omap2_clksel_recalc, |
| 198 | }; |
| 199 | |
| 200 | static struct clk sys_altclk = { |
| 201 | .name = "sys_altclk", |
Russell King | 897dcde | 2008-11-04 16:35:03 +0000 | [diff] [blame] | 202 | .ops = &clkops_null, |
| 203 | .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES, |
Paul Walmsley | b045d08 | 2008-03-18 11:24:28 +0200 | [diff] [blame] | 204 | .recalc = &propagate_rate, |
| 205 | }; |
| 206 | |
| 207 | /* Optional external clock input for some McBSPs */ |
| 208 | static struct clk mcbsp_clks = { |
| 209 | .name = "mcbsp_clks", |
Russell King | 897dcde | 2008-11-04 16:35:03 +0000 | [diff] [blame] | 210 | .ops = &clkops_null, |
| 211 | .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES, |
Paul Walmsley | b045d08 | 2008-03-18 11:24:28 +0200 | [diff] [blame] | 212 | .recalc = &propagate_rate, |
| 213 | }; |
| 214 | |
| 215 | /* PRM EXTERNAL CLOCK OUTPUT */ |
| 216 | |
| 217 | static struct clk sys_clkout1 = { |
| 218 | .name = "sys_clkout1", |
| 219 | .parent = &osc_sys_ck, |
| 220 | .enable_reg = OMAP3430_PRM_CLKOUT_CTRL, |
| 221 | .enable_bit = OMAP3430_CLKOUT_EN_SHIFT, |
| 222 | .flags = CLOCK_IN_OMAP343X, |
| 223 | .recalc = &followparent_recalc, |
| 224 | }; |
| 225 | |
| 226 | /* DPLLS */ |
| 227 | |
| 228 | /* CM CLOCKS */ |
| 229 | |
Roman Tereshonkov | 3760d31 | 2008-03-13 21:35:09 +0200 | [diff] [blame] | 230 | static const struct clksel_rate dpll_bypass_rates[] = { |
| 231 | { .div = 1, .val = 0, .flags = RATE_IN_343X | DEFAULT_RATE }, |
| 232 | { .div = 0 } |
Paul Walmsley | b045d08 | 2008-03-18 11:24:28 +0200 | [diff] [blame] | 233 | }; |
| 234 | |
Roman Tereshonkov | 3760d31 | 2008-03-13 21:35:09 +0200 | [diff] [blame] | 235 | static const struct clksel_rate dpll_locked_rates[] = { |
| 236 | { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE }, |
| 237 | { .div = 0 } |
Paul Walmsley | b045d08 | 2008-03-18 11:24:28 +0200 | [diff] [blame] | 238 | }; |
| 239 | |
| 240 | static const struct clksel_rate div16_dpll_rates[] = { |
| 241 | { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE }, |
| 242 | { .div = 2, .val = 2, .flags = RATE_IN_343X }, |
| 243 | { .div = 3, .val = 3, .flags = RATE_IN_343X }, |
| 244 | { .div = 4, .val = 4, .flags = RATE_IN_343X }, |
| 245 | { .div = 5, .val = 5, .flags = RATE_IN_343X }, |
| 246 | { .div = 6, .val = 6, .flags = RATE_IN_343X }, |
| 247 | { .div = 7, .val = 7, .flags = RATE_IN_343X }, |
| 248 | { .div = 8, .val = 8, .flags = RATE_IN_343X }, |
| 249 | { .div = 9, .val = 9, .flags = RATE_IN_343X }, |
| 250 | { .div = 10, .val = 10, .flags = RATE_IN_343X }, |
| 251 | { .div = 11, .val = 11, .flags = RATE_IN_343X }, |
| 252 | { .div = 12, .val = 12, .flags = RATE_IN_343X }, |
| 253 | { .div = 13, .val = 13, .flags = RATE_IN_343X }, |
| 254 | { .div = 14, .val = 14, .flags = RATE_IN_343X }, |
| 255 | { .div = 15, .val = 15, .flags = RATE_IN_343X }, |
| 256 | { .div = 16, .val = 16, .flags = RATE_IN_343X }, |
| 257 | { .div = 0 } |
| 258 | }; |
| 259 | |
Roman Tereshonkov | 3760d31 | 2008-03-13 21:35:09 +0200 | [diff] [blame] | 260 | /* DPLL1 */ |
| 261 | /* MPU clock source */ |
| 262 | /* Type: DPLL */ |
Paul Walmsley | 88b8ba9 | 2008-07-03 12:24:46 +0300 | [diff] [blame] | 263 | static struct dpll_data dpll1_dd = { |
Roman Tereshonkov | 3760d31 | 2008-03-13 21:35:09 +0200 | [diff] [blame] | 264 | .mult_div1_reg = OMAP_CM_REGADDR(MPU_MOD, OMAP3430_CM_CLKSEL1_PLL), |
| 265 | .mult_mask = OMAP3430_MPU_DPLL_MULT_MASK, |
| 266 | .div1_mask = OMAP3430_MPU_DPLL_DIV_MASK, |
| 267 | .control_reg = OMAP_CM_REGADDR(MPU_MOD, OMAP3430_CM_CLKEN_PLL), |
| 268 | .enable_mask = OMAP3430_EN_MPU_DPLL_MASK, |
Paul Walmsley | 542313c | 2008-07-03 12:24:45 +0300 | [diff] [blame] | 269 | .modes = (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED), |
Roman Tereshonkov | 3760d31 | 2008-03-13 21:35:09 +0200 | [diff] [blame] | 270 | .auto_recal_bit = OMAP3430_EN_MPU_DPLL_DRIFTGUARD_SHIFT, |
| 271 | .recal_en_bit = OMAP3430_MPU_DPLL_RECAL_EN_SHIFT, |
| 272 | .recal_st_bit = OMAP3430_MPU_DPLL_ST_SHIFT, |
Paul Walmsley | 542313c | 2008-07-03 12:24:45 +0300 | [diff] [blame] | 273 | .autoidle_reg = OMAP_CM_REGADDR(MPU_MOD, OMAP3430_CM_AUTOIDLE_PLL), |
| 274 | .autoidle_mask = OMAP3430_AUTO_MPU_DPLL_MASK, |
| 275 | .idlest_reg = OMAP_CM_REGADDR(MPU_MOD, OMAP3430_CM_IDLEST_PLL), |
| 276 | .idlest_bit = OMAP3430_ST_MPU_CLK_SHIFT, |
Paul Walmsley | 88b8ba9 | 2008-07-03 12:24:46 +0300 | [diff] [blame] | 277 | .max_multiplier = OMAP3_MAX_DPLL_MULT, |
| 278 | .max_divider = OMAP3_MAX_DPLL_DIV, |
| 279 | .rate_tolerance = DEFAULT_DPLL_RATE_TOLERANCE |
Roman Tereshonkov | 3760d31 | 2008-03-13 21:35:09 +0200 | [diff] [blame] | 280 | }; |
| 281 | |
| 282 | static struct clk dpll1_ck = { |
| 283 | .name = "dpll1_ck", |
Russell King | 897dcde | 2008-11-04 16:35:03 +0000 | [diff] [blame] | 284 | .ops = &clkops_null, |
Roman Tereshonkov | 3760d31 | 2008-03-13 21:35:09 +0200 | [diff] [blame] | 285 | .parent = &sys_ck, |
| 286 | .dpll_data = &dpll1_dd, |
Russell King | 897dcde | 2008-11-04 16:35:03 +0000 | [diff] [blame] | 287 | .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES, |
Paul Walmsley | 88b8ba9 | 2008-07-03 12:24:46 +0300 | [diff] [blame] | 288 | .round_rate = &omap2_dpll_round_rate, |
Roman Tereshonkov | 3760d31 | 2008-03-13 21:35:09 +0200 | [diff] [blame] | 289 | .recalc = &omap3_dpll_recalc, |
| 290 | }; |
| 291 | |
| 292 | /* |
| 293 | * This virtual clock provides the CLKOUTX2 output from the DPLL if the |
| 294 | * DPLL isn't bypassed. |
| 295 | */ |
| 296 | static struct clk dpll1_x2_ck = { |
| 297 | .name = "dpll1_x2_ck", |
Russell King | 5713718 | 2008-11-04 16:48:35 +0000 | [diff] [blame^] | 298 | .ops = &clkops_null, |
Roman Tereshonkov | 3760d31 | 2008-03-13 21:35:09 +0200 | [diff] [blame] | 299 | .parent = &dpll1_ck, |
Russell King | 5713718 | 2008-11-04 16:48:35 +0000 | [diff] [blame^] | 300 | .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES, |
Roman Tereshonkov | 3760d31 | 2008-03-13 21:35:09 +0200 | [diff] [blame] | 301 | .recalc = &omap3_clkoutx2_recalc, |
| 302 | }; |
| 303 | |
| 304 | /* On DPLL1, unlike other DPLLs, the divider is downstream from CLKOUTX2 */ |
| 305 | static const struct clksel div16_dpll1_x2m2_clksel[] = { |
| 306 | { .parent = &dpll1_x2_ck, .rates = div16_dpll_rates }, |
| 307 | { .parent = NULL } |
| 308 | }; |
| 309 | |
| 310 | /* |
| 311 | * Does not exist in the TRM - needed to separate the M2 divider from |
| 312 | * bypass selection in mpu_ck |
| 313 | */ |
| 314 | static struct clk dpll1_x2m2_ck = { |
| 315 | .name = "dpll1_x2m2_ck", |
Russell King | 5713718 | 2008-11-04 16:48:35 +0000 | [diff] [blame^] | 316 | .ops = &clkops_null, |
Roman Tereshonkov | 3760d31 | 2008-03-13 21:35:09 +0200 | [diff] [blame] | 317 | .parent = &dpll1_x2_ck, |
| 318 | .init = &omap2_init_clksel_parent, |
| 319 | .clksel_reg = OMAP_CM_REGADDR(MPU_MOD, OMAP3430_CM_CLKSEL2_PLL), |
| 320 | .clksel_mask = OMAP3430_MPU_DPLL_CLKOUT_DIV_MASK, |
| 321 | .clksel = div16_dpll1_x2m2_clksel, |
Russell King | 5713718 | 2008-11-04 16:48:35 +0000 | [diff] [blame^] | 322 | .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES, |
Roman Tereshonkov | 3760d31 | 2008-03-13 21:35:09 +0200 | [diff] [blame] | 323 | .recalc = &omap2_clksel_recalc, |
| 324 | }; |
| 325 | |
| 326 | /* DPLL2 */ |
| 327 | /* IVA2 clock source */ |
| 328 | /* Type: DPLL */ |
| 329 | |
Paul Walmsley | 88b8ba9 | 2008-07-03 12:24:46 +0300 | [diff] [blame] | 330 | static struct dpll_data dpll2_dd = { |
Roman Tereshonkov | 3760d31 | 2008-03-13 21:35:09 +0200 | [diff] [blame] | 331 | .mult_div1_reg = OMAP_CM_REGADDR(OMAP3430_IVA2_MOD, OMAP3430_CM_CLKSEL1_PLL), |
| 332 | .mult_mask = OMAP3430_IVA2_DPLL_MULT_MASK, |
| 333 | .div1_mask = OMAP3430_IVA2_DPLL_DIV_MASK, |
| 334 | .control_reg = OMAP_CM_REGADDR(OMAP3430_IVA2_MOD, OMAP3430_CM_CLKEN_PLL), |
| 335 | .enable_mask = OMAP3430_EN_IVA2_DPLL_MASK, |
Paul Walmsley | 542313c | 2008-07-03 12:24:45 +0300 | [diff] [blame] | 336 | .modes = (1 << DPLL_LOW_POWER_STOP) | (1 << DPLL_LOCKED) | |
| 337 | (1 << DPLL_LOW_POWER_BYPASS), |
Roman Tereshonkov | 3760d31 | 2008-03-13 21:35:09 +0200 | [diff] [blame] | 338 | .auto_recal_bit = OMAP3430_EN_IVA2_DPLL_DRIFTGUARD_SHIFT, |
| 339 | .recal_en_bit = OMAP3430_PRM_IRQENABLE_MPU_IVA2_DPLL_RECAL_EN_SHIFT, |
| 340 | .recal_st_bit = OMAP3430_PRM_IRQSTATUS_MPU_IVA2_DPLL_ST_SHIFT, |
Paul Walmsley | 542313c | 2008-07-03 12:24:45 +0300 | [diff] [blame] | 341 | .autoidle_reg = OMAP_CM_REGADDR(OMAP3430_IVA2_MOD, OMAP3430_CM_AUTOIDLE_PLL), |
| 342 | .autoidle_mask = OMAP3430_AUTO_IVA2_DPLL_MASK, |
| 343 | .idlest_reg = OMAP_CM_REGADDR(OMAP3430_IVA2_MOD, OMAP3430_CM_IDLEST_PLL), |
Paul Walmsley | 88b8ba9 | 2008-07-03 12:24:46 +0300 | [diff] [blame] | 344 | .idlest_bit = OMAP3430_ST_IVA2_CLK_SHIFT, |
| 345 | .max_multiplier = OMAP3_MAX_DPLL_MULT, |
| 346 | .max_divider = OMAP3_MAX_DPLL_DIV, |
| 347 | .rate_tolerance = DEFAULT_DPLL_RATE_TOLERANCE |
Roman Tereshonkov | 3760d31 | 2008-03-13 21:35:09 +0200 | [diff] [blame] | 348 | }; |
| 349 | |
| 350 | static struct clk dpll2_ck = { |
| 351 | .name = "dpll2_ck", |
Russell King | 548d849 | 2008-11-04 14:02:46 +0000 | [diff] [blame] | 352 | .ops = &clkops_noncore_dpll_ops, |
Roman Tereshonkov | 3760d31 | 2008-03-13 21:35:09 +0200 | [diff] [blame] | 353 | .parent = &sys_ck, |
| 354 | .dpll_data = &dpll2_dd, |
Paul Walmsley | 542313c | 2008-07-03 12:24:45 +0300 | [diff] [blame] | 355 | .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES, |
Paul Walmsley | 88b8ba9 | 2008-07-03 12:24:46 +0300 | [diff] [blame] | 356 | .round_rate = &omap2_dpll_round_rate, |
Roman Tereshonkov | 3760d31 | 2008-03-13 21:35:09 +0200 | [diff] [blame] | 357 | .recalc = &omap3_dpll_recalc, |
| 358 | }; |
| 359 | |
| 360 | static const struct clksel div16_dpll2_m2x2_clksel[] = { |
| 361 | { .parent = &dpll2_ck, .rates = div16_dpll_rates }, |
| 362 | { .parent = NULL } |
| 363 | }; |
| 364 | |
| 365 | /* |
| 366 | * The TRM is conflicted on whether IVA2 clock comes from DPLL2 CLKOUT |
| 367 | * or CLKOUTX2. CLKOUT seems most plausible. |
| 368 | */ |
| 369 | static struct clk dpll2_m2_ck = { |
| 370 | .name = "dpll2_m2_ck", |
Russell King | 5713718 | 2008-11-04 16:48:35 +0000 | [diff] [blame^] | 371 | .ops = &clkops_null, |
Roman Tereshonkov | 3760d31 | 2008-03-13 21:35:09 +0200 | [diff] [blame] | 372 | .parent = &dpll2_ck, |
| 373 | .init = &omap2_init_clksel_parent, |
| 374 | .clksel_reg = OMAP_CM_REGADDR(OMAP3430_IVA2_MOD, |
| 375 | OMAP3430_CM_CLKSEL2_PLL), |
| 376 | .clksel_mask = OMAP3430_IVA2_DPLL_CLKOUT_DIV_MASK, |
| 377 | .clksel = div16_dpll2_m2x2_clksel, |
Russell King | 5713718 | 2008-11-04 16:48:35 +0000 | [diff] [blame^] | 378 | .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES, |
Roman Tereshonkov | 3760d31 | 2008-03-13 21:35:09 +0200 | [diff] [blame] | 379 | .recalc = &omap2_clksel_recalc, |
| 380 | }; |
| 381 | |
Paul Walmsley | 542313c | 2008-07-03 12:24:45 +0300 | [diff] [blame] | 382 | /* |
| 383 | * DPLL3 |
| 384 | * Source clock for all interfaces and for some device fclks |
| 385 | * REVISIT: Also supports fast relock bypass - not included below |
| 386 | */ |
Paul Walmsley | 88b8ba9 | 2008-07-03 12:24:46 +0300 | [diff] [blame] | 387 | static struct dpll_data dpll3_dd = { |
Roman Tereshonkov | 3760d31 | 2008-03-13 21:35:09 +0200 | [diff] [blame] | 388 | .mult_div1_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL1), |
| 389 | .mult_mask = OMAP3430_CORE_DPLL_MULT_MASK, |
| 390 | .div1_mask = OMAP3430_CORE_DPLL_DIV_MASK, |
| 391 | .control_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN), |
| 392 | .enable_mask = OMAP3430_EN_CORE_DPLL_MASK, |
| 393 | .auto_recal_bit = OMAP3430_EN_CORE_DPLL_DRIFTGUARD_SHIFT, |
| 394 | .recal_en_bit = OMAP3430_CORE_DPLL_RECAL_EN_SHIFT, |
| 395 | .recal_st_bit = OMAP3430_CORE_DPLL_ST_SHIFT, |
Paul Walmsley | 542313c | 2008-07-03 12:24:45 +0300 | [diff] [blame] | 396 | .autoidle_reg = OMAP_CM_REGADDR(PLL_MOD, CM_AUTOIDLE), |
| 397 | .autoidle_mask = OMAP3430_AUTO_CORE_DPLL_MASK, |
Paul Walmsley | 88b8ba9 | 2008-07-03 12:24:46 +0300 | [diff] [blame] | 398 | .max_multiplier = OMAP3_MAX_DPLL_MULT, |
| 399 | .max_divider = OMAP3_MAX_DPLL_DIV, |
| 400 | .rate_tolerance = DEFAULT_DPLL_RATE_TOLERANCE |
Roman Tereshonkov | 3760d31 | 2008-03-13 21:35:09 +0200 | [diff] [blame] | 401 | }; |
| 402 | |
| 403 | static struct clk dpll3_ck = { |
| 404 | .name = "dpll3_ck", |
Russell King | 897dcde | 2008-11-04 16:35:03 +0000 | [diff] [blame] | 405 | .ops = &clkops_null, |
Roman Tereshonkov | 3760d31 | 2008-03-13 21:35:09 +0200 | [diff] [blame] | 406 | .parent = &sys_ck, |
| 407 | .dpll_data = &dpll3_dd, |
Russell King | 897dcde | 2008-11-04 16:35:03 +0000 | [diff] [blame] | 408 | .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES, |
Paul Walmsley | 88b8ba9 | 2008-07-03 12:24:46 +0300 | [diff] [blame] | 409 | .round_rate = &omap2_dpll_round_rate, |
Roman Tereshonkov | 3760d31 | 2008-03-13 21:35:09 +0200 | [diff] [blame] | 410 | .recalc = &omap3_dpll_recalc, |
| 411 | }; |
| 412 | |
| 413 | /* |
| 414 | * This virtual clock provides the CLKOUTX2 output from the DPLL if the |
| 415 | * DPLL isn't bypassed |
| 416 | */ |
| 417 | static struct clk dpll3_x2_ck = { |
| 418 | .name = "dpll3_x2_ck", |
Russell King | 5713718 | 2008-11-04 16:48:35 +0000 | [diff] [blame^] | 419 | .ops = &clkops_null, |
Roman Tereshonkov | 3760d31 | 2008-03-13 21:35:09 +0200 | [diff] [blame] | 420 | .parent = &dpll3_ck, |
Russell King | 5713718 | 2008-11-04 16:48:35 +0000 | [diff] [blame^] | 421 | .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES, |
Roman Tereshonkov | 3760d31 | 2008-03-13 21:35:09 +0200 | [diff] [blame] | 422 | .recalc = &omap3_clkoutx2_recalc, |
| 423 | }; |
| 424 | |
Paul Walmsley | b045d08 | 2008-03-18 11:24:28 +0200 | [diff] [blame] | 425 | static const struct clksel_rate div31_dpll3_rates[] = { |
| 426 | { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE }, |
| 427 | { .div = 2, .val = 2, .flags = RATE_IN_343X }, |
| 428 | { .div = 3, .val = 3, .flags = RATE_IN_3430ES2 }, |
| 429 | { .div = 4, .val = 4, .flags = RATE_IN_3430ES2 }, |
| 430 | { .div = 5, .val = 5, .flags = RATE_IN_3430ES2 }, |
| 431 | { .div = 6, .val = 6, .flags = RATE_IN_3430ES2 }, |
| 432 | { .div = 7, .val = 7, .flags = RATE_IN_3430ES2 }, |
| 433 | { .div = 8, .val = 8, .flags = RATE_IN_3430ES2 }, |
| 434 | { .div = 9, .val = 9, .flags = RATE_IN_3430ES2 }, |
| 435 | { .div = 10, .val = 10, .flags = RATE_IN_3430ES2 }, |
| 436 | { .div = 11, .val = 11, .flags = RATE_IN_3430ES2 }, |
| 437 | { .div = 12, .val = 12, .flags = RATE_IN_3430ES2 }, |
| 438 | { .div = 13, .val = 13, .flags = RATE_IN_3430ES2 }, |
| 439 | { .div = 14, .val = 14, .flags = RATE_IN_3430ES2 }, |
| 440 | { .div = 15, .val = 15, .flags = RATE_IN_3430ES2 }, |
| 441 | { .div = 16, .val = 16, .flags = RATE_IN_3430ES2 }, |
| 442 | { .div = 17, .val = 17, .flags = RATE_IN_3430ES2 }, |
| 443 | { .div = 18, .val = 18, .flags = RATE_IN_3430ES2 }, |
| 444 | { .div = 19, .val = 19, .flags = RATE_IN_3430ES2 }, |
| 445 | { .div = 20, .val = 20, .flags = RATE_IN_3430ES2 }, |
| 446 | { .div = 21, .val = 21, .flags = RATE_IN_3430ES2 }, |
| 447 | { .div = 22, .val = 22, .flags = RATE_IN_3430ES2 }, |
| 448 | { .div = 23, .val = 23, .flags = RATE_IN_3430ES2 }, |
| 449 | { .div = 24, .val = 24, .flags = RATE_IN_3430ES2 }, |
| 450 | { .div = 25, .val = 25, .flags = RATE_IN_3430ES2 }, |
| 451 | { .div = 26, .val = 26, .flags = RATE_IN_3430ES2 }, |
| 452 | { .div = 27, .val = 27, .flags = RATE_IN_3430ES2 }, |
| 453 | { .div = 28, .val = 28, .flags = RATE_IN_3430ES2 }, |
| 454 | { .div = 29, .val = 29, .flags = RATE_IN_3430ES2 }, |
| 455 | { .div = 30, .val = 30, .flags = RATE_IN_3430ES2 }, |
| 456 | { .div = 31, .val = 31, .flags = RATE_IN_3430ES2 }, |
| 457 | { .div = 0 }, |
| 458 | }; |
| 459 | |
| 460 | static const struct clksel div31_dpll3m2_clksel[] = { |
| 461 | { .parent = &dpll3_ck, .rates = div31_dpll3_rates }, |
| 462 | { .parent = NULL } |
| 463 | }; |
| 464 | |
| 465 | /* |
Roman Tereshonkov | 3760d31 | 2008-03-13 21:35:09 +0200 | [diff] [blame] | 466 | * DPLL3 output M2 |
| 467 | * REVISIT: This DPLL output divider must be changed in SRAM, so until |
| 468 | * that code is ready, this should remain a 'read-only' clksel clock. |
Paul Walmsley | b045d08 | 2008-03-18 11:24:28 +0200 | [diff] [blame] | 469 | */ |
| 470 | static struct clk dpll3_m2_ck = { |
| 471 | .name = "dpll3_m2_ck", |
Russell King | 5713718 | 2008-11-04 16:48:35 +0000 | [diff] [blame^] | 472 | .ops = &clkops_null, |
Paul Walmsley | b045d08 | 2008-03-18 11:24:28 +0200 | [diff] [blame] | 473 | .parent = &dpll3_ck, |
| 474 | .init = &omap2_init_clksel_parent, |
| 475 | .clksel_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL1), |
| 476 | .clksel_mask = OMAP3430_CORE_DPLL_CLKOUT_DIV_MASK, |
| 477 | .clksel = div31_dpll3m2_clksel, |
Russell King | 5713718 | 2008-11-04 16:48:35 +0000 | [diff] [blame^] | 478 | .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES, |
Paul Walmsley | b045d08 | 2008-03-18 11:24:28 +0200 | [diff] [blame] | 479 | .recalc = &omap2_clksel_recalc, |
| 480 | }; |
| 481 | |
Roman Tereshonkov | 3760d31 | 2008-03-13 21:35:09 +0200 | [diff] [blame] | 482 | static const struct clksel core_ck_clksel[] = { |
Paul Walmsley | 333943b | 2008-08-19 11:08:45 +0300 | [diff] [blame] | 483 | { .parent = &sys_ck, .rates = dpll_bypass_rates }, |
Roman Tereshonkov | 3760d31 | 2008-03-13 21:35:09 +0200 | [diff] [blame] | 484 | { .parent = &dpll3_m2_ck, .rates = dpll_locked_rates }, |
| 485 | { .parent = NULL } |
Paul Walmsley | b045d08 | 2008-03-18 11:24:28 +0200 | [diff] [blame] | 486 | }; |
| 487 | |
Roman Tereshonkov | 3760d31 | 2008-03-13 21:35:09 +0200 | [diff] [blame] | 488 | static struct clk core_ck = { |
| 489 | .name = "core_ck", |
Russell King | 5713718 | 2008-11-04 16:48:35 +0000 | [diff] [blame^] | 490 | .ops = &clkops_null, |
Roman Tereshonkov | 3760d31 | 2008-03-13 21:35:09 +0200 | [diff] [blame] | 491 | .init = &omap2_init_clksel_parent, |
| 492 | .clksel_reg = OMAP_CM_REGADDR(PLL_MOD, CM_IDLEST), |
Paul Walmsley | 542313c | 2008-07-03 12:24:45 +0300 | [diff] [blame] | 493 | .clksel_mask = OMAP3430_ST_CORE_CLK_MASK, |
Roman Tereshonkov | 3760d31 | 2008-03-13 21:35:09 +0200 | [diff] [blame] | 494 | .clksel = core_ck_clksel, |
Russell King | 5713718 | 2008-11-04 16:48:35 +0000 | [diff] [blame^] | 495 | .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES, |
Roman Tereshonkov | 3760d31 | 2008-03-13 21:35:09 +0200 | [diff] [blame] | 496 | .recalc = &omap2_clksel_recalc, |
| 497 | }; |
| 498 | |
| 499 | static const struct clksel dpll3_m2x2_ck_clksel[] = { |
Paul Walmsley | 333943b | 2008-08-19 11:08:45 +0300 | [diff] [blame] | 500 | { .parent = &sys_ck, .rates = dpll_bypass_rates }, |
Roman Tereshonkov | 3760d31 | 2008-03-13 21:35:09 +0200 | [diff] [blame] | 501 | { .parent = &dpll3_x2_ck, .rates = dpll_locked_rates }, |
| 502 | { .parent = NULL } |
Paul Walmsley | b045d08 | 2008-03-18 11:24:28 +0200 | [diff] [blame] | 503 | }; |
| 504 | |
| 505 | static struct clk dpll3_m2x2_ck = { |
| 506 | .name = "dpll3_m2x2_ck", |
Russell King | 5713718 | 2008-11-04 16:48:35 +0000 | [diff] [blame^] | 507 | .ops = &clkops_null, |
Roman Tereshonkov | 3760d31 | 2008-03-13 21:35:09 +0200 | [diff] [blame] | 508 | .init = &omap2_init_clksel_parent, |
| 509 | .clksel_reg = OMAP_CM_REGADDR(PLL_MOD, CM_IDLEST), |
Paul Walmsley | 542313c | 2008-07-03 12:24:45 +0300 | [diff] [blame] | 510 | .clksel_mask = OMAP3430_ST_CORE_CLK_MASK, |
Roman Tereshonkov | 3760d31 | 2008-03-13 21:35:09 +0200 | [diff] [blame] | 511 | .clksel = dpll3_m2x2_ck_clksel, |
Russell King | 5713718 | 2008-11-04 16:48:35 +0000 | [diff] [blame^] | 512 | .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES, |
Roman Tereshonkov | 3760d31 | 2008-03-13 21:35:09 +0200 | [diff] [blame] | 513 | .recalc = &omap2_clksel_recalc, |
| 514 | }; |
| 515 | |
| 516 | /* The PWRDN bit is apparently only available on 3430ES2 and above */ |
| 517 | static const struct clksel div16_dpll3_clksel[] = { |
| 518 | { .parent = &dpll3_ck, .rates = div16_dpll_rates }, |
| 519 | { .parent = NULL } |
| 520 | }; |
| 521 | |
| 522 | /* This virtual clock is the source for dpll3_m3x2_ck */ |
| 523 | static struct clk dpll3_m3_ck = { |
| 524 | .name = "dpll3_m3_ck", |
Russell King | 5713718 | 2008-11-04 16:48:35 +0000 | [diff] [blame^] | 525 | .ops = &clkops_null, |
Roman Tereshonkov | 3760d31 | 2008-03-13 21:35:09 +0200 | [diff] [blame] | 526 | .parent = &dpll3_ck, |
| 527 | .init = &omap2_init_clksel_parent, |
| 528 | .clksel_reg = OMAP_CM_REGADDR(OMAP3430_EMU_MOD, CM_CLKSEL1), |
| 529 | .clksel_mask = OMAP3430_DIV_DPLL3_MASK, |
| 530 | .clksel = div16_dpll3_clksel, |
Russell King | 5713718 | 2008-11-04 16:48:35 +0000 | [diff] [blame^] | 531 | .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES, |
Roman Tereshonkov | 3760d31 | 2008-03-13 21:35:09 +0200 | [diff] [blame] | 532 | .recalc = &omap2_clksel_recalc, |
Paul Walmsley | b045d08 | 2008-03-18 11:24:28 +0200 | [diff] [blame] | 533 | }; |
| 534 | |
| 535 | /* The PWRDN bit is apparently only available on 3430ES2 and above */ |
| 536 | static struct clk dpll3_m3x2_ck = { |
| 537 | .name = "dpll3_m3x2_ck", |
Roman Tereshonkov | 3760d31 | 2008-03-13 21:35:09 +0200 | [diff] [blame] | 538 | .parent = &dpll3_m3_ck, |
Paul Walmsley | b045d08 | 2008-03-18 11:24:28 +0200 | [diff] [blame] | 539 | .enable_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN), |
| 540 | .enable_bit = OMAP3430_PWRDN_EMU_CORE_SHIFT, |
| 541 | .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES | INVERT_ENABLE, |
Roman Tereshonkov | 3760d31 | 2008-03-13 21:35:09 +0200 | [diff] [blame] | 542 | .recalc = &omap3_clkoutx2_recalc, |
Paul Walmsley | b045d08 | 2008-03-18 11:24:28 +0200 | [diff] [blame] | 543 | }; |
| 544 | |
Roman Tereshonkov | 3760d31 | 2008-03-13 21:35:09 +0200 | [diff] [blame] | 545 | static const struct clksel emu_core_alwon_ck_clksel[] = { |
Paul Walmsley | 333943b | 2008-08-19 11:08:45 +0300 | [diff] [blame] | 546 | { .parent = &sys_ck, .rates = dpll_bypass_rates }, |
Roman Tereshonkov | 3760d31 | 2008-03-13 21:35:09 +0200 | [diff] [blame] | 547 | { .parent = &dpll3_m3x2_ck, .rates = dpll_locked_rates }, |
Paul Walmsley | b045d08 | 2008-03-18 11:24:28 +0200 | [diff] [blame] | 548 | { .parent = NULL } |
| 549 | }; |
| 550 | |
| 551 | static struct clk emu_core_alwon_ck = { |
| 552 | .name = "emu_core_alwon_ck", |
Russell King | 5713718 | 2008-11-04 16:48:35 +0000 | [diff] [blame^] | 553 | .ops = &clkops_null, |
Roman Tereshonkov | 3760d31 | 2008-03-13 21:35:09 +0200 | [diff] [blame] | 554 | .parent = &dpll3_m3x2_ck, |
Paul Walmsley | b045d08 | 2008-03-18 11:24:28 +0200 | [diff] [blame] | 555 | .init = &omap2_init_clksel_parent, |
Roman Tereshonkov | 3760d31 | 2008-03-13 21:35:09 +0200 | [diff] [blame] | 556 | .clksel_reg = OMAP_CM_REGADDR(PLL_MOD, CM_IDLEST), |
Paul Walmsley | 542313c | 2008-07-03 12:24:45 +0300 | [diff] [blame] | 557 | .clksel_mask = OMAP3430_ST_CORE_CLK_MASK, |
Roman Tereshonkov | 3760d31 | 2008-03-13 21:35:09 +0200 | [diff] [blame] | 558 | .clksel = emu_core_alwon_ck_clksel, |
Russell King | 5713718 | 2008-11-04 16:48:35 +0000 | [diff] [blame^] | 559 | .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES, |
Roman Tereshonkov | 3760d31 | 2008-03-13 21:35:09 +0200 | [diff] [blame] | 560 | .recalc = &omap2_clksel_recalc, |
Paul Walmsley | b045d08 | 2008-03-18 11:24:28 +0200 | [diff] [blame] | 561 | }; |
| 562 | |
| 563 | /* DPLL4 */ |
| 564 | /* Supplies 96MHz, 54Mhz TV DAC, DSS fclk, CAM sensor clock, emul trace clk */ |
| 565 | /* Type: DPLL */ |
Paul Walmsley | 88b8ba9 | 2008-07-03 12:24:46 +0300 | [diff] [blame] | 566 | static struct dpll_data dpll4_dd = { |
Paul Walmsley | b045d08 | 2008-03-18 11:24:28 +0200 | [diff] [blame] | 567 | .mult_div1_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL2), |
| 568 | .mult_mask = OMAP3430_PERIPH_DPLL_MULT_MASK, |
| 569 | .div1_mask = OMAP3430_PERIPH_DPLL_DIV_MASK, |
| 570 | .control_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN), |
| 571 | .enable_mask = OMAP3430_EN_PERIPH_DPLL_MASK, |
Paul Walmsley | 542313c | 2008-07-03 12:24:45 +0300 | [diff] [blame] | 572 | .modes = (1 << DPLL_LOW_POWER_STOP) | (1 << DPLL_LOCKED), |
Paul Walmsley | b045d08 | 2008-03-18 11:24:28 +0200 | [diff] [blame] | 573 | .auto_recal_bit = OMAP3430_EN_PERIPH_DPLL_DRIFTGUARD_SHIFT, |
| 574 | .recal_en_bit = OMAP3430_PERIPH_DPLL_RECAL_EN_SHIFT, |
| 575 | .recal_st_bit = OMAP3430_PERIPH_DPLL_ST_SHIFT, |
Paul Walmsley | 542313c | 2008-07-03 12:24:45 +0300 | [diff] [blame] | 576 | .autoidle_reg = OMAP_CM_REGADDR(PLL_MOD, CM_AUTOIDLE), |
| 577 | .autoidle_mask = OMAP3430_AUTO_PERIPH_DPLL_MASK, |
| 578 | .idlest_reg = OMAP_CM_REGADDR(PLL_MOD, CM_IDLEST), |
| 579 | .idlest_bit = OMAP3430_ST_PERIPH_CLK_SHIFT, |
Paul Walmsley | 88b8ba9 | 2008-07-03 12:24:46 +0300 | [diff] [blame] | 580 | .max_multiplier = OMAP3_MAX_DPLL_MULT, |
| 581 | .max_divider = OMAP3_MAX_DPLL_DIV, |
| 582 | .rate_tolerance = DEFAULT_DPLL_RATE_TOLERANCE |
Paul Walmsley | b045d08 | 2008-03-18 11:24:28 +0200 | [diff] [blame] | 583 | }; |
| 584 | |
| 585 | static struct clk dpll4_ck = { |
| 586 | .name = "dpll4_ck", |
Russell King | 548d849 | 2008-11-04 14:02:46 +0000 | [diff] [blame] | 587 | .ops = &clkops_noncore_dpll_ops, |
Paul Walmsley | b045d08 | 2008-03-18 11:24:28 +0200 | [diff] [blame] | 588 | .parent = &sys_ck, |
| 589 | .dpll_data = &dpll4_dd, |
Paul Walmsley | 542313c | 2008-07-03 12:24:45 +0300 | [diff] [blame] | 590 | .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES, |
Paul Walmsley | 88b8ba9 | 2008-07-03 12:24:46 +0300 | [diff] [blame] | 591 | .round_rate = &omap2_dpll_round_rate, |
Paul Walmsley | b045d08 | 2008-03-18 11:24:28 +0200 | [diff] [blame] | 592 | .recalc = &omap3_dpll_recalc, |
| 593 | }; |
| 594 | |
| 595 | /* |
| 596 | * This virtual clock provides the CLKOUTX2 output from the DPLL if the |
Roman Tereshonkov | 3760d31 | 2008-03-13 21:35:09 +0200 | [diff] [blame] | 597 | * DPLL isn't bypassed -- |
| 598 | * XXX does this serve any downstream clocks? |
Paul Walmsley | b045d08 | 2008-03-18 11:24:28 +0200 | [diff] [blame] | 599 | */ |
| 600 | static struct clk dpll4_x2_ck = { |
| 601 | .name = "dpll4_x2_ck", |
Russell King | 5713718 | 2008-11-04 16:48:35 +0000 | [diff] [blame^] | 602 | .ops = &clkops_null, |
Paul Walmsley | b045d08 | 2008-03-18 11:24:28 +0200 | [diff] [blame] | 603 | .parent = &dpll4_ck, |
Russell King | 5713718 | 2008-11-04 16:48:35 +0000 | [diff] [blame^] | 604 | .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES, |
Paul Walmsley | b045d08 | 2008-03-18 11:24:28 +0200 | [diff] [blame] | 605 | .recalc = &omap3_clkoutx2_recalc, |
| 606 | }; |
| 607 | |
| 608 | static const struct clksel div16_dpll4_clksel[] = { |
Roman Tereshonkov | 3760d31 | 2008-03-13 21:35:09 +0200 | [diff] [blame] | 609 | { .parent = &dpll4_ck, .rates = div16_dpll_rates }, |
Paul Walmsley | b045d08 | 2008-03-18 11:24:28 +0200 | [diff] [blame] | 610 | { .parent = NULL } |
| 611 | }; |
| 612 | |
Roman Tereshonkov | 3760d31 | 2008-03-13 21:35:09 +0200 | [diff] [blame] | 613 | /* This virtual clock is the source for dpll4_m2x2_ck */ |
| 614 | static struct clk dpll4_m2_ck = { |
| 615 | .name = "dpll4_m2_ck", |
Russell King | 5713718 | 2008-11-04 16:48:35 +0000 | [diff] [blame^] | 616 | .ops = &clkops_null, |
Roman Tereshonkov | 3760d31 | 2008-03-13 21:35:09 +0200 | [diff] [blame] | 617 | .parent = &dpll4_ck, |
| 618 | .init = &omap2_init_clksel_parent, |
| 619 | .clksel_reg = OMAP_CM_REGADDR(PLL_MOD, OMAP3430_CM_CLKSEL3), |
| 620 | .clksel_mask = OMAP3430_DIV_96M_MASK, |
| 621 | .clksel = div16_dpll4_clksel, |
Russell King | 5713718 | 2008-11-04 16:48:35 +0000 | [diff] [blame^] | 622 | .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES, |
Roman Tereshonkov | 3760d31 | 2008-03-13 21:35:09 +0200 | [diff] [blame] | 623 | .recalc = &omap2_clksel_recalc, |
| 624 | }; |
| 625 | |
Paul Walmsley | b045d08 | 2008-03-18 11:24:28 +0200 | [diff] [blame] | 626 | /* The PWRDN bit is apparently only available on 3430ES2 and above */ |
| 627 | static struct clk dpll4_m2x2_ck = { |
| 628 | .name = "dpll4_m2x2_ck", |
Roman Tereshonkov | 3760d31 | 2008-03-13 21:35:09 +0200 | [diff] [blame] | 629 | .parent = &dpll4_m2_ck, |
Paul Walmsley | b045d08 | 2008-03-18 11:24:28 +0200 | [diff] [blame] | 630 | .enable_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN), |
| 631 | .enable_bit = OMAP3430_PWRDN_96M_SHIFT, |
Paul Walmsley | b045d08 | 2008-03-18 11:24:28 +0200 | [diff] [blame] | 632 | .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES | INVERT_ENABLE, |
Roman Tereshonkov | 3760d31 | 2008-03-13 21:35:09 +0200 | [diff] [blame] | 633 | .recalc = &omap3_clkoutx2_recalc, |
| 634 | }; |
| 635 | |
| 636 | static const struct clksel omap_96m_alwon_fck_clksel[] = { |
Paul Walmsley | 333943b | 2008-08-19 11:08:45 +0300 | [diff] [blame] | 637 | { .parent = &sys_ck, .rates = dpll_bypass_rates }, |
Roman Tereshonkov | 3760d31 | 2008-03-13 21:35:09 +0200 | [diff] [blame] | 638 | { .parent = &dpll4_m2x2_ck, .rates = dpll_locked_rates }, |
| 639 | { .parent = NULL } |
Paul Walmsley | b045d08 | 2008-03-18 11:24:28 +0200 | [diff] [blame] | 640 | }; |
| 641 | |
| 642 | static struct clk omap_96m_alwon_fck = { |
| 643 | .name = "omap_96m_alwon_fck", |
Russell King | 5713718 | 2008-11-04 16:48:35 +0000 | [diff] [blame^] | 644 | .ops = &clkops_null, |
Paul Walmsley | b045d08 | 2008-03-18 11:24:28 +0200 | [diff] [blame] | 645 | .parent = &dpll4_m2x2_ck, |
Roman Tereshonkov | 3760d31 | 2008-03-13 21:35:09 +0200 | [diff] [blame] | 646 | .init = &omap2_init_clksel_parent, |
| 647 | .clksel_reg = OMAP_CM_REGADDR(PLL_MOD, CM_IDLEST), |
Paul Walmsley | 542313c | 2008-07-03 12:24:45 +0300 | [diff] [blame] | 648 | .clksel_mask = OMAP3430_ST_PERIPH_CLK_MASK, |
Roman Tereshonkov | 3760d31 | 2008-03-13 21:35:09 +0200 | [diff] [blame] | 649 | .clksel = omap_96m_alwon_fck_clksel, |
Russell King | 5713718 | 2008-11-04 16:48:35 +0000 | [diff] [blame^] | 650 | .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES, |
Roman Tereshonkov | 3760d31 | 2008-03-13 21:35:09 +0200 | [diff] [blame] | 651 | .recalc = &omap2_clksel_recalc, |
Paul Walmsley | b045d08 | 2008-03-18 11:24:28 +0200 | [diff] [blame] | 652 | }; |
| 653 | |
| 654 | static struct clk omap_96m_fck = { |
| 655 | .name = "omap_96m_fck", |
Russell King | 5713718 | 2008-11-04 16:48:35 +0000 | [diff] [blame^] | 656 | .ops = &clkops_null, |
Paul Walmsley | b045d08 | 2008-03-18 11:24:28 +0200 | [diff] [blame] | 657 | .parent = &omap_96m_alwon_fck, |
Russell King | 5713718 | 2008-11-04 16:48:35 +0000 | [diff] [blame^] | 658 | .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES, |
Paul Walmsley | b045d08 | 2008-03-18 11:24:28 +0200 | [diff] [blame] | 659 | .recalc = &followparent_recalc, |
| 660 | }; |
| 661 | |
Roman Tereshonkov | 3760d31 | 2008-03-13 21:35:09 +0200 | [diff] [blame] | 662 | static const struct clksel cm_96m_fck_clksel[] = { |
Paul Walmsley | 333943b | 2008-08-19 11:08:45 +0300 | [diff] [blame] | 663 | { .parent = &sys_ck, .rates = dpll_bypass_rates }, |
Roman Tereshonkov | 3760d31 | 2008-03-13 21:35:09 +0200 | [diff] [blame] | 664 | { .parent = &dpll4_m2x2_ck, .rates = dpll_locked_rates }, |
| 665 | { .parent = NULL } |
| 666 | }; |
| 667 | |
Paul Walmsley | b045d08 | 2008-03-18 11:24:28 +0200 | [diff] [blame] | 668 | static struct clk cm_96m_fck = { |
| 669 | .name = "cm_96m_fck", |
Russell King | 5713718 | 2008-11-04 16:48:35 +0000 | [diff] [blame^] | 670 | .ops = &clkops_null, |
Paul Walmsley | b045d08 | 2008-03-18 11:24:28 +0200 | [diff] [blame] | 671 | .parent = &dpll4_m2x2_ck, |
Roman Tereshonkov | 3760d31 | 2008-03-13 21:35:09 +0200 | [diff] [blame] | 672 | .init = &omap2_init_clksel_parent, |
| 673 | .clksel_reg = OMAP_CM_REGADDR(PLL_MOD, CM_IDLEST), |
Paul Walmsley | 542313c | 2008-07-03 12:24:45 +0300 | [diff] [blame] | 674 | .clksel_mask = OMAP3430_ST_PERIPH_CLK_MASK, |
Roman Tereshonkov | 3760d31 | 2008-03-13 21:35:09 +0200 | [diff] [blame] | 675 | .clksel = cm_96m_fck_clksel, |
Russell King | 5713718 | 2008-11-04 16:48:35 +0000 | [diff] [blame^] | 676 | .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES, |
Roman Tereshonkov | 3760d31 | 2008-03-13 21:35:09 +0200 | [diff] [blame] | 677 | .recalc = &omap2_clksel_recalc, |
| 678 | }; |
| 679 | |
| 680 | /* This virtual clock is the source for dpll4_m3x2_ck */ |
| 681 | static struct clk dpll4_m3_ck = { |
| 682 | .name = "dpll4_m3_ck", |
Russell King | 5713718 | 2008-11-04 16:48:35 +0000 | [diff] [blame^] | 683 | .ops = &clkops_null, |
Roman Tereshonkov | 3760d31 | 2008-03-13 21:35:09 +0200 | [diff] [blame] | 684 | .parent = &dpll4_ck, |
| 685 | .init = &omap2_init_clksel_parent, |
| 686 | .clksel_reg = OMAP_CM_REGADDR(OMAP3430_DSS_MOD, CM_CLKSEL), |
| 687 | .clksel_mask = OMAP3430_CLKSEL_TV_MASK, |
| 688 | .clksel = div16_dpll4_clksel, |
Russell King | 5713718 | 2008-11-04 16:48:35 +0000 | [diff] [blame^] | 689 | .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES, |
Roman Tereshonkov | 3760d31 | 2008-03-13 21:35:09 +0200 | [diff] [blame] | 690 | .recalc = &omap2_clksel_recalc, |
Paul Walmsley | b045d08 | 2008-03-18 11:24:28 +0200 | [diff] [blame] | 691 | }; |
| 692 | |
| 693 | /* The PWRDN bit is apparently only available on 3430ES2 and above */ |
| 694 | static struct clk dpll4_m3x2_ck = { |
| 695 | .name = "dpll4_m3x2_ck", |
Roman Tereshonkov | 3760d31 | 2008-03-13 21:35:09 +0200 | [diff] [blame] | 696 | .parent = &dpll4_m3_ck, |
Paul Walmsley | b045d08 | 2008-03-18 11:24:28 +0200 | [diff] [blame] | 697 | .init = &omap2_init_clksel_parent, |
| 698 | .enable_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN), |
| 699 | .enable_bit = OMAP3430_PWRDN_TV_SHIFT, |
Paul Walmsley | b045d08 | 2008-03-18 11:24:28 +0200 | [diff] [blame] | 700 | .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES | INVERT_ENABLE, |
Roman Tereshonkov | 3760d31 | 2008-03-13 21:35:09 +0200 | [diff] [blame] | 701 | .recalc = &omap3_clkoutx2_recalc, |
| 702 | }; |
| 703 | |
| 704 | static const struct clksel virt_omap_54m_fck_clksel[] = { |
Paul Walmsley | 333943b | 2008-08-19 11:08:45 +0300 | [diff] [blame] | 705 | { .parent = &sys_ck, .rates = dpll_bypass_rates }, |
Roman Tereshonkov | 3760d31 | 2008-03-13 21:35:09 +0200 | [diff] [blame] | 706 | { .parent = &dpll4_m3x2_ck, .rates = dpll_locked_rates }, |
| 707 | { .parent = NULL } |
| 708 | }; |
| 709 | |
| 710 | static struct clk virt_omap_54m_fck = { |
| 711 | .name = "virt_omap_54m_fck", |
Russell King | 5713718 | 2008-11-04 16:48:35 +0000 | [diff] [blame^] | 712 | .ops = &clkops_null, |
Roman Tereshonkov | 3760d31 | 2008-03-13 21:35:09 +0200 | [diff] [blame] | 713 | .parent = &dpll4_m3x2_ck, |
| 714 | .init = &omap2_init_clksel_parent, |
| 715 | .clksel_reg = OMAP_CM_REGADDR(PLL_MOD, CM_IDLEST), |
Paul Walmsley | 542313c | 2008-07-03 12:24:45 +0300 | [diff] [blame] | 716 | .clksel_mask = OMAP3430_ST_PERIPH_CLK_MASK, |
Roman Tereshonkov | 3760d31 | 2008-03-13 21:35:09 +0200 | [diff] [blame] | 717 | .clksel = virt_omap_54m_fck_clksel, |
Russell King | 5713718 | 2008-11-04 16:48:35 +0000 | [diff] [blame^] | 718 | .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES, |
Paul Walmsley | b045d08 | 2008-03-18 11:24:28 +0200 | [diff] [blame] | 719 | .recalc = &omap2_clksel_recalc, |
| 720 | }; |
| 721 | |
| 722 | static const struct clksel_rate omap_54m_d4m3x2_rates[] = { |
| 723 | { .div = 1, .val = 0, .flags = RATE_IN_343X | DEFAULT_RATE }, |
| 724 | { .div = 0 } |
| 725 | }; |
| 726 | |
| 727 | static const struct clksel_rate omap_54m_alt_rates[] = { |
| 728 | { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE }, |
| 729 | { .div = 0 } |
| 730 | }; |
| 731 | |
| 732 | static const struct clksel omap_54m_clksel[] = { |
Roman Tereshonkov | 3760d31 | 2008-03-13 21:35:09 +0200 | [diff] [blame] | 733 | { .parent = &virt_omap_54m_fck, .rates = omap_54m_d4m3x2_rates }, |
Paul Walmsley | b045d08 | 2008-03-18 11:24:28 +0200 | [diff] [blame] | 734 | { .parent = &sys_altclk, .rates = omap_54m_alt_rates }, |
| 735 | { .parent = NULL } |
| 736 | }; |
| 737 | |
| 738 | static struct clk omap_54m_fck = { |
| 739 | .name = "omap_54m_fck", |
Russell King | 5713718 | 2008-11-04 16:48:35 +0000 | [diff] [blame^] | 740 | .ops = &clkops_null, |
Paul Walmsley | b045d08 | 2008-03-18 11:24:28 +0200 | [diff] [blame] | 741 | .init = &omap2_init_clksel_parent, |
| 742 | .clksel_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL1), |
| 743 | .clksel_mask = OMAP3430_SOURCE_54M, |
| 744 | .clksel = omap_54m_clksel, |
Russell King | 5713718 | 2008-11-04 16:48:35 +0000 | [diff] [blame^] | 745 | .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES, |
Paul Walmsley | b045d08 | 2008-03-18 11:24:28 +0200 | [diff] [blame] | 746 | .recalc = &omap2_clksel_recalc, |
| 747 | }; |
| 748 | |
| 749 | static const struct clksel_rate omap_48m_96md2_rates[] = { |
| 750 | { .div = 2, .val = 0, .flags = RATE_IN_343X | DEFAULT_RATE }, |
| 751 | { .div = 0 } |
| 752 | }; |
| 753 | |
| 754 | static const struct clksel_rate omap_48m_alt_rates[] = { |
| 755 | { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE }, |
| 756 | { .div = 0 } |
| 757 | }; |
| 758 | |
| 759 | static const struct clksel omap_48m_clksel[] = { |
| 760 | { .parent = &cm_96m_fck, .rates = omap_48m_96md2_rates }, |
| 761 | { .parent = &sys_altclk, .rates = omap_48m_alt_rates }, |
| 762 | { .parent = NULL } |
| 763 | }; |
| 764 | |
| 765 | static struct clk omap_48m_fck = { |
| 766 | .name = "omap_48m_fck", |
Russell King | 5713718 | 2008-11-04 16:48:35 +0000 | [diff] [blame^] | 767 | .ops = &clkops_null, |
Paul Walmsley | b045d08 | 2008-03-18 11:24:28 +0200 | [diff] [blame] | 768 | .init = &omap2_init_clksel_parent, |
| 769 | .clksel_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL1), |
| 770 | .clksel_mask = OMAP3430_SOURCE_48M, |
| 771 | .clksel = omap_48m_clksel, |
Russell King | 5713718 | 2008-11-04 16:48:35 +0000 | [diff] [blame^] | 772 | .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES, |
Paul Walmsley | b045d08 | 2008-03-18 11:24:28 +0200 | [diff] [blame] | 773 | .recalc = &omap2_clksel_recalc, |
| 774 | }; |
| 775 | |
| 776 | static struct clk omap_12m_fck = { |
| 777 | .name = "omap_12m_fck", |
Russell King | 5713718 | 2008-11-04 16:48:35 +0000 | [diff] [blame^] | 778 | .ops = &clkops_null, |
Paul Walmsley | b045d08 | 2008-03-18 11:24:28 +0200 | [diff] [blame] | 779 | .parent = &omap_48m_fck, |
| 780 | .fixed_div = 4, |
Russell King | 5713718 | 2008-11-04 16:48:35 +0000 | [diff] [blame^] | 781 | .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES, |
Paul Walmsley | b045d08 | 2008-03-18 11:24:28 +0200 | [diff] [blame] | 782 | .recalc = &omap2_fixed_divisor_recalc, |
| 783 | }; |
| 784 | |
Roman Tereshonkov | 3760d31 | 2008-03-13 21:35:09 +0200 | [diff] [blame] | 785 | /* This virstual clock is the source for dpll4_m4x2_ck */ |
| 786 | static struct clk dpll4_m4_ck = { |
| 787 | .name = "dpll4_m4_ck", |
Russell King | 5713718 | 2008-11-04 16:48:35 +0000 | [diff] [blame^] | 788 | .ops = &clkops_null, |
Roman Tereshonkov | 3760d31 | 2008-03-13 21:35:09 +0200 | [diff] [blame] | 789 | .parent = &dpll4_ck, |
Paul Walmsley | b045d08 | 2008-03-18 11:24:28 +0200 | [diff] [blame] | 790 | .init = &omap2_init_clksel_parent, |
Paul Walmsley | b045d08 | 2008-03-18 11:24:28 +0200 | [diff] [blame] | 791 | .clksel_reg = OMAP_CM_REGADDR(OMAP3430_DSS_MOD, CM_CLKSEL), |
| 792 | .clksel_mask = OMAP3430_CLKSEL_DSS1_MASK, |
| 793 | .clksel = div16_dpll4_clksel, |
Russell King | 5713718 | 2008-11-04 16:48:35 +0000 | [diff] [blame^] | 794 | .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES, |
Roman Tereshonkov | 3760d31 | 2008-03-13 21:35:09 +0200 | [diff] [blame] | 795 | .recalc = &omap2_clksel_recalc, |
| 796 | }; |
| 797 | |
| 798 | /* The PWRDN bit is apparently only available on 3430ES2 and above */ |
| 799 | static struct clk dpll4_m4x2_ck = { |
| 800 | .name = "dpll4_m4x2_ck", |
| 801 | .parent = &dpll4_m4_ck, |
| 802 | .enable_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN), |
| 803 | .enable_bit = OMAP3430_PWRDN_CAM_SHIFT, |
Paul Walmsley | b045d08 | 2008-03-18 11:24:28 +0200 | [diff] [blame] | 804 | .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES | INVERT_ENABLE, |
Roman Tereshonkov | 3760d31 | 2008-03-13 21:35:09 +0200 | [diff] [blame] | 805 | .recalc = &omap3_clkoutx2_recalc, |
| 806 | }; |
| 807 | |
| 808 | /* This virtual clock is the source for dpll4_m5x2_ck */ |
| 809 | static struct clk dpll4_m5_ck = { |
| 810 | .name = "dpll4_m5_ck", |
Russell King | 5713718 | 2008-11-04 16:48:35 +0000 | [diff] [blame^] | 811 | .ops = &clkops_null, |
Roman Tereshonkov | 3760d31 | 2008-03-13 21:35:09 +0200 | [diff] [blame] | 812 | .parent = &dpll4_ck, |
| 813 | .init = &omap2_init_clksel_parent, |
| 814 | .clksel_reg = OMAP_CM_REGADDR(OMAP3430_CAM_MOD, CM_CLKSEL), |
| 815 | .clksel_mask = OMAP3430_CLKSEL_CAM_MASK, |
| 816 | .clksel = div16_dpll4_clksel, |
Russell King | 5713718 | 2008-11-04 16:48:35 +0000 | [diff] [blame^] | 817 | .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES, |
Paul Walmsley | b045d08 | 2008-03-18 11:24:28 +0200 | [diff] [blame] | 818 | .recalc = &omap2_clksel_recalc, |
| 819 | }; |
| 820 | |
| 821 | /* The PWRDN bit is apparently only available on 3430ES2 and above */ |
| 822 | static struct clk dpll4_m5x2_ck = { |
| 823 | .name = "dpll4_m5x2_ck", |
Roman Tereshonkov | 3760d31 | 2008-03-13 21:35:09 +0200 | [diff] [blame] | 824 | .parent = &dpll4_m5_ck, |
Paul Walmsley | b045d08 | 2008-03-18 11:24:28 +0200 | [diff] [blame] | 825 | .enable_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN), |
| 826 | .enable_bit = OMAP3430_PWRDN_CAM_SHIFT, |
Paul Walmsley | b045d08 | 2008-03-18 11:24:28 +0200 | [diff] [blame] | 827 | .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES | INVERT_ENABLE, |
Roman Tereshonkov | 3760d31 | 2008-03-13 21:35:09 +0200 | [diff] [blame] | 828 | .recalc = &omap3_clkoutx2_recalc, |
| 829 | }; |
| 830 | |
| 831 | /* This virtual clock is the source for dpll4_m6x2_ck */ |
| 832 | static struct clk dpll4_m6_ck = { |
| 833 | .name = "dpll4_m6_ck", |
Russell King | 5713718 | 2008-11-04 16:48:35 +0000 | [diff] [blame^] | 834 | .ops = &clkops_null, |
Roman Tereshonkov | 3760d31 | 2008-03-13 21:35:09 +0200 | [diff] [blame] | 835 | .parent = &dpll4_ck, |
| 836 | .init = &omap2_init_clksel_parent, |
| 837 | .clksel_reg = OMAP_CM_REGADDR(OMAP3430_EMU_MOD, CM_CLKSEL1), |
| 838 | .clksel_mask = OMAP3430_DIV_DPLL4_MASK, |
| 839 | .clksel = div16_dpll4_clksel, |
Russell King | 5713718 | 2008-11-04 16:48:35 +0000 | [diff] [blame^] | 840 | .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES, |
Paul Walmsley | b045d08 | 2008-03-18 11:24:28 +0200 | [diff] [blame] | 841 | .recalc = &omap2_clksel_recalc, |
| 842 | }; |
| 843 | |
| 844 | /* The PWRDN bit is apparently only available on 3430ES2 and above */ |
| 845 | static struct clk dpll4_m6x2_ck = { |
| 846 | .name = "dpll4_m6x2_ck", |
Roman Tereshonkov | 3760d31 | 2008-03-13 21:35:09 +0200 | [diff] [blame] | 847 | .parent = &dpll4_m6_ck, |
Paul Walmsley | b045d08 | 2008-03-18 11:24:28 +0200 | [diff] [blame] | 848 | .init = &omap2_init_clksel_parent, |
| 849 | .enable_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN), |
| 850 | .enable_bit = OMAP3430_PWRDN_EMU_PERIPH_SHIFT, |
Paul Walmsley | b045d08 | 2008-03-18 11:24:28 +0200 | [diff] [blame] | 851 | .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES | INVERT_ENABLE, |
Roman Tereshonkov | 3760d31 | 2008-03-13 21:35:09 +0200 | [diff] [blame] | 852 | .recalc = &omap3_clkoutx2_recalc, |
Paul Walmsley | b045d08 | 2008-03-18 11:24:28 +0200 | [diff] [blame] | 853 | }; |
| 854 | |
| 855 | static struct clk emu_per_alwon_ck = { |
| 856 | .name = "emu_per_alwon_ck", |
Russell King | 5713718 | 2008-11-04 16:48:35 +0000 | [diff] [blame^] | 857 | .ops = &clkops_null, |
Paul Walmsley | b045d08 | 2008-03-18 11:24:28 +0200 | [diff] [blame] | 858 | .parent = &dpll4_m6x2_ck, |
Russell King | 5713718 | 2008-11-04 16:48:35 +0000 | [diff] [blame^] | 859 | .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES, |
Paul Walmsley | b045d08 | 2008-03-18 11:24:28 +0200 | [diff] [blame] | 860 | .recalc = &followparent_recalc, |
| 861 | }; |
| 862 | |
| 863 | /* DPLL5 */ |
| 864 | /* Supplies 120MHz clock, USIM source clock */ |
| 865 | /* Type: DPLL */ |
| 866 | /* 3430ES2 only */ |
Paul Walmsley | 88b8ba9 | 2008-07-03 12:24:46 +0300 | [diff] [blame] | 867 | static struct dpll_data dpll5_dd = { |
Paul Walmsley | b045d08 | 2008-03-18 11:24:28 +0200 | [diff] [blame] | 868 | .mult_div1_reg = OMAP_CM_REGADDR(PLL_MOD, OMAP3430ES2_CM_CLKSEL4), |
| 869 | .mult_mask = OMAP3430ES2_PERIPH2_DPLL_MULT_MASK, |
| 870 | .div1_mask = OMAP3430ES2_PERIPH2_DPLL_DIV_MASK, |
| 871 | .control_reg = OMAP_CM_REGADDR(PLL_MOD, OMAP3430ES2_CM_CLKEN2), |
| 872 | .enable_mask = OMAP3430ES2_EN_PERIPH2_DPLL_MASK, |
Paul Walmsley | 542313c | 2008-07-03 12:24:45 +0300 | [diff] [blame] | 873 | .modes = (1 << DPLL_LOW_POWER_STOP) | (1 << DPLL_LOCKED), |
Paul Walmsley | b045d08 | 2008-03-18 11:24:28 +0200 | [diff] [blame] | 874 | .auto_recal_bit = OMAP3430ES2_EN_PERIPH2_DPLL_DRIFTGUARD_SHIFT, |
| 875 | .recal_en_bit = OMAP3430ES2_SND_PERIPH_DPLL_RECAL_EN_SHIFT, |
| 876 | .recal_st_bit = OMAP3430ES2_SND_PERIPH_DPLL_ST_SHIFT, |
Paul Walmsley | 542313c | 2008-07-03 12:24:45 +0300 | [diff] [blame] | 877 | .autoidle_reg = OMAP_CM_REGADDR(PLL_MOD, OMAP3430ES2_CM_AUTOIDLE2_PLL), |
| 878 | .autoidle_mask = OMAP3430ES2_AUTO_PERIPH2_DPLL_MASK, |
| 879 | .idlest_reg = OMAP_CM_REGADDR(PLL_MOD, CM_IDLEST2), |
| 880 | .idlest_bit = OMAP3430ES2_ST_PERIPH2_CLK_SHIFT, |
Paul Walmsley | 88b8ba9 | 2008-07-03 12:24:46 +0300 | [diff] [blame] | 881 | .max_multiplier = OMAP3_MAX_DPLL_MULT, |
| 882 | .max_divider = OMAP3_MAX_DPLL_DIV, |
| 883 | .rate_tolerance = DEFAULT_DPLL_RATE_TOLERANCE |
Paul Walmsley | b045d08 | 2008-03-18 11:24:28 +0200 | [diff] [blame] | 884 | }; |
| 885 | |
| 886 | static struct clk dpll5_ck = { |
| 887 | .name = "dpll5_ck", |
Russell King | 548d849 | 2008-11-04 14:02:46 +0000 | [diff] [blame] | 888 | .ops = &clkops_noncore_dpll_ops, |
Paul Walmsley | b045d08 | 2008-03-18 11:24:28 +0200 | [diff] [blame] | 889 | .parent = &sys_ck, |
| 890 | .dpll_data = &dpll5_dd, |
Paul Walmsley | 542313c | 2008-07-03 12:24:45 +0300 | [diff] [blame] | 891 | .flags = CLOCK_IN_OMAP3430ES2 | RATE_PROPAGATES, |
Paul Walmsley | 88b8ba9 | 2008-07-03 12:24:46 +0300 | [diff] [blame] | 892 | .round_rate = &omap2_dpll_round_rate, |
Paul Walmsley | b045d08 | 2008-03-18 11:24:28 +0200 | [diff] [blame] | 893 | .recalc = &omap3_dpll_recalc, |
| 894 | }; |
| 895 | |
Roman Tereshonkov | 3760d31 | 2008-03-13 21:35:09 +0200 | [diff] [blame] | 896 | static const struct clksel div16_dpll5_clksel[] = { |
Paul Walmsley | b045d08 | 2008-03-18 11:24:28 +0200 | [diff] [blame] | 897 | { .parent = &dpll5_ck, .rates = div16_dpll_rates }, |
| 898 | { .parent = NULL } |
| 899 | }; |
| 900 | |
| 901 | static struct clk dpll5_m2_ck = { |
| 902 | .name = "dpll5_m2_ck", |
Russell King | 5713718 | 2008-11-04 16:48:35 +0000 | [diff] [blame^] | 903 | .ops = &clkops_null, |
Paul Walmsley | b045d08 | 2008-03-18 11:24:28 +0200 | [diff] [blame] | 904 | .parent = &dpll5_ck, |
| 905 | .init = &omap2_init_clksel_parent, |
| 906 | .clksel_reg = OMAP_CM_REGADDR(PLL_MOD, OMAP3430ES2_CM_CLKSEL5), |
| 907 | .clksel_mask = OMAP3430ES2_DIV_120M_MASK, |
Roman Tereshonkov | 3760d31 | 2008-03-13 21:35:09 +0200 | [diff] [blame] | 908 | .clksel = div16_dpll5_clksel, |
Russell King | 5713718 | 2008-11-04 16:48:35 +0000 | [diff] [blame^] | 909 | .flags = CLOCK_IN_OMAP3430ES2 | RATE_PROPAGATES, |
Paul Walmsley | b045d08 | 2008-03-18 11:24:28 +0200 | [diff] [blame] | 910 | .recalc = &omap2_clksel_recalc, |
| 911 | }; |
| 912 | |
Roman Tereshonkov | 3760d31 | 2008-03-13 21:35:09 +0200 | [diff] [blame] | 913 | static const struct clksel omap_120m_fck_clksel[] = { |
Paul Walmsley | 333943b | 2008-08-19 11:08:45 +0300 | [diff] [blame] | 914 | { .parent = &sys_ck, .rates = dpll_bypass_rates }, |
Roman Tereshonkov | 3760d31 | 2008-03-13 21:35:09 +0200 | [diff] [blame] | 915 | { .parent = &dpll5_m2_ck, .rates = dpll_locked_rates }, |
| 916 | { .parent = NULL } |
| 917 | }; |
| 918 | |
Paul Walmsley | b045d08 | 2008-03-18 11:24:28 +0200 | [diff] [blame] | 919 | static struct clk omap_120m_fck = { |
| 920 | .name = "omap_120m_fck", |
Russell King | 5713718 | 2008-11-04 16:48:35 +0000 | [diff] [blame^] | 921 | .ops = &clkops_null, |
Paul Walmsley | b045d08 | 2008-03-18 11:24:28 +0200 | [diff] [blame] | 922 | .parent = &dpll5_m2_ck, |
Paul Walmsley | 333943b | 2008-08-19 11:08:45 +0300 | [diff] [blame] | 923 | .init = &omap2_init_clksel_parent, |
| 924 | .clksel_reg = OMAP_CM_REGADDR(PLL_MOD, CM_IDLEST2), |
| 925 | .clksel_mask = OMAP3430ES2_ST_PERIPH2_CLK_MASK, |
| 926 | .clksel = omap_120m_fck_clksel, |
Russell King | 5713718 | 2008-11-04 16:48:35 +0000 | [diff] [blame^] | 927 | .flags = CLOCK_IN_OMAP3430ES2 | RATE_PROPAGATES, |
Paul Walmsley | 333943b | 2008-08-19 11:08:45 +0300 | [diff] [blame] | 928 | .recalc = &omap2_clksel_recalc, |
Paul Walmsley | b045d08 | 2008-03-18 11:24:28 +0200 | [diff] [blame] | 929 | }; |
| 930 | |
| 931 | /* CM EXTERNAL CLOCK OUTPUTS */ |
| 932 | |
| 933 | static const struct clksel_rate clkout2_src_core_rates[] = { |
| 934 | { .div = 1, .val = 0, .flags = RATE_IN_343X | DEFAULT_RATE }, |
| 935 | { .div = 0 } |
| 936 | }; |
| 937 | |
| 938 | static const struct clksel_rate clkout2_src_sys_rates[] = { |
| 939 | { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE }, |
| 940 | { .div = 0 } |
| 941 | }; |
| 942 | |
| 943 | static const struct clksel_rate clkout2_src_96m_rates[] = { |
| 944 | { .div = 1, .val = 2, .flags = RATE_IN_343X | DEFAULT_RATE }, |
| 945 | { .div = 0 } |
| 946 | }; |
| 947 | |
| 948 | static const struct clksel_rate clkout2_src_54m_rates[] = { |
| 949 | { .div = 1, .val = 3, .flags = RATE_IN_343X | DEFAULT_RATE }, |
| 950 | { .div = 0 } |
| 951 | }; |
| 952 | |
| 953 | static const struct clksel clkout2_src_clksel[] = { |
| 954 | { .parent = &core_ck, .rates = clkout2_src_core_rates }, |
| 955 | { .parent = &sys_ck, .rates = clkout2_src_sys_rates }, |
| 956 | { .parent = &omap_96m_alwon_fck, .rates = clkout2_src_96m_rates }, |
| 957 | { .parent = &omap_54m_fck, .rates = clkout2_src_54m_rates }, |
| 958 | { .parent = NULL } |
| 959 | }; |
| 960 | |
| 961 | static struct clk clkout2_src_ck = { |
| 962 | .name = "clkout2_src_ck", |
| 963 | .init = &omap2_init_clksel_parent, |
| 964 | .enable_reg = OMAP3430_CM_CLKOUT_CTRL, |
| 965 | .enable_bit = OMAP3430_CLKOUT2_EN_SHIFT, |
| 966 | .clksel_reg = OMAP3430_CM_CLKOUT_CTRL, |
| 967 | .clksel_mask = OMAP3430_CLKOUT2SOURCE_MASK, |
| 968 | .clksel = clkout2_src_clksel, |
| 969 | .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES, |
| 970 | .recalc = &omap2_clksel_recalc, |
| 971 | }; |
| 972 | |
| 973 | static const struct clksel_rate sys_clkout2_rates[] = { |
| 974 | { .div = 1, .val = 0, .flags = RATE_IN_343X | DEFAULT_RATE }, |
| 975 | { .div = 2, .val = 1, .flags = RATE_IN_343X }, |
| 976 | { .div = 4, .val = 2, .flags = RATE_IN_343X }, |
| 977 | { .div = 8, .val = 3, .flags = RATE_IN_343X }, |
| 978 | { .div = 16, .val = 4, .flags = RATE_IN_343X }, |
| 979 | { .div = 0 }, |
| 980 | }; |
| 981 | |
| 982 | static const struct clksel sys_clkout2_clksel[] = { |
| 983 | { .parent = &clkout2_src_ck, .rates = sys_clkout2_rates }, |
| 984 | { .parent = NULL }, |
| 985 | }; |
| 986 | |
| 987 | static struct clk sys_clkout2 = { |
| 988 | .name = "sys_clkout2", |
Russell King | 5713718 | 2008-11-04 16:48:35 +0000 | [diff] [blame^] | 989 | .ops = &clkops_null, |
Paul Walmsley | b045d08 | 2008-03-18 11:24:28 +0200 | [diff] [blame] | 990 | .init = &omap2_init_clksel_parent, |
| 991 | .clksel_reg = OMAP3430_CM_CLKOUT_CTRL, |
| 992 | .clksel_mask = OMAP3430_CLKOUT2_DIV_MASK, |
| 993 | .clksel = sys_clkout2_clksel, |
Russell King | 5713718 | 2008-11-04 16:48:35 +0000 | [diff] [blame^] | 994 | .flags = CLOCK_IN_OMAP343X, |
Paul Walmsley | b045d08 | 2008-03-18 11:24:28 +0200 | [diff] [blame] | 995 | .recalc = &omap2_clksel_recalc, |
| 996 | }; |
| 997 | |
| 998 | /* CM OUTPUT CLOCKS */ |
| 999 | |
| 1000 | static struct clk corex2_fck = { |
| 1001 | .name = "corex2_fck", |
Russell King | 5713718 | 2008-11-04 16:48:35 +0000 | [diff] [blame^] | 1002 | .ops = &clkops_null, |
Paul Walmsley | b045d08 | 2008-03-18 11:24:28 +0200 | [diff] [blame] | 1003 | .parent = &dpll3_m2x2_ck, |
Russell King | 5713718 | 2008-11-04 16:48:35 +0000 | [diff] [blame^] | 1004 | .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES, |
Paul Walmsley | b045d08 | 2008-03-18 11:24:28 +0200 | [diff] [blame] | 1005 | .recalc = &followparent_recalc, |
| 1006 | }; |
| 1007 | |
| 1008 | /* DPLL power domain clock controls */ |
| 1009 | |
| 1010 | static const struct clksel div2_core_clksel[] = { |
| 1011 | { .parent = &core_ck, .rates = div2_rates }, |
| 1012 | { .parent = NULL } |
| 1013 | }; |
| 1014 | |
Roman Tereshonkov | 3760d31 | 2008-03-13 21:35:09 +0200 | [diff] [blame] | 1015 | /* |
| 1016 | * REVISIT: Are these in DPLL power domain or CM power domain? docs |
| 1017 | * may be inconsistent here? |
| 1018 | */ |
Paul Walmsley | b045d08 | 2008-03-18 11:24:28 +0200 | [diff] [blame] | 1019 | static struct clk dpll1_fck = { |
| 1020 | .name = "dpll1_fck", |
Russell King | 5713718 | 2008-11-04 16:48:35 +0000 | [diff] [blame^] | 1021 | .ops = &clkops_null, |
Paul Walmsley | b045d08 | 2008-03-18 11:24:28 +0200 | [diff] [blame] | 1022 | .parent = &core_ck, |
| 1023 | .init = &omap2_init_clksel_parent, |
| 1024 | .clksel_reg = OMAP_CM_REGADDR(MPU_MOD, OMAP3430_CM_CLKSEL1_PLL), |
| 1025 | .clksel_mask = OMAP3430_MPU_CLK_SRC_MASK, |
| 1026 | .clksel = div2_core_clksel, |
Russell King | 5713718 | 2008-11-04 16:48:35 +0000 | [diff] [blame^] | 1027 | .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES, |
Paul Walmsley | b045d08 | 2008-03-18 11:24:28 +0200 | [diff] [blame] | 1028 | .recalc = &omap2_clksel_recalc, |
| 1029 | }; |
| 1030 | |
Roman Tereshonkov | 3760d31 | 2008-03-13 21:35:09 +0200 | [diff] [blame] | 1031 | /* |
| 1032 | * MPU clksel: |
| 1033 | * If DPLL1 is locked, mpu_ck derives from DPLL1; otherwise, mpu_ck |
| 1034 | * derives from the high-frequency bypass clock originating from DPLL3, |
| 1035 | * called 'dpll1_fck' |
| 1036 | */ |
| 1037 | static const struct clksel mpu_clksel[] = { |
Paul Walmsley | 333943b | 2008-08-19 11:08:45 +0300 | [diff] [blame] | 1038 | { .parent = &dpll1_fck, .rates = dpll_bypass_rates }, |
Roman Tereshonkov | 3760d31 | 2008-03-13 21:35:09 +0200 | [diff] [blame] | 1039 | { .parent = &dpll1_x2m2_ck, .rates = dpll_locked_rates }, |
| 1040 | { .parent = NULL } |
| 1041 | }; |
| 1042 | |
| 1043 | static struct clk mpu_ck = { |
| 1044 | .name = "mpu_ck", |
Russell King | 5713718 | 2008-11-04 16:48:35 +0000 | [diff] [blame^] | 1045 | .ops = &clkops_null, |
Roman Tereshonkov | 3760d31 | 2008-03-13 21:35:09 +0200 | [diff] [blame] | 1046 | .parent = &dpll1_x2m2_ck, |
| 1047 | .init = &omap2_init_clksel_parent, |
| 1048 | .clksel_reg = OMAP_CM_REGADDR(MPU_MOD, OMAP3430_CM_IDLEST_PLL), |
| 1049 | .clksel_mask = OMAP3430_ST_MPU_CLK_MASK, |
| 1050 | .clksel = mpu_clksel, |
Russell King | 5713718 | 2008-11-04 16:48:35 +0000 | [diff] [blame^] | 1051 | .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES, |
Paul Walmsley | 333943b | 2008-08-19 11:08:45 +0300 | [diff] [blame] | 1052 | .clkdm_name = "mpu_clkdm", |
Roman Tereshonkov | 3760d31 | 2008-03-13 21:35:09 +0200 | [diff] [blame] | 1053 | .recalc = &omap2_clksel_recalc, |
| 1054 | }; |
| 1055 | |
| 1056 | /* arm_fck is divided by two when DPLL1 locked; otherwise, passthrough mpu_ck */ |
| 1057 | static const struct clksel_rate arm_fck_rates[] = { |
| 1058 | { .div = 1, .val = 0, .flags = RATE_IN_343X | DEFAULT_RATE }, |
| 1059 | { .div = 2, .val = 1, .flags = RATE_IN_343X }, |
| 1060 | { .div = 0 }, |
| 1061 | }; |
| 1062 | |
| 1063 | static const struct clksel arm_fck_clksel[] = { |
| 1064 | { .parent = &mpu_ck, .rates = arm_fck_rates }, |
| 1065 | { .parent = NULL } |
| 1066 | }; |
| 1067 | |
| 1068 | static struct clk arm_fck = { |
| 1069 | .name = "arm_fck", |
Russell King | 5713718 | 2008-11-04 16:48:35 +0000 | [diff] [blame^] | 1070 | .ops = &clkops_null, |
Roman Tereshonkov | 3760d31 | 2008-03-13 21:35:09 +0200 | [diff] [blame] | 1071 | .parent = &mpu_ck, |
| 1072 | .init = &omap2_init_clksel_parent, |
| 1073 | .clksel_reg = OMAP_CM_REGADDR(MPU_MOD, OMAP3430_CM_IDLEST_PLL), |
| 1074 | .clksel_mask = OMAP3430_ST_MPU_CLK_MASK, |
| 1075 | .clksel = arm_fck_clksel, |
Russell King | 5713718 | 2008-11-04 16:48:35 +0000 | [diff] [blame^] | 1076 | .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES, |
Roman Tereshonkov | 3760d31 | 2008-03-13 21:35:09 +0200 | [diff] [blame] | 1077 | .recalc = &omap2_clksel_recalc, |
| 1078 | }; |
| 1079 | |
Paul Walmsley | 333943b | 2008-08-19 11:08:45 +0300 | [diff] [blame] | 1080 | /* XXX What about neon_clkdm ? */ |
| 1081 | |
Roman Tereshonkov | 3760d31 | 2008-03-13 21:35:09 +0200 | [diff] [blame] | 1082 | /* |
| 1083 | * REVISIT: This clock is never specifically defined in the 3430 TRM, |
| 1084 | * although it is referenced - so this is a guess |
| 1085 | */ |
| 1086 | static struct clk emu_mpu_alwon_ck = { |
| 1087 | .name = "emu_mpu_alwon_ck", |
Russell King | 5713718 | 2008-11-04 16:48:35 +0000 | [diff] [blame^] | 1088 | .ops = &clkops_null, |
Roman Tereshonkov | 3760d31 | 2008-03-13 21:35:09 +0200 | [diff] [blame] | 1089 | .parent = &mpu_ck, |
Russell King | 5713718 | 2008-11-04 16:48:35 +0000 | [diff] [blame^] | 1090 | .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES, |
Roman Tereshonkov | 3760d31 | 2008-03-13 21:35:09 +0200 | [diff] [blame] | 1091 | .recalc = &followparent_recalc, |
| 1092 | }; |
| 1093 | |
Paul Walmsley | b045d08 | 2008-03-18 11:24:28 +0200 | [diff] [blame] | 1094 | static struct clk dpll2_fck = { |
| 1095 | .name = "dpll2_fck", |
Russell King | 5713718 | 2008-11-04 16:48:35 +0000 | [diff] [blame^] | 1096 | .ops = &clkops_null, |
Paul Walmsley | b045d08 | 2008-03-18 11:24:28 +0200 | [diff] [blame] | 1097 | .parent = &core_ck, |
| 1098 | .init = &omap2_init_clksel_parent, |
| 1099 | .clksel_reg = OMAP_CM_REGADDR(OMAP3430_IVA2_MOD, OMAP3430_CM_CLKSEL1_PLL), |
| 1100 | .clksel_mask = OMAP3430_IVA2_CLK_SRC_MASK, |
| 1101 | .clksel = div2_core_clksel, |
Russell King | 5713718 | 2008-11-04 16:48:35 +0000 | [diff] [blame^] | 1102 | .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES, |
Paul Walmsley | b045d08 | 2008-03-18 11:24:28 +0200 | [diff] [blame] | 1103 | .recalc = &omap2_clksel_recalc, |
| 1104 | }; |
| 1105 | |
Roman Tereshonkov | 3760d31 | 2008-03-13 21:35:09 +0200 | [diff] [blame] | 1106 | /* |
| 1107 | * IVA2 clksel: |
| 1108 | * If DPLL2 is locked, iva2_ck derives from DPLL2; otherwise, iva2_ck |
| 1109 | * derives from the high-frequency bypass clock originating from DPLL3, |
| 1110 | * called 'dpll2_fck' |
| 1111 | */ |
| 1112 | |
| 1113 | static const struct clksel iva2_clksel[] = { |
Paul Walmsley | 333943b | 2008-08-19 11:08:45 +0300 | [diff] [blame] | 1114 | { .parent = &dpll2_fck, .rates = dpll_bypass_rates }, |
Roman Tereshonkov | 3760d31 | 2008-03-13 21:35:09 +0200 | [diff] [blame] | 1115 | { .parent = &dpll2_m2_ck, .rates = dpll_locked_rates }, |
| 1116 | { .parent = NULL } |
| 1117 | }; |
| 1118 | |
| 1119 | static struct clk iva2_ck = { |
| 1120 | .name = "iva2_ck", |
| 1121 | .parent = &dpll2_m2_ck, |
| 1122 | .init = &omap2_init_clksel_parent, |
Hiroshi DOYU | 31c203d | 2008-04-01 10:11:22 +0300 | [diff] [blame] | 1123 | .enable_reg = OMAP_CM_REGADDR(OMAP3430_IVA2_MOD, CM_FCLKEN), |
| 1124 | .enable_bit = OMAP3430_CM_FCLKEN_IVA2_EN_IVA2_SHIFT, |
Roman Tereshonkov | 3760d31 | 2008-03-13 21:35:09 +0200 | [diff] [blame] | 1125 | .clksel_reg = OMAP_CM_REGADDR(OMAP3430_IVA2_MOD, |
| 1126 | OMAP3430_CM_IDLEST_PLL), |
| 1127 | .clksel_mask = OMAP3430_ST_IVA2_CLK_MASK, |
| 1128 | .clksel = iva2_clksel, |
Hiroshi DOYU | 31c203d | 2008-04-01 10:11:22 +0300 | [diff] [blame] | 1129 | .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES, |
Paul Walmsley | 333943b | 2008-08-19 11:08:45 +0300 | [diff] [blame] | 1130 | .clkdm_name = "iva2_clkdm", |
Roman Tereshonkov | 3760d31 | 2008-03-13 21:35:09 +0200 | [diff] [blame] | 1131 | .recalc = &omap2_clksel_recalc, |
| 1132 | }; |
| 1133 | |
Paul Walmsley | b045d08 | 2008-03-18 11:24:28 +0200 | [diff] [blame] | 1134 | /* Common interface clocks */ |
| 1135 | |
| 1136 | static struct clk l3_ick = { |
| 1137 | .name = "l3_ick", |
Russell King | 5713718 | 2008-11-04 16:48:35 +0000 | [diff] [blame^] | 1138 | .ops = &clkops_null, |
Paul Walmsley | b045d08 | 2008-03-18 11:24:28 +0200 | [diff] [blame] | 1139 | .parent = &core_ck, |
| 1140 | .init = &omap2_init_clksel_parent, |
| 1141 | .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL), |
| 1142 | .clksel_mask = OMAP3430_CLKSEL_L3_MASK, |
| 1143 | .clksel = div2_core_clksel, |
Russell King | 5713718 | 2008-11-04 16:48:35 +0000 | [diff] [blame^] | 1144 | .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES, |
Paul Walmsley | 333943b | 2008-08-19 11:08:45 +0300 | [diff] [blame] | 1145 | .clkdm_name = "core_l3_clkdm", |
Paul Walmsley | b045d08 | 2008-03-18 11:24:28 +0200 | [diff] [blame] | 1146 | .recalc = &omap2_clksel_recalc, |
| 1147 | }; |
| 1148 | |
| 1149 | static const struct clksel div2_l3_clksel[] = { |
| 1150 | { .parent = &l3_ick, .rates = div2_rates }, |
| 1151 | { .parent = NULL } |
| 1152 | }; |
| 1153 | |
| 1154 | static struct clk l4_ick = { |
| 1155 | .name = "l4_ick", |
Russell King | 5713718 | 2008-11-04 16:48:35 +0000 | [diff] [blame^] | 1156 | .ops = &clkops_null, |
Paul Walmsley | b045d08 | 2008-03-18 11:24:28 +0200 | [diff] [blame] | 1157 | .parent = &l3_ick, |
| 1158 | .init = &omap2_init_clksel_parent, |
| 1159 | .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL), |
| 1160 | .clksel_mask = OMAP3430_CLKSEL_L4_MASK, |
| 1161 | .clksel = div2_l3_clksel, |
Russell King | 5713718 | 2008-11-04 16:48:35 +0000 | [diff] [blame^] | 1162 | .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES, |
Paul Walmsley | 333943b | 2008-08-19 11:08:45 +0300 | [diff] [blame] | 1163 | .clkdm_name = "core_l4_clkdm", |
Paul Walmsley | b045d08 | 2008-03-18 11:24:28 +0200 | [diff] [blame] | 1164 | .recalc = &omap2_clksel_recalc, |
| 1165 | |
| 1166 | }; |
| 1167 | |
| 1168 | static const struct clksel div2_l4_clksel[] = { |
| 1169 | { .parent = &l4_ick, .rates = div2_rates }, |
| 1170 | { .parent = NULL } |
| 1171 | }; |
| 1172 | |
| 1173 | static struct clk rm_ick = { |
| 1174 | .name = "rm_ick", |
Russell King | 5713718 | 2008-11-04 16:48:35 +0000 | [diff] [blame^] | 1175 | .ops = &clkops_null, |
Paul Walmsley | b045d08 | 2008-03-18 11:24:28 +0200 | [diff] [blame] | 1176 | .parent = &l4_ick, |
| 1177 | .init = &omap2_init_clksel_parent, |
| 1178 | .clksel_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_CLKSEL), |
| 1179 | .clksel_mask = OMAP3430_CLKSEL_RM_MASK, |
| 1180 | .clksel = div2_l4_clksel, |
Russell King | 5713718 | 2008-11-04 16:48:35 +0000 | [diff] [blame^] | 1181 | .flags = CLOCK_IN_OMAP343X, |
Paul Walmsley | b045d08 | 2008-03-18 11:24:28 +0200 | [diff] [blame] | 1182 | .recalc = &omap2_clksel_recalc, |
| 1183 | }; |
| 1184 | |
| 1185 | /* GFX power domain */ |
| 1186 | |
Roman Tereshonkov | 3760d31 | 2008-03-13 21:35:09 +0200 | [diff] [blame] | 1187 | /* GFX clocks are in 3430ES1 only. 3430ES2 and later uses the SGX instead */ |
Paul Walmsley | b045d08 | 2008-03-18 11:24:28 +0200 | [diff] [blame] | 1188 | |
| 1189 | static const struct clksel gfx_l3_clksel[] = { |
| 1190 | { .parent = &l3_ick, .rates = gfx_l3_rates }, |
| 1191 | { .parent = NULL } |
| 1192 | }; |
| 1193 | |
Högander Jouni | 5955902 | 2008-08-19 11:08:45 +0300 | [diff] [blame] | 1194 | /* Virtual parent clock for gfx_l3_ick and gfx_l3_fck */ |
| 1195 | static struct clk gfx_l3_ck = { |
| 1196 | .name = "gfx_l3_ck", |
Paul Walmsley | b045d08 | 2008-03-18 11:24:28 +0200 | [diff] [blame] | 1197 | .parent = &l3_ick, |
| 1198 | .init = &omap2_init_clksel_parent, |
| 1199 | .enable_reg = OMAP_CM_REGADDR(GFX_MOD, CM_ICLKEN), |
| 1200 | .enable_bit = OMAP_EN_GFX_SHIFT, |
Högander Jouni | 5955902 | 2008-08-19 11:08:45 +0300 | [diff] [blame] | 1201 | .flags = CLOCK_IN_OMAP3430ES1, |
| 1202 | .recalc = &followparent_recalc, |
| 1203 | }; |
| 1204 | |
| 1205 | static struct clk gfx_l3_fck = { |
| 1206 | .name = "gfx_l3_fck", |
Russell King | 5713718 | 2008-11-04 16:48:35 +0000 | [diff] [blame^] | 1207 | .ops = &clkops_null, |
Högander Jouni | 5955902 | 2008-08-19 11:08:45 +0300 | [diff] [blame] | 1208 | .parent = &gfx_l3_ck, |
| 1209 | .init = &omap2_init_clksel_parent, |
Paul Walmsley | b045d08 | 2008-03-18 11:24:28 +0200 | [diff] [blame] | 1210 | .clksel_reg = OMAP_CM_REGADDR(GFX_MOD, CM_CLKSEL), |
| 1211 | .clksel_mask = OMAP_CLKSEL_GFX_MASK, |
| 1212 | .clksel = gfx_l3_clksel, |
Russell King | 5713718 | 2008-11-04 16:48:35 +0000 | [diff] [blame^] | 1213 | .flags = CLOCK_IN_OMAP3430ES1 | RATE_PROPAGATES, |
Paul Walmsley | 333943b | 2008-08-19 11:08:45 +0300 | [diff] [blame] | 1214 | .clkdm_name = "gfx_3430es1_clkdm", |
Paul Walmsley | b045d08 | 2008-03-18 11:24:28 +0200 | [diff] [blame] | 1215 | .recalc = &omap2_clksel_recalc, |
| 1216 | }; |
| 1217 | |
| 1218 | static struct clk gfx_l3_ick = { |
| 1219 | .name = "gfx_l3_ick", |
Russell King | 5713718 | 2008-11-04 16:48:35 +0000 | [diff] [blame^] | 1220 | .ops = &clkops_null, |
Högander Jouni | 5955902 | 2008-08-19 11:08:45 +0300 | [diff] [blame] | 1221 | .parent = &gfx_l3_ck, |
Russell King | 5713718 | 2008-11-04 16:48:35 +0000 | [diff] [blame^] | 1222 | .flags = CLOCK_IN_OMAP3430ES1, |
Paul Walmsley | 333943b | 2008-08-19 11:08:45 +0300 | [diff] [blame] | 1223 | .clkdm_name = "gfx_3430es1_clkdm", |
Paul Walmsley | b045d08 | 2008-03-18 11:24:28 +0200 | [diff] [blame] | 1224 | .recalc = &followparent_recalc, |
| 1225 | }; |
| 1226 | |
| 1227 | static struct clk gfx_cg1_ck = { |
| 1228 | .name = "gfx_cg1_ck", |
| 1229 | .parent = &gfx_l3_fck, /* REVISIT: correct? */ |
Paul Walmsley | 333943b | 2008-08-19 11:08:45 +0300 | [diff] [blame] | 1230 | .init = &omap2_init_clk_clkdm, |
Paul Walmsley | b045d08 | 2008-03-18 11:24:28 +0200 | [diff] [blame] | 1231 | .enable_reg = OMAP_CM_REGADDR(GFX_MOD, CM_FCLKEN), |
| 1232 | .enable_bit = OMAP3430ES1_EN_2D_SHIFT, |
| 1233 | .flags = CLOCK_IN_OMAP3430ES1, |
Paul Walmsley | 333943b | 2008-08-19 11:08:45 +0300 | [diff] [blame] | 1234 | .clkdm_name = "gfx_3430es1_clkdm", |
Paul Walmsley | b045d08 | 2008-03-18 11:24:28 +0200 | [diff] [blame] | 1235 | .recalc = &followparent_recalc, |
| 1236 | }; |
| 1237 | |
| 1238 | static struct clk gfx_cg2_ck = { |
| 1239 | .name = "gfx_cg2_ck", |
| 1240 | .parent = &gfx_l3_fck, /* REVISIT: correct? */ |
Paul Walmsley | 333943b | 2008-08-19 11:08:45 +0300 | [diff] [blame] | 1241 | .init = &omap2_init_clk_clkdm, |
Paul Walmsley | b045d08 | 2008-03-18 11:24:28 +0200 | [diff] [blame] | 1242 | .enable_reg = OMAP_CM_REGADDR(GFX_MOD, CM_FCLKEN), |
| 1243 | .enable_bit = OMAP3430ES1_EN_3D_SHIFT, |
| 1244 | .flags = CLOCK_IN_OMAP3430ES1, |
Paul Walmsley | 333943b | 2008-08-19 11:08:45 +0300 | [diff] [blame] | 1245 | .clkdm_name = "gfx_3430es1_clkdm", |
Paul Walmsley | b045d08 | 2008-03-18 11:24:28 +0200 | [diff] [blame] | 1246 | .recalc = &followparent_recalc, |
| 1247 | }; |
| 1248 | |
| 1249 | /* SGX power domain - 3430ES2 only */ |
| 1250 | |
| 1251 | static const struct clksel_rate sgx_core_rates[] = { |
| 1252 | { .div = 3, .val = 0, .flags = RATE_IN_343X | DEFAULT_RATE }, |
| 1253 | { .div = 4, .val = 1, .flags = RATE_IN_343X }, |
| 1254 | { .div = 6, .val = 2, .flags = RATE_IN_343X }, |
| 1255 | { .div = 0 }, |
| 1256 | }; |
| 1257 | |
| 1258 | static const struct clksel_rate sgx_96m_rates[] = { |
| 1259 | { .div = 1, .val = 3, .flags = RATE_IN_343X | DEFAULT_RATE }, |
| 1260 | { .div = 0 }, |
| 1261 | }; |
| 1262 | |
| 1263 | static const struct clksel sgx_clksel[] = { |
| 1264 | { .parent = &core_ck, .rates = sgx_core_rates }, |
| 1265 | { .parent = &cm_96m_fck, .rates = sgx_96m_rates }, |
| 1266 | { .parent = NULL }, |
| 1267 | }; |
| 1268 | |
| 1269 | static struct clk sgx_fck = { |
| 1270 | .name = "sgx_fck", |
| 1271 | .init = &omap2_init_clksel_parent, |
| 1272 | .enable_reg = OMAP_CM_REGADDR(OMAP3430ES2_SGX_MOD, CM_FCLKEN), |
| 1273 | .enable_bit = OMAP3430ES2_EN_SGX_SHIFT, |
| 1274 | .clksel_reg = OMAP_CM_REGADDR(OMAP3430ES2_SGX_MOD, CM_CLKSEL), |
| 1275 | .clksel_mask = OMAP3430ES2_CLKSEL_SGX_MASK, |
| 1276 | .clksel = sgx_clksel, |
| 1277 | .flags = CLOCK_IN_OMAP3430ES2, |
Paul Walmsley | 333943b | 2008-08-19 11:08:45 +0300 | [diff] [blame] | 1278 | .clkdm_name = "sgx_clkdm", |
Paul Walmsley | b045d08 | 2008-03-18 11:24:28 +0200 | [diff] [blame] | 1279 | .recalc = &omap2_clksel_recalc, |
| 1280 | }; |
| 1281 | |
| 1282 | static struct clk sgx_ick = { |
| 1283 | .name = "sgx_ick", |
| 1284 | .parent = &l3_ick, |
Paul Walmsley | 333943b | 2008-08-19 11:08:45 +0300 | [diff] [blame] | 1285 | .init = &omap2_init_clk_clkdm, |
Paul Walmsley | b045d08 | 2008-03-18 11:24:28 +0200 | [diff] [blame] | 1286 | .enable_reg = OMAP_CM_REGADDR(OMAP3430ES2_SGX_MOD, CM_ICLKEN), |
| 1287 | .enable_bit = OMAP3430ES2_EN_SGX_SHIFT, |
| 1288 | .flags = CLOCK_IN_OMAP3430ES2, |
Paul Walmsley | 333943b | 2008-08-19 11:08:45 +0300 | [diff] [blame] | 1289 | .clkdm_name = "sgx_clkdm", |
Paul Walmsley | b045d08 | 2008-03-18 11:24:28 +0200 | [diff] [blame] | 1290 | .recalc = &followparent_recalc, |
| 1291 | }; |
| 1292 | |
| 1293 | /* CORE power domain */ |
| 1294 | |
| 1295 | static struct clk d2d_26m_fck = { |
| 1296 | .name = "d2d_26m_fck", |
| 1297 | .parent = &sys_ck, |
Paul Walmsley | 333943b | 2008-08-19 11:08:45 +0300 | [diff] [blame] | 1298 | .init = &omap2_init_clk_clkdm, |
Paul Walmsley | b045d08 | 2008-03-18 11:24:28 +0200 | [diff] [blame] | 1299 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), |
| 1300 | .enable_bit = OMAP3430ES1_EN_D2D_SHIFT, |
| 1301 | .flags = CLOCK_IN_OMAP3430ES1, |
Paul Walmsley | 333943b | 2008-08-19 11:08:45 +0300 | [diff] [blame] | 1302 | .clkdm_name = "d2d_clkdm", |
Paul Walmsley | b045d08 | 2008-03-18 11:24:28 +0200 | [diff] [blame] | 1303 | .recalc = &followparent_recalc, |
| 1304 | }; |
| 1305 | |
| 1306 | static const struct clksel omap343x_gpt_clksel[] = { |
| 1307 | { .parent = &omap_32k_fck, .rates = gpt_32k_rates }, |
| 1308 | { .parent = &sys_ck, .rates = gpt_sys_rates }, |
| 1309 | { .parent = NULL} |
| 1310 | }; |
| 1311 | |
| 1312 | static struct clk gpt10_fck = { |
| 1313 | .name = "gpt10_fck", |
| 1314 | .parent = &sys_ck, |
| 1315 | .init = &omap2_init_clksel_parent, |
| 1316 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), |
| 1317 | .enable_bit = OMAP3430_EN_GPT10_SHIFT, |
| 1318 | .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL), |
| 1319 | .clksel_mask = OMAP3430_CLKSEL_GPT10_MASK, |
| 1320 | .clksel = omap343x_gpt_clksel, |
| 1321 | .flags = CLOCK_IN_OMAP343X, |
Paul Walmsley | 333943b | 2008-08-19 11:08:45 +0300 | [diff] [blame] | 1322 | .clkdm_name = "core_l4_clkdm", |
Paul Walmsley | b045d08 | 2008-03-18 11:24:28 +0200 | [diff] [blame] | 1323 | .recalc = &omap2_clksel_recalc, |
| 1324 | }; |
| 1325 | |
| 1326 | static struct clk gpt11_fck = { |
| 1327 | .name = "gpt11_fck", |
| 1328 | .parent = &sys_ck, |
| 1329 | .init = &omap2_init_clksel_parent, |
| 1330 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), |
| 1331 | .enable_bit = OMAP3430_EN_GPT11_SHIFT, |
| 1332 | .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL), |
| 1333 | .clksel_mask = OMAP3430_CLKSEL_GPT11_MASK, |
| 1334 | .clksel = omap343x_gpt_clksel, |
| 1335 | .flags = CLOCK_IN_OMAP343X, |
Paul Walmsley | 333943b | 2008-08-19 11:08:45 +0300 | [diff] [blame] | 1336 | .clkdm_name = "core_l4_clkdm", |
Paul Walmsley | b045d08 | 2008-03-18 11:24:28 +0200 | [diff] [blame] | 1337 | .recalc = &omap2_clksel_recalc, |
| 1338 | }; |
| 1339 | |
| 1340 | static struct clk cpefuse_fck = { |
| 1341 | .name = "cpefuse_fck", |
| 1342 | .parent = &sys_ck, |
| 1343 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP3430ES2_CM_FCLKEN3), |
| 1344 | .enable_bit = OMAP3430ES2_EN_CPEFUSE_SHIFT, |
| 1345 | .flags = CLOCK_IN_OMAP3430ES2, |
| 1346 | .recalc = &followparent_recalc, |
| 1347 | }; |
| 1348 | |
| 1349 | static struct clk ts_fck = { |
| 1350 | .name = "ts_fck", |
| 1351 | .parent = &omap_32k_fck, |
| 1352 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP3430ES2_CM_FCLKEN3), |
| 1353 | .enable_bit = OMAP3430ES2_EN_TS_SHIFT, |
| 1354 | .flags = CLOCK_IN_OMAP3430ES2, |
| 1355 | .recalc = &followparent_recalc, |
| 1356 | }; |
| 1357 | |
| 1358 | static struct clk usbtll_fck = { |
| 1359 | .name = "usbtll_fck", |
| 1360 | .parent = &omap_120m_fck, |
| 1361 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP3430ES2_CM_FCLKEN3), |
| 1362 | .enable_bit = OMAP3430ES2_EN_USBTLL_SHIFT, |
| 1363 | .flags = CLOCK_IN_OMAP3430ES2, |
| 1364 | .recalc = &followparent_recalc, |
| 1365 | }; |
| 1366 | |
| 1367 | /* CORE 96M FCLK-derived clocks */ |
| 1368 | |
| 1369 | static struct clk core_96m_fck = { |
| 1370 | .name = "core_96m_fck", |
Russell King | 5713718 | 2008-11-04 16:48:35 +0000 | [diff] [blame^] | 1371 | .ops = &clkops_null, |
Paul Walmsley | b045d08 | 2008-03-18 11:24:28 +0200 | [diff] [blame] | 1372 | .parent = &omap_96m_fck, |
Russell King | 5713718 | 2008-11-04 16:48:35 +0000 | [diff] [blame^] | 1373 | .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES, |
Paul Walmsley | 333943b | 2008-08-19 11:08:45 +0300 | [diff] [blame] | 1374 | .clkdm_name = "core_l4_clkdm", |
Paul Walmsley | b045d08 | 2008-03-18 11:24:28 +0200 | [diff] [blame] | 1375 | .recalc = &followparent_recalc, |
| 1376 | }; |
| 1377 | |
| 1378 | static struct clk mmchs3_fck = { |
| 1379 | .name = "mmchs_fck", |
Tony Lindgren | d887466 | 2008-12-10 17:37:16 -0800 | [diff] [blame] | 1380 | .id = 2, |
Paul Walmsley | b045d08 | 2008-03-18 11:24:28 +0200 | [diff] [blame] | 1381 | .parent = &core_96m_fck, |
| 1382 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), |
| 1383 | .enable_bit = OMAP3430ES2_EN_MMC3_SHIFT, |
| 1384 | .flags = CLOCK_IN_OMAP3430ES2, |
Paul Walmsley | 333943b | 2008-08-19 11:08:45 +0300 | [diff] [blame] | 1385 | .clkdm_name = "core_l4_clkdm", |
Paul Walmsley | b045d08 | 2008-03-18 11:24:28 +0200 | [diff] [blame] | 1386 | .recalc = &followparent_recalc, |
| 1387 | }; |
| 1388 | |
| 1389 | static struct clk mmchs2_fck = { |
| 1390 | .name = "mmchs_fck", |
Tony Lindgren | d887466 | 2008-12-10 17:37:16 -0800 | [diff] [blame] | 1391 | .id = 1, |
Paul Walmsley | b045d08 | 2008-03-18 11:24:28 +0200 | [diff] [blame] | 1392 | .parent = &core_96m_fck, |
| 1393 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), |
| 1394 | .enable_bit = OMAP3430_EN_MMC2_SHIFT, |
| 1395 | .flags = CLOCK_IN_OMAP343X, |
Paul Walmsley | 333943b | 2008-08-19 11:08:45 +0300 | [diff] [blame] | 1396 | .clkdm_name = "core_l4_clkdm", |
Paul Walmsley | b045d08 | 2008-03-18 11:24:28 +0200 | [diff] [blame] | 1397 | .recalc = &followparent_recalc, |
| 1398 | }; |
| 1399 | |
| 1400 | static struct clk mspro_fck = { |
| 1401 | .name = "mspro_fck", |
| 1402 | .parent = &core_96m_fck, |
| 1403 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), |
| 1404 | .enable_bit = OMAP3430_EN_MSPRO_SHIFT, |
| 1405 | .flags = CLOCK_IN_OMAP343X, |
Paul Walmsley | 333943b | 2008-08-19 11:08:45 +0300 | [diff] [blame] | 1406 | .clkdm_name = "core_l4_clkdm", |
Paul Walmsley | b045d08 | 2008-03-18 11:24:28 +0200 | [diff] [blame] | 1407 | .recalc = &followparent_recalc, |
| 1408 | }; |
| 1409 | |
| 1410 | static struct clk mmchs1_fck = { |
| 1411 | .name = "mmchs_fck", |
Paul Walmsley | b045d08 | 2008-03-18 11:24:28 +0200 | [diff] [blame] | 1412 | .parent = &core_96m_fck, |
| 1413 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), |
| 1414 | .enable_bit = OMAP3430_EN_MMC1_SHIFT, |
| 1415 | .flags = CLOCK_IN_OMAP343X, |
Paul Walmsley | 333943b | 2008-08-19 11:08:45 +0300 | [diff] [blame] | 1416 | .clkdm_name = "core_l4_clkdm", |
Paul Walmsley | b045d08 | 2008-03-18 11:24:28 +0200 | [diff] [blame] | 1417 | .recalc = &followparent_recalc, |
| 1418 | }; |
| 1419 | |
| 1420 | static struct clk i2c3_fck = { |
| 1421 | .name = "i2c_fck", |
| 1422 | .id = 3, |
| 1423 | .parent = &core_96m_fck, |
| 1424 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), |
| 1425 | .enable_bit = OMAP3430_EN_I2C3_SHIFT, |
| 1426 | .flags = CLOCK_IN_OMAP343X, |
Paul Walmsley | 333943b | 2008-08-19 11:08:45 +0300 | [diff] [blame] | 1427 | .clkdm_name = "core_l4_clkdm", |
Paul Walmsley | b045d08 | 2008-03-18 11:24:28 +0200 | [diff] [blame] | 1428 | .recalc = &followparent_recalc, |
| 1429 | }; |
| 1430 | |
| 1431 | static struct clk i2c2_fck = { |
| 1432 | .name = "i2c_fck", |
Paul Walmsley | 333943b | 2008-08-19 11:08:45 +0300 | [diff] [blame] | 1433 | .id = 2, |
Paul Walmsley | b045d08 | 2008-03-18 11:24:28 +0200 | [diff] [blame] | 1434 | .parent = &core_96m_fck, |
| 1435 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), |
| 1436 | .enable_bit = OMAP3430_EN_I2C2_SHIFT, |
| 1437 | .flags = CLOCK_IN_OMAP343X, |
Paul Walmsley | 333943b | 2008-08-19 11:08:45 +0300 | [diff] [blame] | 1438 | .clkdm_name = "core_l4_clkdm", |
Paul Walmsley | b045d08 | 2008-03-18 11:24:28 +0200 | [diff] [blame] | 1439 | .recalc = &followparent_recalc, |
| 1440 | }; |
| 1441 | |
| 1442 | static struct clk i2c1_fck = { |
| 1443 | .name = "i2c_fck", |
| 1444 | .id = 1, |
| 1445 | .parent = &core_96m_fck, |
| 1446 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), |
| 1447 | .enable_bit = OMAP3430_EN_I2C1_SHIFT, |
| 1448 | .flags = CLOCK_IN_OMAP343X, |
Paul Walmsley | 333943b | 2008-08-19 11:08:45 +0300 | [diff] [blame] | 1449 | .clkdm_name = "core_l4_clkdm", |
Paul Walmsley | b045d08 | 2008-03-18 11:24:28 +0200 | [diff] [blame] | 1450 | .recalc = &followparent_recalc, |
| 1451 | }; |
| 1452 | |
| 1453 | /* |
| 1454 | * MCBSP 1 & 5 get their 96MHz clock from core_96m_fck; |
| 1455 | * MCBSP 2, 3, 4 get their 96MHz clock from per_96m_fck. |
| 1456 | */ |
| 1457 | static const struct clksel_rate common_mcbsp_96m_rates[] = { |
| 1458 | { .div = 1, .val = 0, .flags = RATE_IN_343X | DEFAULT_RATE }, |
| 1459 | { .div = 0 } |
| 1460 | }; |
| 1461 | |
| 1462 | static const struct clksel_rate common_mcbsp_mcbsp_rates[] = { |
| 1463 | { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE }, |
| 1464 | { .div = 0 } |
| 1465 | }; |
| 1466 | |
| 1467 | static const struct clksel mcbsp_15_clksel[] = { |
| 1468 | { .parent = &core_96m_fck, .rates = common_mcbsp_96m_rates }, |
| 1469 | { .parent = &mcbsp_clks, .rates = common_mcbsp_mcbsp_rates }, |
| 1470 | { .parent = NULL } |
| 1471 | }; |
| 1472 | |
| 1473 | static struct clk mcbsp5_fck = { |
Eduardo Valentin | 78673bc | 2008-07-03 12:24:40 +0300 | [diff] [blame] | 1474 | .name = "mcbsp_fck", |
| 1475 | .id = 5, |
Paul Walmsley | b045d08 | 2008-03-18 11:24:28 +0200 | [diff] [blame] | 1476 | .init = &omap2_init_clksel_parent, |
| 1477 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), |
| 1478 | .enable_bit = OMAP3430_EN_MCBSP5_SHIFT, |
| 1479 | .clksel_reg = OMAP343X_CTRL_REGADDR(OMAP343X_CONTROL_DEVCONF1), |
| 1480 | .clksel_mask = OMAP2_MCBSP5_CLKS_MASK, |
| 1481 | .clksel = mcbsp_15_clksel, |
| 1482 | .flags = CLOCK_IN_OMAP343X, |
Paul Walmsley | 333943b | 2008-08-19 11:08:45 +0300 | [diff] [blame] | 1483 | .clkdm_name = "core_l4_clkdm", |
Paul Walmsley | b045d08 | 2008-03-18 11:24:28 +0200 | [diff] [blame] | 1484 | .recalc = &omap2_clksel_recalc, |
| 1485 | }; |
| 1486 | |
| 1487 | static struct clk mcbsp1_fck = { |
Eduardo Valentin | 78673bc | 2008-07-03 12:24:40 +0300 | [diff] [blame] | 1488 | .name = "mcbsp_fck", |
| 1489 | .id = 1, |
Paul Walmsley | b045d08 | 2008-03-18 11:24:28 +0200 | [diff] [blame] | 1490 | .init = &omap2_init_clksel_parent, |
| 1491 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), |
| 1492 | .enable_bit = OMAP3430_EN_MCBSP1_SHIFT, |
| 1493 | .clksel_reg = OMAP343X_CTRL_REGADDR(OMAP2_CONTROL_DEVCONF0), |
| 1494 | .clksel_mask = OMAP2_MCBSP1_CLKS_MASK, |
| 1495 | .clksel = mcbsp_15_clksel, |
| 1496 | .flags = CLOCK_IN_OMAP343X, |
Paul Walmsley | 333943b | 2008-08-19 11:08:45 +0300 | [diff] [blame] | 1497 | .clkdm_name = "core_l4_clkdm", |
Paul Walmsley | b045d08 | 2008-03-18 11:24:28 +0200 | [diff] [blame] | 1498 | .recalc = &omap2_clksel_recalc, |
| 1499 | }; |
| 1500 | |
| 1501 | /* CORE_48M_FCK-derived clocks */ |
| 1502 | |
| 1503 | static struct clk core_48m_fck = { |
| 1504 | .name = "core_48m_fck", |
Russell King | 5713718 | 2008-11-04 16:48:35 +0000 | [diff] [blame^] | 1505 | .ops = &clkops_null, |
Paul Walmsley | b045d08 | 2008-03-18 11:24:28 +0200 | [diff] [blame] | 1506 | .parent = &omap_48m_fck, |
Russell King | 5713718 | 2008-11-04 16:48:35 +0000 | [diff] [blame^] | 1507 | .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES, |
Paul Walmsley | 333943b | 2008-08-19 11:08:45 +0300 | [diff] [blame] | 1508 | .clkdm_name = "core_l4_clkdm", |
Paul Walmsley | b045d08 | 2008-03-18 11:24:28 +0200 | [diff] [blame] | 1509 | .recalc = &followparent_recalc, |
| 1510 | }; |
| 1511 | |
| 1512 | static struct clk mcspi4_fck = { |
| 1513 | .name = "mcspi_fck", |
| 1514 | .id = 4, |
| 1515 | .parent = &core_48m_fck, |
| 1516 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), |
| 1517 | .enable_bit = OMAP3430_EN_MCSPI4_SHIFT, |
| 1518 | .flags = CLOCK_IN_OMAP343X, |
| 1519 | .recalc = &followparent_recalc, |
| 1520 | }; |
| 1521 | |
| 1522 | static struct clk mcspi3_fck = { |
| 1523 | .name = "mcspi_fck", |
| 1524 | .id = 3, |
| 1525 | .parent = &core_48m_fck, |
| 1526 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), |
| 1527 | .enable_bit = OMAP3430_EN_MCSPI3_SHIFT, |
| 1528 | .flags = CLOCK_IN_OMAP343X, |
| 1529 | .recalc = &followparent_recalc, |
| 1530 | }; |
| 1531 | |
| 1532 | static struct clk mcspi2_fck = { |
| 1533 | .name = "mcspi_fck", |
| 1534 | .id = 2, |
| 1535 | .parent = &core_48m_fck, |
| 1536 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), |
| 1537 | .enable_bit = OMAP3430_EN_MCSPI2_SHIFT, |
| 1538 | .flags = CLOCK_IN_OMAP343X, |
| 1539 | .recalc = &followparent_recalc, |
| 1540 | }; |
| 1541 | |
| 1542 | static struct clk mcspi1_fck = { |
| 1543 | .name = "mcspi_fck", |
| 1544 | .id = 1, |
| 1545 | .parent = &core_48m_fck, |
| 1546 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), |
| 1547 | .enable_bit = OMAP3430_EN_MCSPI1_SHIFT, |
| 1548 | .flags = CLOCK_IN_OMAP343X, |
| 1549 | .recalc = &followparent_recalc, |
| 1550 | }; |
| 1551 | |
| 1552 | static struct clk uart2_fck = { |
| 1553 | .name = "uart2_fck", |
| 1554 | .parent = &core_48m_fck, |
| 1555 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), |
| 1556 | .enable_bit = OMAP3430_EN_UART2_SHIFT, |
| 1557 | .flags = CLOCK_IN_OMAP343X, |
| 1558 | .recalc = &followparent_recalc, |
| 1559 | }; |
| 1560 | |
| 1561 | static struct clk uart1_fck = { |
| 1562 | .name = "uart1_fck", |
| 1563 | .parent = &core_48m_fck, |
| 1564 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), |
| 1565 | .enable_bit = OMAP3430_EN_UART1_SHIFT, |
| 1566 | .flags = CLOCK_IN_OMAP343X, |
| 1567 | .recalc = &followparent_recalc, |
| 1568 | }; |
| 1569 | |
| 1570 | static struct clk fshostusb_fck = { |
| 1571 | .name = "fshostusb_fck", |
| 1572 | .parent = &core_48m_fck, |
| 1573 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), |
| 1574 | .enable_bit = OMAP3430ES1_EN_FSHOSTUSB_SHIFT, |
| 1575 | .flags = CLOCK_IN_OMAP3430ES1, |
| 1576 | .recalc = &followparent_recalc, |
| 1577 | }; |
| 1578 | |
| 1579 | /* CORE_12M_FCK based clocks */ |
| 1580 | |
| 1581 | static struct clk core_12m_fck = { |
| 1582 | .name = "core_12m_fck", |
Russell King | 5713718 | 2008-11-04 16:48:35 +0000 | [diff] [blame^] | 1583 | .ops = &clkops_null, |
Paul Walmsley | b045d08 | 2008-03-18 11:24:28 +0200 | [diff] [blame] | 1584 | .parent = &omap_12m_fck, |
Russell King | 5713718 | 2008-11-04 16:48:35 +0000 | [diff] [blame^] | 1585 | .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES, |
Paul Walmsley | 333943b | 2008-08-19 11:08:45 +0300 | [diff] [blame] | 1586 | .clkdm_name = "core_l4_clkdm", |
Paul Walmsley | b045d08 | 2008-03-18 11:24:28 +0200 | [diff] [blame] | 1587 | .recalc = &followparent_recalc, |
| 1588 | }; |
| 1589 | |
| 1590 | static struct clk hdq_fck = { |
| 1591 | .name = "hdq_fck", |
| 1592 | .parent = &core_12m_fck, |
| 1593 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), |
| 1594 | .enable_bit = OMAP3430_EN_HDQ_SHIFT, |
| 1595 | .flags = CLOCK_IN_OMAP343X, |
| 1596 | .recalc = &followparent_recalc, |
| 1597 | }; |
| 1598 | |
| 1599 | /* DPLL3-derived clock */ |
| 1600 | |
| 1601 | static const struct clksel_rate ssi_ssr_corex2_rates[] = { |
| 1602 | { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE }, |
| 1603 | { .div = 2, .val = 2, .flags = RATE_IN_343X }, |
| 1604 | { .div = 3, .val = 3, .flags = RATE_IN_343X }, |
| 1605 | { .div = 4, .val = 4, .flags = RATE_IN_343X }, |
| 1606 | { .div = 6, .val = 6, .flags = RATE_IN_343X }, |
| 1607 | { .div = 8, .val = 8, .flags = RATE_IN_343X }, |
| 1608 | { .div = 0 } |
| 1609 | }; |
| 1610 | |
| 1611 | static const struct clksel ssi_ssr_clksel[] = { |
| 1612 | { .parent = &corex2_fck, .rates = ssi_ssr_corex2_rates }, |
| 1613 | { .parent = NULL } |
| 1614 | }; |
| 1615 | |
| 1616 | static struct clk ssi_ssr_fck = { |
| 1617 | .name = "ssi_ssr_fck", |
| 1618 | .init = &omap2_init_clksel_parent, |
| 1619 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), |
| 1620 | .enable_bit = OMAP3430_EN_SSI_SHIFT, |
| 1621 | .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL), |
| 1622 | .clksel_mask = OMAP3430_CLKSEL_SSI_MASK, |
| 1623 | .clksel = ssi_ssr_clksel, |
| 1624 | .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES, |
Paul Walmsley | 333943b | 2008-08-19 11:08:45 +0300 | [diff] [blame] | 1625 | .clkdm_name = "core_l4_clkdm", |
Paul Walmsley | b045d08 | 2008-03-18 11:24:28 +0200 | [diff] [blame] | 1626 | .recalc = &omap2_clksel_recalc, |
| 1627 | }; |
| 1628 | |
| 1629 | static struct clk ssi_sst_fck = { |
| 1630 | .name = "ssi_sst_fck", |
Russell King | 5713718 | 2008-11-04 16:48:35 +0000 | [diff] [blame^] | 1631 | .ops = &clkops_null, |
Paul Walmsley | b045d08 | 2008-03-18 11:24:28 +0200 | [diff] [blame] | 1632 | .parent = &ssi_ssr_fck, |
| 1633 | .fixed_div = 2, |
Russell King | 5713718 | 2008-11-04 16:48:35 +0000 | [diff] [blame^] | 1634 | .flags = CLOCK_IN_OMAP343X, |
Paul Walmsley | b045d08 | 2008-03-18 11:24:28 +0200 | [diff] [blame] | 1635 | .recalc = &omap2_fixed_divisor_recalc, |
| 1636 | }; |
| 1637 | |
| 1638 | |
| 1639 | |
| 1640 | /* CORE_L3_ICK based clocks */ |
| 1641 | |
Paul Walmsley | 333943b | 2008-08-19 11:08:45 +0300 | [diff] [blame] | 1642 | /* |
| 1643 | * XXX must add clk_enable/clk_disable for these if standard code won't |
| 1644 | * handle it |
| 1645 | */ |
Paul Walmsley | b045d08 | 2008-03-18 11:24:28 +0200 | [diff] [blame] | 1646 | static struct clk core_l3_ick = { |
| 1647 | .name = "core_l3_ick", |
Russell King | 5713718 | 2008-11-04 16:48:35 +0000 | [diff] [blame^] | 1648 | .ops = &clkops_null, |
Paul Walmsley | b045d08 | 2008-03-18 11:24:28 +0200 | [diff] [blame] | 1649 | .parent = &l3_ick, |
Paul Walmsley | 333943b | 2008-08-19 11:08:45 +0300 | [diff] [blame] | 1650 | .init = &omap2_init_clk_clkdm, |
Russell King | 5713718 | 2008-11-04 16:48:35 +0000 | [diff] [blame^] | 1651 | .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES, |
Paul Walmsley | 333943b | 2008-08-19 11:08:45 +0300 | [diff] [blame] | 1652 | .clkdm_name = "core_l3_clkdm", |
Paul Walmsley | b045d08 | 2008-03-18 11:24:28 +0200 | [diff] [blame] | 1653 | .recalc = &followparent_recalc, |
| 1654 | }; |
| 1655 | |
| 1656 | static struct clk hsotgusb_ick = { |
| 1657 | .name = "hsotgusb_ick", |
| 1658 | .parent = &core_l3_ick, |
| 1659 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), |
| 1660 | .enable_bit = OMAP3430_EN_HSOTGUSB_SHIFT, |
| 1661 | .flags = CLOCK_IN_OMAP343X, |
Paul Walmsley | 333943b | 2008-08-19 11:08:45 +0300 | [diff] [blame] | 1662 | .clkdm_name = "core_l3_clkdm", |
Paul Walmsley | b045d08 | 2008-03-18 11:24:28 +0200 | [diff] [blame] | 1663 | .recalc = &followparent_recalc, |
| 1664 | }; |
| 1665 | |
| 1666 | static struct clk sdrc_ick = { |
| 1667 | .name = "sdrc_ick", |
| 1668 | .parent = &core_l3_ick, |
| 1669 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), |
| 1670 | .enable_bit = OMAP3430_EN_SDRC_SHIFT, |
| 1671 | .flags = CLOCK_IN_OMAP343X | ENABLE_ON_INIT, |
Paul Walmsley | 333943b | 2008-08-19 11:08:45 +0300 | [diff] [blame] | 1672 | .clkdm_name = "core_l3_clkdm", |
Paul Walmsley | b045d08 | 2008-03-18 11:24:28 +0200 | [diff] [blame] | 1673 | .recalc = &followparent_recalc, |
| 1674 | }; |
| 1675 | |
| 1676 | static struct clk gpmc_fck = { |
| 1677 | .name = "gpmc_fck", |
Russell King | 5713718 | 2008-11-04 16:48:35 +0000 | [diff] [blame^] | 1678 | .ops = &clkops_null, |
Paul Walmsley | b045d08 | 2008-03-18 11:24:28 +0200 | [diff] [blame] | 1679 | .parent = &core_l3_ick, |
Russell King | 5713718 | 2008-11-04 16:48:35 +0000 | [diff] [blame^] | 1680 | .flags = CLOCK_IN_OMAP343X | ENABLE_ON_INIT, /* huh? */ |
Paul Walmsley | 333943b | 2008-08-19 11:08:45 +0300 | [diff] [blame] | 1681 | .clkdm_name = "core_l3_clkdm", |
Paul Walmsley | b045d08 | 2008-03-18 11:24:28 +0200 | [diff] [blame] | 1682 | .recalc = &followparent_recalc, |
| 1683 | }; |
| 1684 | |
| 1685 | /* SECURITY_L3_ICK based clocks */ |
| 1686 | |
| 1687 | static struct clk security_l3_ick = { |
| 1688 | .name = "security_l3_ick", |
Russell King | 5713718 | 2008-11-04 16:48:35 +0000 | [diff] [blame^] | 1689 | .ops = &clkops_null, |
Paul Walmsley | b045d08 | 2008-03-18 11:24:28 +0200 | [diff] [blame] | 1690 | .parent = &l3_ick, |
Russell King | 5713718 | 2008-11-04 16:48:35 +0000 | [diff] [blame^] | 1691 | .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES, |
Paul Walmsley | b045d08 | 2008-03-18 11:24:28 +0200 | [diff] [blame] | 1692 | .recalc = &followparent_recalc, |
| 1693 | }; |
| 1694 | |
| 1695 | static struct clk pka_ick = { |
| 1696 | .name = "pka_ick", |
| 1697 | .parent = &security_l3_ick, |
| 1698 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2), |
| 1699 | .enable_bit = OMAP3430_EN_PKA_SHIFT, |
| 1700 | .flags = CLOCK_IN_OMAP343X, |
| 1701 | .recalc = &followparent_recalc, |
| 1702 | }; |
| 1703 | |
| 1704 | /* CORE_L4_ICK based clocks */ |
| 1705 | |
| 1706 | static struct clk core_l4_ick = { |
| 1707 | .name = "core_l4_ick", |
Russell King | 5713718 | 2008-11-04 16:48:35 +0000 | [diff] [blame^] | 1708 | .ops = &clkops_null, |
Paul Walmsley | b045d08 | 2008-03-18 11:24:28 +0200 | [diff] [blame] | 1709 | .parent = &l4_ick, |
Paul Walmsley | 333943b | 2008-08-19 11:08:45 +0300 | [diff] [blame] | 1710 | .init = &omap2_init_clk_clkdm, |
Russell King | 5713718 | 2008-11-04 16:48:35 +0000 | [diff] [blame^] | 1711 | .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES, |
Paul Walmsley | 333943b | 2008-08-19 11:08:45 +0300 | [diff] [blame] | 1712 | .clkdm_name = "core_l4_clkdm", |
Paul Walmsley | b045d08 | 2008-03-18 11:24:28 +0200 | [diff] [blame] | 1713 | .recalc = &followparent_recalc, |
| 1714 | }; |
| 1715 | |
| 1716 | static struct clk usbtll_ick = { |
| 1717 | .name = "usbtll_ick", |
| 1718 | .parent = &core_l4_ick, |
| 1719 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN3), |
| 1720 | .enable_bit = OMAP3430ES2_EN_USBTLL_SHIFT, |
| 1721 | .flags = CLOCK_IN_OMAP3430ES2, |
Paul Walmsley | 333943b | 2008-08-19 11:08:45 +0300 | [diff] [blame] | 1722 | .clkdm_name = "core_l4_clkdm", |
Paul Walmsley | b045d08 | 2008-03-18 11:24:28 +0200 | [diff] [blame] | 1723 | .recalc = &followparent_recalc, |
| 1724 | }; |
| 1725 | |
| 1726 | static struct clk mmchs3_ick = { |
| 1727 | .name = "mmchs_ick", |
Tony Lindgren | d887466 | 2008-12-10 17:37:16 -0800 | [diff] [blame] | 1728 | .id = 2, |
Paul Walmsley | b045d08 | 2008-03-18 11:24:28 +0200 | [diff] [blame] | 1729 | .parent = &core_l4_ick, |
| 1730 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), |
| 1731 | .enable_bit = OMAP3430ES2_EN_MMC3_SHIFT, |
| 1732 | .flags = CLOCK_IN_OMAP3430ES2, |
Paul Walmsley | 333943b | 2008-08-19 11:08:45 +0300 | [diff] [blame] | 1733 | .clkdm_name = "core_l4_clkdm", |
Paul Walmsley | b045d08 | 2008-03-18 11:24:28 +0200 | [diff] [blame] | 1734 | .recalc = &followparent_recalc, |
| 1735 | }; |
| 1736 | |
| 1737 | /* Intersystem Communication Registers - chassis mode only */ |
| 1738 | static struct clk icr_ick = { |
| 1739 | .name = "icr_ick", |
| 1740 | .parent = &core_l4_ick, |
| 1741 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), |
| 1742 | .enable_bit = OMAP3430_EN_ICR_SHIFT, |
| 1743 | .flags = CLOCK_IN_OMAP343X, |
Paul Walmsley | 333943b | 2008-08-19 11:08:45 +0300 | [diff] [blame] | 1744 | .clkdm_name = "core_l4_clkdm", |
Paul Walmsley | b045d08 | 2008-03-18 11:24:28 +0200 | [diff] [blame] | 1745 | .recalc = &followparent_recalc, |
| 1746 | }; |
| 1747 | |
| 1748 | static struct clk aes2_ick = { |
| 1749 | .name = "aes2_ick", |
| 1750 | .parent = &core_l4_ick, |
| 1751 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), |
| 1752 | .enable_bit = OMAP3430_EN_AES2_SHIFT, |
| 1753 | .flags = CLOCK_IN_OMAP343X, |
Paul Walmsley | 333943b | 2008-08-19 11:08:45 +0300 | [diff] [blame] | 1754 | .clkdm_name = "core_l4_clkdm", |
Paul Walmsley | b045d08 | 2008-03-18 11:24:28 +0200 | [diff] [blame] | 1755 | .recalc = &followparent_recalc, |
| 1756 | }; |
| 1757 | |
| 1758 | static struct clk sha12_ick = { |
| 1759 | .name = "sha12_ick", |
| 1760 | .parent = &core_l4_ick, |
| 1761 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), |
| 1762 | .enable_bit = OMAP3430_EN_SHA12_SHIFT, |
| 1763 | .flags = CLOCK_IN_OMAP343X, |
Paul Walmsley | 333943b | 2008-08-19 11:08:45 +0300 | [diff] [blame] | 1764 | .clkdm_name = "core_l4_clkdm", |
Paul Walmsley | b045d08 | 2008-03-18 11:24:28 +0200 | [diff] [blame] | 1765 | .recalc = &followparent_recalc, |
| 1766 | }; |
| 1767 | |
| 1768 | static struct clk des2_ick = { |
| 1769 | .name = "des2_ick", |
| 1770 | .parent = &core_l4_ick, |
| 1771 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), |
| 1772 | .enable_bit = OMAP3430_EN_DES2_SHIFT, |
| 1773 | .flags = CLOCK_IN_OMAP343X, |
Paul Walmsley | 333943b | 2008-08-19 11:08:45 +0300 | [diff] [blame] | 1774 | .clkdm_name = "core_l4_clkdm", |
Paul Walmsley | b045d08 | 2008-03-18 11:24:28 +0200 | [diff] [blame] | 1775 | .recalc = &followparent_recalc, |
| 1776 | }; |
| 1777 | |
| 1778 | static struct clk mmchs2_ick = { |
| 1779 | .name = "mmchs_ick", |
Tony Lindgren | d887466 | 2008-12-10 17:37:16 -0800 | [diff] [blame] | 1780 | .id = 1, |
Paul Walmsley | b045d08 | 2008-03-18 11:24:28 +0200 | [diff] [blame] | 1781 | .parent = &core_l4_ick, |
| 1782 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), |
| 1783 | .enable_bit = OMAP3430_EN_MMC2_SHIFT, |
| 1784 | .flags = CLOCK_IN_OMAP343X, |
Paul Walmsley | 333943b | 2008-08-19 11:08:45 +0300 | [diff] [blame] | 1785 | .clkdm_name = "core_l4_clkdm", |
Paul Walmsley | b045d08 | 2008-03-18 11:24:28 +0200 | [diff] [blame] | 1786 | .recalc = &followparent_recalc, |
| 1787 | }; |
| 1788 | |
| 1789 | static struct clk mmchs1_ick = { |
| 1790 | .name = "mmchs_ick", |
Paul Walmsley | b045d08 | 2008-03-18 11:24:28 +0200 | [diff] [blame] | 1791 | .parent = &core_l4_ick, |
| 1792 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), |
| 1793 | .enable_bit = OMAP3430_EN_MMC1_SHIFT, |
| 1794 | .flags = CLOCK_IN_OMAP343X, |
Paul Walmsley | 333943b | 2008-08-19 11:08:45 +0300 | [diff] [blame] | 1795 | .clkdm_name = "core_l4_clkdm", |
Paul Walmsley | b045d08 | 2008-03-18 11:24:28 +0200 | [diff] [blame] | 1796 | .recalc = &followparent_recalc, |
| 1797 | }; |
| 1798 | |
| 1799 | static struct clk mspro_ick = { |
| 1800 | .name = "mspro_ick", |
| 1801 | .parent = &core_l4_ick, |
| 1802 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), |
| 1803 | .enable_bit = OMAP3430_EN_MSPRO_SHIFT, |
| 1804 | .flags = CLOCK_IN_OMAP343X, |
Paul Walmsley | 333943b | 2008-08-19 11:08:45 +0300 | [diff] [blame] | 1805 | .clkdm_name = "core_l4_clkdm", |
Paul Walmsley | b045d08 | 2008-03-18 11:24:28 +0200 | [diff] [blame] | 1806 | .recalc = &followparent_recalc, |
| 1807 | }; |
| 1808 | |
| 1809 | static struct clk hdq_ick = { |
| 1810 | .name = "hdq_ick", |
| 1811 | .parent = &core_l4_ick, |
| 1812 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), |
| 1813 | .enable_bit = OMAP3430_EN_HDQ_SHIFT, |
| 1814 | .flags = CLOCK_IN_OMAP343X, |
Paul Walmsley | 333943b | 2008-08-19 11:08:45 +0300 | [diff] [blame] | 1815 | .clkdm_name = "core_l4_clkdm", |
Paul Walmsley | b045d08 | 2008-03-18 11:24:28 +0200 | [diff] [blame] | 1816 | .recalc = &followparent_recalc, |
| 1817 | }; |
| 1818 | |
| 1819 | static struct clk mcspi4_ick = { |
| 1820 | .name = "mcspi_ick", |
| 1821 | .id = 4, |
| 1822 | .parent = &core_l4_ick, |
| 1823 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), |
| 1824 | .enable_bit = OMAP3430_EN_MCSPI4_SHIFT, |
| 1825 | .flags = CLOCK_IN_OMAP343X, |
Paul Walmsley | 333943b | 2008-08-19 11:08:45 +0300 | [diff] [blame] | 1826 | .clkdm_name = "core_l4_clkdm", |
Paul Walmsley | b045d08 | 2008-03-18 11:24:28 +0200 | [diff] [blame] | 1827 | .recalc = &followparent_recalc, |
| 1828 | }; |
| 1829 | |
| 1830 | static struct clk mcspi3_ick = { |
| 1831 | .name = "mcspi_ick", |
| 1832 | .id = 3, |
| 1833 | .parent = &core_l4_ick, |
| 1834 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), |
| 1835 | .enable_bit = OMAP3430_EN_MCSPI3_SHIFT, |
| 1836 | .flags = CLOCK_IN_OMAP343X, |
Paul Walmsley | 333943b | 2008-08-19 11:08:45 +0300 | [diff] [blame] | 1837 | .clkdm_name = "core_l4_clkdm", |
Paul Walmsley | b045d08 | 2008-03-18 11:24:28 +0200 | [diff] [blame] | 1838 | .recalc = &followparent_recalc, |
| 1839 | }; |
| 1840 | |
| 1841 | static struct clk mcspi2_ick = { |
| 1842 | .name = "mcspi_ick", |
| 1843 | .id = 2, |
| 1844 | .parent = &core_l4_ick, |
| 1845 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), |
| 1846 | .enable_bit = OMAP3430_EN_MCSPI2_SHIFT, |
| 1847 | .flags = CLOCK_IN_OMAP343X, |
Paul Walmsley | 333943b | 2008-08-19 11:08:45 +0300 | [diff] [blame] | 1848 | .clkdm_name = "core_l4_clkdm", |
Paul Walmsley | b045d08 | 2008-03-18 11:24:28 +0200 | [diff] [blame] | 1849 | .recalc = &followparent_recalc, |
| 1850 | }; |
| 1851 | |
| 1852 | static struct clk mcspi1_ick = { |
| 1853 | .name = "mcspi_ick", |
| 1854 | .id = 1, |
| 1855 | .parent = &core_l4_ick, |
| 1856 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), |
| 1857 | .enable_bit = OMAP3430_EN_MCSPI1_SHIFT, |
| 1858 | .flags = CLOCK_IN_OMAP343X, |
Paul Walmsley | 333943b | 2008-08-19 11:08:45 +0300 | [diff] [blame] | 1859 | .clkdm_name = "core_l4_clkdm", |
Paul Walmsley | b045d08 | 2008-03-18 11:24:28 +0200 | [diff] [blame] | 1860 | .recalc = &followparent_recalc, |
| 1861 | }; |
| 1862 | |
| 1863 | static struct clk i2c3_ick = { |
| 1864 | .name = "i2c_ick", |
| 1865 | .id = 3, |
| 1866 | .parent = &core_l4_ick, |
| 1867 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), |
| 1868 | .enable_bit = OMAP3430_EN_I2C3_SHIFT, |
| 1869 | .flags = CLOCK_IN_OMAP343X, |
Paul Walmsley | 333943b | 2008-08-19 11:08:45 +0300 | [diff] [blame] | 1870 | .clkdm_name = "core_l4_clkdm", |
Paul Walmsley | b045d08 | 2008-03-18 11:24:28 +0200 | [diff] [blame] | 1871 | .recalc = &followparent_recalc, |
| 1872 | }; |
| 1873 | |
| 1874 | static struct clk i2c2_ick = { |
| 1875 | .name = "i2c_ick", |
| 1876 | .id = 2, |
| 1877 | .parent = &core_l4_ick, |
| 1878 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), |
| 1879 | .enable_bit = OMAP3430_EN_I2C2_SHIFT, |
| 1880 | .flags = CLOCK_IN_OMAP343X, |
Paul Walmsley | 333943b | 2008-08-19 11:08:45 +0300 | [diff] [blame] | 1881 | .clkdm_name = "core_l4_clkdm", |
Paul Walmsley | b045d08 | 2008-03-18 11:24:28 +0200 | [diff] [blame] | 1882 | .recalc = &followparent_recalc, |
| 1883 | }; |
| 1884 | |
| 1885 | static struct clk i2c1_ick = { |
| 1886 | .name = "i2c_ick", |
| 1887 | .id = 1, |
| 1888 | .parent = &core_l4_ick, |
| 1889 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), |
| 1890 | .enable_bit = OMAP3430_EN_I2C1_SHIFT, |
| 1891 | .flags = CLOCK_IN_OMAP343X, |
Paul Walmsley | 333943b | 2008-08-19 11:08:45 +0300 | [diff] [blame] | 1892 | .clkdm_name = "core_l4_clkdm", |
Paul Walmsley | b045d08 | 2008-03-18 11:24:28 +0200 | [diff] [blame] | 1893 | .recalc = &followparent_recalc, |
| 1894 | }; |
| 1895 | |
| 1896 | static struct clk uart2_ick = { |
| 1897 | .name = "uart2_ick", |
| 1898 | .parent = &core_l4_ick, |
| 1899 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), |
| 1900 | .enable_bit = OMAP3430_EN_UART2_SHIFT, |
| 1901 | .flags = CLOCK_IN_OMAP343X, |
Paul Walmsley | 333943b | 2008-08-19 11:08:45 +0300 | [diff] [blame] | 1902 | .clkdm_name = "core_l4_clkdm", |
Paul Walmsley | b045d08 | 2008-03-18 11:24:28 +0200 | [diff] [blame] | 1903 | .recalc = &followparent_recalc, |
| 1904 | }; |
| 1905 | |
| 1906 | static struct clk uart1_ick = { |
| 1907 | .name = "uart1_ick", |
| 1908 | .parent = &core_l4_ick, |
| 1909 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), |
| 1910 | .enable_bit = OMAP3430_EN_UART1_SHIFT, |
| 1911 | .flags = CLOCK_IN_OMAP343X, |
Paul Walmsley | 333943b | 2008-08-19 11:08:45 +0300 | [diff] [blame] | 1912 | .clkdm_name = "core_l4_clkdm", |
Paul Walmsley | b045d08 | 2008-03-18 11:24:28 +0200 | [diff] [blame] | 1913 | .recalc = &followparent_recalc, |
| 1914 | }; |
| 1915 | |
| 1916 | static struct clk gpt11_ick = { |
| 1917 | .name = "gpt11_ick", |
| 1918 | .parent = &core_l4_ick, |
| 1919 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), |
| 1920 | .enable_bit = OMAP3430_EN_GPT11_SHIFT, |
| 1921 | .flags = CLOCK_IN_OMAP343X, |
Paul Walmsley | 333943b | 2008-08-19 11:08:45 +0300 | [diff] [blame] | 1922 | .clkdm_name = "core_l4_clkdm", |
Paul Walmsley | b045d08 | 2008-03-18 11:24:28 +0200 | [diff] [blame] | 1923 | .recalc = &followparent_recalc, |
| 1924 | }; |
| 1925 | |
| 1926 | static struct clk gpt10_ick = { |
| 1927 | .name = "gpt10_ick", |
| 1928 | .parent = &core_l4_ick, |
| 1929 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), |
| 1930 | .enable_bit = OMAP3430_EN_GPT10_SHIFT, |
| 1931 | .flags = CLOCK_IN_OMAP343X, |
Paul Walmsley | 333943b | 2008-08-19 11:08:45 +0300 | [diff] [blame] | 1932 | .clkdm_name = "core_l4_clkdm", |
Paul Walmsley | b045d08 | 2008-03-18 11:24:28 +0200 | [diff] [blame] | 1933 | .recalc = &followparent_recalc, |
| 1934 | }; |
| 1935 | |
| 1936 | static struct clk mcbsp5_ick = { |
Eduardo Valentin | 78673bc | 2008-07-03 12:24:40 +0300 | [diff] [blame] | 1937 | .name = "mcbsp_ick", |
| 1938 | .id = 5, |
Paul Walmsley | b045d08 | 2008-03-18 11:24:28 +0200 | [diff] [blame] | 1939 | .parent = &core_l4_ick, |
| 1940 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), |
| 1941 | .enable_bit = OMAP3430_EN_MCBSP5_SHIFT, |
| 1942 | .flags = CLOCK_IN_OMAP343X, |
Paul Walmsley | 333943b | 2008-08-19 11:08:45 +0300 | [diff] [blame] | 1943 | .clkdm_name = "core_l4_clkdm", |
Paul Walmsley | b045d08 | 2008-03-18 11:24:28 +0200 | [diff] [blame] | 1944 | .recalc = &followparent_recalc, |
| 1945 | }; |
| 1946 | |
| 1947 | static struct clk mcbsp1_ick = { |
Eduardo Valentin | 78673bc | 2008-07-03 12:24:40 +0300 | [diff] [blame] | 1948 | .name = "mcbsp_ick", |
| 1949 | .id = 1, |
Paul Walmsley | b045d08 | 2008-03-18 11:24:28 +0200 | [diff] [blame] | 1950 | .parent = &core_l4_ick, |
| 1951 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), |
| 1952 | .enable_bit = OMAP3430_EN_MCBSP1_SHIFT, |
| 1953 | .flags = CLOCK_IN_OMAP343X, |
Paul Walmsley | 333943b | 2008-08-19 11:08:45 +0300 | [diff] [blame] | 1954 | .clkdm_name = "core_l4_clkdm", |
Paul Walmsley | b045d08 | 2008-03-18 11:24:28 +0200 | [diff] [blame] | 1955 | .recalc = &followparent_recalc, |
| 1956 | }; |
| 1957 | |
| 1958 | static struct clk fac_ick = { |
| 1959 | .name = "fac_ick", |
| 1960 | .parent = &core_l4_ick, |
| 1961 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), |
| 1962 | .enable_bit = OMAP3430ES1_EN_FAC_SHIFT, |
| 1963 | .flags = CLOCK_IN_OMAP3430ES1, |
Paul Walmsley | 333943b | 2008-08-19 11:08:45 +0300 | [diff] [blame] | 1964 | .clkdm_name = "core_l4_clkdm", |
Paul Walmsley | b045d08 | 2008-03-18 11:24:28 +0200 | [diff] [blame] | 1965 | .recalc = &followparent_recalc, |
| 1966 | }; |
| 1967 | |
| 1968 | static struct clk mailboxes_ick = { |
| 1969 | .name = "mailboxes_ick", |
| 1970 | .parent = &core_l4_ick, |
| 1971 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), |
| 1972 | .enable_bit = OMAP3430_EN_MAILBOXES_SHIFT, |
| 1973 | .flags = CLOCK_IN_OMAP343X, |
Paul Walmsley | 333943b | 2008-08-19 11:08:45 +0300 | [diff] [blame] | 1974 | .clkdm_name = "core_l4_clkdm", |
Paul Walmsley | b045d08 | 2008-03-18 11:24:28 +0200 | [diff] [blame] | 1975 | .recalc = &followparent_recalc, |
| 1976 | }; |
| 1977 | |
| 1978 | static struct clk omapctrl_ick = { |
| 1979 | .name = "omapctrl_ick", |
| 1980 | .parent = &core_l4_ick, |
| 1981 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), |
| 1982 | .enable_bit = OMAP3430_EN_OMAPCTRL_SHIFT, |
| 1983 | .flags = CLOCK_IN_OMAP343X | ENABLE_ON_INIT, |
| 1984 | .recalc = &followparent_recalc, |
| 1985 | }; |
| 1986 | |
| 1987 | /* SSI_L4_ICK based clocks */ |
| 1988 | |
| 1989 | static struct clk ssi_l4_ick = { |
| 1990 | .name = "ssi_l4_ick", |
Russell King | 5713718 | 2008-11-04 16:48:35 +0000 | [diff] [blame^] | 1991 | .ops = &clkops_null, |
Paul Walmsley | b045d08 | 2008-03-18 11:24:28 +0200 | [diff] [blame] | 1992 | .parent = &l4_ick, |
Russell King | 5713718 | 2008-11-04 16:48:35 +0000 | [diff] [blame^] | 1993 | .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES, |
Paul Walmsley | 333943b | 2008-08-19 11:08:45 +0300 | [diff] [blame] | 1994 | .clkdm_name = "core_l4_clkdm", |
Paul Walmsley | b045d08 | 2008-03-18 11:24:28 +0200 | [diff] [blame] | 1995 | .recalc = &followparent_recalc, |
| 1996 | }; |
| 1997 | |
| 1998 | static struct clk ssi_ick = { |
| 1999 | .name = "ssi_ick", |
| 2000 | .parent = &ssi_l4_ick, |
| 2001 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), |
| 2002 | .enable_bit = OMAP3430_EN_SSI_SHIFT, |
| 2003 | .flags = CLOCK_IN_OMAP343X, |
Paul Walmsley | 333943b | 2008-08-19 11:08:45 +0300 | [diff] [blame] | 2004 | .clkdm_name = "core_l4_clkdm", |
Paul Walmsley | b045d08 | 2008-03-18 11:24:28 +0200 | [diff] [blame] | 2005 | .recalc = &followparent_recalc, |
| 2006 | }; |
| 2007 | |
| 2008 | /* REVISIT: Technically the TRM claims that this is CORE_CLK based, |
| 2009 | * but l4_ick makes more sense to me */ |
| 2010 | |
| 2011 | static const struct clksel usb_l4_clksel[] = { |
| 2012 | { .parent = &l4_ick, .rates = div2_rates }, |
| 2013 | { .parent = NULL }, |
| 2014 | }; |
| 2015 | |
| 2016 | static struct clk usb_l4_ick = { |
| 2017 | .name = "usb_l4_ick", |
| 2018 | .parent = &l4_ick, |
| 2019 | .init = &omap2_init_clksel_parent, |
| 2020 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), |
| 2021 | .enable_bit = OMAP3430ES1_EN_FSHOSTUSB_SHIFT, |
| 2022 | .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL), |
| 2023 | .clksel_mask = OMAP3430ES1_CLKSEL_FSHOSTUSB_MASK, |
| 2024 | .clksel = usb_l4_clksel, |
| 2025 | .flags = CLOCK_IN_OMAP3430ES1, |
| 2026 | .recalc = &omap2_clksel_recalc, |
| 2027 | }; |
| 2028 | |
| 2029 | /* XXX MDM_INTC_ICK, SAD2D_ICK ?? */ |
| 2030 | |
| 2031 | /* SECURITY_L4_ICK2 based clocks */ |
| 2032 | |
| 2033 | static struct clk security_l4_ick2 = { |
| 2034 | .name = "security_l4_ick2", |
Russell King | 5713718 | 2008-11-04 16:48:35 +0000 | [diff] [blame^] | 2035 | .ops = &clkops_null, |
Paul Walmsley | b045d08 | 2008-03-18 11:24:28 +0200 | [diff] [blame] | 2036 | .parent = &l4_ick, |
Russell King | 5713718 | 2008-11-04 16:48:35 +0000 | [diff] [blame^] | 2037 | .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES, |
Paul Walmsley | b045d08 | 2008-03-18 11:24:28 +0200 | [diff] [blame] | 2038 | .recalc = &followparent_recalc, |
| 2039 | }; |
| 2040 | |
| 2041 | static struct clk aes1_ick = { |
| 2042 | .name = "aes1_ick", |
| 2043 | .parent = &security_l4_ick2, |
| 2044 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2), |
| 2045 | .enable_bit = OMAP3430_EN_AES1_SHIFT, |
| 2046 | .flags = CLOCK_IN_OMAP343X, |
| 2047 | .recalc = &followparent_recalc, |
| 2048 | }; |
| 2049 | |
| 2050 | static struct clk rng_ick = { |
| 2051 | .name = "rng_ick", |
| 2052 | .parent = &security_l4_ick2, |
| 2053 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2), |
| 2054 | .enable_bit = OMAP3430_EN_RNG_SHIFT, |
| 2055 | .flags = CLOCK_IN_OMAP343X, |
| 2056 | .recalc = &followparent_recalc, |
| 2057 | }; |
| 2058 | |
| 2059 | static struct clk sha11_ick = { |
| 2060 | .name = "sha11_ick", |
| 2061 | .parent = &security_l4_ick2, |
| 2062 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2), |
| 2063 | .enable_bit = OMAP3430_EN_SHA11_SHIFT, |
| 2064 | .flags = CLOCK_IN_OMAP343X, |
| 2065 | .recalc = &followparent_recalc, |
| 2066 | }; |
| 2067 | |
| 2068 | static struct clk des1_ick = { |
| 2069 | .name = "des1_ick", |
| 2070 | .parent = &security_l4_ick2, |
| 2071 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2), |
| 2072 | .enable_bit = OMAP3430_EN_DES1_SHIFT, |
| 2073 | .flags = CLOCK_IN_OMAP343X, |
| 2074 | .recalc = &followparent_recalc, |
| 2075 | }; |
| 2076 | |
| 2077 | /* DSS */ |
Roman Tereshonkov | 3760d31 | 2008-03-13 21:35:09 +0200 | [diff] [blame] | 2078 | static const struct clksel dss1_alwon_fck_clksel[] = { |
Paul Walmsley | 333943b | 2008-08-19 11:08:45 +0300 | [diff] [blame] | 2079 | { .parent = &sys_ck, .rates = dpll_bypass_rates }, |
Roman Tereshonkov | 3760d31 | 2008-03-13 21:35:09 +0200 | [diff] [blame] | 2080 | { .parent = &dpll4_m4x2_ck, .rates = dpll_locked_rates }, |
| 2081 | { .parent = NULL } |
| 2082 | }; |
Paul Walmsley | b045d08 | 2008-03-18 11:24:28 +0200 | [diff] [blame] | 2083 | |
| 2084 | static struct clk dss1_alwon_fck = { |
| 2085 | .name = "dss1_alwon_fck", |
| 2086 | .parent = &dpll4_m4x2_ck, |
Roman Tereshonkov | 3760d31 | 2008-03-13 21:35:09 +0200 | [diff] [blame] | 2087 | .init = &omap2_init_clksel_parent, |
Paul Walmsley | b045d08 | 2008-03-18 11:24:28 +0200 | [diff] [blame] | 2088 | .enable_reg = OMAP_CM_REGADDR(OMAP3430_DSS_MOD, CM_FCLKEN), |
| 2089 | .enable_bit = OMAP3430_EN_DSS1_SHIFT, |
Roman Tereshonkov | 3760d31 | 2008-03-13 21:35:09 +0200 | [diff] [blame] | 2090 | .clksel_reg = OMAP_CM_REGADDR(PLL_MOD, CM_IDLEST), |
Paul Walmsley | 542313c | 2008-07-03 12:24:45 +0300 | [diff] [blame] | 2091 | .clksel_mask = OMAP3430_ST_PERIPH_CLK_MASK, |
Roman Tereshonkov | 3760d31 | 2008-03-13 21:35:09 +0200 | [diff] [blame] | 2092 | .clksel = dss1_alwon_fck_clksel, |
Paul Walmsley | b045d08 | 2008-03-18 11:24:28 +0200 | [diff] [blame] | 2093 | .flags = CLOCK_IN_OMAP343X, |
Paul Walmsley | 333943b | 2008-08-19 11:08:45 +0300 | [diff] [blame] | 2094 | .clkdm_name = "dss_clkdm", |
Roman Tereshonkov | 3760d31 | 2008-03-13 21:35:09 +0200 | [diff] [blame] | 2095 | .recalc = &omap2_clksel_recalc, |
Paul Walmsley | b045d08 | 2008-03-18 11:24:28 +0200 | [diff] [blame] | 2096 | }; |
| 2097 | |
| 2098 | static struct clk dss_tv_fck = { |
| 2099 | .name = "dss_tv_fck", |
| 2100 | .parent = &omap_54m_fck, |
Paul Walmsley | 333943b | 2008-08-19 11:08:45 +0300 | [diff] [blame] | 2101 | .init = &omap2_init_clk_clkdm, |
Paul Walmsley | b045d08 | 2008-03-18 11:24:28 +0200 | [diff] [blame] | 2102 | .enable_reg = OMAP_CM_REGADDR(OMAP3430_DSS_MOD, CM_FCLKEN), |
| 2103 | .enable_bit = OMAP3430_EN_TV_SHIFT, |
| 2104 | .flags = CLOCK_IN_OMAP343X, |
Paul Walmsley | 333943b | 2008-08-19 11:08:45 +0300 | [diff] [blame] | 2105 | .clkdm_name = "dss_clkdm", |
Paul Walmsley | b045d08 | 2008-03-18 11:24:28 +0200 | [diff] [blame] | 2106 | .recalc = &followparent_recalc, |
| 2107 | }; |
| 2108 | |
| 2109 | static struct clk dss_96m_fck = { |
| 2110 | .name = "dss_96m_fck", |
| 2111 | .parent = &omap_96m_fck, |
Paul Walmsley | 333943b | 2008-08-19 11:08:45 +0300 | [diff] [blame] | 2112 | .init = &omap2_init_clk_clkdm, |
Paul Walmsley | b045d08 | 2008-03-18 11:24:28 +0200 | [diff] [blame] | 2113 | .enable_reg = OMAP_CM_REGADDR(OMAP3430_DSS_MOD, CM_FCLKEN), |
| 2114 | .enable_bit = OMAP3430_EN_TV_SHIFT, |
| 2115 | .flags = CLOCK_IN_OMAP343X, |
Paul Walmsley | 333943b | 2008-08-19 11:08:45 +0300 | [diff] [blame] | 2116 | .clkdm_name = "dss_clkdm", |
Paul Walmsley | b045d08 | 2008-03-18 11:24:28 +0200 | [diff] [blame] | 2117 | .recalc = &followparent_recalc, |
| 2118 | }; |
| 2119 | |
| 2120 | static struct clk dss2_alwon_fck = { |
| 2121 | .name = "dss2_alwon_fck", |
| 2122 | .parent = &sys_ck, |
Paul Walmsley | 333943b | 2008-08-19 11:08:45 +0300 | [diff] [blame] | 2123 | .init = &omap2_init_clk_clkdm, |
Paul Walmsley | b045d08 | 2008-03-18 11:24:28 +0200 | [diff] [blame] | 2124 | .enable_reg = OMAP_CM_REGADDR(OMAP3430_DSS_MOD, CM_FCLKEN), |
| 2125 | .enable_bit = OMAP3430_EN_DSS2_SHIFT, |
| 2126 | .flags = CLOCK_IN_OMAP343X, |
Paul Walmsley | 333943b | 2008-08-19 11:08:45 +0300 | [diff] [blame] | 2127 | .clkdm_name = "dss_clkdm", |
Paul Walmsley | b045d08 | 2008-03-18 11:24:28 +0200 | [diff] [blame] | 2128 | .recalc = &followparent_recalc, |
| 2129 | }; |
| 2130 | |
| 2131 | static struct clk dss_ick = { |
| 2132 | /* Handles both L3 and L4 clocks */ |
| 2133 | .name = "dss_ick", |
| 2134 | .parent = &l4_ick, |
Paul Walmsley | 333943b | 2008-08-19 11:08:45 +0300 | [diff] [blame] | 2135 | .init = &omap2_init_clk_clkdm, |
Paul Walmsley | b045d08 | 2008-03-18 11:24:28 +0200 | [diff] [blame] | 2136 | .enable_reg = OMAP_CM_REGADDR(OMAP3430_DSS_MOD, CM_ICLKEN), |
| 2137 | .enable_bit = OMAP3430_CM_ICLKEN_DSS_EN_DSS_SHIFT, |
| 2138 | .flags = CLOCK_IN_OMAP343X, |
Paul Walmsley | 333943b | 2008-08-19 11:08:45 +0300 | [diff] [blame] | 2139 | .clkdm_name = "dss_clkdm", |
Paul Walmsley | b045d08 | 2008-03-18 11:24:28 +0200 | [diff] [blame] | 2140 | .recalc = &followparent_recalc, |
| 2141 | }; |
| 2142 | |
| 2143 | /* CAM */ |
| 2144 | |
Roman Tereshonkov | 3760d31 | 2008-03-13 21:35:09 +0200 | [diff] [blame] | 2145 | static const struct clksel cam_mclk_clksel[] = { |
Paul Walmsley | 333943b | 2008-08-19 11:08:45 +0300 | [diff] [blame] | 2146 | { .parent = &sys_ck, .rates = dpll_bypass_rates }, |
Roman Tereshonkov | 3760d31 | 2008-03-13 21:35:09 +0200 | [diff] [blame] | 2147 | { .parent = &dpll4_m5x2_ck, .rates = dpll_locked_rates }, |
| 2148 | { .parent = NULL } |
| 2149 | }; |
| 2150 | |
Paul Walmsley | b045d08 | 2008-03-18 11:24:28 +0200 | [diff] [blame] | 2151 | static struct clk cam_mclk = { |
| 2152 | .name = "cam_mclk", |
| 2153 | .parent = &dpll4_m5x2_ck, |
Roman Tereshonkov | 3760d31 | 2008-03-13 21:35:09 +0200 | [diff] [blame] | 2154 | .init = &omap2_init_clksel_parent, |
| 2155 | .clksel_reg = OMAP_CM_REGADDR(PLL_MOD, CM_IDLEST), |
Paul Walmsley | 542313c | 2008-07-03 12:24:45 +0300 | [diff] [blame] | 2156 | .clksel_mask = OMAP3430_ST_PERIPH_CLK_MASK, |
Roman Tereshonkov | 3760d31 | 2008-03-13 21:35:09 +0200 | [diff] [blame] | 2157 | .clksel = cam_mclk_clksel, |
Paul Walmsley | b045d08 | 2008-03-18 11:24:28 +0200 | [diff] [blame] | 2158 | .enable_reg = OMAP_CM_REGADDR(OMAP3430_CAM_MOD, CM_FCLKEN), |
| 2159 | .enable_bit = OMAP3430_EN_CAM_SHIFT, |
| 2160 | .flags = CLOCK_IN_OMAP343X, |
Paul Walmsley | 333943b | 2008-08-19 11:08:45 +0300 | [diff] [blame] | 2161 | .clkdm_name = "cam_clkdm", |
Roman Tereshonkov | 3760d31 | 2008-03-13 21:35:09 +0200 | [diff] [blame] | 2162 | .recalc = &omap2_clksel_recalc, |
Paul Walmsley | b045d08 | 2008-03-18 11:24:28 +0200 | [diff] [blame] | 2163 | }; |
| 2164 | |
Högander Jouni | 5955902 | 2008-08-19 11:08:45 +0300 | [diff] [blame] | 2165 | static struct clk cam_ick = { |
| 2166 | /* Handles both L3 and L4 clocks */ |
| 2167 | .name = "cam_ick", |
Paul Walmsley | b045d08 | 2008-03-18 11:24:28 +0200 | [diff] [blame] | 2168 | .parent = &l4_ick, |
Paul Walmsley | 333943b | 2008-08-19 11:08:45 +0300 | [diff] [blame] | 2169 | .init = &omap2_init_clk_clkdm, |
Paul Walmsley | b045d08 | 2008-03-18 11:24:28 +0200 | [diff] [blame] | 2170 | .enable_reg = OMAP_CM_REGADDR(OMAP3430_CAM_MOD, CM_ICLKEN), |
| 2171 | .enable_bit = OMAP3430_EN_CAM_SHIFT, |
| 2172 | .flags = CLOCK_IN_OMAP343X, |
Paul Walmsley | 333943b | 2008-08-19 11:08:45 +0300 | [diff] [blame] | 2173 | .clkdm_name = "cam_clkdm", |
Paul Walmsley | b045d08 | 2008-03-18 11:24:28 +0200 | [diff] [blame] | 2174 | .recalc = &followparent_recalc, |
| 2175 | }; |
| 2176 | |
| 2177 | /* USBHOST - 3430ES2 only */ |
| 2178 | |
| 2179 | static struct clk usbhost_120m_fck = { |
| 2180 | .name = "usbhost_120m_fck", |
| 2181 | .parent = &omap_120m_fck, |
Paul Walmsley | 333943b | 2008-08-19 11:08:45 +0300 | [diff] [blame] | 2182 | .init = &omap2_init_clk_clkdm, |
Paul Walmsley | b045d08 | 2008-03-18 11:24:28 +0200 | [diff] [blame] | 2183 | .enable_reg = OMAP_CM_REGADDR(OMAP3430ES2_USBHOST_MOD, CM_FCLKEN), |
| 2184 | .enable_bit = OMAP3430ES2_EN_USBHOST2_SHIFT, |
| 2185 | .flags = CLOCK_IN_OMAP3430ES2, |
Paul Walmsley | 333943b | 2008-08-19 11:08:45 +0300 | [diff] [blame] | 2186 | .clkdm_name = "usbhost_clkdm", |
Paul Walmsley | b045d08 | 2008-03-18 11:24:28 +0200 | [diff] [blame] | 2187 | .recalc = &followparent_recalc, |
| 2188 | }; |
| 2189 | |
| 2190 | static struct clk usbhost_48m_fck = { |
| 2191 | .name = "usbhost_48m_fck", |
| 2192 | .parent = &omap_48m_fck, |
Paul Walmsley | 333943b | 2008-08-19 11:08:45 +0300 | [diff] [blame] | 2193 | .init = &omap2_init_clk_clkdm, |
Paul Walmsley | b045d08 | 2008-03-18 11:24:28 +0200 | [diff] [blame] | 2194 | .enable_reg = OMAP_CM_REGADDR(OMAP3430ES2_USBHOST_MOD, CM_FCLKEN), |
| 2195 | .enable_bit = OMAP3430ES2_EN_USBHOST1_SHIFT, |
| 2196 | .flags = CLOCK_IN_OMAP3430ES2, |
Paul Walmsley | 333943b | 2008-08-19 11:08:45 +0300 | [diff] [blame] | 2197 | .clkdm_name = "usbhost_clkdm", |
Paul Walmsley | b045d08 | 2008-03-18 11:24:28 +0200 | [diff] [blame] | 2198 | .recalc = &followparent_recalc, |
| 2199 | }; |
| 2200 | |
Högander Jouni | 5955902 | 2008-08-19 11:08:45 +0300 | [diff] [blame] | 2201 | static struct clk usbhost_ick = { |
| 2202 | /* Handles both L3 and L4 clocks */ |
| 2203 | .name = "usbhost_ick", |
Paul Walmsley | b045d08 | 2008-03-18 11:24:28 +0200 | [diff] [blame] | 2204 | .parent = &l4_ick, |
Paul Walmsley | 333943b | 2008-08-19 11:08:45 +0300 | [diff] [blame] | 2205 | .init = &omap2_init_clk_clkdm, |
Paul Walmsley | b045d08 | 2008-03-18 11:24:28 +0200 | [diff] [blame] | 2206 | .enable_reg = OMAP_CM_REGADDR(OMAP3430ES2_USBHOST_MOD, CM_ICLKEN), |
| 2207 | .enable_bit = OMAP3430ES2_EN_USBHOST_SHIFT, |
| 2208 | .flags = CLOCK_IN_OMAP3430ES2, |
Paul Walmsley | 333943b | 2008-08-19 11:08:45 +0300 | [diff] [blame] | 2209 | .clkdm_name = "usbhost_clkdm", |
Paul Walmsley | b045d08 | 2008-03-18 11:24:28 +0200 | [diff] [blame] | 2210 | .recalc = &followparent_recalc, |
| 2211 | }; |
| 2212 | |
| 2213 | static struct clk usbhost_sar_fck = { |
| 2214 | .name = "usbhost_sar_fck", |
| 2215 | .parent = &osc_sys_ck, |
Paul Walmsley | 333943b | 2008-08-19 11:08:45 +0300 | [diff] [blame] | 2216 | .init = &omap2_init_clk_clkdm, |
Paul Walmsley | b045d08 | 2008-03-18 11:24:28 +0200 | [diff] [blame] | 2217 | .enable_reg = OMAP_PRM_REGADDR(OMAP3430ES2_USBHOST_MOD, PM_PWSTCTRL), |
| 2218 | .enable_bit = OMAP3430ES2_SAVEANDRESTORE_SHIFT, |
| 2219 | .flags = CLOCK_IN_OMAP3430ES2, |
Paul Walmsley | 333943b | 2008-08-19 11:08:45 +0300 | [diff] [blame] | 2220 | .clkdm_name = "usbhost_clkdm", |
Paul Walmsley | b045d08 | 2008-03-18 11:24:28 +0200 | [diff] [blame] | 2221 | .recalc = &followparent_recalc, |
| 2222 | }; |
| 2223 | |
| 2224 | /* WKUP */ |
| 2225 | |
| 2226 | static const struct clksel_rate usim_96m_rates[] = { |
| 2227 | { .div = 2, .val = 3, .flags = RATE_IN_343X | DEFAULT_RATE }, |
| 2228 | { .div = 4, .val = 4, .flags = RATE_IN_343X }, |
| 2229 | { .div = 8, .val = 5, .flags = RATE_IN_343X }, |
| 2230 | { .div = 10, .val = 6, .flags = RATE_IN_343X }, |
| 2231 | { .div = 0 }, |
| 2232 | }; |
| 2233 | |
| 2234 | static const struct clksel_rate usim_120m_rates[] = { |
| 2235 | { .div = 4, .val = 7, .flags = RATE_IN_343X | DEFAULT_RATE }, |
| 2236 | { .div = 8, .val = 8, .flags = RATE_IN_343X }, |
| 2237 | { .div = 16, .val = 9, .flags = RATE_IN_343X }, |
| 2238 | { .div = 20, .val = 10, .flags = RATE_IN_343X }, |
| 2239 | { .div = 0 }, |
| 2240 | }; |
| 2241 | |
| 2242 | static const struct clksel usim_clksel[] = { |
| 2243 | { .parent = &omap_96m_fck, .rates = usim_96m_rates }, |
| 2244 | { .parent = &omap_120m_fck, .rates = usim_120m_rates }, |
| 2245 | { .parent = &sys_ck, .rates = div2_rates }, |
| 2246 | { .parent = NULL }, |
| 2247 | }; |
| 2248 | |
| 2249 | /* 3430ES2 only */ |
| 2250 | static struct clk usim_fck = { |
| 2251 | .name = "usim_fck", |
| 2252 | .init = &omap2_init_clksel_parent, |
| 2253 | .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_FCLKEN), |
| 2254 | .enable_bit = OMAP3430ES2_EN_USIMOCP_SHIFT, |
| 2255 | .clksel_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_CLKSEL), |
| 2256 | .clksel_mask = OMAP3430ES2_CLKSEL_USIMOCP_MASK, |
| 2257 | .clksel = usim_clksel, |
| 2258 | .flags = CLOCK_IN_OMAP3430ES2, |
| 2259 | .recalc = &omap2_clksel_recalc, |
| 2260 | }; |
| 2261 | |
Paul Walmsley | 333943b | 2008-08-19 11:08:45 +0300 | [diff] [blame] | 2262 | /* XXX should gpt1's clksel have wkup_32k_fck as the 32k opt? */ |
Paul Walmsley | b045d08 | 2008-03-18 11:24:28 +0200 | [diff] [blame] | 2263 | static struct clk gpt1_fck = { |
| 2264 | .name = "gpt1_fck", |
| 2265 | .init = &omap2_init_clksel_parent, |
| 2266 | .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_FCLKEN), |
| 2267 | .enable_bit = OMAP3430_EN_GPT1_SHIFT, |
| 2268 | .clksel_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_CLKSEL), |
| 2269 | .clksel_mask = OMAP3430_CLKSEL_GPT1_MASK, |
| 2270 | .clksel = omap343x_gpt_clksel, |
| 2271 | .flags = CLOCK_IN_OMAP343X, |
Paul Walmsley | 333943b | 2008-08-19 11:08:45 +0300 | [diff] [blame] | 2272 | .clkdm_name = "wkup_clkdm", |
Paul Walmsley | b045d08 | 2008-03-18 11:24:28 +0200 | [diff] [blame] | 2273 | .recalc = &omap2_clksel_recalc, |
| 2274 | }; |
| 2275 | |
| 2276 | static struct clk wkup_32k_fck = { |
| 2277 | .name = "wkup_32k_fck", |
Russell King | 897dcde | 2008-11-04 16:35:03 +0000 | [diff] [blame] | 2278 | .ops = &clkops_null, |
Paul Walmsley | 333943b | 2008-08-19 11:08:45 +0300 | [diff] [blame] | 2279 | .init = &omap2_init_clk_clkdm, |
Paul Walmsley | b045d08 | 2008-03-18 11:24:28 +0200 | [diff] [blame] | 2280 | .parent = &omap_32k_fck, |
Russell King | 897dcde | 2008-11-04 16:35:03 +0000 | [diff] [blame] | 2281 | .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES, |
Paul Walmsley | 333943b | 2008-08-19 11:08:45 +0300 | [diff] [blame] | 2282 | .clkdm_name = "wkup_clkdm", |
Paul Walmsley | b045d08 | 2008-03-18 11:24:28 +0200 | [diff] [blame] | 2283 | .recalc = &followparent_recalc, |
| 2284 | }; |
| 2285 | |
Jouni Hogander | 89db948 | 2008-12-10 17:35:24 -0800 | [diff] [blame] | 2286 | static struct clk gpio1_dbck = { |
| 2287 | .name = "gpio1_dbck", |
Paul Walmsley | b045d08 | 2008-03-18 11:24:28 +0200 | [diff] [blame] | 2288 | .parent = &wkup_32k_fck, |
| 2289 | .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_FCLKEN), |
| 2290 | .enable_bit = OMAP3430_EN_GPIO1_SHIFT, |
| 2291 | .flags = CLOCK_IN_OMAP343X, |
Paul Walmsley | 333943b | 2008-08-19 11:08:45 +0300 | [diff] [blame] | 2292 | .clkdm_name = "wkup_clkdm", |
Paul Walmsley | b045d08 | 2008-03-18 11:24:28 +0200 | [diff] [blame] | 2293 | .recalc = &followparent_recalc, |
| 2294 | }; |
| 2295 | |
| 2296 | static struct clk wdt2_fck = { |
| 2297 | .name = "wdt2_fck", |
| 2298 | .parent = &wkup_32k_fck, |
| 2299 | .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_FCLKEN), |
| 2300 | .enable_bit = OMAP3430_EN_WDT2_SHIFT, |
| 2301 | .flags = CLOCK_IN_OMAP343X, |
Paul Walmsley | 333943b | 2008-08-19 11:08:45 +0300 | [diff] [blame] | 2302 | .clkdm_name = "wkup_clkdm", |
Paul Walmsley | b045d08 | 2008-03-18 11:24:28 +0200 | [diff] [blame] | 2303 | .recalc = &followparent_recalc, |
| 2304 | }; |
| 2305 | |
| 2306 | static struct clk wkup_l4_ick = { |
| 2307 | .name = "wkup_l4_ick", |
Russell King | 897dcde | 2008-11-04 16:35:03 +0000 | [diff] [blame] | 2308 | .ops = &clkops_null, |
Paul Walmsley | b045d08 | 2008-03-18 11:24:28 +0200 | [diff] [blame] | 2309 | .parent = &sys_ck, |
Russell King | 897dcde | 2008-11-04 16:35:03 +0000 | [diff] [blame] | 2310 | .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES, |
Paul Walmsley | 333943b | 2008-08-19 11:08:45 +0300 | [diff] [blame] | 2311 | .clkdm_name = "wkup_clkdm", |
Paul Walmsley | b045d08 | 2008-03-18 11:24:28 +0200 | [diff] [blame] | 2312 | .recalc = &followparent_recalc, |
| 2313 | }; |
| 2314 | |
| 2315 | /* 3430ES2 only */ |
| 2316 | /* Never specifically named in the TRM, so we have to infer a likely name */ |
| 2317 | static struct clk usim_ick = { |
| 2318 | .name = "usim_ick", |
| 2319 | .parent = &wkup_l4_ick, |
| 2320 | .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN), |
| 2321 | .enable_bit = OMAP3430ES2_EN_USIMOCP_SHIFT, |
| 2322 | .flags = CLOCK_IN_OMAP3430ES2, |
Paul Walmsley | 333943b | 2008-08-19 11:08:45 +0300 | [diff] [blame] | 2323 | .clkdm_name = "wkup_clkdm", |
Paul Walmsley | b045d08 | 2008-03-18 11:24:28 +0200 | [diff] [blame] | 2324 | .recalc = &followparent_recalc, |
| 2325 | }; |
| 2326 | |
| 2327 | static struct clk wdt2_ick = { |
| 2328 | .name = "wdt2_ick", |
| 2329 | .parent = &wkup_l4_ick, |
| 2330 | .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN), |
| 2331 | .enable_bit = OMAP3430_EN_WDT2_SHIFT, |
| 2332 | .flags = CLOCK_IN_OMAP343X, |
Paul Walmsley | 333943b | 2008-08-19 11:08:45 +0300 | [diff] [blame] | 2333 | .clkdm_name = "wkup_clkdm", |
Paul Walmsley | b045d08 | 2008-03-18 11:24:28 +0200 | [diff] [blame] | 2334 | .recalc = &followparent_recalc, |
| 2335 | }; |
| 2336 | |
| 2337 | static struct clk wdt1_ick = { |
| 2338 | .name = "wdt1_ick", |
| 2339 | .parent = &wkup_l4_ick, |
| 2340 | .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN), |
| 2341 | .enable_bit = OMAP3430_EN_WDT1_SHIFT, |
| 2342 | .flags = CLOCK_IN_OMAP343X, |
Paul Walmsley | 333943b | 2008-08-19 11:08:45 +0300 | [diff] [blame] | 2343 | .clkdm_name = "wkup_clkdm", |
Paul Walmsley | b045d08 | 2008-03-18 11:24:28 +0200 | [diff] [blame] | 2344 | .recalc = &followparent_recalc, |
| 2345 | }; |
| 2346 | |
| 2347 | static struct clk gpio1_ick = { |
| 2348 | .name = "gpio1_ick", |
| 2349 | .parent = &wkup_l4_ick, |
| 2350 | .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN), |
| 2351 | .enable_bit = OMAP3430_EN_GPIO1_SHIFT, |
| 2352 | .flags = CLOCK_IN_OMAP343X, |
Paul Walmsley | 333943b | 2008-08-19 11:08:45 +0300 | [diff] [blame] | 2353 | .clkdm_name = "wkup_clkdm", |
Paul Walmsley | b045d08 | 2008-03-18 11:24:28 +0200 | [diff] [blame] | 2354 | .recalc = &followparent_recalc, |
| 2355 | }; |
| 2356 | |
| 2357 | static struct clk omap_32ksync_ick = { |
| 2358 | .name = "omap_32ksync_ick", |
| 2359 | .parent = &wkup_l4_ick, |
| 2360 | .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN), |
| 2361 | .enable_bit = OMAP3430_EN_32KSYNC_SHIFT, |
| 2362 | .flags = CLOCK_IN_OMAP343X, |
Paul Walmsley | 333943b | 2008-08-19 11:08:45 +0300 | [diff] [blame] | 2363 | .clkdm_name = "wkup_clkdm", |
Paul Walmsley | b045d08 | 2008-03-18 11:24:28 +0200 | [diff] [blame] | 2364 | .recalc = &followparent_recalc, |
| 2365 | }; |
| 2366 | |
Paul Walmsley | 333943b | 2008-08-19 11:08:45 +0300 | [diff] [blame] | 2367 | /* XXX This clock no longer exists in 3430 TRM rev F */ |
Paul Walmsley | b045d08 | 2008-03-18 11:24:28 +0200 | [diff] [blame] | 2368 | static struct clk gpt12_ick = { |
| 2369 | .name = "gpt12_ick", |
| 2370 | .parent = &wkup_l4_ick, |
| 2371 | .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN), |
| 2372 | .enable_bit = OMAP3430_EN_GPT12_SHIFT, |
| 2373 | .flags = CLOCK_IN_OMAP343X, |
Paul Walmsley | 333943b | 2008-08-19 11:08:45 +0300 | [diff] [blame] | 2374 | .clkdm_name = "wkup_clkdm", |
Paul Walmsley | b045d08 | 2008-03-18 11:24:28 +0200 | [diff] [blame] | 2375 | .recalc = &followparent_recalc, |
| 2376 | }; |
| 2377 | |
| 2378 | static struct clk gpt1_ick = { |
| 2379 | .name = "gpt1_ick", |
| 2380 | .parent = &wkup_l4_ick, |
| 2381 | .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN), |
| 2382 | .enable_bit = OMAP3430_EN_GPT1_SHIFT, |
| 2383 | .flags = CLOCK_IN_OMAP343X, |
Paul Walmsley | 333943b | 2008-08-19 11:08:45 +0300 | [diff] [blame] | 2384 | .clkdm_name = "wkup_clkdm", |
Paul Walmsley | b045d08 | 2008-03-18 11:24:28 +0200 | [diff] [blame] | 2385 | .recalc = &followparent_recalc, |
| 2386 | }; |
| 2387 | |
| 2388 | |
| 2389 | |
| 2390 | /* PER clock domain */ |
| 2391 | |
| 2392 | static struct clk per_96m_fck = { |
| 2393 | .name = "per_96m_fck", |
Russell King | 5713718 | 2008-11-04 16:48:35 +0000 | [diff] [blame^] | 2394 | .ops = &clkops_null, |
Paul Walmsley | b045d08 | 2008-03-18 11:24:28 +0200 | [diff] [blame] | 2395 | .parent = &omap_96m_alwon_fck, |
Paul Walmsley | 333943b | 2008-08-19 11:08:45 +0300 | [diff] [blame] | 2396 | .init = &omap2_init_clk_clkdm, |
Russell King | 5713718 | 2008-11-04 16:48:35 +0000 | [diff] [blame^] | 2397 | .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES, |
Paul Walmsley | 333943b | 2008-08-19 11:08:45 +0300 | [diff] [blame] | 2398 | .clkdm_name = "per_clkdm", |
Paul Walmsley | b045d08 | 2008-03-18 11:24:28 +0200 | [diff] [blame] | 2399 | .recalc = &followparent_recalc, |
| 2400 | }; |
| 2401 | |
| 2402 | static struct clk per_48m_fck = { |
| 2403 | .name = "per_48m_fck", |
Russell King | 5713718 | 2008-11-04 16:48:35 +0000 | [diff] [blame^] | 2404 | .ops = &clkops_null, |
Paul Walmsley | b045d08 | 2008-03-18 11:24:28 +0200 | [diff] [blame] | 2405 | .parent = &omap_48m_fck, |
Paul Walmsley | 333943b | 2008-08-19 11:08:45 +0300 | [diff] [blame] | 2406 | .init = &omap2_init_clk_clkdm, |
Russell King | 5713718 | 2008-11-04 16:48:35 +0000 | [diff] [blame^] | 2407 | .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES, |
Paul Walmsley | 333943b | 2008-08-19 11:08:45 +0300 | [diff] [blame] | 2408 | .clkdm_name = "per_clkdm", |
Paul Walmsley | b045d08 | 2008-03-18 11:24:28 +0200 | [diff] [blame] | 2409 | .recalc = &followparent_recalc, |
| 2410 | }; |
| 2411 | |
| 2412 | static struct clk uart3_fck = { |
| 2413 | .name = "uart3_fck", |
| 2414 | .parent = &per_48m_fck, |
| 2415 | .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN), |
| 2416 | .enable_bit = OMAP3430_EN_UART3_SHIFT, |
| 2417 | .flags = CLOCK_IN_OMAP343X, |
Paul Walmsley | 333943b | 2008-08-19 11:08:45 +0300 | [diff] [blame] | 2418 | .clkdm_name = "per_clkdm", |
Paul Walmsley | b045d08 | 2008-03-18 11:24:28 +0200 | [diff] [blame] | 2419 | .recalc = &followparent_recalc, |
| 2420 | }; |
| 2421 | |
| 2422 | static struct clk gpt2_fck = { |
| 2423 | .name = "gpt2_fck", |
| 2424 | .init = &omap2_init_clksel_parent, |
| 2425 | .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN), |
| 2426 | .enable_bit = OMAP3430_EN_GPT2_SHIFT, |
| 2427 | .clksel_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_CLKSEL), |
| 2428 | .clksel_mask = OMAP3430_CLKSEL_GPT2_MASK, |
| 2429 | .clksel = omap343x_gpt_clksel, |
| 2430 | .flags = CLOCK_IN_OMAP343X, |
Paul Walmsley | 333943b | 2008-08-19 11:08:45 +0300 | [diff] [blame] | 2431 | .clkdm_name = "per_clkdm", |
Paul Walmsley | b045d08 | 2008-03-18 11:24:28 +0200 | [diff] [blame] | 2432 | .recalc = &omap2_clksel_recalc, |
| 2433 | }; |
| 2434 | |
| 2435 | static struct clk gpt3_fck = { |
| 2436 | .name = "gpt3_fck", |
| 2437 | .init = &omap2_init_clksel_parent, |
| 2438 | .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN), |
| 2439 | .enable_bit = OMAP3430_EN_GPT3_SHIFT, |
| 2440 | .clksel_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_CLKSEL), |
| 2441 | .clksel_mask = OMAP3430_CLKSEL_GPT3_MASK, |
| 2442 | .clksel = omap343x_gpt_clksel, |
| 2443 | .flags = CLOCK_IN_OMAP343X, |
Paul Walmsley | 333943b | 2008-08-19 11:08:45 +0300 | [diff] [blame] | 2444 | .clkdm_name = "per_clkdm", |
Paul Walmsley | b045d08 | 2008-03-18 11:24:28 +0200 | [diff] [blame] | 2445 | .recalc = &omap2_clksel_recalc, |
| 2446 | }; |
| 2447 | |
| 2448 | static struct clk gpt4_fck = { |
| 2449 | .name = "gpt4_fck", |
| 2450 | .init = &omap2_init_clksel_parent, |
| 2451 | .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN), |
| 2452 | .enable_bit = OMAP3430_EN_GPT4_SHIFT, |
| 2453 | .clksel_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_CLKSEL), |
| 2454 | .clksel_mask = OMAP3430_CLKSEL_GPT4_MASK, |
| 2455 | .clksel = omap343x_gpt_clksel, |
| 2456 | .flags = CLOCK_IN_OMAP343X, |
Paul Walmsley | 333943b | 2008-08-19 11:08:45 +0300 | [diff] [blame] | 2457 | .clkdm_name = "per_clkdm", |
Paul Walmsley | b045d08 | 2008-03-18 11:24:28 +0200 | [diff] [blame] | 2458 | .recalc = &omap2_clksel_recalc, |
| 2459 | }; |
| 2460 | |
| 2461 | static struct clk gpt5_fck = { |
| 2462 | .name = "gpt5_fck", |
| 2463 | .init = &omap2_init_clksel_parent, |
| 2464 | .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN), |
| 2465 | .enable_bit = OMAP3430_EN_GPT5_SHIFT, |
| 2466 | .clksel_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_CLKSEL), |
| 2467 | .clksel_mask = OMAP3430_CLKSEL_GPT5_MASK, |
| 2468 | .clksel = omap343x_gpt_clksel, |
| 2469 | .flags = CLOCK_IN_OMAP343X, |
Paul Walmsley | 333943b | 2008-08-19 11:08:45 +0300 | [diff] [blame] | 2470 | .clkdm_name = "per_clkdm", |
Paul Walmsley | b045d08 | 2008-03-18 11:24:28 +0200 | [diff] [blame] | 2471 | .recalc = &omap2_clksel_recalc, |
| 2472 | }; |
| 2473 | |
| 2474 | static struct clk gpt6_fck = { |
| 2475 | .name = "gpt6_fck", |
| 2476 | .init = &omap2_init_clksel_parent, |
| 2477 | .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN), |
| 2478 | .enable_bit = OMAP3430_EN_GPT6_SHIFT, |
| 2479 | .clksel_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_CLKSEL), |
| 2480 | .clksel_mask = OMAP3430_CLKSEL_GPT6_MASK, |
| 2481 | .clksel = omap343x_gpt_clksel, |
| 2482 | .flags = CLOCK_IN_OMAP343X, |
Paul Walmsley | 333943b | 2008-08-19 11:08:45 +0300 | [diff] [blame] | 2483 | .clkdm_name = "per_clkdm", |
Paul Walmsley | b045d08 | 2008-03-18 11:24:28 +0200 | [diff] [blame] | 2484 | .recalc = &omap2_clksel_recalc, |
| 2485 | }; |
| 2486 | |
| 2487 | static struct clk gpt7_fck = { |
| 2488 | .name = "gpt7_fck", |
| 2489 | .init = &omap2_init_clksel_parent, |
| 2490 | .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN), |
| 2491 | .enable_bit = OMAP3430_EN_GPT7_SHIFT, |
| 2492 | .clksel_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_CLKSEL), |
| 2493 | .clksel_mask = OMAP3430_CLKSEL_GPT7_MASK, |
| 2494 | .clksel = omap343x_gpt_clksel, |
| 2495 | .flags = CLOCK_IN_OMAP343X, |
Paul Walmsley | 333943b | 2008-08-19 11:08:45 +0300 | [diff] [blame] | 2496 | .clkdm_name = "per_clkdm", |
Paul Walmsley | b045d08 | 2008-03-18 11:24:28 +0200 | [diff] [blame] | 2497 | .recalc = &omap2_clksel_recalc, |
| 2498 | }; |
| 2499 | |
| 2500 | static struct clk gpt8_fck = { |
| 2501 | .name = "gpt8_fck", |
| 2502 | .init = &omap2_init_clksel_parent, |
| 2503 | .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN), |
| 2504 | .enable_bit = OMAP3430_EN_GPT8_SHIFT, |
| 2505 | .clksel_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_CLKSEL), |
| 2506 | .clksel_mask = OMAP3430_CLKSEL_GPT8_MASK, |
| 2507 | .clksel = omap343x_gpt_clksel, |
| 2508 | .flags = CLOCK_IN_OMAP343X, |
Paul Walmsley | 333943b | 2008-08-19 11:08:45 +0300 | [diff] [blame] | 2509 | .clkdm_name = "per_clkdm", |
Paul Walmsley | b045d08 | 2008-03-18 11:24:28 +0200 | [diff] [blame] | 2510 | .recalc = &omap2_clksel_recalc, |
| 2511 | }; |
| 2512 | |
| 2513 | static struct clk gpt9_fck = { |
| 2514 | .name = "gpt9_fck", |
| 2515 | .init = &omap2_init_clksel_parent, |
| 2516 | .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN), |
| 2517 | .enable_bit = OMAP3430_EN_GPT9_SHIFT, |
| 2518 | .clksel_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_CLKSEL), |
| 2519 | .clksel_mask = OMAP3430_CLKSEL_GPT9_MASK, |
| 2520 | .clksel = omap343x_gpt_clksel, |
| 2521 | .flags = CLOCK_IN_OMAP343X, |
Paul Walmsley | 333943b | 2008-08-19 11:08:45 +0300 | [diff] [blame] | 2522 | .clkdm_name = "per_clkdm", |
Paul Walmsley | b045d08 | 2008-03-18 11:24:28 +0200 | [diff] [blame] | 2523 | .recalc = &omap2_clksel_recalc, |
| 2524 | }; |
| 2525 | |
| 2526 | static struct clk per_32k_alwon_fck = { |
| 2527 | .name = "per_32k_alwon_fck", |
Russell King | 897dcde | 2008-11-04 16:35:03 +0000 | [diff] [blame] | 2528 | .ops = &clkops_null, |
Paul Walmsley | b045d08 | 2008-03-18 11:24:28 +0200 | [diff] [blame] | 2529 | .parent = &omap_32k_fck, |
Paul Walmsley | 333943b | 2008-08-19 11:08:45 +0300 | [diff] [blame] | 2530 | .clkdm_name = "per_clkdm", |
Russell King | 897dcde | 2008-11-04 16:35:03 +0000 | [diff] [blame] | 2531 | .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES, |
Paul Walmsley | b045d08 | 2008-03-18 11:24:28 +0200 | [diff] [blame] | 2532 | .recalc = &followparent_recalc, |
| 2533 | }; |
| 2534 | |
Jouni Hogander | 89db948 | 2008-12-10 17:35:24 -0800 | [diff] [blame] | 2535 | static struct clk gpio6_dbck = { |
| 2536 | .name = "gpio6_dbck", |
Paul Walmsley | b045d08 | 2008-03-18 11:24:28 +0200 | [diff] [blame] | 2537 | .parent = &per_32k_alwon_fck, |
| 2538 | .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN), |
Jouni Högander | c3aa044a | 2008-03-28 14:57:50 +0200 | [diff] [blame] | 2539 | .enable_bit = OMAP3430_EN_GPIO6_SHIFT, |
Paul Walmsley | b045d08 | 2008-03-18 11:24:28 +0200 | [diff] [blame] | 2540 | .flags = CLOCK_IN_OMAP343X, |
Paul Walmsley | 333943b | 2008-08-19 11:08:45 +0300 | [diff] [blame] | 2541 | .clkdm_name = "per_clkdm", |
Paul Walmsley | b045d08 | 2008-03-18 11:24:28 +0200 | [diff] [blame] | 2542 | .recalc = &followparent_recalc, |
| 2543 | }; |
| 2544 | |
Jouni Hogander | 89db948 | 2008-12-10 17:35:24 -0800 | [diff] [blame] | 2545 | static struct clk gpio5_dbck = { |
| 2546 | .name = "gpio5_dbck", |
Paul Walmsley | b045d08 | 2008-03-18 11:24:28 +0200 | [diff] [blame] | 2547 | .parent = &per_32k_alwon_fck, |
| 2548 | .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN), |
Jouni Högander | c3aa044a | 2008-03-28 14:57:50 +0200 | [diff] [blame] | 2549 | .enable_bit = OMAP3430_EN_GPIO5_SHIFT, |
Paul Walmsley | b045d08 | 2008-03-18 11:24:28 +0200 | [diff] [blame] | 2550 | .flags = CLOCK_IN_OMAP343X, |
Paul Walmsley | 333943b | 2008-08-19 11:08:45 +0300 | [diff] [blame] | 2551 | .clkdm_name = "per_clkdm", |
Paul Walmsley | b045d08 | 2008-03-18 11:24:28 +0200 | [diff] [blame] | 2552 | .recalc = &followparent_recalc, |
| 2553 | }; |
| 2554 | |
Jouni Hogander | 89db948 | 2008-12-10 17:35:24 -0800 | [diff] [blame] | 2555 | static struct clk gpio4_dbck = { |
| 2556 | .name = "gpio4_dbck", |
Paul Walmsley | b045d08 | 2008-03-18 11:24:28 +0200 | [diff] [blame] | 2557 | .parent = &per_32k_alwon_fck, |
| 2558 | .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN), |
Jouni Högander | c3aa044a | 2008-03-28 14:57:50 +0200 | [diff] [blame] | 2559 | .enable_bit = OMAP3430_EN_GPIO4_SHIFT, |
Paul Walmsley | b045d08 | 2008-03-18 11:24:28 +0200 | [diff] [blame] | 2560 | .flags = CLOCK_IN_OMAP343X, |
Paul Walmsley | 333943b | 2008-08-19 11:08:45 +0300 | [diff] [blame] | 2561 | .clkdm_name = "per_clkdm", |
Paul Walmsley | b045d08 | 2008-03-18 11:24:28 +0200 | [diff] [blame] | 2562 | .recalc = &followparent_recalc, |
| 2563 | }; |
| 2564 | |
Jouni Hogander | 89db948 | 2008-12-10 17:35:24 -0800 | [diff] [blame] | 2565 | static struct clk gpio3_dbck = { |
| 2566 | .name = "gpio3_dbck", |
Paul Walmsley | b045d08 | 2008-03-18 11:24:28 +0200 | [diff] [blame] | 2567 | .parent = &per_32k_alwon_fck, |
| 2568 | .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN), |
Jouni Högander | c3aa044a | 2008-03-28 14:57:50 +0200 | [diff] [blame] | 2569 | .enable_bit = OMAP3430_EN_GPIO3_SHIFT, |
Paul Walmsley | b045d08 | 2008-03-18 11:24:28 +0200 | [diff] [blame] | 2570 | .flags = CLOCK_IN_OMAP343X, |
Paul Walmsley | 333943b | 2008-08-19 11:08:45 +0300 | [diff] [blame] | 2571 | .clkdm_name = "per_clkdm", |
Paul Walmsley | b045d08 | 2008-03-18 11:24:28 +0200 | [diff] [blame] | 2572 | .recalc = &followparent_recalc, |
| 2573 | }; |
| 2574 | |
Jouni Hogander | 89db948 | 2008-12-10 17:35:24 -0800 | [diff] [blame] | 2575 | static struct clk gpio2_dbck = { |
| 2576 | .name = "gpio2_dbck", |
Paul Walmsley | b045d08 | 2008-03-18 11:24:28 +0200 | [diff] [blame] | 2577 | .parent = &per_32k_alwon_fck, |
| 2578 | .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN), |
Jouni Högander | c3aa044a | 2008-03-28 14:57:50 +0200 | [diff] [blame] | 2579 | .enable_bit = OMAP3430_EN_GPIO2_SHIFT, |
Paul Walmsley | b045d08 | 2008-03-18 11:24:28 +0200 | [diff] [blame] | 2580 | .flags = CLOCK_IN_OMAP343X, |
Paul Walmsley | 333943b | 2008-08-19 11:08:45 +0300 | [diff] [blame] | 2581 | .clkdm_name = "per_clkdm", |
Paul Walmsley | b045d08 | 2008-03-18 11:24:28 +0200 | [diff] [blame] | 2582 | .recalc = &followparent_recalc, |
| 2583 | }; |
| 2584 | |
| 2585 | static struct clk wdt3_fck = { |
| 2586 | .name = "wdt3_fck", |
| 2587 | .parent = &per_32k_alwon_fck, |
| 2588 | .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN), |
| 2589 | .enable_bit = OMAP3430_EN_WDT3_SHIFT, |
| 2590 | .flags = CLOCK_IN_OMAP343X, |
Paul Walmsley | 333943b | 2008-08-19 11:08:45 +0300 | [diff] [blame] | 2591 | .clkdm_name = "per_clkdm", |
Paul Walmsley | b045d08 | 2008-03-18 11:24:28 +0200 | [diff] [blame] | 2592 | .recalc = &followparent_recalc, |
| 2593 | }; |
| 2594 | |
| 2595 | static struct clk per_l4_ick = { |
| 2596 | .name = "per_l4_ick", |
Russell King | 5713718 | 2008-11-04 16:48:35 +0000 | [diff] [blame^] | 2597 | .ops = &clkops_null, |
Paul Walmsley | b045d08 | 2008-03-18 11:24:28 +0200 | [diff] [blame] | 2598 | .parent = &l4_ick, |
Russell King | 5713718 | 2008-11-04 16:48:35 +0000 | [diff] [blame^] | 2599 | .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES, |
Paul Walmsley | 333943b | 2008-08-19 11:08:45 +0300 | [diff] [blame] | 2600 | .clkdm_name = "per_clkdm", |
Paul Walmsley | b045d08 | 2008-03-18 11:24:28 +0200 | [diff] [blame] | 2601 | .recalc = &followparent_recalc, |
| 2602 | }; |
| 2603 | |
| 2604 | static struct clk gpio6_ick = { |
| 2605 | .name = "gpio6_ick", |
| 2606 | .parent = &per_l4_ick, |
| 2607 | .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN), |
| 2608 | .enable_bit = OMAP3430_EN_GPIO6_SHIFT, |
| 2609 | .flags = CLOCK_IN_OMAP343X, |
Paul Walmsley | 333943b | 2008-08-19 11:08:45 +0300 | [diff] [blame] | 2610 | .clkdm_name = "per_clkdm", |
Paul Walmsley | b045d08 | 2008-03-18 11:24:28 +0200 | [diff] [blame] | 2611 | .recalc = &followparent_recalc, |
| 2612 | }; |
| 2613 | |
| 2614 | static struct clk gpio5_ick = { |
| 2615 | .name = "gpio5_ick", |
| 2616 | .parent = &per_l4_ick, |
| 2617 | .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN), |
| 2618 | .enable_bit = OMAP3430_EN_GPIO5_SHIFT, |
| 2619 | .flags = CLOCK_IN_OMAP343X, |
Paul Walmsley | 333943b | 2008-08-19 11:08:45 +0300 | [diff] [blame] | 2620 | .clkdm_name = "per_clkdm", |
Paul Walmsley | b045d08 | 2008-03-18 11:24:28 +0200 | [diff] [blame] | 2621 | .recalc = &followparent_recalc, |
| 2622 | }; |
| 2623 | |
| 2624 | static struct clk gpio4_ick = { |
| 2625 | .name = "gpio4_ick", |
| 2626 | .parent = &per_l4_ick, |
| 2627 | .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN), |
| 2628 | .enable_bit = OMAP3430_EN_GPIO4_SHIFT, |
| 2629 | .flags = CLOCK_IN_OMAP343X, |
Paul Walmsley | 333943b | 2008-08-19 11:08:45 +0300 | [diff] [blame] | 2630 | .clkdm_name = "per_clkdm", |
Paul Walmsley | b045d08 | 2008-03-18 11:24:28 +0200 | [diff] [blame] | 2631 | .recalc = &followparent_recalc, |
| 2632 | }; |
| 2633 | |
| 2634 | static struct clk gpio3_ick = { |
| 2635 | .name = "gpio3_ick", |
| 2636 | .parent = &per_l4_ick, |
| 2637 | .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN), |
| 2638 | .enable_bit = OMAP3430_EN_GPIO3_SHIFT, |
| 2639 | .flags = CLOCK_IN_OMAP343X, |
Paul Walmsley | 333943b | 2008-08-19 11:08:45 +0300 | [diff] [blame] | 2640 | .clkdm_name = "per_clkdm", |
Paul Walmsley | b045d08 | 2008-03-18 11:24:28 +0200 | [diff] [blame] | 2641 | .recalc = &followparent_recalc, |
| 2642 | }; |
| 2643 | |
| 2644 | static struct clk gpio2_ick = { |
| 2645 | .name = "gpio2_ick", |
| 2646 | .parent = &per_l4_ick, |
| 2647 | .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN), |
| 2648 | .enable_bit = OMAP3430_EN_GPIO2_SHIFT, |
| 2649 | .flags = CLOCK_IN_OMAP343X, |
Paul Walmsley | 333943b | 2008-08-19 11:08:45 +0300 | [diff] [blame] | 2650 | .clkdm_name = "per_clkdm", |
Paul Walmsley | b045d08 | 2008-03-18 11:24:28 +0200 | [diff] [blame] | 2651 | .recalc = &followparent_recalc, |
| 2652 | }; |
| 2653 | |
| 2654 | static struct clk wdt3_ick = { |
| 2655 | .name = "wdt3_ick", |
| 2656 | .parent = &per_l4_ick, |
| 2657 | .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN), |
| 2658 | .enable_bit = OMAP3430_EN_WDT3_SHIFT, |
| 2659 | .flags = CLOCK_IN_OMAP343X, |
Paul Walmsley | 333943b | 2008-08-19 11:08:45 +0300 | [diff] [blame] | 2660 | .clkdm_name = "per_clkdm", |
Paul Walmsley | b045d08 | 2008-03-18 11:24:28 +0200 | [diff] [blame] | 2661 | .recalc = &followparent_recalc, |
| 2662 | }; |
| 2663 | |
| 2664 | static struct clk uart3_ick = { |
| 2665 | .name = "uart3_ick", |
| 2666 | .parent = &per_l4_ick, |
| 2667 | .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN), |
| 2668 | .enable_bit = OMAP3430_EN_UART3_SHIFT, |
| 2669 | .flags = CLOCK_IN_OMAP343X, |
Paul Walmsley | 333943b | 2008-08-19 11:08:45 +0300 | [diff] [blame] | 2670 | .clkdm_name = "per_clkdm", |
Paul Walmsley | b045d08 | 2008-03-18 11:24:28 +0200 | [diff] [blame] | 2671 | .recalc = &followparent_recalc, |
| 2672 | }; |
| 2673 | |
| 2674 | static struct clk gpt9_ick = { |
| 2675 | .name = "gpt9_ick", |
| 2676 | .parent = &per_l4_ick, |
| 2677 | .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN), |
| 2678 | .enable_bit = OMAP3430_EN_GPT9_SHIFT, |
| 2679 | .flags = CLOCK_IN_OMAP343X, |
Paul Walmsley | 333943b | 2008-08-19 11:08:45 +0300 | [diff] [blame] | 2680 | .clkdm_name = "per_clkdm", |
Paul Walmsley | b045d08 | 2008-03-18 11:24:28 +0200 | [diff] [blame] | 2681 | .recalc = &followparent_recalc, |
| 2682 | }; |
| 2683 | |
| 2684 | static struct clk gpt8_ick = { |
| 2685 | .name = "gpt8_ick", |
| 2686 | .parent = &per_l4_ick, |
| 2687 | .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN), |
| 2688 | .enable_bit = OMAP3430_EN_GPT8_SHIFT, |
| 2689 | .flags = CLOCK_IN_OMAP343X, |
Paul Walmsley | 333943b | 2008-08-19 11:08:45 +0300 | [diff] [blame] | 2690 | .clkdm_name = "per_clkdm", |
Paul Walmsley | b045d08 | 2008-03-18 11:24:28 +0200 | [diff] [blame] | 2691 | .recalc = &followparent_recalc, |
| 2692 | }; |
| 2693 | |
| 2694 | static struct clk gpt7_ick = { |
| 2695 | .name = "gpt7_ick", |
| 2696 | .parent = &per_l4_ick, |
| 2697 | .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN), |
| 2698 | .enable_bit = OMAP3430_EN_GPT7_SHIFT, |
| 2699 | .flags = CLOCK_IN_OMAP343X, |
Paul Walmsley | 333943b | 2008-08-19 11:08:45 +0300 | [diff] [blame] | 2700 | .clkdm_name = "per_clkdm", |
Paul Walmsley | b045d08 | 2008-03-18 11:24:28 +0200 | [diff] [blame] | 2701 | .recalc = &followparent_recalc, |
| 2702 | }; |
| 2703 | |
| 2704 | static struct clk gpt6_ick = { |
| 2705 | .name = "gpt6_ick", |
| 2706 | .parent = &per_l4_ick, |
| 2707 | .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN), |
| 2708 | .enable_bit = OMAP3430_EN_GPT6_SHIFT, |
| 2709 | .flags = CLOCK_IN_OMAP343X, |
Paul Walmsley | 333943b | 2008-08-19 11:08:45 +0300 | [diff] [blame] | 2710 | .clkdm_name = "per_clkdm", |
Paul Walmsley | b045d08 | 2008-03-18 11:24:28 +0200 | [diff] [blame] | 2711 | .recalc = &followparent_recalc, |
| 2712 | }; |
| 2713 | |
| 2714 | static struct clk gpt5_ick = { |
| 2715 | .name = "gpt5_ick", |
| 2716 | .parent = &per_l4_ick, |
| 2717 | .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN), |
| 2718 | .enable_bit = OMAP3430_EN_GPT5_SHIFT, |
| 2719 | .flags = CLOCK_IN_OMAP343X, |
Paul Walmsley | 333943b | 2008-08-19 11:08:45 +0300 | [diff] [blame] | 2720 | .clkdm_name = "per_clkdm", |
Paul Walmsley | b045d08 | 2008-03-18 11:24:28 +0200 | [diff] [blame] | 2721 | .recalc = &followparent_recalc, |
| 2722 | }; |
| 2723 | |
| 2724 | static struct clk gpt4_ick = { |
| 2725 | .name = "gpt4_ick", |
| 2726 | .parent = &per_l4_ick, |
| 2727 | .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN), |
| 2728 | .enable_bit = OMAP3430_EN_GPT4_SHIFT, |
| 2729 | .flags = CLOCK_IN_OMAP343X, |
Paul Walmsley | 333943b | 2008-08-19 11:08:45 +0300 | [diff] [blame] | 2730 | .clkdm_name = "per_clkdm", |
Paul Walmsley | b045d08 | 2008-03-18 11:24:28 +0200 | [diff] [blame] | 2731 | .recalc = &followparent_recalc, |
| 2732 | }; |
| 2733 | |
| 2734 | static struct clk gpt3_ick = { |
| 2735 | .name = "gpt3_ick", |
| 2736 | .parent = &per_l4_ick, |
| 2737 | .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN), |
| 2738 | .enable_bit = OMAP3430_EN_GPT3_SHIFT, |
| 2739 | .flags = CLOCK_IN_OMAP343X, |
Paul Walmsley | 333943b | 2008-08-19 11:08:45 +0300 | [diff] [blame] | 2740 | .clkdm_name = "per_clkdm", |
Paul Walmsley | b045d08 | 2008-03-18 11:24:28 +0200 | [diff] [blame] | 2741 | .recalc = &followparent_recalc, |
| 2742 | }; |
| 2743 | |
| 2744 | static struct clk gpt2_ick = { |
| 2745 | .name = "gpt2_ick", |
| 2746 | .parent = &per_l4_ick, |
| 2747 | .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN), |
| 2748 | .enable_bit = OMAP3430_EN_GPT2_SHIFT, |
| 2749 | .flags = CLOCK_IN_OMAP343X, |
Paul Walmsley | 333943b | 2008-08-19 11:08:45 +0300 | [diff] [blame] | 2750 | .clkdm_name = "per_clkdm", |
Paul Walmsley | b045d08 | 2008-03-18 11:24:28 +0200 | [diff] [blame] | 2751 | .recalc = &followparent_recalc, |
| 2752 | }; |
| 2753 | |
| 2754 | static struct clk mcbsp2_ick = { |
Eduardo Valentin | 78673bc | 2008-07-03 12:24:40 +0300 | [diff] [blame] | 2755 | .name = "mcbsp_ick", |
| 2756 | .id = 2, |
Paul Walmsley | b045d08 | 2008-03-18 11:24:28 +0200 | [diff] [blame] | 2757 | .parent = &per_l4_ick, |
| 2758 | .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN), |
| 2759 | .enable_bit = OMAP3430_EN_MCBSP2_SHIFT, |
| 2760 | .flags = CLOCK_IN_OMAP343X, |
Paul Walmsley | 333943b | 2008-08-19 11:08:45 +0300 | [diff] [blame] | 2761 | .clkdm_name = "per_clkdm", |
Paul Walmsley | b045d08 | 2008-03-18 11:24:28 +0200 | [diff] [blame] | 2762 | .recalc = &followparent_recalc, |
| 2763 | }; |
| 2764 | |
| 2765 | static struct clk mcbsp3_ick = { |
Eduardo Valentin | 78673bc | 2008-07-03 12:24:40 +0300 | [diff] [blame] | 2766 | .name = "mcbsp_ick", |
| 2767 | .id = 3, |
Paul Walmsley | b045d08 | 2008-03-18 11:24:28 +0200 | [diff] [blame] | 2768 | .parent = &per_l4_ick, |
| 2769 | .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN), |
| 2770 | .enable_bit = OMAP3430_EN_MCBSP3_SHIFT, |
| 2771 | .flags = CLOCK_IN_OMAP343X, |
Paul Walmsley | 333943b | 2008-08-19 11:08:45 +0300 | [diff] [blame] | 2772 | .clkdm_name = "per_clkdm", |
Paul Walmsley | b045d08 | 2008-03-18 11:24:28 +0200 | [diff] [blame] | 2773 | .recalc = &followparent_recalc, |
| 2774 | }; |
| 2775 | |
| 2776 | static struct clk mcbsp4_ick = { |
Eduardo Valentin | 78673bc | 2008-07-03 12:24:40 +0300 | [diff] [blame] | 2777 | .name = "mcbsp_ick", |
| 2778 | .id = 4, |
Paul Walmsley | b045d08 | 2008-03-18 11:24:28 +0200 | [diff] [blame] | 2779 | .parent = &per_l4_ick, |
| 2780 | .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN), |
| 2781 | .enable_bit = OMAP3430_EN_MCBSP4_SHIFT, |
| 2782 | .flags = CLOCK_IN_OMAP343X, |
Paul Walmsley | 333943b | 2008-08-19 11:08:45 +0300 | [diff] [blame] | 2783 | .clkdm_name = "per_clkdm", |
Paul Walmsley | b045d08 | 2008-03-18 11:24:28 +0200 | [diff] [blame] | 2784 | .recalc = &followparent_recalc, |
| 2785 | }; |
| 2786 | |
| 2787 | static const struct clksel mcbsp_234_clksel[] = { |
| 2788 | { .parent = &per_96m_fck, .rates = common_mcbsp_96m_rates }, |
Paul Walmsley | 333943b | 2008-08-19 11:08:45 +0300 | [diff] [blame] | 2789 | { .parent = &mcbsp_clks, .rates = common_mcbsp_mcbsp_rates }, |
Paul Walmsley | b045d08 | 2008-03-18 11:24:28 +0200 | [diff] [blame] | 2790 | { .parent = NULL } |
| 2791 | }; |
| 2792 | |
| 2793 | static struct clk mcbsp2_fck = { |
Eduardo Valentin | 78673bc | 2008-07-03 12:24:40 +0300 | [diff] [blame] | 2794 | .name = "mcbsp_fck", |
| 2795 | .id = 2, |
Paul Walmsley | b045d08 | 2008-03-18 11:24:28 +0200 | [diff] [blame] | 2796 | .init = &omap2_init_clksel_parent, |
| 2797 | .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN), |
| 2798 | .enable_bit = OMAP3430_EN_MCBSP2_SHIFT, |
| 2799 | .clksel_reg = OMAP343X_CTRL_REGADDR(OMAP2_CONTROL_DEVCONF0), |
| 2800 | .clksel_mask = OMAP2_MCBSP2_CLKS_MASK, |
| 2801 | .clksel = mcbsp_234_clksel, |
| 2802 | .flags = CLOCK_IN_OMAP343X, |
Paul Walmsley | 333943b | 2008-08-19 11:08:45 +0300 | [diff] [blame] | 2803 | .clkdm_name = "per_clkdm", |
Paul Walmsley | b045d08 | 2008-03-18 11:24:28 +0200 | [diff] [blame] | 2804 | .recalc = &omap2_clksel_recalc, |
| 2805 | }; |
| 2806 | |
| 2807 | static struct clk mcbsp3_fck = { |
Eduardo Valentin | 78673bc | 2008-07-03 12:24:40 +0300 | [diff] [blame] | 2808 | .name = "mcbsp_fck", |
| 2809 | .id = 3, |
Paul Walmsley | b045d08 | 2008-03-18 11:24:28 +0200 | [diff] [blame] | 2810 | .init = &omap2_init_clksel_parent, |
| 2811 | .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN), |
| 2812 | .enable_bit = OMAP3430_EN_MCBSP3_SHIFT, |
| 2813 | .clksel_reg = OMAP343X_CTRL_REGADDR(OMAP343X_CONTROL_DEVCONF1), |
| 2814 | .clksel_mask = OMAP2_MCBSP3_CLKS_MASK, |
| 2815 | .clksel = mcbsp_234_clksel, |
| 2816 | .flags = CLOCK_IN_OMAP343X, |
Paul Walmsley | 333943b | 2008-08-19 11:08:45 +0300 | [diff] [blame] | 2817 | .clkdm_name = "per_clkdm", |
Paul Walmsley | b045d08 | 2008-03-18 11:24:28 +0200 | [diff] [blame] | 2818 | .recalc = &omap2_clksel_recalc, |
| 2819 | }; |
| 2820 | |
| 2821 | static struct clk mcbsp4_fck = { |
Eduardo Valentin | 78673bc | 2008-07-03 12:24:40 +0300 | [diff] [blame] | 2822 | .name = "mcbsp_fck", |
| 2823 | .id = 4, |
Paul Walmsley | b045d08 | 2008-03-18 11:24:28 +0200 | [diff] [blame] | 2824 | .init = &omap2_init_clksel_parent, |
| 2825 | .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN), |
| 2826 | .enable_bit = OMAP3430_EN_MCBSP4_SHIFT, |
| 2827 | .clksel_reg = OMAP343X_CTRL_REGADDR(OMAP343X_CONTROL_DEVCONF1), |
| 2828 | .clksel_mask = OMAP2_MCBSP4_CLKS_MASK, |
| 2829 | .clksel = mcbsp_234_clksel, |
| 2830 | .flags = CLOCK_IN_OMAP343X, |
Paul Walmsley | 333943b | 2008-08-19 11:08:45 +0300 | [diff] [blame] | 2831 | .clkdm_name = "per_clkdm", |
Paul Walmsley | b045d08 | 2008-03-18 11:24:28 +0200 | [diff] [blame] | 2832 | .recalc = &omap2_clksel_recalc, |
| 2833 | }; |
| 2834 | |
| 2835 | /* EMU clocks */ |
| 2836 | |
| 2837 | /* More information: ARM Cortex-A8 Technical Reference Manual, sect 10.1 */ |
| 2838 | |
| 2839 | static const struct clksel_rate emu_src_sys_rates[] = { |
| 2840 | { .div = 1, .val = 0, .flags = RATE_IN_343X | DEFAULT_RATE }, |
| 2841 | { .div = 0 }, |
| 2842 | }; |
| 2843 | |
| 2844 | static const struct clksel_rate emu_src_core_rates[] = { |
| 2845 | { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE }, |
| 2846 | { .div = 0 }, |
| 2847 | }; |
| 2848 | |
| 2849 | static const struct clksel_rate emu_src_per_rates[] = { |
| 2850 | { .div = 1, .val = 2, .flags = RATE_IN_343X | DEFAULT_RATE }, |
| 2851 | { .div = 0 }, |
| 2852 | }; |
| 2853 | |
| 2854 | static const struct clksel_rate emu_src_mpu_rates[] = { |
| 2855 | { .div = 1, .val = 3, .flags = RATE_IN_343X | DEFAULT_RATE }, |
| 2856 | { .div = 0 }, |
| 2857 | }; |
| 2858 | |
| 2859 | static const struct clksel emu_src_clksel[] = { |
| 2860 | { .parent = &sys_ck, .rates = emu_src_sys_rates }, |
| 2861 | { .parent = &emu_core_alwon_ck, .rates = emu_src_core_rates }, |
| 2862 | { .parent = &emu_per_alwon_ck, .rates = emu_src_per_rates }, |
| 2863 | { .parent = &emu_mpu_alwon_ck, .rates = emu_src_mpu_rates }, |
| 2864 | { .parent = NULL }, |
| 2865 | }; |
| 2866 | |
| 2867 | /* |
| 2868 | * Like the clkout_src clocks, emu_src_clk is a virtual clock, existing only |
| 2869 | * to switch the source of some of the EMU clocks. |
| 2870 | * XXX Are there CLKEN bits for these EMU clks? |
| 2871 | */ |
| 2872 | static struct clk emu_src_ck = { |
| 2873 | .name = "emu_src_ck", |
Russell King | 897dcde | 2008-11-04 16:35:03 +0000 | [diff] [blame] | 2874 | .ops = &clkops_null, |
Paul Walmsley | b045d08 | 2008-03-18 11:24:28 +0200 | [diff] [blame] | 2875 | .init = &omap2_init_clksel_parent, |
| 2876 | .clksel_reg = OMAP_CM_REGADDR(OMAP3430_EMU_MOD, CM_CLKSEL1), |
| 2877 | .clksel_mask = OMAP3430_MUX_CTRL_MASK, |
| 2878 | .clksel = emu_src_clksel, |
Russell King | 897dcde | 2008-11-04 16:35:03 +0000 | [diff] [blame] | 2879 | .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES, |
Paul Walmsley | 333943b | 2008-08-19 11:08:45 +0300 | [diff] [blame] | 2880 | .clkdm_name = "emu_clkdm", |
Paul Walmsley | b045d08 | 2008-03-18 11:24:28 +0200 | [diff] [blame] | 2881 | .recalc = &omap2_clksel_recalc, |
| 2882 | }; |
| 2883 | |
| 2884 | static const struct clksel_rate pclk_emu_rates[] = { |
| 2885 | { .div = 2, .val = 2, .flags = RATE_IN_343X | DEFAULT_RATE }, |
| 2886 | { .div = 3, .val = 3, .flags = RATE_IN_343X }, |
| 2887 | { .div = 4, .val = 4, .flags = RATE_IN_343X }, |
| 2888 | { .div = 6, .val = 6, .flags = RATE_IN_343X }, |
| 2889 | { .div = 0 }, |
| 2890 | }; |
| 2891 | |
| 2892 | static const struct clksel pclk_emu_clksel[] = { |
| 2893 | { .parent = &emu_src_ck, .rates = pclk_emu_rates }, |
| 2894 | { .parent = NULL }, |
| 2895 | }; |
| 2896 | |
| 2897 | static struct clk pclk_fck = { |
| 2898 | .name = "pclk_fck", |
Russell King | 897dcde | 2008-11-04 16:35:03 +0000 | [diff] [blame] | 2899 | .ops = &clkops_null, |
Paul Walmsley | b045d08 | 2008-03-18 11:24:28 +0200 | [diff] [blame] | 2900 | .init = &omap2_init_clksel_parent, |
| 2901 | .clksel_reg = OMAP_CM_REGADDR(OMAP3430_EMU_MOD, CM_CLKSEL1), |
| 2902 | .clksel_mask = OMAP3430_CLKSEL_PCLK_MASK, |
| 2903 | .clksel = pclk_emu_clksel, |
Russell King | 897dcde | 2008-11-04 16:35:03 +0000 | [diff] [blame] | 2904 | .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES, |
Paul Walmsley | 333943b | 2008-08-19 11:08:45 +0300 | [diff] [blame] | 2905 | .clkdm_name = "emu_clkdm", |
Paul Walmsley | b045d08 | 2008-03-18 11:24:28 +0200 | [diff] [blame] | 2906 | .recalc = &omap2_clksel_recalc, |
| 2907 | }; |
| 2908 | |
| 2909 | static const struct clksel_rate pclkx2_emu_rates[] = { |
| 2910 | { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE }, |
| 2911 | { .div = 2, .val = 2, .flags = RATE_IN_343X }, |
| 2912 | { .div = 3, .val = 3, .flags = RATE_IN_343X }, |
| 2913 | { .div = 0 }, |
| 2914 | }; |
| 2915 | |
| 2916 | static const struct clksel pclkx2_emu_clksel[] = { |
| 2917 | { .parent = &emu_src_ck, .rates = pclkx2_emu_rates }, |
| 2918 | { .parent = NULL }, |
| 2919 | }; |
| 2920 | |
| 2921 | static struct clk pclkx2_fck = { |
| 2922 | .name = "pclkx2_fck", |
Russell King | 897dcde | 2008-11-04 16:35:03 +0000 | [diff] [blame] | 2923 | .ops = &clkops_null, |
Paul Walmsley | b045d08 | 2008-03-18 11:24:28 +0200 | [diff] [blame] | 2924 | .init = &omap2_init_clksel_parent, |
| 2925 | .clksel_reg = OMAP_CM_REGADDR(OMAP3430_EMU_MOD, CM_CLKSEL1), |
| 2926 | .clksel_mask = OMAP3430_CLKSEL_PCLKX2_MASK, |
| 2927 | .clksel = pclkx2_emu_clksel, |
Russell King | 897dcde | 2008-11-04 16:35:03 +0000 | [diff] [blame] | 2928 | .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES, |
Paul Walmsley | 333943b | 2008-08-19 11:08:45 +0300 | [diff] [blame] | 2929 | .clkdm_name = "emu_clkdm", |
Paul Walmsley | b045d08 | 2008-03-18 11:24:28 +0200 | [diff] [blame] | 2930 | .recalc = &omap2_clksel_recalc, |
| 2931 | }; |
| 2932 | |
| 2933 | static const struct clksel atclk_emu_clksel[] = { |
| 2934 | { .parent = &emu_src_ck, .rates = div2_rates }, |
| 2935 | { .parent = NULL }, |
| 2936 | }; |
| 2937 | |
| 2938 | static struct clk atclk_fck = { |
| 2939 | .name = "atclk_fck", |
Russell King | 897dcde | 2008-11-04 16:35:03 +0000 | [diff] [blame] | 2940 | .ops = &clkops_null, |
Paul Walmsley | b045d08 | 2008-03-18 11:24:28 +0200 | [diff] [blame] | 2941 | .init = &omap2_init_clksel_parent, |
| 2942 | .clksel_reg = OMAP_CM_REGADDR(OMAP3430_EMU_MOD, CM_CLKSEL1), |
| 2943 | .clksel_mask = OMAP3430_CLKSEL_ATCLK_MASK, |
| 2944 | .clksel = atclk_emu_clksel, |
Russell King | 897dcde | 2008-11-04 16:35:03 +0000 | [diff] [blame] | 2945 | .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES, |
Paul Walmsley | 333943b | 2008-08-19 11:08:45 +0300 | [diff] [blame] | 2946 | .clkdm_name = "emu_clkdm", |
Paul Walmsley | b045d08 | 2008-03-18 11:24:28 +0200 | [diff] [blame] | 2947 | .recalc = &omap2_clksel_recalc, |
| 2948 | }; |
| 2949 | |
| 2950 | static struct clk traceclk_src_fck = { |
| 2951 | .name = "traceclk_src_fck", |
Russell King | 897dcde | 2008-11-04 16:35:03 +0000 | [diff] [blame] | 2952 | .ops = &clkops_null, |
Paul Walmsley | b045d08 | 2008-03-18 11:24:28 +0200 | [diff] [blame] | 2953 | .init = &omap2_init_clksel_parent, |
| 2954 | .clksel_reg = OMAP_CM_REGADDR(OMAP3430_EMU_MOD, CM_CLKSEL1), |
| 2955 | .clksel_mask = OMAP3430_TRACE_MUX_CTRL_MASK, |
| 2956 | .clksel = emu_src_clksel, |
Russell King | 897dcde | 2008-11-04 16:35:03 +0000 | [diff] [blame] | 2957 | .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES, |
Paul Walmsley | 333943b | 2008-08-19 11:08:45 +0300 | [diff] [blame] | 2958 | .clkdm_name = "emu_clkdm", |
Paul Walmsley | b045d08 | 2008-03-18 11:24:28 +0200 | [diff] [blame] | 2959 | .recalc = &omap2_clksel_recalc, |
| 2960 | }; |
| 2961 | |
| 2962 | static const struct clksel_rate traceclk_rates[] = { |
| 2963 | { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE }, |
| 2964 | { .div = 2, .val = 2, .flags = RATE_IN_343X }, |
| 2965 | { .div = 4, .val = 4, .flags = RATE_IN_343X }, |
| 2966 | { .div = 0 }, |
| 2967 | }; |
| 2968 | |
| 2969 | static const struct clksel traceclk_clksel[] = { |
| 2970 | { .parent = &traceclk_src_fck, .rates = traceclk_rates }, |
| 2971 | { .parent = NULL }, |
| 2972 | }; |
| 2973 | |
| 2974 | static struct clk traceclk_fck = { |
| 2975 | .name = "traceclk_fck", |
Russell King | 897dcde | 2008-11-04 16:35:03 +0000 | [diff] [blame] | 2976 | .ops = &clkops_null, |
Paul Walmsley | b045d08 | 2008-03-18 11:24:28 +0200 | [diff] [blame] | 2977 | .init = &omap2_init_clksel_parent, |
| 2978 | .clksel_reg = OMAP_CM_REGADDR(OMAP3430_EMU_MOD, CM_CLKSEL1), |
| 2979 | .clksel_mask = OMAP3430_CLKSEL_TRACECLK_MASK, |
| 2980 | .clksel = traceclk_clksel, |
Russell King | 897dcde | 2008-11-04 16:35:03 +0000 | [diff] [blame] | 2981 | .flags = CLOCK_IN_OMAP343X, |
Paul Walmsley | 333943b | 2008-08-19 11:08:45 +0300 | [diff] [blame] | 2982 | .clkdm_name = "emu_clkdm", |
Paul Walmsley | b045d08 | 2008-03-18 11:24:28 +0200 | [diff] [blame] | 2983 | .recalc = &omap2_clksel_recalc, |
| 2984 | }; |
| 2985 | |
| 2986 | /* SR clocks */ |
| 2987 | |
| 2988 | /* SmartReflex fclk (VDD1) */ |
| 2989 | static struct clk sr1_fck = { |
| 2990 | .name = "sr1_fck", |
| 2991 | .parent = &sys_ck, |
| 2992 | .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_FCLKEN), |
| 2993 | .enable_bit = OMAP3430_EN_SR1_SHIFT, |
| 2994 | .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES, |
| 2995 | .recalc = &followparent_recalc, |
| 2996 | }; |
| 2997 | |
| 2998 | /* SmartReflex fclk (VDD2) */ |
| 2999 | static struct clk sr2_fck = { |
| 3000 | .name = "sr2_fck", |
| 3001 | .parent = &sys_ck, |
| 3002 | .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_FCLKEN), |
| 3003 | .enable_bit = OMAP3430_EN_SR2_SHIFT, |
| 3004 | .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES, |
| 3005 | .recalc = &followparent_recalc, |
| 3006 | }; |
| 3007 | |
| 3008 | static struct clk sr_l4_ick = { |
| 3009 | .name = "sr_l4_ick", |
Russell King | 897dcde | 2008-11-04 16:35:03 +0000 | [diff] [blame] | 3010 | .ops = &clkops_null, /* RMK: missing? */ |
Paul Walmsley | b045d08 | 2008-03-18 11:24:28 +0200 | [diff] [blame] | 3011 | .parent = &l4_ick, |
| 3012 | .flags = CLOCK_IN_OMAP343X, |
Paul Walmsley | 333943b | 2008-08-19 11:08:45 +0300 | [diff] [blame] | 3013 | .clkdm_name = "core_l4_clkdm", |
Paul Walmsley | b045d08 | 2008-03-18 11:24:28 +0200 | [diff] [blame] | 3014 | .recalc = &followparent_recalc, |
| 3015 | }; |
| 3016 | |
| 3017 | /* SECURE_32K_FCK clocks */ |
| 3018 | |
Paul Walmsley | 333943b | 2008-08-19 11:08:45 +0300 | [diff] [blame] | 3019 | /* XXX This clock no longer exists in 3430 TRM rev F */ |
Paul Walmsley | b045d08 | 2008-03-18 11:24:28 +0200 | [diff] [blame] | 3020 | static struct clk gpt12_fck = { |
| 3021 | .name = "gpt12_fck", |
Russell King | 897dcde | 2008-11-04 16:35:03 +0000 | [diff] [blame] | 3022 | .ops = &clkops_null, |
Paul Walmsley | b045d08 | 2008-03-18 11:24:28 +0200 | [diff] [blame] | 3023 | .parent = &secure_32k_fck, |
Russell King | 897dcde | 2008-11-04 16:35:03 +0000 | [diff] [blame] | 3024 | .flags = CLOCK_IN_OMAP343X, |
Paul Walmsley | b045d08 | 2008-03-18 11:24:28 +0200 | [diff] [blame] | 3025 | .recalc = &followparent_recalc, |
| 3026 | }; |
| 3027 | |
| 3028 | static struct clk wdt1_fck = { |
| 3029 | .name = "wdt1_fck", |
Russell King | 897dcde | 2008-11-04 16:35:03 +0000 | [diff] [blame] | 3030 | .ops = &clkops_null, |
Paul Walmsley | b045d08 | 2008-03-18 11:24:28 +0200 | [diff] [blame] | 3031 | .parent = &secure_32k_fck, |
Russell King | 897dcde | 2008-11-04 16:35:03 +0000 | [diff] [blame] | 3032 | .flags = CLOCK_IN_OMAP343X, |
Paul Walmsley | b045d08 | 2008-03-18 11:24:28 +0200 | [diff] [blame] | 3033 | .recalc = &followparent_recalc, |
| 3034 | }; |
| 3035 | |
Paul Walmsley | b045d08 | 2008-03-18 11:24:28 +0200 | [diff] [blame] | 3036 | static struct clk *onchip_34xx_clks[] __initdata = { |
| 3037 | &omap_32k_fck, |
| 3038 | &virt_12m_ck, |
| 3039 | &virt_13m_ck, |
| 3040 | &virt_16_8m_ck, |
| 3041 | &virt_19_2m_ck, |
| 3042 | &virt_26m_ck, |
| 3043 | &virt_38_4m_ck, |
| 3044 | &osc_sys_ck, |
| 3045 | &sys_ck, |
| 3046 | &sys_altclk, |
| 3047 | &mcbsp_clks, |
| 3048 | &sys_clkout1, |
| 3049 | &dpll1_ck, |
Roman Tereshonkov | 3760d31 | 2008-03-13 21:35:09 +0200 | [diff] [blame] | 3050 | &dpll1_x2_ck, |
| 3051 | &dpll1_x2m2_ck, |
Paul Walmsley | b045d08 | 2008-03-18 11:24:28 +0200 | [diff] [blame] | 3052 | &dpll2_ck, |
Roman Tereshonkov | 3760d31 | 2008-03-13 21:35:09 +0200 | [diff] [blame] | 3053 | &dpll2_m2_ck, |
Paul Walmsley | b045d08 | 2008-03-18 11:24:28 +0200 | [diff] [blame] | 3054 | &dpll3_ck, |
| 3055 | &core_ck, |
| 3056 | &dpll3_x2_ck, |
| 3057 | &dpll3_m2_ck, |
| 3058 | &dpll3_m2x2_ck, |
Roman Tereshonkov | 3760d31 | 2008-03-13 21:35:09 +0200 | [diff] [blame] | 3059 | &dpll3_m3_ck, |
Paul Walmsley | b045d08 | 2008-03-18 11:24:28 +0200 | [diff] [blame] | 3060 | &dpll3_m3x2_ck, |
| 3061 | &emu_core_alwon_ck, |
| 3062 | &dpll4_ck, |
| 3063 | &dpll4_x2_ck, |
| 3064 | &omap_96m_alwon_fck, |
| 3065 | &omap_96m_fck, |
| 3066 | &cm_96m_fck, |
Roman Tereshonkov | 3760d31 | 2008-03-13 21:35:09 +0200 | [diff] [blame] | 3067 | &virt_omap_54m_fck, |
Paul Walmsley | b045d08 | 2008-03-18 11:24:28 +0200 | [diff] [blame] | 3068 | &omap_54m_fck, |
| 3069 | &omap_48m_fck, |
| 3070 | &omap_12m_fck, |
Roman Tereshonkov | 3760d31 | 2008-03-13 21:35:09 +0200 | [diff] [blame] | 3071 | &dpll4_m2_ck, |
Paul Walmsley | b045d08 | 2008-03-18 11:24:28 +0200 | [diff] [blame] | 3072 | &dpll4_m2x2_ck, |
Roman Tereshonkov | 3760d31 | 2008-03-13 21:35:09 +0200 | [diff] [blame] | 3073 | &dpll4_m3_ck, |
Paul Walmsley | b045d08 | 2008-03-18 11:24:28 +0200 | [diff] [blame] | 3074 | &dpll4_m3x2_ck, |
Roman Tereshonkov | 3760d31 | 2008-03-13 21:35:09 +0200 | [diff] [blame] | 3075 | &dpll4_m4_ck, |
Paul Walmsley | b045d08 | 2008-03-18 11:24:28 +0200 | [diff] [blame] | 3076 | &dpll4_m4x2_ck, |
Roman Tereshonkov | 3760d31 | 2008-03-13 21:35:09 +0200 | [diff] [blame] | 3077 | &dpll4_m5_ck, |
Paul Walmsley | b045d08 | 2008-03-18 11:24:28 +0200 | [diff] [blame] | 3078 | &dpll4_m5x2_ck, |
Roman Tereshonkov | 3760d31 | 2008-03-13 21:35:09 +0200 | [diff] [blame] | 3079 | &dpll4_m6_ck, |
Paul Walmsley | b045d08 | 2008-03-18 11:24:28 +0200 | [diff] [blame] | 3080 | &dpll4_m6x2_ck, |
| 3081 | &emu_per_alwon_ck, |
| 3082 | &dpll5_ck, |
| 3083 | &dpll5_m2_ck, |
| 3084 | &omap_120m_fck, |
| 3085 | &clkout2_src_ck, |
| 3086 | &sys_clkout2, |
| 3087 | &corex2_fck, |
| 3088 | &dpll1_fck, |
Roman Tereshonkov | 3760d31 | 2008-03-13 21:35:09 +0200 | [diff] [blame] | 3089 | &mpu_ck, |
| 3090 | &arm_fck, |
| 3091 | &emu_mpu_alwon_ck, |
Paul Walmsley | b045d08 | 2008-03-18 11:24:28 +0200 | [diff] [blame] | 3092 | &dpll2_fck, |
Roman Tereshonkov | 3760d31 | 2008-03-13 21:35:09 +0200 | [diff] [blame] | 3093 | &iva2_ck, |
Paul Walmsley | b045d08 | 2008-03-18 11:24:28 +0200 | [diff] [blame] | 3094 | &l3_ick, |
| 3095 | &l4_ick, |
| 3096 | &rm_ick, |
Högander Jouni | 5955902 | 2008-08-19 11:08:45 +0300 | [diff] [blame] | 3097 | &gfx_l3_ck, |
Paul Walmsley | b045d08 | 2008-03-18 11:24:28 +0200 | [diff] [blame] | 3098 | &gfx_l3_fck, |
| 3099 | &gfx_l3_ick, |
| 3100 | &gfx_cg1_ck, |
| 3101 | &gfx_cg2_ck, |
| 3102 | &sgx_fck, |
| 3103 | &sgx_ick, |
| 3104 | &d2d_26m_fck, |
| 3105 | &gpt10_fck, |
| 3106 | &gpt11_fck, |
| 3107 | &cpefuse_fck, |
| 3108 | &ts_fck, |
| 3109 | &usbtll_fck, |
| 3110 | &core_96m_fck, |
| 3111 | &mmchs3_fck, |
| 3112 | &mmchs2_fck, |
| 3113 | &mspro_fck, |
| 3114 | &mmchs1_fck, |
| 3115 | &i2c3_fck, |
| 3116 | &i2c2_fck, |
| 3117 | &i2c1_fck, |
| 3118 | &mcbsp5_fck, |
| 3119 | &mcbsp1_fck, |
| 3120 | &core_48m_fck, |
| 3121 | &mcspi4_fck, |
| 3122 | &mcspi3_fck, |
| 3123 | &mcspi2_fck, |
| 3124 | &mcspi1_fck, |
| 3125 | &uart2_fck, |
| 3126 | &uart1_fck, |
| 3127 | &fshostusb_fck, |
| 3128 | &core_12m_fck, |
| 3129 | &hdq_fck, |
| 3130 | &ssi_ssr_fck, |
| 3131 | &ssi_sst_fck, |
| 3132 | &core_l3_ick, |
| 3133 | &hsotgusb_ick, |
| 3134 | &sdrc_ick, |
| 3135 | &gpmc_fck, |
| 3136 | &security_l3_ick, |
| 3137 | &pka_ick, |
| 3138 | &core_l4_ick, |
| 3139 | &usbtll_ick, |
| 3140 | &mmchs3_ick, |
| 3141 | &icr_ick, |
| 3142 | &aes2_ick, |
| 3143 | &sha12_ick, |
| 3144 | &des2_ick, |
| 3145 | &mmchs2_ick, |
| 3146 | &mmchs1_ick, |
| 3147 | &mspro_ick, |
| 3148 | &hdq_ick, |
| 3149 | &mcspi4_ick, |
| 3150 | &mcspi3_ick, |
| 3151 | &mcspi2_ick, |
| 3152 | &mcspi1_ick, |
| 3153 | &i2c3_ick, |
| 3154 | &i2c2_ick, |
| 3155 | &i2c1_ick, |
| 3156 | &uart2_ick, |
| 3157 | &uart1_ick, |
| 3158 | &gpt11_ick, |
| 3159 | &gpt10_ick, |
| 3160 | &mcbsp5_ick, |
| 3161 | &mcbsp1_ick, |
| 3162 | &fac_ick, |
| 3163 | &mailboxes_ick, |
| 3164 | &omapctrl_ick, |
| 3165 | &ssi_l4_ick, |
| 3166 | &ssi_ick, |
| 3167 | &usb_l4_ick, |
| 3168 | &security_l4_ick2, |
| 3169 | &aes1_ick, |
| 3170 | &rng_ick, |
| 3171 | &sha11_ick, |
| 3172 | &des1_ick, |
| 3173 | &dss1_alwon_fck, |
| 3174 | &dss_tv_fck, |
| 3175 | &dss_96m_fck, |
| 3176 | &dss2_alwon_fck, |
| 3177 | &dss_ick, |
| 3178 | &cam_mclk, |
Högander Jouni | 5955902 | 2008-08-19 11:08:45 +0300 | [diff] [blame] | 3179 | &cam_ick, |
Paul Walmsley | b045d08 | 2008-03-18 11:24:28 +0200 | [diff] [blame] | 3180 | &usbhost_120m_fck, |
| 3181 | &usbhost_48m_fck, |
Högander Jouni | 5955902 | 2008-08-19 11:08:45 +0300 | [diff] [blame] | 3182 | &usbhost_ick, |
Paul Walmsley | b045d08 | 2008-03-18 11:24:28 +0200 | [diff] [blame] | 3183 | &usbhost_sar_fck, |
| 3184 | &usim_fck, |
| 3185 | &gpt1_fck, |
| 3186 | &wkup_32k_fck, |
Jouni Hogander | 89db948 | 2008-12-10 17:35:24 -0800 | [diff] [blame] | 3187 | &gpio1_dbck, |
Paul Walmsley | b045d08 | 2008-03-18 11:24:28 +0200 | [diff] [blame] | 3188 | &wdt2_fck, |
| 3189 | &wkup_l4_ick, |
| 3190 | &usim_ick, |
| 3191 | &wdt2_ick, |
| 3192 | &wdt1_ick, |
| 3193 | &gpio1_ick, |
| 3194 | &omap_32ksync_ick, |
| 3195 | &gpt12_ick, |
| 3196 | &gpt1_ick, |
| 3197 | &per_96m_fck, |
| 3198 | &per_48m_fck, |
| 3199 | &uart3_fck, |
| 3200 | &gpt2_fck, |
| 3201 | &gpt3_fck, |
| 3202 | &gpt4_fck, |
| 3203 | &gpt5_fck, |
| 3204 | &gpt6_fck, |
| 3205 | &gpt7_fck, |
| 3206 | &gpt8_fck, |
| 3207 | &gpt9_fck, |
| 3208 | &per_32k_alwon_fck, |
Jouni Hogander | 89db948 | 2008-12-10 17:35:24 -0800 | [diff] [blame] | 3209 | &gpio6_dbck, |
| 3210 | &gpio5_dbck, |
| 3211 | &gpio4_dbck, |
| 3212 | &gpio3_dbck, |
| 3213 | &gpio2_dbck, |
Paul Walmsley | b045d08 | 2008-03-18 11:24:28 +0200 | [diff] [blame] | 3214 | &wdt3_fck, |
| 3215 | &per_l4_ick, |
| 3216 | &gpio6_ick, |
| 3217 | &gpio5_ick, |
| 3218 | &gpio4_ick, |
| 3219 | &gpio3_ick, |
| 3220 | &gpio2_ick, |
| 3221 | &wdt3_ick, |
| 3222 | &uart3_ick, |
| 3223 | &gpt9_ick, |
| 3224 | &gpt8_ick, |
| 3225 | &gpt7_ick, |
| 3226 | &gpt6_ick, |
| 3227 | &gpt5_ick, |
| 3228 | &gpt4_ick, |
| 3229 | &gpt3_ick, |
| 3230 | &gpt2_ick, |
| 3231 | &mcbsp2_ick, |
| 3232 | &mcbsp3_ick, |
| 3233 | &mcbsp4_ick, |
| 3234 | &mcbsp2_fck, |
| 3235 | &mcbsp3_fck, |
| 3236 | &mcbsp4_fck, |
| 3237 | &emu_src_ck, |
| 3238 | &pclk_fck, |
| 3239 | &pclkx2_fck, |
| 3240 | &atclk_fck, |
| 3241 | &traceclk_src_fck, |
| 3242 | &traceclk_fck, |
| 3243 | &sr1_fck, |
| 3244 | &sr2_fck, |
| 3245 | &sr_l4_ick, |
| 3246 | &secure_32k_fck, |
| 3247 | &gpt12_fck, |
| 3248 | &wdt1_fck, |
| 3249 | }; |
| 3250 | |
| 3251 | #endif |